drivers/media/dvb-frontends/cxd2820r_t.c

   1 /*
   2  * Sony CXD2820R demodulator driver
   3  *
   4  * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
   5  *
   6  *    This program is free software; you can redistribute it and/or modify
   7  *    it under the terms of the GNU General Public License as published by
   8  *    the Free Software Foundation; either version 2 of the License, or
   9  *    (at your option) any later version.
  10  *
  11  *    This program is distributed in the hope that it will be useful,
  12  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *    GNU General Public License for more details.
  15  *
  16  *    You should have received a copy of the GNU General Public License along
  17  *    with this program; if not, write to the Free Software Foundation, Inc.,
  18  *    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21
  22 #include "cxd2820r_priv.h"
  23
  24 int cxd2820r_set_frontend_t(struct dvb_frontend *fe)
  25 {
  26         struct cxd2820r_priv *priv = fe->demodulator_priv;
  27         struct i2c_client *client = priv->client[0];
  28         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  29         int ret, i, bw_i;
  30         unsigned int utmp;
  31         u32 if_frequency;
  32         u8 buf[3], bw_param;
  33         u8 bw_params1[][5] = {
  34                 { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
  35                 { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
  36                 { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
  37         };
  38         u8 bw_params2[][2] = {
  39                 { 0x1f, 0xdc }, /* 6 MHz */
  40                 { 0x12, 0xf8 }, /* 7 MHz */
  41                 { 0x01, 0xe0 }, /* 8 MHz */
  42         };
  43         struct reg_val_mask tab[] = {
  44                 { 0x00080, 0x00, 0xff },
  45                 { 0x00081, 0x03, 0xff },
  46                 { 0x00085, 0x07, 0xff },
  47                 { 0x00088, 0x01, 0xff },
  48
  49                 { 0x00070, priv->ts_mode, 0xff },
  50                 { 0x00071, !priv->ts_clk_inv << 4, 0x10 },
  51                 { 0x000cb, priv->if_agc_polarity << 6, 0x40 },
  52                 { 0x000a5, 0x00, 0x01 },
  53                 { 0x00082, 0x20, 0x60 },
  54                 { 0x000c2, 0xc3, 0xff },
  55                 { 0x0016a, 0x50, 0xff },
  56                 { 0x00427, 0x41, 0xff },
  57         };
  58
  59         dev_dbg(&client->dev,
  60                 "delivery_system=%d modulation=%d frequency=%u bandwidth_hz=%u inversion=%d\n",
  61                 c->delivery_system, c->modulation, c->frequency,
  62                 c->bandwidth_hz, c->inversion);
  63
  64         switch (c->bandwidth_hz) {
  65         case 6000000:
  66                 bw_i = 0;
  67                 bw_param = 2;
  68                 break;
  69         case 7000000:
  70                 bw_i = 1;
  71                 bw_param = 1;
  72                 break;
  73         case 8000000:
  74                 bw_i = 2;
  75                 bw_param = 0;
  76                 break;
  77         default:
  78                 return -EINVAL;
  79         }
  80
  81         /* program tuner */
  82         if (fe->ops.tuner_ops.set_params)
  83                 fe->ops.tuner_ops.set_params(fe);
  84
  85         if (priv->delivery_system != SYS_DVBT) {
  86                 for (i = 0; i < ARRAY_SIZE(tab); i++) {
  87                         ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
  88                                 tab[i].val, tab[i].mask);
  89                         if (ret)
  90                                 goto error;
  91                 }
  92         }
  93
  94         priv->delivery_system = SYS_DVBT;
  95         priv->ber_running = false; /* tune stops BER counter */
  96
  97         /* program IF frequency */
  98         if (fe->ops.tuner_ops.get_if_frequency) {
  99                 ret = fe->ops.tuner_ops.get_if_frequency(fe, &if_frequency);
 100                 if (ret)
 101                         goto error;
 102                 dev_dbg(&client->dev, "if_frequency=%u\n", if_frequency);
 103         } else {
 104                 ret = -EINVAL;
 105                 goto error;
 106         }
 107
 108         utmp = DIV_ROUND_CLOSEST_ULL((u64)if_frequency * 0x1000000, CXD2820R_CLK);
 109         buf[0] = (utmp >> 16) & 0xff;
 110         buf[1] = (utmp >>  8) & 0xff;
 111         buf[2] = (utmp >>  0) & 0xff;
 112         ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
 113         if (ret)
 114                 goto error;
 115
 116         ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[bw_i], 5);
 117         if (ret)
 118                 goto error;
 119
 120         ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
 121         if (ret)
 122                 goto error;
 123
 124         ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[bw_i], 2);
 125         if (ret)
 126                 goto error;
 127
 128         ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
 129         if (ret)
 130                 goto error;
 131
 132         ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
 133         if (ret)
 134                 goto error;
 135
 136         return ret;
 137 error:
 138         dev_dbg(&client->dev, "failed=%d\n", ret);
 139         return ret;
 140 }
 141
 142 int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
 143                             struct dtv_frontend_properties *c)
 144 {
 145         struct cxd2820r_priv *priv = fe->demodulator_priv;
 146         struct i2c_client *client = priv->client[0];
 147         int ret;
 148         u8 buf[2];
 149
 150         dev_dbg(&client->dev, "\n");
 151
 152         ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
 153         if (ret)
 154                 goto error;
 155
 156         switch ((buf[0] >> 6) & 0x03) {
 157         case 0:
 158                 c->modulation = QPSK;
 159                 break;
 160         case 1:
 161                 c->modulation = QAM_16;
 162                 break;
 163         case 2:
 164                 c->modulation = QAM_64;
 165                 break;
 166         }
 167
 168         switch ((buf[1] >> 1) & 0x03) {
 169         case 0:
 170                 c->transmission_mode = TRANSMISSION_MODE_2K;
 171                 break;
 172         case 1:
 173                 c->transmission_mode = TRANSMISSION_MODE_8K;
 174                 break;
 175         }
 176
 177         switch ((buf[1] >> 3) & 0x03) {
 178         case 0:
 179                 c->guard_interval = GUARD_INTERVAL_1_32;
 180                 break;
 181         case 1:
 182                 c->guard_interval = GUARD_INTERVAL_1_16;
 183                 break;
 184         case 2:
 185                 c->guard_interval = GUARD_INTERVAL_1_8;
 186                 break;
 187         case 3:
 188                 c->guard_interval = GUARD_INTERVAL_1_4;
 189                 break;
 190         }
 191
 192         switch ((buf[0] >> 3) & 0x07) {
 193         case 0:
 194                 c->hierarchy = HIERARCHY_NONE;
 195                 break;
 196         case 1:
 197                 c->hierarchy = HIERARCHY_1;
 198                 break;
 199         case 2:
 200                 c->hierarchy = HIERARCHY_2;
 201                 break;
 202         case 3:
 203                 c->hierarchy = HIERARCHY_4;
 204                 break;
 205         }
 206
 207         switch ((buf[0] >> 0) & 0x07) {
 208         case 0:
 209                 c->code_rate_HP = FEC_1_2;
 210                 break;
 211         case 1:
 212                 c->code_rate_HP = FEC_2_3;
 213                 break;
 214         case 2:
 215                 c->code_rate_HP = FEC_3_4;
 216                 break;
 217         case 3:
 218                 c->code_rate_HP = FEC_5_6;
 219                 break;
 220         case 4:
 221                 c->code_rate_HP = FEC_7_8;
 222                 break;
 223         }
 224
 225         switch ((buf[1] >> 5) & 0x07) {
 226         case 0:
 227                 c->code_rate_LP = FEC_1_2;
 228                 break;
 229         case 1:
 230                 c->code_rate_LP = FEC_2_3;
 231                 break;
 232         case 2:
 233                 c->code_rate_LP = FEC_3_4;
 234                 break;
 235         case 3:
 236                 c->code_rate_LP = FEC_5_6;
 237                 break;
 238         case 4:
 239                 c->code_rate_LP = FEC_7_8;
 240                 break;
 241         }
 242
 243         ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
 244         if (ret)
 245                 goto error;
 246
 247         switch ((buf[0] >> 0) & 0x01) {
 248         case 0:
 249                 c->inversion = INVERSION_OFF;
 250                 break;
 251         case 1:
 252                 c->inversion = INVERSION_ON;
 253                 break;
 254         }
 255
 256         return ret;
 257 error:
 258         dev_dbg(&client->dev, "failed=%d\n", ret);
 259         return ret;
 260 }
 261
 262 int cxd2820r_read_status_t(struct dvb_frontend *fe, enum fe_status *status)
 263 {
 264         struct cxd2820r_priv *priv = fe->demodulator_priv;
 265         struct i2c_client *client = priv->client[0];
 266         struct dtv_frontend_properties *c = &fe->dtv_property_cache;
 267         int ret;
 268         unsigned int utmp, utmp1, utmp2;
 269         u8 buf[3];
 270
 271         /* Lock detection */
 272         ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
 273         if (ret)
 274                 goto error;
 275         ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
 276         if (ret)
 277                 goto error;
 278
 279         utmp1 = (buf[0] >> 0) & 0x07;
 280         utmp2 = (buf[1] >> 3) & 0x01;
 281
 282         if (utmp1 == 6 && utmp2 == 1) {
 283                 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 284                           FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 285         } else if (utmp1 == 6 || utmp2 == 1) {
 286                 *status = FE_HAS_SIGNAL | FE_HAS_CARRIER |
 287                           FE_HAS_VITERBI | FE_HAS_SYNC;
 288         } else {
 289                 *status = 0;
 290         }
 291
 292         dev_dbg(&client->dev, "status=%02x raw=%*ph sync=%u ts=%u\n",
 293                 *status, 2, buf, utmp1, utmp2);
 294
 295         /* Signal strength */
 296         if (*status & FE_HAS_SIGNAL) {
 297                 unsigned int strength;
 298
 299                 ret = cxd2820r_rd_regs(priv, 0x00026, buf, 2);
 300                 if (ret)
 301                         goto error;
 302
 303                 utmp = buf[0] << 8 | buf[1] << 0;
 304                 utmp = ~utmp & 0x0fff;
 305                 /* Scale value to 0x0000-0xffff */
 306                 strength = utmp << 4 | utmp >> 8;
 307
 308                 c->strength.len = 1;
 309                 c->strength.stat[0].scale = FE_SCALE_RELATIVE;
 310                 c->strength.stat[0].uvalue = strength;
 311         } else {
 312                 c->strength.len = 1;
 313                 c->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 314         }
 315
 316         /* CNR */
 317         if (*status & FE_HAS_VITERBI) {
 318                 unsigned int cnr;
 319
 320                 ret = cxd2820r_rd_regs(priv, 0x0002c, buf, 2);
 321                 if (ret)
 322                         goto error;
 323
 324                 utmp = buf[0] << 8 | buf[1] << 0;
 325                 if (utmp)
 326                         cnr = div_u64((u64)(intlog10(utmp)
 327                                       - intlog10(32000 - utmp) + 55532585)
 328                                       * 10000, (1 << 24));
 329                 else
 330                         cnr = 0;
 331
 332                 c->cnr.len = 1;
 333                 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
 334                 c->cnr.stat[0].svalue = cnr;
 335         } else {
 336                 c->cnr.len = 1;
 337                 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 338         }
 339
 340         /* BER */
 341         if (*status & FE_HAS_SYNC) {
 342                 unsigned int post_bit_error;
 343                 bool start_ber;
 344
 345                 if (priv->ber_running) {
 346                         ret = cxd2820r_rd_regs(priv, 0x00076, buf, 3);
 347                         if (ret)
 348                                 goto error;
 349
 350                         if ((buf[2] >> 7) & 0x01) {
 351                                 post_bit_error = buf[2] << 16 | buf[1] << 8 |
 352                                                  buf[0] << 0;
 353                                 post_bit_error &= 0x0fffff;
 354                                 start_ber = true;
 355                         } else {
 356                                 post_bit_error = 0;
 357                                 start_ber = false;
 358                         }
 359                 } else {
 360                         post_bit_error = 0;
 361                         start_ber = true;
 362                 }
 363
 364                 if (start_ber) {
 365                         ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
 366                         if (ret)
 367                                 goto error;
 368                         priv->ber_running = true;
 369                 }
 370
 371                 priv->post_bit_error += post_bit_error;
 372
 373                 c->post_bit_error.len = 1;
 374                 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
 375                 c->post_bit_error.stat[0].uvalue = priv->post_bit_error;
 376         } else {
 377                 c->post_bit_error.len = 1;
 378                 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
 379         }
 380
 381         return ret;
 382 error:
 383         dev_dbg(&client->dev, "failed=%d\n", ret);
 384         return ret;
 385 }
 386
 387 int cxd2820r_init_t(struct dvb_frontend *fe)
 388 {
 389         struct cxd2820r_priv *priv = fe->demodulator_priv;
 390         struct i2c_client *client = priv->client[0];
 391         int ret;
 392
 393         dev_dbg(&client->dev, "\n");
 394
 395         ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
 396         if (ret)
 397                 goto error;
 398
 399         return ret;
 400 error:
 401         dev_dbg(&client->dev, "failed=%d\n", ret);
 402         return ret;
 403 }
 404
 405 int cxd2820r_sleep_t(struct dvb_frontend *fe)
 406 {
 407         struct cxd2820r_priv *priv = fe->demodulator_priv;
 408         struct i2c_client *client = priv->client[0];
 409         int ret, i;
 410         struct reg_val_mask tab[] = {
 411                 { 0x000ff, 0x1f, 0xff },
 412                 { 0x00085, 0x00, 0xff },
 413                 { 0x00088, 0x01, 0xff },
 414                 { 0x00081, 0x00, 0xff },
 415                 { 0x00080, 0x00, 0xff },
 416         };
 417
 418         dev_dbg(&client->dev, "\n");
 419
 420         priv->delivery_system = SYS_UNDEFINED;
 421
 422         for (i = 0; i < ARRAY_SIZE(tab); i++) {
 423                 ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
 424                         tab[i].mask);
 425                 if (ret)
 426                         goto error;
 427         }
 428
 429         return ret;
 430 error:
 431         dev_dbg(&client->dev, "failed=%d\n", ret);
 432         return ret;
 433 }
 434
 435 int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
 436         struct dvb_frontend_tune_settings *s)
 437 {
 438         s->min_delay_ms = 500;
 439         s->step_size = fe->ops.info.frequency_stepsize * 2;
 440         s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
 441
 442         return 0;
 443 }