drivers/media/dvb-frontends/cxd2841er.c

   1 /*
   2  * cxd2841er.c
   3  *
   4  * Sony digital demodulator driver for
   5  *      CXD2841ER - DVB-S/S2/T/T2/C/C2
   6  *      CXD2854ER - DVB-S/S2/T/T2/C/C2, ISDB-T/S
   7  *
   8  * Copyright 2012 Sony Corporation
   9  * Copyright (C) 2014 NetUP Inc.
  10  * Copyright (C) 2014 Sergey Kozlov <serjk@netup.ru>
  11  * Copyright (C) 2014 Abylay Ospan <aospan@netup.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22   */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/bitops.h>
  29 #include <linux/math64.h>
  30 #include <linux/log2.h>
  31 #include <linux/dynamic_debug.h>
  32
  33 #include "dvb_math.h"
  34 #include "dvb_frontend.h"
  35 #include "cxd2841er.h"
  36 #include "cxd2841er_priv.h"
  37
  38 #define MAX_WRITE_REGSIZE       16
  39 #define LOG2_E_100X 144
  40
  41 /* DVB-C constellation */
  42 enum sony_dvbc_constellation_t {
  43         SONY_DVBC_CONSTELLATION_16QAM,
  44         SONY_DVBC_CONSTELLATION_32QAM,
  45         SONY_DVBC_CONSTELLATION_64QAM,
  46         SONY_DVBC_CONSTELLATION_128QAM,
  47         SONY_DVBC_CONSTELLATION_256QAM
  48 };
  49
  50 enum cxd2841er_state {
  51         STATE_SHUTDOWN = 0,
  52         STATE_SLEEP_S,
  53         STATE_ACTIVE_S,
  54         STATE_SLEEP_TC,
  55         STATE_ACTIVE_TC
  56 };
  57
  58 struct cxd2841er_priv {
  59         struct dvb_frontend             frontend;
  60         struct i2c_adapter              *i2c;
  61         u8                              i2c_addr_slvx;
  62         u8                              i2c_addr_slvt;
  63         const struct cxd2841er_config   *config;
  64         enum cxd2841er_state            state;
  65         u8                              system;
  66         enum cxd2841er_xtal             xtal;
  67         enum fe_caps caps;
  68 };
  69
  70 static const struct cxd2841er_cnr_data s_cn_data[] = {
  71         { 0x033e, 0 }, { 0x0339, 100 }, { 0x0333, 200 },
  72         { 0x032e, 300 }, { 0x0329, 400 }, { 0x0324, 500 },
  73         { 0x031e, 600 }, { 0x0319, 700 }, { 0x0314, 800 },
  74         { 0x030f, 900 }, { 0x030a, 1000 }, { 0x02ff, 1100 },
  75         { 0x02f4, 1200 }, { 0x02e9, 1300 }, { 0x02de, 1400 },
  76         { 0x02d4, 1500 }, { 0x02c9, 1600 }, { 0x02bf, 1700 },
  77         { 0x02b5, 1800 }, { 0x02ab, 1900 }, { 0x02a1, 2000 },
  78         { 0x029b, 2100 }, { 0x0295, 2200 }, { 0x0290, 2300 },
  79         { 0x028a, 2400 }, { 0x0284, 2500 }, { 0x027f, 2600 },
  80         { 0x0279, 2700 }, { 0x0274, 2800 }, { 0x026e, 2900 },
  81         { 0x0269, 3000 }, { 0x0262, 3100 }, { 0x025c, 3200 },
  82         { 0x0255, 3300 }, { 0x024f, 3400 }, { 0x0249, 3500 },
  83         { 0x0242, 3600 }, { 0x023c, 3700 }, { 0x0236, 3800 },
  84         { 0x0230, 3900 }, { 0x022a, 4000 }, { 0x0223, 4100 },
  85         { 0x021c, 4200 }, { 0x0215, 4300 }, { 0x020e, 4400 },
  86         { 0x0207, 4500 }, { 0x0201, 4600 }, { 0x01fa, 4700 },
  87         { 0x01f4, 4800 }, { 0x01ed, 4900 }, { 0x01e7, 5000 },
  88         { 0x01e0, 5100 }, { 0x01d9, 5200 }, { 0x01d2, 5300 },
  89         { 0x01cb, 5400 }, { 0x01c4, 5500 }, { 0x01be, 5600 },
  90         { 0x01b7, 5700 }, { 0x01b1, 5800 }, { 0x01aa, 5900 },
  91         { 0x01a4, 6000 }, { 0x019d, 6100 }, { 0x0196, 6200 },
  92         { 0x018f, 6300 }, { 0x0189, 6400 }, { 0x0182, 6500 },
  93         { 0x017c, 6600 }, { 0x0175, 6700 }, { 0x016f, 6800 },
  94         { 0x0169, 6900 }, { 0x0163, 7000 }, { 0x015c, 7100 },
  95         { 0x0156, 7200 }, { 0x0150, 7300 }, { 0x014a, 7400 },
  96         { 0x0144, 7500 }, { 0x013e, 7600 }, { 0x0138, 7700 },
  97         { 0x0132, 7800 }, { 0x012d, 7900 }, { 0x0127, 8000 },
  98         { 0x0121, 8100 }, { 0x011c, 8200 }, { 0x0116, 8300 },
  99         { 0x0111, 8400 }, { 0x010b, 8500 }, { 0x0106, 8600 },
 100         { 0x0101, 8700 }, { 0x00fc, 8800 }, { 0x00f7, 8900 },
 101         { 0x00f2, 9000 }, { 0x00ee, 9100 }, { 0x00ea, 9200 },
 102         { 0x00e6, 9300 }, { 0x00e2, 9400 }, { 0x00de, 9500 },
 103         { 0x00da, 9600 }, { 0x00d7, 9700 }, { 0x00d3, 9800 },
 104         { 0x00d0, 9900 }, { 0x00cc, 10000 }, { 0x00c7, 10100 },
 105         { 0x00c3, 10200 }, { 0x00bf, 10300 }, { 0x00ba, 10400 },
 106         { 0x00b6, 10500 }, { 0x00b2, 10600 }, { 0x00ae, 10700 },
 107         { 0x00aa, 10800 }, { 0x00a7, 10900 }, { 0x00a3, 11000 },
 108         { 0x009f, 11100 }, { 0x009c, 11200 }, { 0x0098, 11300 },
 109         { 0x0094, 11400 }, { 0x0091, 11500 }, { 0x008e, 11600 },
 110         { 0x008a, 11700 }, { 0x0087, 11800 }, { 0x0084, 11900 },
 111         { 0x0081, 12000 }, { 0x007e, 12100 }, { 0x007b, 12200 },
 112         { 0x0079, 12300 }, { 0x0076, 12400 }, { 0x0073, 12500 },
 113         { 0x0071, 12600 }, { 0x006e, 12700 }, { 0x006c, 12800 },
 114         { 0x0069, 12900 }, { 0x0067, 13000 }, { 0x0065, 13100 },
 115         { 0x0062, 13200 }, { 0x0060, 13300 }, { 0x005e, 13400 },
 116         { 0x005c, 13500 }, { 0x005a, 13600 }, { 0x0058, 13700 },
 117         { 0x0056, 13800 }, { 0x0054, 13900 }, { 0x0052, 14000 },
 118         { 0x0050, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 119         { 0x004b, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 120         { 0x0046, 14700 }, { 0x0044, 14800 }, { 0x0043, 14900 },
 121         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 122         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 123         { 0x0037, 15700 }, { 0x0036, 15800 }, { 0x0034, 15900 },
 124         { 0x0033, 16000 }, { 0x0032, 16100 }, { 0x0031, 16200 },
 125         { 0x0030, 16300 }, { 0x002f, 16400 }, { 0x002e, 16500 },
 126         { 0x002d, 16600 }, { 0x002c, 16700 }, { 0x002b, 16800 },
 127         { 0x002a, 16900 }, { 0x0029, 17000 }, { 0x0028, 17100 },
 128         { 0x0027, 17200 }, { 0x0026, 17300 }, { 0x0025, 17400 },
 129         { 0x0024, 17500 }, { 0x0023, 17600 }, { 0x0022, 17800 },
 130         { 0x0021, 17900 }, { 0x0020, 18000 }, { 0x001f, 18200 },
 131         { 0x001e, 18300 }, { 0x001d, 18500 }, { 0x001c, 18700 },
 132         { 0x001b, 18900 }, { 0x001a, 19000 }, { 0x0019, 19200 },
 133         { 0x0018, 19300 }, { 0x0017, 19500 }, { 0x0016, 19700 },
 134         { 0x0015, 19900 }, { 0x0014, 20000 },
 135 };
 136
 137 static const struct cxd2841er_cnr_data s2_cn_data[] = {
 138         { 0x05af, 0 }, { 0x0597, 100 }, { 0x057e, 200 },
 139         { 0x0567, 300 }, { 0x0550, 400 }, { 0x0539, 500 },
 140         { 0x0522, 600 }, { 0x050c, 700 }, { 0x04f6, 800 },
 141         { 0x04e1, 900 }, { 0x04cc, 1000 }, { 0x04b6, 1100 },
 142         { 0x04a1, 1200 }, { 0x048c, 1300 }, { 0x0477, 1400 },
 143         { 0x0463, 1500 }, { 0x044f, 1600 }, { 0x043c, 1700 },
 144         { 0x0428, 1800 }, { 0x0416, 1900 }, { 0x0403, 2000 },
 145         { 0x03ef, 2100 }, { 0x03dc, 2200 }, { 0x03c9, 2300 },
 146         { 0x03b6, 2400 }, { 0x03a4, 2500 }, { 0x0392, 2600 },
 147         { 0x0381, 2700 }, { 0x036f, 2800 }, { 0x035f, 2900 },
 148         { 0x034e, 3000 }, { 0x033d, 3100 }, { 0x032d, 3200 },
 149         { 0x031d, 3300 }, { 0x030d, 3400 }, { 0x02fd, 3500 },
 150         { 0x02ee, 3600 }, { 0x02df, 3700 }, { 0x02d0, 3800 },
 151         { 0x02c2, 3900 }, { 0x02b4, 4000 }, { 0x02a6, 4100 },
 152         { 0x0299, 4200 }, { 0x028c, 4300 }, { 0x027f, 4400 },
 153         { 0x0272, 4500 }, { 0x0265, 4600 }, { 0x0259, 4700 },
 154         { 0x024d, 4800 }, { 0x0241, 4900 }, { 0x0236, 5000 },
 155         { 0x022b, 5100 }, { 0x0220, 5200 }, { 0x0215, 5300 },
 156         { 0x020a, 5400 }, { 0x0200, 5500 }, { 0x01f6, 5600 },
 157         { 0x01ec, 5700 }, { 0x01e2, 5800 }, { 0x01d8, 5900 },
 158         { 0x01cf, 6000 }, { 0x01c6, 6100 }, { 0x01bc, 6200 },
 159         { 0x01b3, 6300 }, { 0x01aa, 6400 }, { 0x01a2, 6500 },
 160         { 0x0199, 6600 }, { 0x0191, 6700 }, { 0x0189, 6800 },
 161         { 0x0181, 6900 }, { 0x0179, 7000 }, { 0x0171, 7100 },
 162         { 0x0169, 7200 }, { 0x0161, 7300 }, { 0x015a, 7400 },
 163         { 0x0153, 7500 }, { 0x014b, 7600 }, { 0x0144, 7700 },
 164         { 0x013d, 7800 }, { 0x0137, 7900 }, { 0x0130, 8000 },
 165         { 0x012a, 8100 }, { 0x0124, 8200 }, { 0x011e, 8300 },
 166         { 0x0118, 8400 }, { 0x0112, 8500 }, { 0x010c, 8600 },
 167         { 0x0107, 8700 }, { 0x0101, 8800 }, { 0x00fc, 8900 },
 168         { 0x00f7, 9000 }, { 0x00f2, 9100 }, { 0x00ec, 9200 },
 169         { 0x00e7, 9300 }, { 0x00e2, 9400 }, { 0x00dd, 9500 },
 170         { 0x00d8, 9600 }, { 0x00d4, 9700 }, { 0x00cf, 9800 },
 171         { 0x00ca, 9900 }, { 0x00c6, 10000 }, { 0x00c2, 10100 },
 172         { 0x00be, 10200 }, { 0x00b9, 10300 }, { 0x00b5, 10400 },
 173         { 0x00b1, 10500 }, { 0x00ae, 10600 }, { 0x00aa, 10700 },
 174         { 0x00a6, 10800 }, { 0x00a3, 10900 }, { 0x009f, 11000 },
 175         { 0x009b, 11100 }, { 0x0098, 11200 }, { 0x0095, 11300 },
 176         { 0x0091, 11400 }, { 0x008e, 11500 }, { 0x008b, 11600 },
 177         { 0x0088, 11700 }, { 0x0085, 11800 }, { 0x0082, 11900 },
 178         { 0x007f, 12000 }, { 0x007c, 12100 }, { 0x007a, 12200 },
 179         { 0x0077, 12300 }, { 0x0074, 12400 }, { 0x0072, 12500 },
 180         { 0x006f, 12600 }, { 0x006d, 12700 }, { 0x006b, 12800 },
 181         { 0x0068, 12900 }, { 0x0066, 13000 }, { 0x0064, 13100 },
 182         { 0x0061, 13200 }, { 0x005f, 13300 }, { 0x005d, 13400 },
 183         { 0x005b, 13500 }, { 0x0059, 13600 }, { 0x0057, 13700 },
 184         { 0x0055, 13800 }, { 0x0053, 13900 }, { 0x0051, 14000 },
 185         { 0x004f, 14100 }, { 0x004e, 14200 }, { 0x004c, 14300 },
 186         { 0x004a, 14400 }, { 0x0049, 14500 }, { 0x0047, 14600 },
 187         { 0x0045, 14700 }, { 0x0044, 14800 }, { 0x0042, 14900 },
 188         { 0x0041, 15000 }, { 0x003f, 15100 }, { 0x003e, 15200 },
 189         { 0x003c, 15300 }, { 0x003b, 15400 }, { 0x003a, 15500 },
 190         { 0x0038, 15600 }, { 0x0037, 15700 }, { 0x0036, 15800 },
 191         { 0x0034, 15900 }, { 0x0033, 16000 }, { 0x0032, 16100 },
 192         { 0x0031, 16200 }, { 0x0030, 16300 }, { 0x002f, 16400 },
 193         { 0x002e, 16500 }, { 0x002d, 16600 }, { 0x002c, 16700 },
 194         { 0x002b, 16800 }, { 0x002a, 16900 }, { 0x0029, 17000 },
 195         { 0x0028, 17100 }, { 0x0027, 17200 }, { 0x0026, 17300 },
 196         { 0x0025, 17400 }, { 0x0024, 17500 }, { 0x0023, 17600 },
 197         { 0x0022, 17800 }, { 0x0021, 17900 }, { 0x0020, 18000 },
 198         { 0x001f, 18200 }, { 0x001e, 18300 }, { 0x001d, 18500 },
 199         { 0x001c, 18700 }, { 0x001b, 18900 }, { 0x001a, 19000 },
 200         { 0x0019, 19200 }, { 0x0018, 19300 }, { 0x0017, 19500 },
 201         { 0x0016, 19700 }, { 0x0015, 19900 }, { 0x0014, 20000 },
 202 };
 203
 204 #define MAKE_IFFREQ_CONFIG(iffreq) ((u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 205 #define MAKE_IFFREQ_CONFIG_XTAL(xtal, iffreq) ((xtal == SONY_XTAL_24000) ? \
 206                 (u32)(((iffreq)/48.0)*16777216.0 + 0.5) : \
 207                 (u32)(((iffreq)/41.0)*16777216.0 + 0.5))
 208
 209 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv);
 210 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv);
 211
 212 static void cxd2841er_i2c_debug(struct cxd2841er_priv *priv,
 213                                 u8 addr, u8 reg, u8 write,
 214                                 const u8 *data, u32 len)
 215 {
 216         dev_dbg(&priv->i2c->dev,
 217                 "cxd2841er: I2C %s addr %02x reg 0x%02x size %d\n",
 218                 (write == 0 ? "read" : "write"), addr, reg, len);
 219         print_hex_dump_bytes("cxd2841er: I2C data: ",
 220                 DUMP_PREFIX_OFFSET, data, len);
 221 }
 222
 223 static int cxd2841er_write_regs(struct cxd2841er_priv *priv,
 224                                 u8 addr, u8 reg, const u8 *data, u32 len)
 225 {
 226         int ret;
 227         u8 buf[MAX_WRITE_REGSIZE + 1];
 228         u8 i2c_addr = (addr == I2C_SLVX ?
 229                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 230         struct i2c_msg msg[1] = {
 231                 {
 232                         .addr = i2c_addr,
 233                         .flags = 0,
 234                         .len = len + 1,
 235                         .buf = buf,
 236                 }
 237         };
 238
 239         if (len + 1 >= sizeof(buf)) {
 240                 dev_warn(&priv->i2c->dev, "wr reg=%04x: len=%d is too big!\n",
 241                          reg, len + 1);
 242                 return -E2BIG;
 243         }
 244
 245         cxd2841er_i2c_debug(priv, i2c_addr, reg, 1, data, len);
 246         buf[0] = reg;
 247         memcpy(&buf[1], data, len);
 248
 249         ret = i2c_transfer(priv->i2c, msg, 1);
 250         if (ret >= 0 && ret != 1)
 251                 ret = -EIO;
 252         if (ret < 0) {
 253                 dev_warn(&priv->i2c->dev,
 254                         "%s: i2c wr failed=%d addr=%02x reg=%02x len=%d\n",
 255                         KBUILD_MODNAME, ret, i2c_addr, reg, len);
 256                 return ret;
 257         }
 258         return 0;
 259 }
 260
 261 static int cxd2841er_write_reg(struct cxd2841er_priv *priv,
 262                                u8 addr, u8 reg, u8 val)
 263 {
 264         return cxd2841er_write_regs(priv, addr, reg, &val, 1);
 265 }
 266
 267 static int cxd2841er_read_regs(struct cxd2841er_priv *priv,
 268                                u8 addr, u8 reg, u8 *val, u32 len)
 269 {
 270         int ret;
 271         u8 i2c_addr = (addr == I2C_SLVX ?
 272                 priv->i2c_addr_slvx : priv->i2c_addr_slvt);
 273         struct i2c_msg msg[2] = {
 274                 {
 275                         .addr = i2c_addr,
 276                         .flags = 0,
 277                         .len = 1,
 278                         .buf = &reg,
 279                 }, {
 280                         .addr = i2c_addr,
 281                         .flags = I2C_M_RD,
 282                         .len = len,
 283                         .buf = val,
 284                 }
 285         };
 286
 287         ret = i2c_transfer(priv->i2c, &msg[0], 1);
 288         if (ret >= 0 && ret != 1)
 289                 ret = -EIO;
 290         if (ret < 0) {
 291                 dev_warn(&priv->i2c->dev,
 292                         "%s: i2c rw failed=%d addr=%02x reg=%02x\n",
 293                         KBUILD_MODNAME, ret, i2c_addr, reg);
 294                 return ret;
 295         }
 296         ret = i2c_transfer(priv->i2c, &msg[1], 1);
 297         if (ret >= 0 && ret != 1)
 298                 ret = -EIO;
 299         if (ret < 0) {
 300                 dev_warn(&priv->i2c->dev,
 301                         "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
 302                         KBUILD_MODNAME, ret, i2c_addr, reg);
 303                 return ret;
 304         }
 305         cxd2841er_i2c_debug(priv, i2c_addr, reg, 0, val, len);
 306         return 0;
 307 }
 308
 309 static int cxd2841er_read_reg(struct cxd2841er_priv *priv,
 310                               u8 addr, u8 reg, u8 *val)
 311 {
 312         return cxd2841er_read_regs(priv, addr, reg, val, 1);
 313 }
 314
 315 static int cxd2841er_set_reg_bits(struct cxd2841er_priv *priv,
 316                                   u8 addr, u8 reg, u8 data, u8 mask)
 317 {
 318         int res;
 319         u8 rdata;
 320
 321         if (mask != 0xff) {
 322                 res = cxd2841er_read_reg(priv, addr, reg, &rdata);
 323                 if (res)
 324                         return res;
 325                 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
 326         }
 327         return cxd2841er_write_reg(priv, addr, reg, data);
 328 }
 329
 330 static int cxd2841er_dvbs2_set_symbol_rate(struct cxd2841er_priv *priv,
 331                                            u32 symbol_rate)
 332 {
 333         u32 reg_value = 0;
 334         u8 data[3] = {0, 0, 0};
 335
 336         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 337         /*
 338          * regValue = (symbolRateKSps * 2^14 / 1000) + 0.5
 339          *          = ((symbolRateKSps * 2^14) + 500) / 1000
 340          *          = ((symbolRateKSps * 16384) + 500) / 1000
 341          */
 342         reg_value = DIV_ROUND_CLOSEST(symbol_rate * 16384, 1000);
 343         if ((reg_value == 0) || (reg_value > 0xFFFFF)) {
 344                 dev_err(&priv->i2c->dev,
 345                         "%s(): reg_value is out of range\n", __func__);
 346                 return -EINVAL;
 347         }
 348         data[0] = (u8)((reg_value >> 16) & 0x0F);
 349         data[1] = (u8)((reg_value >>  8) & 0xFF);
 350         data[2] = (u8)(reg_value & 0xFF);
 351         /* Set SLV-T Bank : 0xAE */
 352         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 353         cxd2841er_write_regs(priv, I2C_SLVT, 0x20, data, 3);
 354         return 0;
 355 }
 356
 357 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 358                                         u8 system);
 359
 360 static int cxd2841er_sleep_s_to_active_s(struct cxd2841er_priv *priv,
 361                                          u8 system, u32 symbol_rate)
 362 {
 363         int ret;
 364         u8 data[4] = { 0, 0, 0, 0 };
 365
 366         if (priv->state != STATE_SLEEP_S) {
 367                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 368                         __func__, (int)priv->state);
 369                 return -EINVAL;
 370         }
 371         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 372         cxd2841er_set_ts_clock_mode(priv, SYS_DVBS);
 373         /* Set demod mode */
 374         if (system == SYS_DVBS) {
 375                 data[0] = 0x0A;
 376         } else if (system == SYS_DVBS2) {
 377                 data[0] = 0x0B;
 378         } else {
 379                 dev_err(&priv->i2c->dev, "%s(): invalid delsys %d\n",
 380                         __func__, system);
 381                 return -EINVAL;
 382         }
 383         /* Set SLV-X Bank : 0x00 */
 384         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 385         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, data[0]);
 386         /* DVB-S/S2 */
 387         data[0] = 0x00;
 388         /* Set SLV-T Bank : 0x00 */
 389         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 390         /* Enable S/S2 auto detection 1 */
 391         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, data[0]);
 392         /* Set SLV-T Bank : 0xAE */
 393         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 394         /* Enable S/S2 auto detection 2 */
 395         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, data[0]);
 396         /* Set SLV-T Bank : 0x00 */
 397         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 398         /* Enable demod clock */
 399         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
 400         /* Enable ADC clock */
 401         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x01);
 402         /* Enable ADC 1 */
 403         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 404         /* Enable ADC 2 */
 405         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x3f);
 406         /* Set SLV-X Bank : 0x00 */
 407         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 408         /* Enable ADC 3 */
 409         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
 410         /* Set SLV-T Bank : 0xA3 */
 411         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa3);
 412         cxd2841er_write_reg(priv, I2C_SLVT, 0xac, 0x00);
 413         data[0] = 0x07;
 414         data[1] = 0x3B;
 415         data[2] = 0x08;
 416         data[3] = 0xC5;
 417         /* Set SLV-T Bank : 0xAB */
 418         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xab);
 419         cxd2841er_write_regs(priv, I2C_SLVT, 0x98, data, 4);
 420         data[0] = 0x05;
 421         data[1] = 0x80;
 422         data[2] = 0x0A;
 423         data[3] = 0x80;
 424         cxd2841er_write_regs(priv, I2C_SLVT, 0xa8, data, 4);
 425         data[0] = 0x0C;
 426         data[1] = 0xCC;
 427         cxd2841er_write_regs(priv, I2C_SLVT, 0xc3, data, 2);
 428         /* Set demod parameter */
 429         ret = cxd2841er_dvbs2_set_symbol_rate(priv, symbol_rate);
 430         if (ret != 0)
 431                 return ret;
 432         /* Set SLV-T Bank : 0x00 */
 433         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 434         /* disable Hi-Z setting 1 */
 435         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x10);
 436         /* disable Hi-Z setting 2 */
 437         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
 438         priv->state = STATE_ACTIVE_S;
 439         return 0;
 440 }
 441
 442 static int cxd2841er_sleep_tc_to_active_t_band(struct cxd2841er_priv *priv,
 443                                                u32 bandwidth);
 444
 445 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
 446                                                 u32 bandwidth);
 447
 448 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
 449                                                u32 bandwidth);
 450
 451 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
 452                 u32 bandwidth);
 453
 454 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv);
 455
 456 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv);
 457
 458 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv);
 459
 460 static int cxd2841er_retune_active(struct cxd2841er_priv *priv,
 461                                    struct dtv_frontend_properties *p)
 462 {
 463         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 464         if (priv->state != STATE_ACTIVE_S &&
 465                         priv->state != STATE_ACTIVE_TC) {
 466                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
 467                         __func__, priv->state);
 468                 return -EINVAL;
 469         }
 470         /* Set SLV-T Bank : 0x00 */
 471         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 472         /* disable TS output */
 473         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 474         if (priv->state == STATE_ACTIVE_S)
 475                 return cxd2841er_dvbs2_set_symbol_rate(
 476                                 priv, p->symbol_rate / 1000);
 477         else if (priv->state == STATE_ACTIVE_TC) {
 478                 switch (priv->system) {
 479                 case SYS_DVBT:
 480                         return cxd2841er_sleep_tc_to_active_t_band(
 481                                         priv, p->bandwidth_hz);
 482                 case SYS_DVBT2:
 483                         return cxd2841er_sleep_tc_to_active_t2_band(
 484                                         priv, p->bandwidth_hz);
 485                 case SYS_DVBC_ANNEX_A:
 486                         return cxd2841er_sleep_tc_to_active_c_band(
 487                                         priv, p->bandwidth_hz);
 488                 case SYS_ISDBT:
 489                         cxd2841er_active_i_to_sleep_tc(priv);
 490                         cxd2841er_sleep_tc_to_shutdown(priv);
 491                         cxd2841er_shutdown_to_sleep_tc(priv);
 492                         return cxd2841er_sleep_tc_to_active_i(
 493                                         priv, p->bandwidth_hz);
 494                 }
 495         }
 496         dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
 497                 __func__, priv->system);
 498         return -EINVAL;
 499 }
 500
 501 static int cxd2841er_active_s_to_sleep_s(struct cxd2841er_priv *priv)
 502 {
 503         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 504         if (priv->state != STATE_ACTIVE_S) {
 505                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 506                         __func__, priv->state);
 507                 return -EINVAL;
 508         }
 509         /* Set SLV-T Bank : 0x00 */
 510         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 511         /* disable TS output */
 512         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 513         /* enable Hi-Z setting 1 */
 514         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1f);
 515         /* enable Hi-Z setting 2 */
 516         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 517         /* Set SLV-X Bank : 0x00 */
 518         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 519         /* disable ADC 1 */
 520         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 521         /* Set SLV-T Bank : 0x00 */
 522         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 523         /* disable ADC clock */
 524         cxd2841er_write_reg(priv, I2C_SLVT, 0x31, 0x00);
 525         /* disable ADC 2 */
 526         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 527         /* disable ADC 3 */
 528         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 529         /* SADC Bias ON */
 530         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 531         /* disable demod clock */
 532         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 533         /* Set SLV-T Bank : 0xAE */
 534         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xae);
 535         /* disable S/S2 auto detection1 */
 536         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 537         /* Set SLV-T Bank : 0x00 */
 538         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 539         /* disable S/S2 auto detection2 */
 540         cxd2841er_write_reg(priv, I2C_SLVT, 0x2d, 0x00);
 541         priv->state = STATE_SLEEP_S;
 542         return 0;
 543 }
 544
 545 static int cxd2841er_sleep_s_to_shutdown(struct cxd2841er_priv *priv)
 546 {
 547         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 548         if (priv->state != STATE_SLEEP_S) {
 549                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 550                         __func__, priv->state);
 551                 return -EINVAL;
 552         }
 553         /* Set SLV-T Bank : 0x00 */
 554         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 555         /* Disable DSQOUT */
 556         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 557         /* Disable DSQIN */
 558         cxd2841er_write_reg(priv, I2C_SLVT, 0x9c, 0x00);
 559         /* Set SLV-X Bank : 0x00 */
 560         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 561         /* Disable oscillator */
 562         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 563         /* Set demod mode */
 564         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 565         priv->state = STATE_SHUTDOWN;
 566         return 0;
 567 }
 568
 569 static int cxd2841er_sleep_tc_to_shutdown(struct cxd2841er_priv *priv)
 570 {
 571         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 572         if (priv->state != STATE_SLEEP_TC) {
 573                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 574                         __func__, priv->state);
 575                 return -EINVAL;
 576         }
 577         /* Set SLV-X Bank : 0x00 */
 578         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 579         /* Disable oscillator */
 580         cxd2841er_write_reg(priv, I2C_SLVX, 0x15, 0x01);
 581         /* Set demod mode */
 582         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
 583         priv->state = STATE_SHUTDOWN;
 584         return 0;
 585 }
 586
 587 static int cxd2841er_active_t_to_sleep_tc(struct cxd2841er_priv *priv)
 588 {
 589         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 590         if (priv->state != STATE_ACTIVE_TC) {
 591                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 592                         __func__, priv->state);
 593                 return -EINVAL;
 594         }
 595         /* Set SLV-T Bank : 0x00 */
 596         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 597         /* disable TS output */
 598         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 599         /* enable Hi-Z setting 1 */
 600         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 601         /* enable Hi-Z setting 2 */
 602         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 603         /* Set SLV-X Bank : 0x00 */
 604         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 605         /* disable ADC 1 */
 606         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 607         /* Set SLV-T Bank : 0x00 */
 608         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 609         /* Disable ADC 2 */
 610         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 611         /* Disable ADC 3 */
 612         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 613         /* Disable ADC clock */
 614         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 615         /* Disable RF level monitor */
 616         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 617         /* Disable demod clock */
 618         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 619         priv->state = STATE_SLEEP_TC;
 620         return 0;
 621 }
 622
 623 static int cxd2841er_active_t2_to_sleep_tc(struct cxd2841er_priv *priv)
 624 {
 625         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 626         if (priv->state != STATE_ACTIVE_TC) {
 627                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 628                         __func__, priv->state);
 629                 return -EINVAL;
 630         }
 631         /* Set SLV-T Bank : 0x00 */
 632         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 633         /* disable TS output */
 634         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 635         /* enable Hi-Z setting 1 */
 636         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 637         /* enable Hi-Z setting 2 */
 638         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 639         /* Cancel DVB-T2 setting */
 640         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
 641         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x40);
 642         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x21);
 643         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
 644         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xfb);
 645         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
 646         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x00, 0x0f);
 647         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
 648         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x00, 0x3f);
 649         /* Set SLV-X Bank : 0x00 */
 650         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 651         /* disable ADC 1 */
 652         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 653         /* Set SLV-T Bank : 0x00 */
 654         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 655         /* Disable ADC 2 */
 656         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 657         /* Disable ADC 3 */
 658         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 659         /* Disable ADC clock */
 660         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 661         /* Disable RF level monitor */
 662         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 663         /* Disable demod clock */
 664         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 665         priv->state = STATE_SLEEP_TC;
 666         return 0;
 667 }
 668
 669 static int cxd2841er_active_c_to_sleep_tc(struct cxd2841er_priv *priv)
 670 {
 671         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 672         if (priv->state != STATE_ACTIVE_TC) {
 673                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 674                         __func__, priv->state);
 675                 return -EINVAL;
 676         }
 677         /* Set SLV-T Bank : 0x00 */
 678         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 679         /* disable TS output */
 680         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 681         /* enable Hi-Z setting 1 */
 682         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 683         /* enable Hi-Z setting 2 */
 684         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 685         /* Cancel DVB-C setting */
 686         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
 687         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
 688         /* Set SLV-X Bank : 0x00 */
 689         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 690         /* disable ADC 1 */
 691         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 692         /* Set SLV-T Bank : 0x00 */
 693         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 694         /* Disable ADC 2 */
 695         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 696         /* Disable ADC 3 */
 697         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 698         /* Disable ADC clock */
 699         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 700         /* Disable RF level monitor */
 701         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 702         /* Disable demod clock */
 703         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 704         priv->state = STATE_SLEEP_TC;
 705         return 0;
 706 }
 707
 708 static int cxd2841er_active_i_to_sleep_tc(struct cxd2841er_priv *priv)
 709 {
 710         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 711         if (priv->state != STATE_ACTIVE_TC) {
 712                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 713                                 __func__, priv->state);
 714                 return -EINVAL;
 715         }
 716         /* Set SLV-T Bank : 0x00 */
 717         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 718         /* disable TS output */
 719         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x01);
 720         /* enable Hi-Z setting 1 */
 721         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x3f);
 722         /* enable Hi-Z setting 2 */
 723         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0xff);
 724
 725         /* TODO: Cancel demod parameter */
 726
 727         /* Set SLV-X Bank : 0x00 */
 728         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 729         /* disable ADC 1 */
 730         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x01);
 731         /* Set SLV-T Bank : 0x00 */
 732         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 733         /* Disable ADC 2 */
 734         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 735         /* Disable ADC 3 */
 736         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 737         /* Disable ADC clock */
 738         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
 739         /* Disable RF level monitor */
 740         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
 741         /* Disable demod clock */
 742         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x00);
 743         priv->state = STATE_SLEEP_TC;
 744         return 0;
 745 }
 746
 747 static int cxd2841er_shutdown_to_sleep_s(struct cxd2841er_priv *priv)
 748 {
 749         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 750         if (priv->state != STATE_SHUTDOWN) {
 751                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 752                         __func__, priv->state);
 753                 return -EINVAL;
 754         }
 755         /* Set SLV-X Bank : 0x00 */
 756         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 757         /* Clear all demodulator registers */
 758         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 759         usleep_range(3000, 5000);
 760         /* Set SLV-X Bank : 0x00 */
 761         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 762         /* Set demod SW reset */
 763         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 764
 765         switch (priv->xtal) {
 766         case SONY_XTAL_20500:
 767                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x00);
 768                 break;
 769         case SONY_XTAL_24000:
 770                 /* Select demod frequency */
 771                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 772                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x03);
 773                 break;
 774         case SONY_XTAL_41000:
 775                 cxd2841er_write_reg(priv, I2C_SLVX, 0x14, 0x01);
 776                 break;
 777         default:
 778                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod xtal %d\n",
 779                                 __func__, priv->xtal);
 780                 return -EINVAL;
 781         }
 782
 783         /* Set demod mode */
 784         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x0a);
 785         /* Clear demod SW reset */
 786         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 787         usleep_range(1000, 2000);
 788         /* Set SLV-T Bank : 0x00 */
 789         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 790         /* enable DSQOUT */
 791         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x1F);
 792         /* enable DSQIN */
 793         cxd2841er_write_reg(priv, I2C_SLVT, 0x9C, 0x40);
 794         /* TADC Bias On */
 795         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 796         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 797         /* SADC Bias On */
 798         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 799         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 800         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 801         priv->state = STATE_SLEEP_S;
 802         return 0;
 803 }
 804
 805 static int cxd2841er_shutdown_to_sleep_tc(struct cxd2841er_priv *priv)
 806 {
 807         u8 data = 0;
 808
 809         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 810         if (priv->state != STATE_SHUTDOWN) {
 811                 dev_dbg(&priv->i2c->dev, "%s(): invalid demod state %d\n",
 812                         __func__, priv->state);
 813                 return -EINVAL;
 814         }
 815         /* Set SLV-X Bank : 0x00 */
 816         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 817         /* Clear all demodulator registers */
 818         cxd2841er_write_reg(priv, I2C_SLVX, 0x02, 0x00);
 819         usleep_range(3000, 5000);
 820         /* Set SLV-X Bank : 0x00 */
 821         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
 822         /* Set demod SW reset */
 823         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x01);
 824   /* Select ADC clock mode */
 825         cxd2841er_write_reg(priv, I2C_SLVX, 0x13, 0x00);
 826
 827         switch (priv->xtal) {
 828         case SONY_XTAL_20500:
 829                 data = 0x0;
 830                 break;
 831         case SONY_XTAL_24000:
 832                 /* Select demod frequency */
 833                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 834                 data = 0x3;
 835                 break;
 836         case SONY_XTAL_41000:
 837                 cxd2841er_write_reg(priv, I2C_SLVX, 0x12, 0x00);
 838                 data = 0x1;
 839                 break;
 840         }
 841         cxd2841er_write_reg(priv, I2C_SLVX, 0x14, data);
 842         /* Clear demod SW reset */
 843         cxd2841er_write_reg(priv, I2C_SLVX, 0x10, 0x00);
 844         usleep_range(1000, 2000);
 845         /* Set SLV-T Bank : 0x00 */
 846         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 847         /* TADC Bias On */
 848         cxd2841er_write_reg(priv, I2C_SLVT, 0x43, 0x0a);
 849         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x0a);
 850         /* SADC Bias On */
 851         cxd2841er_write_reg(priv, I2C_SLVT, 0x63, 0x16);
 852         cxd2841er_write_reg(priv, I2C_SLVT, 0x65, 0x27);
 853         cxd2841er_write_reg(priv, I2C_SLVT, 0x69, 0x06);
 854         priv->state = STATE_SLEEP_TC;
 855         return 0;
 856 }
 857
 858 static int cxd2841er_tune_done(struct cxd2841er_priv *priv)
 859 {
 860         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 861         /* Set SLV-T Bank : 0x00 */
 862         cxd2841er_write_reg(priv, I2C_SLVT, 0, 0);
 863         /* SW Reset */
 864         cxd2841er_write_reg(priv, I2C_SLVT, 0xfe, 0x01);
 865         /* Enable TS output */
 866         cxd2841er_write_reg(priv, I2C_SLVT, 0xc3, 0x00);
 867         return 0;
 868 }
 869
 870 /* Set TS parallel mode */
 871 static void cxd2841er_set_ts_clock_mode(struct cxd2841er_priv *priv,
 872                                         u8 system)
 873 {
 874         u8 serial_ts, ts_rate_ctrl_off, ts_in_off;
 875
 876         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 877         /* Set SLV-T Bank : 0x00 */
 878         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
 879         cxd2841er_read_reg(priv, I2C_SLVT, 0xc4, &serial_ts);
 880         cxd2841er_read_reg(priv, I2C_SLVT, 0xd3, &ts_rate_ctrl_off);
 881         cxd2841er_read_reg(priv, I2C_SLVT, 0xde, &ts_in_off);
 882         dev_dbg(&priv->i2c->dev, "%s(): ser_ts=0x%02x rate_ctrl_off=0x%02x in_off=0x%02x\n",
 883                 __func__, serial_ts, ts_rate_ctrl_off, ts_in_off);
 884
 885         /*
 886          * slave    Bank    Addr    Bit    default    Name
 887          * <SLV-T>  00h     D9h     [7:0]  8'h08      OTSCKPERIOD
 888          */
 889         cxd2841er_write_reg(priv, I2C_SLVT, 0xd9, 0x08);
 890         /*
 891          * Disable TS IF Clock
 892          * slave    Bank    Addr    Bit    default    Name
 893          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 894          */
 895         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x00, 0x01);
 896         /*
 897          * slave    Bank    Addr    Bit    default    Name
 898          * <SLV-T>  00h     33h     [1:0]  2'b01      OREG_CKSEL_TSIF
 899          */
 900         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x33, 0x00, 0x03);
 901         /*
 902          * Enable TS IF Clock
 903          * slave    Bank    Addr    Bit    default    Name
 904          * <SLV-T>  00h     32h     [0]    1'b1       OREG_CK_TSIF_EN
 905          */
 906         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x32, 0x01, 0x01);
 907
 908         if (system == SYS_DVBT) {
 909                 /* Enable parity period for DVB-T */
 910                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 911                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 912         } else if (system == SYS_DVBC_ANNEX_A) {
 913                 /* Enable parity period for DVB-C */
 914                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
 915                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x66, 0x01, 0x01);
 916         }
 917 }
 918
 919 static u8 cxd2841er_chip_id(struct cxd2841er_priv *priv)
 920 {
 921         u8 chip_id = 0;
 922
 923         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 924         if (cxd2841er_write_reg(priv, I2C_SLVT, 0, 0) == 0)
 925                 cxd2841er_read_reg(priv, I2C_SLVT, 0xfd, &chip_id);
 926         else if (cxd2841er_write_reg(priv, I2C_SLVX, 0, 0) == 0)
 927                 cxd2841er_read_reg(priv, I2C_SLVX, 0xfd, &chip_id);
 928
 929         return chip_id;
 930 }
 931
 932 static int cxd2841er_read_status_s(struct dvb_frontend *fe,
 933                                    enum fe_status *status)
 934 {
 935         u8 reg = 0;
 936         struct cxd2841er_priv *priv = fe->demodulator_priv;
 937
 938         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 939         *status = 0;
 940         if (priv->state != STATE_ACTIVE_S) {
 941                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
 942                         __func__, priv->state);
 943                 return -EINVAL;
 944         }
 945         /* Set SLV-T Bank : 0xA0 */
 946         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
 947         /*
 948          *  slave     Bank      Addr      Bit      Signal name
 949          * <SLV-T>    A0h       11h       [2]      ITSLOCK
 950          */
 951         cxd2841er_read_reg(priv, I2C_SLVT, 0x11, &reg);
 952         if (reg & 0x04) {
 953                 *status = FE_HAS_SIGNAL
 954                         | FE_HAS_CARRIER
 955                         | FE_HAS_VITERBI
 956                         | FE_HAS_SYNC
 957                         | FE_HAS_LOCK;
 958         }
 959         dev_dbg(&priv->i2c->dev, "%s(): result 0x%x\n", __func__, *status);
 960         return 0;
 961 }
 962
 963 static int cxd2841er_read_status_t_t2(struct cxd2841er_priv *priv,
 964                                       u8 *sync, u8 *tslock, u8 *unlock)
 965 {
 966         u8 data = 0;
 967
 968         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 969         if (priv->state != STATE_ACTIVE_TC)
 970                 return -EINVAL;
 971         if (priv->system == SYS_DVBT) {
 972                 /* Set SLV-T Bank : 0x10 */
 973                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
 974         } else {
 975                 /* Set SLV-T Bank : 0x20 */
 976                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
 977         }
 978         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
 979         if ((data & 0x07) == 0x07) {
 980                 dev_dbg(&priv->i2c->dev,
 981                         "%s(): invalid hardware state detected\n", __func__);
 982                 *sync = 0;
 983                 *tslock = 0;
 984                 *unlock = 0;
 985         } else {
 986                 *sync = ((data & 0x07) == 0x6 ? 1 : 0);
 987                 *tslock = ((data & 0x20) ? 1 : 0);
 988                 *unlock = ((data & 0x10) ? 1 : 0);
 989         }
 990         return 0;
 991 }
 992
 993 static int cxd2841er_read_status_c(struct cxd2841er_priv *priv, u8 *tslock)
 994 {
 995         u8 data;
 996
 997         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
 998         if (priv->state != STATE_ACTIVE_TC)
 999                 return -EINVAL;
1000         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1001         cxd2841er_read_reg(priv, I2C_SLVT, 0x88, &data);
1002         if ((data & 0x01) == 0) {
1003                 *tslock = 0;
1004         } else {
1005                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1006                 *tslock = ((data & 0x20) ? 1 : 0);
1007         }
1008         return 0;
1009 }
1010
1011 static int cxd2841er_read_status_i(struct cxd2841er_priv *priv,
1012                 u8 *sync, u8 *tslock, u8 *unlock)
1013 {
1014         u8 data = 0;
1015
1016         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1017         if (priv->state != STATE_ACTIVE_TC)
1018                 return -EINVAL;
1019         /* Set SLV-T Bank : 0x60 */
1020         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1021         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data);
1022         dev_dbg(&priv->i2c->dev,
1023                         "%s(): lock=0x%x\n", __func__, data);
1024         *sync = ((data & 0x02) ? 1 : 0);
1025         *tslock = ((data & 0x01) ? 1 : 0);
1026         *unlock = ((data & 0x10) ? 1 : 0);
1027         return 0;
1028 }
1029
1030 static int cxd2841er_read_status_tc(struct dvb_frontend *fe,
1031                                     enum fe_status *status)
1032 {
1033         int ret = 0;
1034         u8 sync = 0;
1035         u8 tslock = 0;
1036         u8 unlock = 0;
1037         struct cxd2841er_priv *priv = fe->demodulator_priv;
1038
1039         *status = 0;
1040         if (priv->state == STATE_ACTIVE_TC) {
1041                 if (priv->system == SYS_DVBT || priv->system == SYS_DVBT2) {
1042                         ret = cxd2841er_read_status_t_t2(
1043                                 priv, &sync, &tslock, &unlock);
1044                         if (ret)
1045                                 goto done;
1046                         if (unlock)
1047                                 goto done;
1048                         if (sync)
1049                                 *status = FE_HAS_SIGNAL |
1050                                         FE_HAS_CARRIER |
1051                                         FE_HAS_VITERBI |
1052                                         FE_HAS_SYNC;
1053                         if (tslock)
1054                                 *status |= FE_HAS_LOCK;
1055                 } else if (priv->system == SYS_ISDBT) {
1056                         ret = cxd2841er_read_status_i(
1057                                         priv, &sync, &tslock, &unlock);
1058                         if (ret)
1059                                 goto done;
1060                         if (unlock)
1061                                 goto done;
1062                         if (sync)
1063                                 *status = FE_HAS_SIGNAL |
1064                                         FE_HAS_CARRIER |
1065                                         FE_HAS_VITERBI |
1066                                         FE_HAS_SYNC;
1067                         if (tslock)
1068                                 *status |= FE_HAS_LOCK;
1069                 } else if (priv->system == SYS_DVBC_ANNEX_A) {
1070                         ret = cxd2841er_read_status_c(priv, &tslock);
1071                         if (ret)
1072                                 goto done;
1073                         if (tslock)
1074                                 *status = FE_HAS_SIGNAL |
1075                                         FE_HAS_CARRIER |
1076                                         FE_HAS_VITERBI |
1077                                         FE_HAS_SYNC |
1078                                         FE_HAS_LOCK;
1079                 }
1080         }
1081 done:
1082         dev_dbg(&priv->i2c->dev, "%s(): status 0x%x\n", __func__, *status);
1083         return ret;
1084 }
1085
1086 static int cxd2841er_get_carrier_offset_s_s2(struct cxd2841er_priv *priv,
1087                                              int *offset)
1088 {
1089         u8 data[3];
1090         u8 is_hs_mode;
1091         s32 cfrl_ctrlval;
1092         s32 temp_div, temp_q, temp_r;
1093
1094         if (priv->state != STATE_ACTIVE_S) {
1095                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1096                         __func__, priv->state);
1097                 return -EINVAL;
1098         }
1099         /*
1100          * Get High Sampling Rate mode
1101          *  slave     Bank      Addr      Bit      Signal name
1102          * <SLV-T>    A0h       10h       [0]      ITRL_LOCK
1103          */
1104         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1105         cxd2841er_read_reg(priv, I2C_SLVT, 0x10, &data[0]);
1106         if (data[0] & 0x01) {
1107                 /*
1108                  *  slave     Bank      Addr      Bit      Signal name
1109                  * <SLV-T>    A0h       50h       [4]      IHSMODE
1110                  */
1111                 cxd2841er_read_reg(priv, I2C_SLVT, 0x50, &data[0]);
1112                 is_hs_mode = (data[0] & 0x10 ? 1 : 0);
1113         } else {
1114                 dev_dbg(&priv->i2c->dev,
1115                         "%s(): unable to detect sampling rate mode\n",
1116                         __func__);
1117                 return -EINVAL;
1118         }
1119         /*
1120          *  slave     Bank      Addr      Bit      Signal name
1121          * <SLV-T>    A0h       45h       [4:0]    ICFRL_CTRLVAL[20:16]
1122          * <SLV-T>    A0h       46h       [7:0]    ICFRL_CTRLVAL[15:8]
1123          * <SLV-T>    A0h       47h       [7:0]    ICFRL_CTRLVAL[7:0]
1124          */
1125         cxd2841er_read_regs(priv, I2C_SLVT, 0x45, data, 3);
1126         cfrl_ctrlval = sign_extend32((((u32)data[0] & 0x1F) << 16) |
1127                                 (((u32)data[1] & 0xFF) <<  8) |
1128                                 ((u32)data[2] & 0xFF), 20);
1129         temp_div = (is_hs_mode ? 1048576 : 1572864);
1130         if (cfrl_ctrlval > 0) {
1131                 temp_q = div_s64_rem(97375LL * cfrl_ctrlval,
1132                         temp_div, &temp_r);
1133         } else {
1134                 temp_q = div_s64_rem(-97375LL * cfrl_ctrlval,
1135                         temp_div, &temp_r);
1136         }
1137         if (temp_r >= temp_div / 2)
1138                 temp_q++;
1139         if (cfrl_ctrlval > 0)
1140                 temp_q *= -1;
1141         *offset = temp_q;
1142         return 0;
1143 }
1144
1145 static int cxd2841er_get_carrier_offset_i(struct cxd2841er_priv *priv,
1146                                            u32 bandwidth, int *offset)
1147 {
1148         u8 data[4];
1149
1150         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1151         if (priv->state != STATE_ACTIVE_TC) {
1152                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1153                         __func__, priv->state);
1154                 return -EINVAL;
1155         }
1156         if (priv->system != SYS_ISDBT) {
1157                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1158                         __func__, priv->system);
1159                 return -EINVAL;
1160         }
1161         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1162         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1163         *offset = -1 * sign_extend32(
1164                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1165                 ((u32)data[2] << 8) | (u32)data[3], 29);
1166
1167         switch (bandwidth) {
1168         case 6000000:
1169                 *offset = -1 * ((*offset) * 8/264);
1170                 break;
1171         case 7000000:
1172                 *offset = -1 * ((*offset) * 8/231);
1173                 break;
1174         case 8000000:
1175                 *offset = -1 * ((*offset) * 8/198);
1176                 break;
1177         default:
1178                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1179                                 __func__, bandwidth);
1180                 return -EINVAL;
1181         }
1182
1183         dev_dbg(&priv->i2c->dev, "%s(): bandwidth %d offset %d\n",
1184                         __func__, bandwidth, *offset);
1185
1186         return 0;
1187 }
1188
1189 static int cxd2841er_get_carrier_offset_t(struct cxd2841er_priv *priv,
1190                                            u32 bandwidth, int *offset)
1191 {
1192         u8 data[4];
1193
1194         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1195         if (priv->state != STATE_ACTIVE_TC) {
1196                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1197                         __func__, priv->state);
1198                 return -EINVAL;
1199         }
1200         if (priv->system != SYS_DVBT) {
1201                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1202                         __func__, priv->system);
1203                 return -EINVAL;
1204         }
1205         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1206         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1207         *offset = -1 * sign_extend32(
1208                 ((u32)(data[0] & 0x1F) << 24) | ((u32)data[1] << 16) |
1209                 ((u32)data[2] << 8) | (u32)data[3], 29);
1210         *offset *= (bandwidth / 1000000);
1211         *offset /= 235;
1212         return 0;
1213 }
1214
1215 static int cxd2841er_get_carrier_offset_t2(struct cxd2841er_priv *priv,
1216                                            u32 bandwidth, int *offset)
1217 {
1218         u8 data[4];
1219
1220         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1221         if (priv->state != STATE_ACTIVE_TC) {
1222                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1223                         __func__, priv->state);
1224                 return -EINVAL;
1225         }
1226         if (priv->system != SYS_DVBT2) {
1227                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1228                         __func__, priv->system);
1229                 return -EINVAL;
1230         }
1231         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1232         cxd2841er_read_regs(priv, I2C_SLVT, 0x4c, data, sizeof(data));
1233         *offset = -1 * sign_extend32(
1234                 ((u32)(data[0] & 0x0F) << 24) | ((u32)data[1] << 16) |
1235                 ((u32)data[2] << 8) | (u32)data[3], 27);
1236         switch (bandwidth) {
1237         case 1712000:
1238                 *offset /= 582;
1239                 break;
1240         case 5000000:
1241         case 6000000:
1242         case 7000000:
1243         case 8000000:
1244                 *offset *= (bandwidth / 1000000);
1245                 *offset /= 940;
1246                 break;
1247         default:
1248                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
1249                         __func__, bandwidth);
1250                 return -EINVAL;
1251         }
1252         return 0;
1253 }
1254
1255 static int cxd2841er_get_carrier_offset_c(struct cxd2841er_priv *priv,
1256                                           int *offset)
1257 {
1258         u8 data[2];
1259
1260         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1261         if (priv->state != STATE_ACTIVE_TC) {
1262                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1263                         __func__, priv->state);
1264                 return -EINVAL;
1265         }
1266         if (priv->system != SYS_DVBC_ANNEX_A) {
1267                 dev_dbg(&priv->i2c->dev, "%s(): invalid delivery system %d\n",
1268                         __func__, priv->system);
1269                 return -EINVAL;
1270         }
1271         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1272         cxd2841er_read_regs(priv, I2C_SLVT, 0x15, data, sizeof(data));
1273         *offset = div_s64(41000LL * sign_extend32((((u32)data[0] & 0x3f) << 8)
1274                                                 | (u32)data[1], 13), 16384);
1275         return 0;
1276 }
1277
1278 static int cxd2841er_read_packet_errors_c(
1279                 struct cxd2841er_priv *priv, u32 *penum)
1280 {
1281         u8 data[3];
1282
1283         *penum = 0;
1284         if (priv->state != STATE_ACTIVE_TC) {
1285                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1286                                 __func__, priv->state);
1287                 return -EINVAL;
1288         }
1289         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1290         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1291         if (data[2] & 0x01)
1292                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1293         return 0;
1294 }
1295
1296 static int cxd2841er_read_packet_errors_t(
1297                 struct cxd2841er_priv *priv, u32 *penum)
1298 {
1299         u8 data[3];
1300
1301         *penum = 0;
1302         if (priv->state != STATE_ACTIVE_TC) {
1303                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1304                         __func__, priv->state);
1305                 return -EINVAL;
1306         }
1307         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1308         cxd2841er_read_regs(priv, I2C_SLVT, 0xea, data, sizeof(data));
1309         if (data[2] & 0x01)
1310                 *penum = ((u32)data[0] << 8) | (u32)data[1];
1311         return 0;
1312 }
1313
1314 static int cxd2841er_read_packet_errors_t2(
1315                 struct cxd2841er_priv *priv, u32 *penum)
1316 {
1317         u8 data[3];
1318
1319         *penum = 0;
1320         if (priv->state != STATE_ACTIVE_TC) {
1321                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1322                         __func__, priv->state);
1323                 return -EINVAL;
1324         }
1325         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
1326         cxd2841er_read_regs(priv, I2C_SLVT, 0xfd, data, sizeof(data));
1327         if (data[0] & 0x01)
1328                 *penum = ((u32)data[1] << 8) | (u32)data[2];
1329         return 0;
1330 }
1331
1332 static int cxd2841er_read_packet_errors_i(
1333                 struct cxd2841er_priv *priv, u32 *penum)
1334 {
1335         u8 data[2];
1336
1337         *penum = 0;
1338         if (priv->state != STATE_ACTIVE_TC) {
1339                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1340                                 __func__, priv->state);
1341                 return -EINVAL;
1342         }
1343         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1344         cxd2841er_read_regs(priv, I2C_SLVT, 0xA1, data, 1);
1345
1346         if (!(data[0] & 0x01))
1347                 return 0;
1348
1349         /* Layer A */
1350         cxd2841er_read_regs(priv, I2C_SLVT, 0xA2, data, sizeof(data));
1351         *penum = ((u32)data[0] << 8) | (u32)data[1];
1352
1353         /* Layer B */
1354         cxd2841er_read_regs(priv, I2C_SLVT, 0xA4, data, sizeof(data));
1355         *penum += ((u32)data[0] << 8) | (u32)data[1];
1356
1357         /* Layer C */
1358         cxd2841er_read_regs(priv, I2C_SLVT, 0xA6, data, sizeof(data));
1359         *penum += ((u32)data[0] << 8) | (u32)data[1];
1360
1361         return 0;
1362 }
1363
1364 static int cxd2841er_read_ber_c(struct cxd2841er_priv *priv,
1365                 u32 *bit_error, u32 *bit_count)
1366 {
1367         u8 data[3];
1368         u32 bit_err, period_exp;
1369
1370         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1371         if (priv->state != STATE_ACTIVE_TC) {
1372                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1373                                 __func__, priv->state);
1374                 return -EINVAL;
1375         }
1376         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1377         cxd2841er_read_regs(priv, I2C_SLVT, 0x62, data, sizeof(data));
1378         if (!(data[0] & 0x80)) {
1379                 dev_dbg(&priv->i2c->dev,
1380                                 "%s(): no valid BER data\n", __func__);
1381                 return -EINVAL;
1382         }
1383         bit_err = ((u32)(data[0] & 0x3f) << 16) |
1384                 ((u32)data[1] << 8) |
1385                 (u32)data[2];
1386         cxd2841er_read_reg(priv, I2C_SLVT, 0x60, data);
1387         period_exp = data[0] & 0x1f;
1388
1389         if ((period_exp <= 11) && (bit_err > (1 << period_exp) * 204 * 8)) {
1390                 dev_dbg(&priv->i2c->dev,
1391                                 "%s(): period_exp(%u) or bit_err(%u)  not in range. no valid BER data\n",
1392                                 __func__, period_exp, bit_err);
1393                 return -EINVAL;
1394         }
1395
1396         dev_dbg(&priv->i2c->dev,
1397                         "%s(): period_exp(%u) or bit_err(%u) count=%d\n",
1398                         __func__, period_exp, bit_err,
1399                         ((1 << period_exp) * 204 * 8));
1400
1401         *bit_error = bit_err;
1402         *bit_count = ((1 << period_exp) * 204 * 8);
1403
1404         return 0;
1405 }
1406
1407 static int cxd2841er_read_ber_i(struct cxd2841er_priv *priv,
1408                 u32 *bit_error, u32 *bit_count)
1409 {
1410         u8 data[3];
1411         u8 pktnum[2];
1412
1413         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1414         if (priv->state != STATE_ACTIVE_TC) {
1415                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
1416                                 __func__, priv->state);
1417                 return -EINVAL;
1418         }
1419
1420         cxd2841er_freeze_regs(priv);
1421         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1422         cxd2841er_read_regs(priv, I2C_SLVT, 0x5B, pktnum, sizeof(pktnum));
1423         cxd2841er_read_regs(priv, I2C_SLVT, 0x16, data, sizeof(data));
1424
1425         if (!pktnum[0] && !pktnum[1]) {
1426                 dev_dbg(&priv->i2c->dev,
1427                                 "%s(): no valid BER data\n", __func__);
1428                 cxd2841er_unfreeze_regs(priv);
1429                 return -EINVAL;
1430         }
1431
1432         *bit_error = ((u32)(data[0] & 0x7F) << 16) |
1433                 ((u32)data[1] << 8) | data[2];
1434         *bit_count = ((((u32)pktnum[0] << 8) | pktnum[1]) * 204 * 8);
1435         dev_dbg(&priv->i2c->dev, "%s(): bit_error=%u bit_count=%u\n",
1436                         __func__, *bit_error, *bit_count);
1437
1438         cxd2841er_unfreeze_regs(priv);
1439         return 0;
1440 }
1441
1442 static int cxd2841er_mon_read_ber_s(struct cxd2841er_priv *priv,
1443                                     u32 *bit_error, u32 *bit_count)
1444 {
1445         u8 data[11];
1446
1447         /* Set SLV-T Bank : 0xA0 */
1448         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1449         /*
1450          *  slave     Bank      Addr      Bit      Signal name
1451          * <SLV-T>    A0h       35h       [0]      IFVBER_VALID
1452          * <SLV-T>    A0h       36h       [5:0]    IFVBER_BITERR[21:16]
1453          * <SLV-T>    A0h       37h       [7:0]    IFVBER_BITERR[15:8]
1454          * <SLV-T>    A0h       38h       [7:0]    IFVBER_BITERR[7:0]
1455          * <SLV-T>    A0h       3Dh       [5:0]    IFVBER_BITNUM[21:16]
1456          * <SLV-T>    A0h       3Eh       [7:0]    IFVBER_BITNUM[15:8]
1457          * <SLV-T>    A0h       3Fh       [7:0]    IFVBER_BITNUM[7:0]
1458          */
1459         cxd2841er_read_regs(priv, I2C_SLVT, 0x35, data, 11);
1460         if (data[0] & 0x01) {
1461                 *bit_error = ((u32)(data[1]  & 0x3F) << 16) |
1462                              ((u32)(data[2]  & 0xFF) <<  8) |
1463                              (u32)(data[3]  & 0xFF);
1464                 *bit_count = ((u32)(data[8]  & 0x3F) << 16) |
1465                              ((u32)(data[9]  & 0xFF) <<  8) |
1466                              (u32)(data[10] & 0xFF);
1467                 if ((*bit_count == 0) || (*bit_error > *bit_count)) {
1468                         dev_dbg(&priv->i2c->dev,
1469                                 "%s(): invalid bit_error %d, bit_count %d\n",
1470                                 __func__, *bit_error, *bit_count);
1471                         return -EINVAL;
1472                 }
1473                 return 0;
1474         }
1475         dev_dbg(&priv->i2c->dev, "%s(): no data available\n", __func__);
1476         return -EINVAL;
1477 }
1478
1479
1480 static int cxd2841er_mon_read_ber_s2(struct cxd2841er_priv *priv,
1481                                      u32 *bit_error, u32 *bit_count)
1482 {
1483         u8 data[5];
1484         u32 period;
1485
1486         /* Set SLV-T Bank : 0xB2 */
1487         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xb2);
1488         /*
1489          *  slave     Bank      Addr      Bit      Signal name
1490          * <SLV-T>    B2h       30h       [0]      IFLBER_VALID
1491          * <SLV-T>    B2h       31h       [3:0]    IFLBER_BITERR[27:24]
1492          * <SLV-T>    B2h       32h       [7:0]    IFLBER_BITERR[23:16]
1493          * <SLV-T>    B2h       33h       [7:0]    IFLBER_BITERR[15:8]
1494          * <SLV-T>    B2h       34h       [7:0]    IFLBER_BITERR[7:0]
1495          */
1496         cxd2841er_read_regs(priv, I2C_SLVT, 0x30, data, 5);
1497         if (data[0] & 0x01) {
1498                 /* Bit error count */
1499                 *bit_error = ((u32)(data[1] & 0x0F) << 24) |
1500                              ((u32)(data[2] & 0xFF) << 16) |
1501                              ((u32)(data[3] & 0xFF) <<  8) |
1502                              (u32)(data[4] & 0xFF);
1503
1504                 /* Set SLV-T Bank : 0xA0 */
1505                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1506                 cxd2841er_read_reg(priv, I2C_SLVT, 0x7a, data);
1507                 /* Measurement period */
1508                 period = (u32)(1 << (data[0] & 0x0F));
1509                 if (period == 0) {
1510                         dev_dbg(&priv->i2c->dev,
1511                                 "%s(): period is 0\n", __func__);
1512                         return -EINVAL;
1513                 }
1514                 if (*bit_error > (period * 64800)) {
1515                         dev_dbg(&priv->i2c->dev,
1516                                 "%s(): invalid bit_err 0x%x period 0x%x\n",
1517                                 __func__, *bit_error, period);
1518                         return -EINVAL;
1519                 }
1520                 *bit_count = period * 64800;
1521
1522                 return 0;
1523         } else {
1524                 dev_dbg(&priv->i2c->dev,
1525                         "%s(): no data available\n", __func__);
1526         }
1527         return -EINVAL;
1528 }
1529
1530 static int cxd2841er_read_ber_t2(struct cxd2841er_priv *priv,
1531                                  u32 *bit_error, u32 *bit_count)
1532 {
1533         u8 data[4];
1534         u32 period_exp, n_ldpc;
1535
1536         if (priv->state != STATE_ACTIVE_TC) {
1537                 dev_dbg(&priv->i2c->dev,
1538                         "%s(): invalid state %d\n", __func__, priv->state);
1539                 return -EINVAL;
1540         }
1541         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1542         cxd2841er_read_regs(priv, I2C_SLVT, 0x39, data, sizeof(data));
1543         if (!(data[0] & 0x10)) {
1544                 dev_dbg(&priv->i2c->dev,
1545                         "%s(): no valid BER data\n", __func__);
1546                 return -EINVAL;
1547         }
1548         *bit_error = ((u32)(data[0] & 0x0f) << 24) |
1549                      ((u32)data[1] << 16) |
1550                      ((u32)data[2] << 8) |
1551                      (u32)data[3];
1552         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1553         period_exp = data[0] & 0x0f;
1554         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x22);
1555         cxd2841er_read_reg(priv, I2C_SLVT, 0x5e, data);
1556         n_ldpc = ((data[0] & 0x03) == 0 ? 16200 : 64800);
1557         if (*bit_error > ((1U << period_exp) * n_ldpc)) {
1558                 dev_dbg(&priv->i2c->dev,
1559                         "%s(): invalid BER value\n", __func__);
1560                 return -EINVAL;
1561         }
1562
1563         /*
1564          * FIXME: the right thing would be to return bit_error untouched,
1565          * but, as we don't know the scale returned by the counters, let's
1566          * at least preserver BER = bit_error/bit_count.
1567          */
1568         if (period_exp >= 4) {
1569                 *bit_count = (1U << (period_exp - 4)) * (n_ldpc / 200);
1570                 *bit_error *= 3125ULL;
1571         } else {
1572                 *bit_count = (1U << period_exp) * (n_ldpc / 200);
1573                 *bit_error *= 50000ULL;
1574         }
1575         return 0;
1576 }
1577
1578 static int cxd2841er_read_ber_t(struct cxd2841er_priv *priv,
1579                                 u32 *bit_error, u32 *bit_count)
1580 {
1581         u8 data[2];
1582         u32 period;
1583
1584         if (priv->state != STATE_ACTIVE_TC) {
1585                 dev_dbg(&priv->i2c->dev,
1586                         "%s(): invalid state %d\n", __func__, priv->state);
1587                 return -EINVAL;
1588         }
1589         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1590         cxd2841er_read_reg(priv, I2C_SLVT, 0x39, data);
1591         if (!(data[0] & 0x01)) {
1592                 dev_dbg(&priv->i2c->dev,
1593                         "%s(): no valid BER data\n", __func__);
1594                 return 0;
1595         }
1596         cxd2841er_read_regs(priv, I2C_SLVT, 0x22, data, sizeof(data));
1597         *bit_error = ((u32)data[0] << 8) | (u32)data[1];
1598         cxd2841er_read_reg(priv, I2C_SLVT, 0x6f, data);
1599         period = ((data[0] & 0x07) == 0) ? 256 : (4096 << (data[0] & 0x07));
1600
1601         /*
1602          * FIXME: the right thing would be to return bit_error untouched,
1603          * but, as we don't know the scale returned by the counters, let's
1604          * at least preserver BER = bit_error/bit_count.
1605          */
1606         *bit_count = period / 128;
1607         *bit_error *= 78125ULL;
1608         return 0;
1609 }
1610
1611 static int cxd2841er_freeze_regs(struct cxd2841er_priv *priv)
1612 {
1613         /*
1614          * Freeze registers: ensure multiple separate register reads
1615          * are from the same snapshot
1616          */
1617         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x01);
1618         return 0;
1619 }
1620
1621 static int cxd2841er_unfreeze_regs(struct cxd2841er_priv *priv)
1622 {
1623         /*
1624          * un-freeze registers
1625          */
1626         cxd2841er_write_reg(priv, I2C_SLVT, 0x01, 0x00);
1627         return 0;
1628 }
1629
1630 static u32 cxd2841er_dvbs_read_snr(struct cxd2841er_priv *priv,
1631                 u8 delsys, u32 *snr)
1632 {
1633         u8 data[3];
1634         u32 res = 0, value;
1635         int min_index, max_index, index;
1636         static const struct cxd2841er_cnr_data *cn_data;
1637
1638         cxd2841er_freeze_regs(priv);
1639         /* Set SLV-T Bank : 0xA1 */
1640         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa1);
1641         /*
1642          *  slave     Bank      Addr      Bit     Signal name
1643          * <SLV-T>    A1h       10h       [0]     ICPM_QUICKRDY
1644          * <SLV-T>    A1h       11h       [4:0]   ICPM_QUICKCNDT[12:8]
1645          * <SLV-T>    A1h       12h       [7:0]   ICPM_QUICKCNDT[7:0]
1646          */
1647         cxd2841er_read_regs(priv, I2C_SLVT, 0x10, data, 3);
1648         if (data[0] & 0x01) {
1649                 value = ((u32)(data[1] & 0x1F) << 8) | (u32)(data[2] & 0xFF);
1650                 min_index = 0;
1651                 if (delsys == SYS_DVBS) {
1652                         cn_data = s_cn_data;
1653                         max_index = sizeof(s_cn_data) /
1654                                 sizeof(s_cn_data[0]) - 1;
1655                 } else {
1656                         cn_data = s2_cn_data;
1657                         max_index = sizeof(s2_cn_data) /
1658                                 sizeof(s2_cn_data[0]) - 1;
1659                 }
1660                 if (value >= cn_data[min_index].value) {
1661                         res = cn_data[min_index].cnr_x1000;
1662                         goto done;
1663                 }
1664                 if (value <= cn_data[max_index].value) {
1665                         res = cn_data[max_index].cnr_x1000;
1666                         goto done;
1667                 }
1668                 while ((max_index - min_index) > 1) {
1669                         index = (max_index + min_index) / 2;
1670                         if (value == cn_data[index].value) {
1671                                 res = cn_data[index].cnr_x1000;
1672                                 goto done;
1673                         } else if (value > cn_data[index].value)
1674                                 max_index = index;
1675                         else
1676                                 min_index = index;
1677                         if ((max_index - min_index) <= 1) {
1678                                 if (value == cn_data[max_index].value) {
1679                                         res = cn_data[max_index].cnr_x1000;
1680                                         goto done;
1681                                 } else {
1682                                         res = cn_data[min_index].cnr_x1000;
1683                                         goto done;
1684                                 }
1685                         }
1686                 }
1687         } else {
1688                 dev_dbg(&priv->i2c->dev,
1689                         "%s(): no data available\n", __func__);
1690                 cxd2841er_unfreeze_regs(priv);
1691                 return -EINVAL;
1692         }
1693 done:
1694         cxd2841er_unfreeze_regs(priv);
1695         *snr = res;
1696         return 0;
1697 }
1698
1699 static uint32_t sony_log(uint32_t x)
1700 {
1701         return (((10000>>8)*(intlog2(x)>>16) + LOG2_E_100X/2)/LOG2_E_100X);
1702 }
1703
1704 static int cxd2841er_read_snr_c(struct cxd2841er_priv *priv, u32 *snr)
1705 {
1706         u32 reg;
1707         u8 data[2];
1708         enum sony_dvbc_constellation_t qam = SONY_DVBC_CONSTELLATION_16QAM;
1709
1710         *snr = 0;
1711         if (priv->state != STATE_ACTIVE_TC) {
1712                 dev_dbg(&priv->i2c->dev,
1713                                 "%s(): invalid state %d\n",
1714                                 __func__, priv->state);
1715                 return -EINVAL;
1716         }
1717
1718         cxd2841er_freeze_regs(priv);
1719         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
1720         cxd2841er_read_regs(priv, I2C_SLVT, 0x19, data, 1);
1721         qam = (enum sony_dvbc_constellation_t) (data[0] & 0x07);
1722         cxd2841er_read_regs(priv, I2C_SLVT, 0x4C, data, 2);
1723
1724         reg = ((u32)(data[0]&0x1f) << 8) | (u32)data[1];
1725         if (reg == 0) {
1726                 dev_dbg(&priv->i2c->dev,
1727                                 "%s(): reg value out of range\n", __func__);
1728                 cxd2841er_unfreeze_regs(priv);
1729                 return 0;
1730         }
1731
1732         switch (qam) {
1733         case SONY_DVBC_CONSTELLATION_16QAM:
1734         case SONY_DVBC_CONSTELLATION_64QAM:
1735         case SONY_DVBC_CONSTELLATION_256QAM:
1736                 /* SNR(dB) = -9.50 * ln(IREG_SNR_ESTIMATE / (24320)) */
1737                 if (reg < 126)
1738                         reg = 126;
1739                 *snr = -95 * (int32_t)sony_log(reg) + 95941;
1740                 break;
1741         case SONY_DVBC_CONSTELLATION_32QAM:
1742         case SONY_DVBC_CONSTELLATION_128QAM:
1743                 /* SNR(dB) = -8.75 * ln(IREG_SNR_ESTIMATE / (20800)) */
1744                 if (reg < 69)
1745                         reg = 69;
1746                 *snr = -88 * (int32_t)sony_log(reg) + 86999;
1747                 break;
1748         default:
1749                 cxd2841er_unfreeze_regs(priv);
1750                 return -EINVAL;
1751         }
1752
1753         cxd2841er_unfreeze_regs(priv);
1754         return 0;
1755 }
1756
1757 static int cxd2841er_read_snr_t(struct cxd2841er_priv *priv, u32 *snr)
1758 {
1759         u32 reg;
1760         u8 data[2];
1761
1762         *snr = 0;
1763         if (priv->state != STATE_ACTIVE_TC) {
1764                 dev_dbg(&priv->i2c->dev,
1765                         "%s(): invalid state %d\n", __func__, priv->state);
1766                 return -EINVAL;
1767         }
1768
1769         cxd2841er_freeze_regs(priv);
1770         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
1771         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1772         reg = ((u32)data[0] << 8) | (u32)data[1];
1773         if (reg == 0) {
1774                 dev_dbg(&priv->i2c->dev,
1775                         "%s(): reg value out of range\n", __func__);
1776                 cxd2841er_unfreeze_regs(priv);
1777                 return 0;
1778         }
1779         if (reg > 4996)
1780                 reg = 4996;
1781         *snr = 10000 * ((intlog10(reg) - intlog10(5350 - reg)) >> 24) + 28500;
1782         cxd2841er_unfreeze_regs(priv);
1783         return 0;
1784 }
1785
1786 static int cxd2841er_read_snr_t2(struct cxd2841er_priv *priv, u32 *snr)
1787 {
1788         u32 reg;
1789         u8 data[2];
1790
1791         *snr = 0;
1792         if (priv->state != STATE_ACTIVE_TC) {
1793                 dev_dbg(&priv->i2c->dev,
1794                         "%s(): invalid state %d\n", __func__, priv->state);
1795                 return -EINVAL;
1796         }
1797
1798         cxd2841er_freeze_regs(priv);
1799         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
1800         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1801         reg = ((u32)data[0] << 8) | (u32)data[1];
1802         if (reg == 0) {
1803                 dev_dbg(&priv->i2c->dev,
1804                         "%s(): reg value out of range\n", __func__);
1805                 cxd2841er_unfreeze_regs(priv);
1806                 return 0;
1807         }
1808         if (reg > 10876)
1809                 reg = 10876;
1810         *snr = 10000 * ((intlog10(reg) -
1811                 intlog10(12600 - reg)) >> 24) + 32000;
1812         cxd2841er_unfreeze_regs(priv);
1813         return 0;
1814 }
1815
1816 static int cxd2841er_read_snr_i(struct cxd2841er_priv *priv, u32 *snr)
1817 {
1818         u32 reg;
1819         u8 data[2];
1820
1821         *snr = 0;
1822         if (priv->state != STATE_ACTIVE_TC) {
1823                 dev_dbg(&priv->i2c->dev,
1824                                 "%s(): invalid state %d\n", __func__,
1825                                 priv->state);
1826                 return -EINVAL;
1827         }
1828
1829         cxd2841er_freeze_regs(priv);
1830         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
1831         cxd2841er_read_regs(priv, I2C_SLVT, 0x28, data, sizeof(data));
1832         reg = ((u32)data[0] << 8) | (u32)data[1];
1833         if (reg == 0) {
1834                 dev_dbg(&priv->i2c->dev,
1835                                 "%s(): reg value out of range\n", __func__);
1836                 cxd2841er_unfreeze_regs(priv);
1837                 return 0;
1838         }
1839         *snr = 10000 * (intlog10(reg) >> 24) - 9031;
1840         cxd2841er_unfreeze_regs(priv);
1841         return 0;
1842 }
1843
1844 static u16 cxd2841er_read_agc_gain_c(struct cxd2841er_priv *priv,
1845                                         u8 delsys)
1846 {
1847         u8 data[2];
1848
1849         cxd2841er_write_reg(
1850                 priv, I2C_SLVT, 0x00, 0x40);
1851         cxd2841er_read_regs(priv, I2C_SLVT, 0x49, data, 2);
1852         dev_dbg(&priv->i2c->dev,
1853                         "%s(): AGC value=%u\n",
1854                         __func__, (((u16)data[0] & 0x0F) << 8) |
1855                         (u16)(data[1] & 0xFF));
1856         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1857 }
1858
1859 static u16 cxd2841er_read_agc_gain_t_t2(struct cxd2841er_priv *priv,
1860                                         u8 delsys)
1861 {
1862         u8 data[2];
1863
1864         cxd2841er_write_reg(
1865                 priv, I2C_SLVT, 0x00, (delsys == SYS_DVBT ? 0x10 : 0x20));
1866         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1867         dev_dbg(&priv->i2c->dev,
1868                         "%s(): AGC value=%u\n",
1869                         __func__, (((u16)data[0] & 0x0F) << 8) |
1870                         (u16)(data[1] & 0xFF));
1871         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1872 }
1873
1874 static u16 cxd2841er_read_agc_gain_i(struct cxd2841er_priv *priv,
1875                 u8 delsys)
1876 {
1877         u8 data[2];
1878
1879         cxd2841er_write_reg(
1880                         priv, I2C_SLVT, 0x00, 0x60);
1881         cxd2841er_read_regs(priv, I2C_SLVT, 0x26, data, 2);
1882
1883         dev_dbg(&priv->i2c->dev,
1884                         "%s(): AGC value=%u\n",
1885                         __func__, (((u16)data[0] & 0x0F) << 8) |
1886                         (u16)(data[1] & 0xFF));
1887         return ((((u16)data[0] & 0x0F) << 8) | (u16)(data[1] & 0xFF)) << 4;
1888 }
1889
1890 static u16 cxd2841er_read_agc_gain_s(struct cxd2841er_priv *priv)
1891 {
1892         u8 data[2];
1893
1894         /* Set SLV-T Bank : 0xA0 */
1895         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
1896         /*
1897          *  slave     Bank      Addr      Bit       Signal name
1898          * <SLV-T>    A0h       1Fh       [4:0]     IRFAGC_GAIN[12:8]
1899          * <SLV-T>    A0h       20h       [7:0]     IRFAGC_GAIN[7:0]
1900          */
1901         cxd2841er_read_regs(priv, I2C_SLVT, 0x1f, data, 2);
1902         return ((((u16)data[0] & 0x1F) << 8) | (u16)(data[1] & 0xFF)) << 3;
1903 }
1904
1905 static void cxd2841er_read_ber(struct dvb_frontend *fe)
1906 {
1907         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1908         struct cxd2841er_priv *priv = fe->demodulator_priv;
1909         u32 ret, bit_error = 0, bit_count = 0;
1910
1911         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1912         switch (p->delivery_system) {
1913         case SYS_DVBC_ANNEX_A:
1914         case SYS_DVBC_ANNEX_B:
1915         case SYS_DVBC_ANNEX_C:
1916                 ret = cxd2841er_read_ber_c(priv, &bit_error, &bit_count);
1917                 break;
1918         case SYS_ISDBT:
1919                 ret = cxd2841er_read_ber_i(priv, &bit_error, &bit_count);
1920                 break;
1921         case SYS_DVBS:
1922                 ret = cxd2841er_mon_read_ber_s(priv, &bit_error, &bit_count);
1923                 break;
1924         case SYS_DVBS2:
1925                 ret = cxd2841er_mon_read_ber_s2(priv, &bit_error, &bit_count);
1926                 break;
1927         case SYS_DVBT:
1928                 ret = cxd2841er_read_ber_t(priv, &bit_error, &bit_count);
1929                 break;
1930         case SYS_DVBT2:
1931                 ret = cxd2841er_read_ber_t2(priv, &bit_error, &bit_count);
1932                 break;
1933         default:
1934                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1935                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1936                 return;
1937         }
1938
1939         if (!ret) {
1940                 p->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
1941                 p->post_bit_error.stat[0].uvalue += bit_error;
1942                 p->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
1943                 p->post_bit_count.stat[0].uvalue += bit_count;
1944         } else {
1945                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1946                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1947         }
1948 }
1949
1950 static void cxd2841er_read_signal_strength(struct dvb_frontend *fe)
1951 {
1952         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
1953         struct cxd2841er_priv *priv = fe->demodulator_priv;
1954         s32 strength;
1955
1956         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
1957         switch (p->delivery_system) {
1958         case SYS_DVBT:
1959         case SYS_DVBT2:
1960                 strength = cxd2841er_read_agc_gain_t_t2(priv,
1961                                                         p->delivery_system);
1962                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1963                 /* Formula was empirically determinated @ 410 MHz */
1964                 p->strength.stat[0].uvalue = strength * 366 / 100 - 89520;
1965                 break;  /* Code moved out of the function */
1966         case SYS_DVBC_ANNEX_A:
1967         case SYS_DVBC_ANNEX_B:
1968         case SYS_DVBC_ANNEX_C:
1969                 strength = cxd2841er_read_agc_gain_c(priv,
1970                                                         p->delivery_system);
1971                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1972                 /*
1973                  * Formula was empirically determinated via linear regression,
1974                  * using frequencies: 175 MHz, 410 MHz and 800 MHz, and a
1975                  * stream modulated with QAM64
1976                  */
1977                 p->strength.stat[0].uvalue = strength * 4045 / 1000 - 85224;
1978                 break;
1979         case SYS_ISDBT:
1980                 strength = cxd2841er_read_agc_gain_i(priv, p->delivery_system);
1981                 p->strength.stat[0].scale = FE_SCALE_DECIBEL;
1982                 /*
1983                  * Formula was empirically determinated via linear regression,
1984                  * using frequencies: 175 MHz, 410 MHz and 800 MHz.
1985                  */
1986                 p->strength.stat[0].uvalue = strength * 3775 / 1000 - 90185;
1987                 break;
1988         case SYS_DVBS:
1989         case SYS_DVBS2:
1990                 strength = 65535 - cxd2841er_read_agc_gain_s(priv);
1991                 p->strength.stat[0].scale = FE_SCALE_RELATIVE;
1992                 p->strength.stat[0].uvalue = strength;
1993                 break;
1994         default:
1995                 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1996                 break;
1997         }
1998 }
1999
2000 static void cxd2841er_read_snr(struct dvb_frontend *fe)
2001 {
2002         u32 tmp = 0;
2003         int ret = 0;
2004         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2005         struct cxd2841er_priv *priv = fe->demodulator_priv;
2006
2007         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2008         switch (p->delivery_system) {
2009         case SYS_DVBC_ANNEX_A:
2010         case SYS_DVBC_ANNEX_B:
2011         case SYS_DVBC_ANNEX_C:
2012                 ret = cxd2841er_read_snr_c(priv, &tmp);
2013                 break;
2014         case SYS_DVBT:
2015                 ret = cxd2841er_read_snr_t(priv, &tmp);
2016                 break;
2017         case SYS_DVBT2:
2018                 ret = cxd2841er_read_snr_t2(priv, &tmp);
2019                 break;
2020         case SYS_ISDBT:
2021                 ret = cxd2841er_read_snr_i(priv, &tmp);
2022                 break;
2023         case SYS_DVBS:
2024         case SYS_DVBS2:
2025                 ret = cxd2841er_dvbs_read_snr(priv, p->delivery_system, &tmp);
2026                 break;
2027         default:
2028                 dev_dbg(&priv->i2c->dev, "%s(): unknown delivery system %d\n",
2029                         __func__, p->delivery_system);
2030                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2031                 return;
2032         }
2033
2034         dev_dbg(&priv->i2c->dev, "%s(): snr=%d\n",
2035                         __func__, (int32_t)tmp);
2036
2037         if (!ret) {
2038                 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;
2039                 p->cnr.stat[0].svalue = tmp;
2040         } else {
2041                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2042         }
2043 }
2044
2045 static void cxd2841er_read_ucblocks(struct dvb_frontend *fe)
2046 {
2047         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
2048         struct cxd2841er_priv *priv = fe->demodulator_priv;
2049         u32 ucblocks = 0;
2050
2051         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2052         switch (p->delivery_system) {
2053         case SYS_DVBC_ANNEX_A:
2054         case SYS_DVBC_ANNEX_B:
2055         case SYS_DVBC_ANNEX_C:
2056                 cxd2841er_read_packet_errors_c(priv, &ucblocks);
2057                 break;
2058         case SYS_DVBT:
2059                 cxd2841er_read_packet_errors_t(priv, &ucblocks);
2060                 break;
2061         case SYS_DVBT2:
2062                 cxd2841er_read_packet_errors_t2(priv, &ucblocks);
2063                 break;
2064         case SYS_ISDBT:
2065                 cxd2841er_read_packet_errors_i(priv, &ucblocks);
2066                 break;
2067         default:
2068                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
2069                 return;
2070         }
2071         dev_dbg(&priv->i2c->dev, "%s() ucblocks=%u\n", __func__, ucblocks);
2072
2073         p->block_error.stat[0].scale = FE_SCALE_COUNTER;
2074         p->block_error.stat[0].uvalue = ucblocks;
2075 }
2076
2077 static int cxd2841er_dvbt2_set_profile(
2078         struct cxd2841er_priv *priv, enum cxd2841er_dvbt2_profile_t profile)
2079 {
2080         u8 tune_mode;
2081         u8 seq_not2d_time;
2082
2083         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2084         switch (profile) {
2085         case DVBT2_PROFILE_BASE:
2086                 tune_mode = 0x01;
2087                 /* Set early unlock time */
2088                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x0E:0x0C;
2089                 break;
2090         case DVBT2_PROFILE_LITE:
2091                 tune_mode = 0x05;
2092                 /* Set early unlock time */
2093                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2094                 break;
2095         case DVBT2_PROFILE_ANY:
2096                 tune_mode = 0x00;
2097                 /* Set early unlock time */
2098                 seq_not2d_time = (priv->xtal == SONY_XTAL_24000)?0x2E:0x28;
2099                 break;
2100         default:
2101                 return -EINVAL;
2102         }
2103         /* Set SLV-T Bank : 0x2E */
2104         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2e);
2105         /* Set profile and tune mode */
2106         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x10, tune_mode, 0x07);
2107         /* Set SLV-T Bank : 0x2B */
2108         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2109         /* Set early unlock detection time */
2110         cxd2841er_write_reg(priv, I2C_SLVT, 0x9d, seq_not2d_time);
2111         return 0;
2112 }
2113
2114 static int cxd2841er_dvbt2_set_plp_config(struct cxd2841er_priv *priv,
2115                                           u8 is_auto, u8 plp_id)
2116 {
2117         if (is_auto) {
2118                 dev_dbg(&priv->i2c->dev,
2119                         "%s() using auto PLP selection\n", __func__);
2120         } else {
2121                 dev_dbg(&priv->i2c->dev,
2122                         "%s() using manual PLP selection, ID %d\n",
2123                         __func__, plp_id);
2124         }
2125         /* Set SLV-T Bank : 0x23 */
2126         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2127         if (!is_auto) {
2128                 /* Manual PLP selection mode. Set the data PLP Id. */
2129                 cxd2841er_write_reg(priv, I2C_SLVT, 0xaf, plp_id);
2130         }
2131         /* Auto PLP select (Scanning mode = 0x00). Data PLP select = 0x01. */
2132         cxd2841er_write_reg(priv, I2C_SLVT, 0xad, (is_auto ? 0x00 : 0x01));
2133         return 0;
2134 }
2135
2136 static int cxd2841er_sleep_tc_to_active_t2_band(struct cxd2841er_priv *priv,
2137                                                 u32 bandwidth)
2138 {
2139         u32 iffreq;
2140         u8 data[MAX_WRITE_REGSIZE];
2141
2142         const uint8_t nominalRate8bw[3][5] = {
2143                 /* TRCG Nominal Rate [37:0] */
2144                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2145                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2146                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2147         };
2148
2149         const uint8_t nominalRate7bw[3][5] = {
2150                 /* TRCG Nominal Rate [37:0] */
2151                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2152                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2153                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2154         };
2155
2156         const uint8_t nominalRate6bw[3][5] = {
2157                 /* TRCG Nominal Rate [37:0] */
2158                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2159                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2160                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2161         };
2162
2163         const uint8_t nominalRate5bw[3][5] = {
2164                 /* TRCG Nominal Rate [37:0] */
2165                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2166                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2167                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2168         };
2169
2170         const uint8_t nominalRate17bw[3][5] = {
2171                 /* TRCG Nominal Rate [37:0] */
2172                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}, /* 20.5MHz XTal */
2173                 {0x68, 0x0F, 0xA2, 0x32, 0xD0}, /* 24MHz XTal */
2174                 {0x58, 0xE2, 0xAF, 0xE0, 0xBC}  /* 41MHz XTal */
2175         };
2176
2177         const uint8_t itbCoef8bw[3][14] = {
2178                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2179                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2180                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1,
2181                         0x29, 0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2182                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA,
2183                         0x23, 0xA9, 0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2184         };
2185
2186         const uint8_t itbCoef7bw[3][14] = {
2187                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2188                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2189                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0,
2190                         0x29, 0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2191                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6,
2192                         0x29, 0xB0, 0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2193         };
2194
2195         const uint8_t itbCoef6bw[3][14] = {
2196                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2197                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2198                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2199                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2200                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2201                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2202         };
2203
2204         const uint8_t itbCoef5bw[3][14] = {
2205                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2206                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2207                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E,
2208                         0x29, 0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2209                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2210                         0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2211         };
2212
2213         const uint8_t itbCoef17bw[3][14] = {
2214                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2215                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}, /* 20.5MHz XTal */
2216                 {0x33, 0x8E, 0x2B, 0x97, 0x2D, 0x95, 0x37, 0x8B,
2217                         0x30, 0x97, 0x2D, 0x9A, 0x21, 0xA4}, /* 24MHz XTal   */
2218                 {0x25, 0xA0, 0x36, 0x8D, 0x2E, 0x94, 0x28, 0x9B,
2219                         0x32, 0x90, 0x2C, 0x9D, 0x29, 0x99}  /* 41MHz XTal   */
2220         };
2221
2222         /* Set SLV-T Bank : 0x20 */
2223         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2224
2225         switch (bandwidth) {
2226         case 8000000:
2227                 /* <Timing Recovery setting> */
2228                 cxd2841er_write_regs(priv, I2C_SLVT,
2229                                 0x9F, nominalRate8bw[priv->xtal], 5);
2230
2231                 /* Set SLV-T Bank : 0x27 */
2232                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2233                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2234                                 0x7a, 0x00, 0x0f);
2235
2236                 /* Set SLV-T Bank : 0x10 */
2237                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2238
2239                 /* Group delay equaliser settings for
2240                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2241                  */
2242                 cxd2841er_write_regs(priv, I2C_SLVT,
2243                                 0xA6, itbCoef8bw[priv->xtal], 14);
2244                 /* <IF freq setting> */
2245                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2246                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2247                 data[1] = (u8)((iffreq >> 8) & 0xff);
2248                 data[2] = (u8)(iffreq & 0xff);
2249                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2250                 /* System bandwidth setting */
2251                 cxd2841er_set_reg_bits(
2252                                 priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2253                 break;
2254         case 7000000:
2255                 /* <Timing Recovery setting> */
2256                 cxd2841er_write_regs(priv, I2C_SLVT,
2257                                 0x9F, nominalRate7bw[priv->xtal], 5);
2258
2259                 /* Set SLV-T Bank : 0x27 */
2260                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2261                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2262                                 0x7a, 0x00, 0x0f);
2263
2264                 /* Set SLV-T Bank : 0x10 */
2265                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2266
2267                 /* Group delay equaliser settings for
2268                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2269                  */
2270                 cxd2841er_write_regs(priv, I2C_SLVT,
2271                                 0xA6, itbCoef7bw[priv->xtal], 14);
2272                 /* <IF freq setting> */
2273                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2274                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2275                 data[1] = (u8)((iffreq >> 8) & 0xff);
2276                 data[2] = (u8)(iffreq & 0xff);
2277                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2278                 /* System bandwidth setting */
2279                 cxd2841er_set_reg_bits(
2280                                 priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2281                 break;
2282         case 6000000:
2283                 /* <Timing Recovery setting> */
2284                 cxd2841er_write_regs(priv, I2C_SLVT,
2285                                 0x9F, nominalRate6bw[priv->xtal], 5);
2286
2287                 /* Set SLV-T Bank : 0x27 */
2288                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2289                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2290                                 0x7a, 0x00, 0x0f);
2291
2292                 /* Set SLV-T Bank : 0x10 */
2293                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2294
2295                 /* Group delay equaliser settings for
2296                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2297                  */
2298                 cxd2841er_write_regs(priv, I2C_SLVT,
2299                                 0xA6, itbCoef6bw[priv->xtal], 14);
2300                 /* <IF freq setting> */
2301                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2302                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2303                 data[1] = (u8)((iffreq >> 8) & 0xff);
2304                 data[2] = (u8)(iffreq & 0xff);
2305                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2306                 /* System bandwidth setting */
2307                 cxd2841er_set_reg_bits(
2308                                 priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2309                 break;
2310         case 5000000:
2311                 /* <Timing Recovery setting> */
2312                 cxd2841er_write_regs(priv, I2C_SLVT,
2313                                 0x9F, nominalRate5bw[priv->xtal], 5);
2314
2315                 /* Set SLV-T Bank : 0x27 */
2316                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2317                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2318                                 0x7a, 0x00, 0x0f);
2319
2320                 /* Set SLV-T Bank : 0x10 */
2321                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2322
2323                 /* Group delay equaliser settings for
2324                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2325                  */
2326                 cxd2841er_write_regs(priv, I2C_SLVT,
2327                                 0xA6, itbCoef5bw[priv->xtal], 14);
2328                 /* <IF freq setting> */
2329                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2330                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2331                 data[1] = (u8)((iffreq >> 8) & 0xff);
2332                 data[2] = (u8)(iffreq & 0xff);
2333                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2334                 /* System bandwidth setting */
2335                 cxd2841er_set_reg_bits(
2336                                 priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2337                 break;
2338         case 1712000:
2339                 /* <Timing Recovery setting> */
2340                 cxd2841er_write_regs(priv, I2C_SLVT,
2341                                 0x9F, nominalRate17bw[priv->xtal], 5);
2342
2343                 /* Set SLV-T Bank : 0x27 */
2344                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
2345                 cxd2841er_set_reg_bits(priv, I2C_SLVT,
2346                                 0x7a, 0x03, 0x0f);
2347
2348                 /* Set SLV-T Bank : 0x10 */
2349                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2350
2351                 /* Group delay equaliser settings for
2352                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2353                  */
2354                 cxd2841er_write_regs(priv, I2C_SLVT,
2355                                 0xA6, itbCoef17bw[priv->xtal], 14);
2356                 /* <IF freq setting> */
2357                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.50);
2358                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2359                 data[1] = (u8)((iffreq >> 8) & 0xff);
2360                 data[2] = (u8)(iffreq & 0xff);
2361                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2362                 /* System bandwidth setting */
2363                 cxd2841er_set_reg_bits(
2364                                 priv, I2C_SLVT, 0xD7, 0x03, 0x07);
2365                 break;
2366         default:
2367                 return -EINVAL;
2368         }
2369         return 0;
2370 }
2371
2372 static int cxd2841er_sleep_tc_to_active_t_band(
2373                 struct cxd2841er_priv *priv, u32 bandwidth)
2374 {
2375         u8 data[MAX_WRITE_REGSIZE];
2376         u32 iffreq;
2377         u8 nominalRate8bw[3][5] = {
2378                 /* TRCG Nominal Rate [37:0] */
2379                 {0x11, 0xF0, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2380                 {0x15, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2381                 {0x11, 0xF0, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2382         };
2383         u8 nominalRate7bw[3][5] = {
2384                 /* TRCG Nominal Rate [37:0] */
2385                 {0x14, 0x80, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2386                 {0x18, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2387                 {0x14, 0x80, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2388         };
2389         u8 nominalRate6bw[3][5] = {
2390                 /* TRCG Nominal Rate [37:0] */
2391                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}, /* 20.5MHz XTal */
2392                 {0x1C, 0x00, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2393                 {0x17, 0xEA, 0xAA, 0xAA, 0xAA}  /* 41MHz XTal */
2394         };
2395         u8 nominalRate5bw[3][5] = {
2396                 /* TRCG Nominal Rate [37:0] */
2397                 {0x1C, 0xB3, 0x33, 0x33, 0x33}, /* 20.5MHz XTal */
2398                 {0x21, 0x99, 0x99, 0x99, 0x99}, /* 24MHz XTal */
2399                 {0x1C, 0xB3, 0x33, 0x33, 0x33}  /* 41MHz XTal */
2400         };
2401
2402         u8 itbCoef8bw[3][14] = {
2403                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2404                         0x1F, 0xA8, 0x2C, 0xC8}, /* 20.5MHz XTal */
2405                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29, 0xA5,
2406                         0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz XTal   */
2407                 {0x26, 0xAF, 0x06, 0xCD, 0x13, 0xBB, 0x28, 0xBA, 0x23, 0xA9,
2408                         0x1F, 0xA8, 0x2C, 0xC8}  /* 41MHz XTal   */
2409         };
2410         u8 itbCoef7bw[3][14] = {
2411                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2412                         0x26, 0xA9, 0x21, 0xA5}, /* 20.5MHz XTal */
2413                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29, 0xA2,
2414                         0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz XTal   */
2415                 {0x2C, 0xBD, 0x02, 0xCF, 0x04, 0xF8, 0x23, 0xA6, 0x29, 0xB0,
2416                         0x26, 0xA9, 0x21, 0xA5}  /* 41MHz XTal   */
2417         };
2418         u8 itbCoef6bw[3][14] = {
2419                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2420                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2421                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2422                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2423                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2424                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2425         };
2426         u8 itbCoef5bw[3][14] = {
2427                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2428                         0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2429                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29, 0xA4,
2430                         0x29, 0xA2, 0x29, 0xA8}, /* 24MHz XTal   */
2431                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00, 0xCF,
2432                         0x00, 0xE6, 0x23, 0xA4}  /* 41MHz XTal   */
2433         };
2434
2435         /* Set SLV-T Bank : 0x13 */
2436         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2437         /* Echo performance optimization setting */
2438         data[0] = 0x01;
2439         data[1] = 0x14;
2440         cxd2841er_write_regs(priv, I2C_SLVT, 0x9C, data, 2);
2441
2442         /* Set SLV-T Bank : 0x10 */
2443         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2444
2445         switch (bandwidth) {
2446         case 8000000:
2447                 /* <Timing Recovery setting> */
2448                 cxd2841er_write_regs(priv, I2C_SLVT,
2449                                 0x9F, nominalRate8bw[priv->xtal], 5);
2450                 /* Group delay equaliser settings for
2451                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2452                 */
2453                 cxd2841er_write_regs(priv, I2C_SLVT,
2454                                 0xA6, itbCoef8bw[priv->xtal], 14);
2455                 /* <IF freq setting> */
2456                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.80);
2457                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2458                 data[1] = (u8)((iffreq >> 8) & 0xff);
2459                 data[2] = (u8)(iffreq & 0xff);
2460                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2461                 /* System bandwidth setting */
2462                 cxd2841er_set_reg_bits(
2463                         priv, I2C_SLVT, 0xD7, 0x00, 0x07);
2464
2465                 /* Demod core latency setting */
2466                 if (priv->xtal == SONY_XTAL_24000) {
2467                         data[0] = 0x15;
2468                         data[1] = 0x28;
2469                 } else {
2470                         data[0] = 0x01;
2471                         data[1] = 0xE0;
2472                 }
2473                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2474
2475                 /* Notch filter setting */
2476                 data[0] = 0x01;
2477                 data[1] = 0x02;
2478                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2479                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2480                 break;
2481         case 7000000:
2482                 /* <Timing Recovery setting> */
2483                 cxd2841er_write_regs(priv, I2C_SLVT,
2484                                 0x9F, nominalRate7bw[priv->xtal], 5);
2485                 /* Group delay equaliser settings for
2486                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2487                 */
2488                 cxd2841er_write_regs(priv, I2C_SLVT,
2489                                 0xA6, itbCoef7bw[priv->xtal], 14);
2490                 /* <IF freq setting> */
2491                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.20);
2492                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2493                 data[1] = (u8)((iffreq >> 8) & 0xff);
2494                 data[2] = (u8)(iffreq & 0xff);
2495                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2496                 /* System bandwidth setting */
2497                 cxd2841er_set_reg_bits(
2498                         priv, I2C_SLVT, 0xD7, 0x02, 0x07);
2499
2500                 /* Demod core latency setting */
2501                 if (priv->xtal == SONY_XTAL_24000) {
2502                         data[0] = 0x1F;
2503                         data[1] = 0xF8;
2504                 } else {
2505                         data[0] = 0x12;
2506                         data[1] = 0xF8;
2507                 }
2508                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2509
2510                 /* Notch filter setting */
2511                 data[0] = 0x00;
2512                 data[1] = 0x03;
2513                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2514                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2515                 break;
2516         case 6000000:
2517                 /* <Timing Recovery setting> */
2518                 cxd2841er_write_regs(priv, I2C_SLVT,
2519                                 0x9F, nominalRate6bw[priv->xtal], 5);
2520                 /* Group delay equaliser settings for
2521                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2522                 */
2523                 cxd2841er_write_regs(priv, I2C_SLVT,
2524                                 0xA6, itbCoef6bw[priv->xtal], 14);
2525                 /* <IF freq setting> */
2526                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2527                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2528                 data[1] = (u8)((iffreq >> 8) & 0xff);
2529                 data[2] = (u8)(iffreq & 0xff);
2530                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2531                 /* System bandwidth setting */
2532                 cxd2841er_set_reg_bits(
2533                         priv, I2C_SLVT, 0xD7, 0x04, 0x07);
2534
2535                 /* Demod core latency setting */
2536                 if (priv->xtal == SONY_XTAL_24000) {
2537                         data[0] = 0x25;
2538                         data[1] = 0x4C;
2539                 } else {
2540                         data[0] = 0x1F;
2541                         data[1] = 0xDC;
2542                 }
2543                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2544
2545                 /* Notch filter setting */
2546                 data[0] = 0x00;
2547                 data[1] = 0x03;
2548                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2549                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2550                 break;
2551         case 5000000:
2552                 /* <Timing Recovery setting> */
2553                 cxd2841er_write_regs(priv, I2C_SLVT,
2554                                 0x9F, nominalRate5bw[priv->xtal], 5);
2555                 /* Group delay equaliser settings for
2556                  * ASCOT2D, ASCOT2E and ASCOT3 tuners
2557                 */
2558                 cxd2841er_write_regs(priv, I2C_SLVT,
2559                                 0xA6, itbCoef5bw[priv->xtal], 14);
2560                 /* <IF freq setting> */
2561                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.60);
2562                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2563                 data[1] = (u8)((iffreq >> 8) & 0xff);
2564                 data[2] = (u8)(iffreq & 0xff);
2565                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2566                 /* System bandwidth setting */
2567                 cxd2841er_set_reg_bits(
2568                         priv, I2C_SLVT, 0xD7, 0x06, 0x07);
2569
2570                 /* Demod core latency setting */
2571                 if (priv->xtal == SONY_XTAL_24000) {
2572                         data[0] = 0x2C;
2573                         data[1] = 0xC2;
2574                 } else {
2575                         data[0] = 0x26;
2576                         data[1] = 0x3C;
2577                 }
2578                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2579
2580                 /* Notch filter setting */
2581                 data[0] = 0x00;
2582                 data[1] = 0x03;
2583                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x17);
2584                 cxd2841er_write_regs(priv, I2C_SLVT, 0x38, data, 2);
2585                 break;
2586         }
2587
2588         return 0;
2589 }
2590
2591 static int cxd2841er_sleep_tc_to_active_i_band(
2592                 struct cxd2841er_priv *priv, u32 bandwidth)
2593 {
2594         u32 iffreq;
2595         u8 data[3];
2596
2597         /* TRCG Nominal Rate */
2598         u8 nominalRate8bw[3][5] = {
2599                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2600                 {0x11, 0xB8, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2601                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2602         };
2603
2604         u8 nominalRate7bw[3][5] = {
2605                 {0x00, 0x00, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2606                 {0x14, 0x40, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2607                 {0x00, 0x00, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2608         };
2609
2610         u8 nominalRate6bw[3][5] = {
2611                 {0x14, 0x2E, 0x00, 0x00, 0x00}, /* 20.5MHz XTal */
2612                 {0x17, 0xA0, 0x00, 0x00, 0x00}, /* 24MHz XTal */
2613                 {0x14, 0x2E, 0x00, 0x00, 0x00}  /* 41MHz XTal */
2614         };
2615
2616         u8 itbCoef8bw[3][14] = {
2617                 {0x00}, /* 20.5MHz XTal */
2618                 {0x2F, 0xBA, 0x28, 0x9B, 0x28, 0x9D, 0x28, 0xA1, 0x29,
2619                         0xA5, 0x2A, 0xAC, 0x29, 0xB5}, /* 24MHz Xtal */
2620                 {0x0}, /* 41MHz XTal   */
2621         };
2622
2623         u8 itbCoef7bw[3][14] = {
2624                 {0x00}, /* 20.5MHz XTal */
2625                 {0x30, 0xB1, 0x29, 0x9A, 0x28, 0x9C, 0x28, 0xA0, 0x29,
2626                         0xA2, 0x2B, 0xA6, 0x2B, 0xAD}, /* 24MHz Xtal */
2627                 {0x00}, /* 41MHz XTal   */
2628         };
2629
2630         u8 itbCoef6bw[3][14] = {
2631                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2632                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 20.5MHz XTal */
2633                 {0x31, 0xA8, 0x29, 0x9B, 0x27, 0x9C, 0x28, 0x9E, 0x29,
2634                         0xA4, 0x29, 0xA2, 0x29, 0xA8}, /* 24MHz Xtal   */
2635                 {0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8, 0x00,
2636                         0xCF, 0x00, 0xE6, 0x23, 0xA4}, /* 41MHz XTal   */
2637         };
2638
2639         dev_dbg(&priv->i2c->dev, "%s() bandwidth=%u\n", __func__, bandwidth);
2640         /* Set SLV-T Bank : 0x10 */
2641         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2642
2643         /*  20.5/41MHz Xtal support is not available
2644          *  on ISDB-T 7MHzBW and 8MHzBW
2645         */
2646         if (priv->xtal != SONY_XTAL_24000 && bandwidth > 6000000) {
2647                 dev_err(&priv->i2c->dev,
2648                         "%s(): bandwidth %d supported only for 24MHz xtal\n",
2649                         __func__, bandwidth);
2650                 return -EINVAL;
2651         }
2652
2653         switch (bandwidth) {
2654         case 8000000:
2655                 /* TRCG Nominal Rate */
2656                 cxd2841er_write_regs(priv, I2C_SLVT,
2657                                 0x9F, nominalRate8bw[priv->xtal], 5);
2658                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2659                 cxd2841er_write_regs(priv, I2C_SLVT,
2660                                 0xA6, itbCoef8bw[priv->xtal], 14);
2661
2662                 /* IF freq setting */
2663                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.75);
2664                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2665                 data[1] = (u8)((iffreq >> 8) & 0xff);
2666                 data[2] = (u8)(iffreq & 0xff);
2667                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2668
2669                 /* System bandwidth setting */
2670                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x0, 0x7);
2671
2672                 /* Demod core latency setting */
2673                 data[0] = 0x13;
2674                 data[1] = 0xFC;
2675                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2676
2677                 /* Acquisition optimization setting */
2678                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2679                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2680                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2681                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x03);
2682                 break;
2683         case 7000000:
2684                 /* TRCG Nominal Rate */
2685                 cxd2841er_write_regs(priv, I2C_SLVT,
2686                                 0x9F, nominalRate7bw[priv->xtal], 5);
2687                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2688                 cxd2841er_write_regs(priv, I2C_SLVT,
2689                                 0xA6, itbCoef7bw[priv->xtal], 14);
2690
2691                 /* IF freq setting */
2692                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 4.15);
2693                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2694                 data[1] = (u8)((iffreq >> 8) & 0xff);
2695                 data[2] = (u8)(iffreq & 0xff);
2696                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2697
2698                 /* System bandwidth setting */
2699                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x02, 0x7);
2700
2701                 /* Demod core latency setting */
2702                 data[0] = 0x1A;
2703                 data[1] = 0xFA;
2704                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2705
2706                 /* Acquisition optimization setting */
2707                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2708                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x03, 0x07);
2709                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2710                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2711                 break;
2712         case 6000000:
2713                 /* TRCG Nominal Rate */
2714                 cxd2841er_write_regs(priv, I2C_SLVT,
2715                                 0x9F, nominalRate6bw[priv->xtal], 5);
2716                 /*  Group delay equaliser settings for ASCOT tuners optimized */
2717                 cxd2841er_write_regs(priv, I2C_SLVT,
2718                                 0xA6, itbCoef6bw[priv->xtal], 14);
2719
2720                 /* IF freq setting */
2721                 iffreq = MAKE_IFFREQ_CONFIG_XTAL(priv->xtal, 3.55);
2722                 data[0] = (u8) ((iffreq >> 16) & 0xff);
2723                 data[1] = (u8)((iffreq >> 8) & 0xff);
2724                 data[2] = (u8)(iffreq & 0xff);
2725                 cxd2841er_write_regs(priv, I2C_SLVT, 0xB6, data, 3);
2726
2727                 /* System bandwidth setting */
2728                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd7, 0x04, 0x7);
2729
2730                 /* Demod core latency setting */
2731                 if (priv->xtal == SONY_XTAL_24000) {
2732                         data[0] = 0x1F;
2733                         data[1] = 0x79;
2734                 } else {
2735                         data[0] = 0x1A;
2736                         data[1] = 0xE2;
2737                 }
2738                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
2739
2740                 /* Acquisition optimization setting */
2741                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x12);
2742                 cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x71, 0x07, 0x07);
2743                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
2744                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBE, 0x02);
2745                 break;
2746         default:
2747                 dev_dbg(&priv->i2c->dev, "%s(): invalid bandwidth %d\n",
2748                                 __func__, bandwidth);
2749                 return -EINVAL;
2750         }
2751         return 0;
2752 }
2753
2754 static int cxd2841er_sleep_tc_to_active_c_band(struct cxd2841er_priv *priv,
2755                                                u32 bandwidth)
2756 {
2757         u8 bw7_8mhz_b10_a6[] = {
2758                 0x2D, 0xC7, 0x04, 0xF4, 0x07, 0xC5, 0x2A, 0xB8,
2759                 0x27, 0x9E, 0x27, 0xA4, 0x29, 0xAB };
2760         u8 bw6mhz_b10_a6[] = {
2761                 0x27, 0xA7, 0x28, 0xB3, 0x02, 0xF0, 0x01, 0xE8,
2762                 0x00, 0xCF, 0x00, 0xE6, 0x23, 0xA4 };
2763         u8 b10_b6[3];
2764         u32 iffreq;
2765
2766         if (bandwidth != 6000000 &&
2767                         bandwidth != 7000000 &&
2768                         bandwidth != 8000000) {
2769                 dev_info(&priv->i2c->dev, "%s(): unsupported bandwidth %d. Forcing 8Mhz!\n",
2770                                 __func__, bandwidth);
2771                 bandwidth = 8000000;
2772         }
2773
2774         dev_dbg(&priv->i2c->dev, "%s() bw=%d\n", __func__, bandwidth);
2775         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2776         switch (bandwidth) {
2777         case 8000000:
2778         case 7000000:
2779                 cxd2841er_write_regs(
2780                         priv, I2C_SLVT, 0xa6,
2781                         bw7_8mhz_b10_a6, sizeof(bw7_8mhz_b10_a6));
2782                 iffreq = MAKE_IFFREQ_CONFIG(4.9);
2783                 break;
2784         case 6000000:
2785                 cxd2841er_write_regs(
2786                         priv, I2C_SLVT, 0xa6,
2787                         bw6mhz_b10_a6, sizeof(bw6mhz_b10_a6));
2788                 iffreq = MAKE_IFFREQ_CONFIG(3.7);
2789                 break;
2790         default:
2791                 dev_err(&priv->i2c->dev, "%s(): unsupported bandwidth %d\n",
2792                         __func__, bandwidth);
2793                 return -EINVAL;
2794         }
2795         /* <IF freq setting> */
2796         b10_b6[0] = (u8) ((iffreq >> 16) & 0xff);
2797         b10_b6[1] = (u8)((iffreq >> 8) & 0xff);
2798         b10_b6[2] = (u8)(iffreq & 0xff);
2799         cxd2841er_write_regs(priv, I2C_SLVT, 0xb6, b10_b6, sizeof(b10_b6));
2800         /* Set SLV-T Bank : 0x11 */
2801         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2802         switch (bandwidth) {
2803         case 8000000:
2804         case 7000000:
2805                 cxd2841er_set_reg_bits(
2806                         priv, I2C_SLVT, 0xa3, 0x00, 0x1f);
2807                 break;
2808         case 6000000:
2809                 cxd2841er_set_reg_bits(
2810                         priv, I2C_SLVT, 0xa3, 0x14, 0x1f);
2811                 break;
2812         }
2813         /* Set SLV-T Bank : 0x40 */
2814         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
2815         switch (bandwidth) {
2816         case 8000000:
2817                 cxd2841er_set_reg_bits(
2818                         priv, I2C_SLVT, 0x26, 0x0b, 0x0f);
2819                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x3e);
2820                 break;
2821         case 7000000:
2822                 cxd2841er_set_reg_bits(
2823                         priv, I2C_SLVT, 0x26, 0x09, 0x0f);
2824                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0xd6);
2825                 break;
2826         case 6000000:
2827                 cxd2841er_set_reg_bits(
2828                         priv, I2C_SLVT, 0x26, 0x08, 0x0f);
2829                 cxd2841er_write_reg(priv, I2C_SLVT,  0x27, 0x6e);
2830                 break;
2831         }
2832         return 0;
2833 }
2834
2835 static int cxd2841er_sleep_tc_to_active_t(struct cxd2841er_priv *priv,
2836                                           u32 bandwidth)
2837 {
2838         u8 data[2] = { 0x09, 0x54 };
2839         u8 data24m[3] = {0xDC, 0x6C, 0x00};
2840
2841         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2842         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
2843         /* Set SLV-X Bank : 0x00 */
2844         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2845         /* Set demod mode */
2846         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x01);
2847         /* Set SLV-T Bank : 0x00 */
2848         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2849         /* Enable demod clock */
2850         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2851         /* Disable RF level monitor */
2852         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2853         /* Enable ADC clock */
2854         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2855         /* Enable ADC 1 */
2856         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2857         /* Enable ADC 2 & 3 */
2858         if (priv->xtal == SONY_XTAL_41000) {
2859                 data[0] = 0x0A;
2860                 data[1] = 0xD4;
2861         }
2862         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2863         /* Enable ADC 4 */
2864         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2865         /* Set SLV-T Bank : 0x10 */
2866         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2867         /* IFAGC gain settings */
2868         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2869         /* Set SLV-T Bank : 0x11 */
2870         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2871         /* BBAGC TARGET level setting */
2872         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2873         /* Set SLV-T Bank : 0x10 */
2874         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2875         /* ASCOT setting ON */
2876         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2877         /* Set SLV-T Bank : 0x18 */
2878         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2879         /* Pre-RS BER moniter setting */
2880         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x36, 0x40, 0x07);
2881         /* FEC Auto Recovery setting */
2882         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
2883         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x01, 0x01);
2884         /* Set SLV-T Bank : 0x00 */
2885         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2886         /* TSIF setting */
2887         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2888         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2889
2890         if (priv->xtal == SONY_XTAL_24000) {
2891                 /* Set SLV-T Bank : 0x10 */
2892                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2893                 cxd2841er_write_reg(priv, I2C_SLVT, 0xBF, 0x60);
2894                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x18);
2895                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data24m, 3);
2896         }
2897
2898         cxd2841er_sleep_tc_to_active_t_band(priv, bandwidth);
2899         /* Set SLV-T Bank : 0x00 */
2900         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2901         /* Disable HiZ Setting 1 */
2902         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
2903         /* Disable HiZ Setting 2 */
2904         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
2905         priv->state = STATE_ACTIVE_TC;
2906         return 0;
2907 }
2908
2909 static int cxd2841er_sleep_tc_to_active_t2(struct cxd2841er_priv *priv,
2910                                            u32 bandwidth)
2911 {
2912         u8 data[MAX_WRITE_REGSIZE];
2913
2914         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
2915         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT2);
2916         /* Set SLV-X Bank : 0x00 */
2917         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
2918         /* Set demod mode */
2919         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x02);
2920         /* Set SLV-T Bank : 0x00 */
2921         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2922         /* Enable demod clock */
2923         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
2924         /* Disable RF level monitor */
2925         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
2926         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
2927         /* Enable ADC clock */
2928         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
2929         /* Enable ADC 1 */
2930         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
2931
2932         if (priv->xtal == SONY_XTAL_41000) {
2933                 data[0] = 0x0A;
2934                 data[1] = 0xD4;
2935         } else {
2936                 data[0] = 0x09;
2937                 data[1] = 0x54;
2938         }
2939
2940         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
2941         /* Enable ADC 4 */
2942         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
2943         /* Set SLV-T Bank : 0x10 */
2944         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2945         /* IFAGC gain settings */
2946         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x0c, 0x1f);
2947         /* Set SLV-T Bank : 0x11 */
2948         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2949         /* BBAGC TARGET level setting */
2950         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x50);
2951         /* Set SLV-T Bank : 0x10 */
2952         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
2953         /* ASCOT setting ON */
2954         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
2955         /* Set SLV-T Bank : 0x20 */
2956         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2957         /* Acquisition optimization setting */
2958         cxd2841er_write_reg(priv, I2C_SLVT, 0x8b, 0x3c);
2959         /* Set SLV-T Bank : 0x2b */
2960         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2961         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x76, 0x20, 0x70);
2962         /* Set SLV-T Bank : 0x23 */
2963         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x23);
2964         /* L1 Control setting */
2965         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE6, 0x00, 0x03);
2966         /* Set SLV-T Bank : 0x00 */
2967         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
2968         /* TSIF setting */
2969         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
2970         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
2971         /* DVB-T2 initial setting */
2972         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x13);
2973         cxd2841er_write_reg(priv, I2C_SLVT, 0x83, 0x10);
2974         cxd2841er_write_reg(priv, I2C_SLVT, 0x86, 0x34);
2975         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9e, 0x09, 0x0f);
2976         cxd2841er_write_reg(priv, I2C_SLVT, 0x9f, 0xd8);
2977         /* Set SLV-T Bank : 0x2a */
2978         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2a);
2979         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x38, 0x04, 0x0f);
2980         /* Set SLV-T Bank : 0x2b */
2981         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2b);
2982         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x11, 0x20, 0x3f);
2983
2984         /* 24MHz Xtal setting */
2985         if (priv->xtal == SONY_XTAL_24000) {
2986                 /* Set SLV-T Bank : 0x11 */
2987                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
2988                 data[0] = 0xEB;
2989                 data[1] = 0x03;
2990                 data[2] = 0x3B;
2991                 cxd2841er_write_regs(priv, I2C_SLVT, 0x33, data, 3);
2992
2993                 /* Set SLV-T Bank : 0x20 */
2994                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x20);
2995                 data[0] = 0x5E;
2996                 data[1] = 0x5E;
2997                 data[2] = 0x47;
2998                 cxd2841er_write_regs(priv, I2C_SLVT, 0x95, data, 3);
2999
3000                 cxd2841er_write_reg(priv, I2C_SLVT, 0x99, 0x18);
3001
3002                 data[0] = 0x3F;
3003                 data[1] = 0xFF;
3004                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD9, data, 2);
3005
3006                 /* Set SLV-T Bank : 0x24 */
3007                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x24);
3008                 data[0] = 0x0B;
3009                 data[1] = 0x72;
3010                 cxd2841er_write_regs(priv, I2C_SLVT, 0x34, data, 2);
3011
3012                 data[0] = 0x93;
3013                 data[1] = 0xF3;
3014                 data[2] = 0x00;
3015                 cxd2841er_write_regs(priv, I2C_SLVT, 0xD2, data, 3);
3016
3017                 data[0] = 0x05;
3018                 data[1] = 0xB8;
3019                 data[2] = 0xD8;
3020                 cxd2841er_write_regs(priv, I2C_SLVT, 0xDD, data, 3);
3021
3022                 cxd2841er_write_reg(priv, I2C_SLVT, 0xE0, 0x00);
3023
3024                 /* Set SLV-T Bank : 0x25 */
3025                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x25);
3026                 cxd2841er_write_reg(priv, I2C_SLVT, 0xED, 0x60);
3027
3028                 /* Set SLV-T Bank : 0x27 */
3029                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x27);
3030                 cxd2841er_write_reg(priv, I2C_SLVT, 0xFA, 0x34);
3031
3032                 /* Set SLV-T Bank : 0x2B */
3033                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2B);
3034                 cxd2841er_write_reg(priv, I2C_SLVT, 0x4B, 0x2F);
3035                 cxd2841er_write_reg(priv, I2C_SLVT, 0x9E, 0x0E);
3036
3037                 /* Set SLV-T Bank : 0x2D */
3038                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x2D);
3039                 data[0] = 0x89;
3040                 data[1] = 0x89;
3041                 cxd2841er_write_regs(priv, I2C_SLVT, 0x24, data, 2);
3042
3043                 /* Set SLV-T Bank : 0x5E */
3044                 cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x5E);
3045                 data[0] = 0x24;
3046                 data[1] = 0x95;
3047                 cxd2841er_write_regs(priv, I2C_SLVT, 0x8C, data, 2);
3048         }
3049
3050         cxd2841er_sleep_tc_to_active_t2_band(priv, bandwidth);
3051
3052         /* Set SLV-T Bank : 0x00 */
3053         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3054         /* Disable HiZ Setting 1 */
3055         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3056         /* Disable HiZ Setting 2 */
3057         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3058         priv->state = STATE_ACTIVE_TC;
3059         return 0;
3060 }
3061
3062 /* ISDB-Tb part */
3063 static int cxd2841er_sleep_tc_to_active_i(struct cxd2841er_priv *priv,
3064                 u32 bandwidth)
3065 {
3066         u8 data[2] = { 0x09, 0x54 };
3067         u8 data24m[2] = {0x60, 0x00};
3068         u8 data24m2[3] = {0xB7, 0x1B, 0x00};
3069
3070         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3071         cxd2841er_set_ts_clock_mode(priv, SYS_DVBT);
3072         /* Set SLV-X Bank : 0x00 */
3073         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3074         /* Set demod mode */
3075         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x06);
3076         /* Set SLV-T Bank : 0x00 */
3077         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3078         /* Enable demod clock */
3079         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3080         /* Enable RF level monitor */
3081         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x01);
3082         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x01);
3083         /* Enable ADC clock */
3084         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3085         /* Enable ADC 1 */
3086         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3087         /* xtal freq 20.5MHz or 24M */
3088         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3089         /* Enable ADC 4 */
3090         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3091         /* ASCOT setting ON */
3092         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3093         /* FEC Auto Recovery setting */
3094         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x30, 0x01, 0x01);
3095         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x31, 0x00, 0x01);
3096         /* ISDB-T initial setting */
3097         /* Set SLV-T Bank : 0x00 */
3098         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3099         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x00, 0x01);
3100         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x00, 0x01);
3101         /* Set SLV-T Bank : 0x10 */
3102         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3103         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x69, 0x04, 0x07);
3104         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x6B, 0x03, 0x07);
3105         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x9D, 0x50, 0xFF);
3106         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xD3, 0x06, 0x1F);
3107         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xED, 0x00, 0x01);
3108         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xE2, 0xCE, 0x80);
3109         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xF2, 0x13, 0x10);
3110         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x2E, 0x3F);
3111         /* Set SLV-T Bank : 0x15 */
3112         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x15);
3113         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xDE, 0x02, 0x03);
3114         /* Set SLV-T Bank : 0x1E */
3115         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x1E);
3116         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x73, 0x68, 0xFF);
3117         /* Set SLV-T Bank : 0x63 */
3118         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x63);
3119         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0x81, 0x00, 0x01);
3120
3121         /* for xtal 24MHz */
3122         /* Set SLV-T Bank : 0x10 */
3123         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3124         cxd2841er_write_regs(priv, I2C_SLVT, 0xBF, data24m, 2);
3125         /* Set SLV-T Bank : 0x60 */
3126         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x60);
3127         cxd2841er_write_regs(priv, I2C_SLVT, 0xA8, data24m2, 3);
3128
3129         cxd2841er_sleep_tc_to_active_i_band(priv, bandwidth);
3130         /* Set SLV-T Bank : 0x00 */
3131         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3132         /* Disable HiZ Setting 1 */
3133         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3134         /* Disable HiZ Setting 2 */
3135         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3136         priv->state = STATE_ACTIVE_TC;
3137         return 0;
3138 }
3139
3140 static int cxd2841er_sleep_tc_to_active_c(struct cxd2841er_priv *priv,
3141                                           u32 bandwidth)
3142 {
3143         u8 data[2] = { 0x09, 0x54 };
3144
3145         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3146         cxd2841er_set_ts_clock_mode(priv, SYS_DVBC_ANNEX_A);
3147         /* Set SLV-X Bank : 0x00 */
3148         cxd2841er_write_reg(priv, I2C_SLVX, 0x00, 0x00);
3149         /* Set demod mode */
3150         cxd2841er_write_reg(priv, I2C_SLVX, 0x17, 0x04);
3151         /* Set SLV-T Bank : 0x00 */
3152         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3153         /* Enable demod clock */
3154         cxd2841er_write_reg(priv, I2C_SLVT, 0x2c, 0x01);
3155         /* Disable RF level monitor */
3156         cxd2841er_write_reg(priv, I2C_SLVT, 0x59, 0x00);
3157         cxd2841er_write_reg(priv, I2C_SLVT, 0x2f, 0x00);
3158         /* Enable ADC clock */
3159         cxd2841er_write_reg(priv, I2C_SLVT, 0x30, 0x00);
3160         /* Enable ADC 1 */
3161         cxd2841er_write_reg(priv, I2C_SLVT, 0x41, 0x1a);
3162         /* xtal freq 20.5MHz */
3163         cxd2841er_write_regs(priv, I2C_SLVT, 0x43, data, 2);
3164         /* Enable ADC 4 */
3165         cxd2841er_write_reg(priv, I2C_SLVX, 0x18, 0x00);
3166         /* Set SLV-T Bank : 0x10 */
3167         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3168         /* IFAGC gain settings */
3169         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xd2, 0x09, 0x1f);
3170         /* Set SLV-T Bank : 0x11 */
3171         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x11);
3172         /* BBAGC TARGET level setting */
3173         cxd2841er_write_reg(priv, I2C_SLVT, 0x6a, 0x48);
3174         /* Set SLV-T Bank : 0x10 */
3175         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3176         /* ASCOT setting ON */
3177         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xa5, 0x01, 0x01);
3178         /* Set SLV-T Bank : 0x40 */
3179         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x40);
3180         /* Demod setting */
3181         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc3, 0x00, 0x04);
3182         /* Set SLV-T Bank : 0x00 */
3183         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3184         /* TSIF setting */
3185         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xce, 0x01, 0x01);
3186         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcf, 0x01, 0x01);
3187
3188         cxd2841er_sleep_tc_to_active_c_band(priv, bandwidth);
3189         /* Set SLV-T Bank : 0x00 */
3190         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3191         /* Disable HiZ Setting 1 */
3192         cxd2841er_write_reg(priv, I2C_SLVT, 0x80, 0x28);
3193         /* Disable HiZ Setting 2 */
3194         cxd2841er_write_reg(priv, I2C_SLVT, 0x81, 0x00);
3195         priv->state = STATE_ACTIVE_TC;
3196         return 0;
3197 }
3198
3199 static int cxd2841er_get_frontend(struct dvb_frontend *fe,
3200                                   struct dtv_frontend_properties *p)
3201 {
3202         enum fe_status status = 0;
3203         struct cxd2841er_priv *priv = fe->demodulator_priv;
3204
3205         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3206         if (priv->state == STATE_ACTIVE_S)
3207                 cxd2841er_read_status_s(fe, &status);
3208         else if (priv->state == STATE_ACTIVE_TC)
3209                 cxd2841er_read_status_tc(fe, &status);
3210
3211         cxd2841er_read_signal_strength(fe);
3212
3213         if (status & FE_HAS_LOCK) {
3214                 cxd2841er_read_snr(fe);
3215                 cxd2841er_read_ucblocks(fe);
3216
3217                 cxd2841er_read_ber(fe);
3218         } else {
3219                 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3220                 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3221                 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3222                 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3223         }
3224         return 0;
3225 }
3226
3227 static int cxd2841er_set_frontend_s(struct dvb_frontend *fe)
3228 {
3229         int ret = 0, i, timeout, carr_offset;
3230         enum fe_status status;
3231         struct cxd2841er_priv *priv = fe->demodulator_priv;
3232         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3233         u32 symbol_rate = p->symbol_rate/1000;
3234
3235         dev_dbg(&priv->i2c->dev, "%s(): %s frequency=%d symbol_rate=%d xtal=%d\n",
3236                 __func__,
3237                 (p->delivery_system == SYS_DVBS ? "DVB-S" : "DVB-S2"),
3238                  p->frequency, symbol_rate, priv->xtal);
3239         switch (priv->state) {
3240         case STATE_SLEEP_S:
3241                 ret = cxd2841er_sleep_s_to_active_s(
3242                         priv, p->delivery_system, symbol_rate);
3243                 break;
3244         case STATE_ACTIVE_S:
3245                 ret = cxd2841er_retune_active(priv, p);
3246                 break;
3247         default:
3248                 dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3249                         __func__, priv->state);
3250                 ret = -EINVAL;
3251                 goto done;
3252         }
3253         if (ret) {
3254                 dev_dbg(&priv->i2c->dev, "%s(): tune failed\n", __func__);
3255                 goto done;
3256         }
3257         if (fe->ops.i2c_gate_ctrl)
3258                 fe->ops.i2c_gate_ctrl(fe, 1);
3259         if (fe->ops.tuner_ops.set_params)
3260                 fe->ops.tuner_ops.set_params(fe);
3261         if (fe->ops.i2c_gate_ctrl)
3262                 fe->ops.i2c_gate_ctrl(fe, 0);
3263         cxd2841er_tune_done(priv);
3264         timeout = ((3000000 + (symbol_rate - 1)) / symbol_rate) + 150;
3265         for (i = 0; i < timeout / CXD2841ER_DVBS_POLLING_INVL; i++) {
3266                 usleep_range(CXD2841ER_DVBS_POLLING_INVL*1000,
3267                         (CXD2841ER_DVBS_POLLING_INVL + 2) * 1000);
3268                 cxd2841er_read_status_s(fe, &status);
3269                 if (status & FE_HAS_LOCK)
3270                         break;
3271         }
3272         if (status & FE_HAS_LOCK) {
3273                 if (cxd2841er_get_carrier_offset_s_s2(
3274                                 priv, &carr_offset)) {
3275                         ret = -EINVAL;
3276                         goto done;
3277                 }
3278                 dev_dbg(&priv->i2c->dev, "%s(): carrier_offset=%d\n",
3279                         __func__, carr_offset);
3280         }
3281 done:
3282         /* Reset stats */
3283         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3284         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3285         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3286         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3287         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3288
3289         return ret;
3290 }
3291
3292 static int cxd2841er_set_frontend_tc(struct dvb_frontend *fe)
3293 {
3294         int ret = 0, timeout;
3295         enum fe_status status;
3296         struct cxd2841er_priv *priv = fe->demodulator_priv;
3297         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3298
3299         dev_dbg(&priv->i2c->dev, "%s() delivery_system=%d bandwidth_hz=%d\n",
3300                  __func__, p->delivery_system, p->bandwidth_hz);
3301         if (p->delivery_system == SYS_DVBT) {
3302                 priv->system = SYS_DVBT;
3303                 switch (priv->state) {
3304                 case STATE_SLEEP_TC:
3305                         ret = cxd2841er_sleep_tc_to_active_t(
3306                                 priv, p->bandwidth_hz);
3307                         break;
3308                 case STATE_ACTIVE_TC:
3309                         ret = cxd2841er_retune_active(priv, p);
3310                         break;
3311                 default:
3312                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3313                                 __func__, priv->state);
3314                         ret = -EINVAL;
3315                 }
3316         } else if (p->delivery_system == SYS_DVBT2) {
3317                 priv->system = SYS_DVBT2;
3318                 cxd2841er_dvbt2_set_plp_config(priv,
3319                         (int)(p->stream_id > 255), p->stream_id);
3320                 cxd2841er_dvbt2_set_profile(priv, DVBT2_PROFILE_BASE);
3321                 switch (priv->state) {
3322                 case STATE_SLEEP_TC:
3323                         ret = cxd2841er_sleep_tc_to_active_t2(priv,
3324                                 p->bandwidth_hz);
3325                         break;
3326                 case STATE_ACTIVE_TC:
3327                         ret = cxd2841er_retune_active(priv, p);
3328                         break;
3329                 default:
3330                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3331                                 __func__, priv->state);
3332                         ret = -EINVAL;
3333                 }
3334         } else if (p->delivery_system == SYS_ISDBT) {
3335                 priv->system = SYS_ISDBT;
3336                 switch (priv->state) {
3337                 case STATE_SLEEP_TC:
3338                         ret = cxd2841er_sleep_tc_to_active_i(
3339                                         priv, p->bandwidth_hz);
3340                         break;
3341                 case STATE_ACTIVE_TC:
3342                         ret = cxd2841er_retune_active(priv, p);
3343                         break;
3344                 default:
3345                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3346                                         __func__, priv->state);
3347                         ret = -EINVAL;
3348                 }
3349         } else if (p->delivery_system == SYS_DVBC_ANNEX_A ||
3350                         p->delivery_system == SYS_DVBC_ANNEX_C) {
3351                 priv->system = SYS_DVBC_ANNEX_A;
3352                 /* correct bandwidth */
3353                 if (p->bandwidth_hz != 6000000 &&
3354                                 p->bandwidth_hz != 7000000 &&
3355                                 p->bandwidth_hz != 8000000) {
3356                         p->bandwidth_hz = 8000000;
3357                         dev_dbg(&priv->i2c->dev, "%s(): forcing bandwidth to %d\n",
3358                                         __func__, p->bandwidth_hz);
3359                 }
3360
3361                 switch (priv->state) {
3362                 case STATE_SLEEP_TC:
3363                         ret = cxd2841er_sleep_tc_to_active_c(
3364                                 priv, p->bandwidth_hz);
3365                         break;
3366                 case STATE_ACTIVE_TC:
3367                         ret = cxd2841er_retune_active(priv, p);
3368                         break;
3369                 default:
3370                         dev_dbg(&priv->i2c->dev, "%s(): invalid state %d\n",
3371                                 __func__, priv->state);
3372                         ret = -EINVAL;
3373                 }
3374         } else {
3375                 dev_dbg(&priv->i2c->dev,
3376                         "%s(): invalid delivery system %d\n",
3377                         __func__, p->delivery_system);
3378                 ret = -EINVAL;
3379         }
3380         if (ret)
3381                 goto done;
3382         if (fe->ops.i2c_gate_ctrl)
3383                 fe->ops.i2c_gate_ctrl(fe, 1);
3384         if (fe->ops.tuner_ops.set_params)
3385                 fe->ops.tuner_ops.set_params(fe);
3386         if (fe->ops.i2c_gate_ctrl)
3387                 fe->ops.i2c_gate_ctrl(fe, 0);
3388         cxd2841er_tune_done(priv);
3389         timeout = 2500;
3390         while (timeout > 0) {
3391                 ret = cxd2841er_read_status_tc(fe, &status);
3392                 if (ret)
3393                         goto done;
3394                 if (status & FE_HAS_LOCK)
3395                         break;
3396                 msleep(20);
3397                 timeout -= 20;
3398         }
3399         if (timeout < 0)
3400                 dev_dbg(&priv->i2c->dev,
3401                         "%s(): LOCK wait timeout\n", __func__);
3402 done:
3403         return ret;
3404 }
3405
3406 static int cxd2841er_tune_s(struct dvb_frontend *fe,
3407                             bool re_tune,
3408                             unsigned int mode_flags,
3409                             unsigned int *delay,
3410                             enum fe_status *status)
3411 {
3412         int ret, carrier_offset;
3413         struct cxd2841er_priv *priv = fe->demodulator_priv;
3414         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3415
3416         dev_dbg(&priv->i2c->dev, "%s() re_tune=%d\n", __func__, re_tune);
3417         if (re_tune) {
3418                 ret = cxd2841er_set_frontend_s(fe);
3419                 if (ret)
3420                         return ret;
3421                 cxd2841er_read_status_s(fe, status);
3422                 if (*status & FE_HAS_LOCK) {
3423                         if (cxd2841er_get_carrier_offset_s_s2(
3424                                         priv, &carrier_offset))
3425                                 return -EINVAL;
3426                         p->frequency += carrier_offset;
3427                         ret = cxd2841er_set_frontend_s(fe);
3428                         if (ret)
3429                                 return ret;
3430                 }
3431         }
3432         *delay = HZ / 5;
3433         return cxd2841er_read_status_s(fe, status);
3434 }
3435
3436 static int cxd2841er_tune_tc(struct dvb_frontend *fe,
3437                              bool re_tune,
3438                              unsigned int mode_flags,
3439                              unsigned int *delay,
3440                              enum fe_status *status)
3441 {
3442         int ret, carrier_offset;
3443         struct cxd2841er_priv *priv = fe->demodulator_priv;
3444         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3445
3446         dev_dbg(&priv->i2c->dev, "%s(): re_tune %d bandwidth=%d\n", __func__,
3447                         re_tune, p->bandwidth_hz);
3448         if (re_tune) {
3449                 ret = cxd2841er_set_frontend_tc(fe);
3450                 if (ret)
3451                         return ret;
3452                 cxd2841er_read_status_tc(fe, status);
3453                 if (*status & FE_HAS_LOCK) {
3454                         switch (priv->system) {
3455                         case SYS_ISDBT:
3456                                 ret = cxd2841er_get_carrier_offset_i(
3457                                                 priv, p->bandwidth_hz,
3458                                                 &carrier_offset);
3459                                 if (ret)
3460                                         return ret;
3461                                 break;
3462                         case SYS_DVBT:
3463                                 ret = cxd2841er_get_carrier_offset_t(
3464                                         priv, p->bandwidth_hz,
3465                                         &carrier_offset);
3466                                 if (ret)
3467                                         return ret;
3468                                 break;
3469                         case SYS_DVBT2:
3470                                 ret = cxd2841er_get_carrier_offset_t2(
3471                                         priv, p->bandwidth_hz,
3472                                         &carrier_offset);
3473                                 if (ret)
3474                                         return ret;
3475                                 break;
3476                         case SYS_DVBC_ANNEX_A:
3477                                 ret = cxd2841er_get_carrier_offset_c(
3478                                         priv, &carrier_offset);
3479                                 if (ret)
3480                                         return ret;
3481                                 break;
3482                         default:
3483                                 dev_dbg(&priv->i2c->dev,
3484                                         "%s(): invalid delivery system %d\n",
3485                                         __func__, priv->system);
3486                                 return -EINVAL;
3487                         }
3488                         dev_dbg(&priv->i2c->dev, "%s(): carrier offset %d\n",
3489                                 __func__, carrier_offset);
3490                         p->frequency += carrier_offset;
3491                         ret = cxd2841er_set_frontend_tc(fe);
3492                         if (ret)
3493                                 return ret;
3494                 }
3495         }
3496         *delay = HZ / 5;
3497         return cxd2841er_read_status_tc(fe, status);
3498 }
3499
3500 static int cxd2841er_sleep_s(struct dvb_frontend *fe)
3501 {
3502         struct cxd2841er_priv *priv = fe->demodulator_priv;
3503
3504         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3505         cxd2841er_active_s_to_sleep_s(fe->demodulator_priv);
3506         cxd2841er_sleep_s_to_shutdown(fe->demodulator_priv);
3507         return 0;
3508 }
3509
3510 static int cxd2841er_sleep_tc(struct dvb_frontend *fe)
3511 {
3512         struct cxd2841er_priv *priv = fe->demodulator_priv;
3513
3514         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3515         if (priv->state == STATE_ACTIVE_TC) {
3516                 switch (priv->system) {
3517                 case SYS_DVBT:
3518                         cxd2841er_active_t_to_sleep_tc(priv);
3519                         break;
3520                 case SYS_DVBT2:
3521                         cxd2841er_active_t2_to_sleep_tc(priv);
3522                         break;
3523                 case SYS_ISDBT:
3524                         cxd2841er_active_i_to_sleep_tc(priv);
3525                         break;
3526                 case SYS_DVBC_ANNEX_A:
3527                         cxd2841er_active_c_to_sleep_tc(priv);
3528                         break;
3529                 default:
3530                         dev_warn(&priv->i2c->dev,
3531                                 "%s(): unknown delivery system %d\n",
3532                                 __func__, priv->system);
3533                 }
3534         }
3535         if (priv->state != STATE_SLEEP_TC) {
3536                 dev_err(&priv->i2c->dev, "%s(): invalid state %d\n",
3537                         __func__, priv->state);
3538                 return -EINVAL;
3539         }
3540         cxd2841er_sleep_tc_to_shutdown(priv);
3541         return 0;
3542 }
3543
3544 static int cxd2841er_send_burst(struct dvb_frontend *fe,
3545                                 enum fe_sec_mini_cmd burst)
3546 {
3547         u8 data;
3548         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3549
3550         dev_dbg(&priv->i2c->dev, "%s(): burst mode %s\n", __func__,
3551                 (burst == SEC_MINI_A ? "A" : "B"));
3552         if (priv->state != STATE_SLEEP_S &&
3553                         priv->state != STATE_ACTIVE_S) {
3554                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3555                         __func__, priv->state);
3556                 return -EINVAL;
3557         }
3558         data = (burst == SEC_MINI_A ? 0 : 1);
3559         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3560         cxd2841er_write_reg(priv, I2C_SLVT, 0x34, 0x01);
3561         cxd2841er_write_reg(priv, I2C_SLVT, 0x35, data);
3562         return 0;
3563 }
3564
3565 static int cxd2841er_set_tone(struct dvb_frontend *fe,
3566                               enum fe_sec_tone_mode tone)
3567 {
3568         u8 data;
3569         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3570
3571         dev_dbg(&priv->i2c->dev, "%s(): tone %s\n", __func__,
3572                 (tone == SEC_TONE_ON ? "On" : "Off"));
3573         if (priv->state != STATE_SLEEP_S &&
3574                         priv->state != STATE_ACTIVE_S) {
3575                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3576                         __func__, priv->state);
3577                 return -EINVAL;
3578         }
3579         data = (tone == SEC_TONE_ON ? 1 : 0);
3580         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3581         cxd2841er_write_reg(priv, I2C_SLVT, 0x36, data);
3582         return 0;
3583 }
3584
3585 static int cxd2841er_send_diseqc_msg(struct dvb_frontend *fe,
3586                                      struct dvb_diseqc_master_cmd *cmd)
3587 {
3588         int i;
3589         u8 data[12];
3590         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3591
3592         if (priv->state != STATE_SLEEP_S &&
3593                         priv->state != STATE_ACTIVE_S) {
3594                 dev_err(&priv->i2c->dev, "%s(): invalid demod state %d\n",
3595                         __func__, priv->state);
3596                 return -EINVAL;
3597         }
3598         dev_dbg(&priv->i2c->dev,
3599                 "%s(): cmd->len %d\n", __func__, cmd->msg_len);
3600         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xbb);
3601         /* DiDEqC enable */
3602         cxd2841er_write_reg(priv, I2C_SLVT, 0x33, 0x01);
3603         /* cmd1 length & data */
3604         cxd2841er_write_reg(priv, I2C_SLVT, 0x3d, cmd->msg_len);
3605         memset(data, 0, sizeof(data));
3606         for (i = 0; i < cmd->msg_len && i < sizeof(data); i++)
3607                 data[i] = cmd->msg[i];
3608         cxd2841er_write_regs(priv, I2C_SLVT, 0x3e, data, sizeof(data));
3609         /* repeat count for cmd1 */
3610         cxd2841er_write_reg(priv, I2C_SLVT, 0x37, 1);
3611         /* repeat count for cmd2: always 0 */
3612         cxd2841er_write_reg(priv, I2C_SLVT, 0x38, 0);
3613         /* start transmit */
3614         cxd2841er_write_reg(priv, I2C_SLVT, 0x32, 0x01);
3615         /* wait for 1 sec timeout */
3616         for (i = 0; i < 50; i++) {
3617                 cxd2841er_read_reg(priv, I2C_SLVT, 0x10, data);
3618                 if (!data[0]) {
3619                         dev_dbg(&priv->i2c->dev,
3620                                 "%s(): DiSEqC cmd has been sent\n", __func__);
3621                         return 0;
3622                 }
3623                 msleep(20);
3624         }
3625         dev_dbg(&priv->i2c->dev,
3626                 "%s(): DiSEqC cmd transmit timeout\n", __func__);
3627         return -ETIMEDOUT;
3628 }
3629
3630 static void cxd2841er_release(struct dvb_frontend *fe)
3631 {
3632         struct cxd2841er_priv *priv  = fe->demodulator_priv;
3633
3634         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3635         kfree(priv);
3636 }
3637
3638 static int cxd2841er_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
3639 {
3640         struct cxd2841er_priv *priv = fe->demodulator_priv;
3641
3642         dev_dbg(&priv->i2c->dev, "%s(): enable=%d\n", __func__, enable);
3643         cxd2841er_set_reg_bits(
3644                 priv, I2C_SLVX, 0x8, (enable ? 0x01 : 0x00), 0x01);
3645         return 0;
3646 }
3647
3648 static enum dvbfe_algo cxd2841er_get_algo(struct dvb_frontend *fe)
3649 {
3650         struct cxd2841er_priv *priv = fe->demodulator_priv;
3651
3652         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3653         return DVBFE_ALGO_HW;
3654 }
3655
3656 static void cxd2841er_init_stats(struct dvb_frontend *fe)
3657 {
3658         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3659
3660         p->strength.len = 1;
3661         p->strength.stat[0].scale = FE_SCALE_RELATIVE;
3662         p->cnr.len = 1;
3663         p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3664         p->block_error.len = 1;
3665         p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3666         p->post_bit_error.len = 1;
3667         p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3668         p->post_bit_count.len = 1;
3669         p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
3670 }
3671
3672
3673 static int cxd2841er_init_s(struct dvb_frontend *fe)
3674 {
3675         struct cxd2841er_priv *priv = fe->demodulator_priv;
3676
3677         /* sanity. force demod to SHUTDOWN state */
3678         if (priv->state == STATE_SLEEP_S) {
3679                 dev_dbg(&priv->i2c->dev, "%s() forcing sleep->shutdown\n",
3680                                 __func__);
3681                 cxd2841er_sleep_s_to_shutdown(priv);
3682         } else if (priv->state == STATE_ACTIVE_S) {
3683                 dev_dbg(&priv->i2c->dev, "%s() forcing active->sleep->shutdown\n",
3684                                 __func__);
3685                 cxd2841er_active_s_to_sleep_s(priv);
3686                 cxd2841er_sleep_s_to_shutdown(priv);
3687         }
3688
3689         dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
3690         cxd2841er_shutdown_to_sleep_s(priv);
3691         /* SONY_DEMOD_CONFIG_SAT_IFAGCNEG set to 1 */
3692         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0xa0);
3693         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xb9, 0x01, 0x01);
3694
3695         cxd2841er_init_stats(fe);
3696
3697         return 0;
3698 }
3699
3700 static int cxd2841er_init_tc(struct dvb_frontend *fe)
3701 {
3702         struct cxd2841er_priv *priv = fe->demodulator_priv;
3703         struct dtv_frontend_properties *p = &fe->dtv_property_cache;
3704
3705         dev_dbg(&priv->i2c->dev, "%s() bandwidth_hz=%d\n",
3706                         __func__, p->bandwidth_hz);
3707         cxd2841er_shutdown_to_sleep_tc(priv);
3708         /* SONY_DEMOD_CONFIG_IFAGCNEG = 1 */
3709         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x10);
3710         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xcb, 0x40, 0x40);
3711         /* SONY_DEMOD_CONFIG_IFAGC_ADC_FS = 0 */
3712         cxd2841er_write_reg(priv, I2C_SLVT, 0xcd, 0x50);
3713         /* SONY_DEMOD_CONFIG_PARALLEL_SEL = 1 */
3714         cxd2841er_write_reg(priv, I2C_SLVT, 0x00, 0x00);
3715         cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x80);
3716
3717         cxd2841er_init_stats(fe);
3718
3719         return 0;
3720 }
3721
3722 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops;
3723 static struct dvb_frontend_ops cxd2841er_t_c_ops;
3724
3725 static struct dvb_frontend *cxd2841er_attach(struct cxd2841er_config *cfg,
3726                                              struct i2c_adapter *i2c,
3727                                              u8 system)
3728 {
3729         u8 chip_id = 0;
3730         const char *type;
3731         const char *name;
3732         struct cxd2841er_priv *priv = NULL;
3733
3734         /* allocate memory for the internal state */
3735         priv = kzalloc(sizeof(struct cxd2841er_priv), GFP_KERNEL);
3736         if (!priv)
3737                 return NULL;
3738         priv->i2c = i2c;
3739         priv->config = cfg;
3740         priv->i2c_addr_slvx = (cfg->i2c_addr + 4) >> 1;
3741         priv->i2c_addr_slvt = (cfg->i2c_addr) >> 1;
3742         priv->xtal = cfg->xtal;
3743         priv->frontend.demodulator_priv = priv;
3744         dev_info(&priv->i2c->dev,
3745                 "%s(): I2C adapter %p SLVX addr %x SLVT addr %x\n",
3746                 __func__, priv->i2c,
3747                 priv->i2c_addr_slvx, priv->i2c_addr_slvt);
3748         chip_id = cxd2841er_chip_id(priv);
3749         switch (chip_id) {
3750         case CXD2841ER_CHIP_ID:
3751                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3752                                 "Sony CXD2841ER DVB-T/T2/C demodulator");
3753                 name = "CXD2841ER";
3754                 break;
3755         case CXD2854ER_CHIP_ID:
3756                 snprintf(cxd2841er_t_c_ops.info.name, 128,
3757                                 "Sony CXD2854ER DVB-T/T2/C and ISDB-T demodulator");
3758                 cxd2841er_t_c_ops.delsys[3] = SYS_ISDBT;
3759                 name = "CXD2854ER";
3760                 break;
3761         default:
3762                 dev_err(&priv->i2c->dev, "%s(): invalid chip ID 0x%02x\n",
3763                                 __func__, chip_id);
3764                 priv->frontend.demodulator_priv = NULL;
3765                 kfree(priv);
3766                 return NULL;
3767         }
3768
3769         /* create dvb_frontend */
3770         if (system == SYS_DVBS) {
3771                 memcpy(&priv->frontend.ops,
3772                         &cxd2841er_dvbs_s2_ops,
3773                         sizeof(struct dvb_frontend_ops));
3774                 type = "S/S2";
3775         } else {
3776                 memcpy(&priv->frontend.ops,
3777                         &cxd2841er_t_c_ops,
3778                         sizeof(struct dvb_frontend_ops));
3779                 type = "T/T2/C/ISDB-T";
3780         }
3781
3782         dev_info(&priv->i2c->dev,
3783                 "%s(): attaching %s DVB-%s frontend\n",
3784                 __func__, name, type);
3785         dev_info(&priv->i2c->dev, "%s(): chip ID 0x%02x OK.\n",
3786                 __func__, chip_id);
3787         return &priv->frontend;
3788 }
3789
3790 struct dvb_frontend *cxd2841er_attach_s(struct cxd2841er_config *cfg,
3791                                         struct i2c_adapter *i2c)
3792 {
3793         return cxd2841er_attach(cfg, i2c, SYS_DVBS);
3794 }
3795 EXPORT_SYMBOL(cxd2841er_attach_s);
3796
3797 struct dvb_frontend *cxd2841er_attach_t_c(struct cxd2841er_config *cfg,
3798                                         struct i2c_adapter *i2c)
3799 {
3800         return cxd2841er_attach(cfg, i2c, 0);
3801 }
3802 EXPORT_SYMBOL(cxd2841er_attach_t_c);
3803
3804 static struct dvb_frontend_ops cxd2841er_dvbs_s2_ops = {
3805         .delsys = { SYS_DVBS, SYS_DVBS2 },
3806         .info = {
3807                 .name           = "Sony CXD2841ER DVB-S/S2 demodulator",
3808                 .frequency_min  = 500000,
3809                 .frequency_max  = 2500000,
3810                 .frequency_stepsize     = 0,
3811                 .symbol_rate_min = 1000000,
3812                 .symbol_rate_max = 45000000,
3813                 .symbol_rate_tolerance = 500,
3814                 .caps = FE_CAN_INVERSION_AUTO |
3815                         FE_CAN_FEC_AUTO |
3816                         FE_CAN_QPSK,
3817         },
3818         .init = cxd2841er_init_s,
3819         .sleep = cxd2841er_sleep_s,
3820         .release = cxd2841er_release,
3821         .set_frontend = cxd2841er_set_frontend_s,
3822         .get_frontend = cxd2841er_get_frontend,
3823         .read_status = cxd2841er_read_status_s,
3824         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3825         .get_frontend_algo = cxd2841er_get_algo,
3826         .set_tone = cxd2841er_set_tone,
3827         .diseqc_send_burst = cxd2841er_send_burst,
3828         .diseqc_send_master_cmd = cxd2841er_send_diseqc_msg,
3829         .tune = cxd2841er_tune_s
3830 };
3831
3832 static struct  dvb_frontend_ops cxd2841er_t_c_ops = {
3833         .delsys = { SYS_DVBT, SYS_DVBT2, SYS_DVBC_ANNEX_A },
3834         .info = {
3835                 .name   = "", /* will set in attach function */
3836                 .caps = FE_CAN_FEC_1_2 |
3837                         FE_CAN_FEC_2_3 |
3838                         FE_CAN_FEC_3_4 |
3839                         FE_CAN_FEC_5_6 |
3840                         FE_CAN_FEC_7_8 |
3841                         FE_CAN_FEC_AUTO |
3842                         FE_CAN_QPSK |
3843                         FE_CAN_QAM_16 |
3844                         FE_CAN_QAM_32 |
3845                         FE_CAN_QAM_64 |
3846                         FE_CAN_QAM_128 |
3847                         FE_CAN_QAM_256 |
3848                         FE_CAN_QAM_AUTO |
3849                         FE_CAN_TRANSMISSION_MODE_AUTO |
3850                         FE_CAN_GUARD_INTERVAL_AUTO |
3851                         FE_CAN_HIERARCHY_AUTO |
3852                         FE_CAN_MUTE_TS |
3853                         FE_CAN_2G_MODULATION,
3854                 .frequency_min = 42000000,
3855                 .frequency_max = 1002000000
3856         },
3857         .init = cxd2841er_init_tc,
3858         .sleep = cxd2841er_sleep_tc,
3859         .release = cxd2841er_release,
3860         .set_frontend = cxd2841er_set_frontend_tc,
3861         .get_frontend = cxd2841er_get_frontend,
3862         .read_status = cxd2841er_read_status_tc,
3863         .tune = cxd2841er_tune_tc,
3864         .i2c_gate_ctrl = cxd2841er_i2c_gate_ctrl,
3865         .get_frontend_algo = cxd2841er_get_algo
3866 };
3867
3868 MODULE_DESCRIPTION("Sony CXD2841ER/CXD2854ER DVB-C/C2/T/T2/S/S2 demodulator driver");
3869 MODULE_AUTHOR("Sergey Kozlov <serjk@netup.ru>, Abylay Ospan <aospan@netup.ru>");
3870 MODULE_LICENSE("GPL");