2 * Linux-DVB Driver for DiBcom's DiB8000 chip (ISDB-T).
4 * Copyright (C) 2009 DiBcom (http://www.dibcom.fr/)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation, version 2.
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/i2c.h>
13 #include <linux/mutex.h>
14 #include <asm/div64.h>
18 #include "dvb_frontend.h"
27 #define MAX_NUMBER_OF_FRONTENDS 6
28 /* #define DIB8000_AGC_FREEZE */
31 module_param(debug, int, 0644);
32 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
34 #define dprintk(args...) do { if (debug) { printk(KERN_DEBUG "DiB8000: "); printk(args); printk("\n"); } } while (0)
37 struct i2c_adapter *adap;
41 struct mutex *i2c_buffer_lock;
44 enum param_loop_step {
49 enum dib8000_autosearch_step {
57 SYMBOL_DEPENDENT_OFF = 0,
61 struct dib8000_state {
62 struct dib8000_config cfg;
64 struct i2c_device i2c;
66 struct dibx000_i2c_master i2c_master;
71 u32 current_bandwidth;
72 struct dibx000_agc_config *current_agc;
81 u8 differential_constellation;
84 s16 ber_monitored_layer;
90 enum frontend_tune_state tune_state;
93 struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
95 /* for the I2C transfer */
96 struct i2c_msg msg[2];
97 u8 i2c_write_buffer[4];
98 u8 i2c_read_buffer[2];
99 struct mutex i2c_buffer_lock;
103 struct i2c_adapter dib8096p_tuner_adap;
104 u16 current_demod_bw;
112 u8 channel_parameters_set;
113 u16 autosearch_state;
118 unsigned long timeout;
119 u8 longest_intlv_layer;
122 /* for DVBv5 stats */
124 unsigned long per_jiffies_stats;
125 unsigned long ber_jiffies_stats;
126 unsigned long ber_jiffies_stats_layer[3];
128 #ifdef DIB8000_AGC_FREEZE
136 enum dib8000_power_mode {
137 DIB8000_POWER_ALL = 0,
138 DIB8000_POWER_INTERFACE_ONLY,
141 static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
144 struct i2c_msg msg[2] = {
145 {.addr = i2c->addr >> 1, .flags = 0, .len = 2},
146 {.addr = i2c->addr >> 1, .flags = I2C_M_RD, .len = 2},
149 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
150 dprintk("could not acquire lock");
154 msg[0].buf = i2c->i2c_write_buffer;
155 msg[0].buf[0] = reg >> 8;
156 msg[0].buf[1] = reg & 0xff;
157 msg[1].buf = i2c->i2c_read_buffer;
159 if (i2c_transfer(i2c->adap, msg, 2) != 2)
160 dprintk("i2c read error on %d", reg);
162 ret = (msg[1].buf[0] << 8) | msg[1].buf[1];
163 mutex_unlock(i2c->i2c_buffer_lock);
167 static u16 __dib8000_read_word(struct dib8000_state *state, u16 reg)
171 state->i2c_write_buffer[0] = reg >> 8;
172 state->i2c_write_buffer[1] = reg & 0xff;
174 memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
175 state->msg[0].addr = state->i2c.addr >> 1;
176 state->msg[0].flags = 0;
177 state->msg[0].buf = state->i2c_write_buffer;
178 state->msg[0].len = 2;
179 state->msg[1].addr = state->i2c.addr >> 1;
180 state->msg[1].flags = I2C_M_RD;
181 state->msg[1].buf = state->i2c_read_buffer;
182 state->msg[1].len = 2;
184 if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
185 dprintk("i2c read error on %d", reg);
187 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
192 static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
196 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
197 dprintk("could not acquire lock");
201 ret = __dib8000_read_word(state, reg);
203 mutex_unlock(&state->i2c_buffer_lock);
208 static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
212 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
213 dprintk("could not acquire lock");
217 rw[0] = __dib8000_read_word(state, reg + 0);
218 rw[1] = __dib8000_read_word(state, reg + 1);
220 mutex_unlock(&state->i2c_buffer_lock);
222 return ((rw[0] << 16) | (rw[1]));
225 static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
227 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4};
230 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) {
231 dprintk("could not acquire lock");
235 msg.buf = i2c->i2c_write_buffer;
236 msg.buf[0] = (reg >> 8) & 0xff;
237 msg.buf[1] = reg & 0xff;
238 msg.buf[2] = (val >> 8) & 0xff;
239 msg.buf[3] = val & 0xff;
241 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
242 mutex_unlock(i2c->i2c_buffer_lock);
247 static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
251 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) {
252 dprintk("could not acquire lock");
256 state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
257 state->i2c_write_buffer[1] = reg & 0xff;
258 state->i2c_write_buffer[2] = (val >> 8) & 0xff;
259 state->i2c_write_buffer[3] = val & 0xff;
261 memset(&state->msg[0], 0, sizeof(struct i2c_msg));
262 state->msg[0].addr = state->i2c.addr >> 1;
263 state->msg[0].flags = 0;
264 state->msg[0].buf = state->i2c_write_buffer;
265 state->msg[0].len = 4;
267 ret = (i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ?
269 mutex_unlock(&state->i2c_buffer_lock);
274 static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
275 (769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (784 << 5) | 0x02, (519 << 5) | 0x0c,
279 static const s16 coeff_2k_sb_1seg[8] = {
280 (692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f, 0 | 0x1f
283 static const s16 coeff_2k_sb_3seg_0dqpsk_1dqpsk[8] = {
284 (832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (912 << 5) | 0x04, (807 << 5) | 0x11,
288 static const s16 coeff_2k_sb_3seg_0dqpsk[8] = {
289 (622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (519 << 5) | 0x02, (572 << 5) | 0x0e,
293 static const s16 coeff_2k_sb_3seg_1dqpsk[8] = {
294 (699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (640 << 5) | 0x03, (866 << 5) | 0x12,
298 static const s16 coeff_2k_sb_3seg[8] = {
299 (664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (697 << 5) | 0x01, (836 << 5) | 0x0e,
303 static const s16 coeff_4k_sb_1seg_dqpsk[8] = {
304 (-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, (750 << 5) | 0x03, (665 << 5) | 0x0f,
308 static const s16 coeff_4k_sb_1seg[8] = {
309 (638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (517 << 5) | 0x00, (698 << 5) | 0x0d,
313 static const s16 coeff_4k_sb_3seg_0dqpsk_1dqpsk[8] = {
314 (-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, (993 << 5) | 0x05, (523 << 5) | 0x14,
318 static const s16 coeff_4k_sb_3seg_0dqpsk[8] = {
319 (-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, (547 << 5) | 0x03, (696 << 5) | 0x12,
323 static const s16 coeff_4k_sb_3seg_1dqpsk[8] = {
324 (-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, (683 << 5) | 0x04, (543 << 5) | 0x14,
328 static const s16 coeff_4k_sb_3seg[8] = {
329 (612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (683 << 5) | 0x02, (869 << 5) | 0x12,
333 static const s16 coeff_8k_sb_1seg_dqpsk[8] = {
334 (-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, (781 << 5) | 0x04, (739 << 5) | 0x13,
338 static const s16 coeff_8k_sb_1seg[8] = {
339 (673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (512 << 5) | 0x01, (780 << 5) | 0x0f,
343 static const s16 coeff_8k_sb_3seg_0dqpsk_1dqpsk[8] = {
344 (863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 << 5) | 0x05, (980 << 5) | 0x18,
348 static const s16 coeff_8k_sb_3seg_0dqpsk[8] = {
349 (-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, (565 << 5) | 0x04, (553 << 5) | 0x15,
353 static const s16 coeff_8k_sb_3seg_1dqpsk[8] = {
354 (-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, (713 << 5) | 0x05, (1018 << 5) | 0x18,
358 static const s16 coeff_8k_sb_3seg[8] = {
359 (514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (683 << 5) | 0x03, (662 << 5) | 0x15,
363 static const s16 ana_fe_coeff_3seg[24] = {
364 81, 80, 78, 74, 68, 61, 54, 45, 37, 28, 19, 11, 4, 1022, 1017, 1013, 1010, 1008, 1008, 1008, 1008, 1010, 1014, 1017
367 static const s16 ana_fe_coeff_1seg[24] = {
368 249, 226, 164, 82, 5, 981, 970, 988, 1018, 20, 31, 26, 8, 1012, 1000, 1018, 1012, 8, 15, 14, 9, 3, 1017, 1003
371 static const s16 ana_fe_coeff_13seg[24] = {
372 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
375 static u16 fft_to_mode(struct dib8000_state *state)
378 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
379 case TRANSMISSION_MODE_2K:
382 case TRANSMISSION_MODE_4K:
386 case TRANSMISSION_MODE_AUTO:
387 case TRANSMISSION_MODE_8K:
394 static void dib8000_set_acquisition_mode(struct dib8000_state *state)
396 u16 nud = dib8000_read_word(state, 298);
397 nud |= (1 << 3) | (1 << 0);
398 dprintk("acquisition mode activated");
399 dib8000_write_word(state, 298, nud);
401 static int dib8000_set_output_mode(struct dvb_frontend *fe, int mode)
403 struct dib8000_state *state = fe->demodulator_priv;
404 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */
406 state->output_mode = mode;
408 fifo_threshold = 1792;
409 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
411 dprintk("-I- Setting output mode for demod %p to %d",
412 &state->fe[0], mode);
415 case OUTMODE_MPEG2_PAR_GATED_CLK: // STBs with parallel gated clock
416 outreg = (1 << 10); /* 0x0400 */
418 case OUTMODE_MPEG2_PAR_CONT_CLK: // STBs with parallel continues clock
419 outreg = (1 << 10) | (1 << 6); /* 0x0440 */
421 case OUTMODE_MPEG2_SERIAL: // STBs with serial input
422 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */
424 case OUTMODE_DIVERSITY:
425 if (state->cfg.hostbus_diversity) {
426 outreg = (1 << 10) | (4 << 6); /* 0x0500 */
431 case OUTMODE_MPEG2_FIFO: // e.g. USB feeding
432 smo_mode |= (3 << 1);
433 fifo_threshold = 512;
434 outreg = (1 << 10) | (5 << 6);
436 case OUTMODE_HIGH_Z: // disable
440 case OUTMODE_ANALOG_ADC:
441 outreg = (1 << 10) | (3 << 6);
442 dib8000_set_acquisition_mode(state);
446 dprintk("Unhandled output_mode passed to be set for demod %p",
451 if (state->cfg.output_mpeg2_in_188_bytes)
452 smo_mode |= (1 << 5);
454 dib8000_write_word(state, 299, smo_mode);
455 dib8000_write_word(state, 300, fifo_threshold); /* synchronous fread */
456 dib8000_write_word(state, 1286, outreg);
457 dib8000_write_word(state, 1291, sram);
462 static int dib8000_set_diversity_in(struct dvb_frontend *fe, int onoff)
464 struct dib8000_state *state = fe->demodulator_priv;
465 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0;
467 dprintk("set diversity input to %i", onoff);
468 if (!state->differential_constellation) {
469 dib8000_write_word(state, 272, 1 << 9); //dvsy_off_lmod4 = 1
470 dib8000_write_word(state, 273, sync_wait | (1 << 2) | 2); // sync_enable = 1; comb_mode = 2
472 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0
473 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0
475 state->diversity_onoff = onoff;
478 case 0: /* only use the internal way - not the diversity input */
479 dib8000_write_word(state, 270, 1);
480 dib8000_write_word(state, 271, 0);
482 case 1: /* both ways */
483 dib8000_write_word(state, 270, 6);
484 dib8000_write_word(state, 271, 6);
486 case 2: /* only the diversity input */
487 dib8000_write_word(state, 270, 0);
488 dib8000_write_word(state, 271, 1);
492 if (state->revision == 0x8002) {
493 tmp = dib8000_read_word(state, 903);
494 dib8000_write_word(state, 903, tmp & ~(1 << 3));
496 dib8000_write_word(state, 903, tmp | (1 << 3));
501 static void dib8000_set_power_mode(struct dib8000_state *state, enum dib8000_power_mode mode)
503 /* by default everything is going to be powered off */
504 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff,
505 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3,
508 if (state->revision != 0x8090)
509 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00;
511 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80;
513 /* now, depending on the requested mode, we power on */
515 /* power up everything in the demod */
516 case DIB8000_POWER_ALL:
521 if (state->revision != 0x8090)
526 case DIB8000_POWER_INTERFACE_ONLY:
527 if (state->revision != 0x8090)
534 dprintk("powermode : 774 : %x ; 775 : %x; 776 : %x ; 900 : %x; 1280 : %x", reg_774, reg_775, reg_776, reg_900, reg_1280);
535 dib8000_write_word(state, 774, reg_774);
536 dib8000_write_word(state, 775, reg_775);
537 dib8000_write_word(state, 776, reg_776);
538 dib8000_write_word(state, 900, reg_900);
539 dib8000_write_word(state, 1280, reg_1280);
542 static int dib8000_set_adc_state(struct dib8000_state *state, enum dibx000_adc_states no)
545 u16 reg, reg_907 = dib8000_read_word(state, 907);
546 u16 reg_908 = dib8000_read_word(state, 908);
549 case DIBX000_SLOW_ADC_ON:
550 if (state->revision != 0x8090) {
551 reg_908 |= (1 << 1) | (1 << 0);
552 ret |= dib8000_write_word(state, 908, reg_908);
553 reg_908 &= ~(1 << 1);
555 reg = dib8000_read_word(state, 1925);
556 /* en_slowAdc = 1 & reset_sladc = 1 */
557 dib8000_write_word(state, 1925, reg |
560 /* read acces to make it works... strange ... */
561 reg = dib8000_read_word(state, 1925);
563 /* en_slowAdc = 1 & reset_sladc = 0 */
564 dib8000_write_word(state, 1925, reg & ~(1<<4));
566 reg = dib8000_read_word(state, 921) & ~((0x3 << 14)
568 /* ref = Vin1 => Vbg ; sel = Vin0 or Vin3 ;
570 dib8000_write_word(state, 921, reg | (1 << 14)
575 case DIBX000_SLOW_ADC_OFF:
576 if (state->revision == 0x8090) {
577 reg = dib8000_read_word(state, 1925);
578 /* reset_sladc = 1 en_slowAdc = 0 */
579 dib8000_write_word(state, 1925,
580 (reg & ~(1<<2)) | (1<<4));
582 reg_908 |= (1 << 1) | (1 << 0);
590 case DIBX000_ADC_OFF: // leave the VBG voltage on
591 reg_907 = (1 << 13) | (1 << 12);
592 reg_908 = (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 1);
595 case DIBX000_VBG_ENABLE:
596 reg_907 &= ~(1 << 15);
599 case DIBX000_VBG_DISABLE:
600 reg_907 |= (1 << 15);
607 ret |= dib8000_write_word(state, 907, reg_907);
608 ret |= dib8000_write_word(state, 908, reg_908);
613 static int dib8000_set_bandwidth(struct dvb_frontend *fe, u32 bw)
615 struct dib8000_state *state = fe->demodulator_priv;
621 if (state->timf == 0) {
622 dprintk("using default timf");
623 timf = state->timf_default;
625 dprintk("using updated timf");
629 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff));
630 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff));
635 static int dib8000_sad_calib(struct dib8000_state *state)
639 if (state->revision == 0x8090) {
640 dib8000_write_word(state, 922, (sad_sel << 2));
641 dib8000_write_word(state, 923, 2048);
643 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1);
644 dib8000_write_word(state, 922, (sad_sel << 2));
647 dib8000_write_word(state, 923, (0 << 1) | (0 << 0));
648 dib8000_write_word(state, 924, 776);
650 /* do the calibration */
651 dib8000_write_word(state, 923, (1 << 0));
652 dib8000_write_word(state, 923, (0 << 0));
659 static int dib8000_set_wbd_ref(struct dvb_frontend *fe, u16 value)
661 struct dib8000_state *state = fe->demodulator_priv;
664 state->wbd_ref = value;
665 return dib8000_write_word(state, 106, value);
668 static void dib8000_reset_pll_common(struct dib8000_state *state, const struct dibx000_bandwidth_config *bw)
670 dprintk("ifreq: %d %x, inversion: %d", bw->ifreq, bw->ifreq, bw->ifreq >> 25);
671 if (state->revision != 0x8090) {
672 dib8000_write_word(state, 23,
673 (u16) (((bw->internal * 1000) >> 16) & 0xffff));
674 dib8000_write_word(state, 24,
675 (u16) ((bw->internal * 1000) & 0xffff));
677 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff));
678 dib8000_write_word(state, 24,
679 (u16) ((bw->internal / 2 * 1000) & 0xffff));
681 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff));
682 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff));
683 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003));
685 if (state->revision != 0x8090)
686 dib8000_write_word(state, 922, bw->sad_cfg);
689 static void dib8000_reset_pll(struct dib8000_state *state)
691 const struct dibx000_bandwidth_config *pll = state->cfg.pll;
694 if (state->revision != 0x8090) {
695 dib8000_write_word(state, 901,
696 (pll->pll_prediv << 8) | (pll->pll_ratio << 0));
698 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) |
699 (pll->bypclk_div << 5) | (pll->enable_refdiv << 4) |
700 (1 << 3) | (pll->pll_range << 1) |
701 (pll->pll_reset << 0);
703 dib8000_write_word(state, 902, clk_cfg1);
704 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3);
705 dib8000_write_word(state, 902, clk_cfg1);
707 dprintk("clk_cfg1: 0x%04x", clk_cfg1);
709 /* smpl_cfg: P_refclksel=2, P_ensmplsel=1 nodivsmpl=1 */
710 if (state->cfg.pll->ADClkSrc == 0)
711 dib8000_write_word(state, 904,
712 (0 << 15) | (0 << 12) | (0 << 10) |
714 (pll->ADClkSrc << 7) | (0 << 1));
715 else if (state->cfg.refclksel != 0)
716 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
717 ((state->cfg.refclksel & 0x3) << 10) |
719 (pll->ADClkSrc << 7) | (0 << 1));
721 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) |
722 (3 << 10) | (pll->modulo << 8) |
723 (pll->ADClkSrc << 7) | (0 << 1));
725 dib8000_write_word(state, 1856, (!pll->pll_reset<<13) |
726 (pll->pll_range<<12) | (pll->pll_ratio<<6) |
729 reg = dib8000_read_word(state, 1857);
730 dib8000_write_word(state, 1857, reg|(!pll->pll_bypass<<15));
732 reg = dib8000_read_word(state, 1858); /* Force clk out pll /2 */
733 dib8000_write_word(state, 1858, reg | 1);
735 dib8000_write_word(state, 904, (pll->modulo << 8));
738 dib8000_reset_pll_common(state, pll);
741 static int dib8000_update_pll(struct dvb_frontend *fe,
742 struct dibx000_bandwidth_config *pll, u32 bw, u8 ratio)
744 struct dib8000_state *state = fe->demodulator_priv;
745 u16 reg_1857, reg_1856 = dib8000_read_word(state, 1856);
746 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ;
749 /* get back old values */
750 prediv = reg_1856 & 0x3f;
751 loopdiv = (reg_1856 >> 6) & 0x3f;
753 if ((pll == NULL) || (pll->pll_prediv == prediv &&
754 pll->pll_ratio == loopdiv))
757 dprintk("Updating pll (prediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio);
758 if (state->revision == 0x8090) {
760 reg_1857 = dib8000_read_word(state, 1857);
762 dib8000_write_word(state, 1857, reg_1857 & ~(1 << 15));
764 dib8000_write_word(state, 1856, reg_1856 |
765 ((pll->pll_ratio & 0x3f) << 6) |
766 (pll->pll_prediv & 0x3f));
768 /* write new system clk into P_sec_len */
769 internal = dib8000_read32(state, 23) / 1000;
770 dprintk("Old Internal = %d", internal);
771 xtal = 2 * (internal / loopdiv) * prediv;
772 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio;
773 dprintk("Xtal = %d , New Fmem = %d New Fdemod = %d, New Fsampling = %d", xtal, internal/1000, internal/2000, internal/8000);
774 dprintk("New Internal = %d", internal);
776 dib8000_write_word(state, 23,
777 (u16) (((internal / 2) >> 16) & 0xffff));
778 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff));
780 dib8000_write_word(state, 1857, reg_1857 | (1 << 15));
782 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1)
783 dprintk("Waiting for PLL to lock");
786 reg_1856 = dib8000_read_word(state, 1856);
787 dprintk("PLL Updated with prediv = %d and loopdiv = %d",
788 reg_1856&0x3f, (reg_1856>>6)&0x3f);
790 if (bw != state->current_demod_bw) {
791 /** Bandwidth change => force PLL update **/
792 dprintk("PLL: Bandwidth Change %d MHz -> %d MHz (prediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv);
794 if (state->cfg.pll->pll_prediv != oldprediv) {
795 /** Full PLL change only if prediv is changed **/
797 /** full update => bypass and reconfigure **/
798 dprintk("PLL: New Setting for %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio);
799 dib8000_write_word(state, 902, dib8000_read_word(state, 902) | (1<<3)); /* bypass PLL */
800 dib8000_reset_pll(state);
801 dib8000_write_word(state, 898, 0x0004); /* sad */
803 ratio = state->cfg.pll->pll_ratio;
805 state->current_demod_bw = bw;
809 /** ratio update => only change ratio **/
810 dprintk("PLL: Update ratio (prediv: %d, ratio: %d)", state->cfg.pll->pll_prediv, ratio);
811 dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL ratio is updated. */
818 static int dib8000_reset_gpio(struct dib8000_state *st)
820 /* reset the GPIOs */
821 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
822 dib8000_write_word(st, 1030, st->cfg.gpio_val);
824 /* TODO 782 is P_gpio_od */
826 dib8000_write_word(st, 1032, st->cfg.gpio_pwm_pos);
828 dib8000_write_word(st, 1037, st->cfg.pwm_freq_div);
832 static int dib8000_cfg_gpio(struct dib8000_state *st, u8 num, u8 dir, u8 val)
834 st->cfg.gpio_dir = dib8000_read_word(st, 1029);
835 st->cfg.gpio_dir &= ~(1 << num); /* reset the direction bit */
836 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */
837 dib8000_write_word(st, 1029, st->cfg.gpio_dir);
839 st->cfg.gpio_val = dib8000_read_word(st, 1030);
840 st->cfg.gpio_val &= ~(1 << num); /* reset the direction bit */
841 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */
842 dib8000_write_word(st, 1030, st->cfg.gpio_val);
844 dprintk("gpio dir: %x: gpio val: %x", st->cfg.gpio_dir, st->cfg.gpio_val);
849 static int dib8000_set_gpio(struct dvb_frontend *fe, u8 num, u8 dir, u8 val)
851 struct dib8000_state *state = fe->demodulator_priv;
852 return dib8000_cfg_gpio(state, num, dir, val);
855 static const u16 dib8000_defaults[] = {
856 /* auto search configuration - lock0 by default waiting
857 * for cpil_lock; lock1 cpil_lock; lock2 tmcc_sync_lock */
878 0x6680 // P_corm_thres Lock algorithms configuration */
880 11, 80, /* set ADC level to -16 */
881 (1 << 13) - 825 - 117,
882 (1 << 13) - 837 - 117,
883 (1 << 13) - 811 - 117,
884 (1 << 13) - 766 - 117,
885 (1 << 13) - 737 - 117,
886 (1 << 13) - 693 - 117,
887 (1 << 13) - 648 - 117,
888 (1 << 13) - 619 - 117,
889 (1 << 13) - 575 - 117,
890 (1 << 13) - 531 - 117,
891 (1 << 13) - 501 - 117,
902 8192, // P_fft_nb_to_cut
905 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
908 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
913 0x0666, // P_pha3_thres
914 0x0000, // P_cti_use_cpe, P_cti_use_prog
917 0x200f, // P_cspu_regul, P_cspu_win_cut
918 0x000f, // P_des_shift_work
921 0x023d, // P_adp_regul_cnt
922 0x00a4, // P_adp_noise_cnt
923 0x00a4, // P_adp_regul_ext
924 0x7ff0, // P_adp_noise_ext
928 0x0000, // P_2d_byp_ti_num
931 0x800, //P_equal_thres_wgn
934 (2 << 9) | 39, // P_equal_ctrl_synchro, P_equal_speedmode
937 0x0001, // P_div_lock0_wait
941 0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard */
944 (1 << 12) | // P_ctrl_corm_thres4pre_freq_inh=1
946 (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
947 (3 << 5) | /* P_ctrl_pre_freq_step=3 */
948 (1 << 0), /* P_pre_freq_win_len=1 */
953 static u16 dib8000_identify(struct i2c_device *client)
957 //because of glitches sometimes
958 value = dib8000_i2c_read16(client, 896);
960 if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) {
961 dprintk("wrong Vendor ID (read=0x%x)", value);
965 value = dib8000_i2c_read16(client, 897);
966 if (value != 0x8000 && value != 0x8001 &&
967 value != 0x8002 && value != 0x8090) {
968 dprintk("wrong Device ID (%x)", value);
974 dprintk("found DiB8000A");
977 dprintk("found DiB8000B");
980 dprintk("found DiB8000C");
983 dprintk("found DiB8096P");
989 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 *unc);
991 static void dib8000_reset_stats(struct dvb_frontend *fe)
993 struct dib8000_state *state = fe->demodulator_priv;
994 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
997 memset(&c->strength, 0, sizeof(c->strength));
998 memset(&c->cnr, 0, sizeof(c->cnr));
999 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error));
1000 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count));
1001 memset(&c->block_error, 0, sizeof(c->block_error));
1003 c->strength.len = 1;
1005 c->block_error.len = 1;
1006 c->block_count.len = 1;
1007 c->post_bit_error.len = 1;
1008 c->post_bit_count.len = 1;
1010 c->strength.stat[0].scale = FE_SCALE_DECIBEL;
1011 c->strength.stat[0].uvalue = 0;
1013 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1014 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1015 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1016 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1017 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
1019 dib8000_read_unc_blocks(fe, &ucb);
1021 state->init_ucb = -ucb;
1022 state->ber_jiffies_stats = 0;
1023 state->per_jiffies_stats = 0;
1024 memset(&state->ber_jiffies_stats_layer, 0,
1025 sizeof(state->ber_jiffies_stats_layer));
1028 static int dib8000_reset(struct dvb_frontend *fe)
1030 struct dib8000_state *state = fe->demodulator_priv;
1032 if ((state->revision = dib8000_identify(&state->i2c)) == 0)
1035 /* sram lead in, rdy */
1036 if (state->revision != 0x8090)
1037 dib8000_write_word(state, 1287, 0x0003);
1039 if (state->revision == 0x8000)
1040 dprintk("error : dib8000 MA not supported");
1042 dibx000_reset_i2c_master(&state->i2c_master);
1044 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1046 /* always leave the VBG voltage on - it consumes almost nothing but takes a long time to start */
1047 dib8000_set_adc_state(state, DIBX000_ADC_OFF);
1049 /* restart all parts */
1050 dib8000_write_word(state, 770, 0xffff);
1051 dib8000_write_word(state, 771, 0xffff);
1052 dib8000_write_word(state, 772, 0xfffc);
1053 dib8000_write_word(state, 898, 0x000c); /* restart sad */
1054 if (state->revision == 0x8090)
1055 dib8000_write_word(state, 1280, 0x0045);
1057 dib8000_write_word(state, 1280, 0x004d);
1058 dib8000_write_word(state, 1281, 0x000c);
1060 dib8000_write_word(state, 770, 0x0000);
1061 dib8000_write_word(state, 771, 0x0000);
1062 dib8000_write_word(state, 772, 0x0000);
1063 dib8000_write_word(state, 898, 0x0004); // sad
1064 dib8000_write_word(state, 1280, 0x0000);
1065 dib8000_write_word(state, 1281, 0x0000);
1068 if (state->revision != 0x8090) {
1069 if (state->cfg.drives)
1070 dib8000_write_word(state, 906, state->cfg.drives);
1072 dprintk("using standard PAD-drive-settings, please adjust settings in config-struct to be optimal.");
1073 /* min drive SDRAM - not optimal - adjust */
1074 dib8000_write_word(state, 906, 0x2d98);
1078 dib8000_reset_pll(state);
1079 if (state->revision != 0x8090)
1080 dib8000_write_word(state, 898, 0x0004);
1082 if (dib8000_reset_gpio(state) != 0)
1083 dprintk("GPIO reset was not successful.");
1085 if ((state->revision != 0x8090) &&
1086 (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0))
1087 dprintk("OUTPUT_MODE could not be resetted.");
1089 state->current_agc = NULL;
1091 // P_iqc_alpha_pha, P_iqc_alpha_amp, P_iqc_dcc_alpha, ...
1092 /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */
1093 if (state->cfg.pll->ifreq == 0)
1094 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */
1096 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */
1101 n = dib8000_defaults;
1106 dib8000_write_word(state, r, *n++);
1113 state->isdbt_cfg_loaded = 0;
1115 //div_cfg override for special configs
1116 if ((state->revision != 8090) && (state->cfg.div_cfg != 0))
1117 dib8000_write_word(state, 903, state->cfg.div_cfg);
1119 /* unforce divstr regardless whether i2c enumeration was done or not */
1120 dib8000_write_word(state, 1285, dib8000_read_word(state, 1285) & ~(1 << 1));
1122 dib8000_set_bandwidth(fe, 6000);
1124 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON);
1125 dib8000_sad_calib(state);
1126 if (state->revision != 0x8090)
1127 dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF);
1129 /* ber_rs_len = 3 */
1130 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5));
1132 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
1134 dib8000_reset_stats(fe);
1139 static void dib8000_restart_agc(struct dib8000_state *state)
1141 // P_restart_iqc & P_restart_agc
1142 dib8000_write_word(state, 770, 0x0a00);
1143 dib8000_write_word(state, 770, 0x0000);
1146 static int dib8000_update_lna(struct dib8000_state *state)
1150 if (state->cfg.update_lna) {
1151 // read dyn_gain here (because it is demod-dependent and not tuner)
1152 dyn_gain = dib8000_read_word(state, 390);
1154 if (state->cfg.update_lna(state->fe[0], dyn_gain)) {
1155 dib8000_restart_agc(state);
1162 static int dib8000_set_agc_config(struct dib8000_state *state, u8 band)
1164 struct dibx000_agc_config *agc = NULL;
1168 if (state->current_band == band && state->current_agc != NULL)
1170 state->current_band = band;
1172 for (i = 0; i < state->cfg.agc_config_count; i++)
1173 if (state->cfg.agc[i].band_caps & band) {
1174 agc = &state->cfg.agc[i];
1179 dprintk("no valid AGC configuration found for band 0x%02x", band);
1183 state->current_agc = agc;
1186 dib8000_write_word(state, 76, agc->setup);
1187 dib8000_write_word(state, 77, agc->inv_gain);
1188 dib8000_write_word(state, 78, agc->time_stabiliz);
1189 dib8000_write_word(state, 101, (agc->alpha_level << 12) | agc->thlock);
1191 // Demod AGC loop configuration
1192 dib8000_write_word(state, 102, (agc->alpha_mant << 5) | agc->alpha_exp);
1193 dib8000_write_word(state, 103, (agc->beta_mant << 6) | agc->beta_exp);
1195 dprintk("WBD: ref: %d, sel: %d, active: %d, alpha: %d",
1196 state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, agc->wbd_sel);
1199 if (state->wbd_ref != 0)
1200 dib8000_write_word(state, 106, state->wbd_ref);
1202 dib8000_write_word(state, 106, agc->wbd_ref);
1204 if (state->revision == 0x8090) {
1205 reg = dib8000_read_word(state, 922) & (0x3 << 2);
1206 dib8000_write_word(state, 922, reg | (agc->wbd_sel << 2));
1209 dib8000_write_word(state, 107, (agc->wbd_alpha << 9) | (agc->perform_agc_softsplit << 8));
1210 dib8000_write_word(state, 108, agc->agc1_max);
1211 dib8000_write_word(state, 109, agc->agc1_min);
1212 dib8000_write_word(state, 110, agc->agc2_max);
1213 dib8000_write_word(state, 111, agc->agc2_min);
1214 dib8000_write_word(state, 112, (agc->agc1_pt1 << 8) | agc->agc1_pt2);
1215 dib8000_write_word(state, 113, (agc->agc1_slope1 << 8) | agc->agc1_slope2);
1216 dib8000_write_word(state, 114, (agc->agc2_pt1 << 8) | agc->agc2_pt2);
1217 dib8000_write_word(state, 115, (agc->agc2_slope1 << 8) | agc->agc2_slope2);
1219 dib8000_write_word(state, 75, agc->agc1_pt3);
1220 if (state->revision != 0x8090)
1221 dib8000_write_word(state, 923,
1222 (dib8000_read_word(state, 923) & 0xffe3) |
1223 (agc->wbd_inv << 4) | (agc->wbd_sel << 2));
1228 static void dib8000_pwm_agc_reset(struct dvb_frontend *fe)
1230 struct dib8000_state *state = fe->demodulator_priv;
1231 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1232 dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000)));
1235 static int dib8000_agc_soft_split(struct dib8000_state *state)
1237 u16 agc, split_offset;
1239 if (!state->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0)
1243 agc = dib8000_read_word(state, 390);
1245 if (agc > state->current_agc->split.min_thres)
1246 split_offset = state->current_agc->split.min;
1247 else if (agc < state->current_agc->split.max_thres)
1248 split_offset = state->current_agc->split.max;
1250 split_offset = state->current_agc->split.max *
1251 (agc - state->current_agc->split.min_thres) /
1252 (state->current_agc->split.max_thres - state->current_agc->split.min_thres);
1254 dprintk("AGC split_offset: %d", split_offset);
1256 // P_agc_force_split and P_agc_split_offset
1257 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset);
1261 static int dib8000_agc_startup(struct dvb_frontend *fe)
1263 struct dib8000_state *state = fe->demodulator_priv;
1264 enum frontend_tune_state *tune_state = &state->tune_state;
1266 u16 reg, upd_demod_gain_period = 0x8000;
1268 switch (*tune_state) {
1270 // set power-up level: interf+analog+AGC
1272 if (state->revision != 0x8090)
1273 dib8000_set_adc_state(state, DIBX000_ADC_ON);
1275 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
1277 reg = dib8000_read_word(state, 1947)&0xff00;
1278 dib8000_write_word(state, 1946,
1279 upd_demod_gain_period & 0xFFFF);
1280 /* bit 14 = enDemodGain */
1281 dib8000_write_word(state, 1947, reg | (1<<14) |
1282 ((upd_demod_gain_period >> 16) & 0xFF));
1284 /* enable adc i & q */
1285 reg = dib8000_read_word(state, 1920);
1286 dib8000_write_word(state, 1920, (reg | 0x3) &
1290 if (dib8000_set_agc_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) {
1291 *tune_state = CT_AGC_STOP;
1292 state->status = FE_STATUS_TUNE_FAILED;
1297 *tune_state = CT_AGC_STEP_0;
1301 //AGC initialization
1302 if (state->cfg.agc_control)
1303 state->cfg.agc_control(fe, 1);
1305 dib8000_restart_agc(state);
1307 // wait AGC rough lock time
1309 *tune_state = CT_AGC_STEP_1;
1313 // wait AGC accurate lock time
1316 if (dib8000_update_lna(state))
1317 // wait only AGC rough lock time
1320 *tune_state = CT_AGC_STEP_2;
1324 dib8000_agc_soft_split(state);
1326 if (state->cfg.agc_control)
1327 state->cfg.agc_control(fe, 0);
1329 *tune_state = CT_AGC_STOP;
1332 ret = dib8000_agc_soft_split(state);
1339 static void dib8096p_host_bus_drive(struct dib8000_state *state, u8 drive)
1345 /* drive host bus 2, 3, 4 */
1346 reg = dib8000_read_word(state, 1798) &
1347 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1348 reg |= (drive<<12) | (drive<<6) | drive;
1349 dib8000_write_word(state, 1798, reg);
1351 /* drive host bus 5,6 */
1352 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8));
1353 reg |= (drive<<8) | (drive<<2);
1354 dib8000_write_word(state, 1799, reg);
1356 /* drive host bus 7, 8, 9 */
1357 reg = dib8000_read_word(state, 1800) &
1358 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1359 reg |= (drive<<12) | (drive<<6) | drive;
1360 dib8000_write_word(state, 1800, reg);
1362 /* drive host bus 10, 11 */
1363 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8));
1364 reg |= (drive<<8) | (drive<<2);
1365 dib8000_write_word(state, 1801, reg);
1367 /* drive host bus 12, 13, 14 */
1368 reg = dib8000_read_word(state, 1802) &
1369 ~(0x7 | (0x7 << 6) | (0x7 << 12));
1370 reg |= (drive<<12) | (drive<<6) | drive;
1371 dib8000_write_word(state, 1802, reg);
1374 static u32 dib8096p_calcSyncFreq(u32 P_Kin, u32 P_Kout,
1375 u32 insertExtSynchro, u32 syncSize)
1378 u32 nom = (insertExtSynchro * P_Kin+syncSize);
1380 u32 syncFreq = ((nom << quantif) / denom);
1382 if ((syncFreq & ((1 << quantif) - 1)) != 0)
1383 syncFreq = (syncFreq >> quantif) + 1;
1385 syncFreq = (syncFreq >> quantif);
1388 syncFreq = syncFreq - 1;
1393 static void dib8096p_cfg_DibTx(struct dib8000_state *state, u32 P_Kin,
1394 u32 P_Kout, u32 insertExtSynchro, u32 synchroMode,
1395 u32 syncWord, u32 syncSize)
1397 dprintk("Configure DibStream Tx");
1399 dib8000_write_word(state, 1615, 1);
1400 dib8000_write_word(state, 1603, P_Kin);
1401 dib8000_write_word(state, 1605, P_Kout);
1402 dib8000_write_word(state, 1606, insertExtSynchro);
1403 dib8000_write_word(state, 1608, synchroMode);
1404 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff);
1405 dib8000_write_word(state, 1610, syncWord & 0xffff);
1406 dib8000_write_word(state, 1612, syncSize);
1407 dib8000_write_word(state, 1615, 0);
1410 static void dib8096p_cfg_DibRx(struct dib8000_state *state, u32 P_Kin,
1411 u32 P_Kout, u32 synchroMode, u32 insertExtSynchro,
1412 u32 syncWord, u32 syncSize, u32 dataOutRate)
1416 dprintk("Configure DibStream Rx synchroMode = %d", synchroMode);
1418 if ((P_Kin != 0) && (P_Kout != 0)) {
1419 syncFreq = dib8096p_calcSyncFreq(P_Kin, P_Kout,
1420 insertExtSynchro, syncSize);
1421 dib8000_write_word(state, 1542, syncFreq);
1424 dib8000_write_word(state, 1554, 1);
1425 dib8000_write_word(state, 1536, P_Kin);
1426 dib8000_write_word(state, 1537, P_Kout);
1427 dib8000_write_word(state, 1539, synchroMode);
1428 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff);
1429 dib8000_write_word(state, 1541, syncWord & 0xffff);
1430 dib8000_write_word(state, 1543, syncSize);
1431 dib8000_write_word(state, 1544, dataOutRate);
1432 dib8000_write_word(state, 1554, 0);
1435 static void dib8096p_enMpegMux(struct dib8000_state *state, int onoff)
1439 reg_1287 = dib8000_read_word(state, 1287);
1443 reg_1287 &= ~(1 << 8);
1446 reg_1287 |= (1 << 8);
1450 dib8000_write_word(state, 1287, reg_1287);
1453 static void dib8096p_configMpegMux(struct dib8000_state *state,
1454 u16 pulseWidth, u16 enSerialMode, u16 enSerialClkDiv2)
1458 dprintk("Enable Mpeg mux");
1460 dib8096p_enMpegMux(state, 0);
1462 /* If the input mode is MPEG do not divide the serial clock */
1463 if ((enSerialMode == 1) && (state->input_mode_mpeg == 1))
1464 enSerialClkDiv2 = 0;
1466 reg_1287 = ((pulseWidth & 0x1f) << 3) |
1467 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1);
1468 dib8000_write_word(state, 1287, reg_1287);
1470 dib8096p_enMpegMux(state, 1);
1473 static void dib8096p_setDibTxMux(struct dib8000_state *state, int mode)
1475 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7);
1479 dprintk("SET MPEG ON DIBSTREAM TX");
1480 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0);
1481 reg_1288 |= (1 << 9); break;
1483 dprintk("SET DIV_OUT ON DIBSTREAM TX");
1484 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0);
1485 reg_1288 |= (1 << 8); break;
1487 dprintk("SET ADC_OUT ON DIBSTREAM TX");
1488 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0);
1489 reg_1288 |= (1 << 7); break;
1493 dib8000_write_word(state, 1288, reg_1288);
1496 static void dib8096p_setHostBusMux(struct dib8000_state *state, int mode)
1498 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4);
1501 case DEMOUT_ON_HOSTBUS:
1502 dprintk("SET DEM OUT OLD INTERF ON HOST BUS");
1503 dib8096p_enMpegMux(state, 0);
1504 reg_1288 |= (1 << 6);
1506 case DIBTX_ON_HOSTBUS:
1507 dprintk("SET DIBSTREAM TX ON HOST BUS");
1508 dib8096p_enMpegMux(state, 0);
1509 reg_1288 |= (1 << 5);
1511 case MPEG_ON_HOSTBUS:
1512 dprintk("SET MPEG MUX ON HOST BUS");
1513 reg_1288 |= (1 << 4);
1518 dib8000_write_word(state, 1288, reg_1288);
1521 static int dib8096p_set_diversity_in(struct dvb_frontend *fe, int onoff)
1523 struct dib8000_state *state = fe->demodulator_priv;
1527 case 0: /* only use the internal way - not the diversity input */
1528 dprintk("%s mode OFF : by default Enable Mpeg INPUT",
1530 /* outputRate = 8 */
1531 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0);
1533 /* Do not divide the serial clock of MPEG MUX in
1534 SERIAL MODE in case input mode MPEG is used */
1535 reg_1287 = dib8000_read_word(state, 1287);
1536 /* enSerialClkDiv2 == 1 ? */
1537 if ((reg_1287 & 0x1) == 1) {
1538 /* force enSerialClkDiv2 = 0 */
1540 dib8000_write_word(state, 1287, reg_1287);
1542 state->input_mode_mpeg = 1;
1544 case 1: /* both ways */
1545 case 2: /* only the diversity input */
1546 dprintk("%s ON : Enable diversity INPUT", __func__);
1547 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0);
1548 state->input_mode_mpeg = 0;
1552 dib8000_set_diversity_in(state->fe[0], onoff);
1556 static int dib8096p_set_output_mode(struct dvb_frontend *fe, int mode)
1558 struct dib8000_state *state = fe->demodulator_priv;
1559 u16 outreg, smo_mode, fifo_threshold;
1560 u8 prefer_mpeg_mux_use = 1;
1563 state->output_mode = mode;
1564 dib8096p_host_bus_drive(state, 1);
1566 fifo_threshold = 1792;
1567 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1);
1568 outreg = dib8000_read_word(state, 1286) &
1569 ~((1 << 10) | (0x7 << 6) | (1 << 1));
1572 case OUTMODE_HIGH_Z:
1576 case OUTMODE_MPEG2_SERIAL:
1577 if (prefer_mpeg_mux_use) {
1578 dprintk("dib8096P setting output mode TS_SERIAL using Mpeg Mux");
1579 dib8096p_configMpegMux(state, 3, 1, 1);
1580 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1581 } else {/* Use Smooth block */
1582 dprintk("dib8096P setting output mode TS_SERIAL using Smooth bloc");
1583 dib8096p_setHostBusMux(state,
1585 outreg |= (2 << 6) | (0 << 1);
1589 case OUTMODE_MPEG2_PAR_GATED_CLK:
1590 if (prefer_mpeg_mux_use) {
1591 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Mpeg Mux");
1592 dib8096p_configMpegMux(state, 2, 0, 0);
1593 dib8096p_setHostBusMux(state, MPEG_ON_HOSTBUS);
1594 } else { /* Use Smooth block */
1595 dprintk("dib8096P setting output mode TS_PARALLEL_GATED using Smooth block");
1596 dib8096p_setHostBusMux(state,
1602 case OUTMODE_MPEG2_PAR_CONT_CLK: /* Using Smooth block only */
1603 dprintk("dib8096P setting output mode TS_PARALLEL_CONT using Smooth block");
1604 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1608 case OUTMODE_MPEG2_FIFO:
1609 /* Using Smooth block because not supported
1610 by new Mpeg Mux bloc */
1611 dprintk("dib8096P setting output mode TS_FIFO using Smooth block");
1612 dib8096p_setHostBusMux(state, DEMOUT_ON_HOSTBUS);
1614 smo_mode |= (3 << 1);
1615 fifo_threshold = 512;
1618 case OUTMODE_DIVERSITY:
1619 dprintk("dib8096P setting output mode MODE_DIVERSITY");
1620 dib8096p_setDibTxMux(state, DIV_ON_DIBTX);
1621 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1624 case OUTMODE_ANALOG_ADC:
1625 dprintk("dib8096P setting output mode MODE_ANALOG_ADC");
1626 dib8096p_setDibTxMux(state, ADC_ON_DIBTX);
1627 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
1631 if (mode != OUTMODE_HIGH_Z)
1634 dprintk("output_mpeg2_in_188_bytes = %d",
1635 state->cfg.output_mpeg2_in_188_bytes);
1636 if (state->cfg.output_mpeg2_in_188_bytes)
1637 smo_mode |= (1 << 5);
1639 ret |= dib8000_write_word(state, 299, smo_mode);
1640 /* synchronous fread */
1641 ret |= dib8000_write_word(state, 299 + 1, fifo_threshold);
1642 ret |= dib8000_write_word(state, 1286, outreg);
1647 static int map_addr_to_serpar_number(struct i2c_msg *msg)
1649 if (msg->buf[0] <= 15)
1651 else if (msg->buf[0] == 17)
1653 else if (msg->buf[0] == 16)
1655 else if (msg->buf[0] == 19)
1657 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25)
1659 else if (msg->buf[0] == 28)
1661 else if (msg->buf[0] == 99)
1668 static int dib8096p_tuner_write_serpar(struct i2c_adapter *i2c_adap,
1669 struct i2c_msg msg[], int num)
1671 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1674 u16 serpar_num = msg[0].buf[0];
1676 while (n_overflow == 1 && i) {
1677 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1680 dprintk("Tuner ITF: write busy (overflow)");
1682 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f));
1683 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]);
1688 static int dib8096p_tuner_read_serpar(struct i2c_adapter *i2c_adap,
1689 struct i2c_msg msg[], int num)
1691 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1692 u8 n_overflow = 1, n_empty = 1;
1694 u16 serpar_num = msg[0].buf[0];
1697 while (n_overflow == 1 && i) {
1698 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1;
1701 dprintk("TunerITF: read busy (overflow)");
1703 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f));
1706 while (n_empty == 1 && i) {
1707 n_empty = dib8000_read_word(state, 1984)&0x1;
1710 dprintk("TunerITF: read busy (empty)");
1713 read_word = dib8000_read_word(state, 1987);
1714 msg[1].buf[0] = (read_word >> 8) & 0xff;
1715 msg[1].buf[1] = (read_word) & 0xff;
1720 static int dib8096p_tuner_rw_serpar(struct i2c_adapter *i2c_adap,
1721 struct i2c_msg msg[], int num)
1723 if (map_addr_to_serpar_number(&msg[0]) == 0) {
1724 if (num == 1) /* write */
1725 return dib8096p_tuner_write_serpar(i2c_adap, msg, 1);
1727 return dib8096p_tuner_read_serpar(i2c_adap, msg, 2);
1732 static int dib8096p_rw_on_apb(struct i2c_adapter *i2c_adap,
1733 struct i2c_msg msg[], int num, u16 apb_address)
1735 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1738 if (num == 1) { /* write */
1739 dib8000_write_word(state, apb_address,
1740 ((msg[0].buf[1] << 8) | (msg[0].buf[2])));
1742 word = dib8000_read_word(state, apb_address);
1743 msg[1].buf[0] = (word >> 8) & 0xff;
1744 msg[1].buf[1] = (word) & 0xff;
1749 static int dib8096p_tuner_xfer(struct i2c_adapter *i2c_adap,
1750 struct i2c_msg msg[], int num)
1752 struct dib8000_state *state = i2c_get_adapdata(i2c_adap);
1753 u16 apb_address = 0, word;
1756 switch (msg[0].buf[0]) {
1842 /* get sad sel request */
1843 i = ((dib8000_read_word(state, 921) >> 12)&0x3);
1844 word = dib8000_read_word(state, 924+i);
1845 msg[1].buf[0] = (word >> 8) & 0xff;
1846 msg[1].buf[1] = (word) & 0xff;
1849 if (num == 1) { /* write */
1850 word = (u16) ((msg[0].buf[1] << 8) |
1852 /* in the VGAMODE Sel are located on bit 0/1 */
1854 word = (dib8000_read_word(state, 921) &
1855 ~(3<<12)) | (word<<12);
1856 /* Set the proper input */
1857 dib8000_write_word(state, 921, word);
1862 if (apb_address != 0) /* R/W acces via APB */
1863 return dib8096p_rw_on_apb(i2c_adap, msg, num, apb_address);
1864 else /* R/W access via SERPAR */
1865 return dib8096p_tuner_rw_serpar(i2c_adap, msg, num);
1870 static u32 dib8096p_i2c_func(struct i2c_adapter *adapter)
1872 return I2C_FUNC_I2C;
1875 static struct i2c_algorithm dib8096p_tuner_xfer_algo = {
1876 .master_xfer = dib8096p_tuner_xfer,
1877 .functionality = dib8096p_i2c_func,
1880 static struct i2c_adapter *dib8096p_get_i2c_tuner(struct dvb_frontend *fe)
1882 struct dib8000_state *st = fe->demodulator_priv;
1883 return &st->dib8096p_tuner_adap;
1886 static int dib8096p_tuner_sleep(struct dvb_frontend *fe, int onoff)
1888 struct dib8000_state *state = fe->demodulator_priv;
1891 dprintk("sleep dib8096p: %d", onoff);
1893 en_cur_state = dib8000_read_word(state, 1922);
1895 /* LNAs and MIX are ON and therefore it is a valid configuration */
1896 if (en_cur_state > 0xff)
1897 state->tuner_enable = en_cur_state ;
1900 en_cur_state &= 0x00ff;
1902 if (state->tuner_enable != 0)
1903 en_cur_state = state->tuner_enable;
1906 dib8000_write_word(state, 1922, en_cur_state);
1911 static const s32 lut_1000ln_mant[] =
1913 908, 7003, 7090, 7170, 7244, 7313, 7377, 7438, 7495, 7549, 7600
1916 static s32 dib8000_get_adc_power(struct dvb_frontend *fe, u8 mode)
1918 struct dib8000_state *state = fe->demodulator_priv;
1919 u32 ix = 0, tmp_val = 0, exp = 0, mant = 0;
1922 val = dib8000_read32(state, 384);
1925 while (tmp_val >>= 1)
1927 mant = (val * 1000 / (1<<exp));
1928 ix = (u8)((mant-1000)/100); /* index of the LUT */
1929 val = (lut_1000ln_mant[ix] + 693*(exp-20) - 6908);
1930 val = (val*256)/1000;
1935 static int dib8090p_get_dc_power(struct dvb_frontend *fe, u8 IQ)
1937 struct dib8000_state *state = fe->demodulator_priv;
1942 val = dib8000_read_word(state, 403);
1945 val = dib8000_read_word(state, 404);
1954 static void dib8000_update_timf(struct dib8000_state *state)
1956 u32 timf = state->timf = dib8000_read32(state, 435);
1958 dib8000_write_word(state, 29, (u16) (timf >> 16));
1959 dib8000_write_word(state, 30, (u16) (timf & 0xffff));
1960 dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
1963 static u32 dib8000_ctrl_timf(struct dvb_frontend *fe, uint8_t op, uint32_t timf)
1965 struct dib8000_state *state = fe->demodulator_priv;
1968 case DEMOD_TIMF_SET:
1971 case DEMOD_TIMF_UPDATE:
1972 dib8000_update_timf(state);
1974 case DEMOD_TIMF_GET:
1977 dib8000_set_bandwidth(state->fe[0], 6000);
1982 static const u16 adc_target_16dB[11] = {
1983 7250, 7238, 7264, 7309, 7338, 7382, 7427, 7456, 7500, 7544, 7574
1986 static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
1988 static u16 dib8000_set_layer(struct dib8000_state *state, u8 layer_index, u16 max_constellation)
1990 u8 cr, constellation, time_intlv;
1991 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
1993 switch (c->layer[layer_index].modulation) {
2009 switch (c->layer[layer_index].fec) {
2028 time_intlv = fls(c->layer[layer_index].interleaving);
2029 if (time_intlv > 3 && !(time_intlv == 4 && c->isdbt_sb_mode == 1))
2032 dib8000_write_word(state, 2 + layer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3) | time_intlv);
2033 if (c->layer[layer_index].segment_count > 0) {
2034 switch (max_constellation) {
2037 if (c->layer[layer_index].modulation == QAM_16 || c->layer[layer_index].modulation == QAM_64)
2038 max_constellation = c->layer[layer_index].modulation;
2041 if (c->layer[layer_index].modulation == QAM_64)
2042 max_constellation = c->layer[layer_index].modulation;
2047 return max_constellation;
2050 static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_noise_cnt -0.002, P_adp_regul_ext 0.02, P_adp_noise_ext -0.001 */
2051 static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_noise_cnt -0.004, P_adp_regul_ext 0.02, P_adp_noise_ext -0.002 */
2052 static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp_noise_cnt -0.01, P_adp_regul_ext 0.1, P_adp_noise_ext -0.002 */
2053 static u16 dib8000_adp_fine_tune(struct dib8000_state *state, u16 max_constellation)
2055 u16 i, ana_gain = 0;
2058 /* channel estimation fine configuration */
2059 switch (max_constellation) {
2070 adp = &adp_Qdefault[0];
2074 for (i = 0; i < 4; i++)
2075 dib8000_write_word(state, 215 + i, adp[i]);
2080 static void dib8000_update_ana_gain(struct dib8000_state *state, u16 ana_gain)
2084 dib8000_write_word(state, 116, ana_gain);
2086 /* update ADC target depending on ana_gain */
2087 if (ana_gain) { /* set -16dB ADC target for ana_gain=-1 */
2088 for (i = 0; i < 10; i++)
2089 dib8000_write_word(state, 80 + i, adc_target_16dB[i]);
2090 } else { /* set -22dB ADC target for ana_gain=0 */
2091 for (i = 0; i < 10; i++)
2092 dib8000_write_word(state, 80 + i, adc_target_16dB[i] - 355);
2096 static void dib8000_load_ana_fe_coefs(struct dib8000_state *state, const s16 *ana_fe)
2100 if (state->isdbt_cfg_loaded == 0)
2101 for (mode = 0; mode < 24; mode++)
2102 dib8000_write_word(state, 117 + mode, ana_fe[mode]);
2105 static const u16 lut_prbs_2k[14] = {
2106 0, 0x423, 0x009, 0x5C7, 0x7A6, 0x3D8, 0x527, 0x7FF, 0x79B, 0x3D6, 0x3A2, 0x53B, 0x2F4, 0x213
2108 static const u16 lut_prbs_4k[14] = {
2109 0, 0x208, 0x0C3, 0x7B9, 0x423, 0x5C7, 0x3D8, 0x7FF, 0x3D6, 0x53B, 0x213, 0x029, 0x0D0, 0x48E
2111 static const u16 lut_prbs_8k[14] = {
2112 0, 0x740, 0x069, 0x7DD, 0x208, 0x7B9, 0x5C7, 0x7FF, 0x53B, 0x029, 0x48E, 0x4C4, 0x367, 0x684
2115 static u16 dib8000_get_init_prbs(struct dib8000_state *state, u16 subchannel)
2117 int sub_channel_prbs_group = 0;
2119 sub_channel_prbs_group = (subchannel / 3) + 1;
2120 dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x", sub_channel_prbs_group, subchannel, lut_prbs_8k[sub_channel_prbs_group]);
2122 switch (state->fe[0]->dtv_property_cache.transmission_mode) {
2123 case TRANSMISSION_MODE_2K:
2124 return lut_prbs_2k[sub_channel_prbs_group];
2125 case TRANSMISSION_MODE_4K:
2126 return lut_prbs_4k[sub_channel_prbs_group];
2128 case TRANSMISSION_MODE_8K:
2129 return lut_prbs_8k[sub_channel_prbs_group];
2133 static void dib8000_set_13seg_channel(struct dib8000_state *state)
2136 u16 coff_pow = 0x2800;
2138 state->seg_mask = 0x1fff; /* All 13 segments enabled */
2140 /* ---- COFF ---- Carloff, the most robust --- */
2141 if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13 segments */
2142 dib8000_write_word(state, 180, (16 << 6) | 9);
2143 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2);
2145 for (i = 0; i < 6; i++)
2146 dib8000_write_word(state, 181+i, coff_pow);
2148 /* P_ctrl_corm_thres4pre_freq_inh=1, P_ctrl_pre_freq_mode_sat=1 */
2149 /* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len=1 */
2150 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1);
2152 /* P_ctrl_pre_freq_win_len=8, P_ctrl_pre_freq_thres_lockin=6 */
2153 dib8000_write_word(state, 340, (8 << 6) | (6 << 0));
2154 /* P_ctrl_pre_freq_thres_lockout=4, P_small_use_tmcc/ac/cp=1 */
2155 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0));
2157 dib8000_write_word(state, 228, 0); /* default value */
2158 dib8000_write_word(state, 265, 31); /* default value */
2159 dib8000_write_word(state, 205, 0x200f); /* init value */
2163 * make the cpil_coff_lock more robust but slower p_coff_winlen
2164 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2167 if (state->cfg.pll->ifreq == 0)
2168 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_seg_inh */
2170 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_13seg);
2173 static void dib8000_set_subchannel_prbs(struct dib8000_state *state, u16 init_prbs)
2177 reg_1 = dib8000_read_word(state, 1);
2178 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */
2181 static void dib8000_small_fine_tune(struct dib8000_state *state)
2185 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2187 dib8000_write_word(state, 352, state->seg_diff_mask);
2188 dib8000_write_word(state, 353, state->seg_mask);
2190 /* P_small_coef_ext_enable=ISDB-Tsb, P_small_narrow_band=ISDB-Tsb, P_small_last_seg=13, P_small_offset_num_car=5 */
2191 dib8000_write_word(state, 351, (c->isdbt_sb_mode << 9) | (c->isdbt_sb_mode << 8) | (13 << 4) | 5);
2193 if (c->isdbt_sb_mode) {
2194 /* ---- SMALL ---- */
2195 switch (c->transmission_mode) {
2196 case TRANSMISSION_MODE_2K:
2197 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2198 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2199 ncoeff = coeff_2k_sb_1seg_dqpsk;
2200 else /* QPSK or QAM */
2201 ncoeff = coeff_2k_sb_1seg;
2202 } else { /* 3-segments */
2203 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2204 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2205 ncoeff = coeff_2k_sb_3seg_0dqpsk_1dqpsk;
2206 else /* QPSK or QAM on external segments */
2207 ncoeff = coeff_2k_sb_3seg_0dqpsk;
2208 } else { /* QPSK or QAM on central segment */
2209 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2210 ncoeff = coeff_2k_sb_3seg_1dqpsk;
2211 else /* QPSK or QAM on external segments */
2212 ncoeff = coeff_2k_sb_3seg;
2216 case TRANSMISSION_MODE_4K:
2217 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2218 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2219 ncoeff = coeff_4k_sb_1seg_dqpsk;
2220 else /* QPSK or QAM */
2221 ncoeff = coeff_4k_sb_1seg;
2222 } else { /* 3-segments */
2223 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2224 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2225 ncoeff = coeff_4k_sb_3seg_0dqpsk_1dqpsk;
2226 else /* QPSK or QAM on external segments */
2227 ncoeff = coeff_4k_sb_3seg_0dqpsk;
2228 } else { /* QPSK or QAM on central segment */
2229 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2230 ncoeff = coeff_4k_sb_3seg_1dqpsk;
2231 else /* QPSK or QAM on external segments */
2232 ncoeff = coeff_4k_sb_3seg;
2236 case TRANSMISSION_MODE_AUTO:
2237 case TRANSMISSION_MODE_8K:
2239 if (c->isdbt_partial_reception == 0) { /* 1-seg */
2240 if (c->layer[0].modulation == DQPSK) /* DQPSK */
2241 ncoeff = coeff_8k_sb_1seg_dqpsk;
2242 else /* QPSK or QAM */
2243 ncoeff = coeff_8k_sb_1seg;
2244 } else { /* 3-segments */
2245 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */
2246 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2247 ncoeff = coeff_8k_sb_3seg_0dqpsk_1dqpsk;
2248 else /* QPSK or QAM on external segments */
2249 ncoeff = coeff_8k_sb_3seg_0dqpsk;
2250 } else { /* QPSK or QAM on central segment */
2251 if (c->layer[1].modulation == DQPSK) /* DQPSK on external segments */
2252 ncoeff = coeff_8k_sb_3seg_1dqpsk;
2253 else /* QPSK or QAM on external segments */
2254 ncoeff = coeff_8k_sb_3seg;
2260 for (i = 0; i < 8; i++)
2261 dib8000_write_word(state, 343 + i, ncoeff[i]);
2265 static const u16 coff_thres_1seg[3] = {300, 150, 80};
2266 static const u16 coff_thres_3seg[3] = {350, 300, 250};
2267 static void dib8000_set_sb_channel(struct dib8000_state *state)
2269 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2273 if (c->transmission_mode == TRANSMISSION_MODE_2K || c->transmission_mode == TRANSMISSION_MODE_4K) {
2274 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */
2275 dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shift = 1 */
2277 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */
2278 dib8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */
2281 if (c->isdbt_partial_reception == 1) /* 3-segments */
2282 state->seg_mask = 0x00E0;
2283 else /* 1-segment */
2284 state->seg_mask = 0x0040;
2286 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2288 /* ---- COFF ---- Carloff, the most robust --- */
2289 /* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_val=1, P_coff_one_seg=~partial_rcpt, P_coff_use_tmcc=1, P_coff_use_ac=1 */
2290 dib8000_write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_reception & 1) << 2) | 0x3);
2292 dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_freq_thres_lockin=8 */
2293 dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres_lockout=6, P_small_use_tmcc/ac/cp=1 */
2295 /* Sound Broadcasting mode 1 seg */
2296 if (c->isdbt_partial_reception == 0) {
2297 /* P_coff_winlen=63, P_coff_thres_lock=15, P_coff_one_seg_width = (P_mode == 3) , P_coff_one_seg_sym = (P_mode-1) */
2298 if (state->mode == 3)
2299 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14));
2301 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14));
2303 /* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 5, P_pre_freq_win_len=4 */
2304 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4);
2305 coff = &coff_thres_1seg[0];
2306 } else { /* Sound Broadcasting mode 3 seg */
2307 dib8000_write_word(state, 180, 0x1fcf | (1 << 14));
2308 /* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 4, P_pre_freq_win_len=4 */
2309 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4);
2310 coff = &coff_thres_3seg[0];
2313 dib8000_write_word(state, 228, 1); /* P_2d_mode_byp=1 */
2314 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */
2316 if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K)
2317 dib8000_write_word(state, 265, 15); /* P_equal_noise_sel = 15 */
2319 /* Write COFF thres */
2320 for (i = 0 ; i < 3; i++) {
2321 dib8000_write_word(state, 181+i, coff[i]);
2322 dib8000_write_word(state, 184+i, coff[i]);
2326 * make the cpil_coff_lock more robust but slower p_coff_winlen
2327 * 6bits; p_coff_thres_lock 6bits (for coff lock if needed)
2330 dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask); /* P_equal_noise_seg_inh */
2332 if (c->isdbt_partial_reception == 0)
2333 dib8000_write_word(state, 178, 64); /* P_fft_powrange = 64 */
2335 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2338 static void dib8000_set_isdbt_common_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
2340 u16 p_cfr_left_edge = 0, p_cfr_right_edge = 0;
2341 u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ;
2342 u16 max_constellation = DQPSK;
2344 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2347 c->isdbt_partial_reception = 1;
2350 dib8000_write_word(state, 10, (seq << 4));
2353 state->mode = fft_to_mode(state);
2356 tmp = dib8000_read_word(state, 1);
2357 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3));
2359 dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_reception & 1) << 5) | ((c->isdbt_sb_mode & 1) << 4));
2361 /* signal optimization parameter */
2362 if (c->isdbt_partial_reception) {
2363 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0];
2364 for (i = 1; i < 3; i++)
2365 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2366 for (i = 0; i < nbseg_diff; i++)
2367 state->seg_diff_mask |= 1 << permu_seg[i+1];
2369 for (i = 0; i < 3; i++)
2370 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count;
2371 for (i = 0; i < nbseg_diff; i++)
2372 state->seg_diff_mask |= 1 << permu_seg[i];
2375 if (state->seg_diff_mask)
2376 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200);
2378 dib8000_write_word(state, 268, (2 << 9) | 39); /*init value */
2380 for (i = 0; i < 3; i++)
2381 max_constellation = dib8000_set_layer(state, i, max_constellation);
2382 if (autosearching == 0) {
2383 state->layer_b_nb_seg = c->layer[1].segment_count;
2384 state->layer_c_nb_seg = c->layer[2].segment_count;
2387 /* WRITE: Mode & Diff mask */
2388 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask);
2390 state->differential_constellation = (state->seg_diff_mask != 0);
2392 /* channel estimation fine configuration */
2393 ana_gain = dib8000_adp_fine_tune(state, max_constellation);
2395 /* update ana_gain depending on max constellation */
2396 dib8000_update_ana_gain(state, ana_gain);
2398 /* ---- ANA_FE ---- */
2399 if (c->isdbt_partial_reception) /* 3-segments */
2400 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_3seg);
2402 dib8000_load_ana_fe_coefs(state, ana_fe_coeff_1seg); /* 1-segment */
2404 /* TSB or ISDBT ? apply it now */
2405 if (c->isdbt_sb_mode) {
2406 dib8000_set_sb_channel(state);
2407 if (c->isdbt_sb_subchannel < 14)
2408 init_prbs = dib8000_get_init_prbs(state, c->isdbt_sb_subchannel);
2412 dib8000_set_13seg_channel(state);
2417 dib8000_small_fine_tune(state);
2419 dib8000_set_subchannel_prbs(state, init_prbs);
2421 /* ---- CHAN_BLK ---- */
2422 for (i = 0; i < 13; i++) {
2423 if ((((~state->seg_diff_mask) >> i) & 1) == 1) {
2424 p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i - 1)) & 1) == 0));
2425 p_cfr_right_edge += (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0));
2428 dib8000_write_word(state, 222, p_cfr_left_edge); /* p_cfr_left_edge */
2429 dib8000_write_word(state, 223, p_cfr_right_edge); /* p_cfr_right_edge */
2430 /* "P_cspu_left_edge" & "P_cspu_right_edge" not used => do not care */
2432 dib8000_write_word(state, 189, ~state->seg_mask | state->seg_diff_mask); /* P_lmod4_seg_inh */
2433 dib8000_write_word(state, 192, ~state->seg_mask | state->seg_diff_mask); /* P_pha3_seg_inh */
2434 dib8000_write_word(state, 225, ~state->seg_mask | state->seg_diff_mask); /* P_tac_seg_inh */
2437 dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_eq_inh */
2439 dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be able to find the DQPSK channels. */
2441 dib8000_write_word(state, 211, state->seg_mask & (~state->seg_diff_mask)); /* P_des_seg_enabled */
2442 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */
2444 dib8000_write_word(state, 178, 32); /* P_fft_powrange = 32 */
2446 /* ---- TMCC ---- */
2447 for (i = 0; i < 3; i++)
2448 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ;
2450 /* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */
2451 /* Threshold is set at 1/4 of max power. */
2452 tmcc_pow *= (1 << (9-2));
2453 dib8000_write_word(state, 290, tmcc_pow); /* P_tmcc_dec_thres_2k */
2454 dib8000_write_word(state, 291, tmcc_pow); /* P_tmcc_dec_thres_4k */
2455 dib8000_write_word(state, 292, tmcc_pow); /* P_tmcc_dec_thres_8k */
2456 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */
2458 /* ---- PHA3 ---- */
2459 if (state->isdbt_cfg_loaded == 0)
2460 dib8000_write_word(state, 250, 3285); /* p_2d_hspeed_thr0 */
2462 state->isdbt_cfg_loaded = 0;
2465 static u32 dib8000_wait_lock(struct dib8000_state *state, u32 internal,
2466 u32 wait0_ms, u32 wait1_ms, u32 wait2_ms)
2468 u32 value = 0; /* P_search_end0 wait time */
2469 u16 reg = 11; /* P_search_end0 start addr */
2471 for (reg = 11; reg < 16; reg += 2) {
2473 if (state->revision == 0x8090)
2474 value = internal * wait1_ms;
2476 value = internal * wait0_ms;
2477 } else if (reg == 13)
2478 value = internal * wait1_ms;
2480 value = internal * wait2_ms;
2481 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff));
2482 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff));
2487 static int dib8000_autosearch_start(struct dvb_frontend *fe)
2489 struct dib8000_state *state = fe->demodulator_priv;
2490 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2492 u32 value, internal = state->cfg.pll->internal;
2494 if (state->revision == 0x8090)
2495 internal = dib8000_read32(state, 23) / 1000;
2497 if ((state->revision >= 0x8002) &&
2498 (state->autosearch_state == AS_SEARCHING_FFT)) {
2499 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */
2500 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */
2502 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P_mode = 0, P_restart_search=1 */
2503 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */
2504 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */
2505 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */
2506 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */
2507 dib8000_write_word(state, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_search_maxtrial=0 */
2509 if (state->revision == 0x8090)
2510 value = dib8000_wait_lock(state, internal, 10, 10, 10); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2512 value = dib8000_wait_lock(state, internal, 20, 20, 20); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2514 dib8000_write_word(state, 17, 0);
2515 dib8000_write_word(state, 18, 200); /* P_search_rstst = 200 */
2516 dib8000_write_word(state, 19, 0);
2517 dib8000_write_word(state, 20, 400); /* P_search_rstend = 400 */
2518 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */
2519 dib8000_write_word(state, 22, value & 0xffff);
2521 if (state->revision == 0x8090)
2522 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */
2524 dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha = 3 */
2525 dib8000_write_word(state, 355, 2); /* P_search_param_max = 2 */
2527 /* P_search_param_select = (1 | 1<<4 | 1 << 8) */
2528 dib8000_write_word(state, 356, 0);
2529 dib8000_write_word(state, 357, 0x111);
2531 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart_ccg = 1 */
2532 dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 */
2533 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_restart_search = 0; */
2534 } else if ((state->revision >= 0x8002) &&
2535 (state->autosearch_state == AS_SEARCHING_GUARD)) {
2536 c->transmission_mode = TRANSMISSION_MODE_8K;
2537 c->guard_interval = GUARD_INTERVAL_1_8;
2539 c->layer[0].modulation = QAM_64;
2540 c->layer[0].fec = FEC_2_3;
2541 c->layer[0].interleaving = 0;
2542 c->layer[0].segment_count = 13;
2545 c->transmission_mode = state->found_nfft;
2547 dib8000_set_isdbt_common_channel(state, slist, 1);
2549 /* set lock_mask values */
2550 dib8000_write_word(state, 6, 0x4);
2551 if (state->revision == 0x8090)
2552 dib8000_write_word(state, 7, ((1 << 12) | (1 << 11) | (1 << 10)));/* tmcc_dec_lock, tmcc_sync_lock, tmcc_data_lock, tmcc_bch_uncor */
2554 dib8000_write_word(state, 7, 0x8);
2555 dib8000_write_word(state, 8, 0x1000);
2557 /* set lock_mask wait time values */
2558 if (state->revision == 0x8090)
2559 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2561 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2563 dib8000_write_word(state, 355, 3); /* P_search_param_max = 3 */
2565 /* P_search_param_select = 0xf; look for the 4 different guard intervals */
2566 dib8000_write_word(state, 356, 0);
2567 dib8000_write_word(state, 357, 0xf);
2569 value = dib8000_read_word(state, 0);
2570 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2571 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
2572 dib8000_write_word(state, 0, (u16)value);
2575 c->layer[0].modulation = QAM_64;
2576 c->layer[0].fec = FEC_2_3;
2577 c->layer[0].interleaving = 0;
2578 c->layer[0].segment_count = 13;
2579 if (!c->isdbt_sb_mode)
2580 c->layer[0].segment_count = 13;
2582 /* choose the right list, in sb, always do everything */
2583 if (c->isdbt_sb_mode) {
2585 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13));
2587 if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2588 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2589 c->transmission_mode = TRANSMISSION_MODE_8K;
2590 c->guard_interval = GUARD_INTERVAL_1_8;
2592 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 to have autosearch start ok with mode2 */
2594 c->guard_interval = GUARD_INTERVAL_1_8;
2598 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2599 c->transmission_mode = TRANSMISSION_MODE_8K;
2601 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */
2606 dprintk("Using list for autosearch : %d", slist);
2608 dib8000_set_isdbt_common_channel(state, slist, 1);
2610 /* set lock_mask values */
2611 dib8000_write_word(state, 6, 0x4);
2612 if (state->revision == 0x8090)
2613 dib8000_write_word(state, 7, (1 << 12) | (1 << 11) | (1 << 10));
2615 dib8000_write_word(state, 7, 0x8);
2616 dib8000_write_word(state, 8, 0x1000);
2618 /* set lock_mask wait time values */
2619 if (state->revision == 0x8090)
2620 dib8000_wait_lock(state, internal, 50, 200, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2622 dib8000_wait_lock(state, internal, 50, 100, 1000); /* time in ms configure P_search_end0 P_search_end1 P_search_end2 */
2624 value = dib8000_read_word(state, 0);
2625 dib8000_write_word(state, 0, (u16)((1 << 15) | value));
2626 dib8000_read_word(state, 1284); /* reset the INT. n_irq_pending */
2627 dib8000_write_word(state, 0, (u16)value);
2632 static int dib8000_autosearch_irq(struct dvb_frontend *fe)
2634 struct dib8000_state *state = fe->demodulator_priv;
2635 u16 irq_pending = dib8000_read_word(state, 1284);
2637 if ((state->revision >= 0x8002) &&
2638 (state->autosearch_state == AS_SEARCHING_FFT)) {
2639 if (irq_pending & 0x1) {
2640 dprintk("dib8000_autosearch_irq: max correlation result available");
2644 if (irq_pending & 0x1) { /* failed */
2645 dprintk("dib8000_autosearch_irq failed");
2649 if (irq_pending & 0x2) { /* succeeded */
2650 dprintk("dib8000_autosearch_irq succeeded");
2655 return 0; // still pending
2658 static void dib8000_viterbi_state(struct dib8000_state *state, u8 onoff)
2662 tmp = dib8000_read_word(state, 771);
2663 if (onoff) /* start P_restart_chd : channel_decoder */
2664 dib8000_write_word(state, 771, tmp & 0xfffd);
2665 else /* stop P_restart_chd : channel_decoder */
2666 dib8000_write_word(state, 771, tmp | (1<<1));
2669 static void dib8000_set_dds(struct dib8000_state *state, s32 offset_khz)
2671 s16 unit_khz_dds_val;
2672 u32 abs_offset_khz = ABS(offset_khz);
2673 u32 dds = state->cfg.pll->ifreq & 0x1ffffff;
2674 u8 invert = !!(state->cfg.pll->ifreq & (1 << 25));
2677 if (state->revision == 0x8090) {
2679 unit_khz_dds_val = (1<<26) / (dib8000_read32(state, 23) / 1000);
2681 dds = (1 << 26) - (abs_offset_khz * unit_khz_dds_val);
2683 dds = (abs_offset_khz * unit_khz_dds_val);
2686 dds = (1<<26) - dds;
2689 unit_khz_dds_val = (u16) (67108864 / state->cfg.pll->internal);
2692 unit_khz_dds_val *= -1;
2696 dds -= abs_offset_khz * unit_khz_dds_val;
2698 dds += abs_offset_khz * unit_khz_dds_val;
2701 dprintk("setting a DDS frequency offset of %c%dkHz", invert ? '-' : ' ', dds / unit_khz_dds_val);
2703 if (abs_offset_khz <= (state->cfg.pll->internal / ratio)) {
2704 /* Max dds offset is the half of the demod freq */
2705 dib8000_write_word(state, 26, invert);
2706 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff);
2707 dib8000_write_word(state, 28, (u16)(dds & 0xffff));
2711 static void dib8000_set_frequency_offset(struct dib8000_state *state)
2713 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2716 int total_dds_offset_khz;
2718 if (state->fe[0]->ops.tuner_ops.get_frequency)
2719 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf);
2721 current_rf = c->frequency;
2723 total_dds_offset_khz = (int)current_rf - (int)c->frequency / 1000;
2725 if (c->isdbt_sb_mode) {
2726 state->subchannel = c->isdbt_sb_subchannel;
2728 i = dib8000_read_word(state, 26) & 1; /* P_dds_invspec */
2729 dib8000_write_word(state, 26, c->inversion ^ i);
2731 if (state->cfg.pll->ifreq == 0) { /* low if tuner */
2732 if ((c->inversion ^ i) == 0)
2733 dib8000_write_word(state, 26, dib8000_read_word(state, 26) | 1);
2735 if ((c->inversion ^ i) == 0)
2736 total_dds_offset_khz *= -1;
2740 dprintk("%dkhz tuner offset (frequency = %dHz & current_rf = %dHz) total_dds_offset_hz = %d", c->frequency - current_rf, c->frequency, current_rf, total_dds_offset_khz);
2742 /* apply dds offset now */
2743 dib8000_set_dds(state, total_dds_offset_khz);
2746 static u16 LUT_isdbt_symbol_duration[4] = { 26, 101, 63 };
2748 static u32 dib8000_get_symbol_duration(struct dib8000_state *state)
2750 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2753 switch (c->transmission_mode) {
2754 case TRANSMISSION_MODE_2K:
2757 case TRANSMISSION_MODE_4K:
2761 case TRANSMISSION_MODE_AUTO:
2762 case TRANSMISSION_MODE_8K:
2767 return (LUT_isdbt_symbol_duration[i] / (c->bandwidth_hz / 1000)) + 1;
2770 static void dib8000_set_isdbt_loop_params(struct dib8000_state *state, enum param_loop_step loop_step)
2772 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2773 u16 reg_32 = 0, reg_37 = 0;
2775 switch (loop_step) {
2777 if (c->isdbt_sb_mode) {
2778 if (c->isdbt_partial_reception == 0) {
2779 reg_32 = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_corm_thres=0x40 */
2780 reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (10-P_mode) */
2781 } else { /* Sound Broadcasting mode 3 seg */
2782 reg_32 = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_corm_thres=0x60 */
2783 reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = (9-P_mode) */
2785 } else { /* 13-seg start conf offset loop parameters */
2786 reg_32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_corm_thres=0x80 */
2787 reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P_ctrl_sfreq_step = 9 */
2791 if (c->isdbt_sb_mode) {
2792 if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */
2793 reg_32 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_corm_thres=0x40*/
2794 reg_37 = (12-state->mode) | ((5 + state->mode) << 5);
2795 } else { /* Sound Broadcasting mode 3 seg */
2796 reg_32 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_corm_thres=0x60 */
2797 reg_37 = (11-state->mode) | ((5 + state->mode) << 5);
2799 } else { /* 13 seg */
2800 reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_thres=0x80 */
2801 reg_37 = ((5+state->mode) << 5) | (10 - state->mode);
2805 dib8000_write_word(state, 32, reg_32);
2806 dib8000_write_word(state, 37, reg_37);
2809 static void dib8000_demod_restart(struct dib8000_state *state)
2811 dib8000_write_word(state, 770, 0x4000);
2812 dib8000_write_word(state, 770, 0x0000);
2816 static void dib8000_set_sync_wait(struct dib8000_state *state)
2818 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2821 /* P_dvsy_sync_wait - reuse mode */
2822 switch (c->transmission_mode) {
2823 case TRANSMISSION_MODE_8K:
2826 case TRANSMISSION_MODE_4K:
2830 case TRANSMISSION_MODE_2K:
2835 if (state->cfg.diversity_delay == 0)
2836 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + 48; /* add 50% SFN margin + compensate for one DVSY-fifo */
2838 sync_wait = (sync_wait * (1 << (c->guard_interval)) * 3) / 2 + state->cfg.diversity_delay; /* add 50% SFN margin + compensate for DVSY-fifo */
2840 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4));
2843 static unsigned long dib8000_get_timeout(struct dib8000_state *state, u32 delay, enum timeout_mode mode)
2845 if (mode == SYMBOL_DEPENDENT_ON)
2846 delay *= state->symbol_duration;
2848 return jiffies + usecs_to_jiffies(delay * 100);
2851 static s32 dib8000_get_status(struct dvb_frontend *fe)
2853 struct dib8000_state *state = fe->demodulator_priv;
2854 return state->status;
2857 static enum frontend_tune_state dib8000_get_tune_state(struct dvb_frontend *fe)
2859 struct dib8000_state *state = fe->demodulator_priv;
2860 return state->tune_state;
2863 static int dib8000_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
2865 struct dib8000_state *state = fe->demodulator_priv;
2867 state->tune_state = tune_state;
2871 static int dib8000_tune_restart_from_demod(struct dvb_frontend *fe)
2873 struct dib8000_state *state = fe->demodulator_priv;
2875 state->status = FE_STATUS_TUNE_PENDING;
2876 state->tune_state = CT_DEMOD_START;
2880 static u16 dib8000_read_lock(struct dvb_frontend *fe)
2882 struct dib8000_state *state = fe->demodulator_priv;
2884 if (state->revision == 0x8090)
2885 return dib8000_read_word(state, 570);
2886 return dib8000_read_word(state, 568);
2889 static int dib8090p_init_sdram(struct dib8000_state *state)
2892 dprintk("init sdram");
2894 reg = dib8000_read_word(state, 274) & 0xfff0;
2895 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */
2897 dib8000_write_word(state, 1803, (7 << 2));
2899 reg = dib8000_read_word(state, 1280);
2900 dib8000_write_word(state, 1280, reg | (1 << 2)); /* force restart P_restart_sdram */
2901 dib8000_write_word(state, 1280, reg); /* release restart P_restart_sdram */
2907 * is_manual_mode - Check if TMCC should be used for parameters settings
2908 * @c: struct dvb_frontend_properties
2910 * By default, TMCC table should be used for parameter settings on most
2911 * usercases. However, sometimes it is desirable to lock the demod to
2912 * use the manual parameters.
2914 * On manual mode, the current dib8000_tune state machine is very restrict:
2915 * It requires that both per-layer and per-transponder parameters to be
2916 * properly specified, otherwise the device won't lock.
2918 * Check if all those conditions are properly satisfied before allowing
2919 * the device to use the manual frequency lock mode.
2921 static int is_manual_mode(struct dtv_frontend_properties *c)
2925 /* Use auto mode on DVB-T compat mode */
2926 if (c->delivery_system != SYS_ISDBT)
2930 * Transmission mode is only detected on auto mode, currently
2932 if (c->transmission_mode == TRANSMISSION_MODE_AUTO) {
2933 dprintk("transmission mode auto");
2938 * Guard interval is only detected on auto mode, currently
2940 if (c->guard_interval == GUARD_INTERVAL_AUTO) {
2941 dprintk("guard interval auto");
2946 * If no layer is enabled, assume auto mode, as at least one
2947 * layer should be enabled
2949 if (!c->isdbt_layer_enabled) {
2950 dprintk("no layer modulation specified");
2955 * Check if the per-layer parameters aren't auto and
2956 * disable a layer if segment count is 0 or invalid.
2958 for (i = 0; i < 3; i++) {
2959 if (!(c->isdbt_layer_enabled & 1 << i))
2962 if ((c->layer[i].segment_count > 13) ||
2963 (c->layer[i].segment_count == 0)) {
2964 c->isdbt_layer_enabled &= ~(1 << i);
2968 n_segs += c->layer[i].segment_count;
2970 if ((c->layer[i].modulation == QAM_AUTO) ||
2971 (c->layer[i].fec == FEC_AUTO)) {
2972 dprintk("layer %c has either modulation or FEC auto",
2979 * Userspace specified a wrong number of segments.
2980 * fallback to auto mode.
2982 if (n_segs == 0 || n_segs > 13) {
2983 dprintk("number of segments is invalid");
2987 /* Everything looks ok for manual mode */
2991 static int dib8000_tune(struct dvb_frontend *fe)
2993 struct dib8000_state *state = fe->demodulator_priv;
2994 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
2995 enum frontend_tune_state *tune_state = &state->tune_state;
2997 u16 locks, deeper_interleaver = 0, i;
2998 int ret = 1; /* 1 symbol duration (in 100us unit) delay most of the time */
3000 unsigned long *timeout = &state->timeout;
3001 unsigned long now = jiffies;
3002 #ifdef DIB8000_AGC_FREEZE
3006 u32 corm[4] = {0, 0, 0, 0};
3007 u8 find_index, max_value;
3010 if (*tune_state < CT_DEMOD_STOP)
3011 dprintk("IN: context status = %d, TUNE_STATE %d autosearch step = %u jiffies = %lu",
3012 state->channel_parameters_set, *tune_state, state->autosearch_state, now);
3015 switch (*tune_state) {
3016 case CT_DEMOD_START: /* 30 */
3017 dib8000_reset_stats(fe);
3019 if (state->revision == 0x8090)
3020 dib8090p_init_sdram(state);
3021 state->status = FE_STATUS_TUNE_PENDING;
3022 state->channel_parameters_set = is_manual_mode(c);
3024 dprintk("Tuning channel on %s search mode",
3025 state->channel_parameters_set ? "manual" : "auto");
3027 dib8000_viterbi_state(state, 0); /* force chan dec in restart */
3030 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60);
3032 dib8000_set_frequency_offset(state);
3033 dib8000_set_bandwidth(fe, c->bandwidth_hz / 1000);
3035 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */
3036 #ifdef DIB8000_AGC_FREEZE
3037 if (state->revision != 0x8090) {
3038 state->agc1_max = dib8000_read_word(state, 108);
3039 state->agc1_min = dib8000_read_word(state, 109);
3040 state->agc2_max = dib8000_read_word(state, 110);
3041 state->agc2_min = dib8000_read_word(state, 111);
3042 agc1 = dib8000_read_word(state, 388);
3043 agc2 = dib8000_read_word(state, 389);
3044 dib8000_write_word(state, 108, agc1);
3045 dib8000_write_word(state, 109, agc1);
3046 dib8000_write_word(state, 110, agc2);
3047 dib8000_write_word(state, 111, agc2);
3050 state->autosearch_state = AS_SEARCHING_FFT;
3051 state->found_nfft = TRANSMISSION_MODE_AUTO;
3052 state->found_guard = GUARD_INTERVAL_AUTO;
3053 *tune_state = CT_DEMOD_SEARCH_NEXT;
3054 } else { /* we already know the channel struct so TUNE only ! */
3055 state->autosearch_state = AS_DONE;
3056 *tune_state = CT_DEMOD_STEP_3;
3058 state->symbol_duration = dib8000_get_symbol_duration(state);
3061 case CT_DEMOD_SEARCH_NEXT: /* 51 */
3062 dib8000_autosearch_start(fe);
3063 if (state->revision == 0x8090)
3067 *tune_state = CT_DEMOD_STEP_1;
3070 case CT_DEMOD_STEP_1: /* 31 */
3071 switch (dib8000_autosearch_irq(fe)) {
3073 state->status = FE_STATUS_TUNE_FAILED;
3074 state->autosearch_state = AS_DONE;
3075 *tune_state = CT_DEMOD_STOP; /* else we are done here */
3077 case 2: /* Succes */
3078 state->status = FE_STATUS_FFT_SUCCESS; /* signal to the upper layer, that there was a channel found and the parameters can be read */
3079 *tune_state = CT_DEMOD_STEP_3;
3080 if (state->autosearch_state == AS_SEARCHING_GUARD)
3081 *tune_state = CT_DEMOD_STEP_2;
3083 state->autosearch_state = AS_DONE;
3085 case 3: /* Autosearch FFT max correlation endded */
3086 *tune_state = CT_DEMOD_STEP_2;
3091 case CT_DEMOD_STEP_2:
3092 switch (state->autosearch_state) {
3093 case AS_SEARCHING_FFT:
3094 /* searching for the correct FFT */
3095 if (state->revision == 0x8090) {
3096 corm[2] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3097 corm[1] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3098 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601));
3100 corm[2] = (dib8000_read_word(state, 594) << 16) | (dib8000_read_word(state, 595));
3101 corm[1] = (dib8000_read_word(state, 596) << 16) | (dib8000_read_word(state, 597));
3102 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599));
3104 /* dprintk("corm fft: %u %u %u", corm[0], corm[1], corm[2]); */
3107 for (find_index = 1 ; find_index < 3 ; find_index++) {
3108 if (corm[max_value] < corm[find_index])
3109 max_value = find_index ;
3112 switch (max_value) {
3114 state->found_nfft = TRANSMISSION_MODE_2K;
3117 state->found_nfft = TRANSMISSION_MODE_4K;
3121 state->found_nfft = TRANSMISSION_MODE_8K;
3124 /* dprintk("Autosearch FFT has found Mode %d", max_value + 1); */
3126 *tune_state = CT_DEMOD_SEARCH_NEXT;
3127 state->autosearch_state = AS_SEARCHING_GUARD;
3128 if (state->revision == 0x8090)
3133 case AS_SEARCHING_GUARD:
3134 /* searching for the correct guard interval */
3135 if (state->revision == 0x8090)
3136 state->found_guard = dib8000_read_word(state, 572) & 0x3;
3138 state->found_guard = dib8000_read_word(state, 570) & 0x3;
3139 /* dprintk("guard interval found=%i", state->found_guard); */
3141 *tune_state = CT_DEMOD_STEP_3;
3144 /* the demod should never be in this state */
3145 state->status = FE_STATUS_TUNE_FAILED;
3146 state->autosearch_state = AS_DONE;
3147 *tune_state = CT_DEMOD_STOP; /* else we are done here */
3152 case CT_DEMOD_STEP_3: /* 33 */
3153 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_1);
3154 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */
3155 *tune_state = CT_DEMOD_STEP_4;
3158 case CT_DEMOD_STEP_4: /* (34) */
3159 dib8000_demod_restart(state);
3161 dib8000_set_sync_wait(state);
3162 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff);
3164 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */
3165 /* coff should lock over P_coff_winlen ofdm symbols : give 3 times this length to lock */
3166 *timeout = dib8000_get_timeout(state, 2 * locks, SYMBOL_DEPENDENT_ON);
3167 *tune_state = CT_DEMOD_STEP_5;
3170 case CT_DEMOD_STEP_5: /* (35) */
3171 locks = dib8000_read_lock(fe);
3172 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */
3173 dib8000_update_timf(state); /* we achieved a coff_cpil_lock - it's time to update the timf */
3174 if (!state->differential_constellation) {
3175 /* 2 times lmod4_win_len + 10 symbols (pipe delay after coff + nb to compute a 1st correlation) */
3176 *timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEPENDENT_ON);
3177 *tune_state = CT_DEMOD_STEP_7;
3179 *tune_state = CT_DEMOD_STEP_8;
3181 } else if (time_after(now, *timeout)) {
3182 *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3186 case CT_DEMOD_STEP_6: /* (36) if there is an input (diversity) */
3187 if ((state->fe[1] != NULL) && (state->output_mode != OUTMODE_DIVERSITY)) {
3188 /* if there is a diversity fe in input and this fe is has not already failled : wait here until this this fe has succedeed or failled */
3189 if (dib8000_get_status(state->fe[1]) <= FE_STATUS_STD_SUCCESS) /* Something is locked on the input fe */
3190 *tune_state = CT_DEMOD_STEP_8; /* go for mpeg */
3191 else if (dib8000_get_status(state->fe[1]) >= FE_STATUS_TUNE_TIME_TOO_SHORT) { /* fe in input failled also, break the current one */
3192 *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3193 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3194 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3195 state->status = FE_STATUS_TUNE_FAILED;
3198 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3199 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3200 *tune_state = CT_DEMOD_STOP; /* else we are done here ; step 8 will close the loops and exit */
3201 state->status = FE_STATUS_TUNE_FAILED;
3205 case CT_DEMOD_STEP_7: /* 37 */
3206 locks = dib8000_read_lock(fe);
3207 if (locks & (1<<10)) { /* lmod4_lock */
3208 ret = 14; /* wait for 14 symbols */
3209 *tune_state = CT_DEMOD_STEP_8;
3210 } else if (time_after(now, *timeout))
3211 *tune_state = CT_DEMOD_STEP_6; /* goto check for diversity input connection */
3214 case CT_DEMOD_STEP_8: /* 38 */
3215 dib8000_viterbi_state(state, 1); /* start viterbi chandec */
3216 dib8000_set_isdbt_loop_params(state, LOOP_TUNE_2);
3218 /* mpeg will never lock on this condition because init_prbs is not set : search for it !*/
3219 if (c->isdbt_sb_mode
3220 && c->isdbt_sb_subchannel < 14
3221 && !state->differential_constellation) {
3222 state->subchannel = 0;
3223 *tune_state = CT_DEMOD_STEP_11;
3225 *tune_state = CT_DEMOD_STEP_9;
3226 state->status = FE_STATUS_LOCKED;
3230 case CT_DEMOD_STEP_9: /* 39 */
3231 if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable of deinterleaving : esram */
3232 /* defines timeout for mpeg lock depending on interleaver length of longest layer */
3233 for (i = 0; i < 3; i++) {
3234 if (c->layer[i].interleaving >= deeper_interleaver) {
3235 dprintk("layer%i: time interleaver = %d ", i, c->layer[i].interleaving);
3236 if (c->layer[i].segment_count > 0) { /* valid layer */
3237 deeper_interleaver = c->layer[0].interleaving;
3238 state->longest_intlv_layer = i;
3243 if (deeper_interleaver == 0)
3244 locks = 2; /* locks is the tmp local variable name */
3245 else if (deeper_interleaver == 3)
3248 locks = 2 * deeper_interleaver;
3250 if (state->diversity_onoff != 0) /* because of diversity sync */
3253 *timeout = now + msecs_to_jiffies(200 * locks); /* give the mpeg lock 800ms if sram is present */
3254 dprintk("Deeper interleaver mode = %d on layer %d : timeout mult factor = %d => will use timeout = %ld",
3255 deeper_interleaver, state->longest_intlv_layer, locks, *timeout);
3257 *tune_state = CT_DEMOD_STEP_10;
3259 *tune_state = CT_DEMOD_STOP;
3262 case CT_DEMOD_STEP_10: /* 40 */
3263 locks = dib8000_read_lock(fe);
3264 if (locks&(1<<(7-state->longest_intlv_layer))) { /* mpeg lock : check the longest one */
3265 dprintk("ISDB-T layer locks: Layer A %s, Layer B %s, Layer C %s",
3266 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3267 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3268 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3269 if (c->isdbt_sb_mode
3270 && c->isdbt_sb_subchannel < 14
3271 && !state->differential_constellation)
3272 /* signal to the upper layer, that there was a channel found and the parameters can be read */
3273 state->status = FE_STATUS_DEMOD_SUCCESS;
3275 state->status = FE_STATUS_DATA_LOCKED;
3276 *tune_state = CT_DEMOD_STOP;
3277 } else if (time_after(now, *timeout)) {
3278 if (c->isdbt_sb_mode
3279 && c->isdbt_sb_subchannel < 14
3280 && !state->differential_constellation) { /* continue to try init prbs autosearch */
3281 state->subchannel += 3;
3282 *tune_state = CT_DEMOD_STEP_11;
3283 } else { /* we are done mpeg of the longest interleaver xas not locking but let's try if an other layer has locked in the same time */
3284 if (locks & (0x7 << 5)) {
3285 dprintk("Not all ISDB-T layers locked in %d ms: Layer A %s, Layer B %s, Layer C %s",
3286 jiffies_to_msecs(now - *timeout),
3287 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3288 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled",
3289 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled");
3291 state->status = FE_STATUS_DATA_LOCKED;
3293 state->status = FE_STATUS_TUNE_FAILED;
3294 *tune_state = CT_DEMOD_STOP;
3299 case CT_DEMOD_STEP_11: /* 41 : init prbs autosearch */
3300 if (state->subchannel <= 41) {
3301 dib8000_set_subchannel_prbs(state, dib8000_get_init_prbs(state, state->subchannel));
3302 *tune_state = CT_DEMOD_STEP_9;
3304 *tune_state = CT_DEMOD_STOP;
3305 state->status = FE_STATUS_TUNE_FAILED;
3313 /* tuning is finished - cleanup the demod */
3314 switch (*tune_state) {
3315 case CT_DEMOD_STOP: /* (42) */
3316 #ifdef DIB8000_AGC_FREEZE
3317 if ((state->revision != 0x8090) && (state->agc1_max != 0)) {
3318 dib8000_write_word(state, 108, state->agc1_max);
3319 dib8000_write_word(state, 109, state->agc1_min);
3320 dib8000_write_word(state, 110, state->agc2_max);
3321 dib8000_write_word(state, 111, state->agc2_min);
3322 state->agc1_max = 0;
3323 state->agc1_min = 0;
3324 state->agc2_max = 0;
3325 state->agc2_min = 0;
3334 if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3))
3335 return ret * state->symbol_duration;
3336 if ((ret > 0) && (ret < state->symbol_duration))
3337 return state->symbol_duration; /* at least one symbol */
3341 static int dib8000_wakeup(struct dvb_frontend *fe)
3343 struct dib8000_state *state = fe->demodulator_priv;
3347 dib8000_set_power_mode(state, DIB8000_POWER_ALL);
3348 dib8000_set_adc_state(state, DIBX000_ADC_ON);
3349 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0)
3350 dprintk("could not start Slow ADC");
3352 if (state->revision == 0x8090)
3353 dib8000_sad_calib(state);
3355 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3356 ret = state->fe[index_frontend]->ops.init(state->fe[index_frontend]);
3364 static int dib8000_sleep(struct dvb_frontend *fe)
3366 struct dib8000_state *state = fe->demodulator_priv;
3370 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3371 ret = state->fe[index_frontend]->ops.sleep(state->fe[index_frontend]);
3376 if (state->revision != 0x8090)
3377 dib8000_set_output_mode(fe, OUTMODE_HIGH_Z);
3378 dib8000_set_power_mode(state, DIB8000_POWER_INTERFACE_ONLY);
3379 return dib8000_set_adc_state(state, DIBX000_SLOW_ADC_OFF) | dib8000_set_adc_state(state, DIBX000_ADC_OFF);
3382 static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat);
3384 static int dib8000_get_frontend(struct dvb_frontend *fe)
3386 struct dib8000_state *state = fe->demodulator_priv;
3388 fe_status_t stat = 0;
3389 u8 index_frontend, sub_index_frontend;
3391 fe->dtv_property_cache.bandwidth_hz = 6000000;
3394 * If called to early, get_frontend makes dib8000_tune to either
3395 * not lock or not sync. This causes dvbv5-scan/dvbv5-zap to fail.
3396 * So, let's just return if frontend 0 has not locked.
3398 dib8000_read_status(fe, &stat);
3399 if (!(stat & FE_HAS_SYNC))
3402 dprintk("dib8000_get_frontend: TMCC lock");
3403 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3404 state->fe[index_frontend]->ops.read_status(state->fe[index_frontend], &stat);
3405 if (stat&FE_HAS_SYNC) {
3406 dprintk("TMCC lock on the slave%i", index_frontend);
3407 /* synchronize the cache with the other frontends */
3408 state->fe[index_frontend]->ops.get_frontend(state->fe[index_frontend]);
3409 for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_index_frontend] != NULL); sub_index_frontend++) {
3410 if (sub_index_frontend != index_frontend) {
3411 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3412 state->fe[sub_index_frontend]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3413 state->fe[sub_index_frontend]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3414 state->fe[sub_index_frontend]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3415 state->fe[sub_index_frontend]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3416 for (i = 0; i < 3; i++) {
3417 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3418 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3419 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3420 state->fe[sub_index_frontend]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3428 fe->dtv_property_cache.isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1;
3430 if (state->revision == 0x8090)
3431 val = dib8000_read_word(state, 572);
3433 val = dib8000_read_word(state, 570);
3434 fe->dtv_property_cache.inversion = (val & 0x40) >> 6;
3435 switch ((val & 0x30) >> 4) {
3437 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
3438 dprintk("dib8000_get_frontend: transmission mode 2K");
3441 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_4K;
3442 dprintk("dib8000_get_frontend: transmission mode 4K");
3446 fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_8K;
3447 dprintk("dib8000_get_frontend: transmission mode 8K");
3451 switch (val & 0x3) {
3453 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
3454 dprintk("dib8000_get_frontend: Guard Interval = 1/32 ");
3457 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_16;
3458 dprintk("dib8000_get_frontend: Guard Interval = 1/16 ");
3461 dprintk("dib8000_get_frontend: Guard Interval = 1/8 ");
3462 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_8;
3465 dprintk("dib8000_get_frontend: Guard Interval = 1/4 ");
3466 fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_4;
3470 val = dib8000_read_word(state, 505);
3471 fe->dtv_property_cache.isdbt_partial_reception = val & 1;
3472 dprintk("dib8000_get_frontend: partial_reception = %d ", fe->dtv_property_cache.isdbt_partial_reception);
3474 for (i = 0; i < 3; i++) {
3477 val = dib8000_read_word(state, 493 + i) & 0x0f;
3478 fe->dtv_property_cache.layer[i].segment_count = val;
3480 if (val == 0 || val > 13)
3486 dprintk("dib8000_get_frontend: Layer %d segments = %d ",
3487 i, fe->dtv_property_cache.layer[i].segment_count);
3489 val = dib8000_read_word(state, 499 + i) & 0x3;
3490 /* Interleaving can be 0, 1, 2 or 4 */
3493 fe->dtv_property_cache.layer[i].interleaving = val;
3495 dprintk("dib8000_get_frontend: Layer %d time_intlv = %d ",
3496 i, fe->dtv_property_cache.layer[i].interleaving);
3498 val = dib8000_read_word(state, 481 + i);
3499 switch (val & 0x7) {
3501 fe->dtv_property_cache.layer[i].fec = FEC_1_2;
3503 dprintk("dib8000_get_frontend: Layer %d Code Rate = 1/2 ", i);
3506 fe->dtv_property_cache.layer[i].fec = FEC_2_3;
3508 dprintk("dib8000_get_frontend: Layer %d Code Rate = 2/3 ", i);
3511 fe->dtv_property_cache.layer[i].fec = FEC_3_4;
3513 dprintk("dib8000_get_frontend: Layer %d Code Rate = 3/4 ", i);
3516 fe->dtv_property_cache.layer[i].fec = FEC_5_6;
3518 dprintk("dib8000_get_frontend: Layer %d Code Rate = 5/6 ", i);
3521 fe->dtv_property_cache.layer[i].fec = FEC_7_8;
3523 dprintk("dib8000_get_frontend: Layer %d Code Rate = 7/8 ", i);
3527 val = dib8000_read_word(state, 487 + i);
3528 switch (val & 0x3) {
3530 fe->dtv_property_cache.layer[i].modulation = DQPSK;
3532 dprintk("dib8000_get_frontend: Layer %d DQPSK ", i);
3535 fe->dtv_property_cache.layer[i].modulation = QPSK;
3537 dprintk("dib8000_get_frontend: Layer %d QPSK ", i);
3540 fe->dtv_property_cache.layer[i].modulation = QAM_16;
3542 dprintk("dib8000_get_frontend: Layer %d QAM16 ", i);
3546 fe->dtv_property_cache.layer[i].modulation = QAM_64;
3548 dprintk("dib8000_get_frontend: Layer %d QAM64 ", i);
3553 /* synchronize the cache with the other frontends */
3554 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3555 state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode = fe->dtv_property_cache.isdbt_sb_mode;
3556 state->fe[index_frontend]->dtv_property_cache.inversion = fe->dtv_property_cache.inversion;
3557 state->fe[index_frontend]->dtv_property_cache.transmission_mode = fe->dtv_property_cache.transmission_mode;
3558 state->fe[index_frontend]->dtv_property_cache.guard_interval = fe->dtv_property_cache.guard_interval;
3559 state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception = fe->dtv_property_cache.isdbt_partial_reception;
3560 for (i = 0; i < 3; i++) {
3561 state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count = fe->dtv_property_cache.layer[i].segment_count;
3562 state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving = fe->dtv_property_cache.layer[i].interleaving;
3563 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = fe->dtv_property_cache.layer[i].fec;
3564 state->fe[index_frontend]->dtv_property_cache.layer[i].modulation = fe->dtv_property_cache.layer[i].modulation;
3570 static int dib8000_set_frontend(struct dvb_frontend *fe)
3572 struct dib8000_state *state = fe->demodulator_priv;
3573 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3574 int l, i, active, time, time_slave = 0;
3575 u8 exit_condition, index_frontend;
3576 unsigned long delay, callback_time;
3578 if (c->frequency == 0) {
3579 dprintk("dib8000: must at least specify frequency ");
3583 if (c->bandwidth_hz == 0) {
3584 dprintk("dib8000: no bandwidth specified, set to default ");
3585 c->bandwidth_hz = 6000000;
3588 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3589 /* synchronization of the cache */
3590 state->fe[index_frontend]->dtv_property_cache.delivery_system = SYS_ISDBT;
3591 memcpy(&state->fe[index_frontend]->dtv_property_cache, &fe->dtv_property_cache, sizeof(struct dtv_frontend_properties));
3593 /* set output mode and diversity input */
3594 if (state->revision != 0x8090) {
3595 dib8000_set_diversity_in(state->fe[index_frontend], 1);
3596 if (index_frontend != 0)
3597 dib8000_set_output_mode(state->fe[index_frontend],
3600 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3602 dib8096p_set_diversity_in(state->fe[index_frontend], 1);
3603 if (index_frontend != 0)
3604 dib8096p_set_output_mode(state->fe[index_frontend],
3607 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z);
3610 /* tune the tuner */
3611 if (state->fe[index_frontend]->ops.tuner_ops.set_params)
3612 state->fe[index_frontend]->ops.tuner_ops.set_params(state->fe[index_frontend]);
3614 dib8000_set_tune_state(state->fe[index_frontend], CT_AGC_START);
3617 /* turn off the diversity of the last chip */
3618 if (state->revision != 0x8090)
3619 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0);
3621 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0);
3623 /* start up the AGC */
3625 time = dib8000_agc_startup(state->fe[0]);
3626 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3627 time_slave = dib8000_agc_startup(state->fe[index_frontend]);
3630 else if ((time_slave != 0) && (time_slave > time))
3637 * Despite dib8000_agc_startup returns time at a 0.1 ms range,
3638 * the actual sleep time depends on CONFIG_HZ. The worse case
3639 * is when CONFIG_HZ=100. In such case, the minimum granularity
3640 * is 10ms. On some real field tests, the tuner sometimes don't
3641 * lock when this timer is lower than 10ms. So, enforce a 10ms
3644 time = 10 * (time + 99)/100;
3645 usleep_range(time * 1000, (time + 1) * 1000);
3647 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3648 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_AGC_STOP) {
3653 } while (exit_condition == 0);
3655 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3656 dib8000_set_tune_state(state->fe[index_frontend], CT_DEMOD_START);
3661 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3662 delay = dib8000_tune(state->fe[index_frontend]);
3664 delay = jiffies + usecs_to_jiffies(100 * delay);
3665 if (!callback_time || delay < callback_time)
3666 callback_time = delay;
3669 /* we are in autosearch */
3670 if (state->channel_parameters_set == 0) { /* searching */
3671 if ((dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_DEMOD_SUCCESS) || (dib8000_get_status(state->fe[index_frontend]) == FE_STATUS_FFT_SUCCESS)) {
3672 dprintk("autosearch succeeded on fe%i", index_frontend);
3673 dib8000_get_frontend(state->fe[index_frontend]); /* we read the channel parameters from the frontend which was successful */
3674 state->channel_parameters_set = 1;
3676 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) {
3677 if (l != index_frontend) { /* and for all frontend except the successful one */
3678 dprintk("Restarting frontend %d\n", l);
3679 dib8000_tune_restart_from_demod(state->fe[l]);
3681 state->fe[l]->dtv_property_cache.isdbt_sb_mode = state->fe[index_frontend]->dtv_property_cache.isdbt_sb_mode;
3682 state->fe[l]->dtv_property_cache.inversion = state->fe[index_frontend]->dtv_property_cache.inversion;
3683 state->fe[l]->dtv_property_cache.transmission_mode = state->fe[index_frontend]->dtv_property_cache.transmission_mode;
3684 state->fe[l]->dtv_property_cache.guard_interval = state->fe[index_frontend]->dtv_property_cache.guard_interval;
3685 state->fe[l]->dtv_property_cache.isdbt_partial_reception = state->fe[index_frontend]->dtv_property_cache.isdbt_partial_reception;
3686 for (i = 0; i < 3; i++) {
3687 state->fe[l]->dtv_property_cache.layer[i].segment_count = state->fe[index_frontend]->dtv_property_cache.layer[i].segment_count;
3688 state->fe[l]->dtv_property_cache.layer[i].interleaving = state->fe[index_frontend]->dtv_property_cache.layer[i].interleaving;
3689 state->fe[l]->dtv_property_cache.layer[i].fec = state->fe[index_frontend]->dtv_property_cache.layer[i].fec;
3690 state->fe[l]->dtv_property_cache.layer[i].modulation = state->fe[index_frontend]->dtv_property_cache.layer[i].modulation;
3698 /* tuning is done when the master frontend is done (failed or success) */
3699 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED ||
3700 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED ||
3701 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) {
3703 /* we need to wait for all frontends to be finished */
3704 for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3705 if (dib8000_get_tune_state(state->fe[index_frontend]) != CT_DEMOD_STOP)
3709 dprintk("tuning done with status %d", dib8000_get_status(state->fe[0]));
3712 if ((active == 1) && (callback_time == 0)) {
3713 dprintk("strange callback time something went wrong");
3717 while ((active == 1) && (time_before(jiffies, callback_time)))
3721 /* set output mode */
3722 if (state->revision != 0x8090)
3723 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode);
3725 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode);
3726 if (state->cfg.enMpegOutput == 0) {
3727 dib8096p_setDibTxMux(state, MPEG_ON_DIBTX);
3728 dib8096p_setHostBusMux(state, DIBTX_ON_HOSTBUS);
3735 static int dib8000_get_stats(struct dvb_frontend *fe, fe_status_t stat);
3737 static int dib8000_read_status(struct dvb_frontend *fe, fe_status_t * stat)
3739 struct dib8000_state *state = fe->demodulator_priv;
3740 u16 lock_slave = 0, lock;
3743 lock = dib8000_read_lock(fe);
3744 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3745 lock_slave |= dib8000_read_lock(state->fe[index_frontend]);
3749 if (((lock >> 13) & 1) || ((lock_slave >> 13) & 1))
3750 *stat |= FE_HAS_SIGNAL;
3752 if (((lock >> 8) & 1) || ((lock_slave >> 8) & 1)) /* Equal */
3753 *stat |= FE_HAS_CARRIER;
3755 if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */
3756 *stat |= FE_HAS_SYNC;
3758 if ((((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) && ((lock >> 5) & 7)) /* FEC MPEG */
3759 *stat |= FE_HAS_LOCK;
3761 if (((lock >> 12) & 1) || ((lock_slave >> 12) & 1)) {
3762 lock = dib8000_read_word(state, 554); /* Viterbi Layer A */
3764 *stat |= FE_HAS_VITERBI;
3766 lock = dib8000_read_word(state, 555); /* Viterbi Layer B */
3768 *stat |= FE_HAS_VITERBI;
3770 lock = dib8000_read_word(state, 556); /* Viterbi Layer C */
3772 *stat |= FE_HAS_VITERBI;
3774 dib8000_get_stats(fe, *stat);
3779 static int dib8000_read_ber(struct dvb_frontend *fe, u32 * ber)
3781 struct dib8000_state *state = fe->demodulator_priv;
3784 if (state->revision == 0x8090)
3785 *ber = (dib8000_read_word(state, 562) << 16) |
3786 dib8000_read_word(state, 563);
3788 *ber = (dib8000_read_word(state, 560) << 16) |
3789 dib8000_read_word(state, 561);
3793 static int dib8000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
3795 struct dib8000_state *state = fe->demodulator_priv;
3797 /* packet error on 13 seg */
3798 if (state->revision == 0x8090)
3799 *unc = dib8000_read_word(state, 567);
3801 *unc = dib8000_read_word(state, 565);
3805 static int dib8000_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
3807 struct dib8000_state *state = fe->demodulator_priv;
3812 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++) {
3813 state->fe[index_frontend]->ops.read_signal_strength(state->fe[index_frontend], &val);
3814 if (val > 65535 - *strength)
3820 val = 65535 - dib8000_read_word(state, 390);
3821 if (val > 65535 - *strength)
3828 static u32 dib8000_get_snr(struct dvb_frontend *fe)
3830 struct dib8000_state *state = fe->demodulator_priv;
3834 if (state->revision != 0x8090)
3835 val = dib8000_read_word(state, 542);
3837 val = dib8000_read_word(state, 544);
3838 n = (val >> 6) & 0xff;
3840 if ((exp & 0x20) != 0)
3844 if (state->revision != 0x8090)
3845 val = dib8000_read_word(state, 543);
3847 val = dib8000_read_word(state, 545);
3848 s = (val >> 6) & 0xff;
3850 if ((exp & 0x20) != 0)
3855 u32 t = (s/n) << 16;
3856 return t + ((s << 16) - n*t) / n;
3861 static int dib8000_read_snr(struct dvb_frontend *fe, u16 * snr)
3863 struct dib8000_state *state = fe->demodulator_priv;
3867 snr_master = dib8000_get_snr(fe);
3868 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL); index_frontend++)
3869 snr_master += dib8000_get_snr(state->fe[index_frontend]);
3871 if ((snr_master >> 16) != 0) {
3872 snr_master = 10*intlog10(snr_master>>16);
3873 *snr = snr_master / ((1 << 24) / 10);
3881 struct per_layer_regs {
3885 static const struct per_layer_regs per_layer_regs[] = {
3891 struct linear_segments {
3897 * Table to estimate signal strength in dBm.
3898 * This table was empirically determinated by measuring the signal
3899 * strength generated by a DTA-2111 RF generator directly connected into
3900 * a dib8076 device (a PixelView PV-D231U stick), using a good quality
3901 * 3 meters RC6 cable and good RC6 connectors.
3902 * The real value can actually be different on other devices, depending
3903 * on several factors, like if LNA is enabled or not, if diversity is
3904 * enabled, type of connectors, etc.
3905 * Yet, it is better to use this measure in dB than a random non-linear
3906 * percentage value, especially for antenna adjustments.
3907 * On my tests, the precision of the measure using this table is about
3908 * 0.5 dB, with sounds reasonable enough.
3910 static struct linear_segments strength_to_db_table[] = {
3911 { 55953, 108500 }, /* -22.5 dBm */
3924 { 50117, 96000 }, /* -35 dBm */
3940 { 42010, 80000 }, /* -51 dBm */
3944 static u32 interpolate_value(u32 value, struct linear_segments *segments,
3952 if (value >= segments[0].x)
3953 return segments[0].y;
3954 if (value < segments[len-1].x)
3955 return segments[len-1].y;
3957 for (i = 1; i < len - 1; i++) {
3958 /* If value is identical, no need to interpolate */
3959 if (value == segments[i].x)
3960 return segments[i].y;
3961 if (value > segments[i].x)
3965 /* Linear interpolation between the two (x,y) points */
3966 dy = segments[i - 1].y - segments[i].y;
3967 dx = segments[i - 1].x - segments[i].x;
3969 tmp64 = value - segments[i].x;
3972 ret = segments[i].y + tmp64;
3977 static u32 dib8000_get_time_us(struct dvb_frontend *fe, int layer)
3979 struct dib8000_state *state = fe->demodulator_priv;
3980 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
3981 int ini_layer, end_layer, i;
3984 int guard, rate_num, rate_denum = 1, bits_per_symbol, nsegs;
3985 int interleaving = 0, fft_div;
3989 end_layer = layer + 1;
3995 switch (c->guard_interval) {
3996 case GUARD_INTERVAL_1_4:
3999 case GUARD_INTERVAL_1_8:
4002 case GUARD_INTERVAL_1_16:
4006 case GUARD_INTERVAL_1_32:
4011 switch (c->transmission_mode) {
4012 case TRANSMISSION_MODE_2K:
4015 case TRANSMISSION_MODE_4K:
4019 case TRANSMISSION_MODE_8K:
4025 for (i = ini_layer; i < end_layer; i++) {
4026 nsegs = c->layer[i].segment_count;
4027 if (nsegs == 0 || nsegs > 13)
4030 switch (c->layer[i].modulation) {
4033 bits_per_symbol = 2;
4036 bits_per_symbol = 4;
4040 bits_per_symbol = 6;
4044 switch (c->layer[i].fec) {
4068 interleaving = c->layer[i].interleaving;
4070 denom += bits_per_symbol * rate_num * fft_div * nsegs * 384;
4073 /* If all goes wrong, wait for 1s for the next stats */
4077 /* Estimate the period for the total bit rate */
4078 time_us = rate_denum * (1008 * 1562500L);
4080 do_div(tmp64, guard);
4081 time_us = time_us + tmp64;
4082 time_us += denom / 2;
4083 do_div(time_us, denom);
4085 tmp = 1008 * 96 * interleaving;
4086 time_us += tmp + tmp / guard;
4091 static int dib8000_get_stats(struct dvb_frontend *fe, fe_status_t stat)
4093 struct dib8000_state *state = fe->demodulator_priv;
4094 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache;
4096 int show_per_stats = 0;
4097 u32 time_us = 0, snr, val;
4102 /* Get Signal strength */
4103 dib8000_read_signal_strength(fe, &strength);
4105 db = interpolate_value(val,
4106 strength_to_db_table,
4107 ARRAY_SIZE(strength_to_db_table)) - 131000;
4108 c->strength.stat[0].svalue = db;
4110 /* UCB/BER/CNR measures require lock */
4111 if (!(stat & FE_HAS_LOCK)) {
4113 c->block_count.len = 1;
4114 c->block_error.len = 1;
4115 c->post_bit_error.len = 1;
4116 c->post_bit_count.len = 1;
4117 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4118 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4119 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4120 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4121 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;
4125 /* Check if time for stats was elapsed */
4126 if (time_after(jiffies, state->per_jiffies_stats)) {
4127 state->per_jiffies_stats = jiffies + msecs_to_jiffies(1000);
4130 snr = dib8000_get_snr(fe);
4131 for (i = 1; i < MAX_NUMBER_OF_FRONTENDS; i++) {
4133 snr += dib8000_get_snr(state->fe[i]);
4138 snr = 10 * intlog10(snr);
4139 snr = (1000L * snr) >> 24;
4143 c->cnr.stat[0].svalue = snr;
4144 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;
4146 /* Get UCB measures */
4147 dib8000_read_unc_blocks(fe, &val);
4148 if (val < state->init_ucb)
4149 state->init_ucb += 0x100000000LL;
4151 c->block_error.stat[0].scale = FE_SCALE_COUNTER;
4152 c->block_error.stat[0].uvalue = val + state->init_ucb;
4154 /* Estimate the number of packets based on bitrate */
4156 time_us = dib8000_get_time_us(fe, -1);
4159 blocks = 1250000ULL * 1000000ULL;
4160 do_div(blocks, time_us * 8 * 204);
4161 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4162 c->block_count.stat[0].uvalue += blocks;
4168 /* Get post-BER measures */
4169 if (time_after(jiffies, state->ber_jiffies_stats)) {
4170 time_us = dib8000_get_time_us(fe, -1);
4171 state->ber_jiffies_stats = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4173 dprintk("Next all layers stats available in %u us.", time_us);
4175 dib8000_read_ber(fe, &val);
4176 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;
4177 c->post_bit_error.stat[0].uvalue += val;
4179 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;
4180 c->post_bit_count.stat[0].uvalue += 100000000;
4183 if (state->revision < 0x8002)
4186 c->block_error.len = 4;
4187 c->post_bit_error.len = 4;
4188 c->post_bit_count.len = 4;
4190 for (i = 0; i < 3; i++) {
4191 unsigned nsegs = c->layer[i].segment_count;
4193 if (nsegs == 0 || nsegs > 13)
4198 if (time_after(jiffies, state->ber_jiffies_stats_layer[i])) {
4199 time_us = dib8000_get_time_us(fe, i);
4201 state->ber_jiffies_stats_layer[i] = jiffies + msecs_to_jiffies((time_us + 500) / 1000);
4202 dprintk("Next layer %c stats will be available in %u us\n",
4205 val = dib8000_read_word(state, per_layer_regs[i].ber);
4206 c->post_bit_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4207 c->post_bit_error.stat[1 + i].uvalue += val;
4209 c->post_bit_count.stat[1 + i].scale = FE_SCALE_COUNTER;
4210 c->post_bit_count.stat[1 + i].uvalue += 100000000;
4213 if (show_per_stats) {
4214 val = dib8000_read_word(state, per_layer_regs[i].per);
4216 c->block_error.stat[1 + i].scale = FE_SCALE_COUNTER;
4217 c->block_error.stat[1 + i].uvalue += val;
4220 time_us = dib8000_get_time_us(fe, i);
4222 blocks = 1250000ULL * 1000000ULL;
4223 do_div(blocks, time_us * 8 * 204);
4224 c->block_count.stat[0].scale = FE_SCALE_COUNTER;
4225 c->block_count.stat[0].uvalue += blocks;
4232 static int dib8000_set_slave_frontend(struct dvb_frontend *fe, struct dvb_frontend *fe_slave)
4234 struct dib8000_state *state = fe->demodulator_priv;
4235 u8 index_frontend = 1;
4237 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4239 if (index_frontend < MAX_NUMBER_OF_FRONTENDS) {
4240 dprintk("set slave fe %p to index %i", fe_slave, index_frontend);
4241 state->fe[index_frontend] = fe_slave;
4245 dprintk("too many slave frontend");
4249 static int dib8000_remove_slave_frontend(struct dvb_frontend *fe)
4251 struct dib8000_state *state = fe->demodulator_priv;
4252 u8 index_frontend = 1;
4254 while ((index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] != NULL))
4256 if (index_frontend != 1) {
4257 dprintk("remove slave fe %p (index %i)", state->fe[index_frontend-1], index_frontend-1);
4258 state->fe[index_frontend] = NULL;
4262 dprintk("no frontend to be removed");
4266 static struct dvb_frontend *dib8000_get_slave_frontend(struct dvb_frontend *fe, int slave_index)
4268 struct dib8000_state *state = fe->demodulator_priv;
4270 if (slave_index >= MAX_NUMBER_OF_FRONTENDS)
4272 return state->fe[slave_index];
4275 static int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods,
4276 u8 default_addr, u8 first_addr, u8 is_dib8096p)
4280 struct i2c_device client = {.adap = host };
4282 client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
4283 if (!client.i2c_write_buffer) {
4284 dprintk("%s: not enough memory", __func__);
4287 client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
4288 if (!client.i2c_read_buffer) {
4289 dprintk("%s: not enough memory", __func__);
4291 goto error_memory_read;
4293 client.i2c_buffer_lock = kzalloc(sizeof(struct mutex), GFP_KERNEL);
4294 if (!client.i2c_buffer_lock) {
4295 dprintk("%s: not enough memory", __func__);
4297 goto error_memory_lock;
4299 mutex_init(client.i2c_buffer_lock);
4301 for (k = no_of_demods - 1; k >= 0; k--) {
4302 /* designated i2c address */
4303 new_addr = first_addr + (k << 1);
4305 client.addr = new_addr;
4307 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */
4308 if (dib8000_identify(&client) == 0) {
4309 /* sram lead in, rdy */
4311 dib8000_i2c_write16(&client, 1287, 0x0003);
4312 client.addr = default_addr;
4313 if (dib8000_identify(&client) == 0) {
4314 dprintk("#%d: not identified", k);
4320 /* start diversity to pull_down div_str - just for i2c-enumeration */
4321 dib8000_i2c_write16(&client, 1286, (1 << 10) | (4 << 6));
4323 /* set new i2c address and force divstart */
4324 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2);
4325 client.addr = new_addr;
4326 dib8000_identify(&client);
4328 dprintk("IC %d initialized (to i2c_address 0x%x)", k, new_addr);
4331 for (k = 0; k < no_of_demods; k++) {
4332 new_addr = first_addr | (k << 1);
4333 client.addr = new_addr;
4336 dib8000_i2c_write16(&client, 1285, new_addr << 2);
4338 /* deactivate div - it was just for i2c-enumeration */
4339 dib8000_i2c_write16(&client, 1286, 0);
4343 kfree(client.i2c_buffer_lock);
4345 kfree(client.i2c_read_buffer);
4347 kfree(client.i2c_write_buffer);
4352 static int dib8000_fe_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings *tune)
4354 tune->min_delay_ms = 1000;
4355 tune->step_size = 0;
4356 tune->max_drift = 0;
4360 static void dib8000_release(struct dvb_frontend *fe)
4362 struct dib8000_state *st = fe->demodulator_priv;
4365 for (index_frontend = 1; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (st->fe[index_frontend] != NULL); index_frontend++)
4366 dvb_frontend_detach(st->fe[index_frontend]);
4368 dibx000_exit_i2c_master(&st->i2c_master);
4369 i2c_del_adapter(&st->dib8096p_tuner_adap);
4374 static struct i2c_adapter *dib8000_get_i2c_master(struct dvb_frontend *fe, enum dibx000_i2c_interface intf, int gating)
4376 struct dib8000_state *st = fe->demodulator_priv;
4377 return dibx000_get_i2c_adapter(&st->i2c_master, intf, gating);
4380 static int dib8000_pid_filter_ctrl(struct dvb_frontend *fe, u8 onoff)
4382 struct dib8000_state *st = fe->demodulator_priv;
4383 u16 val = dib8000_read_word(st, 299) & 0xffef;
4384 val |= (onoff & 0x1) << 4;
4386 dprintk("pid filter enabled %d", onoff);
4387 return dib8000_write_word(st, 299, val);
4390 static int dib8000_pid_filter(struct dvb_frontend *fe, u8 id, u16 pid, u8 onoff)
4392 struct dib8000_state *st = fe->demodulator_priv;
4393 dprintk("Index %x, PID %d, OnOff %d", id, pid, onoff);
4394 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0);
4397 static const struct dvb_frontend_ops dib8000_ops = {
4398 .delsys = { SYS_ISDBT },
4400 .name = "DiBcom 8000 ISDB-T",
4401 .frequency_min = 44250000,
4402 .frequency_max = 867250000,
4403 .frequency_stepsize = 62500,
4404 .caps = FE_CAN_INVERSION_AUTO |
4405 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
4406 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
4407 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
4408 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER | FE_CAN_HIERARCHY_AUTO,
4411 .release = dib8000_release,
4413 .init = dib8000_wakeup,
4414 .sleep = dib8000_sleep,
4416 .set_frontend = dib8000_set_frontend,
4417 .get_tune_settings = dib8000_fe_get_tune_settings,
4418 .get_frontend = dib8000_get_frontend,
4420 .read_status = dib8000_read_status,
4421 .read_ber = dib8000_read_ber,
4422 .read_signal_strength = dib8000_read_signal_strength,
4423 .read_snr = dib8000_read_snr,
4424 .read_ucblocks = dib8000_read_unc_blocks,
4427 static struct dvb_frontend *dib8000_init(struct i2c_adapter *i2c_adap, u8 i2c_addr, struct dib8000_config *cfg)
4429 struct dvb_frontend *fe;
4430 struct dib8000_state *state;
4432 dprintk("dib8000_init");
4434 state = kzalloc(sizeof(struct dib8000_state), GFP_KERNEL);
4437 fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
4441 memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
4442 state->i2c.adap = i2c_adap;
4443 state->i2c.addr = i2c_addr;
4444 state->i2c.i2c_write_buffer = state->i2c_write_buffer;
4445 state->i2c.i2c_read_buffer = state->i2c_read_buffer;
4446 mutex_init(&state->i2c_buffer_lock);
4447 state->i2c.i2c_buffer_lock = &state->i2c_buffer_lock;
4448 state->gpio_val = cfg->gpio_val;
4449 state->gpio_dir = cfg->gpio_dir;
4451 /* Ensure the output mode remains at the previous default if it's
4452 * not specifically set by the caller.
4454 if ((state->cfg.output_mode != OUTMODE_MPEG2_SERIAL) && (state->cfg.output_mode != OUTMODE_MPEG2_PAR_GATED_CLK))
4455 state->cfg.output_mode = OUTMODE_MPEG2_FIFO;
4458 fe->demodulator_priv = state;
4459 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops));
4461 state->timf_default = cfg->pll->timf;
4463 if (dib8000_identify(&state->i2c) == 0)
4466 dibx000_init_i2c_master(&state->i2c_master, DIB8000, state->i2c.adap, state->i2c.addr);
4468 /* init 8096p tuner adapter */
4469 strncpy(state->dib8096p_tuner_adap.name, "DiB8096P tuner interface",
4470 sizeof(state->dib8096p_tuner_adap.name));
4471 state->dib8096p_tuner_adap.algo = &dib8096p_tuner_xfer_algo;
4472 state->dib8096p_tuner_adap.algo_data = NULL;
4473 state->dib8096p_tuner_adap.dev.parent = state->i2c.adap->dev.parent;
4474 i2c_set_adapdata(&state->dib8096p_tuner_adap, state);
4475 i2c_add_adapter(&state->dib8096p_tuner_adap);
4479 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len = 3 */
4480 state->current_demod_bw = 6000;
4489 void *dib8000_attach(struct dib8000_ops *ops)
4494 ops->pwm_agc_reset = dib8000_pwm_agc_reset;
4495 ops->get_dc_power = dib8090p_get_dc_power;
4496 ops->set_gpio = dib8000_set_gpio;
4497 ops->get_slave_frontend = dib8000_get_slave_frontend;
4498 ops->set_tune_state = dib8000_set_tune_state;
4499 ops->pid_filter_ctrl = dib8000_pid_filter_ctrl;
4500 ops->remove_slave_frontend = dib8000_remove_slave_frontend;
4501 ops->get_adc_power = dib8000_get_adc_power;
4502 ops->update_pll = dib8000_update_pll;
4503 ops->tuner_sleep = dib8096p_tuner_sleep;
4504 ops->get_tune_state = dib8000_get_tune_state;
4505 ops->get_i2c_tuner = dib8096p_get_i2c_tuner;
4506 ops->set_slave_frontend = dib8000_set_slave_frontend;
4507 ops->pid_filter = dib8000_pid_filter;
4508 ops->ctrl_timf = dib8000_ctrl_timf;
4509 ops->init = dib8000_init;
4510 ops->get_i2c_master = dib8000_get_i2c_master;
4511 ops->i2c_enumeration = dib8000_i2c_enumeration;
4512 ops->set_wbd_ref = dib8000_set_wbd_ref;
4516 EXPORT_SYMBOL(dib8000_attach);
4518 MODULE_AUTHOR("Olivier Grenie <Olivier.Grenie@dibcom.fr, " "Patrick Boettcher <pboettcher@dibcom.fr>");
4519 MODULE_DESCRIPTION("Driver for the DiBcom 8000 ISDB-T demodulator");
4520 MODULE_LICENSE("GPL");