2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.
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31 #ifndef __DRXDRIVER_H__
32 #define __DRXDRIVER_H__
34 #include <linux/kernel.h>
35 #include <linux/errno.h>
38 * This structure contains the I2C address, the device ID and a user_data pointer.
39 * The user_data pointer can be used for application specific purposes.
41 struct i2c_device_addr {
42 u16 i2c_addr; /* The I2C address of the device. */
43 u16 i2c_dev_id; /* The device identifier. */
44 void *user_data; /* User data pointer */
48 * \def IS_I2C_10BIT( addr )
49 * \brief Determine if I2C address 'addr' is a 10 bits address or not.
50 * \param addr The I2C address.
52 * \retval 0 if address is not a 10 bits I2C address.
53 * \retval 1 if address is a 10 bits I2C address.
55 #define IS_I2C_10BIT(addr) \
56 (((addr) & 0xF8) == 0xF0)
58 /*------------------------------------------------------------------------------
60 ------------------------------------------------------------------------------*/
63 * \fn drxbsp_i2c_init()
64 * \brief Initialize I2C communication module.
65 * \return int Return status.
66 * \retval 0 Initialization successful.
67 * \retval -EIO Initialization failed.
69 int drxbsp_i2c_init(void);
72 * \fn drxbsp_i2c_term()
73 * \brief Terminate I2C communication module.
74 * \return int Return status.
75 * \retval 0 Termination successful.
76 * \retval -EIO Termination failed.
78 int drxbsp_i2c_term(void);
81 * \fn int drxbsp_i2c_write_read( struct i2c_device_addr *w_dev_addr,
84 * struct i2c_device_addr *r_dev_addr,
87 * \brief Read and/or write count bytes from I2C bus, store them in data[].
88 * \param w_dev_addr The device i2c address and the device ID to write to
89 * \param w_count The number of bytes to write
90 * \param wData The array to write the data to
91 * \param r_dev_addr The device i2c address and the device ID to read from
92 * \param r_count The number of bytes to read
93 * \param r_data The array to read the data from
94 * \return int Return status.
96 * \retval -EIO Failure.
97 * \retval -EINVAL Parameter 'wcount' is not zero but parameter
98 * 'wdata' contains NULL.
99 * Idem for 'rcount' and 'rdata'.
100 * Both w_dev_addr and r_dev_addr are NULL.
102 * This function must implement an atomic write and/or read action on the I2C bus
103 * No other process may use the I2C bus when this function is executing.
104 * The critical section of this function runs from and including the I2C
105 * write, up to and including the I2C read action.
107 * The device ID can be useful if several devices share an I2C address.
108 * It can be used to control a "switch" on the I2C bus to the correct device.
110 int drxbsp_i2c_write_read(struct i2c_device_addr *w_dev_addr,
113 struct i2c_device_addr *r_dev_addr,
114 u16 r_count, u8 *r_data);
117 * \fn drxbsp_i2c_error_text()
118 * \brief Returns a human readable error.
119 * Counter part of numerical drx_i2c_error_g.
121 * \return char* Pointer to human readable error text.
123 char *drxbsp_i2c_error_text(void);
126 * \var drx_i2c_error_g;
127 * \brief I2C specific error codes, platform dependent.
129 extern int drx_i2c_error_g;
131 #define TUNER_MODE_SUB0 0x0001 /* for sub-mode (e.g. RF-AGC setting) */
132 #define TUNER_MODE_SUB1 0x0002 /* for sub-mode (e.g. RF-AGC setting) */
133 #define TUNER_MODE_SUB2 0x0004 /* for sub-mode (e.g. RF-AGC setting) */
134 #define TUNER_MODE_SUB3 0x0008 /* for sub-mode (e.g. RF-AGC setting) */
135 #define TUNER_MODE_SUB4 0x0010 /* for sub-mode (e.g. RF-AGC setting) */
136 #define TUNER_MODE_SUB5 0x0020 /* for sub-mode (e.g. RF-AGC setting) */
137 #define TUNER_MODE_SUB6 0x0040 /* for sub-mode (e.g. RF-AGC setting) */
138 #define TUNER_MODE_SUB7 0x0080 /* for sub-mode (e.g. RF-AGC setting) */
140 #define TUNER_MODE_DIGITAL 0x0100 /* for digital channel (e.g. DVB-T) */
141 #define TUNER_MODE_ANALOG 0x0200 /* for analog channel (e.g. PAL) */
142 #define TUNER_MODE_SWITCH 0x0400 /* during channel switch & scanning */
143 #define TUNER_MODE_LOCK 0x0800 /* after tuner has locked */
144 #define TUNER_MODE_6MHZ 0x1000 /* for 6MHz bandwidth channels */
145 #define TUNER_MODE_7MHZ 0x2000 /* for 7MHz bandwidth channels */
146 #define TUNER_MODE_8MHZ 0x4000 /* for 8MHz bandwidth channels */
148 #define TUNER_MODE_SUB_MAX 8
149 #define TUNER_MODE_SUBALL (TUNER_MODE_SUB0 | TUNER_MODE_SUB1 | \
150 TUNER_MODE_SUB2 | TUNER_MODE_SUB3 | \
151 TUNER_MODE_SUB4 | TUNER_MODE_SUB5 | \
152 TUNER_MODE_SUB6 | TUNER_MODE_SUB7)
155 enum tuner_lock_status {
160 struct tuner_common {
161 char *name; /* Tuner brand & type name */
162 s32 min_freq_rf; /* Lowest RF input frequency, in kHz */
163 s32 max_freq_rf; /* Highest RF input frequency, in kHz */
165 u8 sub_mode; /* Index to sub-mode in use */
166 char ***sub_mode_descriptions; /* Pointer to description of sub-modes */
167 u8 sub_modes; /* Number of available sub-modes */
169 /* The following fields will be either 0, NULL or false and do not need
171 void *self_check; /* gives proof of initialization */
172 bool programmed; /* only valid if self_check is OK */
173 s32 r_ffrequency; /* only valid if programmed */
174 s32 i_ffrequency; /* only valid if programmed */
176 void *my_user_data; /* pointer to associated demod instance */
177 u16 my_capabilities; /* value for storing application flags */
180 struct tuner_instance;
182 typedef int(*tuner_open_func_t) (struct tuner_instance *tuner);
183 typedef int(*tuner_close_func_t) (struct tuner_instance *tuner);
185 typedef int(*tuner_set_frequency_func_t) (struct tuner_instance *tuner,
190 typedef int(*tuner_get_frequency_func_t) (struct tuner_instance *tuner,
197 typedef int(*tuner_lock_status_func_t) (struct tuner_instance *tuner,
198 enum tuner_lock_status *
201 typedef int(*tune_ri2c_write_read_func_t) (struct tuner_instance *tuner,
202 struct i2c_device_addr *
203 w_dev_addr, u16 w_count,
205 struct i2c_device_addr *
206 r_dev_addr, u16 r_count,
210 tuner_open_func_t open_func;
211 tuner_close_func_t close_func;
212 tuner_set_frequency_func_t set_frequency_func;
213 tuner_get_frequency_func_t get_frequency_func;
214 tuner_lock_status_func_t lock_status_func;
215 tune_ri2c_write_read_func_t i2c_write_read_func;
219 struct tuner_instance {
220 struct i2c_device_addr my_i2c_dev_addr;
221 struct tuner_common *my_common_attr;
223 struct tuner_ops *my_funct;
226 int drxbsp_tuner_open(struct tuner_instance *tuner);
228 int drxbsp_tuner_close(struct tuner_instance *tuner);
230 int drxbsp_tuner_set_frequency(struct tuner_instance *tuner,
234 int drxbsp_tuner_get_frequency(struct tuner_instance *tuner,
239 int drxbsp_tuner_lock_status(struct tuner_instance *tuner,
240 enum tuner_lock_status *lock_stat);
242 int drxbsp_tuner_default_i2c_write_read(struct tuner_instance *tuner,
243 struct i2c_device_addr *w_dev_addr,
246 struct i2c_device_addr *r_dev_addr,
247 u16 r_count, u8 *r_data);
249 int drxbsp_hst_init(void);
251 int drxbsp_hst_term(void);
253 void *drxbsp_hst_memcpy(void *to, void *from, u32 n);
255 int drxbsp_hst_memcmp(void *s1, void *s2, u32 n);
257 u32 drxbsp_hst_clock(void);
259 int drxbsp_hst_sleep(u32 n);
265 * This section configures the DRX Data Access Protocols (DAPs).
270 * \def DRXDAP_SINGLE_MASTER
271 * \brief Enable I2C single or I2C multimaster mode on host.
273 * Set to 1 to enable single master mode
274 * Set to 0 to enable multi master mode
276 * The actual DAP implementation may be restricted to only one of the modes.
277 * A compiler warning or error will be generated if the DAP implementation
278 * overides or cannot handle the mode defined below.
281 #ifndef DRXDAP_SINGLE_MASTER
282 #define DRXDAP_SINGLE_MASTER 0
286 * \def DRXDAP_MAX_WCHUNKSIZE
287 * \brief Defines maximum chunksize of an i2c write action by host.
289 * This indicates the maximum size of data the I2C device driver is able to
290 * write at a time. This includes I2C device address and register addressing.
292 * This maximum size may be restricted by the actual DAP implementation.
293 * A compiler warning or error will be generated if the DAP implementation
294 * overides or cannot handle the chunksize defined below.
296 * Beware that the DAP uses DRXDAP_MAX_WCHUNKSIZE to create a temporary data
297 * buffer. Do not undefine or choose too large, unless your system is able to
298 * handle a stack buffer of that size.
301 #ifndef DRXDAP_MAX_WCHUNKSIZE
302 #define DRXDAP_MAX_WCHUNKSIZE 60
306 * \def DRXDAP_MAX_RCHUNKSIZE
307 * \brief Defines maximum chunksize of an i2c read action by host.
309 * This indicates the maximum size of data the I2C device driver is able to read
310 * at a time. Minimum value is 2. Also, the read chunk size must be even.
312 * This maximum size may be restricted by the actual DAP implementation.
313 * A compiler warning or error will be generated if the DAP implementation
314 * overides or cannot handle the chunksize defined below.
317 #ifndef DRXDAP_MAX_RCHUNKSIZE
318 #define DRXDAP_MAX_RCHUNKSIZE 60
323 * This section describes drxdriver defines.
329 * \brief Generic UNKNOWN value for DRX enumerated types.
331 * Used to indicate that the parameter value is unknown or not yet initalized.
334 #define DRX_UNKNOWN (254)
339 * \brief Generic AUTO value for DRX enumerated types.
341 * Used to instruct the driver to automatically determine the value of the
345 #define DRX_AUTO (255)
350 * This section describes flag definitions for the device capbilities.
355 * \brief LNA capability flag
357 * Device has a Low Noise Amplifier
360 #define DRX_CAPABILITY_HAS_LNA (1UL << 0)
362 * \brief OOB-RX capability flag
367 #define DRX_CAPABILITY_HAS_OOBRX (1UL << 1)
369 * \brief ATV capability flag
374 #define DRX_CAPABILITY_HAS_ATV (1UL << 2)
376 * \brief DVB-T capability flag
381 #define DRX_CAPABILITY_HAS_DVBT (1UL << 3)
383 * \brief ITU-B capability flag
388 #define DRX_CAPABILITY_HAS_ITUB (1UL << 4)
390 * \brief Audio capability flag
395 #define DRX_CAPABILITY_HAS_AUD (1UL << 5)
397 * \brief SAW switch capability flag
399 * Device has SAW switch
402 #define DRX_CAPABILITY_HAS_SAWSW (1UL << 6)
404 * \brief GPIO1 capability flag
409 #define DRX_CAPABILITY_HAS_GPIO1 (1UL << 7)
411 * \brief GPIO2 capability flag
416 #define DRX_CAPABILITY_HAS_GPIO2 (1UL << 8)
418 * \brief IRQN capability flag
423 #define DRX_CAPABILITY_HAS_IRQN (1UL << 9)
425 * \brief 8VSB capability flag
430 #define DRX_CAPABILITY_HAS_8VSB (1UL << 10)
432 * \brief SMA-TX capability flag
437 #define DRX_CAPABILITY_HAS_SMATX (1UL << 11)
439 * \brief SMA-RX capability flag
444 #define DRX_CAPABILITY_HAS_SMARX (1UL << 12)
446 * \brief ITU-A/C capability flag
451 #define DRX_CAPABILITY_HAS_ITUAC (1UL << 13)
453 /*-------------------------------------------------------------------------
455 -------------------------------------------------------------------------*/
456 /* Macros to stringify the version number */
457 #define DRX_VERSIONSTRING(MAJOR, MINOR, PATCH) \
458 DRX_VERSIONSTRING_HELP(MAJOR)"." \
459 DRX_VERSIONSTRING_HELP(MINOR)"." \
460 DRX_VERSIONSTRING_HELP(PATCH)
461 #define DRX_VERSIONSTRING_HELP(NUM) #NUM
464 * \brief Macro to create byte array elements from 16 bit integers.
465 * This macro is used to create byte arrays for block writes.
466 * Block writes speed up I2C traffic between host and demod.
467 * The macro takes care of the required byte order in a 16 bits word.
468 * x->lowbyte(x), highbyte(x)
470 #define DRX_16TO8(x) ((u8) (((u16)x) & 0xFF)), \
471 ((u8)((((u16)x)>>8)&0xFF))
474 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value
476 #define DRX_S9TOS16(x) ((((u16)x)&0x100) ? ((s16)((u16)(x)|0xFF00)) : (x))
479 * \brief Macro to sign extend signed 9 bit value to signed 16 bit value
481 #define DRX_S24TODRXFREQ(x) ((((u32) x) & 0x00800000UL) ? \
483 (((u32) x) | 0xFF000000)) : \
487 * \brief Macro to convert 16 bit register value to a s32
489 #define DRX_U16TODRXFREQ(x) ((x & 0x8000) ? \
491 (((u32) x) | 0xFFFF0000)) : \
494 /*-------------------------------------------------------------------------
496 -------------------------------------------------------------------------*/
499 * \enum enum drx_standard
500 * \brief Modulation standards.
503 DRX_STANDARD_DVBT = 0, /**< Terrestrial DVB-T. */
504 DRX_STANDARD_8VSB, /**< Terrestrial 8VSB. */
505 DRX_STANDARD_NTSC, /**< Terrestrial\Cable analog NTSC. */
506 DRX_STANDARD_PAL_SECAM_BG,
507 /**< Terrestrial analog PAL/SECAM B/G */
508 DRX_STANDARD_PAL_SECAM_DK,
509 /**< Terrestrial analog PAL/SECAM D/K */
510 DRX_STANDARD_PAL_SECAM_I,
511 /**< Terrestrial analog PAL/SECAM I */
512 DRX_STANDARD_PAL_SECAM_L,
513 /**< Terrestrial analog PAL/SECAM L
514 with negative modulation */
515 DRX_STANDARD_PAL_SECAM_LP,
516 /**< Terrestrial analog PAL/SECAM L
517 with positive modulation */
518 DRX_STANDARD_ITU_A, /**< Cable ITU ANNEX A. */
519 DRX_STANDARD_ITU_B, /**< Cable ITU ANNEX B. */
520 DRX_STANDARD_ITU_C, /**< Cable ITU ANNEX C. */
521 DRX_STANDARD_ITU_D, /**< Cable ITU ANNEX D. */
522 DRX_STANDARD_FM, /**< Terrestrial\Cable FM radio */
523 DRX_STANDARD_DTMB, /**< Terrestrial DTMB standard (China)*/
524 DRX_STANDARD_UNKNOWN = DRX_UNKNOWN,
525 /**< Standard unknown. */
526 DRX_STANDARD_AUTO = DRX_AUTO
527 /**< Autodetect standard. */
531 * \enum enum drx_standard
532 * \brief Modulation sub-standards.
534 enum drx_substandard {
535 DRX_SUBSTANDARD_MAIN = 0, /**< Main subvariant of standard */
536 DRX_SUBSTANDARD_ATV_BG_SCANDINAVIA,
537 DRX_SUBSTANDARD_ATV_DK_POLAND,
538 DRX_SUBSTANDARD_ATV_DK_CHINA,
539 DRX_SUBSTANDARD_UNKNOWN = DRX_UNKNOWN,
540 /**< Sub-standard unknown. */
541 DRX_SUBSTANDARD_AUTO = DRX_AUTO
542 /**< Auto (default) sub-standard */
546 * \enum enum drx_bandwidth
547 * \brief Channel bandwidth or channel spacing.
550 DRX_BANDWIDTH_8MHZ = 0, /**< Bandwidth 8 MHz. */
551 DRX_BANDWIDTH_7MHZ, /**< Bandwidth 7 MHz. */
552 DRX_BANDWIDTH_6MHZ, /**< Bandwidth 6 MHz. */
553 DRX_BANDWIDTH_UNKNOWN = DRX_UNKNOWN,
554 /**< Bandwidth unknown. */
555 DRX_BANDWIDTH_AUTO = DRX_AUTO
556 /**< Auto Set Bandwidth */
560 * \enum enum drx_mirror
561 * \brief Indicate if channel spectrum is mirrored or not.
564 DRX_MIRROR_NO = 0, /**< Spectrum is not mirrored. */
565 DRX_MIRROR_YES, /**< Spectrum is mirrored. */
566 DRX_MIRROR_UNKNOWN = DRX_UNKNOWN,
567 /**< Unknown if spectrum is mirrored. */
568 DRX_MIRROR_AUTO = DRX_AUTO
569 /**< Autodetect if spectrum is mirrored. */
573 * \enum enum drx_modulation
574 * \brief Constellation type of the channel.
576 enum drx_modulation {
577 DRX_CONSTELLATION_BPSK = 0, /**< Modulation is BPSK. */
578 DRX_CONSTELLATION_QPSK, /**< Constellation is QPSK. */
579 DRX_CONSTELLATION_PSK8, /**< Constellation is PSK8. */
580 DRX_CONSTELLATION_QAM16, /**< Constellation is QAM16. */
581 DRX_CONSTELLATION_QAM32, /**< Constellation is QAM32. */
582 DRX_CONSTELLATION_QAM64, /**< Constellation is QAM64. */
583 DRX_CONSTELLATION_QAM128, /**< Constellation is QAM128. */
584 DRX_CONSTELLATION_QAM256, /**< Constellation is QAM256. */
585 DRX_CONSTELLATION_QAM512, /**< Constellation is QAM512. */
586 DRX_CONSTELLATION_QAM1024, /**< Constellation is QAM1024. */
587 DRX_CONSTELLATION_QPSK_NR, /**< Constellation is QPSK_NR */
588 DRX_CONSTELLATION_UNKNOWN = DRX_UNKNOWN,
589 /**< Constellation unknown. */
590 DRX_CONSTELLATION_AUTO = DRX_AUTO
591 /**< Autodetect constellation. */
595 * \enum enum drx_hierarchy
596 * \brief Hierarchy of the channel.
599 DRX_HIERARCHY_NONE = 0, /**< None hierarchical channel. */
600 DRX_HIERARCHY_ALPHA1, /**< Hierarchical channel, alpha=1. */
601 DRX_HIERARCHY_ALPHA2, /**< Hierarchical channel, alpha=2. */
602 DRX_HIERARCHY_ALPHA4, /**< Hierarchical channel, alpha=4. */
603 DRX_HIERARCHY_UNKNOWN = DRX_UNKNOWN,
604 /**< Hierarchy unknown. */
605 DRX_HIERARCHY_AUTO = DRX_AUTO
606 /**< Autodetect hierarchy. */
610 * \enum enum drx_priority
611 * \brief Channel priority in case of hierarchical transmission.
614 DRX_PRIORITY_LOW = 0, /**< Low priority channel. */
615 DRX_PRIORITY_HIGH, /**< High priority channel. */
616 DRX_PRIORITY_UNKNOWN = DRX_UNKNOWN
617 /**< Priority unknown. */
621 * \enum enum drx_coderate
622 * \brief Channel priority in case of hierarchical transmission.
625 DRX_CODERATE_1DIV2 = 0, /**< Code rate 1/2nd. */
626 DRX_CODERATE_2DIV3, /**< Code rate 2/3nd. */
627 DRX_CODERATE_3DIV4, /**< Code rate 3/4nd. */
628 DRX_CODERATE_5DIV6, /**< Code rate 5/6nd. */
629 DRX_CODERATE_7DIV8, /**< Code rate 7/8nd. */
630 DRX_CODERATE_UNKNOWN = DRX_UNKNOWN,
631 /**< Code rate unknown. */
632 DRX_CODERATE_AUTO = DRX_AUTO
633 /**< Autodetect code rate. */
637 * \enum enum drx_guard
638 * \brief Guard interval of a channel.
641 DRX_GUARD_1DIV32 = 0, /**< Guard interval 1/32nd. */
642 DRX_GUARD_1DIV16, /**< Guard interval 1/16th. */
643 DRX_GUARD_1DIV8, /**< Guard interval 1/8th. */
644 DRX_GUARD_1DIV4, /**< Guard interval 1/4th. */
645 DRX_GUARD_UNKNOWN = DRX_UNKNOWN,
646 /**< Guard interval unknown. */
647 DRX_GUARD_AUTO = DRX_AUTO
648 /**< Autodetect guard interval. */
652 * \enum enum drx_fft_mode
656 DRX_FFTMODE_2K = 0, /**< 2K FFT mode. */
657 DRX_FFTMODE_4K, /**< 4K FFT mode. */
658 DRX_FFTMODE_8K, /**< 8K FFT mode. */
659 DRX_FFTMODE_UNKNOWN = DRX_UNKNOWN,
660 /**< FFT mode unknown. */
661 DRX_FFTMODE_AUTO = DRX_AUTO
662 /**< Autodetect FFT mode. */
666 * \enum enum drx_classification
667 * \brief Channel classification.
669 enum drx_classification {
670 DRX_CLASSIFICATION_GAUSS = 0, /**< Gaussion noise. */
671 DRX_CLASSIFICATION_HVY_GAUSS, /**< Heavy Gaussion noise. */
672 DRX_CLASSIFICATION_COCHANNEL, /**< Co-channel. */
673 DRX_CLASSIFICATION_STATIC, /**< Static echo. */
674 DRX_CLASSIFICATION_MOVING, /**< Moving echo. */
675 DRX_CLASSIFICATION_ZERODB, /**< Zero dB echo. */
676 DRX_CLASSIFICATION_UNKNOWN = DRX_UNKNOWN,
677 /**< Unknown classification */
678 DRX_CLASSIFICATION_AUTO = DRX_AUTO
679 /**< Autodetect classification. */
683 * /enum enum drx_interleave_mode
684 * /brief Interleave modes
686 enum drx_interleave_mode {
687 DRX_INTERLEAVEMODE_I128_J1 = 0,
688 DRX_INTERLEAVEMODE_I128_J1_V2,
689 DRX_INTERLEAVEMODE_I128_J2,
690 DRX_INTERLEAVEMODE_I64_J2,
691 DRX_INTERLEAVEMODE_I128_J3,
692 DRX_INTERLEAVEMODE_I32_J4,
693 DRX_INTERLEAVEMODE_I128_J4,
694 DRX_INTERLEAVEMODE_I16_J8,
695 DRX_INTERLEAVEMODE_I128_J5,
696 DRX_INTERLEAVEMODE_I8_J16,
697 DRX_INTERLEAVEMODE_I128_J6,
698 DRX_INTERLEAVEMODE_RESERVED_11,
699 DRX_INTERLEAVEMODE_I128_J7,
700 DRX_INTERLEAVEMODE_RESERVED_13,
701 DRX_INTERLEAVEMODE_I128_J8,
702 DRX_INTERLEAVEMODE_RESERVED_15,
703 DRX_INTERLEAVEMODE_I12_J17,
704 DRX_INTERLEAVEMODE_I5_J4,
705 DRX_INTERLEAVEMODE_B52_M240,
706 DRX_INTERLEAVEMODE_B52_M720,
707 DRX_INTERLEAVEMODE_B52_M48,
708 DRX_INTERLEAVEMODE_B52_M0,
709 DRX_INTERLEAVEMODE_UNKNOWN = DRX_UNKNOWN,
710 /**< Unknown interleave mode */
711 DRX_INTERLEAVEMODE_AUTO = DRX_AUTO
712 /**< Autodetect interleave mode */
716 * \enum enum drx_carrier_mode
717 * \brief Channel Carrier Mode.
719 enum drx_carrier_mode {
720 DRX_CARRIER_MULTI = 0, /**< Multi carrier mode */
721 DRX_CARRIER_SINGLE, /**< Single carrier mode */
722 DRX_CARRIER_UNKNOWN = DRX_UNKNOWN,
723 /**< Carrier mode unknown. */
724 DRX_CARRIER_AUTO = DRX_AUTO /**< Autodetect carrier mode */
728 * \enum enum drx_frame_mode
729 * \brief Channel Frame Mode.
731 enum drx_frame_mode {
732 DRX_FRAMEMODE_420 = 0, /**< 420 with variable PN */
733 DRX_FRAMEMODE_595, /**< 595 */
734 DRX_FRAMEMODE_945, /**< 945 with variable PN */
735 DRX_FRAMEMODE_420_FIXED_PN,
736 /**< 420 with fixed PN */
737 DRX_FRAMEMODE_945_FIXED_PN,
738 /**< 945 with fixed PN */
739 DRX_FRAMEMODE_UNKNOWN = DRX_UNKNOWN,
740 /**< Frame mode unknown. */
741 DRX_FRAMEMODE_AUTO = DRX_AUTO
742 /**< Autodetect frame mode */
746 * \enum enum drx_tps_frame
747 * \brief Frame number in current super-frame.
750 DRX_TPS_FRAME1 = 0, /**< TPS frame 1. */
751 DRX_TPS_FRAME2, /**< TPS frame 2. */
752 DRX_TPS_FRAME3, /**< TPS frame 3. */
753 DRX_TPS_FRAME4, /**< TPS frame 4. */
754 DRX_TPS_FRAME_UNKNOWN = DRX_UNKNOWN
755 /**< TPS frame unknown. */
759 * \enum enum drx_ldpc
763 DRX_LDPC_0_4 = 0, /**< LDPC 0.4 */
764 DRX_LDPC_0_6, /**< LDPC 0.6 */
765 DRX_LDPC_0_8, /**< LDPC 0.8 */
766 DRX_LDPC_UNKNOWN = DRX_UNKNOWN,
767 /**< LDPC unknown. */
768 DRX_LDPC_AUTO = DRX_AUTO /**< Autodetect LDPC */
772 * \enum enum drx_pilot_mode
773 * \brief Pilot modes in DTMB.
775 enum drx_pilot_mode {
776 DRX_PILOT_ON = 0, /**< Pilot On */
777 DRX_PILOT_OFF, /**< Pilot Off */
778 DRX_PILOT_UNKNOWN = DRX_UNKNOWN,
779 /**< Pilot unknown. */
780 DRX_PILOT_AUTO = DRX_AUTO /**< Autodetect Pilot */
783 #define DRX_CTRL_BASE ((u32)0)
785 #define DRX_CTRL_NOP (DRX_CTRL_BASE + 0)/**< No Operation */
786 #define DRX_CTRL_PROBE_DEVICE (DRX_CTRL_BASE + 1)/**< Probe device */
788 #define DRX_CTRL_LOAD_UCODE (DRX_CTRL_BASE + 2)/**< Load microcode */
789 #define DRX_CTRL_VERIFY_UCODE (DRX_CTRL_BASE + 3)/**< Verify microcode */
790 #define DRX_CTRL_SET_CHANNEL (DRX_CTRL_BASE + 4)/**< Set channel */
791 #define DRX_CTRL_GET_CHANNEL (DRX_CTRL_BASE + 5)/**< Get channel */
792 #define DRX_CTRL_LOCK_STATUS (DRX_CTRL_BASE + 6)/**< Get lock status */
793 #define DRX_CTRL_SIG_QUALITY (DRX_CTRL_BASE + 7)/**< Get signal quality */
794 #define DRX_CTRL_SIG_STRENGTH (DRX_CTRL_BASE + 8)/**< Get signal strength*/
795 #define DRX_CTRL_RF_POWER (DRX_CTRL_BASE + 9)/**< Get RF power */
796 #define DRX_CTRL_CONSTEL (DRX_CTRL_BASE + 10)/**< Get constel point */
797 #define DRX_CTRL_SCAN_INIT (DRX_CTRL_BASE + 11)/**< Initialize scan */
798 #define DRX_CTRL_SCAN_NEXT (DRX_CTRL_BASE + 12)/**< Scan for next */
799 #define DRX_CTRL_SCAN_STOP (DRX_CTRL_BASE + 13)/**< Stop scan */
800 #define DRX_CTRL_TPS_INFO (DRX_CTRL_BASE + 14)/**< Get TPS info */
801 #define DRX_CTRL_SET_CFG (DRX_CTRL_BASE + 15)/**< Set configuration */
802 #define DRX_CTRL_GET_CFG (DRX_CTRL_BASE + 16)/**< Get configuration */
803 #define DRX_CTRL_VERSION (DRX_CTRL_BASE + 17)/**< Get version info */
804 #define DRX_CTRL_I2C_BRIDGE (DRX_CTRL_BASE + 18)/**< Open/close bridge */
805 #define DRX_CTRL_SET_STANDARD (DRX_CTRL_BASE + 19)/**< Set demod std */
806 #define DRX_CTRL_GET_STANDARD (DRX_CTRL_BASE + 20)/**< Get demod std */
807 #define DRX_CTRL_SET_OOB (DRX_CTRL_BASE + 21)/**< Set OOB param */
808 #define DRX_CTRL_GET_OOB (DRX_CTRL_BASE + 22)/**< Get OOB param */
809 #define DRX_CTRL_AUD_SET_STANDARD (DRX_CTRL_BASE + 23)/**< Set audio param */
810 #define DRX_CTRL_AUD_GET_STANDARD (DRX_CTRL_BASE + 24)/**< Get audio param */
811 #define DRX_CTRL_AUD_GET_STATUS (DRX_CTRL_BASE + 25)/**< Read RDS */
812 #define DRX_CTRL_AUD_BEEP (DRX_CTRL_BASE + 26)/**< Read RDS */
813 #define DRX_CTRL_I2C_READWRITE (DRX_CTRL_BASE + 27)/**< Read/write I2C */
814 #define DRX_CTRL_PROGRAM_TUNER (DRX_CTRL_BASE + 28)/**< Program tuner */
817 #define DRX_CTRL_MB_CFG (DRX_CTRL_BASE + 29) /**< */
818 #define DRX_CTRL_MB_READ (DRX_CTRL_BASE + 30) /**< */
819 #define DRX_CTRL_MB_WRITE (DRX_CTRL_BASE + 31) /**< */
820 #define DRX_CTRL_MB_CONSTEL (DRX_CTRL_BASE + 32) /**< */
821 #define DRX_CTRL_MB_MER (DRX_CTRL_BASE + 33) /**< */
824 #define DRX_CTRL_UIO_CFG DRX_CTRL_SET_UIO_CFG /**< Configure UIO */
825 #define DRX_CTRL_SET_UIO_CFG (DRX_CTRL_BASE + 34) /**< Configure UIO */
826 #define DRX_CTRL_GET_UIO_CFG (DRX_CTRL_BASE + 35) /**< Configure UIO */
827 #define DRX_CTRL_UIO_READ (DRX_CTRL_BASE + 36) /**< Read from UIO */
828 #define DRX_CTRL_UIO_WRITE (DRX_CTRL_BASE + 37) /**< Write to UIO */
829 #define DRX_CTRL_READ_EVENTS (DRX_CTRL_BASE + 38) /**< Read events */
830 #define DRX_CTRL_HDL_EVENTS (DRX_CTRL_BASE + 39) /**< Handle events */
831 #define DRX_CTRL_POWER_MODE (DRX_CTRL_BASE + 40) /**< Set power mode */
832 #define DRX_CTRL_LOAD_FILTER (DRX_CTRL_BASE + 41) /**< Load chan. filter */
833 #define DRX_CTRL_VALIDATE_UCODE (DRX_CTRL_BASE + 42) /**< Validate ucode */
834 #define DRX_CTRL_DUMP_REGISTERS (DRX_CTRL_BASE + 43) /**< Dump registers */
836 #define DRX_CTRL_MAX (DRX_CTRL_BASE + 44) /* never to be used */
839 * enum drxu_code_action - indicate if firmware has to be uploaded or verified.
840 * @UCODE_UPLOAD: Upload the microcode image to device
841 * @UCODE_VERIFY: Compare microcode image with code on device
843 enum drxu_code_action {
849 * \enum enum drx_lock_status * \brief Used to reflect current lock status of demodulator.
851 * The generic lock states have device dependent semantics.
854 **< Device will never lock on this signal *
856 **< Device has no lock at all *
858 **< Generic lock state *
860 **< Generic lock state *
862 **< Generic lock state *
864 **< Generic lock state *
866 **< Generic lock state *
868 **< Generic lock state *
870 **< Generic lock state *
872 **< Generic lock state *
874 **< Generic lock state *
875 DRX_LOCKED **< Device is in lock *
878 enum drx_lock_status {
894 * \enum enum drx_uio* \brief Used to address a User IO (UIO).
929 DRX_UIO_MAX = DRX_UIO32
933 * \enum enum drxuio_mode * \brief Used to configure the modus oprandi of a UIO.
935 * DRX_UIO_MODE_FIRMWARE is an old uio mode.
936 * It is replaced by the modes DRX_UIO_MODE_FIRMWARE0 .. DRX_UIO_MODE_FIRMWARE9.
937 * To be backward compatible DRX_UIO_MODE_FIRMWARE is equivalent to
938 * DRX_UIO_MODE_FIRMWARE0.
941 DRX_UIO_MODE_DISABLE = 0x01,
942 /**< not used, pin is configured as input */
943 DRX_UIO_MODE_READWRITE = 0x02,
944 /**< used for read/write by application */
945 DRX_UIO_MODE_FIRMWARE = 0x04,
946 /**< controlled by firmware, function 0 */
947 DRX_UIO_MODE_FIRMWARE0 = DRX_UIO_MODE_FIRMWARE,
948 /**< same as above */
949 DRX_UIO_MODE_FIRMWARE1 = 0x08,
950 /**< controlled by firmware, function 1 */
951 DRX_UIO_MODE_FIRMWARE2 = 0x10,
952 /**< controlled by firmware, function 2 */
953 DRX_UIO_MODE_FIRMWARE3 = 0x20,
954 /**< controlled by firmware, function 3 */
955 DRX_UIO_MODE_FIRMWARE4 = 0x40,
956 /**< controlled by firmware, function 4 */
957 DRX_UIO_MODE_FIRMWARE5 = 0x80
958 /**< controlled by firmware, function 5 */
962 * \enum enum drxoob_downstream_standard * \brief Used to select OOB standard.
964 * Based on ANSI 55-1 and 55-2
966 enum drxoob_downstream_standard {
969 DRX_OOB_MODE_B_GRADE_A,
971 DRX_OOB_MODE_B_GRADE_B
975 /*-------------------------------------------------------------------------
977 -------------------------------------------------------------------------*/
979 /*============================================================================*/
980 /*============================================================================*/
981 /*== CTRL CFG related data structures ========================================*/
982 /*============================================================================*/
983 /*============================================================================*/
986 #define DRX_CFG_BASE 0
989 #define DRX_CFG_MPEG_OUTPUT (DRX_CFG_BASE + 0) /* MPEG TS output */
990 #define DRX_CFG_PKTERR (DRX_CFG_BASE + 1) /* Packet Error */
991 #define DRX_CFG_SYMCLK_OFFS (DRX_CFG_BASE + 2) /* Symbol Clk Offset */
992 #define DRX_CFG_SMA (DRX_CFG_BASE + 3) /* Smart Antenna */
993 #define DRX_CFG_PINSAFE (DRX_CFG_BASE + 4) /* Pin safe mode */
994 #define DRX_CFG_SUBSTANDARD (DRX_CFG_BASE + 5) /* substandard */
995 #define DRX_CFG_AUD_VOLUME (DRX_CFG_BASE + 6) /* volume */
996 #define DRX_CFG_AUD_RDS (DRX_CFG_BASE + 7) /* rds */
997 #define DRX_CFG_AUD_AUTOSOUND (DRX_CFG_BASE + 8) /* ASS & ASC */
998 #define DRX_CFG_AUD_ASS_THRES (DRX_CFG_BASE + 9) /* ASS Thresholds */
999 #define DRX_CFG_AUD_DEVIATION (DRX_CFG_BASE + 10) /* Deviation */
1000 #define DRX_CFG_AUD_PRESCALE (DRX_CFG_BASE + 11) /* Prescale */
1001 #define DRX_CFG_AUD_MIXER (DRX_CFG_BASE + 12) /* Mixer */
1002 #define DRX_CFG_AUD_AVSYNC (DRX_CFG_BASE + 13) /* AVSync */
1003 #define DRX_CFG_AUD_CARRIER (DRX_CFG_BASE + 14) /* Audio carriers */
1004 #define DRX_CFG_I2S_OUTPUT (DRX_CFG_BASE + 15) /* I2S output */
1005 #define DRX_CFG_ATV_STANDARD (DRX_CFG_BASE + 16) /* ATV standard */
1006 #define DRX_CFG_SQI_SPEED (DRX_CFG_BASE + 17) /* SQI speed */
1007 #define DRX_CTRL_CFG_MAX (DRX_CFG_BASE + 18) /* never to be used */
1009 #define DRX_CFG_PINS_SAFE_MODE DRX_CFG_PINSAFE
1010 /*============================================================================*/
1011 /*============================================================================*/
1012 /*== CTRL related data structures ============================================*/
1013 /*============================================================================*/
1014 /*============================================================================*/
1017 * \struct struct drxu_code_info * \brief Parameters for microcode upload and verfiy.
1019 * Used by DRX_CTRL_LOAD_UCODE and DRX_CTRL_VERIFY_UCODE
1021 struct drxu_code_info {
1023 /**< Pointer to microcode image. */
1025 /**< Microcode image size. */
1029 * \struct drx_mc_version_rec_t
1030 * \brief Microcode version record
1031 * Version numbers are stored in BCD format, as usual:
1032 * o major number = bits 31-20 (first three nibbles of MSW)
1033 * o minor number = bits 19-16 (fourth nibble of MSW)
1034 * o patch number = bits 15-0 (remaining nibbles in LSW)
1036 * The device type indicates for which the device is meant. It is based on the
1037 * JTAG ID, using everything except the bond ID and the metal fix.
1040 * - mc_dev_type == 0 => any device allowed
1041 * - mc_base_version == 0.0.0 => full microcode (mc_version is the version)
1042 * - mc_base_version != 0.0.0 => patch microcode, the base microcode version
1043 * (mc_version is the version)
1045 #define AUX_VER_RECORD 0x8000
1047 struct drx_mc_version_rec {
1048 u16 aux_type; /* type of aux data - 0x8000 for version record */
1049 u32 mc_dev_type; /* device type, based on JTAG ID */
1050 u32 mc_version; /* version of microcode */
1051 u32 mc_base_version; /* in case of patch: the original microcode version */
1054 /*========================================*/
1057 * \struct drx_filter_info_t
1058 * \brief Parameters for loading filter coefficients
1060 * Used by DRX_CTRL_LOAD_FILTER
1062 struct drx_filter_info {
1064 /**< pointer to coefficients for RE */
1066 /**< pointer to coefficients for IM */
1068 /**< size of coefficients for RE */
1070 /**< size of coefficients for IM */
1073 /*========================================*/
1076 * \struct struct drx_channel * \brief The set of parameters describing a single channel.
1078 * Used by DRX_CTRL_SET_CHANNEL and DRX_CTRL_GET_CHANNEL.
1079 * Only certain fields need to be used for a specfic standard.
1082 struct drx_channel {
1084 /**< frequency in kHz */
1085 enum drx_bandwidth bandwidth;
1087 enum drx_mirror mirror; /**< mirrored or not on RF */
1088 enum drx_modulation constellation;
1089 /**< constellation */
1090 enum drx_hierarchy hierarchy;
1092 enum drx_priority priority; /**< priority */
1093 enum drx_coderate coderate; /**< coderate */
1094 enum drx_guard guard; /**< guard interval */
1095 enum drx_fft_mode fftmode; /**< fftmode */
1096 enum drx_classification classification;
1097 /**< classification */
1099 /**< symbolrate in symbols/sec */
1100 enum drx_interleave_mode interleavemode;
1101 /**< interleaveMode QAM */
1102 enum drx_ldpc ldpc; /**< ldpc */
1103 enum drx_carrier_mode carrier; /**< carrier */
1104 enum drx_frame_mode framemode;
1106 enum drx_pilot_mode pilot; /**< pilot mode */
1109 /*========================================*/
1112 * \struct struct drx_sig_quality * Signal quality metrics.
1114 * Used by DRX_CTRL_SIG_QUALITY.
1116 struct drx_sig_quality {
1117 u16 MER; /**< in steps of 0.1 dB */
1118 u32 pre_viterbi_ber;
1119 /**< in steps of 1/scale_factor_ber */
1120 u32 post_viterbi_ber;
1121 /**< in steps of 1/scale_factor_ber */
1122 u32 scale_factor_ber;
1123 /**< scale factor for BER */
1125 /**< number of packet errors */
1126 u32 post_reed_solomon_ber;
1127 /**< in steps of 1/scale_factor_ber */
1129 /**< in steps of 1/scale_factor_ber */
1130 u32 aver_iter;/**< in steps of 0.01 */
1132 /**< indicative signal quality low=0..100=high */
1135 enum drx_cfg_sqi_speed {
1136 DRX_SQI_SPEED_FAST = 0,
1137 DRX_SQI_SPEED_MEDIUM,
1139 DRX_SQI_SPEED_UNKNOWN = DRX_UNKNOWN
1142 /*========================================*/
1145 * \struct struct drx_complex * A complex number.
1147 * Used by DRX_CTRL_CONSTEL.
1149 struct drx_complex {
1151 /**< Imaginary part. */
1156 /*========================================*/
1159 * \struct struct drx_frequency_plan * Array element of a frequency plan.
1161 * Used by DRX_CTRL_SCAN_INIT.
1163 struct drx_frequency_plan {
1165 /**< First centre frequency in this band */
1167 /**< Last centre frequency in this band */
1169 /**< Stepping frequency in this band */
1170 enum drx_bandwidth bandwidth;
1171 /**< Bandwidth within this frequency band */
1173 /**< First channel number in this band, or first
1174 index in ch_names */
1176 /**< Optional list of channel names in this
1180 /*========================================*/
1183 * \struct struct drx_scan_param * Parameters for channel scan.
1185 * Used by DRX_CTRL_SCAN_INIT.
1187 struct drx_scan_param {
1188 struct drx_frequency_plan *frequency_plan;
1189 /**< Frequency plan (array)*/
1190 u16 frequency_plan_size; /**< Number of bands */
1191 u32 num_tries; /**< Max channels tried */
1192 s32 skip; /**< Minimum frequency step to take
1193 after a channel is found */
1194 void *ext_params; /**< Standard specific params */
1197 /*========================================*/
1200 * \brief Scan commands.
1201 * Used by scanning algorithms.
1203 enum drx_scan_command {
1204 DRX_SCAN_COMMAND_INIT = 0,/**< Initialize scanning */
1205 DRX_SCAN_COMMAND_NEXT, /**< Next scan */
1206 DRX_SCAN_COMMAND_STOP /**< Stop scanning */
1209 /*========================================*/
1212 * \brief Inner scan function prototype.
1214 typedef int(*drx_scan_func_t) (void *scan_context,
1215 enum drx_scan_command scan_command,
1216 struct drx_channel *scan_channel,
1217 bool *get_next_channel);
1219 /*========================================*/
1222 * \struct struct drxtps_info * TPS information, DVB-T specific.
1224 * Used by DRX_CTRL_TPS_INFO.
1226 struct drxtps_info {
1227 enum drx_fft_mode fftmode; /**< Fft mode */
1228 enum drx_guard guard; /**< Guard interval */
1229 enum drx_modulation constellation;
1230 /**< Constellation */
1231 enum drx_hierarchy hierarchy;
1233 enum drx_coderate high_coderate;
1234 /**< High code rate */
1235 enum drx_coderate low_coderate;
1236 /**< Low cod rate */
1237 enum drx_tps_frame frame; /**< Tps frame */
1238 u8 length; /**< Length */
1239 u16 cell_id; /**< Cell id */
1242 /*========================================*/
1245 * \brief Power mode of device.
1247 * Used by DRX_CTRL_SET_POWER_MODE.
1249 enum drx_power_mode {
1251 /**< Generic , Power Up Mode */
1253 /**< Device specific , Power Up Mode */
1255 /**< Device specific , Power Up Mode */
1257 /**< Device specific , Power Up Mode */
1259 /**< Device specific , Power Up Mode */
1261 /**< Device specific , Power Up Mode */
1263 /**< Device specific , Power Up Mode */
1265 /**< Device specific , Power Up Mode */
1267 /**< Device specific , Power Up Mode */
1270 /**< Device specific , Power Down Mode */
1272 /**< Device specific , Power Down Mode */
1274 /**< Device specific , Power Down Mode */
1276 /**< Device specific , Power Down Mode */
1278 /**< Device specific , Power Down Mode */
1280 /**< Device specific , Power Down Mode */
1282 /**< Device specific , Power Down Mode */
1284 /**< Device specific , Power Down Mode */
1285 DRX_POWER_DOWN = 255
1286 /**< Generic , Power Down Mode */
1289 /*========================================*/
1292 * \enum enum drx_module * \brief Software module identification.
1294 * Used by DRX_CTRL_VERSION.
1298 DRX_MODULE_MICROCODE,
1299 DRX_MODULE_DRIVERCORE,
1300 DRX_MODULE_DEVICEDRIVER,
1303 DRX_MODULE_BSP_TUNER,
1304 DRX_MODULE_BSP_HOST,
1309 * \enum struct drx_version * \brief Version information of one software module.
1311 * Used by DRX_CTRL_VERSION.
1313 struct drx_version {
1314 enum drx_module module_type;
1315 /**< Type identifier of the module */
1317 /**< Name or description of module */
1318 u16 v_major; /**< Major version number */
1319 u16 v_minor; /**< Minor version number */
1320 u16 v_patch; /**< Patch version number */
1321 char *v_string; /**< Version as text string */
1325 * \enum struct drx_version_list * \brief List element of NULL terminated, linked list for version information.
1327 * Used by DRX_CTRL_VERSION.
1329 struct drx_version_list {
1330 struct drx_version *version;/**< Version information */
1331 struct drx_version_list *next;
1332 /**< Next list element */
1335 /*========================================*/
1338 * \brief Parameters needed to confiugure a UIO.
1340 * Used by DRX_CTRL_UIO_CFG.
1344 /**< UIO identifier */
1345 enum drxuio_mode mode;
1346 /**< UIO operational mode */
1349 /*========================================*/
1352 * \brief Parameters needed to read from or write to a UIO.
1354 * Used by DRX_CTRL_UIO_READ and DRX_CTRL_UIO_WRITE.
1356 struct drxuio_data {
1358 /**< UIO identifier */
1360 /**< UIO value (true=1, false=0) */
1363 /*========================================*/
1366 * \brief Parameters needed to configure OOB.
1368 * Used by DRX_CTRL_SET_OOB.
1371 s32 frequency; /**< Frequency in kHz */
1372 enum drxoob_downstream_standard standard;
1373 /**< OOB standard */
1374 bool spectrum_inverted; /**< If true, then spectrum
1378 /*========================================*/
1381 * \brief Metrics from OOB.
1383 * Used by DRX_CTRL_GET_OOB.
1385 struct drxoob_status {
1386 s32 frequency; /**< Frequency in Khz */
1387 enum drx_lock_status lock; /**< Lock status */
1388 u32 mer; /**< MER */
1389 s32 symbol_rate_offset; /**< Symbolrate offset in ppm */
1392 /*========================================*/
1395 * \brief Device dependent configuration data.
1397 * Used by DRX_CTRL_SET_CFG and DRX_CTRL_GET_CFG.
1398 * A sort of nested drx_ctrl() functionality for device specific controls.
1402 /**< Function identifier */
1404 /**< Function data */
1407 /*========================================*/
1410 * /struct DRXMpegStartWidth_t
1411 * MStart width [nr MCLK cycles] for serial MPEG output.
1414 enum drxmpeg_str_width {
1415 DRX_MPEG_STR_WIDTH_1,
1416 DRX_MPEG_STR_WIDTH_8
1419 /* CTRL CFG MPEG ouput */
1421 * \struct struct drx_cfg_mpeg_output * \brief Configuartion parameters for MPEG output control.
1423 * Used by DRX_CFG_MPEG_OUTPUT, in combination with DRX_CTRL_SET_CFG and
1427 struct drx_cfg_mpeg_output {
1428 bool enable_mpeg_output;/**< If true, enable MPEG output */
1429 bool insert_rs_byte; /**< If true, insert RS byte */
1430 bool enable_parallel; /**< If true, parallel out otherwise
1432 bool invert_data; /**< If true, invert DATA signals */
1433 bool invert_err; /**< If true, invert ERR signal */
1434 bool invert_str; /**< If true, invert STR signals */
1435 bool invert_val; /**< If true, invert VAL signals */
1436 bool invert_clk; /**< If true, invert CLK signals */
1437 bool static_clk; /**< If true, static MPEG clockrate
1438 will be used, otherwise clockrate
1439 will adapt to the bitrate of the
1441 u32 bitrate; /**< Maximum bitrate in b/s in case
1442 static clockrate is selected */
1443 enum drxmpeg_str_width width_str;
1444 /**< MPEG start width */
1448 /*========================================*/
1451 * \struct struct drxi2c_data * \brief Data for I2C via 2nd or 3rd or etc I2C port.
1453 * Used by DRX_CTRL_I2C_READWRITE.
1454 * If port_nr is equal to primairy port_nr BSPI2C will be used.
1457 struct drxi2c_data {
1458 u16 port_nr; /**< I2C port number */
1459 struct i2c_device_addr *w_dev_addr;
1460 /**< Write device address */
1461 u16 w_count; /**< Size of write data in bytes */
1462 u8 *wData; /**< Pointer to write data */
1463 struct i2c_device_addr *r_dev_addr;
1464 /**< Read device address */
1465 u16 r_count; /**< Size of data to read in bytes */
1466 u8 *r_data; /**< Pointer to read buffer */
1469 /*========================================*/
1472 * \enum enum drx_aud_standard * \brief Audio standard identifier.
1474 * Used by DRX_CTRL_SET_AUD.
1476 enum drx_aud_standard {
1477 DRX_AUD_STANDARD_BTSC, /**< set BTSC standard (USA) */
1478 DRX_AUD_STANDARD_A2, /**< set A2-Korea FM Stereo */
1479 DRX_AUD_STANDARD_EIAJ, /**< set to Japanese FM Stereo */
1480 DRX_AUD_STANDARD_FM_STEREO,/**< set to FM-Stereo Radio */
1481 DRX_AUD_STANDARD_M_MONO, /**< for 4.5 MHz mono detected */
1482 DRX_AUD_STANDARD_D_K_MONO, /**< for 6.5 MHz mono detected */
1483 DRX_AUD_STANDARD_BG_FM, /**< set BG_FM standard */
1484 DRX_AUD_STANDARD_D_K1, /**< set D_K1 standard */
1485 DRX_AUD_STANDARD_D_K2, /**< set D_K2 standard */
1486 DRX_AUD_STANDARD_D_K3, /**< set D_K3 standard */
1487 DRX_AUD_STANDARD_BG_NICAM_FM,
1488 /**< set BG_NICAM_FM standard */
1489 DRX_AUD_STANDARD_L_NICAM_AM,
1490 /**< set L_NICAM_AM standard */
1491 DRX_AUD_STANDARD_I_NICAM_FM,
1492 /**< set I_NICAM_FM standard */
1493 DRX_AUD_STANDARD_D_K_NICAM_FM,
1494 /**< set D_K_NICAM_FM standard */
1495 DRX_AUD_STANDARD_NOT_READY,/**< used to detect audio standard */
1496 DRX_AUD_STANDARD_AUTO = DRX_AUTO,
1497 /**< Automatic Standard Detection */
1498 DRX_AUD_STANDARD_UNKNOWN = DRX_UNKNOWN
1499 /**< used as auto and for readback */
1502 /* CTRL_AUD_GET_STATUS - struct drx_aud_status */
1504 * \enum enum drx_aud_nicam_status * \brief Status of NICAM carrier.
1506 enum drx_aud_nicam_status {
1507 DRX_AUD_NICAM_DETECTED = 0,
1508 /**< NICAM carrier detected */
1509 DRX_AUD_NICAM_NOT_DETECTED,
1510 /**< NICAM carrier not detected */
1511 DRX_AUD_NICAM_BAD /**< NICAM carrier bad quality */
1515 * \struct struct drx_aud_status * \brief Audio status characteristics.
1517 struct drx_aud_status {
1518 bool stereo; /**< stereo detection */
1519 bool carrier_a; /**< carrier A detected */
1520 bool carrier_b; /**< carrier B detected */
1521 bool sap; /**< sap / bilingual detection */
1522 bool rds; /**< RDS data array present */
1523 enum drx_aud_nicam_status nicam_status;
1524 /**< status of NICAM carrier */
1525 s8 fm_ident; /**< FM Identification value */
1528 /* CTRL_AUD_READ_RDS - DRXRDSdata_t */
1531 * \struct DRXRDSdata_t
1532 * \brief Raw RDS data array.
1534 struct drx_cfg_aud_rds {
1535 bool valid; /**< RDS data validation */
1536 u16 data[18]; /**< data from one RDS data array */
1539 /* DRX_CFG_AUD_VOLUME - struct drx_cfg_aud_volume - set/get */
1541 * \enum DRXAudAVCDecayTime_t
1542 * \brief Automatic volume control configuration.
1544 enum drx_aud_avc_mode {
1545 DRX_AUD_AVC_OFF, /**< Automatic volume control off */
1546 DRX_AUD_AVC_DECAYTIME_8S, /**< level volume in 8 seconds */
1547 DRX_AUD_AVC_DECAYTIME_4S, /**< level volume in 4 seconds */
1548 DRX_AUD_AVC_DECAYTIME_2S, /**< level volume in 2 seconds */
1549 DRX_AUD_AVC_DECAYTIME_20MS/**< level volume in 20 millisec */
1553 * /enum DRXAudMaxAVCGain_t
1554 * /brief Automatic volume control max gain in audio baseband.
1556 enum drx_aud_avc_max_gain {
1557 DRX_AUD_AVC_MAX_GAIN_0DB, /**< maximum AVC gain 0 dB */
1558 DRX_AUD_AVC_MAX_GAIN_6DB, /**< maximum AVC gain 6 dB */
1559 DRX_AUD_AVC_MAX_GAIN_12DB /**< maximum AVC gain 12 dB */
1563 * /enum DRXAudMaxAVCAtten_t
1564 * /brief Automatic volume control max attenuation in audio baseband.
1566 enum drx_aud_avc_max_atten {
1567 DRX_AUD_AVC_MAX_ATTEN_12DB,
1568 /**< maximum AVC attenuation 12 dB */
1569 DRX_AUD_AVC_MAX_ATTEN_18DB,
1570 /**< maximum AVC attenuation 18 dB */
1571 DRX_AUD_AVC_MAX_ATTEN_24DB/**< maximum AVC attenuation 24 dB */
1574 * \struct struct drx_cfg_aud_volume * \brief Audio volume configuration.
1576 struct drx_cfg_aud_volume {
1577 bool mute; /**< mute overrides volume setting */
1578 s16 volume; /**< volume, range -114 to 12 dB */
1579 enum drx_aud_avc_mode avc_mode; /**< AVC auto volume control mode */
1580 u16 avc_ref_level; /**< AVC reference level */
1581 enum drx_aud_avc_max_gain avc_max_gain;
1582 /**< AVC max gain selection */
1583 enum drx_aud_avc_max_atten avc_max_atten;
1584 /**< AVC max attenuation selection */
1585 s16 strength_left; /**< quasi-peak, left speaker */
1586 s16 strength_right; /**< quasi-peak, right speaker */
1589 /* DRX_CFG_I2S_OUTPUT - struct drx_cfg_i2s_output - set/get */
1591 * \enum enum drxi2s_mode * \brief I2S output mode.
1594 DRX_I2S_MODE_MASTER, /**< I2S is in master mode */
1595 DRX_I2S_MODE_SLAVE /**< I2S is in slave mode */
1599 * \enum enum drxi2s_word_length * \brief Width of I2S data.
1601 enum drxi2s_word_length {
1602 DRX_I2S_WORDLENGTH_32 = 0,/**< I2S data is 32 bit wide */
1603 DRX_I2S_WORDLENGTH_16 = 1 /**< I2S data is 16 bit wide */
1607 * \enum enum drxi2s_format * \brief Data wordstrobe alignment for I2S.
1609 enum drxi2s_format {
1610 DRX_I2S_FORMAT_WS_WITH_DATA,
1611 /**< I2S data and wordstrobe are aligned */
1612 DRX_I2S_FORMAT_WS_ADVANCED
1613 /**< I2S data one cycle after wordstrobe */
1617 * \enum enum drxi2s_polarity * \brief Polarity of I2S data.
1619 enum drxi2s_polarity {
1620 DRX_I2S_POLARITY_RIGHT,/**< wordstrobe - right high, left low */
1621 DRX_I2S_POLARITY_LEFT /**< wordstrobe - right low, left high */
1625 * \struct struct drx_cfg_i2s_output * \brief I2S output configuration.
1627 struct drx_cfg_i2s_output {
1628 bool output_enable; /**< I2S output enable */
1629 u32 frequency; /**< range from 8000-48000 Hz */
1630 enum drxi2s_mode mode; /**< I2S mode, master or slave */
1631 enum drxi2s_word_length word_length;
1632 /**< I2S wordlength, 16 or 32 bits */
1633 enum drxi2s_polarity polarity;/**< I2S wordstrobe polarity */
1634 enum drxi2s_format format; /**< I2S wordstrobe delay to data */
1637 /* ------------------------------expert interface-----------------------------*/
1639 * /enum enum drx_aud_fm_deemphasis * setting for FM-Deemphasis in audio demodulator.
1642 enum drx_aud_fm_deemphasis {
1643 DRX_AUD_FM_DEEMPH_50US,
1644 DRX_AUD_FM_DEEMPH_75US,
1645 DRX_AUD_FM_DEEMPH_OFF
1649 * /enum DRXAudDeviation_t
1650 * setting for deviation mode in audio demodulator.
1653 enum drx_cfg_aud_deviation {
1654 DRX_AUD_DEVIATION_NORMAL,
1655 DRX_AUD_DEVIATION_HIGH
1659 * /enum enum drx_no_carrier_option * setting for carrier, mute/noise.
1662 enum drx_no_carrier_option {
1663 DRX_NO_CARRIER_MUTE,
1664 DRX_NO_CARRIER_NOISE
1668 * \enum DRXAudAutoSound_t
1669 * \brief Automatic Sound
1671 enum drx_cfg_aud_auto_sound {
1672 DRX_AUD_AUTO_SOUND_OFF = 0,
1673 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_ON,
1674 DRX_AUD_AUTO_SOUND_SELECT_ON_CHANGE_OFF
1678 * \enum DRXAudASSThres_t
1679 * \brief Automatic Sound Select Thresholds
1681 struct drx_cfg_aud_ass_thres {
1682 u16 a2; /* A2 Threshold for ASS configuration */
1683 u16 btsc; /* BTSC Threshold for ASS configuration */
1684 u16 nicam; /* Nicam Threshold for ASS configuration */
1688 * \struct struct drx_aud_carrier * \brief Carrier detection related parameters
1690 struct drx_aud_carrier {
1691 u16 thres; /* carrier detetcion threshold for primary carrier (A) */
1692 enum drx_no_carrier_option opt; /* Mute or noise at no carrier detection (A) */
1693 s32 shift; /* DC level of incoming signal (A) */
1694 s32 dco; /* frequency adjustment (A) */
1698 * \struct struct drx_cfg_aud_carriers * \brief combining carrier A & B to one struct
1700 struct drx_cfg_aud_carriers {
1701 struct drx_aud_carrier a;
1702 struct drx_aud_carrier b;
1706 * /enum enum drx_aud_i2s_src * Selection of audio source
1708 enum drx_aud_i2s_src {
1710 DRX_AUD_SRC_STEREO_OR_AB,
1711 DRX_AUD_SRC_STEREO_OR_A,
1712 DRX_AUD_SRC_STEREO_OR_B};
1715 * \enum enum drx_aud_i2s_matrix * \brief Used for selecting I2S output.
1717 enum drx_aud_i2s_matrix {
1718 DRX_AUD_I2S_MATRIX_A_MONO,
1719 /**< A sound only, stereo or mono */
1720 DRX_AUD_I2S_MATRIX_B_MONO,
1721 /**< B sound only, stereo or mono */
1722 DRX_AUD_I2S_MATRIX_STEREO,
1723 /**< A+B sound, transparant */
1724 DRX_AUD_I2S_MATRIX_MONO /**< A+B mixed to mono sum, (L+R)/2 */};
1727 * /enum enum drx_aud_fm_matrix * setting for FM-Matrix in audio demodulator.
1730 enum drx_aud_fm_matrix {
1731 DRX_AUD_FM_MATRIX_NO_MATRIX,
1732 DRX_AUD_FM_MATRIX_GERMAN,
1733 DRX_AUD_FM_MATRIX_KOREAN,
1734 DRX_AUD_FM_MATRIX_SOUND_A,
1735 DRX_AUD_FM_MATRIX_SOUND_B};
1738 * \struct DRXAudMatrices_t
1739 * \brief Mixer settings
1741 struct drx_cfg_aud_mixer {
1742 enum drx_aud_i2s_src source_i2s;
1743 enum drx_aud_i2s_matrix matrix_i2s;
1744 enum drx_aud_fm_matrix matrix_fm;
1748 * \enum DRXI2SVidSync_t
1749 * \brief Audio/video synchronization, interacts with I2S mode.
1750 * AUTO_1 and AUTO_2 are for automatic video standard detection with preference
1751 * for NTSC or Monochrome, because the frequencies are too close (59.94 & 60 Hz)
1753 enum drx_cfg_aud_av_sync {
1754 DRX_AUD_AVSYNC_OFF,/**< audio/video synchronization is off */
1755 DRX_AUD_AVSYNC_NTSC,
1756 /**< it is an NTSC system */
1757 DRX_AUD_AVSYNC_MONOCHROME,
1758 /**< it is a MONOCHROME system */
1759 DRX_AUD_AVSYNC_PAL_SECAM
1760 /**< it is a PAL/SECAM system */};
1763 * \struct struct drx_cfg_aud_prescale * \brief Prescalers
1765 struct drx_cfg_aud_prescale {
1771 * \struct struct drx_aud_beep * \brief Beep
1773 struct drx_aud_beep {
1774 s16 volume; /* dB */
1775 u16 frequency; /* Hz */
1780 * \enum enum drx_aud_btsc_detect * \brief BTSC detetcion mode
1782 enum drx_aud_btsc_detect {
1784 DRX_BTSC_MONO_AND_SAP};
1787 * \struct struct drx_aud_data * \brief Audio data structure
1789 struct drx_aud_data {
1791 bool audio_is_active;
1792 enum drx_aud_standard audio_standard;
1793 struct drx_cfg_i2s_output i2sdata;
1794 struct drx_cfg_aud_volume volume;
1795 enum drx_cfg_aud_auto_sound auto_sound;
1796 struct drx_cfg_aud_ass_thres ass_thresholds;
1797 struct drx_cfg_aud_carriers carriers;
1798 struct drx_cfg_aud_mixer mixer;
1799 enum drx_cfg_aud_deviation deviation;
1800 enum drx_cfg_aud_av_sync av_sync;
1801 struct drx_cfg_aud_prescale prescale;
1802 enum drx_aud_fm_deemphasis deemph;
1803 enum drx_aud_btsc_detect btsc_detect;
1805 u16 rds_data_counter;
1806 bool rds_data_present;
1810 * \enum enum drx_qam_lock_range * \brief QAM lock range mode
1812 enum drx_qam_lock_range {
1813 DRX_QAM_LOCKRANGE_NORMAL,
1814 DRX_QAM_LOCKRANGE_EXTENDED};
1816 /*============================================================================*/
1817 /*============================================================================*/
1818 /*== Data access structures ==================================================*/
1819 /*============================================================================*/
1820 /*============================================================================*/
1822 /* Address on device */
1823 typedef u32 dr_xaddr_t, *pdr_xaddr_t;
1825 /* Protocol specific flags */
1826 typedef u32 dr_xflags_t, *pdr_xflags_t;
1828 /* Write block of data to device */
1829 typedef int(*drx_write_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1830 u32 addr, /* address of register/memory */
1831 u16 datasize, /* size of data in bytes */
1832 u8 *data, /* data to send */
1835 /* Read block of data from device */
1836 typedef int(*drx_read_block_func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1837 u32 addr, /* address of register/memory */
1838 u16 datasize, /* size of data in bytes */
1839 u8 *data, /* receive buffer */
1842 /* Write 8-bits value to device */
1843 typedef int(*drx_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1844 u32 addr, /* address of register/memory */
1845 u8 data, /* data to send */
1848 /* Read 8-bits value to device */
1849 typedef int(*drx_read_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1850 u32 addr, /* address of register/memory */
1851 u8 *data, /* receive buffer */
1854 /* Read modify write 8-bits value to device */
1855 typedef int(*drx_read_modify_write_reg8func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1856 u32 waddr, /* write address of register */
1857 u32 raddr, /* read address of register */
1858 u8 wdata, /* data to write */
1859 u8 *rdata); /* data to read */
1861 /* Write 16-bits value to device */
1862 typedef int(*drx_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1863 u32 addr, /* address of register/memory */
1864 u16 data, /* data to send */
1867 /* Read 16-bits value to device */
1868 typedef int(*drx_read_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1869 u32 addr, /* address of register/memory */
1870 u16 *data, /* receive buffer */
1873 /* Read modify write 16-bits value to device */
1874 typedef int(*drx_read_modify_write_reg16func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1875 u32 waddr, /* write address of register */
1876 u32 raddr, /* read address of register */
1877 u16 wdata, /* data to write */
1878 u16 *rdata); /* data to read */
1880 /* Write 32-bits value to device */
1881 typedef int(*drx_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1882 u32 addr, /* address of register/memory */
1883 u32 data, /* data to send */
1886 /* Read 32-bits value to device */
1887 typedef int(*drx_read_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1888 u32 addr, /* address of register/memory */
1889 u32 *data, /* receive buffer */
1892 /* Read modify write 32-bits value to device */
1893 typedef int(*drx_read_modify_write_reg32func_t) (struct i2c_device_addr *dev_addr, /* address of I2C device */
1894 u32 waddr, /* write address of register */
1895 u32 raddr, /* read address of register */
1896 u32 wdata, /* data to write */
1897 u32 *rdata); /* data to read */
1900 * \struct struct drx_access_func * \brief Interface to an access protocol.
1902 struct drx_access_func {
1903 struct drx_version *protocolVersion;
1904 drx_write_block_func_t write_block_func;
1905 drx_read_block_func_t read_block_func;
1906 drx_write_reg8func_t write_reg8func;
1907 drx_read_reg8func_t read_reg8func;
1908 drx_read_modify_write_reg8func_t read_modify_write_reg8func;
1909 drx_write_reg16func_t write_reg16func;
1910 drx_read_reg16func_t read_reg16func;
1911 drx_read_modify_write_reg16func_t read_modify_write_reg16func;
1912 drx_write_reg32func_t write_reg32func;
1913 drx_read_reg32func_t read_reg32func;
1914 drx_read_modify_write_reg32func_t read_modify_write_reg32func;
1917 /* Register address and data for register dump function */
1918 struct drx_reg_dump {
1923 /*============================================================================*/
1924 /*============================================================================*/
1925 /*== Demod instance data structures ==========================================*/
1926 /*============================================================================*/
1927 /*============================================================================*/
1930 * \struct struct drx_common_attr * \brief Set of common attributes, shared by all DRX devices.
1932 struct drx_common_attr {
1933 /* Microcode (firmware) attributes */
1934 u8 *microcode; /**< Pointer to microcode image. */
1936 /**< Size of microcode image in bytes. */
1937 bool verify_microcode;
1938 /**< Use microcode verify or not. */
1939 struct drx_mc_version_rec mcversion;
1940 /**< Version record of microcode from file */
1942 /* Clocks and tuner attributes */
1943 s32 intermediate_freq;
1944 /**< IF,if tuner instance not used. (kHz)*/
1946 /**< Systemclock frequency. (kHz) */
1948 /**< Oscillator clock frequency. (kHz) */
1949 s16 osc_clock_deviation;
1950 /**< Oscillator clock deviation. (ppm) */
1951 bool mirror_freq_spect;
1952 /**< Mirror IF frequency spectrum or not.*/
1954 /* Initial MPEG output attributes */
1955 struct drx_cfg_mpeg_output mpeg_cfg;
1956 /**< MPEG configuration */
1958 bool is_opened; /**< if true instance is already opened. */
1961 struct drx_scan_param *scan_param;
1962 /**< scan parameters */
1963 u16 scan_freq_plan_index;
1964 /**< next index in freq plan */
1965 s32 scan_next_frequency;
1966 /**< next freq to scan */
1967 bool scan_ready; /**< scan ready flag */
1968 u32 scan_max_channels;/**< number of channels in freqplan */
1969 u32 scan_channels_scanned;
1970 /**< number of channels scanned */
1971 /* Channel scan - inner loop: demod related */
1972 drx_scan_func_t scan_function;
1973 /**< function to check channel */
1974 /* Channel scan - inner loop: SYSObj related */
1975 void *scan_context; /**< Context Pointer of SYSObj */
1976 /* Channel scan - parameters for default DTV scan function in core driver */
1977 u16 scan_demod_lock_timeout;
1978 /**< millisecs to wait for lock */
1979 enum drx_lock_status scan_desired_lock;
1980 /**< lock requirement for channel found */
1981 /* scan_active can be used by SetChannel to decide how to program the tuner,
1982 fast or slow (but stable). Usually fast during scan. */
1983 bool scan_active; /**< true when scan routines are active */
1985 /* Power management */
1986 enum drx_power_mode current_power_mode;
1987 /**< current power management mode */
1990 u8 tuner_port_nr; /**< nr of I2C port to wich tuner is */
1991 s32 tuner_min_freq_rf;
1992 /**< minimum RF input frequency, in kHz */
1993 s32 tuner_max_freq_rf;
1994 /**< maximum RF input frequency, in kHz */
1995 bool tuner_rf_agc_pol; /**< if true invert RF AGC polarity */
1996 bool tuner_if_agc_pol; /**< if true invert IF AGC polarity */
1997 bool tuner_slow_mode; /**< if true invert IF AGC polarity */
1999 struct drx_channel current_channel;
2000 /**< current channel parameters */
2001 enum drx_standard current_standard;
2002 /**< current standard selection */
2003 enum drx_standard prev_standard;
2004 /**< previous standard selection */
2005 enum drx_standard di_cache_standard;
2006 /**< standard in DI cache if available */
2007 bool use_bootloader; /**< use bootloader in open */
2008 u32 capabilities; /**< capabilities flags */
2009 u32 product_id; /**< product ID inc. metal fix number */};
2012 * Generic functions for DRX devices.
2015 struct drx_demod_instance;
2017 typedef int(*drx_open_func_t) (struct drx_demod_instance *demod);
2018 typedef int(*drx_close_func_t) (struct drx_demod_instance *demod);
2019 typedef int(*drx_ctrl_func_t) (struct drx_demod_instance *demod,
2024 * \struct struct drx_demod_func * \brief A stucture containing all functions of a demodulator.
2026 struct drx_demod_func {
2027 u32 type_id; /**< Device type identifier. */
2028 drx_open_func_t open_func; /**< Pointer to Open() function. */
2029 drx_close_func_t close_func;/**< Pointer to Close() function. */
2030 drx_ctrl_func_t ctrl_func; /**< Pointer to Ctrl() function. */};
2033 * \struct struct drx_demod_instance * \brief Top structure of demodulator instance.
2035 struct drx_demod_instance {
2036 /* type specific demodulator data */
2037 struct drx_demod_func *my_demod_funct;
2038 /**< demodulator functions */
2039 struct drx_access_func *my_access_funct;
2040 /**< data access protocol functions */
2041 struct tuner_instance *my_tuner;
2042 /**< tuner instance,if NULL then baseband */
2043 struct i2c_device_addr *my_i2c_dev_addr;
2044 /**< i2c address and device identifier */
2045 struct drx_common_attr *my_common_attr;
2046 /**< common DRX attributes */
2047 void *my_ext_attr; /**< device specific attributes */
2048 /* generic demodulator data */
2051 /*-------------------------------------------------------------------------
2053 Conversion from enum values to human readable form.
2054 -------------------------------------------------------------------------*/
2058 #define DRX_STR_STANDARD(x) ( \
2059 (x == DRX_STANDARD_DVBT) ? "DVB-T" : \
2060 (x == DRX_STANDARD_8VSB) ? "8VSB" : \
2061 (x == DRX_STANDARD_NTSC) ? "NTSC" : \
2062 (x == DRX_STANDARD_PAL_SECAM_BG) ? "PAL/SECAM B/G" : \
2063 (x == DRX_STANDARD_PAL_SECAM_DK) ? "PAL/SECAM D/K" : \
2064 (x == DRX_STANDARD_PAL_SECAM_I) ? "PAL/SECAM I" : \
2065 (x == DRX_STANDARD_PAL_SECAM_L) ? "PAL/SECAM L" : \
2066 (x == DRX_STANDARD_PAL_SECAM_LP) ? "PAL/SECAM LP" : \
2067 (x == DRX_STANDARD_ITU_A) ? "ITU-A" : \
2068 (x == DRX_STANDARD_ITU_B) ? "ITU-B" : \
2069 (x == DRX_STANDARD_ITU_C) ? "ITU-C" : \
2070 (x == DRX_STANDARD_ITU_D) ? "ITU-D" : \
2071 (x == DRX_STANDARD_FM) ? "FM" : \
2072 (x == DRX_STANDARD_DTMB) ? "DTMB" : \
2073 (x == DRX_STANDARD_AUTO) ? "Auto" : \
2074 (x == DRX_STANDARD_UNKNOWN) ? "Unknown" : \
2079 #define DRX_STR_BANDWIDTH(x) ( \
2080 (x == DRX_BANDWIDTH_8MHZ) ? "8 MHz" : \
2081 (x == DRX_BANDWIDTH_7MHZ) ? "7 MHz" : \
2082 (x == DRX_BANDWIDTH_6MHZ) ? "6 MHz" : \
2083 (x == DRX_BANDWIDTH_AUTO) ? "Auto" : \
2084 (x == DRX_BANDWIDTH_UNKNOWN) ? "Unknown" : \
2086 #define DRX_STR_FFTMODE(x) ( \
2087 (x == DRX_FFTMODE_2K) ? "2k" : \
2088 (x == DRX_FFTMODE_4K) ? "4k" : \
2089 (x == DRX_FFTMODE_8K) ? "8k" : \
2090 (x == DRX_FFTMODE_AUTO) ? "Auto" : \
2091 (x == DRX_FFTMODE_UNKNOWN) ? "Unknown" : \
2093 #define DRX_STR_GUARD(x) ( \
2094 (x == DRX_GUARD_1DIV32) ? "1/32nd" : \
2095 (x == DRX_GUARD_1DIV16) ? "1/16th" : \
2096 (x == DRX_GUARD_1DIV8) ? "1/8th" : \
2097 (x == DRX_GUARD_1DIV4) ? "1/4th" : \
2098 (x == DRX_GUARD_AUTO) ? "Auto" : \
2099 (x == DRX_GUARD_UNKNOWN) ? "Unknown" : \
2101 #define DRX_STR_CONSTELLATION(x) ( \
2102 (x == DRX_CONSTELLATION_BPSK) ? "BPSK" : \
2103 (x == DRX_CONSTELLATION_QPSK) ? "QPSK" : \
2104 (x == DRX_CONSTELLATION_PSK8) ? "PSK8" : \
2105 (x == DRX_CONSTELLATION_QAM16) ? "QAM16" : \
2106 (x == DRX_CONSTELLATION_QAM32) ? "QAM32" : \
2107 (x == DRX_CONSTELLATION_QAM64) ? "QAM64" : \
2108 (x == DRX_CONSTELLATION_QAM128) ? "QAM128" : \
2109 (x == DRX_CONSTELLATION_QAM256) ? "QAM256" : \
2110 (x == DRX_CONSTELLATION_QAM512) ? "QAM512" : \
2111 (x == DRX_CONSTELLATION_QAM1024) ? "QAM1024" : \
2112 (x == DRX_CONSTELLATION_QPSK_NR) ? "QPSK_NR" : \
2113 (x == DRX_CONSTELLATION_AUTO) ? "Auto" : \
2114 (x == DRX_CONSTELLATION_UNKNOWN) ? "Unknown" : \
2116 #define DRX_STR_CODERATE(x) ( \
2117 (x == DRX_CODERATE_1DIV2) ? "1/2nd" : \
2118 (x == DRX_CODERATE_2DIV3) ? "2/3rd" : \
2119 (x == DRX_CODERATE_3DIV4) ? "3/4th" : \
2120 (x == DRX_CODERATE_5DIV6) ? "5/6th" : \
2121 (x == DRX_CODERATE_7DIV8) ? "7/8th" : \
2122 (x == DRX_CODERATE_AUTO) ? "Auto" : \
2123 (x == DRX_CODERATE_UNKNOWN) ? "Unknown" : \
2125 #define DRX_STR_HIERARCHY(x) ( \
2126 (x == DRX_HIERARCHY_NONE) ? "None" : \
2127 (x == DRX_HIERARCHY_ALPHA1) ? "Alpha=1" : \
2128 (x == DRX_HIERARCHY_ALPHA2) ? "Alpha=2" : \
2129 (x == DRX_HIERARCHY_ALPHA4) ? "Alpha=4" : \
2130 (x == DRX_HIERARCHY_AUTO) ? "Auto" : \
2131 (x == DRX_HIERARCHY_UNKNOWN) ? "Unknown" : \
2133 #define DRX_STR_PRIORITY(x) ( \
2134 (x == DRX_PRIORITY_LOW) ? "Low" : \
2135 (x == DRX_PRIORITY_HIGH) ? "High" : \
2136 (x == DRX_PRIORITY_UNKNOWN) ? "Unknown" : \
2138 #define DRX_STR_MIRROR(x) ( \
2139 (x == DRX_MIRROR_NO) ? "Normal" : \
2140 (x == DRX_MIRROR_YES) ? "Mirrored" : \
2141 (x == DRX_MIRROR_AUTO) ? "Auto" : \
2142 (x == DRX_MIRROR_UNKNOWN) ? "Unknown" : \
2144 #define DRX_STR_CLASSIFICATION(x) ( \
2145 (x == DRX_CLASSIFICATION_GAUSS) ? "Gaussion" : \
2146 (x == DRX_CLASSIFICATION_HVY_GAUSS) ? "Heavy Gaussion" : \
2147 (x == DRX_CLASSIFICATION_COCHANNEL) ? "Co-channel" : \
2148 (x == DRX_CLASSIFICATION_STATIC) ? "Static echo" : \
2149 (x == DRX_CLASSIFICATION_MOVING) ? "Moving echo" : \
2150 (x == DRX_CLASSIFICATION_ZERODB) ? "Zero dB echo" : \
2151 (x == DRX_CLASSIFICATION_UNKNOWN) ? "Unknown" : \
2152 (x == DRX_CLASSIFICATION_AUTO) ? "Auto" : \
2155 #define DRX_STR_INTERLEAVEMODE(x) ( \
2156 (x == DRX_INTERLEAVEMODE_I128_J1) ? "I128_J1" : \
2157 (x == DRX_INTERLEAVEMODE_I128_J1_V2) ? "I128_J1_V2" : \
2158 (x == DRX_INTERLEAVEMODE_I128_J2) ? "I128_J2" : \
2159 (x == DRX_INTERLEAVEMODE_I64_J2) ? "I64_J2" : \
2160 (x == DRX_INTERLEAVEMODE_I128_J3) ? "I128_J3" : \
2161 (x == DRX_INTERLEAVEMODE_I32_J4) ? "I32_J4" : \
2162 (x == DRX_INTERLEAVEMODE_I128_J4) ? "I128_J4" : \
2163 (x == DRX_INTERLEAVEMODE_I16_J8) ? "I16_J8" : \
2164 (x == DRX_INTERLEAVEMODE_I128_J5) ? "I128_J5" : \
2165 (x == DRX_INTERLEAVEMODE_I8_J16) ? "I8_J16" : \
2166 (x == DRX_INTERLEAVEMODE_I128_J6) ? "I128_J6" : \
2167 (x == DRX_INTERLEAVEMODE_RESERVED_11) ? "Reserved 11" : \
2168 (x == DRX_INTERLEAVEMODE_I128_J7) ? "I128_J7" : \
2169 (x == DRX_INTERLEAVEMODE_RESERVED_13) ? "Reserved 13" : \
2170 (x == DRX_INTERLEAVEMODE_I128_J8) ? "I128_J8" : \
2171 (x == DRX_INTERLEAVEMODE_RESERVED_15) ? "Reserved 15" : \
2172 (x == DRX_INTERLEAVEMODE_I12_J17) ? "I12_J17" : \
2173 (x == DRX_INTERLEAVEMODE_I5_J4) ? "I5_J4" : \
2174 (x == DRX_INTERLEAVEMODE_B52_M240) ? "B52_M240" : \
2175 (x == DRX_INTERLEAVEMODE_B52_M720) ? "B52_M720" : \
2176 (x == DRX_INTERLEAVEMODE_B52_M48) ? "B52_M48" : \
2177 (x == DRX_INTERLEAVEMODE_B52_M0) ? "B52_M0" : \
2178 (x == DRX_INTERLEAVEMODE_UNKNOWN) ? "Unknown" : \
2179 (x == DRX_INTERLEAVEMODE_AUTO) ? "Auto" : \
2182 #define DRX_STR_LDPC(x) ( \
2183 (x == DRX_LDPC_0_4) ? "0.4" : \
2184 (x == DRX_LDPC_0_6) ? "0.6" : \
2185 (x == DRX_LDPC_0_8) ? "0.8" : \
2186 (x == DRX_LDPC_AUTO) ? "Auto" : \
2187 (x == DRX_LDPC_UNKNOWN) ? "Unknown" : \
2190 #define DRX_STR_CARRIER(x) ( \
2191 (x == DRX_CARRIER_MULTI) ? "Multi" : \
2192 (x == DRX_CARRIER_SINGLE) ? "Single" : \
2193 (x == DRX_CARRIER_AUTO) ? "Auto" : \
2194 (x == DRX_CARRIER_UNKNOWN) ? "Unknown" : \
2197 #define DRX_STR_FRAMEMODE(x) ( \
2198 (x == DRX_FRAMEMODE_420) ? "420" : \
2199 (x == DRX_FRAMEMODE_595) ? "595" : \
2200 (x == DRX_FRAMEMODE_945) ? "945" : \
2201 (x == DRX_FRAMEMODE_420_FIXED_PN) ? "420 with fixed PN" : \
2202 (x == DRX_FRAMEMODE_945_FIXED_PN) ? "945 with fixed PN" : \
2203 (x == DRX_FRAMEMODE_AUTO) ? "Auto" : \
2204 (x == DRX_FRAMEMODE_UNKNOWN) ? "Unknown" : \
2207 #define DRX_STR_PILOT(x) ( \
2208 (x == DRX_PILOT_ON) ? "On" : \
2209 (x == DRX_PILOT_OFF) ? "Off" : \
2210 (x == DRX_PILOT_AUTO) ? "Auto" : \
2211 (x == DRX_PILOT_UNKNOWN) ? "Unknown" : \
2215 #define DRX_STR_TPS_FRAME(x) ( \
2216 (x == DRX_TPS_FRAME1) ? "Frame1" : \
2217 (x == DRX_TPS_FRAME2) ? "Frame2" : \
2218 (x == DRX_TPS_FRAME3) ? "Frame3" : \
2219 (x == DRX_TPS_FRAME4) ? "Frame4" : \
2220 (x == DRX_TPS_FRAME_UNKNOWN) ? "Unknown" : \
2225 #define DRX_STR_LOCKSTATUS(x) ( \
2226 (x == DRX_NEVER_LOCK) ? "Never" : \
2227 (x == DRX_NOT_LOCKED) ? "No" : \
2228 (x == DRX_LOCKED) ? "Locked" : \
2229 (x == DRX_LOCK_STATE_1) ? "Lock state 1" : \
2230 (x == DRX_LOCK_STATE_2) ? "Lock state 2" : \
2231 (x == DRX_LOCK_STATE_3) ? "Lock state 3" : \
2232 (x == DRX_LOCK_STATE_4) ? "Lock state 4" : \
2233 (x == DRX_LOCK_STATE_5) ? "Lock state 5" : \
2234 (x == DRX_LOCK_STATE_6) ? "Lock state 6" : \
2235 (x == DRX_LOCK_STATE_7) ? "Lock state 7" : \
2236 (x == DRX_LOCK_STATE_8) ? "Lock state 8" : \
2237 (x == DRX_LOCK_STATE_9) ? "Lock state 9" : \
2240 /* version information , modules */
2241 #define DRX_STR_MODULE(x) ( \
2242 (x == DRX_MODULE_DEVICE) ? "Device" : \
2243 (x == DRX_MODULE_MICROCODE) ? "Microcode" : \
2244 (x == DRX_MODULE_DRIVERCORE) ? "CoreDriver" : \
2245 (x == DRX_MODULE_DEVICEDRIVER) ? "DeviceDriver" : \
2246 (x == DRX_MODULE_BSP_I2C) ? "BSP I2C" : \
2247 (x == DRX_MODULE_BSP_TUNER) ? "BSP Tuner" : \
2248 (x == DRX_MODULE_BSP_HOST) ? "BSP Host" : \
2249 (x == DRX_MODULE_DAP) ? "Data Access Protocol" : \
2250 (x == DRX_MODULE_UNKNOWN) ? "Unknown" : \
2253 #define DRX_STR_POWER_MODE(x) ( \
2254 (x == DRX_POWER_UP) ? "DRX_POWER_UP " : \
2255 (x == DRX_POWER_MODE_1) ? "DRX_POWER_MODE_1" : \
2256 (x == DRX_POWER_MODE_2) ? "DRX_POWER_MODE_2" : \
2257 (x == DRX_POWER_MODE_3) ? "DRX_POWER_MODE_3" : \
2258 (x == DRX_POWER_MODE_4) ? "DRX_POWER_MODE_4" : \
2259 (x == DRX_POWER_MODE_5) ? "DRX_POWER_MODE_5" : \
2260 (x == DRX_POWER_MODE_6) ? "DRX_POWER_MODE_6" : \
2261 (x == DRX_POWER_MODE_7) ? "DRX_POWER_MODE_7" : \
2262 (x == DRX_POWER_MODE_8) ? "DRX_POWER_MODE_8" : \
2263 (x == DRX_POWER_MODE_9) ? "DRX_POWER_MODE_9" : \
2264 (x == DRX_POWER_MODE_10) ? "DRX_POWER_MODE_10" : \
2265 (x == DRX_POWER_MODE_11) ? "DRX_POWER_MODE_11" : \
2266 (x == DRX_POWER_MODE_12) ? "DRX_POWER_MODE_12" : \
2267 (x == DRX_POWER_MODE_13) ? "DRX_POWER_MODE_13" : \
2268 (x == DRX_POWER_MODE_14) ? "DRX_POWER_MODE_14" : \
2269 (x == DRX_POWER_MODE_15) ? "DRX_POWER_MODE_15" : \
2270 (x == DRX_POWER_MODE_16) ? "DRX_POWER_MODE_16" : \
2271 (x == DRX_POWER_DOWN) ? "DRX_POWER_DOWN " : \
2274 #define DRX_STR_OOB_STANDARD(x) ( \
2275 (x == DRX_OOB_MODE_A) ? "ANSI 55-1 " : \
2276 (x == DRX_OOB_MODE_B_GRADE_A) ? "ANSI 55-2 A" : \
2277 (x == DRX_OOB_MODE_B_GRADE_B) ? "ANSI 55-2 B" : \
2280 #define DRX_STR_AUD_STANDARD(x) ( \
2281 (x == DRX_AUD_STANDARD_BTSC) ? "BTSC" : \
2282 (x == DRX_AUD_STANDARD_A2) ? "A2" : \
2283 (x == DRX_AUD_STANDARD_EIAJ) ? "EIAJ" : \
2284 (x == DRX_AUD_STANDARD_FM_STEREO) ? "FM Stereo" : \
2285 (x == DRX_AUD_STANDARD_AUTO) ? "Auto" : \
2286 (x == DRX_AUD_STANDARD_M_MONO) ? "M-Standard Mono" : \
2287 (x == DRX_AUD_STANDARD_D_K_MONO) ? "D/K Mono FM" : \
2288 (x == DRX_AUD_STANDARD_BG_FM) ? "B/G-Dual Carrier FM (A2)" : \
2289 (x == DRX_AUD_STANDARD_D_K1) ? "D/K1-Dual Carrier FM" : \
2290 (x == DRX_AUD_STANDARD_D_K2) ? "D/K2-Dual Carrier FM" : \
2291 (x == DRX_AUD_STANDARD_D_K3) ? "D/K3-Dual Carrier FM" : \
2292 (x == DRX_AUD_STANDARD_BG_NICAM_FM) ? "B/G-NICAM-FM" : \
2293 (x == DRX_AUD_STANDARD_L_NICAM_AM) ? "L-NICAM-AM" : \
2294 (x == DRX_AUD_STANDARD_I_NICAM_FM) ? "I-NICAM-FM" : \
2295 (x == DRX_AUD_STANDARD_D_K_NICAM_FM) ? "D/K-NICAM-FM" : \
2296 (x == DRX_AUD_STANDARD_UNKNOWN) ? "Unknown" : \
2298 #define DRX_STR_AUD_STEREO(x) ( \
2299 (x == true) ? "Stereo" : \
2300 (x == false) ? "Mono" : \
2303 #define DRX_STR_AUD_SAP(x) ( \
2304 (x == true) ? "Present" : \
2305 (x == false) ? "Not present" : \
2308 #define DRX_STR_AUD_CARRIER(x) ( \
2309 (x == true) ? "Present" : \
2310 (x == false) ? "Not present" : \
2313 #define DRX_STR_AUD_RDS(x) ( \
2314 (x == true) ? "Available" : \
2315 (x == false) ? "Not Available" : \
2318 #define DRX_STR_AUD_NICAM_STATUS(x) ( \
2319 (x == DRX_AUD_NICAM_DETECTED) ? "Detected" : \
2320 (x == DRX_AUD_NICAM_NOT_DETECTED) ? "Not detected" : \
2321 (x == DRX_AUD_NICAM_BAD) ? "Bad" : \
2324 #define DRX_STR_RDS_VALID(x) ( \
2325 (x == true) ? "Valid" : \
2326 (x == false) ? "Not Valid" : \
2329 /*-------------------------------------------------------------------------
2331 -------------------------------------------------------------------------*/
2334 * \brief Create a compilable reference to the microcode attribute
2335 * \param d pointer to demod instance
2337 * Used as main reference to an attribute field.
2338 * Used by both macro implementation and function implementation.
2339 * These macros are defined to avoid duplication of code in macro and function
2340 * definitions that handle access of demod common or extended attributes.
2344 #define DRX_ATTR_MCRECORD(d) ((d)->my_common_attr->mcversion)
2345 #define DRX_ATTR_MIRRORFREQSPECT(d) ((d)->my_common_attr->mirror_freq_spect)
2346 #define DRX_ATTR_CURRENTPOWERMODE(d)((d)->my_common_attr->current_power_mode)
2347 #define DRX_ATTR_ISOPENED(d) ((d)->my_common_attr->is_opened)
2348 #define DRX_ATTR_USEBOOTLOADER(d) ((d)->my_common_attr->use_bootloader)
2349 #define DRX_ATTR_CURRENTSTANDARD(d) ((d)->my_common_attr->current_standard)
2350 #define DRX_ATTR_PREVSTANDARD(d) ((d)->my_common_attr->prev_standard)
2351 #define DRX_ATTR_CACHESTANDARD(d) ((d)->my_common_attr->di_cache_standard)
2352 #define DRX_ATTR_CURRENTCHANNEL(d) ((d)->my_common_attr->current_channel)
2353 #define DRX_ATTR_MICROCODE(d) ((d)->my_common_attr->microcode)
2354 #define DRX_ATTR_MICROCODESIZE(d) ((d)->my_common_attr->microcode_size)
2355 #define DRX_ATTR_VERIFYMICROCODE(d) ((d)->my_common_attr->verify_microcode)
2356 #define DRX_ATTR_CAPABILITIES(d) ((d)->my_common_attr->capabilities)
2357 #define DRX_ATTR_PRODUCTID(d) ((d)->my_common_attr->product_id)
2358 #define DRX_ATTR_INTERMEDIATEFREQ(d) ((d)->my_common_attr->intermediate_freq)
2359 #define DRX_ATTR_SYSCLOCKFREQ(d) ((d)->my_common_attr->sys_clock_freq)
2360 #define DRX_ATTR_TUNERRFAGCPOL(d) ((d)->my_common_attr->tuner_rf_agc_pol)
2361 #define DRX_ATTR_TUNERIFAGCPOL(d) ((d)->my_common_attr->tuner_if_agc_pol)
2362 #define DRX_ATTR_TUNERSLOWMODE(d) ((d)->my_common_attr->tuner_slow_mode)
2363 #define DRX_ATTR_TUNERSPORTNR(d) ((d)->my_common_attr->tuner_port_nr)
2364 #define DRX_ATTR_TUNER(d) ((d)->my_tuner)
2365 #define DRX_ATTR_I2CADDR(d) ((d)->my_i2c_dev_addr->i2c_addr)
2366 #define DRX_ATTR_I2CDEVID(d) ((d)->my_i2c_dev_addr->i2c_dev_id)
2367 #define DRX_ISMCVERTYPE(x) ((x) == AUX_VER_RECORD)
2369 /**************************/
2371 /* Macros with device-specific handling are converted to CFG functions */
2373 #define DRX_ACCESSMACRO_SET(demod, value, cfg_name, data_type) \
2375 struct drx_cfg config; \
2376 data_type cfg_data; \
2377 config.cfg_type = cfg_name; \
2378 config.cfg_data = &cfg_data; \
2380 drx_ctrl(demod, DRX_CTRL_SET_CFG, &config); \
2383 #define DRX_ACCESSMACRO_GET(demod, value, cfg_name, data_type, error_value) \
2386 struct drx_cfg config; \
2387 data_type cfg_data; \
2388 config.cfg_type = cfg_name; \
2389 config.cfg_data = &cfg_data; \
2390 cfg_status = drx_ctrl(demod, DRX_CTRL_GET_CFG, &config); \
2391 if (cfg_status == 0) { \
2394 value = (data_type)error_value; \
2398 /* Configuration functions for usage by Access (XS) Macros */
2400 #ifndef DRX_XS_CFG_BASE
2401 #define DRX_XS_CFG_BASE (500)
2404 #define DRX_XS_CFG_PRESET (DRX_XS_CFG_BASE + 0)
2405 #define DRX_XS_CFG_AUD_BTSC_DETECT (DRX_XS_CFG_BASE + 1)
2406 #define DRX_XS_CFG_QAM_LOCKRANGE (DRX_XS_CFG_BASE + 2)
2408 /* Access Macros with device-specific handling */
2410 #define DRX_SET_PRESET(d, x) \
2411 DRX_ACCESSMACRO_SET((d), (x), DRX_XS_CFG_PRESET, char*)
2412 #define DRX_GET_PRESET(d, x) \
2413 DRX_ACCESSMACRO_GET((d), (x), DRX_XS_CFG_PRESET, char*, "ERROR")
2415 #define DRX_SET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2416 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect)
2417 #define DRX_GET_AUD_BTSC_DETECT(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2418 DRX_XS_CFG_AUD_BTSC_DETECT, enum drx_aud_btsc_detect, DRX_UNKNOWN)
2420 #define DRX_SET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_SET((d), (x), \
2421 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range)
2422 #define DRX_GET_QAM_LOCKRANGE(d, x) DRX_ACCESSMACRO_GET((d), (x), \
2423 DRX_XS_CFG_QAM_LOCKRANGE, enum drx_qam_lock_range, DRX_UNKNOWN)
2426 * \brief Macro to check if std is an ATV standard
2427 * \retval true std is an ATV standard
2428 * \retval false std is an ATV standard
2430 #define DRX_ISATVSTD(std) (((std) == DRX_STANDARD_PAL_SECAM_BG) || \
2431 ((std) == DRX_STANDARD_PAL_SECAM_DK) || \
2432 ((std) == DRX_STANDARD_PAL_SECAM_I) || \
2433 ((std) == DRX_STANDARD_PAL_SECAM_L) || \
2434 ((std) == DRX_STANDARD_PAL_SECAM_LP) || \
2435 ((std) == DRX_STANDARD_NTSC) || \
2436 ((std) == DRX_STANDARD_FM))
2439 * \brief Macro to check if std is an QAM standard
2440 * \retval true std is an QAM standards
2441 * \retval false std is an QAM standards
2443 #define DRX_ISQAMSTD(std) (((std) == DRX_STANDARD_ITU_A) || \
2444 ((std) == DRX_STANDARD_ITU_B) || \
2445 ((std) == DRX_STANDARD_ITU_C) || \
2446 ((std) == DRX_STANDARD_ITU_D))
2449 * \brief Macro to check if std is VSB standard
2450 * \retval true std is VSB standard
2451 * \retval false std is not VSB standard
2453 #define DRX_ISVSBSTD(std) ((std) == DRX_STANDARD_8VSB)
2456 * \brief Macro to check if std is DVBT standard
2457 * \retval true std is DVBT standard
2458 * \retval false std is not DVBT standard
2460 #define DRX_ISDVBTSTD(std) ((std) == DRX_STANDARD_DVBT)
2462 /*-------------------------------------------------------------------------
2464 -------------------------------------------------------------------------*/
2466 int drx_init(struct drx_demod_instance *demods[]);
2470 int drx_open(struct drx_demod_instance *demod);
2472 int drx_close(struct drx_demod_instance *demod);
2474 int drx_ctrl(struct drx_demod_instance *demod,
2475 u32 ctrl, void *ctrl_data);
2477 /*-------------------------------------------------------------------------
2479 -------------------------------------------------------------------------*/
2480 #endif /* __DRXDRIVER_H__ */