2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf-dma-sg.h>
35 #include <media/soc_camera.h>
36 #include <media/drv-intf/soc_mediabus.h>
37 #include <media/v4l2-of.h>
39 #include <linux/videodev2.h>
42 #include <linux/platform_data/media/camera-pxa.h>
44 #define PXA_CAM_VERSION "0.0.6"
45 #define PXA_CAM_DRV_NAME "pxa27x-camera"
47 /* Camera Interface */
60 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
61 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
62 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
63 #define CICR0_ENB (1 << 28) /* Camera interface enable */
64 #define CICR0_DIS (1 << 27) /* Camera interface disable */
65 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
66 #define CICR0_TOM (1 << 9) /* Time-out mask */
67 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
68 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
69 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
70 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
71 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
72 #define CICR0_CDM (1 << 3) /* Disable-done mask */
73 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
74 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
75 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
77 #define CICR1_TBIT (1 << 31) /* Transparency bit */
78 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
79 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
80 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
81 #define CICR1_RGB_F (1 << 11) /* RGB format */
82 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
83 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
84 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
85 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
86 #define CICR1_DW (0x7 << 0) /* Data width mask */
88 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
90 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
92 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
93 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
95 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
98 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
100 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
102 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
103 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
105 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
107 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
108 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
109 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
110 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
111 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
112 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
113 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
114 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
116 #define CISR_FTO (1 << 15) /* FIFO time-out */
117 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
118 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
119 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
120 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
121 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
122 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
123 #define CISR_EOL (1 << 8) /* End of line */
124 #define CISR_PAR_ERR (1 << 7) /* Parity error */
125 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
126 #define CISR_CDD (1 << 5) /* Camera interface disable done */
127 #define CISR_SOF (1 << 4) /* Start of frame */
128 #define CISR_EOF (1 << 3) /* End of frame */
129 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
130 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
131 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
133 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
134 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
135 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
136 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
137 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
138 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
139 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
140 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
142 #define CICR0_SIM_MP (0 << 24)
143 #define CICR0_SIM_SP (1 << 24)
144 #define CICR0_SIM_MS (2 << 24)
145 #define CICR0_SIM_EP (3 << 24)
146 #define CICR0_SIM_ES (4 << 24)
148 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
149 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
150 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
151 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
152 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
154 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
155 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
156 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
157 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
158 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
160 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
161 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
162 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
163 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
165 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
166 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
167 CICR0_EOFM | CICR0_FOM)
172 enum pxa_camera_active_dma {
178 /* descriptor needed for the PXA DMA engine */
181 struct pxa_dma_desc *sg_cpu;
186 /* buffer for one video frame */
188 /* common v4l buffer stuff -- must be first */
189 struct videobuf_buffer vb;
191 /* our descriptor lists for Y, U and V channels */
192 struct pxa_cam_dma dmas[3];
194 enum pxa_camera_active_dma active_dma;
197 struct pxa_camera_dev {
198 struct soc_camera_host soc_host;
200 * PXA27x is only supposed to handle one camera on its Quick Capture
201 * interface. If anyone ever builds hardware to enable more than
202 * one camera, they will have to modify this driver too
210 unsigned int dma_chans[3];
212 struct pxacamera_platform_data *pdata;
213 struct resource *res;
214 unsigned long platform_flags;
218 u16 width_flags; /* max 10 bits */
220 struct list_head capture;
224 struct pxa_buffer *active;
225 struct pxa_dma_desc *sg_tail[3];
234 static const char *pxa_cam_driver_description = "PXA_Camera";
236 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
239 * Videobuf operations
241 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
244 struct soc_camera_device *icd = vq->priv_data;
246 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
248 *size = icd->sizeimage;
252 if (*size * *count > vid_limit * 1024 * 1024)
253 *count = (vid_limit * 1024 * 1024) / *size;
258 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
260 struct soc_camera_device *icd = vq->priv_data;
261 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
262 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
265 BUG_ON(in_interrupt());
267 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
268 &buf->vb, buf->vb.baddr, buf->vb.bsize);
271 * This waits until this buffer is out of danger, i.e., until it is no
272 * longer in STATE_QUEUED or STATE_ACTIVE
274 videobuf_waiton(vq, &buf->vb, 0, 0);
276 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
277 if (buf->dmas[i].sg_cpu)
278 dma_free_coherent(ici->v4l2_dev.dev,
279 buf->dmas[i].sg_size,
281 buf->dmas[i].sg_dma);
282 buf->dmas[i].sg_cpu = NULL;
284 videobuf_dma_unmap(vq->dev, dma);
285 videobuf_dma_free(dma);
287 buf->vb.state = VIDEOBUF_NEEDS_INIT;
290 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
291 int sg_first_ofs, int size)
293 int i, offset, dma_len, xfer_len;
294 struct scatterlist *sg;
296 offset = sg_first_ofs;
297 for_each_sg(sglist, sg, sglen, i) {
298 dma_len = sg_dma_len(sg);
300 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
301 xfer_len = roundup(min(dma_len - offset, size), 8);
303 size = max(0, size - xfer_len);
314 * pxa_init_dma_channel - init dma descriptors
315 * @pcdev: pxa camera device
316 * @buf: pxa buffer to find pxa dma channel
317 * @dma: dma video buffer
318 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
319 * @cibr: camera Receive Buffer Register
320 * @size: bytes to transfer
321 * @sg_first: first element of sg_list
322 * @sg_first_ofs: offset in first element of sg_list
324 * Prepares the pxa dma descriptors to transfer one camera channel.
325 * Beware sg_first and sg_first_ofs are both input and output parameters.
327 * Returns 0 or -ENOMEM if no coherent memory is available
329 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
330 struct pxa_buffer *buf,
331 struct videobuf_dmabuf *dma, int channel,
333 struct scatterlist **sg_first, int *sg_first_ofs)
335 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
336 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
337 struct scatterlist *sg;
338 int i, offset, sglen;
339 int dma_len = 0, xfer_len = 0;
342 dma_free_coherent(dev, pxa_dma->sg_size,
343 pxa_dma->sg_cpu, pxa_dma->sg_dma);
345 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
346 *sg_first_ofs, size);
348 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
349 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
350 &pxa_dma->sg_dma, GFP_KERNEL);
351 if (!pxa_dma->sg_cpu)
354 pxa_dma->sglen = sglen;
355 offset = *sg_first_ofs;
357 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
358 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
361 for_each_sg(*sg_first, sg, sglen, i) {
362 dma_len = sg_dma_len(sg);
364 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
365 xfer_len = roundup(min(dma_len - offset, size), 8);
367 size = max(0, size - xfer_len);
369 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
370 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
371 pxa_dma->sg_cpu[i].dcmd =
372 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
375 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
377 pxa_dma->sg_cpu[i].ddadr =
378 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
380 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
381 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
382 sg_dma_address(sg) + offset, xfer_len);
389 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
390 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
393 * Handle 1 special case :
394 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
395 * to dma_len (end on PAGE boundary). In this case, the sg element
396 * for next plane should be the next after the last used to store the
397 * last scatter gather RAM page
399 if (xfer_len >= dma_len) {
400 *sg_first_ofs = xfer_len - dma_len;
401 *sg_first = sg_next(sg);
403 *sg_first_ofs = xfer_len;
410 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
411 struct pxa_buffer *buf)
413 buf->active_dma = DMA_Y;
414 if (pcdev->channels == 3)
415 buf->active_dma |= DMA_U | DMA_V;
419 * Please check the DMA prepared buffer structure in :
420 * Documentation/video4linux/pxa_camera.txt
421 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
422 * modification while DMA chain is running will work anyway.
424 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
425 struct videobuf_buffer *vb, enum v4l2_field field)
427 struct soc_camera_device *icd = vq->priv_data;
428 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
429 struct pxa_camera_dev *pcdev = ici->priv;
430 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
431 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
433 int size_y, size_u = 0, size_v = 0;
435 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
436 vb, vb->baddr, vb->bsize);
438 /* Added list head initialization on alloc */
439 WARN_ON(!list_empty(&vb->queue));
443 * This can be useful if you want to see if we actually fill
444 * the buffer with something
446 memset((void *)vb->baddr, 0xaa, vb->bsize);
449 BUG_ON(NULL == icd->current_fmt);
452 * I think, in buf_prepare you only have to protect global data,
453 * the actual buffer is yours
457 if (buf->code != icd->current_fmt->code ||
458 vb->width != icd->user_width ||
459 vb->height != icd->user_height ||
460 vb->field != field) {
461 buf->code = icd->current_fmt->code;
462 vb->width = icd->user_width;
463 vb->height = icd->user_height;
465 vb->state = VIDEOBUF_NEEDS_INIT;
468 vb->size = icd->sizeimage;
469 if (0 != vb->baddr && vb->bsize < vb->size) {
474 if (vb->state == VIDEOBUF_NEEDS_INIT) {
477 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
478 struct scatterlist *sg;
480 ret = videobuf_iolock(vq, vb, NULL);
484 if (pcdev->channels == 3) {
486 size_u = size_v = size / 4;
493 /* init DMA for Y channel */
494 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
497 dev_err(dev, "DMA initialization for Y/RGB failed\n");
501 /* init DMA for U channel */
503 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
504 size_u, &sg, &next_ofs);
506 dev_err(dev, "DMA initialization for U failed\n");
510 /* init DMA for V channel */
512 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
513 size_v, &sg, &next_ofs);
515 dev_err(dev, "DMA initialization for V failed\n");
519 vb->state = VIDEOBUF_PREPARED;
523 pxa_videobuf_set_actdma(pcdev, buf);
528 free_buffer(vq, buf);
535 * pxa_dma_start_channels - start DMA channel for active buffer
536 * @pcdev: pxa camera device
538 * Initialize DMA channels to the beginning of the active video buffer, and
539 * start these channels.
541 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
544 struct pxa_buffer *active;
546 active = pcdev->active;
548 for (i = 0; i < pcdev->channels; i++) {
549 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
550 "%s (channel=%d) ddadr=%08x\n", __func__,
551 i, active->dmas[i].sg_dma);
552 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
553 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
557 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
561 for (i = 0; i < pcdev->channels; i++) {
562 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
563 "%s (channel=%d)\n", __func__, i);
564 DCSR(pcdev->dma_chans[i]) = 0;
568 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
569 struct pxa_buffer *buf)
572 struct pxa_dma_desc *buf_last_desc;
574 for (i = 0; i < pcdev->channels; i++) {
575 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
576 buf_last_desc->ddadr = DDADR_STOP;
578 if (pcdev->sg_tail[i])
579 /* Link the new buffer to the old tail */
580 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
582 /* Update the channel tail */
583 pcdev->sg_tail[i] = buf_last_desc;
588 * pxa_camera_start_capture - start video capturing
589 * @pcdev: camera device
591 * Launch capturing. DMA channels should not be active yet. They should get
592 * activated at the end of frame interrupt, to capture only whole frames, and
593 * never begin the capture of a partial frame.
595 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
599 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
600 /* Enable End-Of-Frame Interrupt */
601 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
602 cicr0 &= ~CICR0_EOFM;
603 __raw_writel(cicr0, pcdev->base + CICR0);
606 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
610 pxa_dma_stop_channels(pcdev);
612 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
613 __raw_writel(cicr0, pcdev->base + CICR0);
615 pcdev->active = NULL;
616 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
619 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
620 static void pxa_videobuf_queue(struct videobuf_queue *vq,
621 struct videobuf_buffer *vb)
623 struct soc_camera_device *icd = vq->priv_data;
624 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
625 struct pxa_camera_dev *pcdev = ici->priv;
626 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
628 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
629 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
631 list_add_tail(&vb->queue, &pcdev->capture);
633 vb->state = VIDEOBUF_ACTIVE;
634 pxa_dma_add_tail_buf(pcdev, buf);
637 pxa_camera_start_capture(pcdev);
640 static void pxa_videobuf_release(struct videobuf_queue *vq,
641 struct videobuf_buffer *vb)
643 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
645 struct soc_camera_device *icd = vq->priv_data;
646 struct device *dev = icd->parent;
648 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
649 vb, vb->baddr, vb->bsize);
652 case VIDEOBUF_ACTIVE:
653 dev_dbg(dev, "%s (active)\n", __func__);
655 case VIDEOBUF_QUEUED:
656 dev_dbg(dev, "%s (queued)\n", __func__);
658 case VIDEOBUF_PREPARED:
659 dev_dbg(dev, "%s (prepared)\n", __func__);
662 dev_dbg(dev, "%s (unknown)\n", __func__);
667 free_buffer(vq, buf);
670 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
671 struct videobuf_buffer *vb,
672 struct pxa_buffer *buf)
676 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
677 list_del_init(&vb->queue);
678 vb->state = VIDEOBUF_DONE;
679 v4l2_get_timestamp(&vb->ts);
682 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
685 if (list_empty(&pcdev->capture)) {
686 pxa_camera_stop_capture(pcdev);
687 for (i = 0; i < pcdev->channels; i++)
688 pcdev->sg_tail[i] = NULL;
692 pcdev->active = list_entry(pcdev->capture.next,
693 struct pxa_buffer, vb.queue);
697 * pxa_camera_check_link_miss - check missed DMA linking
698 * @pcdev: camera device
700 * The DMA chaining is done with DMA running. This means a tiny temporal window
701 * remains, where a buffer is queued on the chain, while the chain is already
702 * stopped. This means the tailed buffer would never be transferred by DMA.
703 * This function restarts the capture for this corner case, where :
704 * - DADR() == DADDR_STOP
705 * - a videobuffer is queued on the pcdev->capture list
707 * Please check the "DMA hot chaining timeslice issue" in
708 * Documentation/video4linux/pxa_camera.txt
710 * Context: should only be called within the dma irq handler
712 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
714 int i, is_dma_stopped = 1;
716 for (i = 0; i < pcdev->channels; i++)
717 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
719 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
720 "%s : top queued buffer=%p, dma_stopped=%d\n",
721 __func__, pcdev->active, is_dma_stopped);
722 if (pcdev->active && is_dma_stopped)
723 pxa_camera_start_capture(pcdev);
726 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
727 enum pxa_camera_active_dma act_dma)
729 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
730 struct pxa_buffer *buf;
732 u32 status, camera_status, overrun;
733 struct videobuf_buffer *vb;
735 spin_lock_irqsave(&pcdev->lock, flags);
737 status = DCSR(channel);
738 DCSR(channel) = status;
740 camera_status = __raw_readl(pcdev->base + CISR);
741 overrun = CISR_IFO_0;
742 if (pcdev->channels == 3)
743 overrun |= CISR_IFO_1 | CISR_IFO_2;
745 if (status & DCSR_BUSERR) {
746 dev_err(dev, "DMA Bus Error IRQ!\n");
750 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
751 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
757 * pcdev->active should not be NULL in DMA irq handler.
759 * But there is one corner case : if capture was stopped due to an
760 * overrun of channel 1, and at that same channel 2 was completed.
762 * When handling the overrun in DMA irq for channel 1, we'll stop the
763 * capture and restart it (and thus set pcdev->active to NULL). But the
764 * DMA irq handler will already be pending for channel 2. So on entering
765 * the DMA irq handler for channel 2 there will be no active buffer, yet
771 vb = &pcdev->active->vb;
772 buf = container_of(vb, struct pxa_buffer, vb);
773 WARN_ON(buf->inwork || list_empty(&vb->queue));
775 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
776 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
777 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
779 if (status & DCSR_ENDINTR) {
781 * It's normal if the last frame creates an overrun, as there
782 * are no more DMA descriptors to fetch from QCI fifos
784 if (camera_status & overrun &&
785 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
786 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
788 pxa_camera_stop_capture(pcdev);
789 pxa_camera_start_capture(pcdev);
792 buf->active_dma &= ~act_dma;
793 if (!buf->active_dma) {
794 pxa_camera_wakeup(pcdev, vb, buf);
795 pxa_camera_check_link_miss(pcdev);
800 spin_unlock_irqrestore(&pcdev->lock, flags);
803 static void pxa_camera_dma_irq_y(int channel, void *data)
805 struct pxa_camera_dev *pcdev = data;
806 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
809 static void pxa_camera_dma_irq_u(int channel, void *data)
811 struct pxa_camera_dev *pcdev = data;
812 pxa_camera_dma_irq(channel, pcdev, DMA_U);
815 static void pxa_camera_dma_irq_v(int channel, void *data)
817 struct pxa_camera_dev *pcdev = data;
818 pxa_camera_dma_irq(channel, pcdev, DMA_V);
821 static struct videobuf_queue_ops pxa_videobuf_ops = {
822 .buf_setup = pxa_videobuf_setup,
823 .buf_prepare = pxa_videobuf_prepare,
824 .buf_queue = pxa_videobuf_queue,
825 .buf_release = pxa_videobuf_release,
828 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
829 struct soc_camera_device *icd)
831 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
832 struct pxa_camera_dev *pcdev = ici->priv;
835 * We must pass NULL as dev pointer, then all pci_* dma operations
836 * transform to normal dma_* ones.
838 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
839 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
840 sizeof(struct pxa_buffer), icd, &ici->host_lock);
843 static u32 mclk_get_divisor(struct platform_device *pdev,
844 struct pxa_camera_dev *pcdev)
846 unsigned long mclk = pcdev->mclk;
847 struct device *dev = &pdev->dev;
849 unsigned long lcdclk;
851 lcdclk = clk_get_rate(pcdev->clk);
852 pcdev->ciclk = lcdclk;
854 /* mclk <= ciclk / 4 (27.4.2) */
855 if (mclk > lcdclk / 4) {
857 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
860 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
861 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
863 /* If we're not supplying MCLK, leave it at 0 */
864 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
865 pcdev->mclk = lcdclk / (2 * (div + 1));
867 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
873 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
876 /* We want a timeout > 1 pixel time, not ">=" */
877 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
879 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
882 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
886 /* disable all interrupts */
887 __raw_writel(0x3ff, pcdev->base + CICR0);
889 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
890 cicr4 |= CICR4_PCLK_EN;
891 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
892 cicr4 |= CICR4_MCLK_EN;
893 if (pcdev->platform_flags & PXA_CAMERA_PCP)
895 if (pcdev->platform_flags & PXA_CAMERA_HSP)
897 if (pcdev->platform_flags & PXA_CAMERA_VSP)
900 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
902 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
903 /* Initialise the timeout under the assumption pclk = mclk */
904 recalculate_fifo_timeout(pcdev, pcdev->mclk);
906 /* "Safe default" - 13MHz */
907 recalculate_fifo_timeout(pcdev, 13000000);
909 clk_prepare_enable(pcdev->clk);
912 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
914 clk_disable_unprepare(pcdev->clk);
917 static irqreturn_t pxa_camera_irq(int irq, void *data)
919 struct pxa_camera_dev *pcdev = data;
920 unsigned long status, cifr, cicr0;
921 struct pxa_buffer *buf;
922 struct videobuf_buffer *vb;
924 status = __raw_readl(pcdev->base + CISR);
925 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
926 "Camera interrupt status 0x%lx\n", status);
931 __raw_writel(status, pcdev->base + CISR);
933 if (status & CISR_EOF) {
934 /* Reset the FIFOs */
935 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
936 __raw_writel(cifr, pcdev->base + CIFR);
938 pcdev->active = list_first_entry(&pcdev->capture,
939 struct pxa_buffer, vb.queue);
940 vb = &pcdev->active->vb;
941 buf = container_of(vb, struct pxa_buffer, vb);
942 pxa_videobuf_set_actdma(pcdev, buf);
944 pxa_dma_start_channels(pcdev);
946 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
947 __raw_writel(cicr0, pcdev->base + CICR0);
953 static int pxa_camera_add_device(struct soc_camera_device *icd)
955 dev_info(icd->parent, "PXA Camera driver attached to camera %d\n",
961 static void pxa_camera_remove_device(struct soc_camera_device *icd)
963 dev_info(icd->parent, "PXA Camera driver detached from camera %d\n",
968 * The following two functions absolutely depend on the fact, that
969 * there can be only one camera on PXA quick capture interface
970 * Called with .host_lock held
972 static int pxa_camera_clock_start(struct soc_camera_host *ici)
974 struct pxa_camera_dev *pcdev = ici->priv;
976 pxa_camera_activate(pcdev);
981 /* Called with .host_lock held */
982 static void pxa_camera_clock_stop(struct soc_camera_host *ici)
984 struct pxa_camera_dev *pcdev = ici->priv;
986 /* disable capture, disable interrupts */
987 __raw_writel(0x3ff, pcdev->base + CICR0);
989 /* Stop DMA engine */
990 DCSR(pcdev->dma_chans[0]) = 0;
991 DCSR(pcdev->dma_chans[1]) = 0;
992 DCSR(pcdev->dma_chans[2]) = 0;
994 pxa_camera_deactivate(pcdev);
997 static int test_platform_param(struct pxa_camera_dev *pcdev,
998 unsigned char buswidth, unsigned long *flags)
1001 * Platform specified synchronization and pixel clock polarities are
1002 * only a recommendation and are only used during probing. The PXA270
1003 * quick capture interface supports both.
1005 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1006 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
1007 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1008 V4L2_MBUS_HSYNC_ACTIVE_LOW |
1009 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
1010 V4L2_MBUS_VSYNC_ACTIVE_LOW |
1011 V4L2_MBUS_DATA_ACTIVE_HIGH |
1012 V4L2_MBUS_PCLK_SAMPLE_RISING |
1013 V4L2_MBUS_PCLK_SAMPLE_FALLING;
1015 /* If requested data width is supported by the platform, use it */
1016 if ((1 << (buswidth - 1)) & pcdev->width_flags)
1022 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1023 unsigned long flags, __u32 pixfmt)
1025 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1026 struct pxa_camera_dev *pcdev = ici->priv;
1027 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1028 unsigned long dw, bpp;
1029 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1030 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1036 * Datawidth is now guaranteed to be equal to one of the three values.
1037 * We fix bit-per-pixel equal to data-width...
1039 switch (icd->current_fmt->host_fmt->bits_per_sample) {
1050 * Actually it can only be 8 now,
1051 * default is just to silence compiler warnings
1058 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1059 cicr4 |= CICR4_PCLK_EN;
1060 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1061 cicr4 |= CICR4_MCLK_EN;
1062 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1064 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1066 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1069 cicr0 = __raw_readl(pcdev->base + CICR0);
1070 if (cicr0 & CICR0_ENB)
1071 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1073 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1076 case V4L2_PIX_FMT_YUV422P:
1077 pcdev->channels = 3;
1078 cicr1 |= CICR1_YCBCR_F;
1080 * Normally, pxa bus wants as input UYVY format. We allow all
1081 * reorderings of the YUV422 format, as no processing is done,
1082 * and the YUV stream is just passed through without any
1083 * transformation. Note that UYVY is the only format that
1084 * should be used if pxa framebuffer Overlay2 is used.
1086 case V4L2_PIX_FMT_UYVY:
1087 case V4L2_PIX_FMT_VYUY:
1088 case V4L2_PIX_FMT_YUYV:
1089 case V4L2_PIX_FMT_YVYU:
1090 cicr1 |= CICR1_COLOR_SP_VAL(2);
1092 case V4L2_PIX_FMT_RGB555:
1093 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1094 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1096 case V4L2_PIX_FMT_RGB565:
1097 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1102 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1103 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1104 cicr4 |= pcdev->mclk_divisor;
1106 __raw_writel(cicr1, pcdev->base + CICR1);
1107 __raw_writel(cicr2, pcdev->base + CICR2);
1108 __raw_writel(cicr3, pcdev->base + CICR3);
1109 __raw_writel(cicr4, pcdev->base + CICR4);
1111 /* CIF interrupts are not used, only DMA */
1112 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1113 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1114 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1115 __raw_writel(cicr0, pcdev->base + CICR0);
1118 static int pxa_camera_set_bus_param(struct soc_camera_device *icd)
1120 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1121 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1122 struct pxa_camera_dev *pcdev = ici->priv;
1123 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1124 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
1125 unsigned long bus_flags, common_flags;
1127 struct pxa_cam *cam = icd->host_priv;
1129 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1134 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1136 common_flags = soc_mbus_config_compatible(&cfg,
1138 if (!common_flags) {
1139 dev_warn(icd->parent,
1140 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1141 cfg.flags, bus_flags);
1144 } else if (ret != -ENOIOCTLCMD) {
1147 common_flags = bus_flags;
1150 pcdev->channels = 1;
1152 /* Make choises, based on platform preferences */
1153 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1154 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1155 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1156 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1158 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1161 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1162 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1163 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1164 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1166 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1169 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1170 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1171 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1172 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1174 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1177 cfg.flags = common_flags;
1178 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1179 if (ret < 0 && ret != -ENOIOCTLCMD) {
1180 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1185 cam->flags = common_flags;
1187 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1192 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1193 unsigned char buswidth)
1195 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1196 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1197 struct pxa_camera_dev *pcdev = ici->priv;
1198 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1199 unsigned long bus_flags, common_flags;
1200 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1205 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1207 common_flags = soc_mbus_config_compatible(&cfg,
1209 if (!common_flags) {
1210 dev_warn(icd->parent,
1211 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1212 cfg.flags, bus_flags);
1215 } else if (ret == -ENOIOCTLCMD) {
1222 static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1224 .fourcc = V4L2_PIX_FMT_YUV422P,
1225 .name = "Planar YUV422 16 bit",
1226 .bits_per_sample = 8,
1227 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1228 .order = SOC_MBUS_ORDER_LE,
1229 .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V,
1233 /* This will be corrected as we get more formats */
1234 static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1236 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1237 (fmt->bits_per_sample == 8 &&
1238 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1239 (fmt->bits_per_sample > 8 &&
1240 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1243 static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
1244 struct soc_camera_format_xlate *xlate)
1246 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1247 struct device *dev = icd->parent;
1248 int formats = 0, ret;
1249 struct pxa_cam *cam;
1250 struct v4l2_subdev_mbus_code_enum code = {
1251 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1254 const struct soc_mbus_pixelfmt *fmt;
1256 ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
1258 /* No more formats */
1261 fmt = soc_mbus_get_fmtdesc(code.code);
1263 dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code);
1267 /* This also checks support for the requested bits-per-sample */
1268 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1272 if (!icd->host_priv) {
1273 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1277 icd->host_priv = cam;
1279 cam = icd->host_priv;
1282 switch (code.code) {
1283 case MEDIA_BUS_FMT_UYVY8_2X8:
1286 xlate->host_fmt = &pxa_camera_formats[0];
1287 xlate->code = code.code;
1289 dev_dbg(dev, "Providing format %s using code %d\n",
1290 pxa_camera_formats[0].name, code.code);
1292 case MEDIA_BUS_FMT_VYUY8_2X8:
1293 case MEDIA_BUS_FMT_YUYV8_2X8:
1294 case MEDIA_BUS_FMT_YVYU8_2X8:
1295 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1296 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1298 dev_dbg(dev, "Providing format %s packed\n",
1302 if (!pxa_camera_packing_supported(fmt))
1306 "Providing format %s in pass-through mode\n",
1310 /* Generic pass-through */
1313 xlate->host_fmt = fmt;
1314 xlate->code = code.code;
1321 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1323 kfree(icd->host_priv);
1324 icd->host_priv = NULL;
1327 static int pxa_camera_check_frame(u32 width, u32 height)
1329 /* limit to pxa hardware capabilities */
1330 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1334 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1335 const struct v4l2_crop *a)
1337 const struct v4l2_rect *rect = &a->c;
1338 struct device *dev = icd->parent;
1339 struct soc_camera_host *ici = to_soc_camera_host(dev);
1340 struct pxa_camera_dev *pcdev = ici->priv;
1341 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1342 struct soc_camera_sense sense = {
1343 .master_clock = pcdev->mclk,
1344 .pixel_clock_max = pcdev->ciclk / 4,
1346 struct v4l2_subdev_format fmt = {
1347 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1349 struct v4l2_mbus_framefmt *mf = &fmt.format;
1350 struct pxa_cam *cam = icd->host_priv;
1351 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1354 /* If PCLK is used to latch data from the sensor, check sense */
1355 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1356 icd->sense = &sense;
1358 ret = v4l2_subdev_call(sd, video, s_crop, a);
1363 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1364 rect->width, rect->height, rect->left, rect->top);
1368 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
1372 if (pxa_camera_check_frame(mf->width, mf->height)) {
1374 * Camera cropping produced a frame beyond our capabilities.
1375 * FIXME: just extract a subframe, that we can process.
1377 v4l_bound_align_image(&mf->width, 48, 2048, 1,
1378 &mf->height, 32, 2048, 0,
1379 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1380 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt);
1384 if (pxa_camera_check_frame(mf->width, mf->height)) {
1385 dev_warn(icd->parent,
1386 "Inconsistent state. Use S_FMT to repair\n");
1391 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1392 if (sense.pixel_clock > sense.pixel_clock_max) {
1394 "pixel clock %lu set by the camera too high!",
1398 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1401 icd->user_width = mf->width;
1402 icd->user_height = mf->height;
1404 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1409 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1410 struct v4l2_format *f)
1412 struct device *dev = icd->parent;
1413 struct soc_camera_host *ici = to_soc_camera_host(dev);
1414 struct pxa_camera_dev *pcdev = ici->priv;
1415 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1416 const struct soc_camera_format_xlate *xlate = NULL;
1417 struct soc_camera_sense sense = {
1418 .master_clock = pcdev->mclk,
1419 .pixel_clock_max = pcdev->ciclk / 4,
1421 struct v4l2_pix_format *pix = &f->fmt.pix;
1422 struct v4l2_subdev_format format = {
1423 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1425 struct v4l2_mbus_framefmt *mf = &format.format;
1428 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1430 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1434 /* If PCLK is used to latch data from the sensor, check sense */
1435 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1436 /* The caller holds a mutex. */
1437 icd->sense = &sense;
1439 mf->width = pix->width;
1440 mf->height = pix->height;
1441 mf->field = pix->field;
1442 mf->colorspace = pix->colorspace;
1443 mf->code = xlate->code;
1445 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
1447 if (mf->code != xlate->code)
1453 dev_warn(dev, "Failed to configure for format %x\n",
1455 } else if (pxa_camera_check_frame(mf->width, mf->height)) {
1457 "Camera driver produced an unsupported frame %dx%d\n",
1458 mf->width, mf->height);
1460 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1461 if (sense.pixel_clock > sense.pixel_clock_max) {
1463 "pixel clock %lu set by the camera too high!",
1467 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1473 pix->width = mf->width;
1474 pix->height = mf->height;
1475 pix->field = mf->field;
1476 pix->colorspace = mf->colorspace;
1477 icd->current_fmt = xlate;
1482 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1483 struct v4l2_format *f)
1485 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1486 const struct soc_camera_format_xlate *xlate;
1487 struct v4l2_pix_format *pix = &f->fmt.pix;
1488 struct v4l2_subdev_pad_config pad_cfg;
1489 struct v4l2_subdev_format format = {
1490 .which = V4L2_SUBDEV_FORMAT_TRY,
1492 struct v4l2_mbus_framefmt *mf = &format.format;
1493 __u32 pixfmt = pix->pixelformat;
1496 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1498 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1503 * Limit to pxa hardware capabilities. YUV422P planar format requires
1504 * images size to be a multiple of 16 bytes. If not, zeros will be
1505 * inserted between Y and U planes, and U and V planes, which violates
1506 * the YUV422P standard.
1508 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1509 &pix->height, 32, 2048, 0,
1510 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1512 /* limit to sensor capabilities */
1513 mf->width = pix->width;
1514 mf->height = pix->height;
1515 /* Only progressive video supported so far */
1516 mf->field = V4L2_FIELD_NONE;
1517 mf->colorspace = pix->colorspace;
1518 mf->code = xlate->code;
1520 ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format);
1524 pix->width = mf->width;
1525 pix->height = mf->height;
1526 pix->colorspace = mf->colorspace;
1528 switch (mf->field) {
1529 case V4L2_FIELD_ANY:
1530 case V4L2_FIELD_NONE:
1531 pix->field = V4L2_FIELD_NONE;
1534 /* TODO: support interlaced at least in pass-through mode */
1535 dev_err(icd->parent, "Field type %d unsupported.\n",
1543 static int pxa_camera_reqbufs(struct soc_camera_device *icd,
1544 struct v4l2_requestbuffers *p)
1549 * This is for locking debugging only. I removed spinlocks and now I
1550 * check whether .prepare is ever called on a linked buffer, or whether
1551 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1552 * it hadn't triggered
1554 for (i = 0; i < p->count; i++) {
1555 struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1556 struct pxa_buffer, vb);
1558 INIT_LIST_HEAD(&buf->vb.queue);
1564 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1566 struct soc_camera_device *icd = file->private_data;
1567 struct pxa_buffer *buf;
1569 buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer,
1572 poll_wait(file, &buf->vb.done, pt);
1574 if (buf->vb.state == VIDEOBUF_DONE ||
1575 buf->vb.state == VIDEOBUF_ERROR)
1576 return POLLIN|POLLRDNORM;
1581 static int pxa_camera_querycap(struct soc_camera_host *ici,
1582 struct v4l2_capability *cap)
1584 /* cap->name is set by the firendly caller:-> */
1585 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1586 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1587 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1592 static int pxa_camera_suspend(struct device *dev)
1594 struct soc_camera_host *ici = to_soc_camera_host(dev);
1595 struct pxa_camera_dev *pcdev = ici->priv;
1598 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1599 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1600 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1601 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1602 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1604 if (pcdev->soc_host.icd) {
1605 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1606 ret = v4l2_subdev_call(sd, core, s_power, 0);
1607 if (ret == -ENOIOCTLCMD)
1614 static int pxa_camera_resume(struct device *dev)
1616 struct soc_camera_host *ici = to_soc_camera_host(dev);
1617 struct pxa_camera_dev *pcdev = ici->priv;
1620 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1621 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1622 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1624 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1625 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1626 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1627 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1628 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1630 if (pcdev->soc_host.icd) {
1631 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1632 ret = v4l2_subdev_call(sd, core, s_power, 1);
1633 if (ret == -ENOIOCTLCMD)
1637 /* Restart frame capture if active buffer exists */
1638 if (!ret && pcdev->active)
1639 pxa_camera_start_capture(pcdev);
1644 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1645 .owner = THIS_MODULE,
1646 .add = pxa_camera_add_device,
1647 .remove = pxa_camera_remove_device,
1648 .clock_start = pxa_camera_clock_start,
1649 .clock_stop = pxa_camera_clock_stop,
1650 .set_crop = pxa_camera_set_crop,
1651 .get_formats = pxa_camera_get_formats,
1652 .put_formats = pxa_camera_put_formats,
1653 .set_fmt = pxa_camera_set_fmt,
1654 .try_fmt = pxa_camera_try_fmt,
1655 .init_videobuf = pxa_camera_init_videobuf,
1656 .reqbufs = pxa_camera_reqbufs,
1657 .poll = pxa_camera_poll,
1658 .querycap = pxa_camera_querycap,
1659 .set_bus_param = pxa_camera_set_bus_param,
1662 static int pxa_camera_pdata_from_dt(struct device *dev,
1663 struct pxa_camera_dev *pcdev)
1666 struct device_node *np = dev->of_node;
1667 struct v4l2_of_endpoint ep;
1668 int err = of_property_read_u32(np, "clock-frequency",
1671 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
1672 pcdev->mclk = mclk_rate;
1675 np = of_graph_get_next_endpoint(np, NULL);
1677 dev_err(dev, "could not find endpoint\n");
1681 err = v4l2_of_parse_endpoint(np, &ep);
1683 dev_err(dev, "could not parse endpoint\n");
1687 switch (ep.bus.parallel.bus_width) {
1689 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
1692 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
1695 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
1698 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
1701 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1707 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
1708 pcdev->platform_flags |= PXA_CAMERA_MASTER;
1709 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1710 pcdev->platform_flags |= PXA_CAMERA_HSP;
1711 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1712 pcdev->platform_flags |= PXA_CAMERA_VSP;
1713 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1714 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
1715 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1716 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
1724 static int pxa_camera_probe(struct platform_device *pdev)
1726 struct pxa_camera_dev *pcdev;
1727 struct resource *res;
1732 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1733 irq = platform_get_irq(pdev, 0);
1734 if (!res || irq < 0)
1737 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1739 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1743 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
1744 if (IS_ERR(pcdev->clk))
1745 return PTR_ERR(pcdev->clk);
1749 pcdev->pdata = pdev->dev.platform_data;
1750 if (&pdev->dev.of_node && !pcdev->pdata) {
1751 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
1753 pcdev->platform_flags = pcdev->pdata->flags;
1754 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1759 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1760 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1762 * Platform hasn't set available data widths. This is bad.
1763 * Warn and use a default.
1765 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1766 "data widths, using default 10 bit\n");
1767 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1769 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1770 pcdev->width_flags = 1 << 7;
1771 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1772 pcdev->width_flags |= 1 << 8;
1773 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1774 pcdev->width_flags |= 1 << 9;
1776 dev_warn(&pdev->dev,
1777 "mclk == 0! Please, fix your platform data. "
1778 "Using default 20MHz\n");
1779 pcdev->mclk = 20000000;
1782 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1784 INIT_LIST_HEAD(&pcdev->capture);
1785 spin_lock_init(&pcdev->lock);
1788 * Request the regions.
1790 base = devm_ioremap_resource(&pdev->dev, res);
1792 return PTR_ERR(base);
1798 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1799 pxa_camera_dma_irq_y, pcdev);
1801 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1804 pcdev->dma_chans[0] = err;
1805 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1807 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1808 pxa_camera_dma_irq_u, pcdev);
1810 dev_err(&pdev->dev, "Can't request DMA for U\n");
1811 goto exit_free_dma_y;
1813 pcdev->dma_chans[1] = err;
1814 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1816 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1817 pxa_camera_dma_irq_v, pcdev);
1819 dev_err(&pdev->dev, "Can't request DMA for V\n");
1820 goto exit_free_dma_u;
1822 pcdev->dma_chans[2] = err;
1823 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1825 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1826 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1827 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1830 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
1831 PXA_CAM_DRV_NAME, pcdev);
1833 dev_err(&pdev->dev, "Camera interrupt register failed\n");
1837 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1838 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1839 pcdev->soc_host.priv = pcdev;
1840 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1841 pcdev->soc_host.nr = pdev->id;
1843 err = soc_camera_host_register(&pcdev->soc_host);
1850 pxa_free_dma(pcdev->dma_chans[2]);
1852 pxa_free_dma(pcdev->dma_chans[1]);
1854 pxa_free_dma(pcdev->dma_chans[0]);
1858 static int pxa_camera_remove(struct platform_device *pdev)
1860 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1861 struct pxa_camera_dev *pcdev = container_of(soc_host,
1862 struct pxa_camera_dev, soc_host);
1864 pxa_free_dma(pcdev->dma_chans[0]);
1865 pxa_free_dma(pcdev->dma_chans[1]);
1866 pxa_free_dma(pcdev->dma_chans[2]);
1868 soc_camera_host_unregister(soc_host);
1870 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1875 static const struct dev_pm_ops pxa_camera_pm = {
1876 .suspend = pxa_camera_suspend,
1877 .resume = pxa_camera_resume,
1880 static const struct of_device_id pxa_camera_of_match[] = {
1881 { .compatible = "marvell,pxa270-qci", },
1884 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
1886 static struct platform_driver pxa_camera_driver = {
1888 .name = PXA_CAM_DRV_NAME,
1889 .pm = &pxa_camera_pm,
1890 .of_match_table = of_match_ptr(pxa_camera_of_match),
1892 .probe = pxa_camera_probe,
1893 .remove = pxa_camera_remove,
1896 module_platform_driver(pxa_camera_driver);
1898 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1899 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1900 MODULE_LICENSE("GPL");
1901 MODULE_VERSION(PXA_CAM_VERSION);
1902 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);