2 * V4L2 Driver for PXA camera host
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/init.h>
14 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dma/pxa-dma.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-dev.h>
37 #include <media/videobuf2-dma-sg.h>
38 #include <media/soc_camera.h>
39 #include <media/drv-intf/soc_mediabus.h>
40 #include <media/v4l2-of.h>
42 #include <linux/videodev2.h>
44 #include <linux/platform_data/media/camera-pxa.h>
46 #define PXA_CAM_VERSION "0.0.6"
47 #define PXA_CAM_DRV_NAME "pxa27x-camera"
49 /* Camera Interface */
62 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
63 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
64 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
65 #define CICR0_ENB (1 << 28) /* Camera interface enable */
66 #define CICR0_DIS (1 << 27) /* Camera interface disable */
67 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
68 #define CICR0_TOM (1 << 9) /* Time-out mask */
69 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
70 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
71 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
72 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
73 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
74 #define CICR0_CDM (1 << 3) /* Disable-done mask */
75 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
76 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
77 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
79 #define CICR1_TBIT (1 << 31) /* Transparency bit */
80 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
81 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
82 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
83 #define CICR1_RGB_F (1 << 11) /* RGB format */
84 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
85 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
86 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
87 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
88 #define CICR1_DW (0x7 << 0) /* Data width mask */
90 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
92 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
94 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
95 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
97 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
100 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
102 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
104 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
105 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
107 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
109 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
110 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
111 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
112 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
113 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
114 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
115 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
116 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
118 #define CISR_FTO (1 << 15) /* FIFO time-out */
119 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
120 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
121 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
122 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
123 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
124 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
125 #define CISR_EOL (1 << 8) /* End of line */
126 #define CISR_PAR_ERR (1 << 7) /* Parity error */
127 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
128 #define CISR_CDD (1 << 5) /* Camera interface disable done */
129 #define CISR_SOF (1 << 4) /* Start of frame */
130 #define CISR_EOF (1 << 3) /* End of frame */
131 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
132 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
133 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
135 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
136 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
137 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
138 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
139 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
140 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
141 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
142 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
144 #define CICR0_SIM_MP (0 << 24)
145 #define CICR0_SIM_SP (1 << 24)
146 #define CICR0_SIM_MS (2 << 24)
147 #define CICR0_SIM_EP (3 << 24)
148 #define CICR0_SIM_ES (4 << 24)
150 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
151 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
152 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
153 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
154 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
156 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
157 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
158 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
159 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
160 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
162 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
163 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
164 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
165 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
167 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
168 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
169 CICR0_EOFM | CICR0_FOM)
171 #define sensor_call(cam, o, f, args...) \
172 v4l2_subdev_call(sd, o, f, ##args)
177 enum pxa_camera_active_dma {
183 /* buffer for one video frame */
185 /* common v4l buffer stuff -- must be first */
186 struct vb2_v4l2_buffer vbuf;
187 struct list_head queue;
190 /* our descriptor lists for Y, U and V channels */
191 struct dma_async_tx_descriptor *descs[3];
192 dma_cookie_t cookie[3];
193 struct scatterlist *sg[3];
195 size_t plane_sizes[3];
197 enum pxa_camera_active_dma active_dma;
200 struct pxa_camera_dev {
201 struct soc_camera_host soc_host;
203 * PXA27x is only supposed to handle one camera on its Quick Capture
204 * interface. If anyone ever builds hardware to enable more than
205 * one camera, they will have to modify this driver too
213 struct dma_chan *dma_chans[3];
215 struct pxacamera_platform_data *pdata;
216 struct resource *res;
217 unsigned long platform_flags;
221 u16 width_flags; /* max 10 bits */
223 struct list_head capture;
226 unsigned int buf_sequence;
228 struct pxa_buffer *active;
229 struct tasklet_struct task_eof;
238 static const char *pxa_cam_driver_description = "PXA_Camera";
240 static struct pxa_camera_dev *icd_to_pcdev(struct soc_camera_device *icd)
242 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
243 struct pxa_camera_dev *pcdev = ici->priv;
249 * Videobuf operations
251 static struct pxa_buffer *vb2_to_pxa_buffer(struct vb2_buffer *vb)
253 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
255 return container_of(vbuf, struct pxa_buffer, vbuf);
258 static struct device *pcdev_to_dev(struct pxa_camera_dev *pcdev)
260 return pcdev->soc_host.v4l2_dev.dev;
263 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
264 enum pxa_camera_active_dma act_dma);
266 static void pxa_camera_dma_irq_y(void *data)
268 struct pxa_camera_dev *pcdev = data;
270 pxa_camera_dma_irq(pcdev, DMA_Y);
273 static void pxa_camera_dma_irq_u(void *data)
275 struct pxa_camera_dev *pcdev = data;
277 pxa_camera_dma_irq(pcdev, DMA_U);
280 static void pxa_camera_dma_irq_v(void *data)
282 struct pxa_camera_dev *pcdev = data;
284 pxa_camera_dma_irq(pcdev, DMA_V);
288 * pxa_init_dma_channel - init dma descriptors
289 * @pcdev: pxa camera device
290 * @vb: videobuffer2 buffer
291 * @dma: dma video buffer
292 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
293 * @cibr: camera Receive Buffer Register
295 * Prepares the pxa dma descriptors to transfer one camera channel.
297 * Returns 0 if success or -ENOMEM if no memory is available
299 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
300 struct pxa_buffer *buf, int channel,
301 struct scatterlist *sg, int sglen)
303 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
304 struct dma_async_tx_descriptor *tx;
306 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
307 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
309 dev_err(pcdev_to_dev(pcdev),
310 "dmaengine_prep_slave_sg failed\n");
314 tx->callback_param = pcdev;
317 tx->callback = pxa_camera_dma_irq_y;
320 tx->callback = pxa_camera_dma_irq_u;
323 tx->callback = pxa_camera_dma_irq_v;
327 buf->descs[channel] = tx;
330 dev_dbg(pcdev_to_dev(pcdev),
331 "%s (vb=%p) dma_tx=%p\n",
337 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
338 struct pxa_buffer *buf)
340 buf->active_dma = DMA_Y;
341 if (pcdev->channels == 3)
342 buf->active_dma |= DMA_U | DMA_V;
346 * pxa_dma_start_channels - start DMA channel for active buffer
347 * @pcdev: pxa camera device
349 * Initialize DMA channels to the beginning of the active video buffer, and
350 * start these channels.
352 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
355 struct pxa_buffer *active;
357 active = pcdev->active;
359 for (i = 0; i < pcdev->channels; i++) {
360 dev_dbg(pcdev_to_dev(pcdev),
361 "%s (channel=%d)\n", __func__, i);
362 dma_async_issue_pending(pcdev->dma_chans[i]);
366 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
370 for (i = 0; i < pcdev->channels; i++) {
371 dev_dbg(pcdev_to_dev(pcdev),
372 "%s (channel=%d)\n", __func__, i);
373 dmaengine_terminate_all(pcdev->dma_chans[i]);
377 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
378 struct pxa_buffer *buf)
382 for (i = 0; i < pcdev->channels; i++) {
383 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
384 dev_dbg(pcdev_to_dev(pcdev),
385 "%s (channel=%d) : submit vb=%p cookie=%d\n",
386 __func__, i, buf, buf->descs[i]->cookie);
391 * pxa_camera_start_capture - start video capturing
392 * @pcdev: camera device
394 * Launch capturing. DMA channels should not be active yet. They should get
395 * activated at the end of frame interrupt, to capture only whole frames, and
396 * never begin the capture of a partial frame.
398 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
402 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
403 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
404 /* Enable End-Of-Frame Interrupt */
405 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
406 cicr0 &= ~CICR0_EOFM;
407 __raw_writel(cicr0, pcdev->base + CICR0);
410 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
414 pxa_dma_stop_channels(pcdev);
416 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
417 __raw_writel(cicr0, pcdev->base + CICR0);
419 pcdev->active = NULL;
420 dev_dbg(pcdev_to_dev(pcdev), "%s\n", __func__);
423 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
424 struct pxa_buffer *buf)
426 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
427 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
429 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
430 list_del_init(&buf->queue);
431 vb->timestamp = ktime_get_ns();
432 vbuf->sequence = pcdev->buf_sequence++;
433 vbuf->field = V4L2_FIELD_NONE;
434 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
435 dev_dbg(pcdev_to_dev(pcdev), "%s dequeud buffer (buf=0x%p)\n",
438 if (list_empty(&pcdev->capture)) {
439 pxa_camera_stop_capture(pcdev);
443 pcdev->active = list_entry(pcdev->capture.next,
444 struct pxa_buffer, queue);
448 * pxa_camera_check_link_miss - check missed DMA linking
449 * @pcdev: camera device
451 * The DMA chaining is done with DMA running. This means a tiny temporal window
452 * remains, where a buffer is queued on the chain, while the chain is already
453 * stopped. This means the tailed buffer would never be transferred by DMA.
454 * This function restarts the capture for this corner case, where :
455 * - DADR() == DADDR_STOP
456 * - a videobuffer is queued on the pcdev->capture list
458 * Please check the "DMA hot chaining timeslice issue" in
459 * Documentation/video4linux/pxa_camera.txt
461 * Context: should only be called within the dma irq handler
463 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
464 dma_cookie_t last_submitted,
465 dma_cookie_t last_issued)
467 bool is_dma_stopped = last_submitted != last_issued;
469 dev_dbg(pcdev_to_dev(pcdev),
470 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
471 __func__, pcdev->active, is_dma_stopped);
473 if (pcdev->active && is_dma_stopped)
474 pxa_camera_start_capture(pcdev);
477 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
478 enum pxa_camera_active_dma act_dma)
480 struct pxa_buffer *buf, *last_buf;
482 u32 camera_status, overrun;
484 enum dma_status last_status;
485 dma_cookie_t last_issued;
487 spin_lock_irqsave(&pcdev->lock, flags);
489 camera_status = __raw_readl(pcdev->base + CISR);
490 dev_dbg(pcdev_to_dev(pcdev), "camera dma irq, cisr=0x%x dma=%d\n",
491 camera_status, act_dma);
492 overrun = CISR_IFO_0;
493 if (pcdev->channels == 3)
494 overrun |= CISR_IFO_1 | CISR_IFO_2;
497 * pcdev->active should not be NULL in DMA irq handler.
499 * But there is one corner case : if capture was stopped due to an
500 * overrun of channel 1, and at that same channel 2 was completed.
502 * When handling the overrun in DMA irq for channel 1, we'll stop the
503 * capture and restart it (and thus set pcdev->active to NULL). But the
504 * DMA irq handler will already be pending for channel 2. So on entering
505 * the DMA irq handler for channel 2 there will be no active buffer, yet
512 WARN_ON(buf->inwork || list_empty(&buf->queue));
515 * It's normal if the last frame creates an overrun, as there
516 * are no more DMA descriptors to fetch from QCI fifos
529 last_buf = list_entry(pcdev->capture.prev,
530 struct pxa_buffer, queue);
531 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
532 last_buf->cookie[chan],
534 if (camera_status & overrun &&
535 last_status != DMA_COMPLETE) {
536 dev_dbg(pcdev_to_dev(pcdev), "FIFO overrun! CISR: %x\n",
538 pxa_camera_stop_capture(pcdev);
539 list_for_each_entry(buf, &pcdev->capture, queue)
540 pxa_dma_add_tail_buf(pcdev, buf);
541 pxa_camera_start_capture(pcdev);
544 buf->active_dma &= ~act_dma;
545 if (!buf->active_dma) {
546 pxa_camera_wakeup(pcdev, buf);
547 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
552 spin_unlock_irqrestore(&pcdev->lock, flags);
555 static u32 mclk_get_divisor(struct platform_device *pdev,
556 struct pxa_camera_dev *pcdev)
558 unsigned long mclk = pcdev->mclk;
560 unsigned long lcdclk;
562 lcdclk = clk_get_rate(pcdev->clk);
563 pcdev->ciclk = lcdclk;
565 /* mclk <= ciclk / 4 (27.4.2) */
566 if (mclk > lcdclk / 4) {
568 dev_warn(pcdev_to_dev(pcdev),
569 "Limiting master clock to %lu\n", mclk);
572 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
573 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
575 /* If we're not supplying MCLK, leave it at 0 */
576 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
577 pcdev->mclk = lcdclk / (2 * (div + 1));
579 dev_dbg(pcdev_to_dev(pcdev), "LCD clock %luHz, target freq %luHz, divisor %u\n",
585 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
588 /* We want a timeout > 1 pixel time, not ">=" */
589 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
591 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
594 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
598 /* disable all interrupts */
599 __raw_writel(0x3ff, pcdev->base + CICR0);
601 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
602 cicr4 |= CICR4_PCLK_EN;
603 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
604 cicr4 |= CICR4_MCLK_EN;
605 if (pcdev->platform_flags & PXA_CAMERA_PCP)
607 if (pcdev->platform_flags & PXA_CAMERA_HSP)
609 if (pcdev->platform_flags & PXA_CAMERA_VSP)
612 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
614 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
615 /* Initialise the timeout under the assumption pclk = mclk */
616 recalculate_fifo_timeout(pcdev, pcdev->mclk);
618 /* "Safe default" - 13MHz */
619 recalculate_fifo_timeout(pcdev, 13000000);
621 clk_prepare_enable(pcdev->clk);
624 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
626 clk_disable_unprepare(pcdev->clk);
629 static void pxa_camera_eof(unsigned long arg)
631 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
633 struct pxa_buffer *buf;
635 dev_dbg(pcdev_to_dev(pcdev),
636 "Camera interrupt status 0x%x\n",
637 __raw_readl(pcdev->base + CISR));
639 /* Reset the FIFOs */
640 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
641 __raw_writel(cifr, pcdev->base + CIFR);
643 pcdev->active = list_first_entry(&pcdev->capture,
644 struct pxa_buffer, queue);
646 pxa_videobuf_set_actdma(pcdev, buf);
648 pxa_dma_start_channels(pcdev);
651 static irqreturn_t pxa_camera_irq(int irq, void *data)
653 struct pxa_camera_dev *pcdev = data;
654 unsigned long status, cicr0;
656 status = __raw_readl(pcdev->base + CISR);
657 dev_dbg(pcdev_to_dev(pcdev),
658 "Camera interrupt status 0x%lx\n", status);
663 __raw_writel(status, pcdev->base + CISR);
665 if (status & CISR_EOF) {
666 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
667 __raw_writel(cicr0, pcdev->base + CICR0);
668 tasklet_schedule(&pcdev->task_eof);
674 static int pxa_camera_add_device(struct soc_camera_device *icd)
676 struct pxa_camera_dev *pcdev = icd_to_pcdev(icd);
678 dev_info(pcdev_to_dev(pcdev), "PXA Camera driver attached to camera %d\n",
684 static void pxa_camera_remove_device(struct soc_camera_device *icd)
686 struct pxa_camera_dev *pcdev = icd_to_pcdev(icd);
688 dev_info(pcdev_to_dev(pcdev), "PXA Camera driver detached from camera %d\n",
693 * The following two functions absolutely depend on the fact, that
694 * there can be only one camera on PXA quick capture interface
695 * Called with .host_lock held
697 static int pxa_camera_clock_start(struct soc_camera_host *ici)
699 struct pxa_camera_dev *pcdev = ici->priv;
701 pxa_camera_activate(pcdev);
706 /* Called with .host_lock held */
707 static void pxa_camera_clock_stop(struct soc_camera_host *ici)
709 struct pxa_camera_dev *pcdev = ici->priv;
711 /* disable capture, disable interrupts */
712 __raw_writel(0x3ff, pcdev->base + CICR0);
714 /* Stop DMA engine */
715 pxa_dma_stop_channels(pcdev);
716 pxa_camera_deactivate(pcdev);
719 static int test_platform_param(struct pxa_camera_dev *pcdev,
720 unsigned char buswidth, unsigned long *flags)
723 * Platform specified synchronization and pixel clock polarities are
724 * only a recommendation and are only used during probing. The PXA270
725 * quick capture interface supports both.
727 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
728 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
729 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
730 V4L2_MBUS_HSYNC_ACTIVE_LOW |
731 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
732 V4L2_MBUS_VSYNC_ACTIVE_LOW |
733 V4L2_MBUS_DATA_ACTIVE_HIGH |
734 V4L2_MBUS_PCLK_SAMPLE_RISING |
735 V4L2_MBUS_PCLK_SAMPLE_FALLING;
737 /* If requested data width is supported by the platform, use it */
738 if ((1 << (buswidth - 1)) & pcdev->width_flags)
744 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
745 unsigned long flags, __u32 pixfmt)
747 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
748 struct pxa_camera_dev *pcdev = ici->priv;
749 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
750 unsigned long dw, bpp;
751 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
752 int ret = sensor_call(pcdev, sensor, g_skip_top_lines, &y_skip_top);
758 * Datawidth is now guaranteed to be equal to one of the three values.
759 * We fix bit-per-pixel equal to data-width...
761 switch (icd->current_fmt->host_fmt->bits_per_sample) {
772 * Actually it can only be 8 now,
773 * default is just to silence compiler warnings
780 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
781 cicr4 |= CICR4_PCLK_EN;
782 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
783 cicr4 |= CICR4_MCLK_EN;
784 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
786 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
788 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
791 cicr0 = __raw_readl(pcdev->base + CICR0);
792 if (cicr0 & CICR0_ENB)
793 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
795 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
798 case V4L2_PIX_FMT_YUV422P:
800 cicr1 |= CICR1_YCBCR_F;
802 * Normally, pxa bus wants as input UYVY format. We allow all
803 * reorderings of the YUV422 format, as no processing is done,
804 * and the YUV stream is just passed through without any
805 * transformation. Note that UYVY is the only format that
806 * should be used if pxa framebuffer Overlay2 is used.
808 case V4L2_PIX_FMT_UYVY:
809 case V4L2_PIX_FMT_VYUY:
810 case V4L2_PIX_FMT_YUYV:
811 case V4L2_PIX_FMT_YVYU:
812 cicr1 |= CICR1_COLOR_SP_VAL(2);
814 case V4L2_PIX_FMT_RGB555:
815 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
816 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
818 case V4L2_PIX_FMT_RGB565:
819 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
824 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
825 CICR3_BFW_VAL(min((u32)255, y_skip_top));
826 cicr4 |= pcdev->mclk_divisor;
828 __raw_writel(cicr1, pcdev->base + CICR1);
829 __raw_writel(cicr2, pcdev->base + CICR2);
830 __raw_writel(cicr3, pcdev->base + CICR3);
831 __raw_writel(cicr4, pcdev->base + CICR4);
833 /* CIF interrupts are not used, only DMA */
834 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
835 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
836 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
837 __raw_writel(cicr0, pcdev->base + CICR0);
843 static void pxa_buffer_cleanup(struct pxa_buffer *buf)
847 for (i = 0; i < 3 && buf->descs[i]; i++) {
848 dmaengine_desc_free(buf->descs[i]);
850 buf->descs[i] = NULL;
853 buf->plane_sizes[i] = 0;
858 static int pxa_buffer_init(struct pxa_camera_dev *pcdev,
859 struct pxa_buffer *buf)
861 struct vb2_buffer *vb = &buf->vbuf.vb2_buf;
862 struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, 0);
863 int nb_channels = pcdev->channels;
865 unsigned long size = vb2_plane_size(vb, 0);
867 switch (nb_channels) {
869 buf->plane_sizes[0] = size;
872 buf->plane_sizes[0] = size / 2;
873 buf->plane_sizes[1] = size / 4;
874 buf->plane_sizes[2] = size / 4;
879 buf->nb_planes = nb_channels;
881 ret = sg_split(sgt->sgl, sgt->nents, 0, nb_channels,
882 buf->plane_sizes, buf->sg, buf->sg_len, GFP_KERNEL);
884 dev_err(pcdev_to_dev(pcdev),
885 "sg_split failed: %d\n", ret);
888 for (i = 0; i < nb_channels; i++) {
889 ret = pxa_init_dma_channel(pcdev, buf, i,
890 buf->sg[i], buf->sg_len[i]);
892 pxa_buffer_cleanup(buf);
896 INIT_LIST_HEAD(&buf->queue);
901 static void pxac_vb2_cleanup(struct vb2_buffer *vb)
903 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
904 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
906 dev_dbg(pcdev_to_dev(pcdev),
907 "%s(vb=%p)\n", __func__, vb);
908 pxa_buffer_cleanup(buf);
911 static void pxac_vb2_queue(struct vb2_buffer *vb)
913 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
914 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
916 dev_dbg(pcdev_to_dev(pcdev),
917 "%s(vb=%p) nb_channels=%d size=%lu active=%p\n",
918 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0),
921 list_add_tail(&buf->queue, &pcdev->capture);
923 pxa_dma_add_tail_buf(pcdev, buf);
927 * Please check the DMA prepared buffer structure in :
928 * Documentation/video4linux/pxa_camera.txt
929 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
930 * modification while DMA chain is running will work anyway.
932 static int pxac_vb2_prepare(struct vb2_buffer *vb)
934 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
935 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
936 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
939 switch (pcdev->channels) {
942 vb2_set_plane_payload(vb, 0, icd->sizeimage);
948 dev_dbg(pcdev_to_dev(pcdev),
949 "%s (vb=%p) nb_channels=%d size=%lu\n",
950 __func__, vb, pcdev->channels, vb2_get_plane_payload(vb, 0));
952 WARN_ON(!icd->current_fmt);
956 * This can be useful if you want to see if we actually fill
957 * the buffer with something
959 for (i = 0; i < vb->num_planes; i++)
960 memset((void *)vb2_plane_vaddr(vb, i),
961 0xaa, vb2_get_plane_payload(vb, i));
965 * I think, in buf_prepare you only have to protect global data,
966 * the actual buffer is yours
969 pxa_videobuf_set_actdma(pcdev, buf);
974 static int pxac_vb2_init(struct vb2_buffer *vb)
976 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vb->vb2_queue);
977 struct pxa_buffer *buf = vb2_to_pxa_buffer(vb);
979 dev_dbg(pcdev_to_dev(pcdev),
980 "%s(nb_channels=%d)\n",
981 __func__, pcdev->channels);
983 return pxa_buffer_init(pcdev, buf);
986 static int pxac_vb2_queue_setup(struct vb2_queue *vq,
988 unsigned int *num_planes, unsigned int sizes[],
989 struct device *alloc_devs[])
991 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
992 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
993 int size = icd->sizeimage;
995 dev_dbg(pcdev_to_dev(pcdev),
996 "%s(vq=%p nbufs=%d num_planes=%d size=%d)\n",
997 __func__, vq, *nbufs, *num_planes, size);
999 * Called from VIDIOC_REQBUFS or in compatibility mode For YUV422P
1000 * format, even if there are 3 planes Y, U and V, we reply there is only
1001 * one plane, containing Y, U and V data, one after the other.
1004 return sizes[0] < size ? -EINVAL : 0;
1007 switch (pcdev->channels) {
1022 static int pxac_vb2_start_streaming(struct vb2_queue *vq, unsigned int count)
1024 struct pxa_camera_dev *pcdev = vb2_get_drv_priv(vq);
1026 dev_dbg(pcdev_to_dev(pcdev), "%s(count=%d) active=%p\n",
1027 __func__, count, pcdev->active);
1029 pcdev->buf_sequence = 0;
1031 pxa_camera_start_capture(pcdev);
1036 static void pxac_vb2_stop_streaming(struct vb2_queue *vq)
1038 vb2_wait_for_all_buffers(vq);
1041 static struct vb2_ops pxac_vb2_ops = {
1042 .queue_setup = pxac_vb2_queue_setup,
1043 .buf_init = pxac_vb2_init,
1044 .buf_prepare = pxac_vb2_prepare,
1045 .buf_queue = pxac_vb2_queue,
1046 .buf_cleanup = pxac_vb2_cleanup,
1047 .start_streaming = pxac_vb2_start_streaming,
1048 .stop_streaming = pxac_vb2_stop_streaming,
1049 .wait_prepare = vb2_ops_wait_prepare,
1050 .wait_finish = vb2_ops_wait_finish,
1053 static int pxa_camera_init_videobuf2(struct vb2_queue *vq,
1054 struct soc_camera_device *icd)
1056 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1057 struct pxa_camera_dev *pcdev = ici->priv;
1060 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1061 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF;
1062 vq->drv_priv = pcdev;
1063 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1064 vq->buf_struct_size = sizeof(struct pxa_buffer);
1066 vq->ops = &pxac_vb2_ops;
1067 vq->mem_ops = &vb2_dma_sg_memops;
1069 ret = vb2_queue_init(vq);
1070 dev_dbg(pcdev_to_dev(pcdev),
1071 "vb2_queue_init(vq=%p): %d\n", vq, ret);
1077 * Video ioctls section
1079 static int pxa_camera_set_bus_param(struct soc_camera_device *icd)
1081 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1082 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1083 struct pxa_camera_dev *pcdev = ici->priv;
1084 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1085 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
1086 unsigned long bus_flags, common_flags;
1088 struct pxa_cam *cam = icd->host_priv;
1090 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1095 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1097 common_flags = soc_mbus_config_compatible(&cfg,
1099 if (!common_flags) {
1100 dev_warn(pcdev_to_dev(pcdev),
1101 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1102 cfg.flags, bus_flags);
1105 } else if (ret != -ENOIOCTLCMD) {
1108 common_flags = bus_flags;
1111 pcdev->channels = 1;
1113 /* Make choises, based on platform preferences */
1114 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1115 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1116 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1117 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1119 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1122 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1123 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1124 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1125 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1127 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1130 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1131 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1132 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1133 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1135 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1138 cfg.flags = common_flags;
1139 ret = sensor_call(pcdev, video, s_mbus_config, &cfg);
1140 if (ret < 0 && ret != -ENOIOCTLCMD) {
1141 dev_dbg(pcdev_to_dev(pcdev), "camera s_mbus_config(0x%lx) returned %d\n",
1146 cam->flags = common_flags;
1148 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1153 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1154 unsigned char buswidth)
1156 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1157 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1158 struct pxa_camera_dev *pcdev = ici->priv;
1159 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1160 unsigned long bus_flags, common_flags;
1161 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1166 ret = sensor_call(pcdev, video, g_mbus_config, &cfg);
1168 common_flags = soc_mbus_config_compatible(&cfg,
1170 if (!common_flags) {
1171 dev_warn(pcdev_to_dev(pcdev),
1172 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1173 cfg.flags, bus_flags);
1176 } else if (ret == -ENOIOCTLCMD) {
1183 static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1185 .fourcc = V4L2_PIX_FMT_YUV422P,
1186 .name = "Planar YUV422 16 bit",
1187 .bits_per_sample = 8,
1188 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1189 .order = SOC_MBUS_ORDER_LE,
1190 .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V,
1194 /* This will be corrected as we get more formats */
1195 static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1197 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1198 (fmt->bits_per_sample == 8 &&
1199 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1200 (fmt->bits_per_sample > 8 &&
1201 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1204 static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
1205 struct soc_camera_format_xlate *xlate)
1207 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1208 struct pxa_camera_dev *pcdev = icd_to_pcdev(icd);
1209 int formats = 0, ret;
1210 struct pxa_cam *cam;
1211 struct v4l2_subdev_mbus_code_enum code = {
1212 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1215 const struct soc_mbus_pixelfmt *fmt;
1217 ret = sensor_call(pcdev, pad, enum_mbus_code, NULL, &code);
1219 /* No more formats */
1222 fmt = soc_mbus_get_fmtdesc(code.code);
1224 dev_err(pcdev_to_dev(pcdev), "Invalid format code #%u: %d\n", idx, code.code);
1228 /* This also checks support for the requested bits-per-sample */
1229 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1233 if (!icd->host_priv) {
1234 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1238 icd->host_priv = cam;
1240 cam = icd->host_priv;
1243 switch (code.code) {
1244 case MEDIA_BUS_FMT_UYVY8_2X8:
1247 xlate->host_fmt = &pxa_camera_formats[0];
1248 xlate->code = code.code;
1250 dev_dbg(pcdev_to_dev(pcdev),
1251 "Providing format %s using code %d\n",
1252 pxa_camera_formats[0].name, code.code);
1254 case MEDIA_BUS_FMT_VYUY8_2X8:
1255 case MEDIA_BUS_FMT_YUYV8_2X8:
1256 case MEDIA_BUS_FMT_YVYU8_2X8:
1257 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1258 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1260 dev_dbg(pcdev_to_dev(pcdev),
1261 "Providing format %s packed\n",
1265 if (!pxa_camera_packing_supported(fmt))
1268 dev_dbg(pcdev_to_dev(pcdev),
1269 "Providing format %s in pass-through mode\n",
1273 /* Generic pass-through */
1276 xlate->host_fmt = fmt;
1277 xlate->code = code.code;
1284 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1286 kfree(icd->host_priv);
1287 icd->host_priv = NULL;
1290 static int pxa_camera_check_frame(u32 width, u32 height)
1292 /* limit to pxa hardware capabilities */
1293 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1297 static int pxa_camera_set_selection(struct soc_camera_device *icd,
1298 struct v4l2_selection *sel)
1300 const struct v4l2_rect *rect = &sel->r;
1301 struct device *dev = icd->parent;
1302 struct soc_camera_host *ici = to_soc_camera_host(dev);
1303 struct pxa_camera_dev *pcdev = ici->priv;
1304 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1305 struct soc_camera_sense sense = {
1306 .master_clock = pcdev->mclk,
1307 .pixel_clock_max = pcdev->ciclk / 4,
1309 struct v4l2_subdev_format fmt = {
1310 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1312 struct v4l2_mbus_framefmt *mf = &fmt.format;
1313 struct pxa_cam *cam = icd->host_priv;
1314 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1315 struct v4l2_subdev_selection sdsel = {
1316 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1317 .target = sel->target,
1318 .flags = sel->flags,
1323 /* If PCLK is used to latch data from the sensor, check sense */
1324 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1325 icd->sense = &sense;
1327 ret = sensor_call(pcdev, pad, set_selection, NULL, &sdsel);
1332 dev_warn(pcdev_to_dev(pcdev), "Failed to crop to %ux%u@%u:%u\n",
1333 rect->width, rect->height, rect->left, rect->top);
1338 ret = sensor_call(pcdev, pad, get_fmt, NULL, &fmt);
1342 if (pxa_camera_check_frame(mf->width, mf->height)) {
1344 * Camera cropping produced a frame beyond our capabilities.
1345 * FIXME: just extract a subframe, that we can process.
1347 v4l_bound_align_image(&mf->width, 48, 2048, 1,
1348 &mf->height, 32, 2048, 0,
1349 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1350 ret = sensor_call(pcdev, pad, set_fmt, NULL, &fmt);
1354 if (pxa_camera_check_frame(mf->width, mf->height)) {
1355 dev_warn(pcdev_to_dev(pcdev),
1356 "Inconsistent state. Use S_FMT to repair\n");
1361 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1362 if (sense.pixel_clock > sense.pixel_clock_max) {
1363 dev_err(pcdev_to_dev(pcdev),
1364 "pixel clock %lu set by the camera too high!",
1368 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1371 icd->user_width = mf->width;
1372 icd->user_height = mf->height;
1374 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1379 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1380 struct v4l2_format *f)
1382 struct device *dev = icd->parent;
1383 struct soc_camera_host *ici = to_soc_camera_host(dev);
1384 struct pxa_camera_dev *pcdev = ici->priv;
1385 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1386 const struct soc_camera_format_xlate *xlate = NULL;
1387 struct soc_camera_sense sense = {
1388 .master_clock = pcdev->mclk,
1389 .pixel_clock_max = pcdev->ciclk / 4,
1391 struct v4l2_pix_format *pix = &f->fmt.pix;
1392 struct v4l2_subdev_format format = {
1393 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1395 struct v4l2_mbus_framefmt *mf = &format.format;
1398 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1400 dev_warn(pcdev_to_dev(pcdev),
1401 "Format %x not found\n", pix->pixelformat);
1405 /* If PCLK is used to latch data from the sensor, check sense */
1406 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1407 /* The caller holds a mutex. */
1408 icd->sense = &sense;
1410 mf->width = pix->width;
1411 mf->height = pix->height;
1412 mf->field = pix->field;
1413 mf->colorspace = pix->colorspace;
1414 mf->code = xlate->code;
1416 ret = sensor_call(pcdev, pad, set_fmt, NULL, &format);
1418 if (mf->code != xlate->code)
1424 dev_warn(pcdev_to_dev(pcdev),
1425 "Failed to configure for format %x\n",
1427 } else if (pxa_camera_check_frame(mf->width, mf->height)) {
1428 dev_warn(pcdev_to_dev(pcdev),
1429 "Camera driver produced an unsupported frame %dx%d\n",
1430 mf->width, mf->height);
1432 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1433 if (sense.pixel_clock > sense.pixel_clock_max) {
1434 dev_err(pcdev_to_dev(pcdev),
1435 "pixel clock %lu set by the camera too high!",
1439 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1445 pix->width = mf->width;
1446 pix->height = mf->height;
1447 pix->field = mf->field;
1448 pix->colorspace = mf->colorspace;
1449 icd->current_fmt = xlate;
1454 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1455 struct v4l2_format *f)
1457 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1458 struct pxa_camera_dev *pcdev = icd_to_pcdev(icd);
1459 const struct soc_camera_format_xlate *xlate;
1460 struct v4l2_pix_format *pix = &f->fmt.pix;
1461 struct v4l2_subdev_pad_config pad_cfg;
1462 struct v4l2_subdev_format format = {
1463 .which = V4L2_SUBDEV_FORMAT_TRY,
1465 struct v4l2_mbus_framefmt *mf = &format.format;
1466 __u32 pixfmt = pix->pixelformat;
1469 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1471 dev_warn(pcdev_to_dev(pcdev), "Format %x not found\n", pixfmt);
1476 * Limit to pxa hardware capabilities. YUV422P planar format requires
1477 * images size to be a multiple of 16 bytes. If not, zeros will be
1478 * inserted between Y and U planes, and U and V planes, which violates
1479 * the YUV422P standard.
1481 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1482 &pix->height, 32, 2048, 0,
1483 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1485 /* limit to sensor capabilities */
1486 mf->width = pix->width;
1487 mf->height = pix->height;
1488 /* Only progressive video supported so far */
1489 mf->field = V4L2_FIELD_NONE;
1490 mf->colorspace = pix->colorspace;
1491 mf->code = xlate->code;
1493 ret = sensor_call(pcdev, pad, set_fmt, &pad_cfg, &format);
1497 pix->width = mf->width;
1498 pix->height = mf->height;
1499 pix->colorspace = mf->colorspace;
1501 switch (mf->field) {
1502 case V4L2_FIELD_ANY:
1503 case V4L2_FIELD_NONE:
1504 pix->field = V4L2_FIELD_NONE;
1507 /* TODO: support interlaced at least in pass-through mode */
1508 dev_err(pcdev_to_dev(pcdev), "Field type %d unsupported.\n",
1516 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1518 struct soc_camera_device *icd = file->private_data;
1520 return vb2_poll(&icd->vb2_vidq, file, pt);
1523 static int pxa_camera_querycap(struct soc_camera_host *ici,
1524 struct v4l2_capability *cap)
1526 /* cap->name is set by the firendly caller:-> */
1527 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1528 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1529 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1535 * Driver probe, remove, suspend and resume operations
1537 static int pxa_camera_suspend(struct device *dev)
1539 struct soc_camera_host *ici = to_soc_camera_host(dev);
1540 struct pxa_camera_dev *pcdev = ici->priv;
1543 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1544 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1545 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1546 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1547 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1549 if (pcdev->soc_host.icd) {
1550 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1551 ret = sensor_call(pcdev, core, s_power, 0);
1552 if (ret == -ENOIOCTLCMD)
1559 static int pxa_camera_resume(struct device *dev)
1561 struct soc_camera_host *ici = to_soc_camera_host(dev);
1562 struct pxa_camera_dev *pcdev = ici->priv;
1565 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1566 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1567 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1568 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1569 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1571 if (pcdev->soc_host.icd) {
1572 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1573 ret = sensor_call(pcdev, core, s_power, 1);
1574 if (ret == -ENOIOCTLCMD)
1578 /* Restart frame capture if active buffer exists */
1579 if (!ret && pcdev->active)
1580 pxa_camera_start_capture(pcdev);
1585 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1586 .owner = THIS_MODULE,
1587 .add = pxa_camera_add_device,
1588 .remove = pxa_camera_remove_device,
1589 .clock_start = pxa_camera_clock_start,
1590 .clock_stop = pxa_camera_clock_stop,
1591 .set_selection = pxa_camera_set_selection,
1592 .get_formats = pxa_camera_get_formats,
1593 .put_formats = pxa_camera_put_formats,
1594 .set_fmt = pxa_camera_set_fmt,
1595 .try_fmt = pxa_camera_try_fmt,
1596 .init_videobuf2 = pxa_camera_init_videobuf2,
1597 .poll = pxa_camera_poll,
1598 .querycap = pxa_camera_querycap,
1599 .set_bus_param = pxa_camera_set_bus_param,
1602 static int pxa_camera_pdata_from_dt(struct device *dev,
1603 struct pxa_camera_dev *pcdev)
1606 struct device_node *np = dev->of_node;
1607 struct v4l2_of_endpoint ep;
1608 int err = of_property_read_u32(np, "clock-frequency",
1611 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
1612 pcdev->mclk = mclk_rate;
1615 np = of_graph_get_next_endpoint(np, NULL);
1617 dev_err(pcdev_to_dev(pcdev), "could not find endpoint\n");
1621 err = v4l2_of_parse_endpoint(np, &ep);
1623 dev_err(pcdev_to_dev(pcdev), "could not parse endpoint\n");
1627 switch (ep.bus.parallel.bus_width) {
1629 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
1632 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
1635 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
1638 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
1641 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1647 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
1648 pcdev->platform_flags |= PXA_CAMERA_MASTER;
1649 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1650 pcdev->platform_flags |= PXA_CAMERA_HSP;
1651 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1652 pcdev->platform_flags |= PXA_CAMERA_VSP;
1653 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1654 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
1655 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1656 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
1664 static int pxa_camera_probe(struct platform_device *pdev)
1666 struct pxa_camera_dev *pcdev;
1667 struct resource *res;
1669 struct dma_slave_config config = {
1670 .src_addr_width = 0,
1672 .direction = DMA_DEV_TO_MEM,
1674 dma_cap_mask_t mask;
1675 struct pxad_param params;
1679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680 irq = platform_get_irq(pdev, 0);
1681 if (!res || irq < 0)
1684 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1686 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1690 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
1691 if (IS_ERR(pcdev->clk))
1692 return PTR_ERR(pcdev->clk);
1696 pcdev->pdata = pdev->dev.platform_data;
1697 if (&pdev->dev.of_node && !pcdev->pdata) {
1698 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
1700 pcdev->platform_flags = pcdev->pdata->flags;
1701 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1706 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1707 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1709 * Platform hasn't set available data widths. This is bad.
1710 * Warn and use a default.
1712 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1713 "data widths, using default 10 bit\n");
1714 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1716 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1717 pcdev->width_flags = 1 << 7;
1718 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1719 pcdev->width_flags |= 1 << 8;
1720 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1721 pcdev->width_flags |= 1 << 9;
1723 dev_warn(&pdev->dev,
1724 "mclk == 0! Please, fix your platform data. "
1725 "Using default 20MHz\n");
1726 pcdev->mclk = 20000000;
1729 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1731 INIT_LIST_HEAD(&pcdev->capture);
1732 spin_lock_init(&pcdev->lock);
1735 * Request the regions.
1737 base = devm_ioremap_resource(&pdev->dev, res);
1739 return PTR_ERR(base);
1746 dma_cap_set(DMA_SLAVE, mask);
1747 dma_cap_set(DMA_PRIVATE, mask);
1751 pcdev->dma_chans[0] =
1752 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1753 ¶ms, &pdev->dev, "CI_Y");
1754 if (!pcdev->dma_chans[0]) {
1755 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1760 pcdev->dma_chans[1] =
1761 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1762 ¶ms, &pdev->dev, "CI_U");
1763 if (!pcdev->dma_chans[1]) {
1764 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1765 goto exit_free_dma_y;
1769 pcdev->dma_chans[2] =
1770 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1771 ¶ms, &pdev->dev, "CI_V");
1772 if (!pcdev->dma_chans[2]) {
1773 dev_err(&pdev->dev, "Can't request DMA for V\n");
1774 goto exit_free_dma_u;
1777 for (i = 0; i < 3; i++) {
1778 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
1779 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
1781 dev_err(&pdev->dev, "dma slave config failed: %d\n",
1788 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
1789 PXA_CAM_DRV_NAME, pcdev);
1791 dev_err(&pdev->dev, "Camera interrupt register failed\n");
1795 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1796 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1797 pcdev->soc_host.priv = pcdev;
1798 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1799 pcdev->soc_host.nr = pdev->id;
1800 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
1802 err = soc_camera_host_register(&pcdev->soc_host);
1809 dma_release_channel(pcdev->dma_chans[2]);
1811 dma_release_channel(pcdev->dma_chans[1]);
1813 dma_release_channel(pcdev->dma_chans[0]);
1817 static int pxa_camera_remove(struct platform_device *pdev)
1819 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1820 struct pxa_camera_dev *pcdev = container_of(soc_host,
1821 struct pxa_camera_dev, soc_host);
1823 dma_release_channel(pcdev->dma_chans[0]);
1824 dma_release_channel(pcdev->dma_chans[1]);
1825 dma_release_channel(pcdev->dma_chans[2]);
1827 soc_camera_host_unregister(soc_host);
1829 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1834 static const struct dev_pm_ops pxa_camera_pm = {
1835 .suspend = pxa_camera_suspend,
1836 .resume = pxa_camera_resume,
1839 static const struct of_device_id pxa_camera_of_match[] = {
1840 { .compatible = "marvell,pxa270-qci", },
1843 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
1845 static struct platform_driver pxa_camera_driver = {
1847 .name = PXA_CAM_DRV_NAME,
1848 .pm = &pxa_camera_pm,
1849 .of_match_table = of_match_ptr(pxa_camera_of_match),
1851 .probe = pxa_camera_probe,
1852 .remove = pxa_camera_remove,
1855 module_platform_driver(pxa_camera_driver);
1857 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1858 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1859 MODULE_LICENSE("GPL");
1860 MODULE_VERSION(PXA_CAM_VERSION);
1861 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);