2 * winbond-cir.c - Driver for the Consumer IR functionality of Winbond
5 * Currently supports the Winbond WPCD376i chip (PNP id WEC1022), but
6 * could probably support others (Winbond WEC102X, NatSemi, etc)
7 * with minor modifications.
9 * Original Author: David Härdeman <david@hardeman.nu>
10 * Copyright (C) 2009 - 2011 David Härdeman <david@hardeman.nu>
12 * Dedicated to my daughter Matilda, without whose loving attention this
13 * driver would have been finished in half the time and with a fraction
17 * o Winbond WPCD376I datasheet helpfully provided by Jesse Barnes at Intel
18 * o NatSemi PC87338/PC97338 datasheet (for the serial port stuff)
24 * o Wake-On-CIR functionality
29 * This program is free software; you can redistribute it and/or modify
30 * it under the terms of the GNU General Public License as published by
31 * the Free Software Foundation; either version 2 of the License, or
32 * (at your option) any later version.
34 * This program is distributed in the hope that it will be useful,
35 * but WITHOUT ANY WARRANTY; without even the implied warranty of
36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
37 * GNU General Public License for more details.
39 * You should have received a copy of the GNU General Public License
40 * along with this program; if not, write to the Free Software
41 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
44 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
46 #include <linux/module.h>
47 #include <linux/pnp.h>
48 #include <linux/interrupt.h>
49 #include <linux/timer.h>
50 #include <linux/leds.h>
51 #include <linux/spinlock.h>
52 #include <linux/pci_ids.h>
54 #include <linux/bitrev.h>
55 #include <linux/slab.h>
56 #include <linux/wait.h>
57 #include <linux/sched.h>
58 #include <media/rc-core.h>
60 #define DRVNAME "winbond-cir"
62 /* CEIR Wake-Up Registers, relative to data->wbase */
63 #define WBCIR_REG_WCEIR_CTL 0x03 /* CEIR Receiver Control */
64 #define WBCIR_REG_WCEIR_STS 0x04 /* CEIR Receiver Status */
65 #define WBCIR_REG_WCEIR_EV_EN 0x05 /* CEIR Receiver Event Enable */
66 #define WBCIR_REG_WCEIR_CNTL 0x06 /* CEIR Receiver Counter Low */
67 #define WBCIR_REG_WCEIR_CNTH 0x07 /* CEIR Receiver Counter High */
68 #define WBCIR_REG_WCEIR_INDEX 0x08 /* CEIR Receiver Index */
69 #define WBCIR_REG_WCEIR_DATA 0x09 /* CEIR Receiver Data */
70 #define WBCIR_REG_WCEIR_CSL 0x0A /* CEIR Re. Compare Strlen */
71 #define WBCIR_REG_WCEIR_CFG1 0x0B /* CEIR Re. Configuration 1 */
72 #define WBCIR_REG_WCEIR_CFG2 0x0C /* CEIR Re. Configuration 2 */
74 /* CEIR Enhanced Functionality Registers, relative to data->ebase */
75 #define WBCIR_REG_ECEIR_CTS 0x00 /* Enhanced IR Control Status */
76 #define WBCIR_REG_ECEIR_CCTL 0x01 /* Infrared Counter Control */
77 #define WBCIR_REG_ECEIR_CNT_LO 0x02 /* Infrared Counter LSB */
78 #define WBCIR_REG_ECEIR_CNT_HI 0x03 /* Infrared Counter MSB */
79 #define WBCIR_REG_ECEIR_IREM 0x04 /* Infrared Emitter Status */
81 /* SP3 Banked Registers, relative to data->sbase */
82 #define WBCIR_REG_SP3_BSR 0x03 /* Bank Select, all banks */
84 #define WBCIR_REG_SP3_RXDATA 0x00 /* FIFO RX data (r) */
85 #define WBCIR_REG_SP3_TXDATA 0x00 /* FIFO TX data (w) */
86 #define WBCIR_REG_SP3_IER 0x01 /* Interrupt Enable */
87 #define WBCIR_REG_SP3_EIR 0x02 /* Event Identification (r) */
88 #define WBCIR_REG_SP3_FCR 0x02 /* FIFO Control (w) */
89 #define WBCIR_REG_SP3_MCR 0x04 /* Mode Control */
90 #define WBCIR_REG_SP3_LSR 0x05 /* Link Status */
91 #define WBCIR_REG_SP3_MSR 0x06 /* Modem Status */
92 #define WBCIR_REG_SP3_ASCR 0x07 /* Aux Status and Control */
94 #define WBCIR_REG_SP3_BGDL 0x00 /* Baud Divisor LSB */
95 #define WBCIR_REG_SP3_BGDH 0x01 /* Baud Divisor MSB */
96 #define WBCIR_REG_SP3_EXCR1 0x02 /* Extended Control 1 */
97 #define WBCIR_REG_SP3_EXCR2 0x04 /* Extended Control 2 */
98 #define WBCIR_REG_SP3_TXFLV 0x06 /* TX FIFO Level */
99 #define WBCIR_REG_SP3_RXFLV 0x07 /* RX FIFO Level */
101 #define WBCIR_REG_SP3_MRID 0x00 /* Module Identification */
102 #define WBCIR_REG_SP3_SH_LCR 0x01 /* LCR Shadow */
103 #define WBCIR_REG_SP3_SH_FCR 0x02 /* FCR Shadow */
105 #define WBCIR_REG_SP3_IRCR1 0x02 /* Infrared Control 1 */
107 #define WBCIR_REG_SP3_IRCR2 0x04 /* Infrared Control 2 */
109 #define WBCIR_REG_SP3_IRCR3 0x00 /* Infrared Control 3 */
110 #define WBCIR_REG_SP3_SIR_PW 0x02 /* SIR Pulse Width */
112 #define WBCIR_REG_SP3_IRRXDC 0x00 /* IR RX Demod Control */
113 #define WBCIR_REG_SP3_IRTXMC 0x01 /* IR TX Mod Control */
114 #define WBCIR_REG_SP3_RCCFG 0x02 /* CEIR Config */
115 #define WBCIR_REG_SP3_IRCFG1 0x04 /* Infrared Config 1 */
116 #define WBCIR_REG_SP3_IRCFG4 0x07 /* Infrared Config 4 */
119 * Magic values follow
122 /* No interrupts for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
123 #define WBCIR_IRQ_NONE 0x00
124 /* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
125 #define WBCIR_IRQ_RX 0x01
126 /* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
127 #define WBCIR_IRQ_TX_LOW 0x02
128 /* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
129 #define WBCIR_IRQ_ERR 0x04
130 /* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
131 #define WBCIR_IRQ_TX_EMPTY 0x20
132 /* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
133 #define WBCIR_LED_ENABLE 0x80
134 /* RX data available bit for WBCIR_REG_SP3_LSR */
135 #define WBCIR_RX_AVAIL 0x01
136 /* RX data overrun error bit for WBCIR_REG_SP3_LSR */
137 #define WBCIR_RX_OVERRUN 0x02
138 /* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
139 #define WBCIR_TX_EOT 0x04
140 /* RX disable bit for WBCIR_REG_SP3_ASCR */
141 #define WBCIR_RX_DISABLE 0x20
142 /* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
143 #define WBCIR_TX_UNDERRUN 0x40
144 /* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
145 #define WBCIR_EXT_ENABLE 0x01
146 /* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
147 #define WBCIR_REGSEL_COMPARE 0x10
148 /* Select mask register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
149 #define WBCIR_REGSEL_MASK 0x20
150 /* Starting address of selected register in WBCIR_REG_WCEIR_INDEX */
151 #define WBCIR_REG_ADDR0 0x00
153 /* Valid banks for the SP3 UART */
165 /* Supported power-on IR Protocols */
166 enum wbcir_protocol {
167 IR_PROTOCOL_RC5 = 0x0,
168 IR_PROTOCOL_NEC = 0x1,
169 IR_PROTOCOL_RC6 = 0x2,
172 /* Possible states for IR reception */
174 WBCIR_RXSTATE_INACTIVE = 0,
175 WBCIR_RXSTATE_ACTIVE,
179 /* Possible states for IR transmission */
181 WBCIR_TXSTATE_INACTIVE = 0,
182 WBCIR_TXSTATE_ACTIVE,
187 #define WBCIR_NAME "winbond-cir"
188 #define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
189 #define WBCIR_ID_CHIP 0x04 /* Chip ID for the WPCD376I */
190 #define INVALID_SCANCODE 0x7FFFFFFF /* Invalid with all protos */
191 #define WAKEUP_IOMEM_LEN 0x10 /* Wake-Up I/O Reg Len */
192 #define EHFUNC_IOMEM_LEN 0x10 /* Enhanced Func I/O Reg Len */
193 #define SP_IOMEM_LEN 0x08 /* Serial Port 3 (IR) Reg Len */
195 /* Per-device data */
199 struct led_classdev led;
201 unsigned long wbase; /* Wake-Up Baseaddr */
202 unsigned long ebase; /* Enhanced Func. Baseaddr */
203 unsigned long sbase; /* Serial Port Baseaddr */
204 unsigned int irq; /* Serial Port IRQ */
208 enum wbcir_rxstate rxstate;
209 struct led_trigger *rxtrigger;
210 struct ir_raw_event rxev;
213 enum wbcir_txstate txstate;
214 struct led_trigger *txtrigger;
222 static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
223 module_param(protocol, uint, 0444);
224 MODULE_PARM_DESC(protocol, "IR protocol to use for the power-on command "
225 "(0 = RC5, 1 = NEC, 2 = RC6A, default)");
227 static bool invert; /* default = 0 */
228 module_param(invert, bool, 0444);
229 MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
231 static bool txandrx; /* default = 0 */
232 module_param(txandrx, bool, 0444);
233 MODULE_PARM_DESC(txandrx, "Allow simultaneous TX and RX");
235 static unsigned int wake_sc = 0x800F040C;
236 module_param(wake_sc, uint, 0644);
237 MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
239 static unsigned int wake_rc6mode = 6;
240 module_param(wake_rc6mode, uint, 0644);
241 MODULE_PARM_DESC(wake_rc6mode, "RC6 mode for the power-on command "
242 "(0 = 0, 6 = 6A, default)");
246 /*****************************************************************************
250 *****************************************************************************/
252 /* Caller needs to hold wbcir_lock */
254 wbcir_set_bits(unsigned long addr, u8 bits, u8 mask)
259 val = ((val & ~mask) | (bits & mask));
263 /* Selects the register bank for the serial port */
265 wbcir_select_bank(struct wbcir_data *data, enum wbcir_bank bank)
267 outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
271 wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
273 if (data->irqmask == irqmask)
276 wbcir_select_bank(data, WBCIR_BANK_0);
277 outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
278 data->irqmask = irqmask;
281 static enum led_brightness
282 wbcir_led_brightness_get(struct led_classdev *led_cdev)
284 struct wbcir_data *data = container_of(led_cdev,
288 if (inb(data->ebase + WBCIR_REG_ECEIR_CTS) & WBCIR_LED_ENABLE)
295 wbcir_led_brightness_set(struct led_classdev *led_cdev,
296 enum led_brightness brightness)
298 struct wbcir_data *data = container_of(led_cdev,
302 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS,
303 brightness == LED_OFF ? 0x00 : WBCIR_LED_ENABLE,
307 /* Manchester encodes bits to RC6 message cells (see wbcir_shutdown) */
309 wbcir_to_rc6cells(u8 val)
315 for (i = 0; i < 4; i++) {
317 coded |= 0x02 << (i * 2);
319 coded |= 0x01 << (i * 2);
326 /*****************************************************************************
328 * INTERRUPT FUNCTIONS
330 *****************************************************************************/
333 wbcir_idle_rx(struct rc_dev *dev, bool idle)
335 struct wbcir_data *data = dev->priv;
337 if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
338 data->rxstate = WBCIR_RXSTATE_ACTIVE;
339 led_trigger_event(data->rxtrigger, LED_FULL);
342 if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE)
343 /* Tell hardware to go idle by setting RXINACTIVE */
344 outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
348 wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
351 DEFINE_IR_RAW_EVENT(rawir);
353 /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
354 while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
355 irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
356 if (data->rxstate == WBCIR_RXSTATE_ERROR)
358 rawir.pulse = irdata & 0x80 ? false : true;
359 rawir.duration = US_TO_NS(((irdata & 0x7F) + 1) * 10);
360 ir_raw_event_store_with_filter(data->dev, &rawir);
363 /* Check if we should go idle */
364 if (data->dev->idle) {
365 led_trigger_event(data->rxtrigger, LED_OFF);
366 data->rxstate = WBCIR_RXSTATE_INACTIVE;
369 ir_raw_event_handle(data->dev);
373 wbcir_irq_tx(struct wbcir_data *data)
383 switch (data->txstate) {
384 case WBCIR_TXSTATE_INACTIVE:
387 led_trigger_event(data->txtrigger, LED_FULL);
389 case WBCIR_TXSTATE_ACTIVE:
390 /* TX FIFO low (3 bytes or less) */
393 case WBCIR_TXSTATE_ERROR:
401 * TX data is run-length coded in bytes: YXXXXXXX
402 * Y = space (1) or pulse (0)
403 * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
405 for (used = 0; used < space && data->txoff != data->txlen; used++) {
406 if (data->txbuf[data->txoff] == 0) {
410 byte = min((u32)0x80, data->txbuf[data->txoff]);
411 data->txbuf[data->txoff] -= byte;
413 byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
417 while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
422 if (data->txstate == WBCIR_TXSTATE_ERROR)
423 /* Clear TX underrun bit */
424 outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
425 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
426 led_trigger_event(data->txtrigger, LED_OFF);
429 data->txstate = WBCIR_TXSTATE_INACTIVE;
430 } else if (data->txoff == data->txlen) {
431 /* At the end of transmission, tell the hw before last byte */
432 outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
433 outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
434 outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
435 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
438 /* More data to follow... */
439 outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
440 if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
441 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
443 data->txstate = WBCIR_TXSTATE_ACTIVE;
449 wbcir_irq_handler(int irqno, void *cookie)
451 struct pnp_dev *device = cookie;
452 struct wbcir_data *data = pnp_get_drvdata(device);
456 spin_lock_irqsave(&data->spinlock, flags);
457 wbcir_select_bank(data, WBCIR_BANK_0);
458 status = inb(data->sbase + WBCIR_REG_SP3_EIR);
459 status &= data->irqmask;
462 spin_unlock_irqrestore(&data->spinlock, flags);
466 if (status & WBCIR_IRQ_ERR) {
467 /* RX overflow? (read clears bit) */
468 if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
469 data->rxstate = WBCIR_RXSTATE_ERROR;
470 ir_raw_event_reset(data->dev);
474 if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
475 data->txstate = WBCIR_TXSTATE_ERROR;
478 if (status & WBCIR_IRQ_RX)
479 wbcir_irq_rx(data, device);
481 if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
484 spin_unlock_irqrestore(&data->spinlock, flags);
488 /*****************************************************************************
490 * RC-CORE INTERFACE FUNCTIONS
492 *****************************************************************************/
495 wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
497 struct wbcir_data *data = dev->priv;
502 freq = DIV_ROUND_CLOSEST(carrier, 1000);
503 if (freq < 30 || freq > 60)
523 spin_lock_irqsave(&data->spinlock, flags);
524 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
525 spin_unlock_irqrestore(&data->spinlock, flags);
529 if (data->txcarrier != freq) {
530 wbcir_select_bank(data, WBCIR_BANK_7);
531 wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
532 data->txcarrier = freq;
535 spin_unlock_irqrestore(&data->spinlock, flags);
540 wbcir_txmask(struct rc_dev *dev, u32 mask)
542 struct wbcir_data *data = dev->priv;
546 /* Four outputs, only one output can be enabled at a time */
564 spin_lock_irqsave(&data->spinlock, flags);
565 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
566 spin_unlock_irqrestore(&data->spinlock, flags);
570 if (data->txmask != mask) {
571 wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
575 spin_unlock_irqrestore(&data->spinlock, flags);
580 wbcir_tx(struct rc_dev *dev, unsigned *b, unsigned count)
582 struct wbcir_data *data = dev->priv;
587 buf = kmalloc(count * sizeof(*b), GFP_KERNEL);
591 /* Convert values to multiples of 10us */
592 for (i = 0; i < count; i++)
593 buf[i] = DIV_ROUND_CLOSEST(b[i], 10);
595 /* Not sure if this is possible, but better safe than sorry */
596 spin_lock_irqsave(&data->spinlock, flags);
597 if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
598 spin_unlock_irqrestore(&data->spinlock, flags);
603 /* Fill the TX fifo once, the irq handler will do the rest */
610 spin_unlock_irqrestore(&data->spinlock, flags);
614 /*****************************************************************************
616 * SETUP/INIT/SUSPEND/RESUME FUNCTIONS
618 *****************************************************************************/
621 wbcir_shutdown(struct pnp_dev *device)
623 struct device *dev = &device->dev;
624 struct wbcir_data *data = pnp_get_drvdata(device);
631 memset(match, 0, sizeof(match));
632 memset(mask, 0, sizeof(mask));
634 if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
640 case IR_PROTOCOL_RC5:
641 if (wake_sc > 0xFFF) {
643 dev_err(dev, "RC5 - Invalid wake scancode\n");
647 /* Mask = 13 bits, ex toggle */
651 match[0] = (wake_sc & 0x003F); /* 6 command bits */
652 match[0] |= (wake_sc & 0x0180) >> 1; /* 2 address bits */
653 match[1] = (wake_sc & 0x0E00) >> 9; /* 3 address bits */
654 if (!(wake_sc & 0x0040)) /* 2nd start bit */
659 case IR_PROTOCOL_NEC:
660 if (wake_sc > 0xFFFFFF) {
662 dev_err(dev, "NEC - Invalid wake scancode\n");
666 mask[0] = mask[1] = mask[2] = mask[3] = 0xFF;
668 match[1] = bitrev8((wake_sc & 0xFF));
669 match[0] = ~match[1];
671 match[3] = bitrev8((wake_sc & 0xFF00) >> 8);
672 if (wake_sc > 0xFFFF)
673 match[2] = bitrev8((wake_sc & 0xFF0000) >> 16);
675 match[2] = ~match[3];
679 case IR_PROTOCOL_RC6:
681 if (wake_rc6mode == 0) {
682 if (wake_sc > 0xFFFF) {
684 dev_err(dev, "RC6 - Invalid wake scancode\n");
689 match[0] = wbcir_to_rc6cells(wake_sc >> 0);
691 match[1] = wbcir_to_rc6cells(wake_sc >> 4);
695 match[2] = wbcir_to_rc6cells(wake_sc >> 8);
697 match[3] = wbcir_to_rc6cells(wake_sc >> 12);
701 match[4] = 0x50; /* mode1 = mode0 = 0, ignore toggle */
703 match[5] = 0x09; /* start bit = 1, mode2 = 0 */
708 } else if (wake_rc6mode == 6) {
712 match[i] = wbcir_to_rc6cells(wake_sc >> 0);
714 match[i] = wbcir_to_rc6cells(wake_sc >> 4);
717 /* Address + Toggle */
718 match[i] = wbcir_to_rc6cells(wake_sc >> 8);
720 match[i] = wbcir_to_rc6cells(wake_sc >> 12);
723 /* Customer bits 7 - 0 */
724 match[i] = wbcir_to_rc6cells(wake_sc >> 16);
726 match[i] = wbcir_to_rc6cells(wake_sc >> 20);
729 if (wake_sc & 0x80000000) {
730 /* Customer range bit and bits 15 - 8 */
731 match[i] = wbcir_to_rc6cells(wake_sc >> 24);
733 match[i] = wbcir_to_rc6cells(wake_sc >> 28);
736 } else if (wake_sc <= 0x007FFFFF) {
740 dev_err(dev, "RC6 - Invalid wake scancode\n");
745 match[i] = 0x93; /* mode1 = mode0 = 1, submode = 0 */
747 match[i] = 0x0A; /* start bit = 1, mode2 = 1 */
752 dev_err(dev, "RC6 - Invalid wake mode\n");
764 /* Set compare and compare mask */
765 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
766 WBCIR_REGSEL_COMPARE | WBCIR_REG_ADDR0,
768 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, match, 11);
769 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_INDEX,
770 WBCIR_REGSEL_MASK | WBCIR_REG_ADDR0,
772 outsb(data->wbase + WBCIR_REG_WCEIR_DATA, mask, 11);
774 /* RC6 Compare String Len */
775 outb(rc6_csl, data->wbase + WBCIR_REG_WCEIR_CSL);
777 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
778 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
780 /* Clear BUFF_EN, Clear END_EN, Set MATCH_EN */
781 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x01, 0x07);
784 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x01, 0x01);
787 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
788 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
791 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
795 * ACPI will set the HW disable bit for SP3 which means that the
796 * output signals are left in an undefined state which may cause
797 * spurious interrupts which we need to ignore until the hardware
800 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
801 disable_irq(data->irq);
804 led_trigger_event(data->rxtrigger, LED_OFF);
805 led_trigger_event(data->txtrigger, LED_OFF);
809 wbcir_suspend(struct pnp_dev *device, pm_message_t state)
811 wbcir_shutdown(device);
816 wbcir_init_hw(struct wbcir_data *data)
820 /* Disable interrupts */
821 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
823 /* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
827 outb(tmp, data->wbase + WBCIR_REG_WCEIR_CTL);
829 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
830 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
832 /* Clear BUFF_EN, Clear END_EN, Clear MATCH_EN */
833 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
835 /* Set RC5 cell time to correspond to 36 kHz */
836 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CFG1, 0x4A, 0x7F);
840 outb(0x04, data->ebase + WBCIR_REG_ECEIR_CCTL);
842 outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
845 * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
846 * set SP3_IRRX_SW to binary 01, helpfully not documented
848 outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
851 /* Enable extended mode */
852 wbcir_select_bank(data, WBCIR_BANK_2);
853 outb(WBCIR_EXT_ENABLE, data->sbase + WBCIR_REG_SP3_EXCR1);
856 * Configure baud generator, IR data will be sampled at
857 * a bitrate of: (24Mhz * prescaler) / (divisor * 16).
859 * The ECIR registers include a flag to change the
860 * 24Mhz clock freq to 48Mhz.
862 * It's not documented in the specs, but fifo levels
863 * other than 16 seems to be unsupported.
866 /* prescaler 1.0, tx/rx fifo lvl 16 */
867 outb(0x30, data->sbase + WBCIR_REG_SP3_EXCR2);
869 /* Set baud divisor to sample every 10 us */
870 outb(0x0F, data->sbase + WBCIR_REG_SP3_BGDL);
871 outb(0x00, data->sbase + WBCIR_REG_SP3_BGDH);
874 wbcir_select_bank(data, WBCIR_BANK_0);
875 outb(0xC0, data->sbase + WBCIR_REG_SP3_MCR);
876 inb(data->sbase + WBCIR_REG_SP3_LSR); /* Clear LSR */
877 inb(data->sbase + WBCIR_REG_SP3_MSR); /* Clear MSR */
879 /* Disable RX demod, enable run-length enc/dec, set freq span */
880 wbcir_select_bank(data, WBCIR_BANK_7);
881 outb(0x90, data->sbase + WBCIR_REG_SP3_RCCFG);
884 wbcir_select_bank(data, WBCIR_BANK_4);
885 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
887 /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
888 wbcir_select_bank(data, WBCIR_BANK_5);
889 outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
892 wbcir_select_bank(data, WBCIR_BANK_6);
893 outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
895 /* Set RX demodulation freq, not really used */
896 wbcir_select_bank(data, WBCIR_BANK_7);
897 outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
899 /* Set TX modulation, 36kHz, 7us pulse width */
900 outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
901 data->txcarrier = 36000;
903 /* Set invert and pin direction */
905 outb(0x10, data->sbase + WBCIR_REG_SP3_IRCFG4);
907 outb(0x00, data->sbase + WBCIR_REG_SP3_IRCFG4);
909 /* Set FIFO thresholds (RX = 8, TX = 3), reset RX/TX */
910 wbcir_select_bank(data, WBCIR_BANK_0);
911 outb(0x97, data->sbase + WBCIR_REG_SP3_FCR);
913 /* Clear AUX status bits */
914 outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
917 data->rxstate = WBCIR_RXSTATE_INACTIVE;
918 data->rxev.duration = 0;
919 ir_raw_event_reset(data->dev);
920 ir_raw_event_handle(data->dev);
923 if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
926 data->txstate = WBCIR_TXSTATE_INACTIVE;
929 /* Enable interrupts */
930 wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
934 wbcir_resume(struct pnp_dev *device)
936 struct wbcir_data *data = pnp_get_drvdata(device);
939 enable_irq(data->irq);
945 wbcir_probe(struct pnp_dev *device, const struct pnp_device_id *dev_id)
947 struct device *dev = &device->dev;
948 struct wbcir_data *data;
951 if (!(pnp_port_len(device, 0) == EHFUNC_IOMEM_LEN &&
952 pnp_port_len(device, 1) == WAKEUP_IOMEM_LEN &&
953 pnp_port_len(device, 2) == SP_IOMEM_LEN)) {
954 dev_err(dev, "Invalid resources\n");
958 data = kzalloc(sizeof(*data), GFP_KERNEL);
964 pnp_set_drvdata(device, data);
966 spin_lock_init(&data->spinlock);
967 data->ebase = pnp_port_start(device, 0);
968 data->wbase = pnp_port_start(device, 1);
969 data->sbase = pnp_port_start(device, 2);
970 data->irq = pnp_irq(device, 0);
972 if (data->wbase == 0 || data->ebase == 0 ||
973 data->sbase == 0 || data->irq == 0) {
975 dev_err(dev, "Invalid resources\n");
979 dev_dbg(&device->dev, "Found device "
980 "(w: 0x%lX, e: 0x%lX, s: 0x%lX, i: %u)\n",
981 data->wbase, data->ebase, data->sbase, data->irq);
983 led_trigger_register_simple("cir-tx", &data->txtrigger);
984 if (!data->txtrigger) {
989 led_trigger_register_simple("cir-rx", &data->rxtrigger);
990 if (!data->rxtrigger) {
992 goto exit_unregister_txtrigger;
995 data->led.name = "cir::activity";
996 data->led.default_trigger = "cir-rx";
997 data->led.brightness_set = wbcir_led_brightness_set;
998 data->led.brightness_get = wbcir_led_brightness_get;
999 err = led_classdev_register(&device->dev, &data->led);
1001 goto exit_unregister_rxtrigger;
1003 data->dev = rc_allocate_device();
1006 goto exit_unregister_led;
1009 data->dev->driver_type = RC_DRIVER_IR_RAW;
1010 data->dev->driver_name = WBCIR_NAME;
1011 data->dev->input_name = WBCIR_NAME;
1012 data->dev->input_phys = "wbcir/cir0";
1013 data->dev->input_id.bustype = BUS_HOST;
1014 data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
1015 data->dev->input_id.product = WBCIR_ID_FAMILY;
1016 data->dev->input_id.version = WBCIR_ID_CHIP;
1017 data->dev->map_name = RC_MAP_RC6_MCE;
1018 data->dev->s_idle = wbcir_idle_rx;
1019 data->dev->s_tx_mask = wbcir_txmask;
1020 data->dev->s_tx_carrier = wbcir_txcarrier;
1021 data->dev->tx_ir = wbcir_tx;
1022 data->dev->priv = data;
1023 data->dev->dev.parent = &device->dev;
1024 data->dev->timeout = MS_TO_NS(100);
1025 data->dev->allowed_protos = RC_TYPE_ALL;
1027 if (!request_region(data->wbase, WAKEUP_IOMEM_LEN, DRVNAME)) {
1028 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1029 data->wbase, data->wbase + WAKEUP_IOMEM_LEN - 1);
1034 if (!request_region(data->ebase, EHFUNC_IOMEM_LEN, DRVNAME)) {
1035 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1036 data->ebase, data->ebase + EHFUNC_IOMEM_LEN - 1);
1038 goto exit_release_wbase;
1041 if (!request_region(data->sbase, SP_IOMEM_LEN, DRVNAME)) {
1042 dev_err(dev, "Region 0x%lx-0x%lx already in use!\n",
1043 data->sbase, data->sbase + SP_IOMEM_LEN - 1);
1045 goto exit_release_ebase;
1048 err = request_irq(data->irq, wbcir_irq_handler,
1049 IRQF_DISABLED, DRVNAME, device);
1051 dev_err(dev, "Failed to claim IRQ %u\n", data->irq);
1053 goto exit_release_sbase;
1056 err = rc_register_device(data->dev);
1060 device_init_wakeup(&device->dev, 1);
1062 wbcir_init_hw(data);
1067 free_irq(data->irq, device);
1069 release_region(data->sbase, SP_IOMEM_LEN);
1071 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1073 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1075 rc_free_device(data->dev);
1076 exit_unregister_led:
1077 led_classdev_unregister(&data->led);
1078 exit_unregister_rxtrigger:
1079 led_trigger_unregister_simple(data->rxtrigger);
1080 exit_unregister_txtrigger:
1081 led_trigger_unregister_simple(data->txtrigger);
1084 pnp_set_drvdata(device, NULL);
1089 static void __devexit
1090 wbcir_remove(struct pnp_dev *device)
1092 struct wbcir_data *data = pnp_get_drvdata(device);
1094 /* Disable interrupts */
1095 wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
1096 free_irq(data->irq, device);
1098 /* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
1099 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_STS, 0x17, 0x17);
1102 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
1104 /* Clear BUFF_EN, END_EN, MATCH_EN */
1105 wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_EV_EN, 0x00, 0x07);
1107 rc_unregister_device(data->dev);
1109 led_trigger_unregister_simple(data->rxtrigger);
1110 led_trigger_unregister_simple(data->txtrigger);
1111 led_classdev_unregister(&data->led);
1113 /* This is ok since &data->led isn't actually used */
1114 wbcir_led_brightness_set(&data->led, LED_OFF);
1116 release_region(data->wbase, WAKEUP_IOMEM_LEN);
1117 release_region(data->ebase, EHFUNC_IOMEM_LEN);
1118 release_region(data->sbase, SP_IOMEM_LEN);
1122 pnp_set_drvdata(device, NULL);
1125 static const struct pnp_device_id wbcir_ids[] = {
1129 MODULE_DEVICE_TABLE(pnp, wbcir_ids);
1131 static struct pnp_driver wbcir_driver = {
1133 .id_table = wbcir_ids,
1134 .probe = wbcir_probe,
1135 .remove = __devexit_p(wbcir_remove),
1136 .suspend = wbcir_suspend,
1137 .resume = wbcir_resume,
1138 .shutdown = wbcir_shutdown
1147 case IR_PROTOCOL_RC5:
1148 case IR_PROTOCOL_NEC:
1149 case IR_PROTOCOL_RC6:
1152 pr_err("Invalid power-on protocol\n");
1155 ret = pnp_register_driver(&wbcir_driver);
1157 pr_err("Unable to register driver\n");
1165 pnp_unregister_driver(&wbcir_driver);
1168 module_init(wbcir_init);
1169 module_exit(wbcir_exit);
1171 MODULE_AUTHOR("David Härdeman <david@hardeman.nu>");
1172 MODULE_DESCRIPTION("Winbond SuperI/O Consumer IR Driver");
1173 MODULE_LICENSE("GPL");