2 * FCI FC2580 silicon tuner driver
4 * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 #include "fc2580_priv.h"
25 * I2C write and read works only for one single register. Multiple registers
26 * could not be accessed using normal register address auto-increment.
27 * There could be (very likely) register to change that behavior....
29 * Due to that limitation functions:
32 * could not be used for accessing more than one register at once.
35 * Currently it blind writes bunch of static registers from the
36 * fc2580_freq_regs_lut[] when fc2580_set_params() is called. Add some
37 * logic to reduce unneeded register writes.
38 * There is also don't-care registers, initialized with value 0xff, and those
39 * are also written to the chip currently (yes, not wise).
42 /* write multiple registers */
43 static int fc2580_wr_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
47 struct i2c_msg msg[1] = {
49 .addr = priv->cfg->i2c_addr,
57 memcpy(&buf[1], val, len);
59 ret = i2c_transfer(priv->i2c, msg, 1);
63 dev_warn(&priv->i2c->dev, "%s: i2c wr failed=%d reg=%02x " \
64 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
70 /* read multiple registers */
71 static int fc2580_rd_regs(struct fc2580_priv *priv, u8 reg, u8 *val, int len)
75 struct i2c_msg msg[2] = {
77 .addr = priv->cfg->i2c_addr,
82 .addr = priv->cfg->i2c_addr,
89 ret = i2c_transfer(priv->i2c, msg, 2);
91 memcpy(val, buf, len);
94 dev_warn(&priv->i2c->dev, "%s: i2c rd failed=%d reg=%02x " \
95 "len=%d\n", KBUILD_MODNAME, ret, reg, len);
102 /* write single register */
103 static int fc2580_wr_reg(struct fc2580_priv *priv, u8 reg, u8 val)
105 return fc2580_wr_regs(priv, reg, &val, 1);
108 /* read single register */
109 static int fc2580_rd_reg(struct fc2580_priv *priv, u8 reg, u8 *val)
111 return fc2580_rd_regs(priv, reg, val, 1);
114 static int fc2580_set_params(struct dvb_frontend *fe)
116 struct fc2580_priv *priv = fe->tuner_priv;
117 struct dtv_frontend_properties *c = &fe->dtv_property_cache;
119 unsigned int r_val, n_val, k_val, k_val_reg, f_ref;
124 * Fractional-N synthesizer/PLL.
125 * Most likely all those PLL calculations are not correct. I am not
126 * sure, but it looks like it is divider based Fractional-N synthesizer.
127 * There is divider for reference clock too?
128 * Anyhow, synthesizer calculation results seems to be quite correct.
131 dev_dbg(&priv->i2c->dev, "%s: delivery_system=%d frequency=%d " \
132 "bandwidth_hz=%d\n", __func__,
133 c->delivery_system, c->frequency, c->bandwidth_hz);
135 if (fe->ops.i2c_gate_ctrl)
136 fe->ops.i2c_gate_ctrl(fe, 1);
139 for (i = 0; i < ARRAY_SIZE(fc2580_pll_lut); i++) {
140 if (c->frequency <= fc2580_pll_lut[i].freq)
144 if (i == ARRAY_SIZE(fc2580_pll_lut))
147 f_vco = c->frequency;
148 f_vco *= fc2580_pll_lut[i].div;
150 if (f_vco >= 2600000000UL)
151 tmp_val = 0x0e | fc2580_pll_lut[i].band;
153 tmp_val = 0x06 | fc2580_pll_lut[i].band;
155 ret = fc2580_wr_reg(priv, 0x02, tmp_val);
159 if (f_vco >= 2UL * 76 * priv->cfg->clock) {
162 } else if (f_vco >= 1UL * 76 * priv->cfg->clock) {
170 f_ref = 2UL * priv->cfg->clock / r_val;
171 n_val = div_u64_rem(f_vco, f_ref, &k_val);
172 k_val_reg = 1UL * k_val * (1 << 20) / f_ref;
174 ret = fc2580_wr_reg(priv, 0x18, r18_val | ((k_val_reg >> 16) & 0xff));
178 ret = fc2580_wr_reg(priv, 0x1a, (k_val_reg >> 8) & 0xff);
182 ret = fc2580_wr_reg(priv, 0x1b, (k_val_reg >> 0) & 0xff);
186 ret = fc2580_wr_reg(priv, 0x1c, n_val);
190 if (priv->cfg->clock >= 28000000) {
191 ret = fc2580_wr_reg(priv, 0x4b, 0x22);
196 if (fc2580_pll_lut[i].band == 0x00) {
197 if (c->frequency <= 794000000)
202 ret = fc2580_wr_reg(priv, 0x2d, tmp_val);
208 for (i = 0; i < ARRAY_SIZE(fc2580_freq_regs_lut); i++) {
209 if (c->frequency <= fc2580_freq_regs_lut[i].freq)
213 if (i == ARRAY_SIZE(fc2580_freq_regs_lut))
216 ret = fc2580_wr_reg(priv, 0x25, fc2580_freq_regs_lut[i].r25_val);
220 ret = fc2580_wr_reg(priv, 0x27, fc2580_freq_regs_lut[i].r27_val);
224 ret = fc2580_wr_reg(priv, 0x28, fc2580_freq_regs_lut[i].r28_val);
228 ret = fc2580_wr_reg(priv, 0x29, fc2580_freq_regs_lut[i].r29_val);
232 ret = fc2580_wr_reg(priv, 0x2b, fc2580_freq_regs_lut[i].r2b_val);
236 ret = fc2580_wr_reg(priv, 0x2c, fc2580_freq_regs_lut[i].r2c_val);
240 ret = fc2580_wr_reg(priv, 0x2d, fc2580_freq_regs_lut[i].r2d_val);
244 ret = fc2580_wr_reg(priv, 0x30, fc2580_freq_regs_lut[i].r30_val);
248 ret = fc2580_wr_reg(priv, 0x44, fc2580_freq_regs_lut[i].r44_val);
252 ret = fc2580_wr_reg(priv, 0x50, fc2580_freq_regs_lut[i].r50_val);
256 ret = fc2580_wr_reg(priv, 0x53, fc2580_freq_regs_lut[i].r53_val);
260 ret = fc2580_wr_reg(priv, 0x5f, fc2580_freq_regs_lut[i].r5f_val);
264 ret = fc2580_wr_reg(priv, 0x61, fc2580_freq_regs_lut[i].r61_val);
268 ret = fc2580_wr_reg(priv, 0x62, fc2580_freq_regs_lut[i].r62_val);
272 ret = fc2580_wr_reg(priv, 0x63, fc2580_freq_regs_lut[i].r63_val);
276 ret = fc2580_wr_reg(priv, 0x67, fc2580_freq_regs_lut[i].r67_val);
280 ret = fc2580_wr_reg(priv, 0x68, fc2580_freq_regs_lut[i].r68_val);
284 ret = fc2580_wr_reg(priv, 0x69, fc2580_freq_regs_lut[i].r69_val);
288 ret = fc2580_wr_reg(priv, 0x6a, fc2580_freq_regs_lut[i].r6a_val);
292 ret = fc2580_wr_reg(priv, 0x6b, fc2580_freq_regs_lut[i].r6b_val);
296 ret = fc2580_wr_reg(priv, 0x6c, fc2580_freq_regs_lut[i].r6c_val);
300 ret = fc2580_wr_reg(priv, 0x6d, fc2580_freq_regs_lut[i].r6d_val);
304 ret = fc2580_wr_reg(priv, 0x6e, fc2580_freq_regs_lut[i].r6e_val);
308 ret = fc2580_wr_reg(priv, 0x6f, fc2580_freq_regs_lut[i].r6f_val);
313 for (i = 0; i < ARRAY_SIZE(fc2580_if_filter_lut); i++) {
314 if (c->bandwidth_hz <= fc2580_if_filter_lut[i].freq)
318 if (i == ARRAY_SIZE(fc2580_if_filter_lut))
321 ret = fc2580_wr_reg(priv, 0x36, fc2580_if_filter_lut[i].r36_val);
325 ret = fc2580_wr_reg(priv, 0x37, 1UL * priv->cfg->clock * \
326 fc2580_if_filter_lut[i].mul / 1000000000);
330 ret = fc2580_wr_reg(priv, 0x39, fc2580_if_filter_lut[i].r39_val);
335 ret = fc2580_wr_reg(priv, 0x2e, 0x09);
339 for (i = 0; i < 5; i++) {
340 ret = fc2580_rd_reg(priv, 0x2f, &tmp_val);
344 /* done when [7:6] are set */
345 if ((tmp_val & 0xc0) == 0xc0)
348 ret = fc2580_wr_reg(priv, 0x2e, 0x01);
352 ret = fc2580_wr_reg(priv, 0x2e, 0x09);
356 usleep_range(5000, 25000);
359 dev_dbg(&priv->i2c->dev, "%s: loop=%i\n", __func__, i);
361 ret = fc2580_wr_reg(priv, 0x2e, 0x01);
365 if (fe->ops.i2c_gate_ctrl)
366 fe->ops.i2c_gate_ctrl(fe, 0);
370 if (fe->ops.i2c_gate_ctrl)
371 fe->ops.i2c_gate_ctrl(fe, 0);
373 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
377 static int fc2580_init(struct dvb_frontend *fe)
379 struct fc2580_priv *priv = fe->tuner_priv;
382 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
384 if (fe->ops.i2c_gate_ctrl)
385 fe->ops.i2c_gate_ctrl(fe, 1);
387 for (i = 0; i < ARRAY_SIZE(fc2580_init_reg_vals); i++) {
388 ret = fc2580_wr_reg(priv, fc2580_init_reg_vals[i].reg,
389 fc2580_init_reg_vals[i].val);
394 if (fe->ops.i2c_gate_ctrl)
395 fe->ops.i2c_gate_ctrl(fe, 0);
399 if (fe->ops.i2c_gate_ctrl)
400 fe->ops.i2c_gate_ctrl(fe, 0);
402 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
406 static int fc2580_sleep(struct dvb_frontend *fe)
408 struct fc2580_priv *priv = fe->tuner_priv;
411 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
413 if (fe->ops.i2c_gate_ctrl)
414 fe->ops.i2c_gate_ctrl(fe, 1);
416 ret = fc2580_wr_reg(priv, 0x02, 0x0a);
420 if (fe->ops.i2c_gate_ctrl)
421 fe->ops.i2c_gate_ctrl(fe, 0);
425 if (fe->ops.i2c_gate_ctrl)
426 fe->ops.i2c_gate_ctrl(fe, 0);
428 dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
432 static int fc2580_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
434 struct fc2580_priv *priv = fe->tuner_priv;
436 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
438 *frequency = 0; /* Zero-IF */
443 static int fc2580_release(struct dvb_frontend *fe)
445 struct fc2580_priv *priv = fe->tuner_priv;
447 dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
449 kfree(fe->tuner_priv);
454 static const struct dvb_tuner_ops fc2580_tuner_ops = {
456 .name = "FCI FC2580",
457 .frequency_min = 174000000,
458 .frequency_max = 862000000,
461 .release = fc2580_release,
464 .sleep = fc2580_sleep,
465 .set_params = fc2580_set_params,
467 .get_if_frequency = fc2580_get_if_frequency,
470 struct dvb_frontend *fc2580_attach(struct dvb_frontend *fe,
471 struct i2c_adapter *i2c, const struct fc2580_config *cfg)
473 struct fc2580_priv *priv;
477 if (fe->ops.i2c_gate_ctrl)
478 fe->ops.i2c_gate_ctrl(fe, 1);
480 priv = kzalloc(sizeof(struct fc2580_priv), GFP_KERNEL);
483 dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
490 /* check if the tuner is there */
491 ret = fc2580_rd_reg(priv, 0x01, &chip_id);
495 dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
505 dev_info(&priv->i2c->dev,
506 "%s: FCI FC2580 successfully identified\n",
509 fe->tuner_priv = priv;
510 memcpy(&fe->ops.tuner_ops, &fc2580_tuner_ops,
511 sizeof(struct dvb_tuner_ops));
513 if (fe->ops.i2c_gate_ctrl)
514 fe->ops.i2c_gate_ctrl(fe, 0);
518 if (fe->ops.i2c_gate_ctrl)
519 fe->ops.i2c_gate_ctrl(fe, 0);
521 dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
525 EXPORT_SYMBOL(fc2580_attach);
527 MODULE_DESCRIPTION("FCI FC2580 silicon tuner driver");
528 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
529 MODULE_LICENSE("GPL");