drivers/media/video/exynos/tv/hdmi_reg_5250.c

   1 /*
   2  * Samsung HDMI driver
   3  *
   4  * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
   5  *
   6  * Jiun Yu <jiun.yu@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published
  10  * by the Free Software Foundiation. either version 2 of the License,
  11  * or (at your option) any later version
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/pm_runtime.h>
  16 #include <plat/devs.h>
  17 #include <plat/tv-core.h>
  18
  19 #include "hdmi.h"
  20 #include "regs-hdmi-5250.h"
  21
  22 static const struct hdmi_preset_conf hdmi_conf_480p60 = {
  23         .core = {
  24                 .h_blank = {0x8a, 0x00},
  25                 .v2_blank = {0x0d, 0x02},
  26                 .v1_blank = {0x2d, 0x00},
  27                 .v_line = {0x0d, 0x02},
  28                 .h_line = {0x5a, 0x03},
  29                 .hsync_pol = {0x01},
  30                 .vsync_pol = {0x01},
  31                 .int_pro_mode = {0x00},
  32                 .v_blank_f0 = {0xff, 0xff},
  33                 .v_blank_f1 = {0xff, 0xff},
  34                 .h_sync_start = {0x0e, 0x00},
  35                 .h_sync_end = {0x4c, 0x00},
  36                 .v_sync_line_bef_2 = {0x0f, 0x00},
  37                 .v_sync_line_bef_1 = {0x09, 0x00},
  38                 .v_sync_line_aft_2 = {0xff, 0xff},
  39                 .v_sync_line_aft_1 = {0xff, 0xff},
  40                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
  41                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
  42                 .v_blank_f2 = {0xff, 0xff},
  43                 .v_blank_f3 = {0xff, 0xff},
  44                 .v_blank_f4 = {0xff, 0xff},
  45                 .v_blank_f5 = {0xff, 0xff},
  46                 .v_sync_line_aft_3 = {0xff, 0xff},
  47                 .v_sync_line_aft_4 = {0xff, 0xff},
  48                 .v_sync_line_aft_5 = {0xff, 0xff},
  49                 .v_sync_line_aft_6 = {0xff, 0xff},
  50                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
  51                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
  52                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
  53                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
  54                 .vact_space_1 = {0xff, 0xff},
  55                 .vact_space_2 = {0xff, 0xff},
  56                 .vact_space_3 = {0xff, 0xff},
  57                 .vact_space_4 = {0xff, 0xff},
  58                 .vact_space_5 = {0xff, 0xff},
  59                 .vact_space_6 = {0xff, 0xff},
  60                 /* other don't care */
  61         },
  62         .tg = {
  63                 0x00, /* cmd */
  64                 0x5a, 0x03, /* h_fsz */
  65                 0x8a, 0x00, 0xd0, 0x02, /* hact */
  66                 0x0d, 0x02, /* v_fsz */
  67                 0x01, 0x00, 0x33, 0x02, /* vsync */
  68                 0x2d, 0x00, 0xe0, 0x01, /* vact */
  69                 0x33, 0x02, /* field_chg */
  70                 0x48, 0x02, /* vact_st2 */
  71                 0x00, 0x00, /* vact_st3 */
  72                 0x00, 0x00, /* vact_st4 */
  73                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
  74                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
  75                 0x00, /* 3d FP */
  76         },
  77         .mbus_fmt = {
  78                 .width = 720,
  79                 .height = 480,
  80                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
  81                 .field = V4L2_FIELD_NONE,
  82         },
  83 };
  84
  85 static const struct hdmi_preset_conf hdmi_conf_720p60 = {
  86         .core = {
  87                 .h_blank = {0x72, 0x01},
  88                 .v2_blank = {0xee, 0x02},
  89                 .v1_blank = {0x1e, 0x00},
  90                 .v_line = {0xee, 0x02},
  91                 .h_line = {0x72, 0x06},
  92                 .hsync_pol = {0x00},
  93                 .vsync_pol = {0x00},
  94                 .int_pro_mode = {0x00},
  95                 .v_blank_f0 = {0xff, 0xff},
  96                 .v_blank_f1 = {0xff, 0xff},
  97                 .h_sync_start = {0x6c, 0x00},
  98                 .h_sync_end = {0x94, 0x00},
  99                 .v_sync_line_bef_2 = {0x0a, 0x00},
 100                 .v_sync_line_bef_1 = {0x05, 0x00},
 101                 .v_sync_line_aft_2 = {0xff, 0xff},
 102                 .v_sync_line_aft_1 = {0xff, 0xff},
 103                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 104                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 105                 .v_blank_f2 = {0xff, 0xff},
 106                 .v_blank_f3 = {0xff, 0xff},
 107                 .v_blank_f4 = {0xff, 0xff},
 108                 .v_blank_f5 = {0xff, 0xff},
 109                 .v_sync_line_aft_3 = {0xff, 0xff},
 110                 .v_sync_line_aft_4 = {0xff, 0xff},
 111                 .v_sync_line_aft_5 = {0xff, 0xff},
 112                 .v_sync_line_aft_6 = {0xff, 0xff},
 113                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 114                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 115                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 116                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 117                 .vact_space_1 = {0xff, 0xff},
 118                 .vact_space_2 = {0xff, 0xff},
 119                 .vact_space_3 = {0xff, 0xff},
 120                 .vact_space_4 = {0xff, 0xff},
 121                 .vact_space_5 = {0xff, 0xff},
 122                 .vact_space_6 = {0xff, 0xff},
 123                 /* other don't care */
 124         },
 125         .tg = {
 126                 0x00, /* cmd */
 127                 0x72, 0x06, /* h_fsz */
 128                 0x72, 0x01, 0x00, 0x05, /* hact */
 129                 0xee, 0x02, /* v_fsz */
 130                 0x01, 0x00, 0x33, 0x02, /* vsync */
 131                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 132                 0x33, 0x02, /* field_chg */
 133                 0x48, 0x02, /* vact_st2 */
 134                 0x00, 0x00, /* vact_st3 */
 135                 0x00, 0x00, /* vact_st4 */
 136                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 137                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 138                 0x00, /* 3d FP */
 139         },
 140         .mbus_fmt = {
 141                 .width = 1280,
 142                 .height = 720,
 143                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 144                 .field = V4L2_FIELD_NONE,
 145         },
 146 };
 147
 148 static const struct hdmi_preset_conf hdmi_conf_1080i60 = {
 149         .core = {
 150                 .h_blank = {0x18, 0x01},
 151                 .v2_blank = {0x32, 0x02},
 152                 .v1_blank = {0x16, 0x00},
 153                 .v_line = {0x65, 0x04},
 154                 .h_line = {0x98, 0x08},
 155                 .hsync_pol = {0x00},
 156                 .vsync_pol = {0x00},
 157                 .int_pro_mode = {0x01},
 158                 .v_blank_f0 = {0x49, 0x02},
 159                 .v_blank_f1 = {0x65, 0x04},
 160                 .h_sync_start = {0x56, 0x00},
 161                 .h_sync_end = {0x82, 0x00},
 162                 .v_sync_line_bef_2 = {0x07, 0x00},
 163                 .v_sync_line_bef_1 = {0x02, 0x00},
 164                 .v_sync_line_aft_2 = {0x39, 0x02},
 165                 .v_sync_line_aft_1 = {0x34, 0x02},
 166                 .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
 167                 .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
 168                 .v_blank_f2 = {0xff, 0xff},
 169                 .v_blank_f3 = {0xff, 0xff},
 170                 .v_blank_f4 = {0xff, 0xff},
 171                 .v_blank_f5 = {0xff, 0xff},
 172                 .v_sync_line_aft_3 = {0xff, 0xff},
 173                 .v_sync_line_aft_4 = {0xff, 0xff},
 174                 .v_sync_line_aft_5 = {0xff, 0xff},
 175                 .v_sync_line_aft_6 = {0xff, 0xff},
 176                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 177                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 178                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 179                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 180                 .vact_space_1 = {0xff, 0xff},
 181                 .vact_space_2 = {0xff, 0xff},
 182                 .vact_space_3 = {0xff, 0xff},
 183                 .vact_space_4 = {0xff, 0xff},
 184                 .vact_space_5 = {0xff, 0xff},
 185                 .vact_space_6 = {0xff, 0xff},
 186                 /* other don't care */
 187         },
 188         .tg = {
 189                 0x00, /* cmd */
 190                 0x98, 0x08, /* h_fsz */
 191                 0x18, 0x01, 0x80, 0x07, /* hact */
 192                 0x65, 0x04, /* v_fsz */
 193                 0x01, 0x00, 0x33, 0x02, /* vsync */
 194                 0x16, 0x00, 0x1c, 0x02, /* vact */
 195                 0x33, 0x02, /* field_chg */
 196                 0x49, 0x02, /* vact_st2 */
 197                 0x00, 0x00, /* vact_st3 */
 198                 0x00, 0x00, /* vact_st4 */
 199                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 200                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 201                 0x00, /* 3d FP */
 202         },
 203         .mbus_fmt = {
 204                 .width = 1920,
 205                 .height = 1080,
 206                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 207                 .field = V4L2_FIELD_NONE,
 208         },
 209 };
 210
 211 static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
 212         .core = {
 213                 .h_blank = {0x18, 0x01},
 214                 .v2_blank = {0x65, 0x04},
 215                 .v1_blank = {0x2d, 0x00},
 216                 .v_line = {0x65, 0x04},
 217                 .h_line = {0x98, 0x08},
 218                 .hsync_pol = {0x00},
 219                 .vsync_pol = {0x00},
 220                 .int_pro_mode = {0x00},
 221                 .v_blank_f0 = {0xff, 0xff},
 222                 .v_blank_f1 = {0xff, 0xff},
 223                 .h_sync_start = {0x56, 0x00},
 224                 .h_sync_end = {0x82, 0x00},
 225                 .v_sync_line_bef_2 = {0x09, 0x00},
 226                 .v_sync_line_bef_1 = {0x04, 0x00},
 227                 .v_sync_line_aft_2 = {0xff, 0xff},
 228                 .v_sync_line_aft_1 = {0xff, 0xff},
 229                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 230                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 231                 .v_blank_f2 = {0xff, 0xff},
 232                 .v_blank_f3 = {0xff, 0xff},
 233                 .v_blank_f4 = {0xff, 0xff},
 234                 .v_blank_f5 = {0xff, 0xff},
 235                 .v_sync_line_aft_3 = {0xff, 0xff},
 236                 .v_sync_line_aft_4 = {0xff, 0xff},
 237                 .v_sync_line_aft_5 = {0xff, 0xff},
 238                 .v_sync_line_aft_6 = {0xff, 0xff},
 239                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 240                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 241                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 242                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 243                 /* other don't care */
 244         },
 245         .tg = {
 246                 0x00, /* cmd */
 247                 0x98, 0x08, /* h_fsz */
 248                 0x18, 0x01, 0x80, 0x07, /* hact */
 249                 0x65, 0x04, /* v_fsz */
 250                 0x01, 0x00, 0x33, 0x02, /* vsync */
 251                 0x2d, 0x00, 0x38, 0x04, /* vact */
 252                 0x33, 0x02, /* field_chg */
 253                 0x48, 0x02, /* vact_st2 */
 254                 0x00, 0x00, /* vact_st3 */
 255                 0x00, 0x00, /* vact_st4 */
 256                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 257                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 258                 0x00, /* 3d FP */
 259         },
 260         .mbus_fmt = {
 261                 .width = 1920,
 262                 .height = 1080,
 263                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 264                 .field = V4L2_FIELD_NONE,
 265         },
 266 };
 267
 268 static const struct hdmi_preset_conf hdmi_conf_576p50 = {
 269         .core = {
 270                 .h_blank = {0x90, 0x00},
 271                 .v2_blank = {0x71, 0x02},
 272                 .v1_blank = {0x31, 0x00},
 273                 .v_line = {0x71, 0x02},
 274                 .h_line = {0x60, 0x03},
 275                 .hsync_pol = {0x01},
 276                 .vsync_pol = {0x01},
 277                 .int_pro_mode = {0x00},
 278                 .v_blank_f0 = {0xff, 0xff},
 279                 .v_blank_f1 = {0xff, 0xff},
 280                 .h_sync_start = {0x0a, 0x00},
 281                 .h_sync_end = {0x4a, 0x00},
 282                 .v_sync_line_bef_2 = {0x0a, 0x00},
 283                 .v_sync_line_bef_1 = {0x05, 0x00},
 284                 .v_sync_line_aft_2 = {0xff, 0xff},
 285                 .v_sync_line_aft_1 = {0xff, 0xff},
 286                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 287                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 288                 .v_blank_f2 = {0xff, 0xff},
 289                 .v_blank_f3 = {0xff, 0xff},
 290                 .v_blank_f4 = {0xff, 0xff},
 291                 .v_blank_f5 = {0xff, 0xff},
 292                 .v_sync_line_aft_3 = {0xff, 0xff},
 293                 .v_sync_line_aft_4 = {0xff, 0xff},
 294                 .v_sync_line_aft_5 = {0xff, 0xff},
 295                 .v_sync_line_aft_6 = {0xff, 0xff},
 296                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 297                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 298                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 299                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 300                 /* other don't care */
 301         },
 302         .tg = {
 303                 0x00, /* cmd */
 304                 0x60, 0x03, /* h_fsz */
 305                 0x90, 0x00, 0xd0, 0x02, /* hact */
 306                 0x71, 0x02, /* v_fsz */
 307                 0x01, 0x00, 0x33, 0x02, /* vsync */
 308                 0x31, 0x00, 0x40, 0x02, /* vact */
 309                 0x33, 0x02, /* field_chg */
 310                 0x48, 0x02, /* vact_st2 */
 311                 0x00, 0x00, /* vact_st3 */
 312                 0x00, 0x00, /* vact_st4 */
 313                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 314                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 315                 0x00, /* 3d FP */
 316         },
 317         .mbus_fmt = {
 318                 .width = 720,
 319                 .height = 576,
 320                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 321                 .field = V4L2_FIELD_NONE,
 322         },
 323 };
 324
 325 static const struct hdmi_preset_conf hdmi_conf_720p50 = {
 326         .core = {
 327                 .h_blank = {0xbc, 0x02},
 328                 .v2_blank = {0xee, 0x02},
 329                 .v1_blank = {0x1e, 0x00},
 330                 .v_line = {0xee, 0x02},
 331                 .h_line = {0xbc, 0x07},
 332                 .hsync_pol = {0x00},
 333                 .vsync_pol = {0x00},
 334                 .int_pro_mode = {0x00},
 335                 .v_blank_f0 = {0xff, 0xff},
 336                 .v_blank_f1 = {0xff, 0xff},
 337                 .h_sync_start = {0xb6, 0x01},
 338                 .h_sync_end = {0xde, 0x01},
 339                 .v_sync_line_bef_2 = {0x0a, 0x00},
 340                 .v_sync_line_bef_1 = {0x05, 0x00},
 341                 .v_sync_line_aft_2 = {0xff, 0xff},
 342                 .v_sync_line_aft_1 = {0xff, 0xff},
 343                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 344                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 345                 .v_blank_f2 = {0xff, 0xff},
 346                 .v_blank_f3 = {0xff, 0xff},
 347                 .v_blank_f4 = {0xff, 0xff},
 348                 .v_blank_f5 = {0xff, 0xff},
 349                 .v_sync_line_aft_3 = {0xff, 0xff},
 350                 .v_sync_line_aft_4 = {0xff, 0xff},
 351                 .v_sync_line_aft_5 = {0xff, 0xff},
 352                 .v_sync_line_aft_6 = {0xff, 0xff},
 353                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 354                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 355                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 356                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 357                 .vact_space_1 = {0xff, 0xff},
 358                 .vact_space_2 = {0xff, 0xff},
 359                 .vact_space_3 = {0xff, 0xff},
 360                 .vact_space_4 = {0xff, 0xff},
 361                 .vact_space_5 = {0xff, 0xff},
 362                 .vact_space_6 = {0xff, 0xff},
 363                 /* other don't care */
 364         },
 365         .tg = {
 366                 0x00, /* cmd */
 367                 0xbc, 0x07, /* h_fsz */
 368                 0xbc, 0x02, 0x00, 0x05, /* hact */
 369                 0xee, 0x02, /* v_fsz */
 370                 0x01, 0x00, 0x33, 0x02, /* vsync */
 371                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 372                 0x33, 0x02, /* field_chg */
 373                 0x48, 0x02, /* vact_st2 */
 374                 0x00, 0x00, /* vact_st3 */
 375                 0x00, 0x00, /* vact_st4 */
 376                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 377                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 378                 0x00, /* 3d FP */
 379         },
 380         .mbus_fmt = {
 381                 .width = 1280,
 382                 .height = 720,
 383                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 384                 .field = V4L2_FIELD_NONE,
 385         },
 386 };
 387
 388 static const struct hdmi_preset_conf hdmi_conf_1080i50 = {
 389         .core = {
 390                 .h_blank = {0xd0, 0x02},
 391                 .v2_blank = {0x32, 0x02},
 392                 .v1_blank = {0x16, 0x00},
 393                 .v_line = {0x65, 0x04},
 394                 .h_line = {0x50, 0x0a},
 395                 .hsync_pol = {0x00},
 396                 .vsync_pol = {0x00},
 397                 .int_pro_mode = {0x01},
 398                 .v_blank_f0 = {0x49, 0x02},
 399                 .v_blank_f1 = {0x65, 0x04},
 400                 .h_sync_start = {0x0e, 0x02},
 401                 .h_sync_end = {0x3a, 0x02},
 402                 .v_sync_line_bef_2 = {0x07, 0x00},
 403                 .v_sync_line_bef_1 = {0x02, 0x00},
 404                 .v_sync_line_aft_2 = {0x39, 0x02},
 405                 .v_sync_line_aft_1 = {0x34, 0x02},
 406                 .v_sync_line_aft_pxl_2 = {0x38, 0x07},
 407                 .v_sync_line_aft_pxl_1 = {0x38, 0x07},
 408                 .v_blank_f2 = {0xff, 0xff},
 409                 .v_blank_f3 = {0xff, 0xff},
 410                 .v_blank_f4 = {0xff, 0xff},
 411                 .v_blank_f5 = {0xff, 0xff},
 412                 .v_sync_line_aft_3 = {0xff, 0xff},
 413                 .v_sync_line_aft_4 = {0xff, 0xff},
 414                 .v_sync_line_aft_5 = {0xff, 0xff},
 415                 .v_sync_line_aft_6 = {0xff, 0xff},
 416                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 417                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 418                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 419                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 420                 .vact_space_1 = {0xff, 0xff},
 421                 .vact_space_2 = {0xff, 0xff},
 422                 .vact_space_3 = {0xff, 0xff},
 423                 .vact_space_4 = {0xff, 0xff},
 424                 .vact_space_5 = {0xff, 0xff},
 425                 .vact_space_6 = {0xff, 0xff},
 426                 /* other don't care */
 427         },
 428         .tg = {
 429                 0x00, /* cmd */
 430                 0x50, 0x0a, /* h_fsz */
 431                 0xd0, 0x02, 0x80, 0x07, /* hact */
 432                 0x65, 0x04, /* v_fsz */
 433                 0x01, 0x00, 0x33, 0x02, /* vsync */
 434                 0x16, 0x00, 0x1c, 0x02, /* vact */
 435                 0x33, 0x02, /* field_chg */
 436                 0x49, 0x02, /* vact_st2 */
 437                 0x00, 0x00, /* vact_st3 */
 438                 0x00, 0x00, /* vact_st4 */
 439                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 440                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 441                 0x00, /* 3d FP */
 442         },
 443         .mbus_fmt = {
 444                 .width = 1920,
 445                 .height = 1080,
 446                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 447                 .field = V4L2_FIELD_NONE,
 448         },
 449 };
 450
 451 static const struct hdmi_preset_conf hdmi_conf_1080p50 = {
 452         .core = {
 453                 .h_blank = {0xd0, 0x02},
 454                 .v2_blank = {0x65, 0x04},
 455                 .v1_blank = {0x2d, 0x00},
 456                 .v_line = {0x65, 0x04},
 457                 .h_line = {0x50, 0x0a},
 458                 .hsync_pol = {0x00},
 459                 .vsync_pol = {0x00},
 460                 .int_pro_mode = {0x00},
 461                 .v_blank_f0 = {0xff, 0xff},
 462                 .v_blank_f1 = {0xff, 0xff},
 463                 .h_sync_start = {0x0e, 0x02},
 464                 .h_sync_end = {0x3a, 0x02},
 465                 .v_sync_line_bef_2 = {0x09, 0x00},
 466                 .v_sync_line_bef_1 = {0x04, 0x00},
 467                 .v_sync_line_aft_2 = {0xff, 0xff},
 468                 .v_sync_line_aft_1 = {0xff, 0xff},
 469                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 470                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 471                 .v_blank_f2 = {0xff, 0xff},
 472                 .v_blank_f3 = {0xff, 0xff},
 473                 .v_blank_f4 = {0xff, 0xff},
 474                 .v_blank_f5 = {0xff, 0xff},
 475                 .v_sync_line_aft_3 = {0xff, 0xff},
 476                 .v_sync_line_aft_4 = {0xff, 0xff},
 477                 .v_sync_line_aft_5 = {0xff, 0xff},
 478                 .v_sync_line_aft_6 = {0xff, 0xff},
 479                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 480                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 481                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 482                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 483                 .vact_space_1 = {0xff, 0xff},
 484                 .vact_space_2 = {0xff, 0xff},
 485                 .vact_space_3 = {0xff, 0xff},
 486                 .vact_space_4 = {0xff, 0xff},
 487                 .vact_space_5 = {0xff, 0xff},
 488                 .vact_space_6 = {0xff, 0xff},
 489                 /* other don't care */
 490         },
 491         .tg = {
 492                 0x00, /* cmd */
 493                 0x50, 0x0a, /* h_fsz */
 494                 0xd0, 0x02, 0x80, 0x07, /* hact */
 495                 0x65, 0x04, /* v_fsz */
 496                 0x01, 0x00, 0x33, 0x02, /* vsync */
 497                 0x2d, 0x00, 0x38, 0x04, /* vact */
 498                 0x33, 0x02, /* field_chg */
 499                 0x48, 0x02, /* vact_st2 */
 500                 0x00, 0x00, /* vact_st3 */
 501                 0x00, 0x00, /* vact_st4 */
 502                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 503                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 504                 0x00, /* 3d FP */
 505         },
 506         .mbus_fmt = {
 507                 .width = 1920,
 508                 .height = 1080,
 509                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 510                 .field = V4L2_FIELD_NONE,
 511         },
 512 };
 513
 514 static const struct hdmi_preset_conf hdmi_conf_1080p30 = {
 515         .core = {
 516                 .h_blank = {0x18, 0x01},
 517                 .v2_blank = {0x65, 0x04},
 518                 .v1_blank = {0x2d, 0x00},
 519                 .v_line = {0x65, 0x04},
 520                 .h_line = {0x98, 0x08},
 521                 .hsync_pol = {0x00},
 522                 .vsync_pol = {0x00},
 523                 .int_pro_mode = {0x00},
 524                 .v_blank_f0 = {0xff, 0xff},
 525                 .v_blank_f1 = {0xff, 0xff},
 526                 .h_sync_start = {0x56, 0x00},
 527                 .h_sync_end = {0x82, 0x00},
 528                 .v_sync_line_bef_2 = {0x09, 0x00},
 529                 .v_sync_line_bef_1 = {0x04, 0x00},
 530                 .v_sync_line_aft_2 = {0xff, 0xff},
 531                 .v_sync_line_aft_1 = {0xff, 0xff},
 532                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 533                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 534                 .v_blank_f2 = {0xff, 0xff},
 535                 .v_blank_f3 = {0xff, 0xff},
 536                 .v_blank_f4 = {0xff, 0xff},
 537                 .v_blank_f5 = {0xff, 0xff},
 538                 .v_sync_line_aft_3 = {0xff, 0xff},
 539                 .v_sync_line_aft_4 = {0xff, 0xff},
 540                 .v_sync_line_aft_5 = {0xff, 0xff},
 541                 .v_sync_line_aft_6 = {0xff, 0xff},
 542                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 543                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 544                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 545                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 546                 .vact_space_1 = {0xff, 0xff},
 547                 .vact_space_2 = {0xff, 0xff},
 548                 .vact_space_3 = {0xff, 0xff},
 549                 .vact_space_4 = {0xff, 0xff},
 550                 .vact_space_5 = {0xff, 0xff},
 551                 .vact_space_6 = {0xff, 0xff},
 552                 /* other don't care */
 553         },
 554         .tg = {
 555                 0x00, /* cmd */
 556                 0x98, 0x08, /* h_fsz */
 557                 0x18, 0x01, 0x80, 0x07, /* hact */
 558                 0x65, 0x04, /* v_fsz */
 559                 0x01, 0x00, 0x33, 0x02, /* vsync */
 560                 0x2d, 0x00, 0x38, 0x04, /* vact */
 561                 0x33, 0x02, /* field_chg */
 562                 0x48, 0x02, /* vact_st2 */
 563                 0x00, 0x00, /* vact_st3 */
 564                 0x00, 0x00, /* vact_st4 */
 565                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 566                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 567                 0x00, /* 3d FP */
 568         },
 569         .mbus_fmt = {
 570                 .width = 1920,
 571                 .height = 1080,
 572                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 573                 .field = V4L2_FIELD_NONE,
 574         },
 575 };
 576
 577 static const struct hdmi_preset_conf hdmi_conf_1080p24 = {
 578         .core = {
 579                 .h_blank = {0x3e, 0x03},
 580                 .v2_blank = {0x65, 0x04},
 581                 .v1_blank = {0x2d, 0x00},
 582                 .v_line = {0x65, 0x04},
 583                 .h_line = {0xbe, 0x0a},
 584                 .hsync_pol = {0x00},
 585                 .vsync_pol = {0x00},
 586                 .int_pro_mode = {0x00},
 587                 .v_blank_f0 = {0xff, 0xff},
 588                 .v_blank_f1 = {0xff, 0xff},
 589                 .h_sync_start = {0x7c, 0x02},
 590                 .h_sync_end = {0xa8, 0x02},
 591                 .v_sync_line_bef_2 = {0x09, 0x00},
 592                 .v_sync_line_bef_1 = {0x04, 0x00},
 593                 .v_sync_line_aft_2 = {0xff, 0xff},
 594                 .v_sync_line_aft_1 = {0xff, 0xff},
 595                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 596                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 597                 .v_blank_f2 = {0xff, 0xff},
 598                 .v_blank_f3 = {0xff, 0xff},
 599                 .v_blank_f4 = {0xff, 0xff},
 600                 .v_blank_f5 = {0xff, 0xff},
 601                 .v_sync_line_aft_3 = {0xff, 0xff},
 602                 .v_sync_line_aft_4 = {0xff, 0xff},
 603                 .v_sync_line_aft_5 = {0xff, 0xff},
 604                 .v_sync_line_aft_6 = {0xff, 0xff},
 605                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 606                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 607                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 608                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 609                 .vact_space_1 = {0xff, 0xff},
 610                 .vact_space_2 = {0xff, 0xff},
 611                 .vact_space_3 = {0xff, 0xff},
 612                 .vact_space_4 = {0xff, 0xff},
 613                 .vact_space_5 = {0xff, 0xff},
 614                 .vact_space_6 = {0xff, 0xff},
 615                 /* other don't care */
 616         },
 617         .tg = {
 618                 0x00, /* cmd */
 619                 0xbe, 0x0a, /* h_fsz */
 620                 0x3e, 0x03, 0x80, 0x07, /* hact */
 621                 0x65, 0x04, /* v_fsz */
 622                 0x01, 0x00, 0x33, 0x02, /* vsync */
 623                 0x2d, 0x00, 0x38, 0x04, /* vact */
 624                 0x33, 0x02, /* field_chg */
 625                 0x48, 0x02, /* vact_st2 */
 626                 0x00, 0x00, /* vact_st3 */
 627                 0x00, 0x00, /* vact_st4 */
 628                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 629                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 630                 0x00, /* 3d FP */
 631         },
 632         .mbus_fmt = {
 633                 .width = 1920,
 634                 .height = 1080,
 635                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 636                 .field = V4L2_FIELD_NONE,
 637         },
 638 };
 639
 640 static const struct hdmi_preset_conf hdmi_conf_1080p25 = {
 641         .core = {
 642                 .h_blank = {0xd0, 0x02},
 643                 .v2_blank = {0x65, 0x04},
 644                 .v1_blank = {0x2d, 0x00},
 645                 .v_line = {0x65, 0x04},
 646                 .h_line = {0x50, 0x0a},
 647                 .hsync_pol = {0x00},
 648                 .vsync_pol = {0x00},
 649                 .int_pro_mode = {0x00},
 650                 .v_blank_f0 = {0xff, 0xff},
 651                 .v_blank_f1 = {0xff, 0xff},
 652                 .h_sync_start = {0x0e, 0x02},
 653                 .h_sync_end = {0x3a, 0x02},
 654                 .v_sync_line_bef_2 = {0x09, 0x00},
 655                 .v_sync_line_bef_1 = {0x04, 0x00},
 656                 .v_sync_line_aft_2 = {0xff, 0xff},
 657                 .v_sync_line_aft_1 = {0xff, 0xff},
 658                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 659                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 660                 .v_blank_f2 = {0xff, 0xff},
 661                 .v_blank_f3 = {0xff, 0xff},
 662                 .v_blank_f4 = {0xff, 0xff},
 663                 .v_blank_f5 = {0xff, 0xff},
 664                 .v_sync_line_aft_3 = {0xff, 0xff},
 665                 .v_sync_line_aft_4 = {0xff, 0xff},
 666                 .v_sync_line_aft_5 = {0xff, 0xff},
 667                 .v_sync_line_aft_6 = {0xff, 0xff},
 668                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 669                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 670                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 671                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 672                 .vact_space_1 = {0xff, 0xff},
 673                 .vact_space_2 = {0xff, 0xff},
 674                 .vact_space_3 = {0xff, 0xff},
 675                 .vact_space_4 = {0xff, 0xff},
 676                 .vact_space_5 = {0xff, 0xff},
 677                 .vact_space_6 = {0xff, 0xff},
 678                 /* other don't care */
 679         },
 680         .tg = {
 681                 0x00, /* cmd */
 682                 0x50, 0x0a, /* h_fsz */
 683                 0xd0, 0x02, 0x80, 0x07, /* hact */
 684                 0x65, 0x04, /* v_fsz */
 685                 0x01, 0x00, 0x33, 0x02, /* vsync */
 686                 0x2d, 0x00, 0x38, 0x04, /* vact */
 687                 0x33, 0x02, /* field_chg */
 688                 0x48, 0x02, /* vact_st2 */
 689                 0x00, 0x00, /* vact_st3 */
 690                 0x00, 0x00, /* vact_st4 */
 691                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 692                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 693                 0x00, /* 3d FP */
 694         },
 695         .mbus_fmt = {
 696                 .width = 1920,
 697                 .height = 1080,
 698                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 699                 .field = V4L2_FIELD_NONE,
 700         },
 701 };
 702
 703 static const struct hdmi_preset_conf hdmi_conf_480p59_94 = {
 704         .core = {
 705                 .h_blank = {0x8a, 0x00},
 706                 .v2_blank = {0x0d, 0x02},
 707                 .v1_blank = {0x2d, 0x00},
 708                 .v_line = {0x0d, 0x02},
 709                 .h_line = {0x5a, 0x03},
 710                 .hsync_pol = {0x01},
 711                 .vsync_pol = {0x01},
 712                 .int_pro_mode = {0x00},
 713                 .v_blank_f0 = {0xff, 0xff},
 714                 .v_blank_f1 = {0xff, 0xff},
 715                 .h_sync_start = {0x0e, 0x00},
 716                 .h_sync_end = {0x4c, 0x00},
 717                 .v_sync_line_bef_2 = {0x0f, 0x00},
 718                 .v_sync_line_bef_1 = {0x09, 0x00},
 719                 .v_sync_line_aft_2 = {0xff, 0xff},
 720                 .v_sync_line_aft_1 = {0xff, 0xff},
 721                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 722                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 723                 .v_blank_f2 = {0xff, 0xff},
 724                 .v_blank_f3 = {0xff, 0xff},
 725                 .v_blank_f4 = {0xff, 0xff},
 726                 .v_blank_f5 = {0xff, 0xff},
 727                 .v_sync_line_aft_3 = {0xff, 0xff},
 728                 .v_sync_line_aft_4 = {0xff, 0xff},
 729                 .v_sync_line_aft_5 = {0xff, 0xff},
 730                 .v_sync_line_aft_6 = {0xff, 0xff},
 731                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 732                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 733                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 734                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 735                 .vact_space_1 = {0xff, 0xff},
 736                 .vact_space_2 = {0xff, 0xff},
 737                 .vact_space_3 = {0xff, 0xff},
 738                 .vact_space_4 = {0xff, 0xff},
 739                 .vact_space_5 = {0xff, 0xff},
 740                 .vact_space_6 = {0xff, 0xff},
 741                 /* other don't care */
 742         },
 743         .tg = {
 744                 0x00, /* cmd */
 745                 0x5a, 0x03, /* h_fsz */
 746                 0x8a, 0x00, 0xd0, 0x02, /* hact */
 747                 0x0d, 0x02, /* v_fsz */
 748                 0x01, 0x00, 0x33, 0x02, /* vsync */
 749                 0x2d, 0x00, 0xe0, 0x01, /* vact */
 750                 0x33, 0x02, /* field_chg */
 751                 0x48, 0x02, /* vact_st2 */
 752                 0x00, 0x00, /* vact_st3 */
 753                 0x00, 0x00, /* vact_st4 */
 754                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 755                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 756                 0x00, /* 3d FP */
 757         },
 758         .mbus_fmt = {
 759                 .width = 720,
 760                 .height = 480,
 761                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 762                 .field = V4L2_FIELD_NONE,
 763         },
 764 };
 765
 766 static const struct hdmi_preset_conf hdmi_conf_720p59_94 = {
 767         .core = {
 768                 .h_blank = {0x72, 0x01},
 769                 .v2_blank = {0xee, 0x02},
 770                 .v1_blank = {0x1e, 0x00},
 771                 .v_line = {0xee, 0x02},
 772                 .h_line = {0x72, 0x06},
 773                 .hsync_pol = {0x00},
 774                 .vsync_pol = {0x00},
 775                 .int_pro_mode = {0x00},
 776                 .v_blank_f0 = {0xff, 0xff},
 777                 .v_blank_f1 = {0xff, 0xff},
 778                 .h_sync_start = {0x6c, 0x00},
 779                 .h_sync_end = {0x94, 0x00},
 780                 .v_sync_line_bef_2 = {0x0a, 0x00},
 781                 .v_sync_line_bef_1 = {0x05, 0x00},
 782                 .v_sync_line_aft_2 = {0xff, 0xff},
 783                 .v_sync_line_aft_1 = {0xff, 0xff},
 784                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 785                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 786                 .v_blank_f2 = {0xff, 0xff},
 787                 .v_blank_f3 = {0xff, 0xff},
 788                 .v_blank_f4 = {0xff, 0xff},
 789                 .v_blank_f5 = {0xff, 0xff},
 790                 .v_sync_line_aft_3 = {0xff, 0xff},
 791                 .v_sync_line_aft_4 = {0xff, 0xff},
 792                 .v_sync_line_aft_5 = {0xff, 0xff},
 793                 .v_sync_line_aft_6 = {0xff, 0xff},
 794                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 795                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 796                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 797                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 798                 .vact_space_1 = {0xff, 0xff},
 799                 .vact_space_2 = {0xff, 0xff},
 800                 .vact_space_3 = {0xff, 0xff},
 801                 .vact_space_4 = {0xff, 0xff},
 802                 .vact_space_5 = {0xff, 0xff},
 803                 .vact_space_6 = {0xff, 0xff},
 804                 /* other don't care */
 805         },
 806         .tg = {
 807                 0x00, /* cmd */
 808                 0x72, 0x06, /* h_fsz */
 809                 0x72, 0x01, 0x00, 0x05, /* hact */
 810                 0xee, 0x02, /* v_fsz */
 811                 0x01, 0x00, 0x33, 0x02, /* vsync */
 812                 0x1e, 0x00, 0xd0, 0x02, /* vact */
 813                 0x33, 0x02, /* field_chg */
 814                 0x48, 0x02, /* vact_st2 */
 815                 0x00, 0x00, /* vact_st3 */
 816                 0x00, 0x00, /* vact_st4 */
 817                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 818                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 819                 0x00, /* 3d FP */
 820         },
 821         .mbus_fmt = {
 822                 .width = 1280,
 823                 .height = 720,
 824                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 825                 .field = V4L2_FIELD_NONE,
 826         },
 827 };
 828
 829 static const struct hdmi_preset_conf hdmi_conf_1080i59_94 = {
 830         .core = {
 831                 .h_blank = {0x18, 0x01},
 832                 .v2_blank = {0x32, 0x02},
 833                 .v1_blank = {0x16, 0x00},
 834                 .v_line = {0x65, 0x04},
 835                 .h_line = {0x98, 0x08},
 836                 .hsync_pol = {0x00},
 837                 .vsync_pol = {0x00},
 838                 .int_pro_mode = {0x01},
 839                 .v_blank_f0 = {0x49, 0x02},
 840                 .v_blank_f1 = {0x65, 0x04},
 841                 .h_sync_start = {0x56, 0x00},
 842                 .h_sync_end = {0x82, 0x00},
 843                 .v_sync_line_bef_2 = {0x07, 0x00},
 844                 .v_sync_line_bef_1 = {0x02, 0x00},
 845                 .v_sync_line_aft_2 = {0x39, 0x02},
 846                 .v_sync_line_aft_1 = {0x34, 0x02},
 847                 .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
 848                 .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
 849                 .v_blank_f2 = {0xff, 0xff},
 850                 .v_blank_f3 = {0xff, 0xff},
 851                 .v_blank_f4 = {0xff, 0xff},
 852                 .v_blank_f5 = {0xff, 0xff},
 853                 .v_sync_line_aft_3 = {0xff, 0xff},
 854                 .v_sync_line_aft_4 = {0xff, 0xff},
 855                 .v_sync_line_aft_5 = {0xff, 0xff},
 856                 .v_sync_line_aft_6 = {0xff, 0xff},
 857                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 858                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 859                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 860                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 861                 .vact_space_1 = {0xff, 0xff},
 862                 .vact_space_2 = {0xff, 0xff},
 863                 .vact_space_3 = {0xff, 0xff},
 864                 .vact_space_4 = {0xff, 0xff},
 865                 .vact_space_5 = {0xff, 0xff},
 866                 .vact_space_6 = {0xff, 0xff},
 867                 /* other don't care */
 868         },
 869         .tg = {
 870                 0x00, /* cmd */
 871                 0x98, 0x08, /* h_fsz */
 872                 0x18, 0x01, 0x80, 0x07, /* hact */
 873                 0x65, 0x04, /* v_fsz */
 874                 0x01, 0x00, 0x33, 0x02, /* vsync */
 875                 0x16, 0x00, 0x1c, 0x02, /* vact */
 876                 0x33, 0x02, /* field_chg */
 877                 0x49, 0x02, /* vact_st2 */
 878                 0x00, 0x00, /* vact_st3 */
 879                 0x00, 0x00, /* vact_st4 */
 880                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
 881                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 882                 0x00, /* 3d FP */
 883         },
 884         .mbus_fmt = {
 885                 .width = 1920,
 886                 .height = 1080,
 887                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 888                 .field = V4L2_FIELD_NONE,
 889         },
 890 };
 891
 892 static const struct hdmi_preset_conf hdmi_conf_1080p59_94 = {
 893         .core = {
 894                 .h_blank = {0x18, 0x01},
 895                 .v2_blank = {0x65, 0x04},
 896                 .v1_blank = {0x2d, 0x00},
 897                 .v_line = {0x65, 0x04},
 898                 .h_line = {0x98, 0x08},
 899                 .hsync_pol = {0x00},
 900                 .vsync_pol = {0x00},
 901                 .int_pro_mode = {0x00},
 902                 .v_blank_f0 = {0xff, 0xff},
 903                 .v_blank_f1 = {0xff, 0xff},
 904                 .h_sync_start = {0x56, 0x00},
 905                 .h_sync_end = {0x82, 0x00},
 906                 .v_sync_line_bef_2 = {0x09, 0x00},
 907                 .v_sync_line_bef_1 = {0x04, 0x00},
 908                 .v_sync_line_aft_2 = {0xff, 0xff},
 909                 .v_sync_line_aft_1 = {0xff, 0xff},
 910                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 911                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 912                 .v_blank_f2 = {0xff, 0xff},
 913                 .v_blank_f3 = {0xff, 0xff},
 914                 .v_blank_f4 = {0xff, 0xff},
 915                 .v_blank_f5 = {0xff, 0xff},
 916                 .v_sync_line_aft_3 = {0xff, 0xff},
 917                 .v_sync_line_aft_4 = {0xff, 0xff},
 918                 .v_sync_line_aft_5 = {0xff, 0xff},
 919                 .v_sync_line_aft_6 = {0xff, 0xff},
 920                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 921                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 922                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 923                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 924                 .vact_space_1 = {0xff, 0xff},
 925                 .vact_space_2 = {0xff, 0xff},
 926                 .vact_space_3 = {0xff, 0xff},
 927                 .vact_space_4 = {0xff, 0xff},
 928                 .vact_space_5 = {0xff, 0xff},
 929                 .vact_space_6 = {0xff, 0xff},
 930                 /* other don't care */
 931         },
 932         .tg = {
 933                 0x00, /* cmd */
 934                 0x98, 0x08, /* h_fsz */
 935                 0x18, 0x01, 0x80, 0x07, /* hact */
 936                 0x65, 0x04, /* v_fsz */
 937                 0x01, 0x00, 0x33, 0x02, /* vsync */
 938                 0x2d, 0x00, 0x38, 0x04, /* vact */
 939                 0x33, 0x02, /* field_chg */
 940                 0x48, 0x02, /* vact_st2 */
 941                 0x00, 0x00, /* vact_st3 */
 942                 0x00, 0x00, /* vact_st4 */
 943                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
 944                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
 945                 0x00, /* 3d FP */
 946         },
 947         .mbus_fmt = {
 948                 .width = 1920,
 949                 .height = 1080,
 950                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
 951                 .field = V4L2_FIELD_NONE,
 952         },
 953 };
 954
 955 static const struct hdmi_preset_conf hdmi_conf_720p60_sb_half = {
 956         .core = {
 957                 .h_blank = {0x72, 0x01},
 958                 .v2_blank = {0xee, 0x02},
 959                 .v1_blank = {0x1e, 0x00},
 960                 .v_line = {0xee, 0x02},
 961                 .h_line = {0x72, 0x06},
 962                 .hsync_pol = {0x00},
 963                 .vsync_pol = {0x00},
 964                 .int_pro_mode = {0x00},
 965                 .v_blank_f0 = {0xff, 0xff},
 966                 .v_blank_f1 = {0xff, 0xff},
 967                 .h_sync_start = {0x6c, 0x00},
 968                 .h_sync_end = {0x94, 0x00},
 969                 .v_sync_line_bef_2 = {0x0a, 0x00},
 970                 .v_sync_line_bef_1 = {0x05, 0x00},
 971                 .v_sync_line_aft_2 = {0xff, 0xff},
 972                 .v_sync_line_aft_1 = {0xff, 0xff},
 973                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
 974                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
 975                 .v_blank_f2 = {0xff, 0xff},
 976                 .v_blank_f3 = {0xff, 0xff},
 977                 .v_blank_f4 = {0xff, 0xff},
 978                 .v_blank_f5 = {0xff, 0xff},
 979                 .v_sync_line_aft_3 = {0xff, 0xff},
 980                 .v_sync_line_aft_4 = {0xff, 0xff},
 981                 .v_sync_line_aft_5 = {0xff, 0xff},
 982                 .v_sync_line_aft_6 = {0xff, 0xff},
 983                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
 984                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
 985                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
 986                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
 987                 .vact_space_1 = {0xff, 0xff},
 988                 .vact_space_2 = {0xff, 0xff},
 989                 .vact_space_3 = {0xff, 0xff},
 990                 .vact_space_4 = {0xff, 0xff},
 991                 .vact_space_5 = {0xff, 0xff},
 992                 .vact_space_6 = {0xff, 0xff},
 993                 /* other don't care */
 994         },
 995         .tg = {
 996                 0x00, /* cmd */
 997                 0x72, 0x06, /* h_fsz */
 998                 0x72, 0x01, 0x00, 0x05, /* hact */
 999                 0xee, 0x02, /* v_fsz */
1000                 0x01, 0x00, 0x33, 0x02, /* vsync */
1001                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1002                 0x33, 0x02, /* field_chg */
1003                 0x0c, 0x03, /* vact_st2 */
1004                 0x00, 0x00, /* vact_st3 */
1005                 0x00, 0x00, /* vact_st4 */
1006                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1007                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1008                 0x00, /* 3d FP */
1009         },
1010         .mbus_fmt = {
1011                 .width = 1280,
1012                 .height = 720,
1013                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1014                 .field = V4L2_FIELD_NONE,
1015         },
1016 };
1017
1018 static const struct hdmi_preset_conf hdmi_conf_720p60_tb = {
1019         .core = {
1020                 .h_blank = {0x72, 0x01},
1021                 .v2_blank = {0xee, 0x02},
1022                 .v1_blank = {0x1e, 0x00},
1023                 .v_line = {0xee, 0x02},
1024                 .h_line = {0x72, 0x06},
1025                 .hsync_pol = {0x00},
1026                 .vsync_pol = {0x00},
1027                 .int_pro_mode = {0x00},
1028                 .v_blank_f0 = {0xff, 0xff},
1029                 .v_blank_f1 = {0xff, 0xff},
1030                 .h_sync_start = {0x6c, 0x00},
1031                 .h_sync_end = {0x94, 0x00},
1032                 .v_sync_line_bef_2 = {0x0a, 0x00},
1033                 .v_sync_line_bef_1 = {0x05, 0x00},
1034                 .v_sync_line_aft_2 = {0xff, 0xff},
1035                 .v_sync_line_aft_1 = {0xff, 0xff},
1036                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1037                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1038                 .v_blank_f2 = {0xff, 0xff},
1039                 .v_blank_f3 = {0xff, 0xff},
1040                 .v_blank_f4 = {0xff, 0xff},
1041                 .v_blank_f5 = {0xff, 0xff},
1042                 .v_sync_line_aft_3 = {0xff, 0xff},
1043                 .v_sync_line_aft_4 = {0xff, 0xff},
1044                 .v_sync_line_aft_5 = {0xff, 0xff},
1045                 .v_sync_line_aft_6 = {0xff, 0xff},
1046                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1047                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1048                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1049                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1050                 .vact_space_1 = {0xff, 0xff},
1051                 .vact_space_2 = {0xff, 0xff},
1052                 .vact_space_3 = {0xff, 0xff},
1053                 .vact_space_4 = {0xff, 0xff},
1054                 .vact_space_5 = {0xff, 0xff},
1055                 .vact_space_6 = {0xff, 0xff},
1056                 /* other don't care */
1057         },
1058         .tg = {
1059                 0x00, /* cmd */
1060                 0x72, 0x06, /* h_fsz */
1061                 0x72, 0x01, 0x00, 0x05, /* hact */
1062                 0xee, 0x02, /* v_fsz */
1063                 0x01, 0x00, 0x33, 0x02, /* vsync */
1064                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1065                 0x33, 0x02, /* field_chg */
1066                 0x0c, 0x03, /* vact_st2 */
1067                 0x00, 0x00, /* vact_st3 */
1068                 0x00, 0x00, /* vact_st4 */
1069                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1070                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1071                 0x00, /* 3d FP */
1072         },
1073         .mbus_fmt = {
1074                 .width = 1280,
1075                 .height = 720,
1076                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1077                 .field = V4L2_FIELD_NONE,
1078         },
1079 };
1080
1081 static const struct hdmi_preset_conf hdmi_conf_720p59_94_sb_half = {
1082         .core = {
1083                 .h_blank = {0x72, 0x01},
1084                 .v2_blank = {0xee, 0x02},
1085                 .v1_blank = {0x1e, 0x00},
1086                 .v_line = {0xee, 0x02},
1087                 .h_line = {0x72, 0x06},
1088                 .hsync_pol = {0x00},
1089                 .vsync_pol = {0x00},
1090                 .int_pro_mode = {0x00},
1091                 .v_blank_f0 = {0xff, 0xff},
1092                 .v_blank_f1 = {0xff, 0xff},
1093                 .h_sync_start = {0x6c, 0x00},
1094                 .h_sync_end = {0x94, 0x00},
1095                 .v_sync_line_bef_2 = {0x0a, 0x00},
1096                 .v_sync_line_bef_1 = {0x05, 0x00},
1097                 .v_sync_line_aft_2 = {0xff, 0xff},
1098                 .v_sync_line_aft_1 = {0xff, 0xff},
1099                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1100                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1101                 .v_blank_f2 = {0xff, 0xff},
1102                 .v_blank_f3 = {0xff, 0xff},
1103                 .v_blank_f4 = {0xff, 0xff},
1104                 .v_blank_f5 = {0xff, 0xff},
1105                 .v_sync_line_aft_3 = {0xff, 0xff},
1106                 .v_sync_line_aft_4 = {0xff, 0xff},
1107                 .v_sync_line_aft_5 = {0xff, 0xff},
1108                 .v_sync_line_aft_6 = {0xff, 0xff},
1109                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1110                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1111                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1112                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1113                 .vact_space_1 = {0xff, 0xff},
1114                 .vact_space_2 = {0xff, 0xff},
1115                 .vact_space_3 = {0xff, 0xff},
1116                 .vact_space_4 = {0xff, 0xff},
1117                 .vact_space_5 = {0xff, 0xff},
1118                 .vact_space_6 = {0xff, 0xff},
1119                 /* other don't care */
1120         },
1121         .tg = {
1122                 0x00, /* cmd */
1123                 0x72, 0x06, /* h_fsz */
1124                 0x72, 0x01, 0x00, 0x05, /* hact */
1125                 0xee, 0x02, /* v_fsz */
1126                 0x01, 0x00, 0x33, 0x02, /* vsync */
1127                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1128                 0x00, 0x00, /* field_chg */
1129                 0x0c, 0x03, /* vact_st2 */
1130                 0x00, 0x00, /* vact_st3 */
1131                 0x00, 0x00, /* vact_st4 */
1132                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1133                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1134                 0x00, /* 3d FP */
1135         },
1136         .mbus_fmt = {
1137                 .width = 1280,
1138                 .height = 720,
1139                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1140                 .field = V4L2_FIELD_NONE,
1141         },
1142 };
1143
1144 static const struct hdmi_preset_conf hdmi_conf_720p59_94_tb = {
1145         .core = {
1146                 .h_blank = {0x72, 0x01},
1147                 .v2_blank = {0xee, 0x02},
1148                 .v1_blank = {0x1e, 0x00},
1149                 .v_line = {0xee, 0x02},
1150                 .h_line = {0x72, 0x06},
1151                 .hsync_pol = {0x00},
1152                 .vsync_pol = {0x00},
1153                 .int_pro_mode = {0x00},
1154                 .v_blank_f0 = {0xff, 0xff},
1155                 .v_blank_f1 = {0xff, 0xff},
1156                 .h_sync_start = {0x6c, 0x00},
1157                 .h_sync_end = {0x94, 0x00},
1158                 .v_sync_line_bef_2 = {0x0a, 0x00},
1159                 .v_sync_line_bef_1 = {0x05, 0x00},
1160                 .v_sync_line_aft_2 = {0xff, 0xff},
1161                 .v_sync_line_aft_1 = {0xff, 0xff},
1162                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1163                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1164                 .v_blank_f2 = {0xff, 0xff},
1165                 .v_blank_f3 = {0xff, 0xff},
1166                 .v_blank_f4 = {0xff, 0xff},
1167                 .v_blank_f5 = {0xff, 0xff},
1168                 .v_sync_line_aft_3 = {0xff, 0xff},
1169                 .v_sync_line_aft_4 = {0xff, 0xff},
1170                 .v_sync_line_aft_5 = {0xff, 0xff},
1171                 .v_sync_line_aft_6 = {0xff, 0xff},
1172                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1173                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1174                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1175                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1176                 .vact_space_1 = {0xff, 0xff},
1177                 .vact_space_2 = {0xff, 0xff},
1178                 .vact_space_3 = {0xff, 0xff},
1179                 .vact_space_4 = {0xff, 0xff},
1180                 .vact_space_5 = {0xff, 0xff},
1181                 .vact_space_6 = {0xff, 0xff},
1182                 /* other don't care */
1183         },
1184         .tg = {
1185                 0x00, /* cmd */
1186                 0x72, 0x06, /* h_fsz */
1187                 0x72, 0x01, 0x00, 0x05, /* hact */
1188                 0xee, 0x02, /* v_fsz */
1189                 0x01, 0x00, 0x33, 0x02, /* vsync */
1190                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1191                 0x00, 0x00, /* field_chg */
1192                 0x0c, 0x03, /* vact_st2 */
1193                 0x00, 0x00, /* vact_st3 */
1194                 0x00, 0x00, /* vact_st4 */
1195                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1196                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1197                 0x00, /* 3d FP */
1198         },
1199         .mbus_fmt = {
1200                 .width = 1280,
1201                 .height = 720,
1202                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1203                 .field = V4L2_FIELD_NONE,
1204         },
1205 };
1206
1207 static const struct hdmi_preset_conf hdmi_conf_720p50_sb_half = {
1208         .core = {
1209                 .h_blank = {0xbc, 0x02},
1210                 .v2_blank = {0xdc, 0x05},
1211                 .v1_blank = {0x1e, 0x00},
1212                 .v_line = {0xdc, 0x05},
1213                 .h_line = {0xbc, 0x07},
1214                 .hsync_pol = {0x00},
1215                 .vsync_pol = {0x00},
1216                 .int_pro_mode = {0x00},
1217                 .v_blank_f0 = {0xff, 0xff},
1218                 .v_blank_f1 = {0xff, 0xff},
1219                 .h_sync_start = {0xb6, 0x01},
1220                 .h_sync_end = {0xde, 0x01},
1221                 .v_sync_line_bef_2 = {0x0a, 0x00},
1222                 .v_sync_line_bef_1 = {0x05, 0x00},
1223                 .v_sync_line_aft_2 = {0xff, 0xff},
1224                 .v_sync_line_aft_1 = {0xff, 0xff},
1225                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1226                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1227                 .v_blank_f2 = {0xff, 0xff},
1228                 .v_blank_f3 = {0xff, 0xff},
1229                 .v_blank_f4 = {0xff, 0xff},
1230                 .v_blank_f5 = {0xff, 0xff},
1231                 .v_sync_line_aft_3 = {0xff, 0xff},
1232                 .v_sync_line_aft_4 = {0xff, 0xff},
1233                 .v_sync_line_aft_5 = {0xff, 0xff},
1234                 .v_sync_line_aft_6 = {0xff, 0xff},
1235                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1236                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1237                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1238                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1239                 .vact_space_1 = {0xee, 0x02},
1240                 .vact_space_2 = {0x0c, 0x03},
1241                 .vact_space_3 = {0xff, 0xff},
1242                 .vact_space_4 = {0xff, 0xff},
1243                 .vact_space_5 = {0xff, 0xff},
1244                 .vact_space_6 = {0xff, 0xff},
1245                 /* other don't care */
1246         },
1247         .tg = {
1248                 0x00, /* cmd */
1249                 0xbc, 0x07, /* h_fsz */
1250                 0xbc, 0x02, 0x00, 0x05, /* hact */
1251                 0xee, 0x02, /* v_fsz */
1252                 0x01, 0x00, 0x33, 0x02, /* vsync */
1253                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1254                 0x00, 0x00, /* field_chg */
1255                 0x0c, 0x03, /* vact_st2 */
1256                 0x00, 0x00, /* vact_st3 */
1257                 0x00, 0x00, /* vact_st4 */
1258                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1259                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1260                 0x00, /* 3d FP */
1261         },
1262         .mbus_fmt = {
1263                 .width = 1280,
1264                 .height = 720,
1265                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1266                 .field = V4L2_FIELD_NONE,
1267         },
1268 };
1269
1270 static const struct hdmi_preset_conf hdmi_conf_720p50_tb = {
1271         .core = {
1272                 .h_blank = {0xbc, 0x02},
1273                 .v2_blank = {0xdc, 0x05},
1274                 .v1_blank = {0x1e, 0x00},
1275                 .v_line = {0xdc, 0x05},
1276                 .h_line = {0xbc, 0x07},
1277                 .hsync_pol = {0x00},
1278                 .vsync_pol = {0x00},
1279                 .int_pro_mode = {0x00},
1280                 .v_blank_f0 = {0xff, 0xff},
1281                 .v_blank_f1 = {0xff, 0xff},
1282                 .h_sync_start = {0xb6, 0x01},
1283                 .h_sync_end = {0xde, 0x01},
1284                 .v_sync_line_bef_2 = {0x0a, 0x00},
1285                 .v_sync_line_bef_1 = {0x05, 0x00},
1286                 .v_sync_line_aft_2 = {0xff, 0xff},
1287                 .v_sync_line_aft_1 = {0xff, 0xff},
1288                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1289                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1290                 .v_blank_f2 = {0xff, 0xff},
1291                 .v_blank_f3 = {0xff, 0xff},
1292                 .v_blank_f4 = {0xff, 0xff},
1293                 .v_blank_f5 = {0xff, 0xff},
1294                 .v_sync_line_aft_3 = {0xff, 0xff},
1295                 .v_sync_line_aft_4 = {0xff, 0xff},
1296                 .v_sync_line_aft_5 = {0xff, 0xff},
1297                 .v_sync_line_aft_6 = {0xff, 0xff},
1298                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1299                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1300                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1301                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1302                 .vact_space_1 = {0xee, 0x02},
1303                 .vact_space_2 = {0x0c, 0x03},
1304                 .vact_space_3 = {0xff, 0xff},
1305                 .vact_space_4 = {0xff, 0xff},
1306                 .vact_space_5 = {0xff, 0xff},
1307                 .vact_space_6 = {0xff, 0xff},
1308                 /* other don't care */
1309         },
1310         .tg = {
1311                 0x00, /* cmd */
1312                 0xbc, 0x07, /* h_fsz */
1313                 0xbc, 0x02, 0x00, 0x05, /* hact */
1314                 0xee, 0x02, /* v_fsz */
1315                 0x01, 0x00, 0x33, 0x02, /* vsync */
1316                 0x1e, 0x00, 0xd0, 0x02, /* vact */
1317                 0x00, 0x00, /* field_chg */
1318                 0x0c, 0x03, /* vact_st2 */
1319                 0x00, 0x00, /* vact_st3 */
1320                 0x00, 0x00, /* vact_st4 */
1321                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1322                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1323                 0x00, /* 3d FP */
1324         },
1325         .mbus_fmt = {
1326                 .width = 1280,
1327                 .height = 720,
1328                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1329                 .field = V4L2_FIELD_NONE,
1330         },
1331 };
1332
1333 static const struct hdmi_preset_conf hdmi_conf_1080p24_fp = {
1334         .core = {
1335                 .h_blank = {0x3e, 0x03},
1336                 .v2_blank = {0xca, 0x08},
1337                 .v1_blank = {0x2d, 0x00},
1338                 .v_line = {0xca, 0x08},
1339                 .h_line = {0xbe, 0x0a},
1340                 .hsync_pol = {0x00},
1341                 .vsync_pol = {0x00},
1342                 .int_pro_mode = {0x00},
1343                 .v_blank_f0 = {0xff, 0xff},
1344                 .v_blank_f1 = {0xff, 0xff},
1345                 .h_sync_start = {0x7c, 0x02},
1346                 .h_sync_end = {0xa8, 0x02},
1347                 .v_sync_line_bef_2 = {0x09, 0x00},
1348                 .v_sync_line_bef_1 = {0x04, 0x00},
1349                 .v_sync_line_aft_2 = {0xff, 0xff},
1350                 .v_sync_line_aft_1 = {0xff, 0xff},
1351                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1352                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1353                 .v_blank_f2 = {0xff, 0xff},
1354                 .v_blank_f3 = {0xff, 0xff},
1355                 .v_blank_f4 = {0xff, 0xff},
1356                 .v_blank_f5 = {0xff, 0xff},
1357                 .v_sync_line_aft_3 = {0xff, 0xff},
1358                 .v_sync_line_aft_4 = {0xff, 0xff},
1359                 .v_sync_line_aft_5 = {0xff, 0xff},
1360                 .v_sync_line_aft_6 = {0xff, 0xff},
1361                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1362                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1363                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1364                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1365                 .vact_space_1 = {0x65, 0x04},
1366                 .vact_space_2 = {0x92, 0x04},
1367                 .vact_space_3 = {0xff, 0xff},
1368                 .vact_space_4 = {0xff, 0xff},
1369                 .vact_space_5 = {0xff, 0xff},
1370                 .vact_space_6 = {0xff, 0xff},
1371                 /* other don't care */
1372         },
1373         .tg = {
1374                 0x00, /* cmd */
1375                 0xbe, 0x0a, /* h_fsz */
1376                 0x3e, 0x03, 0x80, 0x07, /* hact */
1377                 0xca, 0x08, /* v_fsz */
1378                 0x01, 0x00, 0x33, 0x02, /* vsync */
1379                 0x2d, 0x00, 0x38, 0x04, /* vact */
1380                 0x33, 0x02, /* field_chg */
1381                 0x92, 0x04, /* vact_st2 */
1382                 0x00, 0x00, /* vact_st3 */
1383                 0x00, 0x00, /* vact_st4 */
1384                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1385                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1386                 0x01, /* 3d FP */
1387         },
1388         .mbus_fmt = {
1389                 .width = 1920,
1390                 .height = 1080,
1391                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1392                 .field = V4L2_FIELD_NONE,
1393         },
1394 };
1395
1396 static const struct hdmi_preset_conf hdmi_conf_1080p24_sb_half = {
1397         .core = {
1398                 .h_blank = {0x3e, 0x03},
1399                 .v2_blank = {0x65, 0x04},
1400                 .v1_blank = {0x2d, 0x00},
1401                 .v_line = {0x65, 0x04},
1402                 .h_line = {0xbe, 0x0a},
1403                 .hsync_pol = {0x00},
1404                 .vsync_pol = {0x00},
1405                 .int_pro_mode = {0x00},
1406                 .v_blank_f0 = {0xff, 0xff},
1407                 .v_blank_f1 = {0xff, 0xff},
1408                 .h_sync_start = {0x7c, 0x02},
1409                 .h_sync_end = {0xa8, 0x02},
1410                 .v_sync_line_bef_2 = {0x09, 0x00},
1411                 .v_sync_line_bef_1 = {0x04, 0x00},
1412                 .v_sync_line_aft_2 = {0xff, 0xff},
1413                 .v_sync_line_aft_1 = {0xff, 0xff},
1414                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1415                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1416                 .v_blank_f2 = {0xff, 0xff},
1417                 .v_blank_f3 = {0xff, 0xff},
1418                 .v_blank_f4 = {0xff, 0xff},
1419                 .v_blank_f5 = {0xff, 0xff},
1420                 .v_sync_line_aft_3 = {0xff, 0xff},
1421                 .v_sync_line_aft_4 = {0xff, 0xff},
1422                 .v_sync_line_aft_5 = {0xff, 0xff},
1423                 .v_sync_line_aft_6 = {0xff, 0xff},
1424                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1425                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1426                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1427                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1428                 .vact_space_1 = {0xff, 0xff},
1429                 .vact_space_2 = {0xff, 0xff},
1430                 .vact_space_3 = {0xff, 0xff},
1431                 .vact_space_4 = {0xff, 0xff},
1432                 .vact_space_5 = {0xff, 0xff},
1433                 .vact_space_6 = {0xff, 0xff},
1434                 /* other don't care */
1435         },
1436         .tg = {
1437                 0x00, /* cmd */
1438                 0xbe, 0x0a, /* h_fsz */
1439                 0x3e, 0x03, 0x80, 0x07, /* hact */
1440                 0x65, 0x04, /* v_fsz */
1441                 0x01, 0x00, 0x33, 0x02, /* vsync */
1442                 0x2d, 0x00, 0x38, 0x04, /* vact */
1443                 0x33, 0x02, /* field_chg */
1444                 0x48, 0x02, /* vact_st2 */
1445                 0x00, 0x00, /* vact_st3 */
1446                 0x00, 0x00, /* vact_st4 */
1447                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1448                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1449                 0x00, /* 3d FP */
1450         },
1451         .mbus_fmt = {
1452                 .width = 1920,
1453                 .height = 1080,
1454                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1455                 .field = V4L2_FIELD_NONE,
1456         },
1457 };
1458
1459 static const struct hdmi_preset_conf hdmi_conf_1080p24_tb = {
1460         .core = {
1461                 .h_blank = {0x3e, 0x03},
1462                 .v2_blank = {0x65, 0x04},
1463                 .v1_blank = {0x2d, 0x00},
1464                 .v_line = {0x65, 0x04},
1465                 .h_line = {0xbe, 0x0a},
1466                 .hsync_pol = {0x00},
1467                 .vsync_pol = {0x00},
1468                 .int_pro_mode = {0x00},
1469                 .v_blank_f0 = {0xff, 0xff},
1470                 .v_blank_f1 = {0xff, 0xff},
1471                 .h_sync_start = {0x7c, 0x02},
1472                 .h_sync_end = {0xa8, 0x02},
1473                 .v_sync_line_bef_2 = {0x09, 0x00},
1474                 .v_sync_line_bef_1 = {0x04, 0x00},
1475                 .v_sync_line_aft_2 = {0xff, 0xff},
1476                 .v_sync_line_aft_1 = {0xff, 0xff},
1477                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1478                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1479                 .v_blank_f2 = {0xff, 0xff},
1480                 .v_blank_f3 = {0xff, 0xff},
1481                 .v_blank_f4 = {0xff, 0xff},
1482                 .v_blank_f5 = {0xff, 0xff},
1483                 .v_sync_line_aft_3 = {0xff, 0xff},
1484                 .v_sync_line_aft_4 = {0xff, 0xff},
1485                 .v_sync_line_aft_5 = {0xff, 0xff},
1486                 .v_sync_line_aft_6 = {0xff, 0xff},
1487                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1488                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1489                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1490                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1491                 .vact_space_1 = {0xff, 0xff},
1492                 .vact_space_2 = {0xff, 0xff},
1493                 .vact_space_3 = {0xff, 0xff},
1494                 .vact_space_4 = {0xff, 0xff},
1495                 .vact_space_5 = {0xff, 0xff},
1496                 .vact_space_6 = {0xff, 0xff},
1497                 /* other don't care */
1498         },
1499         .tg = {
1500                 0x00, /* cmd */
1501                 0xbe, 0x0a, /* h_fsz */
1502                 0x3e, 0x03, 0x80, 0x07, /* hact */
1503                 0x65, 0x04, /* v_fsz */
1504                 0x01, 0x00, 0x33, 0x02, /* vsync */
1505                 0x2d, 0x00, 0x38, 0x04, /* vact */
1506                 0x33, 0x02, /* field_chg */
1507                 0x48, 0x02, /* vact_st2 */
1508                 0x00, 0x00, /* vact_st3 */
1509                 0x00, 0x00, /* vact_st4 */
1510                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1511                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1512                 0x00, /* 3d FP */
1513         },
1514         .mbus_fmt = {
1515                 .width = 1920,
1516                 .height = 1080,
1517                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1518                 .field = V4L2_FIELD_NONE,
1519         },
1520 };
1521
1522 static const struct hdmi_preset_conf hdmi_conf_1080p23_98_fp = {
1523         .core = {
1524                 .h_blank = {0x3e, 0x03},
1525                 .v2_blank = {0xca, 0x08},
1526                 .v1_blank = {0x2d, 0x00},
1527                 .v_line = {0xca, 0x08},
1528                 .h_line = {0xbe, 0x0a},
1529                 .hsync_pol = {0x00},
1530                 .vsync_pol = {0x00},
1531                 .int_pro_mode = {0x00},
1532                 .v_blank_f0 = {0xff, 0xff},
1533                 .v_blank_f1 = {0xff, 0xff},
1534                 .h_sync_start = {0x7c, 0x02},
1535                 .h_sync_end = {0xa8, 0x02},
1536                 .v_sync_line_bef_2 = {0x09, 0x00},
1537                 .v_sync_line_bef_1 = {0x04, 0x00},
1538                 .v_sync_line_aft_2 = {0xff, 0xff},
1539                 .v_sync_line_aft_1 = {0xff, 0xff},
1540                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1541                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1542                 .v_blank_f2 = {0xff, 0xff},
1543                 .v_blank_f3 = {0xff, 0xff},
1544                 .v_blank_f4 = {0xff, 0xff},
1545                 .v_blank_f5 = {0xff, 0xff},
1546                 .v_sync_line_aft_3 = {0xff, 0xff},
1547                 .v_sync_line_aft_4 = {0xff, 0xff},
1548                 .v_sync_line_aft_5 = {0xff, 0xff},
1549                 .v_sync_line_aft_6 = {0xff, 0xff},
1550                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1551                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1552                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1553                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1554                 .vact_space_1 = {0x65, 0x04},
1555                 .vact_space_2 = {0x92, 0x04},
1556                 .vact_space_3 = {0xff, 0xff},
1557                 .vact_space_4 = {0xff, 0xff},
1558                 .vact_space_5 = {0xff, 0xff},
1559                 .vact_space_6 = {0xff, 0xff},
1560                 /* other don't care */
1561         },
1562         .tg = {
1563                 0x00, /* cmd */
1564                 0xbe, 0x0a, /* h_fsz */
1565                 0x3e, 0x03, 0x80, 0x07, /* hact */
1566                 0xca, 0x08, /* v_fsz */
1567                 0x01, 0x00, 0x33, 0x02, /* vsync */
1568                 0x2d, 0x00, 0x38, 0x04, /* vact */
1569                 0x33, 0x02, /* field_chg */
1570                 0x92, 0x04, /* vact_st2 */
1571                 0x00, 0x00, /* vact_st3 */
1572                 0x00, 0x00, /* vact_st4 */
1573                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1574                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1575                 0x01, /* 3d FP */
1576         },
1577         .mbus_fmt = {
1578                 .width = 1920,
1579                 .height = 1080,
1580                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1581                 .field = V4L2_FIELD_NONE,
1582         },
1583 };
1584
1585 static const struct hdmi_preset_conf hdmi_conf_1080p23_98_sb_half = {
1586         .core = {
1587                 .h_blank = {0x3e, 0x03},
1588                 .v2_blank = {0x65, 0x04},
1589                 .v1_blank = {0x2d, 0x00},
1590                 .v_line = {0x65, 0x04},
1591                 .h_line = {0xbe, 0x0a},
1592                 .hsync_pol = {0x00},
1593                 .vsync_pol = {0x00},
1594                 .int_pro_mode = {0x00},
1595                 .v_blank_f0 = {0xff, 0xff},
1596                 .v_blank_f1 = {0xff, 0xff},
1597                 .h_sync_start = {0x7c, 0x02},
1598                 .h_sync_end = {0xa8, 0x02},
1599                 .v_sync_line_bef_2 = {0x09, 0x00},
1600                 .v_sync_line_bef_1 = {0x04, 0x00},
1601                 .v_sync_line_aft_2 = {0xff, 0xff},
1602                 .v_sync_line_aft_1 = {0xff, 0xff},
1603                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1604                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1605                 .v_blank_f2 = {0xff, 0xff},
1606                 .v_blank_f3 = {0xff, 0xff},
1607                 .v_blank_f4 = {0xff, 0xff},
1608                 .v_blank_f5 = {0xff, 0xff},
1609                 .v_sync_line_aft_3 = {0xff, 0xff},
1610                 .v_sync_line_aft_4 = {0xff, 0xff},
1611                 .v_sync_line_aft_5 = {0xff, 0xff},
1612                 .v_sync_line_aft_6 = {0xff, 0xff},
1613                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1614                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1615                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1616                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1617                 .vact_space_1 = {0xff, 0xff},
1618                 .vact_space_2 = {0xff, 0xff},
1619                 .vact_space_3 = {0xff, 0xff},
1620                 .vact_space_4 = {0xff, 0xff},
1621                 .vact_space_5 = {0xff, 0xff},
1622                 .vact_space_6 = {0xff, 0xff},
1623                 /* other don't care */
1624         },
1625         .tg = {
1626                 0x00, /* cmd */
1627                 0xbe, 0x0a, /* h_fsz */
1628                 0x3e, 0x03, 0x80, 0x07, /* hact */
1629                 0x65, 0x04, /* v_fsz */
1630                 0x01, 0x00, 0x33, 0x02, /* vsync */
1631                 0x2d, 0x00, 0x38, 0x04, /* vact */
1632                 0x33, 0x02, /* field_chg */
1633                 0x48, 0x02, /* vact_st2 */
1634                 0x00, 0x00, /* vact_st3 */
1635                 0x00, 0x00, /* vact_st4 */
1636                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1637                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1638                 0x00, /* 3d FP */
1639         },
1640         .mbus_fmt = {
1641                 .width = 1920,
1642                 .height = 1080,
1643                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1644                 .field = V4L2_FIELD_NONE,
1645         },
1646 };
1647
1648 static const struct hdmi_preset_conf hdmi_conf_1080p23_98_tb = {
1649         .core = {
1650                 .h_blank = {0x3e, 0x03},
1651                 .v2_blank = {0x65, 0x04},
1652                 .v1_blank = {0x2d, 0x00},
1653                 .v_line = {0x65, 0x04},
1654                 .h_line = {0xbe, 0x0a},
1655                 .hsync_pol = {0x00},
1656                 .vsync_pol = {0x00},
1657                 .int_pro_mode = {0x00},
1658                 .v_blank_f0 = {0xff, 0xff},
1659                 .v_blank_f1 = {0xff, 0xff},
1660                 .h_sync_start = {0x7c, 0x02},
1661                 .h_sync_end = {0xa8, 0x02},
1662                 .v_sync_line_bef_2 = {0x09, 0x00},
1663                 .v_sync_line_bef_1 = {0x04, 0x00},
1664                 .v_sync_line_aft_2 = {0xff, 0xff},
1665                 .v_sync_line_aft_1 = {0xff, 0xff},
1666                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1667                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1668                 .v_blank_f2 = {0xff, 0xff},
1669                 .v_blank_f3 = {0xff, 0xff},
1670                 .v_blank_f4 = {0xff, 0xff},
1671                 .v_blank_f5 = {0xff, 0xff},
1672                 .v_sync_line_aft_3 = {0xff, 0xff},
1673                 .v_sync_line_aft_4 = {0xff, 0xff},
1674                 .v_sync_line_aft_5 = {0xff, 0xff},
1675                 .v_sync_line_aft_6 = {0xff, 0xff},
1676                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1677                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1678                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1679                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1680                 .vact_space_1 = {0xff, 0xff},
1681                 .vact_space_2 = {0xff, 0xff},
1682                 .vact_space_3 = {0xff, 0xff},
1683                 .vact_space_4 = {0xff, 0xff},
1684                 .vact_space_5 = {0xff, 0xff},
1685                 .vact_space_6 = {0xff, 0xff},
1686                 /* other don't care */
1687         },
1688         .tg = {
1689                 0x00, /* cmd */
1690                 0xbe, 0x0a, /* h_fsz */
1691                 0x3e, 0x03, 0x80, 0x07, /* hact */
1692                 0x65, 0x04, /* v_fsz */
1693                 0x01, 0x00, 0x33, 0x02, /* vsync */
1694                 0x2d, 0x00, 0x38, 0x04, /* vact */
1695                 0x33, 0x02, /* field_chg */
1696                 0x48, 0x02, /* vact_st2 */
1697                 0x00, 0x00, /* vact_st3 */
1698                 0x00, 0x00, /* vact_st4 */
1699                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1700                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1701                 0x00, /* 3d FP */
1702         },
1703         .mbus_fmt = {
1704                 .width = 1920,
1705                 .height = 1080,
1706                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1707                 .field = V4L2_FIELD_NONE,
1708         },
1709 };
1710
1711 static const struct hdmi_preset_conf hdmi_conf_1080i60_sb_half = {
1712         .core = {
1713                 .h_blank = {0x18, 0x01},
1714                 .v2_blank = {0x32, 0x02},
1715                 .v1_blank = {0x16, 0x00},
1716                 .v_line = {0x65, 0x04},
1717                 .h_line = {0x98, 0x08},
1718                 .hsync_pol = {0x00},
1719                 .vsync_pol = {0x00},
1720                 .int_pro_mode = {0x01},
1721                 .v_blank_f0 = {0x49, 0x02},
1722                 .v_blank_f1 = {0x65, 0x04},
1723                 .h_sync_start = {0x56, 0x00},
1724                 .h_sync_end = {0x82, 0x00},
1725                 .v_sync_line_bef_2 = {0x07, 0x00},
1726                 .v_sync_line_bef_1 = {0x02, 0x00},
1727                 .v_sync_line_aft_2 = {0x39, 0x02},
1728                 .v_sync_line_aft_1 = {0x34, 0x02},
1729                 .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
1730                 .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
1731                 .v_blank_f2 = {0xff, 0xff},
1732                 .v_blank_f3 = {0xff, 0xff},
1733                 .v_blank_f4 = {0xff, 0xff},
1734                 .v_blank_f5 = {0xff, 0xff},
1735                 .v_sync_line_aft_3 = {0xff, 0xff},
1736                 .v_sync_line_aft_4 = {0xff, 0xff},
1737                 .v_sync_line_aft_5 = {0xff, 0xff},
1738                 .v_sync_line_aft_6 = {0xff, 0xff},
1739                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1740                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1741                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1742                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1743                 .vact_space_1 = {0xff, 0xff},
1744                 .vact_space_2 = {0xff, 0xff},
1745                 .vact_space_3 = {0xff, 0xff},
1746                 .vact_space_4 = {0xff, 0xff},
1747                 .vact_space_5 = {0xff, 0xff},
1748                 .vact_space_6 = {0xff, 0xff},
1749                 /* other don't care */
1750         },
1751         .tg = {
1752                 0x00, /* cmd */
1753                 0x98, 0x08, /* h_fsz */
1754                 0x18, 0x01, 0x80, 0x07, /* hact */
1755                 0x64, 0x04, /* v_fsz */
1756                 0x01, 0x00, 0x33, 0x02, /* vsync */
1757                 0x16, 0x00, 0x1c, 0x02, /* vact */
1758                 0x65, 0x04, /* field_chg */
1759                 0x49, 0x02, /* vact_st2 */
1760                 0x7b, 0x04, /* vact_st3 */
1761                 0xae, 0x06, /* vact_st4 */
1762                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
1763                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1764                 0x00, /* 3d FP */
1765         },
1766         .mbus_fmt = {
1767                 .width = 1920,
1768                 .height = 1080,
1769                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1770                 .field = V4L2_FIELD_NONE,
1771         },
1772 };
1773
1774 static const struct hdmi_preset_conf hdmi_conf_1080i59_94_sb_half = {
1775         .core = {
1776                 .h_blank = {0x18, 0x01},
1777                 .v2_blank = {0x32, 0x02},
1778                 .v1_blank = {0x16, 0x00},
1779                 .v_line = {0x65, 0x04},
1780                 .h_line = {0x98, 0x08},
1781                 .hsync_pol = {0x00},
1782                 .vsync_pol = {0x00},
1783                 .int_pro_mode = {0x01},
1784                 .v_blank_f0 = {0x49, 0x02},
1785                 .v_blank_f1 = {0x65, 0x04},
1786                 .h_sync_start = {0x56, 0x00},
1787                 .h_sync_end = {0x82, 0x00},
1788                 .v_sync_line_bef_2 = {0x07, 0x00},
1789                 .v_sync_line_bef_1 = {0x02, 0x00},
1790                 .v_sync_line_aft_2 = {0x39, 0x02},
1791                 .v_sync_line_aft_1 = {0x34, 0x02},
1792                 .v_sync_line_aft_pxl_2 = {0xa4, 0x04},
1793                 .v_sync_line_aft_pxl_1 = {0xa4, 0x04},
1794                 .v_blank_f2 = {0xff, 0xff},
1795                 .v_blank_f3 = {0xff, 0xff},
1796                 .v_blank_f4 = {0xff, 0xff},
1797                 .v_blank_f5 = {0xff, 0xff},
1798                 .v_sync_line_aft_3 = {0xff, 0xff},
1799                 .v_sync_line_aft_4 = {0xff, 0xff},
1800                 .v_sync_line_aft_5 = {0xff, 0xff},
1801                 .v_sync_line_aft_6 = {0xff, 0xff},
1802                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1803                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1804                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1805                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1806                 .vact_space_1 = {0xff, 0xff},
1807                 .vact_space_2 = {0xff, 0xff},
1808                 .vact_space_3 = {0xff, 0xff},
1809                 .vact_space_4 = {0xff, 0xff},
1810                 .vact_space_5 = {0xff, 0xff},
1811                 .vact_space_6 = {0xff, 0xff},
1812                 /* other don't care */
1813         },
1814         .tg = {
1815                 0x00, /* cmd */
1816                 0x98, 0x08, /* h_fsz */
1817                 0x18, 0x01, 0x80, 0x07, /* hact */
1818                 0x64, 0x04, /* v_fsz */
1819                 0x01, 0x00, 0x33, 0x02, /* vsync */
1820                 0x16, 0x00, 0x1c, 0x02, /* vact */
1821                 0x65, 0x04, /* field_chg */
1822                 0x49, 0x02, /* vact_st2 */
1823                 0x7b, 0x04, /* vact_st3 */
1824                 0xae, 0x06, /* vact_st4 */
1825                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
1826                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1827                 0x00, /* 3d FP */
1828         },
1829         .mbus_fmt = {
1830                 .width = 1920,
1831                 .height = 1080,
1832                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1833                 .field = V4L2_FIELD_NONE,
1834         },
1835 };
1836
1837 static const struct hdmi_preset_conf hdmi_conf_1080i50_sb_half = {
1838         .core = {
1839                 .h_blank = {0xd0, 0x02},
1840                 .v2_blank = {0x32, 0x02},
1841                 .v1_blank = {0x16, 0x00},
1842                 .v_line = {0x65, 0x04},
1843                 .h_line = {0x50, 0x0a},
1844                 .hsync_pol = {0x00},
1845                 .vsync_pol = {0x00},
1846                 .int_pro_mode = {0x01},
1847                 .v_blank_f0 = {0x49, 0x02},
1848                 .v_blank_f1 = {0x65, 0x04},
1849                 .h_sync_start = {0x0e, 0x02},
1850                 .h_sync_end = {0x3a, 0x02},
1851                 .v_sync_line_bef_2 = {0x07, 0x00},
1852                 .v_sync_line_bef_1 = {0x02, 0x00},
1853                 .v_sync_line_aft_2 = {0x39, 0x02},
1854                 .v_sync_line_aft_1 = {0x34, 0x02},
1855                 .v_sync_line_aft_pxl_2 = {0x38, 0x07},
1856                 .v_sync_line_aft_pxl_1 = {0x38, 0x07},
1857                 .v_blank_f2 = {0xff, 0xff},
1858                 .v_blank_f3 = {0xff, 0xff},
1859                 .v_blank_f4 = {0xff, 0xff},
1860                 .v_blank_f5 = {0xff, 0xff},
1861                 .v_sync_line_aft_3 = {0xff, 0xff},
1862                 .v_sync_line_aft_4 = {0xff, 0xff},
1863                 .v_sync_line_aft_5 = {0xff, 0xff},
1864                 .v_sync_line_aft_6 = {0xff, 0xff},
1865                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1866                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1867                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1868                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1869                 .vact_space_1 = {0xff, 0xff},
1870                 .vact_space_2 = {0xff, 0xff},
1871                 .vact_space_3 = {0xff, 0xff},
1872                 .vact_space_4 = {0xff, 0xff},
1873                 .vact_space_5 = {0xff, 0xff},
1874                 .vact_space_6 = {0xff, 0xff},
1875                 /* other don't care */
1876         },
1877         .tg = {
1878                 0x00, /* cmd */
1879                 0x50, 0x0a, /* h_fsz */
1880                 0xd0, 0x02, 0x80, 0x07, /* hact */
1881                 0x64, 0x04, /* v_fsz */
1882                 0x01, 0x00, 0x33, 0x02, /* vsync */
1883                 0x16, 0x00, 0x1c, 0x02, /* vact */
1884                 0x65, 0x04, /* field_chg */
1885                 0x49, 0x02, /* vact_st2 */
1886                 0x7b, 0x04, /* vact_st3 */
1887                 0xae, 0x06, /* vact_st4 */
1888                 0x01, 0x00, 0x33, 0x02, /* vsync top/bot */
1889                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1890                 0x00, /* 3d FP */
1891         },
1892         .mbus_fmt = {
1893                 .width = 1920,
1894                 .height = 1080,
1895                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1896                 .field = V4L2_FIELD_NONE,
1897         },
1898 };
1899
1900 static const struct hdmi_preset_conf hdmi_conf_1080p60_sb_half = {
1901         .core = {
1902                 .h_blank = {0x18, 0x01},
1903                 .v2_blank = {0x65, 0x04},
1904                 .v1_blank = {0x2d, 0x00},
1905                 .v_line = {0x65, 0x04},
1906                 .h_line = {0x98, 0x08},
1907                 .hsync_pol = {0x00},
1908                 .vsync_pol = {0x00},
1909                 .int_pro_mode = {0x00},
1910                 .v_blank_f0 = {0xff, 0xff},
1911                 .v_blank_f1 = {0xff, 0xff},
1912                 .h_sync_start = {0x56, 0x00},
1913                 .h_sync_end = {0x82, 0x00},
1914                 .v_sync_line_bef_2 = {0x09, 0x00},
1915                 .v_sync_line_bef_1 = {0x04, 0x00},
1916                 .v_sync_line_aft_2 = {0xff, 0xff},
1917                 .v_sync_line_aft_1 = {0xff, 0xff},
1918                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1919                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1920                 .v_blank_f2 = {0xff, 0xff},
1921                 .v_blank_f3 = {0xff, 0xff},
1922                 .v_blank_f4 = {0xff, 0xff},
1923                 .v_blank_f5 = {0xff, 0xff},
1924                 .v_sync_line_aft_3 = {0xff, 0xff},
1925                 .v_sync_line_aft_4 = {0xff, 0xff},
1926                 .v_sync_line_aft_5 = {0xff, 0xff},
1927                 .v_sync_line_aft_6 = {0xff, 0xff},
1928                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1929                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1930                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1931                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1932                 .vact_space_1 = {0xff, 0xff},
1933                 .vact_space_2 = {0xff, 0xff},
1934                 .vact_space_3 = {0xff, 0xff},
1935                 .vact_space_4 = {0xff, 0xff},
1936                 .vact_space_5 = {0xff, 0xff},
1937                 .vact_space_6 = {0xff, 0xff},
1938                 /* other don't care */
1939         },
1940         .tg = {
1941                 0x00, /* cmd */
1942                 0x98, 0x08, /* h_fsz */
1943                 0x18, 0x01, 0x80, 0x07, /* hact */
1944                 0x65, 0x04, /* v_fsz */
1945                 0x01, 0x00, 0x33, 0x02, /* vsync */
1946                 0x2d, 0x00, 0x38, 0x04, /* vact */
1947                 0x33, 0x02, /* field_chg */
1948                 0x48, 0x02, /* vact_st2 */
1949                 0x00, 0x00, /* vact_st3 */
1950                 0x00, 0x00, /* vact_st4 */
1951                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
1952                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
1953                 0x00, /* 3d FP */
1954         },
1955         .mbus_fmt = {
1956                 .width = 1920,
1957                 .height = 1080,
1958                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
1959                 .field = V4L2_FIELD_NONE,
1960         },
1961 };
1962
1963 static const struct hdmi_preset_conf hdmi_conf_1080p60_tb = {
1964         .core = {
1965                 .h_blank = {0x18, 0x01},
1966                 .v2_blank = {0x65, 0x04},
1967                 .v1_blank = {0x2d, 0x00},
1968                 .v_line = {0x65, 0x04},
1969                 .h_line = {0x98, 0x08},
1970                 .hsync_pol = {0x00},
1971                 .vsync_pol = {0x00},
1972                 .int_pro_mode = {0x00},
1973                 .v_blank_f0 = {0xff, 0xff},
1974                 .v_blank_f1 = {0xff, 0xff},
1975                 .h_sync_start = {0x56, 0x00},
1976                 .h_sync_end = {0x82, 0x00},
1977                 .v_sync_line_bef_2 = {0x09, 0x00},
1978                 .v_sync_line_bef_1 = {0x04, 0x00},
1979                 .v_sync_line_aft_2 = {0xff, 0xff},
1980                 .v_sync_line_aft_1 = {0xff, 0xff},
1981                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
1982                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
1983                 .v_blank_f2 = {0xff, 0xff},
1984                 .v_blank_f3 = {0xff, 0xff},
1985                 .v_blank_f4 = {0xff, 0xff},
1986                 .v_blank_f5 = {0xff, 0xff},
1987                 .v_sync_line_aft_3 = {0xff, 0xff},
1988                 .v_sync_line_aft_4 = {0xff, 0xff},
1989                 .v_sync_line_aft_5 = {0xff, 0xff},
1990                 .v_sync_line_aft_6 = {0xff, 0xff},
1991                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
1992                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
1993                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
1994                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
1995                 .vact_space_1 = {0xff, 0xff},
1996                 .vact_space_2 = {0xff, 0xff},
1997                 .vact_space_3 = {0xff, 0xff},
1998                 .vact_space_4 = {0xff, 0xff},
1999                 .vact_space_5 = {0xff, 0xff},
2000                 .vact_space_6 = {0xff, 0xff},
2001                 /* other don't care */
2002         },
2003         .tg = {
2004                 0x00, /* cmd */
2005                 0x98, 0x08, /* h_fsz */
2006                 0x18, 0x01, 0x80, 0x07, /* hact */
2007                 0x65, 0x04, /* v_fsz */
2008                 0x01, 0x00, 0x33, 0x02, /* vsync */
2009                 0x2d, 0x00, 0x38, 0x04, /* vact */
2010                 0x33, 0x02, /* field_chg */
2011                 0x48, 0x02, /* vact_st2 */
2012                 0x00, 0x00, /* vact_st3 */
2013                 0x00, 0x00, /* vact_st4 */
2014                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
2015                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
2016                 0x00, /* 3d FP */
2017         },
2018         .mbus_fmt = {
2019                 .width = 1920,
2020                 .height = 1080,
2021                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
2022                 .field = V4L2_FIELD_NONE,
2023         },
2024 };
2025
2026 static const struct hdmi_preset_conf hdmi_conf_1080p30_sb_half = {
2027         .core = {
2028                 .h_blank = {0x18, 0x01},
2029                 .v2_blank = {0x65, 0x04},
2030                 .v1_blank = {0x2d, 0x00},
2031                 .v_line = {0x65, 0x04},
2032                 .h_line = {0x98, 0x08},
2033                 .hsync_pol = {0x00},
2034                 .vsync_pol = {0x00},
2035                 .int_pro_mode = {0x00},
2036                 .v_blank_f0 = {0xff, 0xff},
2037                 .v_blank_f1 = {0xff, 0xff},
2038                 .h_sync_start = {0x56, 0x00},
2039                 .h_sync_end = {0x82, 0x00},
2040                 .v_sync_line_bef_2 = {0x09, 0x00},
2041                 .v_sync_line_bef_1 = {0x04, 0x00},
2042                 .v_sync_line_aft_2 = {0xff, 0xff},
2043                 .v_sync_line_aft_1 = {0xff, 0xff},
2044                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
2045                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
2046                 .v_blank_f2 = {0xff, 0xff},
2047                 .v_blank_f3 = {0xff, 0xff},
2048                 .v_blank_f4 = {0xff, 0xff},
2049                 .v_blank_f5 = {0xff, 0xff},
2050                 .v_sync_line_aft_3 = {0xff, 0xff},
2051                 .v_sync_line_aft_4 = {0xff, 0xff},
2052                 .v_sync_line_aft_5 = {0xff, 0xff},
2053                 .v_sync_line_aft_6 = {0xff, 0xff},
2054                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
2055                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
2056                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
2057                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
2058                 .vact_space_1 = {0xff, 0xff},
2059                 .vact_space_2 = {0xff, 0xff},
2060                 .vact_space_3 = {0xff, 0xff},
2061                 .vact_space_4 = {0xff, 0xff},
2062                 .vact_space_5 = {0xff, 0xff},
2063                 .vact_space_6 = {0xff, 0xff},
2064                 /* other don't care */
2065         },
2066         .tg = {
2067                 0x00, /* cmd */
2068                 0x98, 0x08, /* h_fsz */
2069                 0x18, 0x01, 0x80, 0x07, /* hact */
2070                 0x65, 0x04, /* v_fsz */
2071                 0x01, 0x00, 0x33, 0x02, /* vsync */
2072                 0x2d, 0x00, 0x38, 0x04, /* vact */
2073                 0x33, 0x02, /* field_chg */
2074                 0x48, 0x02, /* vact_st2 */
2075                 0x00, 0x00, /* vact_st3 */
2076                 0x00, 0x00, /* vact_st4 */
2077                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
2078                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
2079                 0x00, /* 3d FP */
2080         },
2081         .mbus_fmt = {
2082                 .width = 1920,
2083                 .height = 1080,
2084                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
2085                 .field = V4L2_FIELD_NONE,
2086         },
2087 };
2088
2089 static const struct hdmi_preset_conf hdmi_conf_1080p30_tb = {
2090         .core = {
2091                 .h_blank = {0x18, 0x01},
2092                 .v2_blank = {0x65, 0x04},
2093                 .v1_blank = {0x2d, 0x00},
2094                 .v_line = {0x65, 0x04},
2095                 .h_line = {0x98, 0x08},
2096                 .hsync_pol = {0x00},
2097                 .vsync_pol = {0x00},
2098                 .int_pro_mode = {0x00},
2099                 .v_blank_f0 = {0xff, 0xff},
2100                 .v_blank_f1 = {0xff, 0xff},
2101                 .h_sync_start = {0x56, 0x00},
2102                 .h_sync_end = {0x82, 0x00},
2103                 .v_sync_line_bef_2 = {0x09, 0x00},
2104                 .v_sync_line_bef_1 = {0x04, 0x00},
2105                 .v_sync_line_aft_2 = {0xff, 0xff},
2106                 .v_sync_line_aft_1 = {0xff, 0xff},
2107                 .v_sync_line_aft_pxl_2 = {0xff, 0xff},
2108                 .v_sync_line_aft_pxl_1 = {0xff, 0xff},
2109                 .v_blank_f2 = {0xff, 0xff},
2110                 .v_blank_f3 = {0xff, 0xff},
2111                 .v_blank_f4 = {0xff, 0xff},
2112                 .v_blank_f5 = {0xff, 0xff},
2113                 .v_sync_line_aft_3 = {0xff, 0xff},
2114                 .v_sync_line_aft_4 = {0xff, 0xff},
2115                 .v_sync_line_aft_5 = {0xff, 0xff},
2116                 .v_sync_line_aft_6 = {0xff, 0xff},
2117                 .v_sync_line_aft_pxl_3 = {0xff, 0xff},
2118                 .v_sync_line_aft_pxl_4 = {0xff, 0xff},
2119                 .v_sync_line_aft_pxl_5 = {0xff, 0xff},
2120                 .v_sync_line_aft_pxl_6 = {0xff, 0xff},
2121                 .vact_space_1 = {0xff, 0xff},
2122                 .vact_space_2 = {0xff, 0xff},
2123                 .vact_space_3 = {0xff, 0xff},
2124                 .vact_space_4 = {0xff, 0xff},
2125                 .vact_space_5 = {0xff, 0xff},
2126                 .vact_space_6 = {0xff, 0xff},
2127                 /* other don't care */
2128         },
2129         .tg = {
2130                 0x00, /* cmd */
2131                 0x98, 0x08, /* h_fsz */
2132                 0x18, 0x01, 0x80, 0x07, /* hact */
2133                 0x65, 0x04, /* v_fsz */
2134                 0x01, 0x00, 0x33, 0x02, /* vsync */
2135                 0x2d, 0x00, 0x38, 0x04, /* vact */
2136                 0x33, 0x02, /* field_chg */
2137                 0x48, 0x02, /* vact_st2 */
2138                 0x00, 0x00, /* vact_st3 */
2139                 0x00, 0x00, /* vact_st4 */
2140                 0x01, 0x00, 0x01, 0x00, /* vsync top/bot */
2141                 0x01, 0x00, 0x33, 0x02, /* field top/bot */
2142                 0x00, /* 3d FP */
2143         },
2144         .mbus_fmt = {
2145                 .width = 1920,
2146                 .height = 1080,
2147                 .code = V4L2_MBUS_FMT_FIXED, /* means RGB888 */
2148                 .field = V4L2_FIELD_NONE,
2149         },
2150 };
2151
2152 static const struct hdmi_3d_info info_2d = {
2153         .is_3d = HDMI_VIDEO_FORMAT_2D,
2154 };
2155
2156 static const struct hdmi_3d_info info_3d_sb_h = {
2157         .is_3d = HDMI_VIDEO_FORMAT_3D,
2158         .fmt_3d = HDMI_3D_FORMAT_SB_HALF,
2159 };
2160
2161 static const struct hdmi_3d_info info_3d_tb = {
2162         .is_3d = HDMI_VIDEO_FORMAT_3D,
2163         .fmt_3d = HDMI_3D_FORMAT_TB,
2164 };
2165
2166 static const struct hdmi_3d_info info_3d_fp = {
2167         .is_3d = HDMI_VIDEO_FORMAT_3D,
2168         .fmt_3d = HDMI_3D_FORMAT_FP,
2169 };
2170
2171 const struct hdmi_conf hdmi_conf[] = {
2172         { V4L2_DV_480P59_94,       &hdmi_conf_480p59_94,        &info_2d },
2173         { V4L2_DV_480P60,          &hdmi_conf_480p60,           &info_2d },
2174         { V4L2_DV_576P50,          &hdmi_conf_576p50,           &info_2d },
2175         { V4L2_DV_720P50,          &hdmi_conf_720p50,           &info_2d },
2176         { V4L2_DV_720P59_94,       &hdmi_conf_720p59_94,        &info_2d },
2177         { V4L2_DV_720P60,          &hdmi_conf_720p60,           &info_2d },
2178         { V4L2_DV_1080I50,         &hdmi_conf_1080i50,          &info_2d },
2179         { V4L2_DV_1080I59_94,      &hdmi_conf_1080i59_94,       &info_2d },
2180         { V4L2_DV_1080I60,         &hdmi_conf_1080i60,          &info_2d },
2181         { V4L2_DV_1080P24,         &hdmi_conf_1080p24,          &info_2d },
2182         { V4L2_DV_1080P25,         &hdmi_conf_1080p25,          &info_2d },
2183         { V4L2_DV_1080P30,         &hdmi_conf_1080p30,          &info_2d },
2184         { V4L2_DV_1080P50,         &hdmi_conf_1080p50,          &info_2d },
2185         { V4L2_DV_1080P59_94,      &hdmi_conf_1080p59_94,       &info_2d },
2186         { V4L2_DV_1080P60,         &hdmi_conf_1080p60,          &info_2d },
2187         { V4L2_DV_720P60_SB_HALF,  &hdmi_conf_720p60_sb_half,   &info_3d_sb_h },
2188         { V4L2_DV_720P60_TB,       &hdmi_conf_720p60_tb,        &info_3d_tb },
2189         { V4L2_DV_720P59_94_SB_HALF, &hdmi_conf_720p59_94_sb_half,
2190                 &info_3d_sb_h },
2191         { V4L2_DV_720P59_94_TB,    &hdmi_conf_720p59_94_tb,     &info_3d_tb },
2192         { V4L2_DV_720P50_SB_HALF,  &hdmi_conf_720p50_sb_half,   &info_3d_sb_h },
2193         { V4L2_DV_720P50_TB,       &hdmi_conf_720p50_tb,        &info_3d_tb },
2194         { V4L2_DV_1080P24_FP,      &hdmi_conf_1080p24_fp,       &info_3d_fp },
2195         { V4L2_DV_1080P24_SB_HALF, &hdmi_conf_1080p24_sb_half,  &info_3d_sb_h },
2196         { V4L2_DV_1080P24_TB,      &hdmi_conf_1080p24_tb,       &info_3d_tb },
2197         { V4L2_DV_1080P23_98_FP,   &hdmi_conf_1080p23_98_fp,    &info_3d_fp },
2198         { V4L2_DV_1080P23_98_SB_HALF, &hdmi_conf_1080p23_98_sb_half,
2199                 &info_3d_sb_h },
2200         { V4L2_DV_1080P23_98_TB,   &hdmi_conf_1080p23_98_tb,    &info_3d_tb },
2201         { V4L2_DV_1080I60_SB_HALF, &hdmi_conf_1080i60_sb_half,  &info_3d_sb_h },
2202         { V4L2_DV_1080I59_94_SB_HALF, &hdmi_conf_1080i59_94_sb_half,
2203                 &info_3d_sb_h },
2204         { V4L2_DV_1080I50_SB_HALF, &hdmi_conf_1080i50_sb_half, &info_3d_sb_h },
2205         { V4L2_DV_1080P60_SB_HALF, &hdmi_conf_1080p60_sb_half, &info_3d_sb_h },
2206         { V4L2_DV_1080P60_TB, &hdmi_conf_1080p60_tb, &info_3d_tb },
2207         { V4L2_DV_1080P30_SB_HALF, &hdmi_conf_1080p30_sb_half, &info_3d_sb_h },
2208         { V4L2_DV_1080P30_TB, &hdmi_conf_1080p30_tb, &info_3d_tb },
2209 };
2210
2211 const int hdmi_pre_cnt = ARRAY_SIZE(hdmi_conf);
2212
2213 irqreturn_t hdmi_irq_handler(int irq, void *dev_data)
2214 {
2215         struct hdmi_device *hdev = dev_data;
2216         u32 intc_flag;
2217
2218         if (!pm_runtime_suspended(hdev->dev)) {
2219                 intc_flag = hdmi_read(hdev, HDMI_INTC_FLAG_0);
2220                 /* clearing flags for HPD plug/unplug */
2221                 if (intc_flag & HDMI_INTC_FLAG_HPD_UNPLUG) {
2222                         printk(KERN_INFO "unplugged\n");
2223                         if (hdev->hdcp_info.hdcp_enable)
2224                                 hdcp_stop(hdev);
2225                         hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
2226                                         HDMI_INTC_FLAG_HPD_UNPLUG);
2227                         atomic_set(&hdev->hpd_state, HPD_LOW);
2228                 }
2229                 if (intc_flag & HDMI_INTC_FLAG_HPD_PLUG) {
2230                         printk(KERN_INFO "plugged\n");
2231                         hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
2232                                         HDMI_INTC_FLAG_HPD_PLUG);
2233                         atomic_set(&hdev->hpd_state, HPD_HIGH);
2234                 }
2235                 if (intc_flag & HDMI_INTC_FLAG_HDCP) {
2236                         printk(KERN_INFO "hdcp interrupt occur\n");
2237                         hdcp_irq_handler(hdev);
2238                         hdmi_write_mask(hdev, HDMI_INTC_FLAG_0, ~0,
2239                                         HDMI_INTC_FLAG_HDCP);
2240                 }
2241         } else{
2242                 if (s5p_v4l2_hpd_read_gpio())
2243                         atomic_set(&hdev->hpd_state, HPD_HIGH);
2244                 else
2245                         atomic_set(&hdev->hpd_state, HPD_LOW);
2246         }
2247
2248         queue_work(hdev->hpd_wq, &hdev->hpd_work);
2249
2250         return IRQ_HANDLED;
2251 }
2252
2253 void hdmi_reg_init(struct hdmi_device *hdev)
2254 {
2255         /* enable HPD interrupts */
2256         hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, HDMI_INTC_EN_GLOBAL |
2257                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
2258         /* choose HDMI mode */
2259         hdmi_write_mask(hdev, HDMI_MODE_SEL,
2260                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
2261         /* disable bluescreen */
2262         hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
2263         /* enable AVI packet every vsync, fixes purple line problem */
2264         hdmi_writeb(hdev, HDMI_AVI_CON, 0x02);
2265         /* RGB888 is default output format of HDMI,
2266          * look to CEA-861-D, table 7 for more detail */
2267         hdmi_writeb(hdev, HDMI_AVI_BYTE(1), 0 << 5);
2268         hdmi_write_mask(hdev, HDMI_CON_1, 2, 3 << 5);
2269 }
2270
2271 void hdmi_timing_apply(struct hdmi_device *hdev,
2272         const struct hdmi_preset_conf *conf)
2273 {
2274         const struct hdmi_core_regs *core = &conf->core;
2275         const struct hdmi_tg_regs *tg = &conf->tg;
2276
2277         /* setting core registers */
2278         hdmi_writeb(hdev, HDMI_H_BLANK_0, core->h_blank[0]);
2279         hdmi_writeb(hdev, HDMI_H_BLANK_1, core->h_blank[1]);
2280         hdmi_writeb(hdev, HDMI_V2_BLANK_0, core->v2_blank[0]);
2281         hdmi_writeb(hdev, HDMI_V2_BLANK_1, core->v2_blank[1]);
2282         hdmi_writeb(hdev, HDMI_V1_BLANK_0, core->v1_blank[0]);
2283         hdmi_writeb(hdev, HDMI_V1_BLANK_1, core->v1_blank[1]);
2284         hdmi_writeb(hdev, HDMI_V_LINE_0, core->v_line[0]);
2285         hdmi_writeb(hdev, HDMI_V_LINE_1, core->v_line[1]);
2286         hdmi_writeb(hdev, HDMI_H_LINE_0, core->h_line[0]);
2287         hdmi_writeb(hdev, HDMI_H_LINE_1, core->h_line[1]);
2288         hdmi_writeb(hdev, HDMI_HSYNC_POL, core->hsync_pol[0]);
2289         hdmi_writeb(hdev, HDMI_VSYNC_POL, core->vsync_pol[0]);
2290         hdmi_writeb(hdev, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
2291         hdmi_writeb(hdev, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
2292         hdmi_writeb(hdev, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
2293         hdmi_writeb(hdev, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
2294         hdmi_writeb(hdev, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
2295         hdmi_writeb(hdev, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
2296         hdmi_writeb(hdev, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
2297         hdmi_writeb(hdev, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
2298         hdmi_writeb(hdev, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
2299         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_2_0, core->v_sync_line_bef_2[0]);
2300         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_2_1, core->v_sync_line_bef_2[1]);
2301         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_1_0, core->v_sync_line_bef_1[0]);
2302         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_BEF_1_1, core->v_sync_line_bef_1[1]);
2303         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_2_0, core->v_sync_line_aft_2[0]);
2304         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_2_1, core->v_sync_line_aft_2[1]);
2305         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_1_0, core->v_sync_line_aft_1[0]);
2306         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_1_1, core->v_sync_line_aft_1[1]);
2307         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
2308                         core->v_sync_line_aft_pxl_2[0]);
2309         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
2310                         core->v_sync_line_aft_pxl_2[1]);
2311         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
2312                         core->v_sync_line_aft_pxl_1[0]);
2313         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
2314                         core->v_sync_line_aft_pxl_1[1]);
2315         hdmi_writeb(hdev, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
2316         hdmi_writeb(hdev, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
2317         hdmi_writeb(hdev, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
2318         hdmi_writeb(hdev, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
2319         hdmi_writeb(hdev, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
2320         hdmi_writeb(hdev, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
2321         hdmi_writeb(hdev, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
2322         hdmi_writeb(hdev, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
2323         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_3_0, core->v_sync_line_aft_3[0]);
2324         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_3_1, core->v_sync_line_aft_3[1]);
2325         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_4_0, core->v_sync_line_aft_4[0]);
2326         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_4_1, core->v_sync_line_aft_4[1]);
2327         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_5_0, core->v_sync_line_aft_5[0]);
2328         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_5_1, core->v_sync_line_aft_5[1]);
2329         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_6_0, core->v_sync_line_aft_6[0]);
2330         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_6_1, core->v_sync_line_aft_6[1]);
2331         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
2332                         core->v_sync_line_aft_pxl_3[0]);
2333         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
2334                         core->v_sync_line_aft_pxl_3[1]);
2335         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
2336                         core->v_sync_line_aft_pxl_4[0]);
2337         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
2338                         core->v_sync_line_aft_pxl_4[1]);
2339         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
2340                         core->v_sync_line_aft_pxl_5[0]);
2341         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
2342                         core->v_sync_line_aft_pxl_5[1]);
2343         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
2344                         core->v_sync_line_aft_pxl_6[0]);
2345         hdmi_writeb(hdev, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
2346                         core->v_sync_line_aft_pxl_6[1]);
2347         hdmi_writeb(hdev, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
2348         hdmi_writeb(hdev, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
2349         hdmi_writeb(hdev, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
2350         hdmi_writeb(hdev, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
2351         hdmi_writeb(hdev, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
2352         hdmi_writeb(hdev, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
2353         hdmi_writeb(hdev, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
2354         hdmi_writeb(hdev, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
2355         hdmi_writeb(hdev, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
2356         hdmi_writeb(hdev, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
2357         hdmi_writeb(hdev, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
2358         hdmi_writeb(hdev, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
2359
2360         /* Timing generator registers */
2361         hdmi_writeb(hdev, HDMI_TG_H_FSZ_L, tg->h_fsz_l);
2362         hdmi_writeb(hdev, HDMI_TG_H_FSZ_H, tg->h_fsz_h);
2363         hdmi_writeb(hdev, HDMI_TG_HACT_ST_L, tg->hact_st_l);
2364         hdmi_writeb(hdev, HDMI_TG_HACT_ST_H, tg->hact_st_h);
2365         hdmi_writeb(hdev, HDMI_TG_HACT_SZ_L, tg->hact_sz_l);
2366         hdmi_writeb(hdev, HDMI_TG_HACT_SZ_H, tg->hact_sz_h);
2367         hdmi_writeb(hdev, HDMI_TG_V_FSZ_L, tg->v_fsz_l);
2368         hdmi_writeb(hdev, HDMI_TG_V_FSZ_H, tg->v_fsz_h);
2369         hdmi_writeb(hdev, HDMI_TG_VSYNC_L, tg->vsync_l);
2370         hdmi_writeb(hdev, HDMI_TG_VSYNC_H, tg->vsync_h);
2371         hdmi_writeb(hdev, HDMI_TG_VSYNC2_L, tg->vsync2_l);
2372         hdmi_writeb(hdev, HDMI_TG_VSYNC2_H, tg->vsync2_h);
2373         hdmi_writeb(hdev, HDMI_TG_VACT_ST_L, tg->vact_st_l);
2374         hdmi_writeb(hdev, HDMI_TG_VACT_ST_H, tg->vact_st_h);
2375         hdmi_writeb(hdev, HDMI_TG_VACT_SZ_L, tg->vact_sz_l);
2376         hdmi_writeb(hdev, HDMI_TG_VACT_SZ_H, tg->vact_sz_h);
2377         hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_L, tg->field_chg_l);
2378         hdmi_writeb(hdev, HDMI_TG_FIELD_CHG_H, tg->field_chg_h);
2379         hdmi_writeb(hdev, HDMI_TG_VACT_ST2_L, tg->vact_st2_l);
2380         hdmi_writeb(hdev, HDMI_TG_VACT_ST2_H, tg->vact_st2_h);
2381         hdmi_writeb(hdev, HDMI_TG_VACT_ST3_L, tg->vact_st3_l);
2382         hdmi_writeb(hdev, HDMI_TG_VACT_ST3_H, tg->vact_st3_h);
2383         hdmi_writeb(hdev, HDMI_TG_VACT_ST4_L, tg->vact_st4_l);
2384         hdmi_writeb(hdev, HDMI_TG_VACT_ST4_H, tg->vact_st4_h);
2385         hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi_l);
2386         hdmi_writeb(hdev, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi_h);
2387         hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi_l);
2388         hdmi_writeb(hdev, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi_h);
2389         hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi_l);
2390         hdmi_writeb(hdev, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi_h);
2391         hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi_l);
2392         hdmi_writeb(hdev, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi_h);
2393         hdmi_writeb(hdev, HDMI_TG_3D, tg->tg_3d);
2394 }
2395
2396 int hdmi_conf_apply(struct hdmi_device *hdmi_dev)
2397 {
2398         struct device *dev = hdmi_dev->dev;
2399         const struct hdmi_preset_conf *conf = hdmi_dev->cur_conf;
2400         struct v4l2_dv_preset preset;
2401         int ret;
2402
2403         dev_dbg(dev, "%s\n", __func__);
2404
2405         /* configure presets */
2406         preset.preset = hdmi_dev->cur_preset;
2407         ret = v4l2_subdev_call(hdmi_dev->phy_sd, video, s_dv_preset, &preset);
2408         if (ret) {
2409                 dev_err(dev, "failed to set preset (%u)\n", preset.preset);
2410                 return ret;
2411         }
2412
2413         hdmi_reg_init(hdmi_dev);
2414
2415         /* setting core registers */
2416         hdmi_timing_apply(hdmi_dev, conf);
2417
2418         return 0;
2419 }
2420
2421 int is_hdmiphy_ready(struct hdmi_device *hdev)
2422 {
2423         u32 val = hdmi_read(hdev, HDMI_PHY_STATUS);
2424         if (val & HDMI_PHY_STATUS_READY)
2425                 return 1;
2426
2427         return 0;
2428 }
2429
2430 void hdmi_enable(struct hdmi_device *hdev, int on)
2431 {
2432         if (on)
2433                 hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_EN);
2434         else
2435                 hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_EN);
2436 }
2437
2438 void hdmi_hpd_enable(struct hdmi_device *hdev, int on)
2439 {
2440         /* enable HPD interrupts */
2441         hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, HDMI_INTC_EN_GLOBAL |
2442                         HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
2443 }
2444
2445 void hdmi_tg_enable(struct hdmi_device *hdev, int on)
2446 {
2447         u32 mask;
2448
2449         mask = (hdev->cur_conf->mbus_fmt.field == V4L2_FIELD_INTERLACED) ?
2450                         HDMI_TG_EN | HDMI_FIELD_EN : HDMI_TG_EN;
2451
2452         if (on)
2453                 hdmi_write_mask(hdev, HDMI_TG_CMD, ~0, mask);
2454         else
2455                 hdmi_write_mask(hdev, HDMI_TG_CMD, 0, mask);
2456 }
2457
2458 static u8 hdmi_chksum(struct hdmi_device *hdev, u32 start, u8 len, u32 hdr_sum)
2459 {
2460         int i;
2461
2462         /* hdr_sum : header0 + header1 + header2
2463          * start : start address of packet byte1
2464          * len : packet bytes - 1 */
2465         for (i = 0; i < len; ++i)
2466                 hdr_sum += hdmi_read(hdev, start + i * 4);
2467
2468         return (u8)(0x100 - (hdr_sum & 0xff));
2469 }
2470
2471 void hdmi_reg_stop_vsi(struct hdmi_device *hdev)
2472 {
2473         hdmi_writeb(hdev, HDMI_VSI_CON, HDMI_VSI_CON_DO_NOT_TRANSMIT);
2474 }
2475
2476 void hdmi_reg_infoframe(struct hdmi_device *hdev,
2477                 struct hdmi_infoframe *infoframe)
2478 {
2479         struct device *dev = hdev->dev;
2480         const struct hdmi_3d_info *info = hdmi_preset2info(hdev->cur_preset);
2481         u32 hdr_sum;
2482         u8 chksum;
2483         dev_dbg(dev, "%s: InfoFrame type = 0x%x\n", __func__, infoframe->type);
2484
2485         switch (infoframe->type) {
2486         case HDMI_PACKET_TYPE_VSI:
2487                 hdmi_writeb(hdev, HDMI_VSI_CON, HDMI_VSI_CON_EVERY_VSYNC);
2488                 hdmi_writeb(hdev, HDMI_VSI_HEADER0, infoframe->type);
2489                 hdmi_writeb(hdev, HDMI_VSI_HEADER1, infoframe->ver);
2490                 /* 0x000C03 : 24-bit IEEE Registration Identifier */
2491                 hdmi_writeb(hdev, HDMI_VSI_DATA(1), 0x03);
2492                 hdmi_writeb(hdev, HDMI_VSI_DATA(2), 0x0c);
2493                 hdmi_writeb(hdev, HDMI_VSI_DATA(3), 0x00);
2494                 hdmi_writeb(hdev, HDMI_VSI_DATA(4),
2495                         HDMI_VSI_DATA04_VIDEO_FORMAT(info->is_3d));
2496                 hdmi_writeb(hdev, HDMI_VSI_DATA(5),
2497                         HDMI_VSI_DATA05_3D_STRUCTURE(info->fmt_3d));
2498                 if (info->fmt_3d == HDMI_3D_FORMAT_SB_HALF) {
2499                         infoframe->len += 1;
2500                         hdmi_writeb(hdev, HDMI_VSI_DATA(6),
2501                         (u8)HDMI_VSI_DATA06_3D_EXT_DATA(HDMI_H_SUB_SAMPLE));
2502                 }
2503                 hdmi_writeb(hdev, HDMI_VSI_HEADER2, infoframe->len);
2504                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
2505                 chksum = hdmi_chksum(hdev, HDMI_VSI_DATA(1), infoframe->len, hdr_sum);
2506                 dev_dbg(dev, "VSI checksum = 0x%x\n", chksum);
2507                 hdmi_writeb(hdev, HDMI_VSI_DATA(0), chksum);
2508                 break;
2509         case HDMI_PACKET_TYPE_AVI:
2510                 hdmi_writeb(hdev, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
2511                 hdmi_writeb(hdev, HDMI_AVI_HEADER0, infoframe->type);
2512                 hdmi_writeb(hdev, HDMI_AVI_HEADER1, infoframe->ver);
2513                 hdmi_writeb(hdev, HDMI_AVI_HEADER2, infoframe->len);
2514                 hdmi_writeb(hdev, HDMI_AVI_BYTE(1), hdev->output_fmt << 5);
2515                 hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
2516                 chksum = hdmi_chksum(hdev, HDMI_AVI_BYTE(1), infoframe->len, hdr_sum);
2517                 dev_dbg(dev, "AVI checksum = 0x%x\n", chksum);
2518                 hdmi_writeb(hdev, HDMI_AVI_CHECK_SUM, chksum);
2519                 break;
2520         default:
2521                 break;
2522         }
2523 }
2524
2525 void hdmi_reg_set_acr(struct hdmi_device *hdev)
2526 {
2527         u32 n, cts;
2528         int sample_rate = hdev->sample_rate;
2529
2530         if (sample_rate == 32000) {
2531                 n = 4096;
2532                 cts = 27000;
2533         } else if (sample_rate == 44100) {
2534                 n = 6272;
2535                 cts = 30000;
2536         } else if (sample_rate == 48000) {
2537                 n = 6144;
2538                 cts = 27000;
2539         } else if (sample_rate == 88200) {
2540                 n = 12544;
2541                 cts = 30000;
2542         } else if (sample_rate == 96000) {
2543                 n = 12288;
2544                 cts = 27000;
2545         } else if (sample_rate == 176400) {
2546                 n = 25088;
2547                 cts = 30000;
2548         } else if (sample_rate == 192000) {
2549                 n = 24576;
2550                 cts = 27000;
2551         } else {
2552                 n = 0;
2553                 cts = 0;
2554         }
2555
2556         hdmi_write(hdev, HDMI_ACR_N0, HDMI_ACR_N0_VAL(n));
2557         hdmi_write(hdev, HDMI_ACR_N1, HDMI_ACR_N1_VAL(n));
2558         hdmi_write(hdev, HDMI_ACR_N2, HDMI_ACR_N2_VAL(n));
2559
2560         /* transfer ACR packet */
2561         hdmi_write(hdev, HDMI_ACR_CON, HDMI_ACR_CON_TX_MODE_MESURED_CTS);
2562 }
2563
2564 void hdmi_reg_spdif_audio_init(struct hdmi_device *hdev)
2565 {
2566         u32 val;
2567         int bps, rep_time;
2568
2569         hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_ENABLE);
2570
2571         val = HDMI_SPDIFIN_CFG_NOISE_FILTER_2_SAMPLE |
2572                 HDMI_SPDIFIN_CFG_PCPD_MANUAL |
2573                 HDMI_SPDIFIN_CFG_WORD_LENGTH_MANUAL |
2574                 HDMI_SPDIFIN_CFG_UVCP_REPORT |
2575                 HDMI_SPDIFIN_CFG_HDMI_2_BURST |
2576                 HDMI_SPDIFIN_CFG_DATA_ALIGN_32;
2577         hdmi_write(hdev, HDMI_SPDIFIN_CONFIG_1, val);
2578         hdmi_write(hdev, HDMI_SPDIFIN_CONFIG_2, 0);
2579
2580         bps = hdev->audio_codec == HDMI_AUDIO_PCM ? hdev->bits_per_sample : 16;
2581         rep_time = hdev->audio_codec == HDMI_AUDIO_AC3 ? 1536 * 2 - 1 : 0;
2582         val = HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_LOW(rep_time) |
2583                 HDMI_SPDIFIN_USER_VAL_WORD_LENGTH_24;
2584         hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_1, val);
2585         val = HDMI_SPDIFIN_USER_VAL_REPETITION_TIME_HIGH(rep_time);
2586         hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_2, val);
2587         hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_3, 0);
2588         hdmi_write(hdev, HDMI_SPDIFIN_USER_VALUE_4, 0);
2589
2590         val = HDMI_I2S_IN_ENABLE | HDMI_I2S_AUD_SPDIF | HDMI_I2S_MUX_ENABLE;
2591         hdmi_write(hdev, HDMI_I2S_IN_MUX_CON, val);
2592
2593         hdmi_write(hdev, HDMI_I2S_MUX_CH, HDMI_I2S_CH_ALL_EN);
2594         hdmi_write(hdev, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
2595
2596         hdmi_write_mask(hdev, HDMI_SPDIFIN_CLK_CTRL, 0, HDMI_SPDIFIN_CLK_ON);
2597         hdmi_write_mask(hdev, HDMI_SPDIFIN_CLK_CTRL, ~0, HDMI_SPDIFIN_CLK_ON);
2598
2599         hdmi_write(hdev, HDMI_SPDIFIN_OP_CTRL, HDMI_SPDIFIN_STATUS_CHECK_MODE);
2600         hdmi_write(hdev, HDMI_SPDIFIN_OP_CTRL,
2601                         HDMI_SPDIFIN_STATUS_CHECK_MODE_HDMI);
2602 }
2603
2604 void hdmi_reg_i2s_audio_init(struct hdmi_device *hdev)
2605 {
2606         u32 data_num, bit_ch, sample_frq, val;
2607         int sample_rate = hdev->sample_rate;
2608         int bits_per_sample = hdev->bits_per_sample;
2609
2610         if (bits_per_sample == 16) {
2611                 data_num = 1;
2612                 bit_ch = 0;
2613         } else if (bits_per_sample == 20) {
2614                 data_num = 2;
2615                 bit_ch  = 1;
2616         } else if (bits_per_sample == 24) {
2617                 data_num = 3;
2618                 bit_ch  = 1;
2619         } else if (bits_per_sample == 32) {
2620                 data_num = 1;
2621                 bit_ch  = 2;
2622         } else {
2623                 data_num = 1;
2624                 bit_ch = 0;
2625         }
2626
2627         /* reset I2S */
2628         hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DISABLE);
2629         hdmi_write(hdev, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_ENABLE);
2630
2631         hdmi_write_mask(hdev, HDMI_I2S_DSD_CON, 0, HDMI_I2S_DSD_ENABLE);
2632
2633         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
2634         val = HDMI_I2S_SEL_SCLK(5) | HDMI_I2S_SEL_LRCK(6);
2635         hdmi_write(hdev, HDMI_I2S_PIN_SEL_0, val);
2636         val = HDMI_I2S_SEL_SDATA1(3) | HDMI_I2S_SEL_SDATA0(4);
2637         hdmi_write(hdev, HDMI_I2S_PIN_SEL_1, val);
2638         val = HDMI_I2S_SEL_SDATA3(1) | HDMI_I2S_SEL_SDATA2(2);
2639         hdmi_write(hdev, HDMI_I2S_PIN_SEL_2, val);
2640         hdmi_write(hdev, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
2641
2642         /* I2S_CON_1 & 2 */
2643         val = HDMI_I2S_SCLK_FALLING_EDGE | HDMI_I2S_L_CH_LOW_POL;
2644         hdmi_write(hdev, HDMI_I2S_CON_1, val);
2645         val = HDMI_I2S_MSB_FIRST_MODE | HDMI_I2S_SET_BIT_CH(bit_ch) |
2646                 HDMI_I2S_SET_SDATA_BIT(data_num) | HDMI_I2S_BASIC_FORMAT;
2647         hdmi_write(hdev, HDMI_I2S_CON_2, val);
2648
2649         if (sample_rate == 32000)
2650                 sample_frq = 0x3;
2651         else if (sample_rate == 44100)
2652                 sample_frq = 0x0;
2653         else if (sample_rate == 48000)
2654                 sample_frq = 0x2;
2655         else if (sample_rate == 96000)
2656                 sample_frq = 0xa;
2657         else
2658                 sample_frq = 0;
2659
2660         /* Configure register related to CUV information */
2661         val = HDMI_I2S_CH_STATUS_MODE_0 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH |
2662                 HDMI_I2S_COPYRIGHT | HDMI_I2S_LINEAR_PCM |
2663                 HDMI_I2S_CONSUMER_FORMAT;
2664         hdmi_write(hdev, HDMI_I2S_CH_ST_0, val);
2665         hdmi_write(hdev, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
2666         hdmi_write(hdev, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
2667         val = HDMI_I2S_CLK_ACCUR_LEVEL_1 |
2668                 HDMI_I2S_SET_SAMPLING_FREQ(sample_frq);
2669         hdmi_write(hdev, HDMI_I2S_CH_ST_3, val);
2670         val = HDMI_I2S_ORG_SAMPLING_FREQ_44_1 |
2671                 HDMI_I2S_WORD_LENGTH_MAX24_20BITS |
2672                 HDMI_I2S_WORD_LENGTH_MAX_20BITS;
2673         hdmi_write(hdev, HDMI_I2S_CH_ST_4, val);
2674
2675         hdmi_write(hdev, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
2676
2677         val = HDMI_I2S_IN_ENABLE | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
2678                 | HDMI_I2S_MUX_ENABLE;
2679         hdmi_write(hdev, HDMI_I2S_IN_MUX_CON, val);
2680
2681         val = HDMI_I2S_CH0_L_EN | HDMI_I2S_CH0_R_EN | HDMI_I2S_CH1_L_EN |
2682                 HDMI_I2S_CH1_R_EN | HDMI_I2S_CH2_L_EN | HDMI_I2S_CH2_R_EN |
2683                 HDMI_I2S_CH3_L_EN | HDMI_I2S_CH3_R_EN;
2684         hdmi_write(hdev, HDMI_I2S_MUX_CH, val);
2685
2686         val = HDMI_I2S_CUV_L_EN | HDMI_I2S_CUV_R_EN;
2687         hdmi_write(hdev, HDMI_I2S_MUX_CUV, val);
2688 }
2689
2690 void hdmi_audio_enable(struct hdmi_device *hdev, int on)
2691 {
2692         if (on) {
2693                 hdmi_write(hdev, HDMI_AUI_CON, HDMI_AUI_CON_TRANS_EVERY_VSYNC);
2694                 hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_ASP_ENABLE);
2695         } else {
2696                 hdmi_write(hdev, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
2697                 hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_ASP_ENABLE);
2698         }
2699 }
2700
2701 void hdmi_bluescreen_enable(struct hdmi_device *hdev, int on)
2702 {
2703         if (on)
2704                 hdmi_write_mask(hdev, HDMI_CON_0, ~0, HDMI_BLUE_SCR_EN);
2705         else
2706                 hdmi_write_mask(hdev, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
2707 }
2708
2709 void hdmi_reg_mute(struct hdmi_device *hdev, int on)
2710 {
2711         hdmi_bluescreen_enable(hdev, on);
2712         hdmi_audio_enable(hdev, !on);
2713 }
2714
2715 int hdmi_hpd_status(struct hdmi_device *hdev)
2716 {
2717         return hdmi_read(hdev, HDMI_HPD_STATUS);
2718 }
2719
2720 int is_hdmi_streaming(struct hdmi_device *hdev)
2721 {
2722         if (hdmi_hpd_status(hdev) && hdev->streaming)
2723                 return 1;
2724         return 0;
2725 }
2726
2727 u8 hdmi_get_int_mask(struct hdmi_device *hdev)
2728 {
2729         return hdmi_readb(hdev, HDMI_INTC_CON_0);
2730 }
2731
2732 void hdmi_set_int_mask(struct hdmi_device *hdev, u8 mask, int en)
2733 {
2734         if (en) {
2735                 mask |= HDMI_INTC_EN_GLOBAL;
2736                 hdmi_write_mask(hdev, HDMI_INTC_CON_0, ~0, mask);
2737         } else
2738                 hdmi_write_mask(hdev, HDMI_INTC_CON_0, 0,
2739                                 HDMI_INTC_EN_GLOBAL);
2740 }
2741
2742 void hdmi_sw_hpd_enable(struct hdmi_device *hdev, int en)
2743 {
2744         if (en)
2745                 hdmi_write_mask(hdev, HDMI_HPD, ~0, HDMI_HPD_SEL_I_HPD);
2746         else
2747                 hdmi_write_mask(hdev, HDMI_HPD, 0, HDMI_HPD_SEL_I_HPD);
2748 }
2749
2750 void hdmi_sw_hpd_plug(struct hdmi_device *hdev, int en)
2751 {
2752         if (en)
2753                 hdmi_write_mask(hdev, HDMI_HPD, ~0, HDMI_SW_HPD_PLUGGED);
2754         else
2755                 hdmi_write_mask(hdev, HDMI_HPD, 0, HDMI_SW_HPD_PLUGGED);
2756 }
2757
2758 void hdmi_phy_sw_reset(struct hdmi_device *hdev)
2759 {
2760         hdmi_write_mask(hdev, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
2761         mdelay(10);
2762         hdmi_write_mask(hdev, HDMI_PHY_RSTOUT,  0, HDMI_PHY_SW_RSTOUT);
2763 }
2764
2765 void hdmi_dumpregs(struct hdmi_device *hdev, char *prefix)
2766 {
2767 #define DUMPREG(reg_id) \
2768         dev_dbg(hdev->dev, "%s:" #reg_id " = %08x\n", prefix, \
2769                 readl(hdev->regs + reg_id))
2770
2771         int i;
2772
2773         dev_dbg(hdev->dev, "%s: ---- CONTROL REGISTERS ----\n", prefix);
2774         DUMPREG(HDMI_INTC_CON_0);
2775         DUMPREG(HDMI_INTC_FLAG_0);
2776         DUMPREG(HDMI_HPD_STATUS);
2777         DUMPREG(HDMI_INTC_CON_1);
2778         DUMPREG(HDMI_INTC_FLAG_1);
2779         DUMPREG(HDMI_PHY_STATUS_0);
2780         DUMPREG(HDMI_PHY_STATUS_PLL);
2781         DUMPREG(HDMI_PHY_CON_0);
2782         DUMPREG(HDMI_PHY_RSTOUT);
2783         DUMPREG(HDMI_PHY_VPLL);
2784         DUMPREG(HDMI_PHY_CMU);
2785         DUMPREG(HDMI_CORE_RSTOUT);
2786
2787         dev_dbg(hdev->dev, "%s: ---- CORE REGISTERS ----\n", prefix);
2788         DUMPREG(HDMI_CON_0);
2789         DUMPREG(HDMI_CON_1);
2790         DUMPREG(HDMI_CON_2);
2791         DUMPREG(HDMI_STATUS);
2792         DUMPREG(HDMI_PHY_STATUS);
2793         DUMPREG(HDMI_STATUS_EN);
2794         DUMPREG(HDMI_HPD);
2795         DUMPREG(HDMI_MODE_SEL);
2796         DUMPREG(HDMI_ENC_EN);
2797         DUMPREG(HDMI_DC_CONTROL);
2798         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
2799
2800         dev_dbg(hdev->dev, "%s: ---- CORE SYNC REGISTERS ----\n", prefix);
2801         DUMPREG(HDMI_H_BLANK_0);
2802         DUMPREG(HDMI_H_BLANK_1);
2803         DUMPREG(HDMI_V2_BLANK_0);
2804         DUMPREG(HDMI_V2_BLANK_1);
2805         DUMPREG(HDMI_V1_BLANK_0);
2806         DUMPREG(HDMI_V1_BLANK_1);
2807         DUMPREG(HDMI_V_LINE_0);
2808         DUMPREG(HDMI_V_LINE_1);
2809         DUMPREG(HDMI_H_LINE_0);
2810         DUMPREG(HDMI_H_LINE_1);
2811         DUMPREG(HDMI_HSYNC_POL);
2812
2813         DUMPREG(HDMI_VSYNC_POL);
2814         DUMPREG(HDMI_INT_PRO_MODE);
2815         DUMPREG(HDMI_V_BLANK_F0_0);
2816         DUMPREG(HDMI_V_BLANK_F0_1);
2817         DUMPREG(HDMI_V_BLANK_F1_0);
2818         DUMPREG(HDMI_V_BLANK_F1_1);
2819
2820         DUMPREG(HDMI_H_SYNC_START_0);
2821         DUMPREG(HDMI_H_SYNC_START_1);
2822         DUMPREG(HDMI_H_SYNC_END_0);
2823         DUMPREG(HDMI_H_SYNC_END_1);
2824
2825         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
2826         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
2827         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
2828         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
2829
2830         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
2831         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
2832         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
2833         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
2834
2835         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
2836         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
2837         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
2838         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
2839
2840         DUMPREG(HDMI_V_BLANK_F2_0);
2841         DUMPREG(HDMI_V_BLANK_F2_1);
2842         DUMPREG(HDMI_V_BLANK_F3_0);
2843         DUMPREG(HDMI_V_BLANK_F3_1);
2844         DUMPREG(HDMI_V_BLANK_F4_0);
2845         DUMPREG(HDMI_V_BLANK_F4_1);
2846         DUMPREG(HDMI_V_BLANK_F5_0);
2847         DUMPREG(HDMI_V_BLANK_F5_1);
2848
2849         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
2850         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
2851         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
2852         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
2853         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
2854         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
2855         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
2856         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
2857
2858         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
2859         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
2860         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
2861         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
2862         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
2863         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
2864         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
2865         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
2866
2867         DUMPREG(HDMI_VACT_SPACE_1_0);
2868         DUMPREG(HDMI_VACT_SPACE_1_1);
2869         DUMPREG(HDMI_VACT_SPACE_2_0);
2870         DUMPREG(HDMI_VACT_SPACE_2_1);
2871         DUMPREG(HDMI_VACT_SPACE_3_0);
2872         DUMPREG(HDMI_VACT_SPACE_3_1);
2873         DUMPREG(HDMI_VACT_SPACE_4_0);
2874         DUMPREG(HDMI_VACT_SPACE_4_1);
2875         DUMPREG(HDMI_VACT_SPACE_5_0);
2876         DUMPREG(HDMI_VACT_SPACE_5_1);
2877         DUMPREG(HDMI_VACT_SPACE_6_0);
2878         DUMPREG(HDMI_VACT_SPACE_6_1);
2879
2880         dev_dbg(hdev->dev, "%s: ---- TG REGISTERS ----\n", prefix);
2881         DUMPREG(HDMI_TG_CMD);
2882         DUMPREG(HDMI_TG_H_FSZ_L);
2883         DUMPREG(HDMI_TG_H_FSZ_H);
2884         DUMPREG(HDMI_TG_HACT_ST_L);
2885         DUMPREG(HDMI_TG_HACT_ST_H);
2886         DUMPREG(HDMI_TG_HACT_SZ_L);
2887         DUMPREG(HDMI_TG_HACT_SZ_H);
2888         DUMPREG(HDMI_TG_V_FSZ_L);
2889         DUMPREG(HDMI_TG_V_FSZ_H);
2890         DUMPREG(HDMI_TG_VSYNC_L);
2891         DUMPREG(HDMI_TG_VSYNC_H);
2892         DUMPREG(HDMI_TG_VSYNC2_L);
2893         DUMPREG(HDMI_TG_VSYNC2_H);
2894         DUMPREG(HDMI_TG_VACT_ST_L);
2895         DUMPREG(HDMI_TG_VACT_ST_H);
2896         DUMPREG(HDMI_TG_VACT_SZ_L);
2897         DUMPREG(HDMI_TG_VACT_SZ_H);
2898         DUMPREG(HDMI_TG_FIELD_CHG_L);
2899         DUMPREG(HDMI_TG_FIELD_CHG_H);
2900         DUMPREG(HDMI_TG_VACT_ST2_L);
2901         DUMPREG(HDMI_TG_VACT_ST2_H);
2902         DUMPREG(HDMI_TG_VACT_ST3_L);
2903         DUMPREG(HDMI_TG_VACT_ST3_H);
2904         DUMPREG(HDMI_TG_VACT_ST4_L);
2905         DUMPREG(HDMI_TG_VACT_ST4_H);
2906         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
2907         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
2908         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
2909         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
2910         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
2911         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
2912         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
2913         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
2914         DUMPREG(HDMI_TG_3D);
2915
2916         dev_dbg(hdev->dev, "%s: ---- PACKET REGISTERS ----\n", prefix);
2917         DUMPREG(HDMI_AVI_CON);
2918         DUMPREG(HDMI_AVI_HEADER0);
2919         DUMPREG(HDMI_AVI_HEADER1);
2920         DUMPREG(HDMI_AVI_HEADER2);
2921         DUMPREG(HDMI_AVI_CHECK_SUM);
2922         DUMPREG(HDMI_AVI_BYTE(1));
2923         DUMPREG(HDMI_VSI_CON);
2924         DUMPREG(HDMI_VSI_HEADER0);
2925         DUMPREG(HDMI_VSI_HEADER1);
2926         DUMPREG(HDMI_VSI_HEADER2);
2927         for (i = 0; i < 7; ++i)
2928                 DUMPREG(HDMI_VSI_DATA(i));
2929
2930 #undef DUMPREG
2931 }