2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
25 #include <linux/moduleparam.h>
26 #include <linux/time.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/clk.h>
32 #include <media/v4l2-common.h>
33 #include <media/v4l2-dev.h>
34 #include <media/videobuf2-core.h>
35 #include <media/videobuf2-dma-contig.h>
36 #include <media/soc_camera.h>
37 #include <media/soc_mediabus.h>
39 #include <linux/videodev2.h>
41 #include <mach/mx2_cam.h>
42 #include <mach/hardware.h>
46 #define MX2_CAM_DRV_NAME "mx2-camera"
47 #define MX2_CAM_VERSION "0.0.6"
48 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
51 #define CSICR1_RESET_VAL 0x40000800
52 #define CSICR2_RESET_VAL 0x0
53 #define CSICR3_RESET_VAL 0x0
55 /* csi control reg 1 */
56 #define CSICR1_SWAP16_EN (1 << 31)
57 #define CSICR1_EXT_VSYNC (1 << 30)
58 #define CSICR1_EOF_INTEN (1 << 29)
59 #define CSICR1_PRP_IF_EN (1 << 28)
60 #define CSICR1_CCIR_MODE (1 << 27)
61 #define CSICR1_COF_INTEN (1 << 26)
62 #define CSICR1_SF_OR_INTEN (1 << 25)
63 #define CSICR1_RF_OR_INTEN (1 << 24)
64 #define CSICR1_STATFF_LEVEL (3 << 22)
65 #define CSICR1_STATFF_INTEN (1 << 21)
66 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
67 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
68 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
69 #define CSICR1_RXFF_INTEN (1 << 18)
70 #define CSICR1_SOF_POL (1 << 17)
71 #define CSICR1_SOF_INTEN (1 << 16)
72 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
73 #define CSICR1_HSYNC_POL (1 << 11)
74 #define CSICR1_CCIR_EN (1 << 10)
75 #define CSICR1_MCLKEN (1 << 9)
76 #define CSICR1_FCC (1 << 8)
77 #define CSICR1_PACK_DIR (1 << 7)
78 #define CSICR1_CLR_STATFIFO (1 << 6)
79 #define CSICR1_CLR_RXFIFO (1 << 5)
80 #define CSICR1_GCLK_MODE (1 << 4)
81 #define CSICR1_INV_DATA (1 << 3)
82 #define CSICR1_INV_PCLK (1 << 2)
83 #define CSICR1_REDGE (1 << 1)
85 #define SHIFT_STATFF_LEVEL 22
86 #define SHIFT_RXFF_LEVEL 19
87 #define SHIFT_MCLKDIV 12
90 #define CSICR3_FRMCNT (0xFFFF << 16)
91 #define CSICR3_FRMCNT_RST (1 << 15)
92 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
93 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
94 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
95 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
96 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
97 #define CSICR3_CSI_SUP (1 << 3)
98 #define CSICR3_ZERO_PACK_EN (1 << 2)
99 #define CSICR3_ECC_INT_EN (1 << 1)
100 #define CSICR3_ECC_AUTO_EN (1 << 0)
102 #define SHIFT_FRMCNT 16
105 #define CSISR_SFF_OR_INT (1 << 25)
106 #define CSISR_RFF_OR_INT (1 << 24)
107 #define CSISR_STATFF_INT (1 << 21)
108 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
109 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
110 #define CSISR_RXFF_INT (1 << 18)
111 #define CSISR_EOF_INT (1 << 17)
112 #define CSISR_SOF_INT (1 << 16)
113 #define CSISR_F2_INT (1 << 15)
114 #define CSISR_F1_INT (1 << 14)
115 #define CSISR_COF_INT (1 << 13)
116 #define CSISR_ECC_INT (1 << 1)
117 #define CSISR_DRDY (1 << 0)
121 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
122 #define CSISTATFIFO 0x0c
123 #define CSIRFIFO 0x10
124 #define CSIRXCNT 0x14
125 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
126 #define CSIDMASA_STATFIFO 0x20
127 #define CSIDMATA_STATFIFO 0x24
128 #define CSIDMASA_FB1 0x28
129 #define CSIDMASA_FB2 0x2c
130 #define CSIFBUF_PARA 0x30
131 #define CSIIMAG_PARA 0x34
134 #define PRP_CNTL 0x00
135 #define PRP_INTR_CNTL 0x04
136 #define PRP_INTRSTATUS 0x08
137 #define PRP_SOURCE_Y_PTR 0x0c
138 #define PRP_SOURCE_CB_PTR 0x10
139 #define PRP_SOURCE_CR_PTR 0x14
140 #define PRP_DEST_RGB1_PTR 0x18
141 #define PRP_DEST_RGB2_PTR 0x1c
142 #define PRP_DEST_Y_PTR 0x20
143 #define PRP_DEST_CB_PTR 0x24
144 #define PRP_DEST_CR_PTR 0x28
145 #define PRP_SRC_FRAME_SIZE 0x2c
146 #define PRP_DEST_CH1_LINE_STRIDE 0x30
147 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
148 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
149 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
150 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
151 #define PRP_SRC_LINE_STRIDE 0x44
152 #define PRP_CSC_COEF_012 0x48
153 #define PRP_CSC_COEF_345 0x4c
154 #define PRP_CSC_COEF_678 0x50
155 #define PRP_CH1_RZ_HORI_COEF1 0x54
156 #define PRP_CH1_RZ_HORI_COEF2 0x58
157 #define PRP_CH1_RZ_HORI_VALID 0x5c
158 #define PRP_CH1_RZ_VERT_COEF1 0x60
159 #define PRP_CH1_RZ_VERT_COEF2 0x64
160 #define PRP_CH1_RZ_VERT_VALID 0x68
161 #define PRP_CH2_RZ_HORI_COEF1 0x6c
162 #define PRP_CH2_RZ_HORI_COEF2 0x70
163 #define PRP_CH2_RZ_HORI_VALID 0x74
164 #define PRP_CH2_RZ_VERT_COEF1 0x78
165 #define PRP_CH2_RZ_VERT_COEF2 0x7c
166 #define PRP_CH2_RZ_VERT_VALID 0x80
168 #define PRP_CNTL_CH1EN (1 << 0)
169 #define PRP_CNTL_CH2EN (1 << 1)
170 #define PRP_CNTL_CSIEN (1 << 2)
171 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
172 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
173 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
174 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
175 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
176 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
177 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
178 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
179 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
180 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
181 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
182 #define PRP_CNTL_CH1_LEN (1 << 9)
183 #define PRP_CNTL_CH2_LEN (1 << 10)
184 #define PRP_CNTL_SKIP_FRAME (1 << 11)
185 #define PRP_CNTL_SWRST (1 << 12)
186 #define PRP_CNTL_CLKEN (1 << 13)
187 #define PRP_CNTL_WEN (1 << 14)
188 #define PRP_CNTL_CH1BYP (1 << 15)
189 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
190 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
191 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
192 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
193 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
194 #define PRP_CNTL_CH2B1EN (1 << 29)
195 #define PRP_CNTL_CH2B2EN (1 << 30)
196 #define PRP_CNTL_CH2FEN (1 << 31)
198 /* IRQ Enable and status register */
199 #define PRP_INTR_RDERR (1 << 0)
200 #define PRP_INTR_CH1WERR (1 << 1)
201 #define PRP_INTR_CH2WERR (1 << 2)
202 #define PRP_INTR_CH1FC (1 << 3)
203 #define PRP_INTR_CH2FC (1 << 5)
204 #define PRP_INTR_LBOVF (1 << 7)
205 #define PRP_INTR_CH2OVF (1 << 8)
207 #define MAX_VIDEO_MEM 16
218 /* prp configuration for a client-host fmt pair */
220 enum v4l2_mbus_pixelcode in_fmt;
222 struct mx2_prp_cfg cfg;
225 enum mx2_buffer_state {
231 /* buffer for one video frame */
233 /* common v4l buffer stuff -- must be first */
234 struct vb2_buffer vb;
235 struct list_head queue;
236 enum mx2_buffer_state state;
242 struct mx2_camera_dev {
244 struct soc_camera_host soc_host;
245 struct soc_camera_device *icd;
246 struct clk *clk_csi, *clk_emma;
248 unsigned int irq_csi, irq_emma;
249 void __iomem *base_csi, *base_emma;
250 unsigned long base_dma;
252 struct mx2_camera_platform_data *pdata;
253 struct resource *res_csi, *res_emma;
254 unsigned long platform_flags;
256 struct list_head capture;
257 struct list_head active_bufs;
258 struct list_head discard;
263 struct mx2_buffer *active;
264 struct mx2_buffer *fb1_active;
265 struct mx2_buffer *fb2_active;
269 struct mx2_buffer buf_discard[2];
270 void *discard_buffer;
271 dma_addr_t discard_buffer_dma;
273 struct mx2_fmt_cfg *emma_prp;
275 struct vb2_alloc_ctx *alloc_ctx;
278 static struct mx2_fmt_cfg mx27_emma_prp_table[] = {
280 * This is a generic configuration which is valid for most
281 * prp input-output format combinations.
282 * We set the incomming and outgoing pixelformat to a
283 * 16 Bit wide format and adjust the bytesperline
284 * accordingly. With this configuration the inputdata
285 * will not be changed by the emma and could be any type
286 * of 16 Bit Pixelformat.
293 .in_fmt = PRP_CNTL_DATA_IN_RGB16,
294 .out_fmt = PRP_CNTL_CH1_OUT_RGB16,
295 .src_pixel = 0x2ca00565, /* RGB565 */
296 .ch1_pixel = 0x2ca00565, /* RGB565 */
297 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH1WERR |
298 PRP_INTR_CH1FC | PRP_INTR_LBOVF,
302 .in_fmt = V4L2_MBUS_FMT_YUYV8_2X8,
303 .out_fmt = V4L2_PIX_FMT_YUV420,
306 .in_fmt = PRP_CNTL_DATA_IN_YUV422,
307 .out_fmt = PRP_CNTL_CH2_OUT_YUV420,
308 .src_pixel = 0x22000888, /* YUV422 (YUYV) */
309 .irq_flags = PRP_INTR_RDERR | PRP_INTR_CH2WERR |
310 PRP_INTR_CH2FC | PRP_INTR_LBOVF |
316 static struct mx2_fmt_cfg *mx27_emma_prp_get_format(
317 enum v4l2_mbus_pixelcode in_fmt,
322 for (i = 1; i < ARRAY_SIZE(mx27_emma_prp_table); i++)
323 if ((mx27_emma_prp_table[i].in_fmt == in_fmt) &&
324 (mx27_emma_prp_table[i].out_fmt == out_fmt)) {
325 return &mx27_emma_prp_table[i];
327 /* If no match return the most generic configuration */
328 return &mx27_emma_prp_table[0];
331 static void mx27_update_emma_buf(struct mx2_camera_dev *pcdev,
332 unsigned long phys, int bufnum)
334 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
336 if (prp->cfg.channel == 1) {
337 writel(phys, pcdev->base_emma +
338 PRP_DEST_RGB1_PTR + 4 * bufnum);
340 writel(phys, pcdev->base_emma +
341 PRP_DEST_Y_PTR - 0x14 * bufnum);
342 if (prp->out_fmt == V4L2_PIX_FMT_YUV420) {
343 u32 imgsize = pcdev->icd->user_height *
344 pcdev->icd->user_width;
346 writel(phys + imgsize, pcdev->base_emma +
347 PRP_DEST_CB_PTR - 0x14 * bufnum);
348 writel(phys + ((5 * imgsize) / 4), pcdev->base_emma +
349 PRP_DEST_CR_PTR - 0x14 * bufnum);
354 static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
358 clk_disable(pcdev->clk_csi);
359 writel(0, pcdev->base_csi + CSICR1);
361 writel(0, pcdev->base_emma + PRP_CNTL);
362 } else if (cpu_is_mx25()) {
363 spin_lock_irqsave(&pcdev->lock, flags);
364 pcdev->fb1_active = NULL;
365 pcdev->fb2_active = NULL;
366 writel(0, pcdev->base_csi + CSIDMASA_FB1);
367 writel(0, pcdev->base_csi + CSIDMASA_FB2);
368 spin_unlock_irqrestore(&pcdev->lock, flags);
373 * The following two functions absolutely depend on the fact, that
374 * there can be only one camera on mx2 camera sensor interface
376 static int mx2_camera_add_device(struct soc_camera_device *icd)
378 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
379 struct mx2_camera_dev *pcdev = ici->priv;
386 ret = clk_enable(pcdev->clk_csi);
390 csicr1 = CSICR1_MCLKEN;
393 csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
394 CSICR1_RXFF_LEVEL(0);
395 } else if (cpu_is_mx27())
396 csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
398 pcdev->csicr1 = csicr1;
399 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
402 pcdev->frame_count = 0;
404 dev_info(icd->parent, "Camera driver attached to camera %d\n",
410 static void mx2_camera_remove_device(struct soc_camera_device *icd)
412 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
413 struct mx2_camera_dev *pcdev = ici->priv;
415 BUG_ON(icd != pcdev->icd);
417 dev_info(icd->parent, "Camera driver detached from camera %d\n",
420 mx2_camera_deactivate(pcdev);
425 static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
428 struct vb2_buffer *vb;
429 struct mx2_buffer *buf;
430 struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
432 u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
435 spin_lock_irqsave(&pcdev->lock, flags);
437 if (*fb_active == NULL)
440 vb = &(*fb_active)->vb;
441 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__,
442 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
444 do_gettimeofday(&vb->v4l2_buf.timestamp);
445 vb->v4l2_buf.sequence++;
446 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
448 if (list_empty(&pcdev->capture)) {
450 writel(0, pcdev->base_csi + fb_reg);
452 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
455 list_del(&buf->queue);
456 buf->state = MX2_STATE_ACTIVE;
457 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
458 pcdev->base_csi + fb_reg);
464 spin_unlock_irqrestore(&pcdev->lock, flags);
467 static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
469 struct mx2_camera_dev *pcdev = data;
470 u32 status = readl(pcdev->base_csi + CSISR);
472 if (status & CSISR_DMA_TSF_FB1_INT)
473 mx25_camera_frame_done(pcdev, 1, MX2_STATE_DONE);
474 else if (status & CSISR_DMA_TSF_FB2_INT)
475 mx25_camera_frame_done(pcdev, 2, MX2_STATE_DONE);
477 /* FIXME: handle CSISR_RFF_OR_INT */
479 writel(status, pcdev->base_csi + CSISR);
485 * Videobuf operations
487 static int mx2_videobuf_setup(struct vb2_queue *vq,
488 const struct v4l2_format *fmt,
489 unsigned int *count, unsigned int *num_planes,
490 unsigned int sizes[], void *alloc_ctxs[])
492 struct soc_camera_device *icd = soc_camera_from_vb2q(vq);
493 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
494 struct mx2_camera_dev *pcdev = ici->priv;
495 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
496 icd->current_fmt->host_fmt);
498 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, sizes[0]);
500 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
504 if (bytes_per_line < 0)
505 return bytes_per_line;
507 alloc_ctxs[0] = pcdev->alloc_ctx;
509 sizes[0] = bytes_per_line * icd->user_height;
514 sizes[0] * *count > MAX_VIDEO_MEM * 1024 * 1024)
515 *count = (MAX_VIDEO_MEM * 1024 * 1024) / sizes[0];
522 static int mx2_videobuf_prepare(struct vb2_buffer *vb)
524 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
525 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
526 icd->current_fmt->host_fmt);
529 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
530 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
532 if (bytes_per_line < 0)
533 return bytes_per_line;
537 * This can be useful if you want to see if we actually fill
538 * the buffer with something
540 memset((void *)vb2_plane_vaddr(vb, 0),
541 0xaa, vb2_get_plane_payload(vb, 0));
544 vb2_set_plane_payload(vb, 0, bytes_per_line * icd->user_height);
545 if (vb2_plane_vaddr(vb, 0) &&
546 vb2_get_plane_payload(vb, 0) > vb2_plane_size(vb, 0)) {
557 static void mx2_videobuf_queue(struct vb2_buffer *vb)
559 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
560 struct soc_camera_host *ici =
561 to_soc_camera_host(icd->parent);
562 struct mx2_camera_dev *pcdev = ici->priv;
563 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
566 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
567 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
569 spin_lock_irqsave(&pcdev->lock, flags);
571 buf->state = MX2_STATE_QUEUED;
572 list_add_tail(&buf->queue, &pcdev->capture);
575 u32 csicr3, dma_inten = 0;
577 if (pcdev->fb1_active == NULL) {
578 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
579 pcdev->base_csi + CSIDMASA_FB1);
580 pcdev->fb1_active = buf;
581 dma_inten = CSICR1_FB1_DMA_INTEN;
582 } else if (pcdev->fb2_active == NULL) {
583 writel(vb2_dma_contig_plane_dma_addr(vb, 0),
584 pcdev->base_csi + CSIDMASA_FB2);
585 pcdev->fb2_active = buf;
586 dma_inten = CSICR1_FB2_DMA_INTEN;
590 list_del(&buf->queue);
591 buf->state = MX2_STATE_ACTIVE;
593 csicr3 = readl(pcdev->base_csi + CSICR3);
596 writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
597 pcdev->base_csi + CSICR3);
599 /* clear & enable interrupts */
600 writel(dma_inten, pcdev->base_csi + CSISR);
601 pcdev->csicr1 |= dma_inten;
602 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
605 csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
606 writel(csicr3, pcdev->base_csi + CSICR3);
610 spin_unlock_irqrestore(&pcdev->lock, flags);
613 static void mx2_videobuf_release(struct vb2_buffer *vb)
615 struct soc_camera_device *icd = soc_camera_from_vb2q(vb->vb2_queue);
616 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
617 struct mx2_camera_dev *pcdev = ici->priv;
618 struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
622 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
623 vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
625 switch (buf->state) {
626 case MX2_STATE_ACTIVE:
627 dev_info(icd->parent, "%s (active)\n", __func__);
629 case MX2_STATE_QUEUED:
630 dev_info(icd->parent, "%s (queued)\n", __func__);
633 dev_info(icd->parent, "%s (unknown) %d\n", __func__,
640 * Terminate only queued but inactive buffers. Active buffers are
641 * released when they become inactive after videobuf_waiton().
643 * FIXME: implement forced termination of active buffers for mx27 and
644 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
645 * state. This requires a specific handling for each of the these DMA
649 spin_lock_irqsave(&pcdev->lock, flags);
650 if (cpu_is_mx25() && buf->state == MX2_STATE_ACTIVE) {
651 if (pcdev->fb1_active == buf) {
652 pcdev->csicr1 &= ~CSICR1_FB1_DMA_INTEN;
653 writel(0, pcdev->base_csi + CSIDMASA_FB1);
654 pcdev->fb1_active = NULL;
655 } else if (pcdev->fb2_active == buf) {
656 pcdev->csicr1 &= ~CSICR1_FB2_DMA_INTEN;
657 writel(0, pcdev->base_csi + CSIDMASA_FB2);
658 pcdev->fb2_active = NULL;
660 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
662 spin_unlock_irqrestore(&pcdev->lock, flags);
665 static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
668 struct soc_camera_host *ici =
669 to_soc_camera_host(icd->parent);
670 struct mx2_camera_dev *pcdev = ici->priv;
671 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
673 writel((icd->user_width << 16) | icd->user_height,
674 pcdev->base_emma + PRP_SRC_FRAME_SIZE);
675 writel(prp->cfg.src_pixel,
676 pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
677 if (prp->cfg.channel == 1) {
678 writel((icd->user_width << 16) | icd->user_height,
679 pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
681 pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
682 writel(prp->cfg.ch1_pixel,
683 pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
684 } else { /* channel 2 */
685 writel((icd->user_width << 16) | icd->user_height,
686 pcdev->base_emma + PRP_CH2_OUT_IMAGE_SIZE);
689 /* Enable interrupts */
690 writel(prp->cfg.irq_flags, pcdev->base_emma + PRP_INTR_CNTL);
693 static int mx2_start_streaming(struct vb2_queue *q, unsigned int count)
695 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
696 struct soc_camera_host *ici =
697 to_soc_camera_host(icd->parent);
698 struct mx2_camera_dev *pcdev = ici->priv;
699 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
700 struct vb2_buffer *vb;
701 struct mx2_buffer *buf;
710 spin_lock_irqsave(&pcdev->lock, flags);
712 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
716 buf->state = MX2_STATE_ACTIVE;
718 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
719 mx27_update_emma_buf(pcdev, phys, buf->bufnum);
720 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
722 buf = list_first_entry(&pcdev->capture, struct mx2_buffer,
726 buf->state = MX2_STATE_ACTIVE;
728 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
729 mx27_update_emma_buf(pcdev, phys, buf->bufnum);
730 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
732 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
733 icd->current_fmt->host_fmt);
734 if (bytesperline < 0)
738 * I didn't manage to properly enable/disable the prp
739 * on a per frame basis during running transfers,
740 * thus we allocate a buffer here and use it to
741 * discard frames when no buffer is available.
742 * Feel free to work on this ;)
744 pcdev->discard_size = icd->user_height * bytesperline;
745 pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
746 pcdev->discard_size, &pcdev->discard_buffer_dma,
748 if (!pcdev->discard_buffer)
751 pcdev->buf_discard[0].discard = true;
752 list_add_tail(&pcdev->buf_discard[0].queue,
755 pcdev->buf_discard[1].discard = true;
756 list_add_tail(&pcdev->buf_discard[1].queue,
759 mx27_camera_emma_buf_init(icd, bytesperline);
761 if (prp->cfg.channel == 1) {
762 writel(PRP_CNTL_CH1EN |
768 PRP_CNTL_CH1_TSKIP(0) |
769 PRP_CNTL_IN_TSKIP(0),
770 pcdev->base_emma + PRP_CNTL);
772 writel(PRP_CNTL_CH2EN |
777 PRP_CNTL_CH2_TSKIP(0) |
778 PRP_CNTL_IN_TSKIP(0),
779 pcdev->base_emma + PRP_CNTL);
781 spin_unlock_irqrestore(&pcdev->lock, flags);
787 static int mx2_stop_streaming(struct vb2_queue *q)
789 struct soc_camera_device *icd = soc_camera_from_vb2q(q);
790 struct soc_camera_host *ici =
791 to_soc_camera_host(icd->parent);
792 struct mx2_camera_dev *pcdev = ici->priv;
793 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
799 spin_lock_irqsave(&pcdev->lock, flags);
801 cntl = readl(pcdev->base_emma + PRP_CNTL);
802 if (prp->cfg.channel == 1) {
803 writel(cntl & ~PRP_CNTL_CH1EN,
804 pcdev->base_emma + PRP_CNTL);
806 writel(cntl & ~PRP_CNTL_CH2EN,
807 pcdev->base_emma + PRP_CNTL);
809 INIT_LIST_HEAD(&pcdev->capture);
810 INIT_LIST_HEAD(&pcdev->active_bufs);
811 INIT_LIST_HEAD(&pcdev->discard);
813 b = pcdev->discard_buffer;
814 pcdev->discard_buffer = NULL;
816 spin_unlock_irqrestore(&pcdev->lock, flags);
818 dma_free_coherent(ici->v4l2_dev.dev,
819 pcdev->discard_size, b, pcdev->discard_buffer_dma);
825 static struct vb2_ops mx2_videobuf_ops = {
826 .queue_setup = mx2_videobuf_setup,
827 .buf_prepare = mx2_videobuf_prepare,
828 .buf_queue = mx2_videobuf_queue,
829 .buf_cleanup = mx2_videobuf_release,
830 .start_streaming = mx2_start_streaming,
831 .stop_streaming = mx2_stop_streaming,
834 static int mx2_camera_init_videobuf(struct vb2_queue *q,
835 struct soc_camera_device *icd)
837 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
838 q->io_modes = VB2_MMAP | VB2_USERPTR;
840 q->ops = &mx2_videobuf_ops;
841 q->mem_ops = &vb2_dma_contig_memops;
842 q->buf_struct_size = sizeof(struct mx2_buffer);
844 return vb2_queue_init(q);
847 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
848 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
849 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
850 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
851 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
852 V4L2_MBUS_PCLK_SAMPLE_RISING | \
853 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
854 V4L2_MBUS_DATA_ACTIVE_HIGH | \
855 V4L2_MBUS_DATA_ACTIVE_LOW)
857 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
862 cntl = readl(pcdev->base_emma + PRP_CNTL);
863 writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
864 while (count++ < 100) {
865 if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
874 static int mx2_camera_set_bus_param(struct soc_camera_device *icd)
876 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
877 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
878 struct mx2_camera_dev *pcdev = ici->priv;
879 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
880 unsigned long common_flags;
883 u32 csicr1 = pcdev->csicr1;
885 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
887 common_flags = soc_mbus_config_compatible(&cfg, MX2_BUS_FLAGS);
889 dev_warn(icd->parent,
890 "Flags incompatible: camera 0x%x, host 0x%x\n",
891 cfg.flags, MX2_BUS_FLAGS);
894 } else if (ret != -ENOIOCTLCMD) {
897 common_flags = MX2_BUS_FLAGS;
900 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
901 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
902 if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
903 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
905 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
908 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
909 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
910 if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
911 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
913 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
916 cfg.flags = common_flags;
917 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
918 if (ret < 0 && ret != -ENOIOCTLCMD) {
919 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
924 if (common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
925 csicr1 |= CSICR1_REDGE;
926 if (common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
927 csicr1 |= CSICR1_SOF_POL;
928 if (common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
929 csicr1 |= CSICR1_HSYNC_POL;
930 if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
931 csicr1 |= CSICR1_SWAP16_EN;
932 if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
933 csicr1 |= CSICR1_EXT_VSYNC;
934 if (pcdev->platform_flags & MX2_CAMERA_CCIR)
935 csicr1 |= CSICR1_CCIR_EN;
936 if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
937 csicr1 |= CSICR1_CCIR_MODE;
938 if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
939 csicr1 |= CSICR1_GCLK_MODE;
940 if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
941 csicr1 |= CSICR1_INV_DATA;
942 if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
943 csicr1 |= CSICR1_PACK_DIR;
945 pcdev->csicr1 = csicr1;
947 bytesperline = soc_mbus_bytes_per_line(icd->user_width,
948 icd->current_fmt->host_fmt);
949 if (bytesperline < 0)
953 ret = mx27_camera_emma_prp_reset(pcdev);
956 } else if (cpu_is_mx25()) {
957 writel((bytesperline * icd->user_height) >> 2,
958 pcdev->base_csi + CSIRXCNT);
959 writel((bytesperline << 16) | icd->user_height,
960 pcdev->base_csi + CSIIMAG_PARA);
963 writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
968 static int mx2_camera_set_crop(struct soc_camera_device *icd,
971 struct v4l2_rect *rect = &a->c;
972 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
973 struct v4l2_mbus_framefmt mf;
976 soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
977 soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
979 ret = v4l2_subdev_call(sd, video, s_crop, a);
983 /* The capture device might have changed its output */
984 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
988 dev_dbg(icd->parent, "Sensor cropped %dx%d\n",
989 mf.width, mf.height);
991 icd->user_width = mf.width;
992 icd->user_height = mf.height;
997 static int mx2_camera_get_formats(struct soc_camera_device *icd,
999 struct soc_camera_format_xlate *xlate)
1001 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1002 const struct soc_mbus_pixelfmt *fmt;
1003 struct device *dev = icd->parent;
1004 enum v4l2_mbus_pixelcode code;
1005 int ret, formats = 0;
1007 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1009 /* no more formats */
1012 fmt = soc_mbus_get_fmtdesc(code);
1014 dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
1018 if (code == V4L2_MBUS_FMT_YUYV8_2X8) {
1022 * CH2 can output YUV420 which is a standard format in
1026 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8);
1028 dev_dbg(dev, "Providing host format %s for sensor code %d\n",
1029 xlate->host_fmt->name, code);
1034 /* Generic pass-trough */
1037 xlate->host_fmt = fmt;
1044 static int mx2_camera_set_fmt(struct soc_camera_device *icd,
1045 struct v4l2_format *f)
1047 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1048 struct mx2_camera_dev *pcdev = ici->priv;
1049 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1050 const struct soc_camera_format_xlate *xlate;
1051 struct v4l2_pix_format *pix = &f->fmt.pix;
1052 struct v4l2_mbus_framefmt mf;
1055 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1057 dev_warn(icd->parent, "Format %x not found\n",
1062 mf.width = pix->width;
1063 mf.height = pix->height;
1064 mf.field = pix->field;
1065 mf.colorspace = pix->colorspace;
1066 mf.code = xlate->code;
1068 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1069 if (ret < 0 && ret != -ENOIOCTLCMD)
1072 if (mf.code != xlate->code)
1075 pix->width = mf.width;
1076 pix->height = mf.height;
1077 pix->field = mf.field;
1078 pix->colorspace = mf.colorspace;
1079 icd->current_fmt = xlate;
1082 pcdev->emma_prp = mx27_emma_prp_get_format(xlate->code,
1083 xlate->host_fmt->fourcc);
1088 static int mx2_camera_try_fmt(struct soc_camera_device *icd,
1089 struct v4l2_format *f)
1091 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1092 const struct soc_camera_format_xlate *xlate;
1093 struct v4l2_pix_format *pix = &f->fmt.pix;
1094 struct v4l2_mbus_framefmt mf;
1095 __u32 pixfmt = pix->pixelformat;
1096 unsigned int width_limit;
1099 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1100 if (pixfmt && !xlate) {
1101 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1105 /* FIXME: implement MX27 limits */
1107 /* limit to MX25 hardware capabilities */
1108 if (cpu_is_mx25()) {
1109 if (xlate->host_fmt->bits_per_sample <= 8)
1110 width_limit = 0xffff * 4;
1112 width_limit = 0xffff * 2;
1113 /* CSIIMAG_PARA limit */
1114 if (pix->width > width_limit)
1115 pix->width = width_limit;
1116 if (pix->height > 0xffff)
1117 pix->height = 0xffff;
1119 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1121 if (pix->bytesperline < 0)
1122 return pix->bytesperline;
1123 pix->sizeimage = pix->height * pix->bytesperline;
1124 /* Check against the CSIRXCNT limit */
1125 if (pix->sizeimage > 4 * 0x3ffff) {
1126 /* Adjust geometry, preserve aspect ratio */
1127 unsigned int new_height = int_sqrt(4 * 0x3ffff *
1128 pix->height / pix->bytesperline);
1129 pix->width = new_height * pix->width / pix->height;
1130 pix->height = new_height;
1131 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1133 BUG_ON(pix->bytesperline < 0);
1137 /* limit to sensor capabilities */
1138 mf.width = pix->width;
1139 mf.height = pix->height;
1140 mf.field = pix->field;
1141 mf.colorspace = pix->colorspace;
1142 mf.code = xlate->code;
1144 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1148 if (mf.field == V4L2_FIELD_ANY)
1149 mf.field = V4L2_FIELD_NONE;
1151 * Driver supports interlaced images provided they have
1152 * both fields so that they can be processed as if they
1155 if (mf.field != V4L2_FIELD_NONE && !V4L2_FIELD_HAS_BOTH(mf.field)) {
1156 dev_err(icd->parent, "Field type %d unsupported.\n",
1161 pix->width = mf.width;
1162 pix->height = mf.height;
1163 pix->field = mf.field;
1164 pix->colorspace = mf.colorspace;
1169 static int mx2_camera_querycap(struct soc_camera_host *ici,
1170 struct v4l2_capability *cap)
1172 /* cap->name is set by the friendly caller:-> */
1173 strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
1174 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1179 static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
1181 struct soc_camera_device *icd = file->private_data;
1183 return vb2_poll(&icd->vb2_vidq, file, pt);
1186 static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
1187 .owner = THIS_MODULE,
1188 .add = mx2_camera_add_device,
1189 .remove = mx2_camera_remove_device,
1190 .set_fmt = mx2_camera_set_fmt,
1191 .set_crop = mx2_camera_set_crop,
1192 .get_formats = mx2_camera_get_formats,
1193 .try_fmt = mx2_camera_try_fmt,
1194 .init_videobuf2 = mx2_camera_init_videobuf,
1195 .poll = mx2_camera_poll,
1196 .querycap = mx2_camera_querycap,
1197 .set_bus_param = mx2_camera_set_bus_param,
1200 static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
1201 int bufnum, bool err)
1203 struct mx2_fmt_cfg *prp = pcdev->emma_prp;
1204 struct mx2_buffer *buf;
1205 struct vb2_buffer *vb;
1208 buf = list_first_entry(&pcdev->active_bufs, struct mx2_buffer, queue);
1210 BUG_ON(buf->bufnum != bufnum);
1214 * Discard buffer must not be returned to user space.
1215 * Just return it to the discard queue.
1217 list_move_tail(pcdev->active_bufs.next, &pcdev->discard);
1221 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1222 if (prp->cfg.channel == 1) {
1223 if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR +
1224 4 * bufnum) != phys) {
1225 dev_err(pcdev->dev, "%p != %p\n", phys,
1226 readl(pcdev->base_emma +
1231 if (readl(pcdev->base_emma + PRP_DEST_Y_PTR -
1232 0x14 * bufnum) != phys) {
1233 dev_err(pcdev->dev, "%p != %p\n", phys,
1234 readl(pcdev->base_emma +
1240 dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%p %lu\n", __func__, vb,
1241 vb2_plane_vaddr(vb, 0),
1242 vb2_get_plane_payload(vb, 0));
1244 list_del_init(&buf->queue);
1245 do_gettimeofday(&vb->v4l2_buf.timestamp);
1246 vb->v4l2_buf.sequence = pcdev->frame_count;
1248 vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
1250 vb2_buffer_done(vb, VB2_BUF_STATE_DONE);
1253 pcdev->frame_count++;
1255 if (list_empty(&pcdev->capture)) {
1256 if (list_empty(&pcdev->discard)) {
1257 dev_warn(pcdev->dev, "%s: trying to access empty discard list\n",
1262 buf = list_first_entry(&pcdev->discard, struct mx2_buffer,
1264 buf->bufnum = bufnum;
1266 list_move_tail(pcdev->discard.next, &pcdev->active_bufs);
1267 mx27_update_emma_buf(pcdev, pcdev->discard_buffer_dma, bufnum);
1271 buf = list_first_entry(&pcdev->capture, struct mx2_buffer, queue);
1273 buf->bufnum = bufnum;
1275 list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
1278 buf->state = MX2_STATE_ACTIVE;
1280 phys = vb2_dma_contig_plane_dma_addr(vb, 0);
1281 mx27_update_emma_buf(pcdev, phys, bufnum);
1284 static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
1286 struct mx2_camera_dev *pcdev = data;
1287 unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
1288 struct mx2_buffer *buf;
1289 unsigned long flags;
1291 spin_lock_irqsave(&pcdev->lock, flags);
1293 if (list_empty(&pcdev->active_bufs)) {
1294 dev_warn(pcdev->dev, "%s: called while active list is empty\n",
1299 if (status & (1 << 7)) { /* overflow */
1300 u32 cntl = readl(pcdev->base_emma + PRP_CNTL);
1301 writel(cntl & ~(PRP_CNTL_CH1EN | PRP_CNTL_CH2EN),
1302 pcdev->base_emma + PRP_CNTL);
1303 writel(cntl, pcdev->base_emma + PRP_CNTL);
1305 buf = list_first_entry(&pcdev->active_bufs,
1306 struct mx2_buffer, queue);
1307 mx27_camera_frame_done_emma(pcdev,
1310 status &= ~(1 << 7);
1311 } else if (((status & (3 << 5)) == (3 << 5)) ||
1312 ((status & (3 << 3)) == (3 << 3))) {
1314 * Both buffers have triggered, process the one we're expecting
1317 buf = list_first_entry(&pcdev->active_bufs, struct mx2_buffer,
1319 mx27_camera_frame_done_emma(pcdev, buf->bufnum, false);
1320 status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
1321 } else if ((status & (1 << 6)) || (status & (1 << 4))) {
1322 mx27_camera_frame_done_emma(pcdev, 0, false);
1323 } else if ((status & (1 << 5)) || (status & (1 << 3))) {
1324 mx27_camera_frame_done_emma(pcdev, 1, false);
1328 spin_unlock_irqrestore(&pcdev->lock, flags);
1329 writel(status, pcdev->base_emma + PRP_INTRSTATUS);
1334 static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
1336 struct resource *res_emma = pcdev->res_emma;
1339 if (!request_mem_region(res_emma->start, resource_size(res_emma),
1340 MX2_CAM_DRV_NAME)) {
1345 pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
1346 if (!pcdev->base_emma) {
1351 err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
1352 MX2_CAM_DRV_NAME, pcdev);
1354 dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
1358 pcdev->clk_emma = clk_get(NULL, "emma");
1359 if (IS_ERR(pcdev->clk_emma)) {
1360 err = PTR_ERR(pcdev->clk_emma);
1364 clk_enable(pcdev->clk_emma);
1366 err = mx27_camera_emma_prp_reset(pcdev);
1368 goto exit_clk_emma_put;
1373 clk_disable(pcdev->clk_emma);
1374 clk_put(pcdev->clk_emma);
1376 free_irq(pcdev->irq_emma, pcdev);
1378 iounmap(pcdev->base_emma);
1380 release_mem_region(res_emma->start, resource_size(res_emma));
1385 static int __devinit mx2_camera_probe(struct platform_device *pdev)
1387 struct mx2_camera_dev *pcdev;
1388 struct resource *res_csi, *res_emma;
1389 void __iomem *base_csi;
1390 int irq_csi, irq_emma;
1393 dev_dbg(&pdev->dev, "initialising\n");
1395 res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1396 irq_csi = platform_get_irq(pdev, 0);
1397 if (res_csi == NULL || irq_csi < 0) {
1398 dev_err(&pdev->dev, "Missing platform resources data\n");
1403 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1405 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1410 pcdev->clk_csi = clk_get(&pdev->dev, NULL);
1411 if (IS_ERR(pcdev->clk_csi)) {
1412 err = PTR_ERR(pcdev->clk_csi);
1416 dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
1417 clk_get_rate(pcdev->clk_csi));
1419 pcdev->res_csi = res_csi;
1420 pcdev->pdata = pdev->dev.platform_data;
1424 pcdev->platform_flags = pcdev->pdata->flags;
1426 rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
1431 err = clk_set_rate(pcdev->clk_csi, rate);
1436 INIT_LIST_HEAD(&pcdev->capture);
1437 INIT_LIST_HEAD(&pcdev->active_bufs);
1438 INIT_LIST_HEAD(&pcdev->discard);
1439 spin_lock_init(&pcdev->lock);
1442 * Request the regions.
1444 if (!request_mem_region(res_csi->start, resource_size(res_csi),
1445 MX2_CAM_DRV_NAME)) {
1450 base_csi = ioremap(res_csi->start, resource_size(res_csi));
1455 pcdev->irq_csi = irq_csi;
1456 pcdev->base_csi = base_csi;
1457 pcdev->base_dma = res_csi->start;
1458 pcdev->dev = &pdev->dev;
1460 if (cpu_is_mx25()) {
1461 err = request_irq(pcdev->irq_csi, mx25_camera_irq, 0,
1462 MX2_CAM_DRV_NAME, pcdev);
1464 dev_err(pcdev->dev, "Camera interrupt register failed \n");
1469 if (cpu_is_mx27()) {
1471 res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1472 irq_emma = platform_get_irq(pdev, 1);
1474 if (!res_emma || !irq_emma) {
1475 dev_err(&pdev->dev, "no EMMA resources\n");
1479 pcdev->res_emma = res_emma;
1480 pcdev->irq_emma = irq_emma;
1481 if (mx27_camera_emma_init(pcdev))
1485 pcdev->soc_host.drv_name = MX2_CAM_DRV_NAME,
1486 pcdev->soc_host.ops = &mx2_soc_camera_host_ops,
1487 pcdev->soc_host.priv = pcdev;
1488 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1489 pcdev->soc_host.nr = pdev->id;
1491 pcdev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1492 if (IS_ERR(pcdev->alloc_ctx)) {
1493 err = PTR_ERR(pcdev->alloc_ctx);
1496 err = soc_camera_host_register(&pcdev->soc_host);
1498 goto exit_free_emma;
1500 dev_info(&pdev->dev, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1501 clk_get_rate(pcdev->clk_csi));
1506 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1508 if (cpu_is_mx27()) {
1509 free_irq(pcdev->irq_emma, pcdev);
1510 clk_disable(pcdev->clk_emma);
1511 clk_put(pcdev->clk_emma);
1512 iounmap(pcdev->base_emma);
1513 release_mem_region(pcdev->res_emma->start, resource_size(pcdev->res_emma));
1517 free_irq(pcdev->irq_csi, pcdev);
1521 release_mem_region(res_csi->start, resource_size(res_csi));
1523 clk_put(pcdev->clk_csi);
1530 static int __devexit mx2_camera_remove(struct platform_device *pdev)
1532 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1533 struct mx2_camera_dev *pcdev = container_of(soc_host,
1534 struct mx2_camera_dev, soc_host);
1535 struct resource *res;
1537 clk_put(pcdev->clk_csi);
1539 free_irq(pcdev->irq_csi, pcdev);
1541 free_irq(pcdev->irq_emma, pcdev);
1543 soc_camera_host_unregister(&pcdev->soc_host);
1545 vb2_dma_contig_cleanup_ctx(pcdev->alloc_ctx);
1547 iounmap(pcdev->base_csi);
1549 if (cpu_is_mx27()) {
1550 clk_disable(pcdev->clk_emma);
1551 clk_put(pcdev->clk_emma);
1552 iounmap(pcdev->base_emma);
1553 res = pcdev->res_emma;
1554 release_mem_region(res->start, resource_size(res));
1557 res = pcdev->res_csi;
1558 release_mem_region(res->start, resource_size(res));
1562 dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
1567 static struct platform_driver mx2_camera_driver = {
1569 .name = MX2_CAM_DRV_NAME,
1571 .remove = __devexit_p(mx2_camera_remove),
1575 static int __init mx2_camera_init(void)
1577 return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
1580 static void __exit mx2_camera_exit(void)
1582 return platform_driver_unregister(&mx2_camera_driver);
1585 module_init(mx2_camera_init);
1586 module_exit(mx2_camera_exit);
1588 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1589 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1590 MODULE_LICENSE("GPL");
1591 MODULE_VERSION(MX2_CAM_VERSION);