2 * Samsung S5P Multi Format Codec v 5.1
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <linux/workqueue.h>
23 #include <media/videobuf2-core.h>
24 #include "s5p_mfc_common.h"
25 #include "s5p_mfc_ctrl.h"
26 #include "s5p_mfc_debug.h"
27 #include "s5p_mfc_dec.h"
28 #include "s5p_mfc_enc.h"
29 #include "s5p_mfc_intr.h"
30 #include "s5p_mfc_pm.h"
31 #ifdef CONFIG_EXYNOS_IOMMU
32 #include <mach/sysmmu.h>
33 #include <linux/of_platform.h>
36 #define S5P_MFC_NAME "s5p-mfc"
37 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
38 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
41 module_param(debug, int, S_IRUGO | S_IWUSR);
42 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
44 /* Helper functions for interrupt processing */
45 /* Remove from hw execution round robin */
46 static void clear_work_bit(struct s5p_mfc_ctx *ctx)
48 struct s5p_mfc_dev *dev = ctx->dev;
50 spin_lock(&dev->condlock);
51 clear_bit(ctx->num, &dev->ctx_work_bits);
52 spin_unlock(&dev->condlock);
55 /* Wake up context wait_queue */
56 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
60 ctx->int_type = reason;
65 /* Wake up device wait_queue */
66 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
70 dev->int_type = reason;
75 void s5p_mfc_watchdog(unsigned long arg)
77 struct s5p_mfc_dev *dev = (struct s5p_mfc_dev *)arg;
79 if (test_bit(0, &dev->hw_lock))
80 atomic_inc(&dev->watchdog_cnt);
81 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
82 /* This means that hw is busy and no interrupts were
83 * generated by hw for the Nth time of running this
84 * watchdog timer. This usually means a serious hw
85 * error. Now it is time to kill all instances and
87 mfc_err("Time out during waiting for HW\n");
88 queue_work(dev->watchdog_workqueue, &dev->watchdog_work);
90 dev->watchdog_timer.expires = jiffies +
91 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
92 add_timer(&dev->watchdog_timer);
95 static void s5p_mfc_watchdog_worker(struct work_struct *work)
97 struct s5p_mfc_dev *dev;
98 struct s5p_mfc_ctx *ctx;
103 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
105 mfc_err("Driver timeout error handling\n");
106 /* Lock the mutex that protects open and release.
107 * This is necessary as they may load and unload firmware. */
108 mutex_locked = mutex_trylock(&dev->mfc_mutex);
110 mfc_err("Error: some instance may be closing/opening\n");
111 spin_lock_irqsave(&dev->irqlock, flags);
115 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
119 ctx->state = MFCINST_ERROR;
120 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
121 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
123 wake_up_ctx(ctx, S5P_FIMV_R2H_CMD_ERR_RET, 0);
125 clear_bit(0, &dev->hw_lock);
126 spin_unlock_irqrestore(&dev->irqlock, flags);
127 /* Double check if there is at least one instance running.
128 * If no instance is in memory than no firmware should be present */
129 if (dev->num_inst > 0) {
130 ret = s5p_mfc_reload_firmware(dev);
132 mfc_err("Failed to reload FW\n");
136 ret = s5p_mfc_init_hw(dev);
138 mfc_err("Failed to reinit FW\n");
142 mutex_unlock(&dev->mfc_mutex);
145 static enum s5p_mfc_node_type s5p_mfc_get_node_type(struct file *file)
147 struct video_device *vdev = video_devdata(file);
150 mfc_err("failed to get video_device");
151 return MFCNODE_INVALID;
153 if (vdev->index == 0)
154 return MFCNODE_DECODER;
155 else if (vdev->index == 1)
156 return MFCNODE_ENCODER;
157 return MFCNODE_INVALID;
160 static void s5p_mfc_clear_int_flags(struct s5p_mfc_dev *dev)
163 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
164 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_INT);
166 mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT);
167 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
168 mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID);
172 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
174 struct s5p_mfc_buf *dst_buf;
176 ctx->state = MFCINST_FINISHED;
178 while (!list_empty(&ctx->dst_queue)) {
179 dst_buf = list_entry(ctx->dst_queue.next,
180 struct s5p_mfc_buf, list);
181 mfc_debug(2, "Cleaning up buffer: %d\n",
182 dst_buf->b->v4l2_buf.index);
183 vb2_set_plane_payload(dst_buf->b, 0, 0);
184 vb2_set_plane_payload(dst_buf->b, 1, 0);
185 list_del(&dst_buf->list);
186 ctx->dst_queue_cnt--;
187 dst_buf->b->v4l2_buf.sequence = (ctx->sequence++);
189 if (s5p_mfc_read_info(ctx, PIC_TIME_TOP) ==
190 s5p_mfc_read_info(ctx, PIC_TIME_BOT))
191 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
193 dst_buf->b->v4l2_buf.field = V4L2_FIELD_INTERLACED;
195 ctx->dec_dst_flag &= ~(1 << dst_buf->b->v4l2_buf.index);
196 vb2_buffer_done(dst_buf->b, VB2_BUF_STATE_DONE);
200 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
202 struct s5p_mfc_dev *dev = ctx->dev;
203 struct s5p_mfc_buf *dst_buf, *src_buf;
204 size_t dec_y_addr = s5p_mfc_get_dec_y_adr();
205 unsigned int frame_type = s5p_mfc_get_dec_frame_type();
207 /* Copy timestamp / timecode from decoded src to dst and set
209 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
210 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
211 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dec_y_addr) {
212 memcpy(&dst_buf->b->v4l2_buf.timecode,
213 &src_buf->b->v4l2_buf.timecode,
214 sizeof(struct v4l2_timecode));
215 memcpy(&dst_buf->b->v4l2_buf.timestamp,
216 &src_buf->b->v4l2_buf.timestamp,
217 sizeof(struct timeval));
218 switch (frame_type) {
219 case S5P_FIMV_DECODE_FRAME_I_FRAME:
220 dst_buf->b->v4l2_buf.flags |=
221 V4L2_BUF_FLAG_KEYFRAME;
223 case S5P_FIMV_DECODE_FRAME_P_FRAME:
224 dst_buf->b->v4l2_buf.flags |=
225 V4L2_BUF_FLAG_PFRAME;
227 case S5P_FIMV_DECODE_FRAME_B_FRAME:
228 dst_buf->b->v4l2_buf.flags |=
229 V4L2_BUF_FLAG_BFRAME;
237 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
239 struct s5p_mfc_dev *dev = ctx->dev;
240 struct s5p_mfc_buf *dst_buf;
241 size_t dspl_y_addr = s5p_mfc_get_dspl_y_adr();
242 unsigned int frame_type = s5p_mfc_get_disp_frame_type();
245 /* If frame is same as previous then skip and do not dequeue */
246 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
247 if (!ctx->after_packed_pb)
249 ctx->after_packed_pb = 0;
253 /* The MFC returns address of the buffer, now we have to
254 * check which videobuf does it correspond to */
255 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
256 /* Check if this is the buffer we're looking for */
257 if (vb2_dma_contig_plane_dma_addr(dst_buf->b, 0) == dspl_y_addr) {
258 list_del(&dst_buf->list);
259 ctx->dst_queue_cnt--;
260 dst_buf->b->v4l2_buf.sequence = ctx->sequence;
261 if (s5p_mfc_read_info(ctx, PIC_TIME_TOP) ==
262 s5p_mfc_read_info(ctx, PIC_TIME_BOT))
263 dst_buf->b->v4l2_buf.field = V4L2_FIELD_NONE;
265 dst_buf->b->v4l2_buf.field =
266 V4L2_FIELD_INTERLACED;
267 vb2_set_plane_payload(dst_buf->b, 0, ctx->luma_size);
268 vb2_set_plane_payload(dst_buf->b, 1, ctx->chroma_size);
269 clear_bit(dst_buf->b->v4l2_buf.index,
272 vb2_buffer_done(dst_buf->b,
273 err ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
275 index = dst_buf->b->v4l2_buf.index;
281 /* Handle frame decoding interrupt */
282 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
283 unsigned int reason, unsigned int err)
285 struct s5p_mfc_dev *dev = ctx->dev;
286 unsigned int dst_frame_status;
287 struct s5p_mfc_buf *src_buf;
289 unsigned int res_change;
293 dst_frame_status = s5p_mfc_get_dspl_status()
294 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
295 res_change = (s5p_mfc_get_dspl_status()
296 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
297 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
298 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
299 if (ctx->state == MFCINST_RES_CHANGE_INIT)
300 ctx->state = MFCINST_RES_CHANGE_FLUSH;
301 if (res_change && res_change != 3) {
302 ctx->state = MFCINST_RES_CHANGE_INIT;
303 s5p_mfc_clear_int_flags(dev);
304 wake_up_ctx(ctx, reason, err);
305 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
308 s5p_mfc_try_run(dev);
314 spin_lock_irqsave(&dev->irqlock, flags);
315 /* All frames remaining in the buffer have been extracted */
316 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
317 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
318 s5p_mfc_handle_frame_all_extracted(ctx);
319 ctx->state = MFCINST_RES_CHANGE_END;
320 goto leave_handle_frame;
322 s5p_mfc_handle_frame_all_extracted(ctx);
326 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY ||
327 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_ONLY)
328 s5p_mfc_handle_frame_copy_time(ctx);
330 /* A frame has been decoded and is in the buffer */
331 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
332 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
333 s5p_mfc_handle_frame_new(ctx, err);
335 mfc_debug(2, "No frame decode\n");
337 /* Mark source buffer as complete */
338 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
339 && !list_empty(&ctx->src_queue)) {
340 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
342 ctx->consumed_stream += s5p_mfc_get_consumed_stream();
344 if (ctx->codec_mode != S5P_FIMV_CODEC_H264_DEC &&
345 s5p_mfc_get_dec_frame_type() == S5P_FIMV_DECODE_FRAME_P_FRAME
346 && ctx->consumed_stream + STUFF_BYTE <
347 src_buf->b->v4l2_planes[0].bytesused) {
348 /* Run MFC again on the same buffer */
349 mfc_debug(2, "Running again the same buffer\n");
350 ctx->after_packed_pb = 1;
354 index = src_buf->b->v4l2_buf.index;
355 mfc_debug(2, "MFC needs next buffer\n");
356 ctx->consumed_stream = 0;
357 list_del(&src_buf->list);
358 ctx->src_queue_cnt--;
359 if (s5p_mfc_err_dec(err) > 0)
360 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_ERROR);
362 vb2_buffer_done(src_buf->b, VB2_BUF_STATE_DONE);
366 spin_unlock_irqrestore(&dev->irqlock, flags);
367 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
368 || ctx->dst_queue_cnt < ctx->dpb_count)
370 s5p_mfc_clear_int_flags(dev);
371 wake_up_ctx(ctx, reason, err);
372 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
375 s5p_mfc_try_run(dev);
378 /* Error handling for interrupt */
379 static void s5p_mfc_handle_error(struct s5p_mfc_ctx *ctx,
380 unsigned int reason, unsigned int err)
382 struct s5p_mfc_dev *dev;
385 /* If no context is available then all necessary
386 * processing has been done. */
391 mfc_err("Interrupt Error: %08x\n", err);
392 s5p_mfc_clear_int_flags(dev);
393 wake_up_dev(dev, reason, err);
395 /* Error recovery is dependent on the state of context */
396 switch (ctx->state) {
398 /* This error had to happen while acquireing instance */
399 case MFCINST_GOT_INST:
400 /* This error had to happen while parsing the header */
401 case MFCINST_HEAD_PARSED:
402 /* This error had to happen while setting dst buffers */
403 case MFCINST_RETURN_INST:
404 /* This error had to happen while releasing instance */
406 wake_up_ctx(ctx, reason, err);
407 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
410 ctx->state = MFCINST_ERROR;
412 case MFCINST_FINISHING:
413 case MFCINST_FINISHED:
414 case MFCINST_RUNNING:
415 /* It is higly probable that an error occured
416 * while decoding a frame */
418 ctx->state = MFCINST_ERROR;
419 /* Mark all dst buffers as having an error */
420 spin_lock_irqsave(&dev->irqlock, flags);
421 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
422 /* Mark all src buffers as having an error */
423 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
424 spin_unlock_irqrestore(&dev->irqlock, flags);
425 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
430 mfc_err("Encountered an error interrupt which had not been handled\n");
436 /* Header parsing interrupt handling */
437 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
438 unsigned int reason, unsigned int err)
440 struct s5p_mfc_dev *dev;
445 if (ctx->c_ops->post_seq_start) {
446 if (ctx->c_ops->post_seq_start(ctx))
447 mfc_err("post_seq_start() failed\n");
449 ctx->img_width = s5p_mfc_get_img_width();
450 ctx->img_height = s5p_mfc_get_img_height();
452 s5p_mfc_dec_calc_dpb_size(ctx);
454 ctx->dpb_count = s5p_mfc_get_dpb_count();
455 ctx->mv_count = s5p_mfc_get_mv_count();
456 if (ctx->img_width == 0 || ctx->img_height == 0)
457 ctx->state = MFCINST_ERROR;
459 ctx->state = MFCINST_HEAD_PARSED;
461 if ((ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
462 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC) &&
463 !list_empty(&ctx->src_queue)) {
464 struct s5p_mfc_buf *src_buf;
465 src_buf = list_entry(ctx->src_queue.next,
466 struct s5p_mfc_buf, list);
467 mfc_debug(2, "Check consumed size of header. ");
468 mfc_debug(2, "source : %d, consumed : %d\n",
469 s5p_mfc_get_consumed_stream(),
470 src_buf->b->v4l2_planes[0].bytesused);
471 if (s5p_mfc_get_consumed_stream() <
472 src_buf->b->v4l2_planes[0].bytesused)
476 s5p_mfc_clear_int_flags(dev);
478 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
481 s5p_mfc_try_run(dev);
482 wake_up_ctx(ctx, reason, err);
485 /* Header parsing interrupt handling */
486 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
487 unsigned int reason, unsigned int err)
489 struct s5p_mfc_buf *src_buf;
490 struct s5p_mfc_dev *dev;
496 s5p_mfc_clear_int_flags(dev);
497 ctx->int_type = reason;
500 spin_lock(&dev->condlock);
501 clear_bit(ctx->num, &dev->ctx_work_bits);
502 spin_unlock(&dev->condlock);
504 ctx->state = MFCINST_RUNNING;
505 if (!ctx->dpb_flush && !ctx->remained) {
506 spin_lock_irqsave(&dev->irqlock, flags);
507 if (!list_empty(&ctx->src_queue)) {
508 src_buf = list_entry(ctx->src_queue.next,
509 struct s5p_mfc_buf, list);
510 list_del(&src_buf->list);
511 ctx->src_queue_cnt--;
512 vb2_buffer_done(src_buf->b,
515 spin_unlock_irqrestore(&dev->irqlock, flags);
519 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
524 wake_up(&ctx->queue);
525 s5p_mfc_try_run(dev);
527 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
532 wake_up(&ctx->queue);
536 /* Interrupt processing */
537 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
539 struct s5p_mfc_dev *dev = priv;
540 struct s5p_mfc_ctx *ctx;
545 /* Reset the timeout watchdog */
546 atomic_set(&dev->watchdog_cnt, 0);
547 ctx = dev->ctx[dev->curr_ctx];
548 /* Get the reason of interrupt and the error code */
549 reason = s5p_mfc_get_int_reason();
550 err = s5p_mfc_get_int_err();
551 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
553 case S5P_FIMV_R2H_CMD_ERR_RET:
554 /* An error has occured */
555 if (ctx->state == MFCINST_RUNNING) {
556 if (s5p_mfc_err_dec(err) >= S5P_FIMV_ERR_WARNINGS_START)
557 s5p_mfc_handle_frame(ctx, reason, err);
559 s5p_mfc_handle_error(ctx, reason, err);
561 s5p_mfc_handle_error(ctx, reason, err);
563 clear_bit(0, &dev->enter_suspend);
566 case S5P_FIMV_R2H_CMD_SLICE_DONE_RET:
567 case S5P_FIMV_R2H_CMD_FIELD_DONE_RET:
568 case S5P_FIMV_R2H_CMD_FRAME_DONE_RET:
569 if (ctx->c_ops->post_frame_start) {
570 if (ctx->c_ops->post_frame_start(ctx))
571 mfc_err("post_frame_start() failed\n");
572 s5p_mfc_clear_int_flags(dev);
573 wake_up_ctx(ctx, reason, err);
574 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
577 s5p_mfc_try_run(dev);
579 s5p_mfc_handle_frame(ctx, reason, err);
583 case S5P_FIMV_R2H_CMD_SEQ_DONE_RET:
584 s5p_mfc_handle_seq_done(ctx, reason, err);
587 case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET:
588 ctx->inst_no = s5p_mfc_get_inst_no();
589 ctx->state = MFCINST_GOT_INST;
591 wake_up(&ctx->queue);
594 case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET:
596 ctx->state = MFCINST_FREE;
597 wake_up(&ctx->queue);
600 case S5P_FIMV_R2H_CMD_SYS_INIT_RET:
601 case S5P_FIMV_R2H_CMD_FW_STATUS_RET:
602 case S5P_FIMV_R2H_CMD_SLEEP_RET:
603 case S5P_FIMV_R2H_CMD_WAKEUP_RET:
606 s5p_mfc_clear_int_flags(dev);
607 wake_up_dev(dev, reason, err);
608 clear_bit(0, &dev->hw_lock);
609 clear_bit(0, &dev->enter_suspend);
612 case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET:
613 s5p_mfc_handle_init_buffers(ctx, reason, err);
616 mfc_debug(2, "Unknown int reason\n");
617 s5p_mfc_clear_int_flags(dev);
622 s5p_mfc_clear_int_flags(dev);
623 ctx->int_type = reason;
626 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
627 mfc_err("Failed to unlock hw\n");
631 s5p_mfc_try_run(dev);
632 mfc_debug(2, "Exit via irq_cleanup_hw\n");
636 /* Open an MFC node */
637 static int s5p_mfc_open(struct file *file)
639 struct s5p_mfc_dev *dev = video_drvdata(file);
640 struct s5p_mfc_ctx *ctx = NULL;
646 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
647 /* Allocate memory for context */
648 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
650 mfc_err("Not enough memory\n");
654 v4l2_fh_init(&ctx->fh, video_devdata(file));
655 file->private_data = &ctx->fh;
656 v4l2_fh_add(&ctx->fh);
658 INIT_LIST_HEAD(&ctx->src_queue);
659 INIT_LIST_HEAD(&ctx->dst_queue);
660 ctx->src_queue_cnt = 0;
661 ctx->dst_queue_cnt = 0;
662 /* Get context number */
664 while (dev->ctx[ctx->num]) {
666 if (ctx->num >= MFC_NUM_CONTEXTS) {
667 mfc_err("Too many open contexts\n");
672 /* Mark context as idle */
673 spin_lock_irqsave(&dev->condlock, flags);
674 clear_bit(ctx->num, &dev->ctx_work_bits);
675 spin_unlock_irqrestore(&dev->condlock, flags);
676 dev->ctx[ctx->num] = ctx;
677 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
678 ctx->type = MFCINST_DECODER;
679 ctx->c_ops = get_dec_codec_ops();
680 s5p_mfc_dec_init(ctx);
681 /* Setup ctrl handler */
682 ret = s5p_mfc_dec_ctrls_setup(ctx);
684 mfc_err("Failed to setup mfc controls\n");
685 goto err_dec_ctrls_setup;
687 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
688 ctx->type = MFCINST_ENCODER;
689 ctx->c_ops = get_enc_codec_ops();
690 /* only for encoder */
691 INIT_LIST_HEAD(&ctx->ref_queue);
692 ctx->ref_queue_cnt = 0;
693 s5p_mfc_enc_init(ctx);
696 * MFC encoder control setup fails as of now. Hence in this driver
697 * we are not supporting the encoder
700 /* Setup ctrl handler */
701 ret = s5p_mfc_enc_ctrls_setup(ctx);
703 mfc_err("Failed to setup mfc controls\n");
704 goto err_enc_ctrls_setup;
711 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
713 /* Load firmware if this is the first instance */
714 if (dev->num_inst == 1) {
715 dev->watchdog_timer.expires = jiffies +
716 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
717 add_timer(&dev->watchdog_timer);
718 ret = s5p_mfc_power_on();
720 mfc_err("power on failed\n");
724 ret = s5p_mfc_alloc_and_load_firmware(dev);
728 ret = s5p_mfc_init_hw(dev);
733 /* Init videobuf2 queue for CAPTURE */
735 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
736 q->drv_priv = &ctx->fh;
737 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
738 q->io_modes = VB2_MMAP;
739 q->ops = get_dec_queue_ops();
740 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
741 q->io_modes = VB2_MMAP | VB2_USERPTR;
742 q->ops = get_enc_queue_ops();
747 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
748 ret = vb2_queue_init(q);
750 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
753 /* Init videobuf2 queue for OUTPUT */
755 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
756 q->io_modes = VB2_MMAP;
757 q->drv_priv = &ctx->fh;
758 if (s5p_mfc_get_node_type(file) == MFCNODE_DECODER) {
759 q->io_modes = VB2_MMAP;
760 q->ops = get_dec_queue_ops();
761 } else if (s5p_mfc_get_node_type(file) == MFCNODE_ENCODER) {
762 q->io_modes = VB2_MMAP | VB2_USERPTR;
763 q->ops = get_enc_queue_ops();
768 q->mem_ops = (struct vb2_mem_ops *)&vb2_dma_contig_memops;
769 ret = vb2_queue_init(q);
771 mfc_err("Failed to initialize videobuf2 queue(output)\n");
774 init_waitqueue_head(&ctx->queue);
777 /* Deinit when failure occured */
780 s5p_mfc_release_firmware(dev);
782 dev->ctx[ctx->num] = 0;
783 del_timer_sync(&dev->watchdog_timer);
786 if (dev->num_inst == 1) {
787 if (s5p_mfc_power_off() < 0)
788 mfc_err("power off failed\n");
789 s5p_mfc_release_firmware(dev);
792 s5p_mfc_dec_ctrls_delete(ctx);
796 s5p_mfc_enc_ctrls_delete(ctx);
799 v4l2_fh_del(&ctx->fh);
800 v4l2_fh_exit(&ctx->fh);
808 /* Release MFC context */
809 static int s5p_mfc_release(struct file *file)
811 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
812 struct s5p_mfc_dev *dev = ctx->dev;
817 vb2_queue_release(&ctx->vq_src);
818 vb2_queue_release(&ctx->vq_dst);
819 /* Mark context as idle */
820 spin_lock_irqsave(&dev->condlock, flags);
821 clear_bit(ctx->num, &dev->ctx_work_bits);
822 spin_unlock_irqrestore(&dev->condlock, flags);
823 /* If instance was initialised then
824 * return instance and free reosurces */
825 if (ctx->inst_no != MFC_NO_INSTANCE_SET) {
826 mfc_debug(2, "Has to free instance\n");
827 ctx->state = MFCINST_RETURN_INST;
828 spin_lock_irqsave(&dev->condlock, flags);
829 set_bit(ctx->num, &dev->ctx_work_bits);
830 spin_unlock_irqrestore(&dev->condlock, flags);
831 s5p_mfc_clean_ctx_int_flags(ctx);
832 s5p_mfc_try_run(dev);
833 /* Wait until instance is returned or timeout occured */
834 if (s5p_mfc_wait_for_done_ctx
835 (ctx, S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET, 0)) {
837 mfc_err("Err returning instance\n");
839 mfc_debug(2, "After free instance\n");
841 s5p_mfc_release_codec_buffers(ctx);
842 s5p_mfc_release_instance_buffer(ctx);
843 if (ctx->type == MFCINST_DECODER)
844 s5p_mfc_release_dec_desc_buffer(ctx);
846 ctx->inst_no = MFC_NO_INSTANCE_SET;
848 /* hardware locking scheme */
849 if (dev->curr_ctx == ctx->num)
850 clear_bit(0, &dev->hw_lock);
852 if (dev->num_inst == 0) {
853 mfc_debug(2, "Last instance - release firmware\n");
854 /* reset <-> F/W release */
856 s5p_mfc_release_firmware(dev);
857 del_timer_sync(&dev->watchdog_timer);
858 if (s5p_mfc_power_off() < 0)
859 mfc_err("Power off failed\n");
861 mfc_debug(2, "Shutting down clock\n");
863 dev->ctx[ctx->num] = 0;
864 s5p_mfc_dec_ctrls_delete(ctx);
865 s5p_mfc_enc_ctrls_delete(ctx);
866 v4l2_fh_del(&ctx->fh);
867 v4l2_fh_exit(&ctx->fh);
874 static unsigned int s5p_mfc_poll(struct file *file,
875 struct poll_table_struct *wait)
877 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
878 struct s5p_mfc_dev *dev = ctx->dev;
879 struct vb2_queue *src_q, *dst_q;
880 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
884 src_q = &ctx->vq_src;
885 dst_q = &ctx->vq_dst;
887 * There has to be at least one buffer queued on each queued_list, which
888 * means either in driver already or waiting for driver to claim it
889 * and start processing.
891 if ((!src_q->streaming || list_empty(&src_q->queued_list))
892 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
896 mutex_unlock(&dev->mfc_mutex);
897 poll_wait(file, &src_q->done_wq, wait);
898 poll_wait(file, &dst_q->done_wq, wait);
899 mutex_lock(&dev->mfc_mutex);
900 spin_lock_irqsave(&src_q->done_lock, flags);
901 if (!list_empty(&src_q->done_list))
902 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
904 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
905 || src_vb->state == VB2_BUF_STATE_ERROR))
906 rc |= POLLOUT | POLLWRNORM;
907 spin_unlock_irqrestore(&src_q->done_lock, flags);
908 spin_lock_irqsave(&dst_q->done_lock, flags);
909 if (!list_empty(&dst_q->done_list))
910 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
912 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
913 || dst_vb->state == VB2_BUF_STATE_ERROR))
914 rc |= POLLIN | POLLRDNORM;
915 spin_unlock_irqrestore(&dst_q->done_lock, flags);
921 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
923 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
924 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
926 if (offset < DST_QUEUE_OFF_BASE) {
927 mfc_debug(2, "mmaping source\n");
928 ret = vb2_mmap(&ctx->vq_src, vma);
929 } else { /* capture */
930 mfc_debug(2, "mmaping destination\n");
931 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
932 ret = vb2_mmap(&ctx->vq_dst, vma);
938 static const struct v4l2_file_operations s5p_mfc_fops = {
939 .owner = THIS_MODULE,
940 .open = s5p_mfc_open,
941 .release = s5p_mfc_release,
942 .poll = s5p_mfc_poll,
943 .unlocked_ioctl = video_ioctl2,
944 .mmap = s5p_mfc_mmap,
947 #ifdef CONFIG_EXYNOS_IOMMU
948 static int iommu_init(struct platform_device *pdev,
949 struct device *mfc_l,
950 struct device *mfc_r)
952 struct platform_device *pds;
953 struct dma_iommu_mapping *mapping;
955 pds = find_sysmmu_dt(pdev, "sysmmu_l");
957 printk(KERN_ERR "no sysmmu_l found\n");
960 platform_set_sysmmu(&pds->dev, mfc_l);
961 mapping = s5p_create_iommu_mapping(mfc_l, 0x20000000,
963 if (mapping == NULL) {
964 printk(KERN_ERR "IOMMU mapping failed\n");
968 pds = find_sysmmu_dt(pdev, "sysmmu_r");
970 printk(KERN_ERR "no sysmmu_r found\n");
973 platform_set_sysmmu(&pds->dev, mfc_r);
974 if (!s5p_create_iommu_mapping(mfc_r, 0x20000000,
975 SZ_128M, 4, mapping)) {
976 printk(KERN_ERR "IOMMU mapping failed\n");
984 /* MFC probe function */
985 static int s5p_mfc_probe(struct platform_device *pdev)
987 struct s5p_mfc_dev *dev;
988 struct video_device *vfd;
989 struct resource *res;
992 pr_debug("%s++\n", __func__);
993 dev = kzalloc(sizeof *dev, GFP_KERNEL);
995 dev_err(&pdev->dev, "Not enough memory for MFC device\n");
999 spin_lock_init(&dev->irqlock);
1000 spin_lock_init(&dev->condlock);
1001 dev->plat_dev = pdev;
1002 if (!dev->plat_dev) {
1003 dev_err(&pdev->dev, "No platform data specified\n");
1008 ret = s5p_mfc_init_pm(dev);
1010 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1014 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1016 dev_err(&pdev->dev, "failed to get memory region resource\n");
1021 dev->mfc_mem = request_mem_region(res->start, resource_size(res),
1023 if (dev->mfc_mem == NULL) {
1024 dev_err(&pdev->dev, "failed to get memory region\n");
1028 dev->regs_base = ioremap(dev->mfc_mem->start, resource_size(dev->mfc_mem));
1029 if (dev->regs_base == NULL) {
1030 dev_err(&pdev->dev, "failed to ioremap address region\n");
1035 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1037 dev_err(&pdev->dev, "failed to get irq resource\n");
1041 dev->irq = res->start;
1042 ret = request_irq(dev->irq, s5p_mfc_irq, IRQF_DISABLED, pdev->name,
1045 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1049 dev->mem_dev_l = kzalloc(sizeof *dev, GFP_KERNEL);
1050 dev->mem_dev_r = kzalloc(sizeof *dev, GFP_KERNEL);
1051 #ifdef CONFIG_EXYNOS_IOMMU
1052 dev->mem_dev_l->init_name = "mfc_l";
1053 dev->mem_dev_r->init_name = "mfc_r";
1054 if (iommu_init(pdev, dev->mem_dev_r, dev->mem_dev_l)) {
1055 v4l2_err(&dev->v4l2_dev, "failed to initialize IOMMU\n");
1056 goto err_iommu_init;
1059 dev->alloc_ctx[0] = vb2_dma_contig_init_ctx(dev->mem_dev_l);
1060 if (IS_ERR_OR_NULL(dev->alloc_ctx[0])) {
1061 ret = PTR_ERR(dev->alloc_ctx[0]);
1062 goto err_mem_init_ctx_0;
1064 dev->alloc_ctx[1] = vb2_dma_contig_init_ctx(dev->mem_dev_r);
1065 if (IS_ERR_OR_NULL(dev->alloc_ctx[1])) {
1066 ret = PTR_ERR(dev->alloc_ctx[1]);
1067 goto err_mem_init_ctx_1;
1070 mutex_init(&dev->mfc_mutex);
1072 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1074 goto err_v4l2_dev_reg;
1075 init_waitqueue_head(&dev->queue);
1078 vfd = video_device_alloc();
1080 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1084 vfd->fops = &s5p_mfc_fops,
1085 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1086 vfd->release = video_device_release,
1087 vfd->lock = &dev->mfc_mutex;
1088 vfd->v4l2_dev = &dev->v4l2_dev;
1089 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1091 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1093 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1094 video_device_release(vfd);
1097 v4l2_info(&dev->v4l2_dev,
1098 "decoder registered as /dev/video%d\n", vfd->num);
1099 video_set_drvdata(vfd, dev);
1102 vfd = video_device_alloc();
1104 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1108 vfd->fops = &s5p_mfc_fops,
1109 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1110 vfd->release = video_device_release,
1111 vfd->lock = &dev->mfc_mutex;
1112 vfd->v4l2_dev = &dev->v4l2_dev;
1113 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1115 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
1117 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1118 video_device_release(vfd);
1121 v4l2_info(&dev->v4l2_dev,
1122 "encoder registered as /dev/video%d\n", vfd->num);
1123 video_set_drvdata(vfd, dev);
1124 platform_set_drvdata(pdev, dev);
1127 dev->watchdog_workqueue = create_singlethread_workqueue(S5P_MFC_NAME);
1128 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1129 atomic_set(&dev->watchdog_cnt, 0);
1130 init_timer(&dev->watchdog_timer);
1131 dev->watchdog_timer.data = (unsigned long)dev;
1132 dev->watchdog_timer.function = s5p_mfc_watchdog;
1134 dev->variant = (struct s5p_mfc_variant *)
1135 platform_get_device_id(pdev)->driver_data;
1137 pr_debug("%s--\n", __func__);
1140 /* Deinit MFC if probe had failed */
1142 video_device_release(dev->vfd_enc);
1144 video_unregister_device(dev->vfd_dec);
1146 video_device_release(dev->vfd_dec);
1148 v4l2_device_unregister(&dev->v4l2_dev);
1150 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1152 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1155 free_irq(dev->irq, dev);
1158 iounmap(dev->regs_base);
1159 dev->regs_base = NULL;
1161 release_resource(dev->mfc_mem);
1162 kfree(dev->mfc_mem);
1165 s5p_mfc_final_pm(dev);
1169 pr_debug("%s-- with error\n", __func__);
1174 /* Remove the driver */
1175 static int __devexit s5p_mfc_remove(struct platform_device *pdev)
1177 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1179 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1181 del_timer_sync(&dev->watchdog_timer);
1182 flush_workqueue(dev->watchdog_workqueue);
1183 destroy_workqueue(dev->watchdog_workqueue);
1185 video_unregister_device(dev->vfd_enc);
1186 video_unregister_device(dev->vfd_dec);
1187 v4l2_device_unregister(&dev->v4l2_dev);
1188 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[0]);
1189 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx[1]);
1191 free_irq(dev->irq, dev);
1192 iounmap(dev->regs_base);
1194 release_resource(dev->mfc_mem);
1195 kfree(dev->mfc_mem);
1196 dev->mfc_mem = NULL;
1198 s5p_mfc_final_pm(dev);
1203 #ifdef CONFIG_PM_SLEEP
1205 static int s5p_mfc_suspend(struct device *dev)
1207 struct platform_device *pdev = to_platform_device(dev);
1208 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1211 if (m_dev->num_inst == 0)
1213 return s5p_mfc_sleep(m_dev);
1214 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1215 mfc_err("Error: going to suspend for a second time\n");
1219 /* Check if we're processing then wait if it necessary. */
1220 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1221 /* Try and lock the HW */
1222 /* Wait on the interrupt waitqueue */
1223 ret = wait_event_interruptible_timeout(m_dev->queue,
1224 m_dev->int_cond || m_dev->ctx[m_dev->curr_ctx]->int_cond,
1225 msecs_to_jiffies(MFC_INT_TIMEOUT));
1228 mfc_err("Waiting for hardware to finish timed out\n");
1235 static int s5p_mfc_resume(struct device *dev)
1237 struct platform_device *pdev = to_platform_device(dev);
1238 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1240 if (m_dev->num_inst == 0)
1242 return s5p_mfc_wakeup(m_dev);
1246 #ifdef CONFIG_PM_RUNTIME
1247 static int s5p_mfc_runtime_suspend(struct device *dev)
1249 struct platform_device *pdev = to_platform_device(dev);
1250 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1252 atomic_set(&m_dev->pm.power, 0);
1256 static int s5p_mfc_runtime_resume(struct device *dev)
1258 struct platform_device *pdev = to_platform_device(dev);
1259 struct s5p_mfc_dev *m_dev = platform_get_drvdata(pdev);
1262 if (!m_dev->alloc_ctx)
1264 pre_power = atomic_read(&m_dev->pm.power);
1265 atomic_set(&m_dev->pm.power, 1);
1270 /* Power management */
1271 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1272 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1273 SET_RUNTIME_PM_OPS(s5p_mfc_runtime_suspend, s5p_mfc_runtime_resume,
1277 struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1278 .h264_ctx = 0x96000,
1279 .non_h264_ctx = 0x2800,
1284 struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1285 .dev_ctx = 0x7000, /* 28KB */
1286 .h264_dec_ctx = 0x200000, /* 1.6MB */
1287 .other_dec_ctx = 0x5000, /* 20KB */
1288 .h264_enc_ctx = 0x19000, /* 100KB */
1289 .other_enc_ctx = 0x3000, /* 12KB */
1292 struct s5p_mfc_buf_size buf_size_v5 = {
1294 .cpb = 0x400000, /* 4MB */
1295 .priv = &mfc_buf_size_v5,
1298 struct s5p_mfc_buf_size buf_size_v6 = {
1299 .fw = 0x100000, /* 1MB */
1300 .cpb = 0x300000, /* 3MB */
1301 .priv = &mfc_buf_size_v6,
1304 struct s5p_mfc_buf_align mfc_buf_align_v5 = {
1308 struct s5p_mfc_buf_align mfc_buf_align_v6 = {
1312 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1315 .buf_size = &buf_size_v5,
1316 .buf_align = &mfc_buf_align_v5,
1319 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1322 .buf_size = &buf_size_v6,
1323 .buf_align = &mfc_buf_align_v6,
1326 static struct platform_device_id mfc_driver_ids[] = {
1329 .driver_data = (unsigned long)&mfc_drvdata_v6,
1331 .name = "s5p-mfc-v5",
1332 .driver_data = (unsigned long)&mfc_drvdata_v5,
1334 .name = "s5p-mfc-v6",
1335 .driver_data = (unsigned long)&mfc_drvdata_v6,
1339 MODULE_DEVICE_TABLE(platform, mfc_driver_ids);
1340 static struct platform_driver s5p_mfc_driver = {
1341 .probe = s5p_mfc_probe,
1342 .remove = __devexit_p(s5p_mfc_remove),
1343 .id_table = mfc_driver_ids,
1345 .name = S5P_MFC_NAME,
1346 .owner = THIS_MODULE,
1347 .pm = &s5p_mfc_pm_ops
1351 module_platform_driver(s5p_mfc_driver);
1353 MODULE_LICENSE("GPL");
1354 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1355 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");