2 * linux/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c
4 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com/
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/delay.h>
14 #include <linux/err.h>
15 #include <linux/firmware.h>
16 #include <linux/jiffies.h>
17 #include <linux/sched.h>
18 #include "s5p_mfc_cmd.h"
19 #include "s5p_mfc_common.h"
20 #include "s5p_mfc_debug.h"
21 #include "s5p_mfc_intr.h"
22 #include "s5p_mfc_pm.h"
24 static void *s5p_mfc_bitproc_buf;
25 static size_t s5p_mfc_bitproc_phys;
26 static unsigned char *s5p_mfc_bitproc_virt;
28 /* Allocate and load firmware */
29 int s5p_mfc_alloc_and_load_firmware(struct s5p_mfc_dev *dev)
31 struct firmware *fw_blob;
32 size_t bank2_base_phys;
36 /* Firmare has to be present as a separate file or compiled
39 err = request_firmware((const struct firmware **)&fw_blob,
40 "mfc_fw.bin", dev->v4l2_dev.dev);
42 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
45 dev->fw_size = dev->variant->buf_size->fw;
46 if (s5p_mfc_bitproc_buf) {
47 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
48 release_firmware(fw_blob);
51 s5p_mfc_bitproc_buf = vb2_dma_contig_memops.alloc(
52 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], dev->fw_size);
53 if (IS_ERR(s5p_mfc_bitproc_buf)) {
54 s5p_mfc_bitproc_buf = 0;
55 mfc_err("Allocating bitprocessor buffer failed\n");
56 release_firmware(fw_blob);
59 s5p_mfc_bitproc_phys = s5p_mfc_mem_cookie(
60 dev->alloc_ctx[MFC_BANK1_ALLOC_CTX], s5p_mfc_bitproc_buf);
61 if (s5p_mfc_bitproc_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
62 mfc_err("The base memory for bank 1 is not aligned to 128KB\n");
63 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
64 s5p_mfc_bitproc_phys = 0;
65 s5p_mfc_bitproc_buf = 0;
66 release_firmware(fw_blob);
69 s5p_mfc_bitproc_virt = vb2_dma_contig_memops.vaddr(s5p_mfc_bitproc_buf);
70 if (!s5p_mfc_bitproc_virt) {
71 mfc_err("Bitprocessor memory remap failed\n");
72 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
73 s5p_mfc_bitproc_phys = 0;
74 s5p_mfc_bitproc_buf = 0;
75 release_firmware(fw_blob);
78 dev->bank1 = s5p_mfc_bitproc_phys;
79 if (HAS_PORTNUM(dev) && IS_TWOPORT(dev)) {
80 b_base = vb2_dma_contig_memops.alloc(
81 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], 1 << MFC_BANK2_ALIGN_ORDER);
83 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
84 s5p_mfc_bitproc_phys = 0;
85 s5p_mfc_bitproc_buf = 0;
86 mfc_err("Allocating bank2 base failed\n");
87 release_firmware(fw_blob);
90 bank2_base_phys = s5p_mfc_mem_cookie(
91 dev->alloc_ctx[MFC_BANK2_ALLOC_CTX], b_base);
92 vb2_dma_contig_memops.put(b_base);
93 if (bank2_base_phys & ((1 << MFC_BASE_ALIGN_ORDER) - 1)) {
94 mfc_err("The base memory for bank 2 is not aligned to 128KB\n");
95 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
96 s5p_mfc_bitproc_phys = 0;
97 s5p_mfc_bitproc_buf = 0;
98 release_firmware(fw_blob);
101 dev->bank2 = bank2_base_phys;
103 dev->bank2 = dev->bank1;
105 memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
107 release_firmware(fw_blob);
112 /* Reload firmware to MFC */
113 int s5p_mfc_reload_firmware(struct s5p_mfc_dev *dev)
115 struct firmware *fw_blob;
118 /* Firmare has to be present as a separate file or compiled
121 err = request_firmware((const struct firmware **)&fw_blob,
122 "mfc_fw.bin", dev->v4l2_dev.dev);
124 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
127 if (fw_blob->size > dev->fw_size) {
128 mfc_err("MFC firmware is too big to be loaded\n");
129 release_firmware(fw_blob);
132 if (s5p_mfc_bitproc_buf == 0 || s5p_mfc_bitproc_phys == 0) {
133 mfc_err("MFC firmware is not allocated or was not mapped correctly\n");
134 release_firmware(fw_blob);
137 memcpy(s5p_mfc_bitproc_virt, fw_blob->data, fw_blob->size);
139 release_firmware(fw_blob);
144 /* Release firmware memory */
145 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
147 /* Before calling this function one has to make sure
148 * that MFC is no longer processing */
149 if (!s5p_mfc_bitproc_buf)
151 vb2_dma_contig_memops.put(s5p_mfc_bitproc_buf);
152 s5p_mfc_bitproc_virt = 0;
153 s5p_mfc_bitproc_phys = 0;
154 s5p_mfc_bitproc_buf = 0;
158 /* Reset the device */
159 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
161 unsigned int mc_status;
162 unsigned long timeout;
169 /* except RISC, reset */
170 mfc_write(dev, 0xFEE, S5P_FIMV_MFC_RESET);
172 mfc_write(dev, 0x0, S5P_FIMV_MFC_RESET);
174 /* Zero Initialization of MFC registers */
175 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
176 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
177 mfc_write(dev, 0, S5P_FIMV_FW_VERSION);
179 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT; i++)
180 mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN + (i*4));
183 mfc_write(dev, 0, S5P_FIMV_RISC_ON);
184 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET);
185 mfc_write(dev, 0, S5P_FIMV_MFC_RESET);
189 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
190 /* All reset except for MC */
191 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
194 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
195 /* Check MC status */
197 if (time_after(jiffies, timeout)) {
198 mfc_err("Timeout while resetting MFC\n");
202 mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
204 } while (mc_status & 0x3);
206 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
207 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
214 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
217 mfc_write(dev, dev->bank1, S5P_FIMV_RISC_BASE_ADDRESS);
218 mfc_debug(2, "Base Address : %08x\n", dev->bank1);
220 mfc_write(dev, dev->bank1, S5P_FIMV_MC_DRAMBASE_ADR_A);
221 mfc_write(dev, dev->bank2, S5P_FIMV_MC_DRAMBASE_ADR_B);
222 mfc_debug(2, "Bank1: %08x, Bank2: %08x\n", dev->bank1, dev->bank2);
226 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
229 /* Zero initialization should be done before RESET.
230 * Nothing to do here. */
232 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
233 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
234 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
235 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
239 /* Initialize hardware */
240 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
246 if (!s5p_mfc_bitproc_buf)
250 mfc_debug(2, "MFC reset..\n");
252 ret = s5p_mfc_reset(dev);
254 mfc_err("Failed to reset MFC - timeout\n");
257 mfc_debug(2, "Done MFC reset..\n");
258 /* 1. Set DRAM base Addr */
259 s5p_mfc_init_memctrl(dev);
260 /* 2. Initialize registers of channel I/F */
261 s5p_mfc_clear_cmds(dev);
262 /* 3. Release reset signal to the RISC */
263 s5p_mfc_clean_dev_int_flags(dev);
265 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON);
267 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
268 mfc_debug(2, "Will now wait for completion of firmware transfer\n");
269 if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) {
270 mfc_err("Failed to load firmware\n");
275 s5p_mfc_clean_dev_int_flags(dev);
276 /* 4. Initialize firmware */
277 ret = s5p_mfc_sys_init_cmd(dev);
279 mfc_err("Failed to send command to MFC - timeout\n");
284 mfc_debug(2, "Ok, now will write a command to init the system\n");
285 if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SYS_INIT_RET)) {
286 mfc_err("Failed to load firmware\n");
292 if (dev->int_err != 0 || dev->int_type !=
293 S5P_FIMV_R2H_CMD_SYS_INIT_RET) {
295 mfc_err("Failed to init firmware - error: %d int: %d\n",
296 dev->int_err, dev->int_type);
301 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
302 mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
303 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
310 /* Deinitialize hardware */
311 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
317 s5p_mfc_release_dev_context_buffer(dev);
322 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
328 s5p_mfc_clean_dev_int_flags(dev);
329 ret = s5p_mfc_sleep_cmd(dev);
331 mfc_err("Failed to send command to MFC - timeout\n");
334 if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_SLEEP_RET)) {
335 mfc_err("Failed to sleep\n");
340 if (dev->int_err != 0 || dev->int_type !=
341 S5P_FIMV_R2H_CMD_SLEEP_RET) {
343 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
351 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
357 mfc_debug(2, "MFC reset..\n");
359 ret = s5p_mfc_reset(dev);
361 mfc_err("Failed to reset MFC - timeout\n");
364 mfc_debug(2, "Done MFC reset..\n");
365 /* 1. Set DRAM base Addr */
366 s5p_mfc_init_memctrl(dev);
367 /* 2. Initialize registers of channel I/F */
368 s5p_mfc_clear_cmds(dev);
369 s5p_mfc_clean_dev_int_flags(dev);
370 /* 3. Initialize firmware */
371 ret = s5p_mfc_wakeup_cmd(dev);
373 mfc_err("Failed to send command to MFC - timeout\n");
376 /* 4. Release reset signal to the RISC */
378 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON);
380 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
381 mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
382 if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) {
383 mfc_err("Failed to load firmware\n");
388 if (dev->int_err != 0 || dev->int_type !=
389 S5P_FIMV_R2H_CMD_WAKEUP_RET) {
391 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,