drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/host.h>
  31 #include <linux/mmc/mmc.h>
  32 #include <linux/mmc/dw_mmc.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/of.h>
  37 #include <linux/of_gpio.h>
  38
  39 #include "dw_mmc.h"
  40
  41 #define NUM_PINS(x) (x + 2)
  42
  43 /* Common flag combinations */
  44 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
  45                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  46                                  SDMMC_INT_EBE)
  47 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  48                                  SDMMC_INT_RESP_ERR)
  49 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  50                                  DW_MCI_CMD_ERROR_FLAGS  | SDMMC_INT_HLE)
  51 #define DW_MCI_SEND_STATUS      1
  52 #define DW_MCI_RECV_STATUS      2
  53 #define DW_MCI_DMA_THRESHOLD    16
  54
  55 #ifdef CONFIG_MMC_DW_IDMAC
  56 struct idmac_desc {
  57         u32             des0;   /* Control Descriptor */
  58 #define IDMAC_DES0_DIC  BIT(1)
  59 #define IDMAC_DES0_LD   BIT(2)
  60 #define IDMAC_DES0_FD   BIT(3)
  61 #define IDMAC_DES0_CH   BIT(4)
  62 #define IDMAC_DES0_ER   BIT(5)
  63 #define IDMAC_DES0_CES  BIT(30)
  64 #define IDMAC_DES0_OWN  BIT(31)
  65
  66         u32             des1;   /* Buffer sizes */
  67 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  68         ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  69
  70         u32             des2;   /* buffer 1 physical address */
  71
  72         u32             des3;   /* buffer 2 physical address */
  73 };
  74 #endif /* CONFIG_MMC_DW_IDMAC */
  75
  76 /**
  77  * struct dw_mci_slot - MMC slot state
  78  * @mmc: The mmc_host representing this slot.
  79  * @host: The MMC controller this slot is using.
  80  * @ctype: Card type for this slot.
  81  * @mrq: mmc_request currently being processed or waiting to be
  82  *      processed, or NULL when the slot is idle.
  83  * @queue_node: List node for placing this node in the @queue list of
  84  *      &struct dw_mci.
  85  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
  86  * @flags: Random state bits associated with the slot.
  87  * @id: Number of this slot.
  88  * @last_detect_state: Most recently observed card detect state.
  89  */
  90 struct dw_mci_slot {
  91         struct mmc_host         *mmc;
  92         struct dw_mci           *host;
  93         int                     wp_gpio;
  94         int                     cd_gpio;
  95
  96         u32                     ctype;
  97
  98         struct mmc_request      *mrq;
  99         struct list_head        queue_node;
 100
 101         unsigned int            clock;
 102         unsigned long           flags;
 103 #define DW_MMC_CARD_PRESENT     0
 104 #define DW_MMC_CARD_NEED_INIT   1
 105         int                     id;
 106         int                     last_detect_state;
 107         bool                    cd_gpio_active_low;
 108 };
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 167         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 168         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 169         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 170         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 171         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 172
 173         return 0;
 174 }
 175
 176 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 177 {
 178         return single_open(file, dw_mci_regs_show, inode->i_private);
 179 }
 180
 181 static const struct file_operations dw_mci_regs_fops = {
 182         .owner          = THIS_MODULE,
 183         .open           = dw_mci_regs_open,
 184         .read           = seq_read,
 185         .llseek         = seq_lseek,
 186         .release        = single_release,
 187 };
 188
 189 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 190 {
 191         struct mmc_host *mmc = slot->mmc;
 192         struct dw_mci *host = slot->host;
 193         struct dentry *root;
 194         struct dentry *node;
 195
 196         root = mmc->debugfs_root;
 197         if (!root)
 198                 return;
 199
 200         node = debugfs_create_file("regs", S_IRUSR, root, host,
 201                                    &dw_mci_regs_fops);
 202         if (!node)
 203                 goto err;
 204
 205         node = debugfs_create_file("req", S_IRUSR, root, slot,
 206                                    &dw_mci_req_fops);
 207         if (!node)
 208                 goto err;
 209
 210         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 211         if (!node)
 212                 goto err;
 213
 214         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 215                                   (u32 *)&host->pending_events);
 216         if (!node)
 217                 goto err;
 218
 219         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 220                                   (u32 *)&host->completed_events);
 221         if (!node)
 222                 goto err;
 223
 224         return;
 225
 226 err:
 227         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 228 }
 229 #endif /* defined(CONFIG_DEBUG_FS) */
 230
 231 static void dw_mci_set_timeout(struct dw_mci *host)
 232 {
 233         /* timeout (maximum) */
 234         mci_writel(host, TMOUT, 0xffffffff);
 235 }
 236
 237 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 238 {
 239         struct mmc_data *data;
 240         struct dw_mci_slot *slot = mmc_priv(mmc);
 241         u32 cmdr;
 242         cmd->error = -EINPROGRESS;
 243
 244         cmdr = cmd->opcode;
 245
 246         if (cmdr == MMC_STOP_TRANSMISSION)
 247                 cmdr |= SDMMC_CMD_STOP;
 248         else
 249                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 250
 251         if (cmd->flags & MMC_RSP_PRESENT) {
 252                 /* We expect a response, so set this bit */
 253                 cmdr |= SDMMC_CMD_RESP_EXP;
 254                 if (cmd->flags & MMC_RSP_136)
 255                         cmdr |= SDMMC_CMD_RESP_LONG;
 256         }
 257
 258         if (cmd->flags & MMC_RSP_CRC)
 259                 cmdr |= SDMMC_CMD_RESP_CRC;
 260
 261         data = cmd->data;
 262         if (data) {
 263                 cmdr |= SDMMC_CMD_DAT_EXP;
 264                 if (data->flags & MMC_DATA_STREAM)
 265                         cmdr |= SDMMC_CMD_STRM_MODE;
 266                 if (data->flags & MMC_DATA_WRITE)
 267                         cmdr |= SDMMC_CMD_DAT_WR;
 268         }
 269
 270         if (slot->host->drv_data->ctrl_type == DW_MCI_TYPE_EXYNOS5250)
 271                 if (SDMMC_CLKSEL_GET_SELCLK_DRV(mci_readl(slot->host, CLKSEL)))
 272                         cmdr |= SDMMC_USE_HOLD_REG;
 273
 274         return cmdr;
 275 }
 276
 277 static void dw_mci_start_command(struct dw_mci *host,
 278                                  struct mmc_command *cmd, u32 cmd_flags)
 279 {
 280         host->cmd = cmd;
 281         dev_vdbg(host->dev,
 282                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 283                  cmd->arg, cmd_flags);
 284
 285         mci_writel(host, CMDARG, cmd->arg);
 286         wmb();
 287
 288         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 289 }
 290
 291 static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
 292 {
 293         dw_mci_start_command(host, data->stop, host->stop_cmdr);
 294 }
 295
 296 /* DMA interface functions */
 297 static void dw_mci_stop_dma(struct dw_mci *host)
 298 {
 299         if (host->using_dma) {
 300                 host->dma_ops->stop(host);
 301                 host->dma_ops->cleanup(host);
 302         } else {
 303                 /* Data transfer was stopped by the interrupt handler */
 304                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 305         }
 306 }
 307
 308 static int dw_mci_get_dma_dir(struct mmc_data *data)
 309 {
 310         if (data->flags & MMC_DATA_WRITE)
 311                 return DMA_TO_DEVICE;
 312         else
 313                 return DMA_FROM_DEVICE;
 314 }
 315
 316 #ifdef CONFIG_MMC_DW_IDMAC
 317 static void dw_mci_dma_cleanup(struct dw_mci *host)
 318 {
 319         struct mmc_data *data = host->data;
 320
 321         if (data)
 322                 if (!data->host_cookie)
 323                         dma_unmap_sg(host->dev,
 324                                      data->sg,
 325                                      data->sg_len,
 326                                      dw_mci_get_dma_dir(data));
 327 }
 328
 329 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 330 {
 331         u32 temp;
 332
 333         /* Disable and reset the IDMAC interface */
 334         temp = mci_readl(host, CTRL);
 335         temp &= ~SDMMC_CTRL_USE_IDMAC;
 336         temp |= SDMMC_CTRL_DMA_RESET;
 337         mci_writel(host, CTRL, temp);
 338
 339         /* Stop the IDMAC running */
 340         temp = mci_readl(host, BMOD);
 341         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 342         mci_writel(host, BMOD, temp);
 343 }
 344
 345 static void dw_mci_idmac_complete_dma(struct dw_mci *host)
 346 {
 347         struct mmc_data *data = host->data;
 348
 349         dev_vdbg(host->dev, "DMA complete\n");
 350
 351         host->dma_ops->cleanup(host);
 352
 353         /*
 354          * If the card was removed, data will be NULL. No point in trying to
 355          * send the stop command or waiting for NBUSY in this case.
 356          */
 357         if (data) {
 358                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 359                 tasklet_schedule(&host->tasklet);
 360         }
 361 }
 362
 363 static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
 364                                     unsigned int sg_len)
 365 {
 366         int i;
 367         struct idmac_desc *desc = host->sg_cpu;
 368
 369         for (i = 0; i < sg_len; i++, desc++) {
 370                 unsigned int length = sg_dma_len(&data->sg[i]);
 371                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 372
 373                 /* Set the OWN bit and disable interrupts for this descriptor */
 374                 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
 375
 376                 /* Buffer length */
 377                 IDMAC_SET_BUFFER1_SIZE(desc, length);
 378
 379                 /* Physical address to DMA to/from */
 380                 desc->des2 = mem_addr;
 381         }
 382
 383         /* Set first descriptor */
 384         desc = host->sg_cpu;
 385         desc->des0 |= IDMAC_DES0_FD;
 386
 387         /* Set last descriptor */
 388         desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
 389         desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 390         desc->des0 |= IDMAC_DES0_LD;
 391
 392         wmb();
 393 }
 394
 395 static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 396 {
 397         u32 temp;
 398
 399         dw_mci_translate_sglist(host, host->data, sg_len);
 400
 401         /* Select IDMAC interface */
 402         temp = mci_readl(host, CTRL);
 403         temp |= SDMMC_CTRL_USE_IDMAC;
 404         mci_writel(host, CTRL, temp);
 405
 406         wmb();
 407
 408         /* Enable the IDMAC */
 409         temp = mci_readl(host, BMOD);
 410         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 411         mci_writel(host, BMOD, temp);
 412
 413         /* Start it running */
 414         mci_writel(host, PLDMND, 1);
 415 }
 416
 417 static int dw_mci_idmac_init(struct dw_mci *host)
 418 {
 419         struct idmac_desc *p;
 420         int i;
 421
 422         /* Number of descriptors in the ring buffer */
 423         host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
 424
 425         /* Forward link the descriptor list */
 426         for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
 427                 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
 428
 429         /* Set the last descriptor as the end-of-ring descriptor */
 430         p->des3 = host->sg_dma;
 431         p->des0 = IDMAC_DES0_ER;
 432
 433         mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
 434
 435         /* Mask out interrupts - get Tx & Rx complete only */
 436         mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
 437                    SDMMC_IDMAC_INT_TI);
 438
 439         /* Set the descriptor base address */
 440         mci_writel(host, DBADDR, host->sg_dma);
 441         return 0;
 442 }
 443
 444 static struct dw_mci_dma_ops dw_mci_idmac_ops = {
 445         .init = dw_mci_idmac_init,
 446         .start = dw_mci_idmac_start_dma,
 447         .stop = dw_mci_idmac_stop_dma,
 448         .complete = dw_mci_idmac_complete_dma,
 449         .cleanup = dw_mci_dma_cleanup,
 450 };
 451 #endif /* CONFIG_MMC_DW_IDMAC */
 452
 453 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 454                                    struct mmc_data *data,
 455                                    bool next)
 456 {
 457         struct scatterlist *sg;
 458         unsigned int i, sg_len;
 459
 460         if (!next && data->host_cookie)
 461                 return data->host_cookie;
 462
 463         /*
 464          * We don't do DMA on "complex" transfers, i.e. with
 465          * non-word-aligned buffers or lengths. Also, we don't bother
 466          * with all the DMA setup overhead for short transfers.
 467          */
 468         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 469                 return -EINVAL;
 470
 471         if (data->blksz & 3)
 472                 return -EINVAL;
 473
 474         for_each_sg(data->sg, sg, data->sg_len, i) {
 475                 if (sg->offset & 3 || sg->length & 3)
 476                         return -EINVAL;
 477         }
 478
 479         sg_len = dma_map_sg(host->dev,
 480                             data->sg,
 481                             data->sg_len,
 482                             dw_mci_get_dma_dir(data));
 483         if (sg_len == 0)
 484                 return -EINVAL;
 485
 486         if (next)
 487                 data->host_cookie = sg_len;
 488
 489         return sg_len;
 490 }
 491
 492 static void dw_mci_pre_req(struct mmc_host *mmc,
 493                            struct mmc_request *mrq,
 494                            bool is_first_req)
 495 {
 496         struct dw_mci_slot *slot = mmc_priv(mmc);
 497         struct mmc_data *data = mrq->data;
 498
 499         if (!slot->host->use_dma || !data)
 500                 return;
 501
 502         if (data->host_cookie) {
 503                 data->host_cookie = 0;
 504                 return;
 505         }
 506
 507         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 508                 data->host_cookie = 0;
 509 }
 510
 511 static void dw_mci_post_req(struct mmc_host *mmc,
 512                             struct mmc_request *mrq,
 513                             int err)
 514 {
 515         struct dw_mci_slot *slot = mmc_priv(mmc);
 516         struct mmc_data *data = mrq->data;
 517
 518         if (!slot->host->use_dma || !data)
 519                 return;
 520
 521         if (data->host_cookie)
 522                 dma_unmap_sg(slot->host->dev,
 523                              data->sg,
 524                              data->sg_len,
 525                              dw_mci_get_dma_dir(data));
 526         data->host_cookie = 0;
 527 }
 528
 529 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
 530 {
 531         int sg_len;
 532         u32 temp;
 533
 534         host->using_dma = 0;
 535
 536         /* If we don't have a channel, we can't do DMA */
 537         if (!host->use_dma)
 538                 return -ENODEV;
 539
 540         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
 541         if (sg_len < 0) {
 542                 host->dma_ops->stop(host);
 543                 return sg_len;
 544         }
 545
 546         host->using_dma = 1;
 547
 548         dev_vdbg(host->dev,
 549                  "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
 550                  (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
 551                  sg_len);
 552
 553         /* Enable the DMA interface */
 554         temp = mci_readl(host, CTRL);
 555         temp |= SDMMC_CTRL_DMA_ENABLE;
 556         mci_writel(host, CTRL, temp);
 557
 558         /* Disable RX/TX IRQs, let DMA handle it */
 559         temp = mci_readl(host, INTMASK);
 560         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
 561         mci_writel(host, INTMASK, temp);
 562
 563         host->dma_ops->start(host, sg_len);
 564
 565         return 0;
 566 }
 567
 568 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
 569 {
 570         u32 temp;
 571
 572         data->error = -EINPROGRESS;
 573
 574         WARN_ON(host->data);
 575         host->sg = NULL;
 576         host->data = data;
 577
 578         if (data->flags & MMC_DATA_READ)
 579                 host->dir_status = DW_MCI_RECV_STATUS;
 580         else
 581                 host->dir_status = DW_MCI_SEND_STATUS;
 582
 583         if (dw_mci_submit_data_dma(host, data)) {
 584                 int flags = SG_MITER_ATOMIC;
 585                 if (host->data->flags & MMC_DATA_READ)
 586                         flags |= SG_MITER_TO_SG;
 587                 else
 588                         flags |= SG_MITER_FROM_SG;
 589
 590                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 591                 host->sg = data->sg;
 592                 host->part_buf_start = 0;
 593                 host->part_buf_count = 0;
 594
 595                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
 596                 temp = mci_readl(host, INTMASK);
 597                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
 598                 mci_writel(host, INTMASK, temp);
 599
 600                 temp = mci_readl(host, CTRL);
 601                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
 602                 mci_writel(host, CTRL, temp);
 603         }
 604 }
 605
 606 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 607 {
 608         struct dw_mci *host = slot->host;
 609         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 610         unsigned int cmd_status = 0;
 611
 612         mci_writel(host, CMDARG, arg);
 613         wmb();
 614         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 615
 616         while (time_before(jiffies, timeout)) {
 617                 cmd_status = mci_readl(host, CMD);
 618                 if (!(cmd_status & SDMMC_CMD_START))
 619                         return;
 620         }
 621         dev_err(&slot->mmc->class_dev,
 622                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 623                 cmd, arg, cmd_status);
 624 }
 625
 626 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
 627 {
 628         struct dw_mci *host = slot->host;
 629         u32 div;
 630
 631         if (slot->clock != host->current_speed || force_clkinit) {
 632                 if (host->bus_hz % slot->clock)
 633                         /*
 634                          * move the + 1 after the divide to prevent
 635                          * over-clocking the card.
 636                          */
 637                         div = ((host->bus_hz / slot->clock) >> 1) + 1;
 638                 else
 639                         div = (host->bus_hz  / slot->clock) >> 1;
 640
 641                 dev_info(&slot->mmc->class_dev,
 642                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
 643                          " div = %d)\n", slot->id, host->bus_hz, slot->clock,
 644                          div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
 645
 646                 /* disable clock */
 647                 mci_writel(host, CLKENA, 0);
 648                 mci_writel(host, CLKSRC, 0);
 649
 650                 /* inform CIU */
 651                 mci_send_cmd(slot,
 652                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 653
 654                 /* set clock to desired speed */
 655                 mci_writel(host, CLKDIV, div);
 656
 657                 /* inform CIU */
 658                 mci_send_cmd(slot,
 659                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 660
 661                 /* enable clock */
 662                 mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
 663                            SDMMC_CLKEN_LOW_PWR) << slot->id));
 664
 665                 /* inform CIU */
 666                 mci_send_cmd(slot,
 667                              SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
 668
 669                 host->current_speed = slot->clock;
 670         }
 671
 672         /* Set the current slot bus width */
 673         mci_writel(host, CTYPE, (slot->ctype << slot->id));
 674 }
 675
 676 static void __dw_mci_start_request(struct dw_mci *host,
 677                                    struct dw_mci_slot *slot,
 678                                    struct mmc_command *cmd)
 679 {
 680         struct mmc_request *mrq;
 681         struct mmc_data *data;
 682         u32 cmdflags;
 683
 684         mrq = slot->mrq;
 685         if (host->pdata->select_slot)
 686                 host->pdata->select_slot(slot->id);
 687
 688         /* Slot specific timing and width adjustment */
 689         dw_mci_setup_bus(slot, false);
 690
 691         host->cur_slot = slot;
 692         host->mrq = mrq;
 693
 694         host->pending_events = 0;
 695         host->completed_events = 0;
 696         host->data_status = 0;
 697
 698         data = cmd->data;
 699         if (data) {
 700                 dw_mci_set_timeout(host);
 701                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
 702                 mci_writel(host, BLKSIZ, data->blksz);
 703         }
 704
 705         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
 706
 707         /* this is the first command, send the initialization clock */
 708         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
 709                 cmdflags |= SDMMC_CMD_INIT;
 710
 711         if (data) {
 712                 dw_mci_submit_data(host, data);
 713                 wmb();
 714         }
 715
 716         dw_mci_start_command(host, cmd, cmdflags);
 717
 718         if (mrq->stop)
 719                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
 720 }
 721
 722 static void dw_mci_start_request(struct dw_mci *host,
 723                                  struct dw_mci_slot *slot)
 724 {
 725         struct mmc_request *mrq = slot->mrq;
 726         struct mmc_command *cmd;
 727
 728         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
 729         __dw_mci_start_request(host, slot, cmd);
 730 }
 731
 732 /* must be called with host->lock held */
 733 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
 734                                  struct mmc_request *mrq)
 735 {
 736         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
 737                  host->state);
 738
 739         slot->mrq = mrq;
 740
 741         if (host->state == STATE_IDLE) {
 742                 host->state = STATE_SENDING_CMD;
 743                 dw_mci_start_request(host, slot);
 744         } else {
 745                 list_add_tail(&slot->queue_node, &host->queue);
 746         }
 747 }
 748
 749 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
 750 {
 751         struct dw_mci_slot *slot = mmc_priv(mmc);
 752         struct dw_mci *host = slot->host;
 753
 754         WARN_ON(slot->mrq);
 755
 756         /*
 757          * The check for card presence and queueing of the request must be
 758          * atomic, otherwise the card could be removed in between and the
 759          * request wouldn't fail until another card was inserted.
 760          */
 761         spin_lock_bh(&host->lock);
 762
 763         if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 764                 spin_unlock_bh(&host->lock);
 765                 mrq->cmd->error = -ENOMEDIUM;
 766                 mmc_request_done(mmc, mrq);
 767                 return;
 768         }
 769
 770         dw_mci_queue_request(host, slot, mrq);
 771
 772         spin_unlock_bh(&host->lock);
 773 }
 774
 775 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 776 {
 777         struct dw_mci_slot *slot = mmc_priv(mmc);
 778         u32 regs;
 779
 780         /* set default 1 bit mode */
 781         slot->ctype = SDMMC_CTYPE_1BIT;
 782
 783         switch (ios->bus_width) {
 784         case MMC_BUS_WIDTH_1:
 785                 slot->ctype = SDMMC_CTYPE_1BIT;
 786                 break;
 787         case MMC_BUS_WIDTH_4:
 788                 slot->ctype = SDMMC_CTYPE_4BIT;
 789                 break;
 790         case MMC_BUS_WIDTH_8:
 791                 slot->ctype = SDMMC_CTYPE_8BIT;
 792                 break;
 793         }
 794
 795         regs = mci_readl(slot->host, UHS_REG);
 796
 797         /* DDR mode set */
 798         if (ios->timing == MMC_TIMING_UHS_DDR50) {
 799                 regs |= (0x1 << slot->id) << 16;
 800                 mci_writel(slot->host, CLKSEL, slot->host->ddr_timing);
 801         } else {
 802                 regs &= ~(0x1 << slot->id) << 16;
 803                 mci_writel(slot->host, CLKSEL, slot->host->sdr_timing);
 804         }
 805
 806         if (slot->host->drv_data->ctrl_type == DW_MCI_TYPE_EXYNOS5250) {
 807                 slot->host->bus_hz = clk_get_rate(slot->host->ciu_clk);
 808                 slot->host->bus_hz /= SDMMC_CLKSEL_GET_DIVRATIO(
 809                                         mci_readl(slot->host, CLKSEL));
 810         }
 811
 812         mci_writel(slot->host, UHS_REG, regs);
 813
 814         if (ios->clock) {
 815                 /*
 816                  * Use mirror of ios->clock to prevent race with mmc
 817                  * core ios update when finding the minimum.
 818                  */
 819                 slot->clock = ios->clock;
 820         }
 821
 822         switch (ios->power_mode) {
 823         case MMC_POWER_UP:
 824                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
 825                 break;
 826         default:
 827                 break;
 828         }
 829 }
 830
 831 static int dw_mci_get_ro(struct mmc_host *mmc)
 832 {
 833         int read_only;
 834         struct dw_mci_slot *slot = mmc_priv(mmc);
 835         struct dw_mci_board *brd = slot->host->pdata;
 836
 837         /* Use platform get_ro function, else try on board write protect */
 838         if (brd->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)
 839                 read_only = 0;
 840         else if (brd->get_ro)
 841                 read_only = brd->get_ro(slot->id);
 842         else if (gpio_is_valid(slot->wp_gpio))
 843                 read_only = gpio_get_value(slot->wp_gpio);
 844         else
 845                 read_only =
 846                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
 847
 848         dev_dbg(&mmc->class_dev, "card is %s\n",
 849                 read_only ? "read-only" : "read-write");
 850
 851         return read_only;
 852 }
 853
 854 static int dw_mci_get_cd(struct mmc_host *mmc)
 855 {
 856         int present;
 857         struct dw_mci_slot *slot = mmc_priv(mmc);
 858         struct dw_mci_board *brd = slot->host->pdata;
 859
 860         /* Use platform get_cd function, else try onboard card detect */
 861         if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) {
 862                 present = 1;
 863         } else if (brd->get_cd) {
 864                 present = !brd->get_cd(slot->id);
 865         } else if (gpio_is_valid(slot->cd_gpio)) {
 866                 present = !!gpio_get_value(slot->cd_gpio);
 867                 present ^= slot->cd_gpio_active_low;
 868         } else {
 869                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 870                         == 0 ? 1 : 0;
 871         }
 872
 873         if (present)
 874                 dev_dbg(&mmc->class_dev, "card is present\n");
 875         else
 876                 dev_dbg(&mmc->class_dev, "card is not present\n");
 877
 878         return present;
 879 }
 880
 881 /*
 882  * Disable lower power mode.
 883  *
 884  * Low power mode will stop the card clock when idle.  According to
 885  * documentation we should disable low power mode for SDIO cards if we
 886  * need interrupts to work.
 887  *
 888  * This function is fast if the power mode is already disabled.
 889  */
 890 static void dw_mci_disable_low_power(struct mmc_host *mmc)
 891 {
 892         struct dw_mci_slot *slot = mmc_priv(mmc);
 893         struct dw_mci *host = slot->host;
 894         u32 clk_en_a;
 895         const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
 896
 897         clk_en_a = mci_readl(host, CLKENA);
 898
 899         if (clk_en_a & clken_low_pwr) {
 900                 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
 901                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 902                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 903         }
 904 }
 905
 906 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
 907 {
 908         struct dw_mci_slot *slot = mmc_priv(mmc);
 909         struct dw_mci *host = slot->host;
 910         u32 int_mask;
 911
 912         /* Enable/disable Slot Specific SDIO interrupt */
 913         int_mask = mci_readl(host, INTMASK);
 914         if (enb) {
 915                 /*
 916                  * Turn off low power mode if it was enabled.  This is a bit of
 917                  * a heavy operation and we disable / enable IRQs a lot, so
 918                  * we'll leave them disabled; they will get re-enabled again in
 919                  * dw_mci_setup_bus().
 920                  */
 921                 dw_mci_disable_low_power(mmc);
 922
 923                 mci_writel(host, INTMASK,
 924                            (int_mask | SDMMC_INT_SDIO(slot->id)));
 925         } else {
 926                 mci_writel(host, INTMASK,
 927                            (int_mask & ~SDMMC_INT_SDIO(slot->id)));
 928         }
 929 }
 930
 931 static const struct mmc_host_ops dw_mci_ops = {
 932         .request                = dw_mci_request,
 933         .pre_req                = dw_mci_pre_req,
 934         .post_req               = dw_mci_post_req,
 935         .set_ios                = dw_mci_set_ios,
 936         .get_ro                 = dw_mci_get_ro,
 937         .get_cd                 = dw_mci_get_cd,
 938         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
 939 };
 940
 941 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
 942         __releases(&host->lock)
 943         __acquires(&host->lock)
 944 {
 945         struct dw_mci_slot *slot;
 946         struct mmc_host *prev_mmc = host->cur_slot->mmc;
 947
 948         WARN_ON(host->cmd || host->data);
 949
 950         host->cur_slot->mrq = NULL;
 951         host->mrq = NULL;
 952         if (!list_empty(&host->queue)) {
 953                 slot = list_entry(host->queue.next,
 954                                   struct dw_mci_slot, queue_node);
 955                 list_del(&slot->queue_node);
 956                 dev_vdbg(host->dev, "list not empty: %s is next\n",
 957                          mmc_hostname(slot->mmc));
 958                 host->state = STATE_SENDING_CMD;
 959                 dw_mci_start_request(host, slot);
 960         } else {
 961                 dev_vdbg(host->dev, "list empty\n");
 962                 host->state = STATE_IDLE;
 963         }
 964
 965         spin_unlock(&host->lock);
 966         mmc_request_done(prev_mmc, mrq);
 967         spin_lock(&host->lock);
 968 }
 969
 970 static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
 971 {
 972         u32 status = host->cmd_status;
 973
 974         host->cmd_status = 0;
 975
 976         /* Read the response from the card (up to 16 bytes) */
 977         if (cmd->flags & MMC_RSP_PRESENT) {
 978                 if (cmd->flags & MMC_RSP_136) {
 979                         cmd->resp[3] = mci_readl(host, RESP0);
 980                         cmd->resp[2] = mci_readl(host, RESP1);
 981                         cmd->resp[1] = mci_readl(host, RESP2);
 982                         cmd->resp[0] = mci_readl(host, RESP3);
 983                 } else {
 984                         cmd->resp[0] = mci_readl(host, RESP0);
 985                         cmd->resp[1] = 0;
 986                         cmd->resp[2] = 0;
 987                         cmd->resp[3] = 0;
 988                 }
 989         }
 990
 991         if (status & SDMMC_INT_RTO)
 992                 cmd->error = -ETIMEDOUT;
 993         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
 994                 cmd->error = -EILSEQ;
 995         else if (status & SDMMC_INT_RESP_ERR)
 996                 cmd->error = -EIO;
 997         else
 998                 cmd->error = 0;
 999
1000         if (cmd->error) {
1001                 /* newer ip versions need a delay between retries */
1002                 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1003                         mdelay(20);
1004
1005                 if (cmd->data) {
1006                         dw_mci_stop_dma(host);
1007                         host->data = NULL;
1008                 }
1009         }
1010 }
1011
1012 static void dw_mci_tasklet_func(unsigned long priv)
1013 {
1014         struct dw_mci *host = (struct dw_mci *)priv;
1015         struct mmc_data *data;
1016         struct mmc_command *cmd;
1017         enum dw_mci_state state;
1018         enum dw_mci_state prev_state;
1019         u32 status, ctrl;
1020
1021         spin_lock(&host->lock);
1022
1023         state = host->state;
1024         data = host->data;
1025
1026         do {
1027                 prev_state = state;
1028
1029                 switch (state) {
1030                 case STATE_IDLE:
1031                         break;
1032
1033                 case STATE_SENDING_CMD:
1034                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1035                                                 &host->pending_events))
1036                                 break;
1037
1038                         cmd = host->cmd;
1039                         host->cmd = NULL;
1040                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1041                         dw_mci_command_complete(host, cmd);
1042                         if (cmd == host->mrq->sbc && !cmd->error) {
1043                                 prev_state = state = STATE_SENDING_CMD;
1044                                 __dw_mci_start_request(host, host->cur_slot,
1045                                                        host->mrq->cmd);
1046                                 goto unlock;
1047                         }
1048
1049                         if (!host->mrq->data || cmd->error) {
1050                                 dw_mci_request_end(host, host->mrq);
1051                                 goto unlock;
1052                         }
1053
1054                         prev_state = state = STATE_SENDING_DATA;
1055                         /* fall through */
1056
1057                 case STATE_SENDING_DATA:
1058                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1059                                                &host->pending_events)) {
1060                                 dw_mci_stop_dma(host);
1061                                 if (data->stop)
1062                                         send_stop_cmd(host, data);
1063                                 state = STATE_DATA_ERROR;
1064                                 break;
1065                         }
1066
1067                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1068                                                 &host->pending_events))
1069                                 break;
1070
1071                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1072                         prev_state = state = STATE_DATA_BUSY;
1073                         /* fall through */
1074
1075                 case STATE_DATA_BUSY:
1076                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1077                                                 &host->pending_events))
1078                                 break;
1079
1080                         host->data = NULL;
1081                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1082                         status = host->data_status;
1083
1084                         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1085                                 if (status & SDMMC_INT_DTO) {
1086                                         data->error = -ETIMEDOUT;
1087                                 } else if (status & SDMMC_INT_DCRC) {
1088                                         data->error = -EILSEQ;
1089                                 } else if (status & SDMMC_INT_EBE &&
1090                                            host->dir_status ==
1091                                                         DW_MCI_SEND_STATUS) {
1092                                         /*
1093                                          * No data CRC status was returned.
1094                                          * The number of bytes transferred will
1095                                          * be exaggerated in PIO mode.
1096                                          */
1097                                         data->bytes_xfered = 0;
1098                                         data->error = -ETIMEDOUT;
1099                                 } else {
1100                                         dev_err(host->dev,
1101                                                 "data FIFO error "
1102                                                 "(status=%08x)\n",
1103                                                 status);
1104                                         data->error = -EIO;
1105                                 }
1106                                 /*
1107                                  * After an error, there may be data lingering
1108                                  * in the FIFO, so reset it - doing so
1109                                  * generates a block interrupt, hence setting
1110                                  * the scatter-gather pointer to NULL.
1111                                  */
1112                                 sg_miter_stop(&host->sg_miter);
1113                                 host->sg = NULL;
1114                                 ctrl = mci_readl(host, CTRL);
1115                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1116                                 mci_writel(host, CTRL, ctrl);
1117                         } else {
1118                                 data->bytes_xfered = data->blocks * data->blksz;
1119                                 data->error = 0;
1120                         }
1121
1122                         if (!data->stop) {
1123                                 dw_mci_request_end(host, host->mrq);
1124                                 goto unlock;
1125                         }
1126
1127                         if (host->mrq->sbc && !data->error) {
1128                                 data->stop->error = 0;
1129                                 dw_mci_request_end(host, host->mrq);
1130                                 goto unlock;
1131                         }
1132
1133                         prev_state = state = STATE_SENDING_STOP;
1134                         if (!data->error)
1135                                 send_stop_cmd(host, data);
1136                         /* fall through */
1137
1138                 case STATE_SENDING_STOP:
1139                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1140                                                 &host->pending_events))
1141                                 break;
1142
1143                         host->cmd = NULL;
1144                         dw_mci_command_complete(host, host->mrq->stop);
1145                         dw_mci_request_end(host, host->mrq);
1146                         goto unlock;
1147
1148                 case STATE_DATA_ERROR:
1149                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1150                                                 &host->pending_events))
1151                                 break;
1152
1153                         state = STATE_DATA_BUSY;
1154                         break;
1155                 }
1156         } while (state != prev_state);
1157
1158         host->state = state;
1159 unlock:
1160         spin_unlock(&host->lock);
1161
1162 }
1163
1164 /* push final bytes to part_buf, only use during push */
1165 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
1166 {
1167         memcpy((void *)&host->part_buf, buf, cnt);
1168         host->part_buf_count = cnt;
1169 }
1170
1171 /* append bytes to part_buf, only use during push */
1172 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1173 {
1174         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1175         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1176         host->part_buf_count += cnt;
1177         return cnt;
1178 }
1179
1180 /* pull first bytes from part_buf, only use during pull */
1181 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1182 {
1183         cnt = min(cnt, (int)host->part_buf_count);
1184         if (cnt) {
1185                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1186                        cnt);
1187                 host->part_buf_count -= cnt;
1188                 host->part_buf_start += cnt;
1189         }
1190         return cnt;
1191 }
1192
1193 /* pull final bytes from the part_buf, assuming it's just been filled */
1194 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
1195 {
1196         memcpy(buf, &host->part_buf, cnt);
1197         host->part_buf_start = cnt;
1198         host->part_buf_count = (1 << host->data_shift) - cnt;
1199 }
1200
1201 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1202 {
1203         /* try and push anything in the part_buf */
1204         if (unlikely(host->part_buf_count)) {
1205                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1206                 buf += len;
1207                 cnt -= len;
1208                 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1209                         mci_writew(host, DATA(host->data_offset),
1210                                         host->part_buf16);
1211                         host->part_buf_count = 0;
1212                 }
1213         }
1214 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1215         if (unlikely((unsigned long)buf & 0x1)) {
1216                 while (cnt >= 2) {
1217                         u16 aligned_buf[64];
1218                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1219                         int items = len >> 1;
1220                         int i;
1221                         /* memcpy from input buffer into aligned buffer */
1222                         memcpy(aligned_buf, buf, len);
1223                         buf += len;
1224                         cnt -= len;
1225                         /* push data from aligned buffer into fifo */
1226                         for (i = 0; i < items; ++i)
1227                                 mci_writew(host, DATA(host->data_offset),
1228                                                 aligned_buf[i]);
1229                 }
1230         } else
1231 #endif
1232         {
1233                 u16 *pdata = buf;
1234                 for (; cnt >= 2; cnt -= 2)
1235                         mci_writew(host, DATA(host->data_offset), *pdata++);
1236                 buf = pdata;
1237         }
1238         /* put anything remaining in the part_buf */
1239         if (cnt) {
1240                 dw_mci_set_part_bytes(host, buf, cnt);
1241                 if (!sg_next(host->sg))
1242                         mci_writew(host, DATA(host->data_offset),
1243                                         host->part_buf16);
1244         }
1245 }
1246
1247 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1248 {
1249 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1250         if (unlikely((unsigned long)buf & 0x1)) {
1251                 while (cnt >= 2) {
1252                         /* pull data from fifo into aligned buffer */
1253                         u16 aligned_buf[64];
1254                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
1255                         int items = len >> 1;
1256                         int i;
1257                         for (i = 0; i < items; ++i)
1258                                 aligned_buf[i] = mci_readw(host,
1259                                                 DATA(host->data_offset));
1260                         /* memcpy from aligned buffer into output buffer */
1261                         memcpy(buf, aligned_buf, len);
1262                         buf += len;
1263                         cnt -= len;
1264                 }
1265         } else
1266 #endif
1267         {
1268                 u16 *pdata = buf;
1269                 for (; cnt >= 2; cnt -= 2)
1270                         *pdata++ = mci_readw(host, DATA(host->data_offset));
1271                 buf = pdata;
1272         }
1273         if (cnt) {
1274                 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
1275                 dw_mci_pull_final_bytes(host, buf, cnt);
1276         }
1277 }
1278
1279 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1280 {
1281         /* try and push anything in the part_buf */
1282         if (unlikely(host->part_buf_count)) {
1283                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1284                 buf += len;
1285                 cnt -= len;
1286                 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1287                         mci_writel(host, DATA(host->data_offset),
1288                                         host->part_buf32);
1289                         host->part_buf_count = 0;
1290                 }
1291         }
1292 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1293         if (unlikely((unsigned long)buf & 0x3)) {
1294                 while (cnt >= 4) {
1295                         u32 aligned_buf[32];
1296                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1297                         int items = len >> 2;
1298                         int i;
1299                         /* memcpy from input buffer into aligned buffer */
1300                         memcpy(aligned_buf, buf, len);
1301                         buf += len;
1302                         cnt -= len;
1303                         /* push data from aligned buffer into fifo */
1304                         for (i = 0; i < items; ++i)
1305                                 mci_writel(host, DATA(host->data_offset),
1306                                                 aligned_buf[i]);
1307                 }
1308         } else
1309 #endif
1310         {
1311                 u32 *pdata = buf;
1312                 for (; cnt >= 4; cnt -= 4)
1313                         mci_writel(host, DATA(host->data_offset), *pdata++);
1314                 buf = pdata;
1315         }
1316         /* put anything remaining in the part_buf */
1317         if (cnt) {
1318                 dw_mci_set_part_bytes(host, buf, cnt);
1319                 if (!sg_next(host->sg))
1320                         mci_writel(host, DATA(host->data_offset),
1321                                                 host->part_buf32);
1322         }
1323 }
1324
1325 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1326 {
1327 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1328         if (unlikely((unsigned long)buf & 0x3)) {
1329                 while (cnt >= 4) {
1330                         /* pull data from fifo into aligned buffer */
1331                         u32 aligned_buf[32];
1332                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
1333                         int items = len >> 2;
1334                         int i;
1335                         for (i = 0; i < items; ++i)
1336                                 aligned_buf[i] = mci_readl(host,
1337                                                 DATA(host->data_offset));
1338                         /* memcpy from aligned buffer into output buffer */
1339                         memcpy(buf, aligned_buf, len);
1340                         buf += len;
1341                         cnt -= len;
1342                 }
1343         } else
1344 #endif
1345         {
1346                 u32 *pdata = buf;
1347                 for (; cnt >= 4; cnt -= 4)
1348                         *pdata++ = mci_readl(host, DATA(host->data_offset));
1349                 buf = pdata;
1350         }
1351         if (cnt) {
1352                 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
1353                 dw_mci_pull_final_bytes(host, buf, cnt);
1354         }
1355 }
1356
1357 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1358 {
1359         /* try and push anything in the part_buf */
1360         if (unlikely(host->part_buf_count)) {
1361                 int len = dw_mci_push_part_bytes(host, buf, cnt);
1362                 buf += len;
1363                 cnt -= len;
1364                 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1365                         mci_writew(host, DATA(host->data_offset),
1366                                         host->part_buf);
1367                         host->part_buf_count = 0;
1368                 }
1369         }
1370 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1371         if (unlikely((unsigned long)buf & 0x7)) {
1372                 while (cnt >= 8) {
1373                         u64 aligned_buf[16];
1374                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1375                         int items = len >> 3;
1376                         int i;
1377                         /* memcpy from input buffer into aligned buffer */
1378                         memcpy(aligned_buf, buf, len);
1379                         buf += len;
1380                         cnt -= len;
1381                         /* push data from aligned buffer into fifo */
1382                         for (i = 0; i < items; ++i)
1383                                 mci_writeq(host, DATA(host->data_offset),
1384                                                 aligned_buf[i]);
1385                 }
1386         } else
1387 #endif
1388         {
1389                 u64 *pdata = buf;
1390                 for (; cnt >= 8; cnt -= 8)
1391                         mci_writeq(host, DATA(host->data_offset), *pdata++);
1392                 buf = pdata;
1393         }
1394         /* put anything remaining in the part_buf */
1395         if (cnt) {
1396                 dw_mci_set_part_bytes(host, buf, cnt);
1397                 if (!sg_next(host->sg))
1398                         mci_writeq(host, DATA(host->data_offset),
1399                                         host->part_buf);
1400         }
1401 }
1402
1403 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1404 {
1405 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1406         if (unlikely((unsigned long)buf & 0x7)) {
1407                 while (cnt >= 8) {
1408                         /* pull data from fifo into aligned buffer */
1409                         u64 aligned_buf[16];
1410                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
1411                         int items = len >> 3;
1412                         int i;
1413                         for (i = 0; i < items; ++i)
1414                                 aligned_buf[i] = mci_readq(host,
1415                                                 DATA(host->data_offset));
1416                         /* memcpy from aligned buffer into output buffer */
1417                         memcpy(buf, aligned_buf, len);
1418                         buf += len;
1419                         cnt -= len;
1420                 }
1421         } else
1422 #endif
1423         {
1424                 u64 *pdata = buf;
1425                 for (; cnt >= 8; cnt -= 8)
1426                         *pdata++ = mci_readq(host, DATA(host->data_offset));
1427                 buf = pdata;
1428         }
1429         if (cnt) {
1430                 host->part_buf = mci_readq(host, DATA(host->data_offset));
1431                 dw_mci_pull_final_bytes(host, buf, cnt);
1432         }
1433 }
1434
1435 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1436 {
1437         int len;
1438
1439         /* get remaining partial bytes */
1440         len = dw_mci_pull_part_bytes(host, buf, cnt);
1441         if (unlikely(len == cnt))
1442                 return;
1443         buf += len;
1444         cnt -= len;
1445
1446         /* get the rest of the data */
1447         host->pull_data(host, buf, cnt);
1448 }
1449
1450 static void dw_mci_read_data_pio(struct dw_mci *host)
1451 {
1452         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1453         void *buf;
1454         unsigned int offset;
1455         struct mmc_data *data = host->data;
1456         int shift = host->data_shift;
1457         u32 status;
1458         unsigned int nbytes = 0, len;
1459         unsigned int remain, fcnt;
1460
1461         do {
1462                 if (!sg_miter_next(sg_miter))
1463                         goto done;
1464
1465                 host->sg = sg_miter->__sg;
1466                 buf = sg_miter->addr;
1467                 remain = sg_miter->length;
1468                 offset = 0;
1469
1470                 do {
1471                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1472                                         << shift) + host->part_buf_count;
1473                         len = min(remain, fcnt);
1474                         if (!len)
1475                                 break;
1476                         dw_mci_pull_data(host, (void *)(buf + offset), len);
1477                         offset += len;
1478                         nbytes += len;
1479                         remain -= len;
1480                 } while (remain);
1481
1482                 sg_miter->consumed = offset;
1483                 status = mci_readl(host, MINTSTS);
1484                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1485         } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1486         data->bytes_xfered += nbytes;
1487
1488         if (!remain) {
1489                 if (!sg_miter_next(sg_miter))
1490                         goto done;
1491                 sg_miter->consumed = 0;
1492         }
1493         sg_miter_stop(sg_miter);
1494         return;
1495
1496 done:
1497         data->bytes_xfered += nbytes;
1498         sg_miter_stop(sg_miter);
1499         host->sg = NULL;
1500         smp_wmb();
1501         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1502 }
1503
1504 static void dw_mci_write_data_pio(struct dw_mci *host)
1505 {
1506         struct sg_mapping_iter *sg_miter = &host->sg_miter;
1507         void *buf;
1508         unsigned int offset;
1509         struct mmc_data *data = host->data;
1510         int shift = host->data_shift;
1511         u32 status;
1512         unsigned int nbytes = 0, len;
1513         unsigned int fifo_depth = host->fifo_depth;
1514         unsigned int remain, fcnt;
1515
1516         do {
1517                 if (!sg_miter_next(sg_miter))
1518                         goto done;
1519
1520                 host->sg = sg_miter->__sg;
1521                 buf = sg_miter->addr;
1522                 remain = sg_miter->length;
1523                 offset = 0;
1524
1525                 do {
1526                         fcnt = ((fifo_depth -
1527                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1528                                         << shift) - host->part_buf_count;
1529                         len = min(remain, fcnt);
1530                         if (!len)
1531                                 break;
1532                         host->push_data(host, (void *)(buf + offset), len);
1533                         offset += len;
1534                         nbytes += len;
1535                         remain -= len;
1536                 } while (remain);
1537
1538                 sg_miter->consumed = offset;
1539                 status = mci_readl(host, MINTSTS);
1540                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1541         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1542         data->bytes_xfered += nbytes;
1543
1544         if (!remain) {
1545                 if (!sg_miter_next(sg_miter))
1546                         goto done;
1547                 sg_miter->consumed = 0;
1548         }
1549         sg_miter_stop(sg_miter);
1550         return;
1551
1552 done:
1553         data->bytes_xfered += nbytes;
1554         sg_miter_stop(sg_miter);
1555         host->sg = NULL;
1556         smp_wmb();
1557         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1558 }
1559
1560 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1561 {
1562         if (!host->cmd_status)
1563                 host->cmd_status = status;
1564
1565         smp_wmb();
1566
1567         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1568         tasklet_schedule(&host->tasklet);
1569 }
1570
1571 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1572 {
1573         struct dw_mci *host = dev_id;
1574         u32 pending;
1575         unsigned int pass_count = 0;
1576         int i;
1577
1578         do {
1579                 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1580
1581                 /*
1582                  * DTO fix - version 2.10a and below, and only if internal DMA
1583                  * is configured.
1584                  */
1585                 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1586                         if (!pending &&
1587                             ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1588                                 pending |= SDMMC_INT_DATA_OVER;
1589                 }
1590
1591                 if (!pending)
1592                         break;
1593
1594                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1595                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1596                         host->cmd_status = pending;
1597                         smp_wmb();
1598                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1599                 }
1600
1601                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1602                         /* if there is an error report DATA_ERROR */
1603                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1604                         host->data_status = pending;
1605                         smp_wmb();
1606                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
1607                         tasklet_schedule(&host->tasklet);
1608                 }
1609
1610                 if (pending & SDMMC_INT_DATA_OVER) {
1611                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1612                         if (!host->data_status)
1613                                 host->data_status = pending;
1614                         smp_wmb();
1615                         if (host->dir_status == DW_MCI_RECV_STATUS) {
1616                                 if (host->sg != NULL)
1617                                         dw_mci_read_data_pio(host);
1618                         }
1619                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1620                         tasklet_schedule(&host->tasklet);
1621                 }
1622
1623                 if (pending & SDMMC_INT_RXDR) {
1624                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1625                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
1626                                 dw_mci_read_data_pio(host);
1627                 }
1628
1629                 if (pending & SDMMC_INT_TXDR) {
1630                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1631                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
1632                                 dw_mci_write_data_pio(host);
1633                 }
1634
1635                 if (pending & SDMMC_INT_CMD_DONE) {
1636                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1637                         dw_mci_cmd_interrupt(host, pending);
1638                 }
1639
1640                 if (pending & SDMMC_INT_CD) {
1641                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
1642                         queue_work(host->card_workqueue, &host->card_work);
1643                 }
1644
1645                 /* Handle SDIO Interrupts */
1646                 for (i = 0; i < host->num_slots; i++) {
1647                         struct dw_mci_slot *slot = host->slot[i];
1648                         if (pending & SDMMC_INT_SDIO(i)) {
1649                                 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1650                                 mmc_signal_sdio_irq(slot->mmc);
1651                         }
1652                 }
1653
1654         } while (pass_count++ < 5);
1655
1656 #ifdef CONFIG_MMC_DW_IDMAC
1657         /* Handle DMA interrupts */
1658         pending = mci_readl(host, IDSTS);
1659         if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1660                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1661                 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1662                 host->dma_ops->complete(host);
1663         }
1664 #endif
1665
1666         return IRQ_HANDLED;
1667 }
1668
1669 static void dw_mci_work_routine_card(struct work_struct *work)
1670 {
1671         struct dw_mci *host = container_of(work, struct dw_mci, card_work);
1672         int i;
1673
1674         for (i = 0; i < host->num_slots; i++) {
1675                 struct dw_mci_slot *slot = host->slot[i];
1676                 struct mmc_host *mmc = slot->mmc;
1677                 struct mmc_request *mrq;
1678                 int present;
1679                 u32 ctrl;
1680
1681                 present = dw_mci_get_cd(mmc);
1682                 while (present != slot->last_detect_state) {
1683                         dev_dbg(&slot->mmc->class_dev, "card %s\n",
1684                                 present ? "inserted" : "removed");
1685
1686                         /* Power up slot (before spin_lock, may sleep) */
1687                         if (present != 0 && host->pdata->setpower)
1688                                 host->pdata->setpower(slot->id, mmc->ocr_avail);
1689
1690                         spin_lock_bh(&host->lock);
1691
1692                         /* Card change detected */
1693                         slot->last_detect_state = present;
1694
1695                         /* Mark card as present if applicable */
1696                         if (present != 0)
1697                                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1698
1699                         /* Clean up queue if present */
1700                         mrq = slot->mrq;
1701                         if (mrq) {
1702                                 if (mrq == host->mrq) {
1703                                         host->data = NULL;
1704                                         host->cmd = NULL;
1705
1706                                         switch (host->state) {
1707                                         case STATE_IDLE:
1708                                                 break;
1709                                         case STATE_SENDING_CMD:
1710                                                 mrq->cmd->error = -ENOMEDIUM;
1711                                                 if (!mrq->data)
1712                                                         break;
1713                                                 /* fall through */
1714                                         case STATE_SENDING_DATA:
1715                                                 mrq->data->error = -ENOMEDIUM;
1716                                                 dw_mci_stop_dma(host);
1717                                                 break;
1718                                         case STATE_DATA_BUSY:
1719                                         case STATE_DATA_ERROR:
1720                                                 if (mrq->data->error == -EINPROGRESS)
1721                                                         mrq->data->error = -ENOMEDIUM;
1722                                                 if (!mrq->stop)
1723                                                         break;
1724                                                 /* fall through */
1725                                         case STATE_SENDING_STOP:
1726                                                 mrq->stop->error = -ENOMEDIUM;
1727                                                 break;
1728                                         }
1729
1730                                         dw_mci_request_end(host, mrq);
1731                                 } else {
1732                                         list_del(&slot->queue_node);
1733                                         mrq->cmd->error = -ENOMEDIUM;
1734                                         if (mrq->data)
1735                                                 mrq->data->error = -ENOMEDIUM;
1736                                         if (mrq->stop)
1737                                                 mrq->stop->error = -ENOMEDIUM;
1738
1739                                         spin_unlock(&host->lock);
1740                                         mmc_request_done(slot->mmc, mrq);
1741                                         spin_lock(&host->lock);
1742                                 }
1743                         }
1744
1745                         /* Power down slot */
1746                         if (present == 0) {
1747                                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1748
1749                                 /*
1750                                  * Clear down the FIFO - doing so generates a
1751                                  * block interrupt, hence setting the
1752                                  * scatter-gather pointer to NULL.
1753                                  */
1754                                 sg_miter_stop(&host->sg_miter);
1755                                 host->sg = NULL;
1756
1757                                 ctrl = mci_readl(host, CTRL);
1758                                 ctrl |= SDMMC_CTRL_FIFO_RESET;
1759                                 mci_writel(host, CTRL, ctrl);
1760
1761 #ifdef CONFIG_MMC_DW_IDMAC
1762                                 ctrl = mci_readl(host, BMOD);
1763                                 /* Software reset of DMA */
1764                                 ctrl |= SDMMC_IDMAC_SWRESET;
1765                                 mci_writel(host, BMOD, ctrl);
1766 #endif
1767
1768                         }
1769
1770                         spin_unlock_bh(&host->lock);
1771
1772                         /* Power down slot (after spin_unlock, may sleep) */
1773                         if (present == 0 && host->pdata->setpower)
1774                                 host->pdata->setpower(slot->id, 0);
1775
1776                         present = dw_mci_get_cd(mmc);
1777                 }
1778
1779                 mmc_detect_change(slot->mmc,
1780                         msecs_to_jiffies(host->pdata->detect_delay_ms));
1781         }
1782 }
1783
1784 #ifdef CONFIG_OF
1785 static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
1786 {
1787         struct device_node *np;
1788         char name[7];
1789
1790         if (!dev || !dev->of_node)
1791                 return NULL;
1792
1793         for_each_child_of_node(dev->of_node, np) {
1794                 sprintf(name, "slot%d", slot);
1795                 if (!strcmp(name, np->name))
1796                         return np;
1797         }
1798         return NULL;
1799 }
1800
1801 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1802 {
1803         struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
1804         u32 bus_wd = 1;
1805
1806         if (!np)
1807                 return 1;
1808
1809         if (of_property_read_u32(np, "bus-width", &bus_wd))
1810                 dev_err(dev, "bus-width property not found, assuming width"
1811                                " as 1\n");
1812         return bus_wd;
1813 }
1814
1815 static int dw_mci_of_setup_bus(struct dw_mci *host, u8 slot, u32 bus_wd)
1816 {
1817         struct device_node *np = dw_mci_of_find_slot_node(host->dev, slot);
1818         enum of_gpio_flags flags;
1819         int idx, gpio, ret;
1820
1821         for (idx = 0; idx < NUM_PINS(bus_wd); idx++) {
1822                 gpio = of_get_gpio(np, idx);
1823                 if (!gpio_is_valid(gpio)) {
1824                         dev_err(host->dev, "invalid gpio: %d\n", gpio);
1825                         return -EINVAL;
1826                 }
1827
1828                 ret = devm_gpio_request(host->dev, gpio, "dw-mci-bus");
1829                 if (ret) {
1830                         dev_err(host->dev, "gpio [%d] request failed\n", gpio);
1831                         return -EBUSY;
1832                 }
1833         }
1834
1835         host->slot[slot]->wp_gpio = -1;
1836         gpio = of_get_named_gpio(np, "wp_gpios", 0);
1837         if (!gpio_is_valid(gpio)) {
1838                 dev_info(host->dev, "wp gpio not available");
1839         } else {
1840                 ret = devm_gpio_request(host->dev, gpio, "dw-mci-wp");
1841                 if (ret)
1842                         dev_info(host->dev, "gpio [%d] request failed\n",
1843                                                 gpio);
1844                 else
1845                         host->slot[slot]->wp_gpio = gpio;
1846         }
1847
1848         host->slot[slot]->cd_gpio = -1;
1849         gpio = of_get_named_gpio_flags(np, "cd-gpios", 0, &flags);
1850         if (!gpio_is_valid(gpio)) {
1851                 dev_info(host->dev, "cd gpio not available");
1852         } else {
1853                 ret = devm_gpio_request(host->dev, gpio, "dw-mci-cd");
1854                 if (ret) {
1855                         dev_err(host->dev, "gpio [%d] request failed\n", gpio);
1856                 } else {
1857                         host->slot[slot]->cd_gpio = gpio;
1858                         host->slot[slot]->cd_gpio_active_low =
1859                                 !!(flags & OF_GPIO_ACTIVE_LOW);
1860                 }
1861         }
1862
1863         return 0;
1864 }
1865
1866 #else /* CONFIG_OF */
1867 static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
1868 {
1869         return 1;
1870 }
1871
1872 static int dw_mci_of_setup_bus(struct dw_mci *host, u8 slot, u32 bus_wd)
1873 {
1874         return -EINVAL;
1875 }
1876 #endif /* CONFIG_OF */
1877
1878 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1879 {
1880         struct mmc_host *mmc;
1881         struct dw_mci_slot *slot;
1882         unsigned int ctrl_id;
1883
1884         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
1885         if (!mmc)
1886                 return -ENOMEM;
1887
1888         slot = mmc_priv(mmc);
1889         slot->id = id;
1890         slot->mmc = mmc;
1891         slot->host = host;
1892         host->slot[id] = slot;
1893
1894         mmc->ops = &dw_mci_ops;
1895         mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1896         mmc->f_max = host->bus_hz;
1897
1898         if (host->pdata->get_ocr)
1899                 mmc->ocr_avail = host->pdata->get_ocr(id);
1900         else
1901                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1902
1903         /*
1904          * Start with slot power disabled, it will be enabled when a card
1905          * is detected.
1906          */
1907         if (host->pdata->setpower)
1908                 host->pdata->setpower(id, 0);
1909
1910         if (host->pdata->caps)
1911                 mmc->caps = host->pdata->caps;
1912
1913         if (host->pdata->pm_caps)
1914                 mmc->pm_caps = host->pdata->pm_caps;
1915
1916         if (host->dev->of_node) {
1917                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
1918                 if (ctrl_id < 0)
1919                         ctrl_id = 0;
1920                 mmc->caps |= host->drv_data->caps[ctrl_id];
1921         }
1922
1923         if (host->pdata->caps2)
1924                 mmc->caps2 = host->pdata->caps2;
1925
1926         if (host->pdata->get_bus_wd) {
1927                 if (host->pdata->get_bus_wd(slot->id) >= 4)
1928                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1929         } else if (host->dev->of_node) {
1930                 unsigned int bus_width;
1931                 bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
1932                 if (bus_width >= 4)
1933                         mmc->caps |= MMC_CAP_4_BIT_DATA;
1934                 dw_mci_of_setup_bus(host, slot->id, bus_width);
1935         }
1936
1937         if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1938                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
1939
1940         if (host->pdata->quirks & DW_MCI_QUIRK_DISABLE_MMC)
1941                 mmc->caps2 |= MMC_CAP2_NO_MMC;
1942
1943         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1944                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1945         else
1946                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1947
1948         if (host->pdata->blk_settings) {
1949                 mmc->max_segs = host->pdata->blk_settings->max_segs;
1950                 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1951                 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1952                 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1953                 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1954         } else {
1955                 /* Useful defaults if platform data is unset. */
1956 #ifdef CONFIG_MMC_DW_IDMAC
1957                 mmc->max_segs = host->ring_size;
1958                 mmc->max_blk_size = 65536;
1959                 mmc->max_blk_count = host->ring_size;
1960                 mmc->max_seg_size = 0x1000;
1961                 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1962 #else
1963                 mmc->max_segs = 64;
1964                 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1965                 mmc->max_blk_count = 512;
1966                 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1967                 mmc->max_seg_size = mmc->max_req_size;
1968 #endif /* CONFIG_MMC_DW_IDMAC */
1969         }
1970
1971         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1972         if (IS_ERR(host->vmmc)) {
1973                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
1974                 host->vmmc = NULL;
1975         } else
1976                 regulator_enable(host->vmmc);
1977
1978         if (dw_mci_get_cd(mmc))
1979                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1980         else
1981                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1982
1983         mmc_add_host(mmc);
1984
1985 #if defined(CONFIG_DEBUG_FS)
1986         dw_mci_init_debugfs(slot);
1987 #endif
1988
1989         /* Card initially undetected */
1990         slot->last_detect_state = 0;
1991
1992         /*
1993          * Card may have been plugged in prior to boot so we
1994          * need to run the detect tasklet
1995          */
1996         queue_work(host->card_workqueue, &host->card_work);
1997
1998         return 0;
1999 }
2000
2001 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2002 {
2003         /* Shutdown detect IRQ */
2004         if (slot->host->pdata->exit)
2005                 slot->host->pdata->exit(id);
2006
2007         /* Debugfs stuff is cleaned up by mmc core */
2008         mmc_remove_host(slot->mmc);
2009         slot->host->slot[id] = NULL;
2010         mmc_free_host(slot->mmc);
2011 }
2012
2013 static void dw_mci_init_dma(struct dw_mci *host)
2014 {
2015         /* Alloc memory for sg translation */
2016         host->sg_cpu = dma_alloc_coherent(host->dev, PAGE_SIZE,
2017                                           &host->sg_dma, GFP_KERNEL);
2018         if (!host->sg_cpu) {
2019                 dev_err(host->dev, "%s: could not alloc DMA memory\n",
2020                         __func__);
2021                 goto no_dma;
2022         }
2023
2024         /* Determine which DMA interface to use */
2025 #ifdef CONFIG_MMC_DW_IDMAC
2026         host->dma_ops = &dw_mci_idmac_ops;
2027         dev_info(host->dev, "Using internal DMA controller.\n");
2028 #endif
2029
2030         if (!host->dma_ops)
2031                 goto no_dma;
2032
2033         if (host->dma_ops->init && host->dma_ops->start &&
2034             host->dma_ops->stop && host->dma_ops->cleanup) {
2035                 if (host->dma_ops->init(host)) {
2036                         dev_err(host->dev, "%s: Unable to initialize "
2037                                 "DMA Controller.\n", __func__);
2038                         goto no_dma;
2039                 }
2040         } else {
2041                 dev_err(host->dev, "DMA initialization not found.\n");
2042                 goto no_dma;
2043         }
2044
2045         host->use_dma = 1;
2046         return;
2047
2048 no_dma:
2049         dev_info(host->dev, "Using PIO mode.\n");
2050         host->use_dma = 0;
2051         return;
2052 }
2053
2054 static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
2055 {
2056         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2057         unsigned int ctrl;
2058
2059         mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2060                                 SDMMC_CTRL_DMA_RESET));
2061
2062         /* wait till resets clear */
2063         do {
2064                 ctrl = mci_readl(host, CTRL);
2065                 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
2066                               SDMMC_CTRL_DMA_RESET)))
2067                         return true;
2068         } while (time_before(jiffies, timeout));
2069
2070         dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
2071
2072         return false;
2073 }
2074
2075 #ifdef CONFIG_OF
2076 static struct dw_mci_of_quirks {
2077         char *quirk;
2078         int id;
2079 } of_quriks[] = {
2080         {
2081                 .quirk  = "supports-highspeed",
2082                 .id     = DW_MCI_QUIRK_HIGHSPEED,
2083         }, {
2084                 .quirk  = "card-detection-broken",
2085                 .id     = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2086         }, {
2087                 .quirk  = "no-write-protect",
2088                 .id     = DW_MCI_QUIRK_NO_WRITE_PROTECT,
2089         }, {
2090                 .quirk  = "disable-mmc",
2091                 .id     = DW_MCI_QUIRK_DISABLE_MMC,
2092         },
2093 };
2094
2095 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2096 {
2097         struct dw_mci_board *pdata;
2098         struct device *dev = host->dev;
2099         struct device_node *np = dev->of_node, *slot;
2100         u32 timing[3];
2101         int idx, cnt;
2102
2103         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2104         if (!pdata) {
2105                 dev_err(dev, "could not allocate memory for pdata\n");
2106                 return ERR_PTR(-ENOMEM);
2107         }
2108
2109         /* find out number of slots supported */
2110         for_each_child_of_node(np, slot)
2111                 pdata->num_slots++;
2112
2113         /* get quirks */
2114         cnt = sizeof(of_quriks) / sizeof(struct dw_mci_of_quirks);
2115         for (idx = 0; idx < cnt; idx++)
2116                 if (of_get_property(np, of_quriks[idx].quirk, NULL))
2117                         pdata->quirks |= of_quriks[idx].id;
2118
2119         if (of_property_read_u32_array(dev->of_node,
2120                         "samsung,dw-mshc-sdr-timing", timing, 3))
2121                 host->sdr_timing = DW_MCI_DEF_SDR_TIMING;
2122         else
2123                 host->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0],
2124                                         timing[1], timing[2]);
2125
2126         if (of_property_read_u32_array(dev->of_node,
2127                         "samsung,dw-mshc-ddr-timing", timing, 3))
2128                 host->ddr_timing = DW_MCI_DEF_DDR_TIMING;
2129         else
2130                 host->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0],
2131                                         timing[1], timing[2]);
2132
2133         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2134                 dev_info(dev, "fifo-depth property not found, using "
2135                                 "value of FIFOTH register as default\n");
2136
2137         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2138
2139         if (of_find_property(np, "keep-power-in-suspend", NULL))
2140                 pdata->pm_caps |= MMC_PM_KEEP_POWER;
2141
2142         if (of_find_property(np, "enable-sdio-wakeup", NULL))
2143                 pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2144
2145         return pdata;
2146 }
2147
2148 #else /* CONFIG_OF */
2149 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2150 {
2151         return ERR_PTR(-EINVAL);
2152 }
2153 #endif /* CONFIG_OF */
2154
2155 int dw_mci_probe(struct dw_mci *host)
2156 {
2157         int width, i, ret = 0;
2158         u32 fifo_size;
2159
2160         if (!host->pdata) {
2161                 host->pdata = dw_mci_parse_dt(host);
2162                 if (IS_ERR(host->pdata)) {
2163                         dev_err(host->dev, "platform data not available\n");
2164                         return -EINVAL;
2165                 }
2166         }
2167
2168         if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
2169                 dev_err(host->dev,
2170                         "Platform data must supply select_slot function\n");
2171                 return -ENODEV;
2172         }
2173
2174         host->biu_clk = clk_get(host->dev, "biu");
2175         if (IS_ERR(host->biu_clk))
2176                 dev_info(host->dev, "biu clock not available\n");
2177         else
2178                 clk_enable(host->biu_clk);
2179
2180         host->ciu_clk = clk_get(host->dev, "ciu");
2181         if (IS_ERR(host->ciu_clk))
2182                 dev_info(host->dev, "ciu clock not available\n");
2183         else
2184                 clk_enable(host->ciu_clk);
2185
2186         if (IS_ERR(host->ciu_clk))
2187                 host->bus_hz = host->pdata->bus_hz;
2188         else
2189                 host->bus_hz = clk_get_rate(host->ciu_clk);
2190
2191         if (!host->bus_hz) {
2192                 dev_err(host->dev,
2193                         "Platform data must supply bus speed\n");
2194                 ret = -ENODEV;
2195                 goto err_clk;
2196         }
2197
2198         host->quirks = host->pdata->quirks;
2199
2200         spin_lock_init(&host->lock);
2201         INIT_LIST_HEAD(&host->queue);
2202
2203         /*
2204          * Get the host data width - this assumes that HCON has been set with
2205          * the correct values.
2206          */
2207         i = (mci_readl(host, HCON) >> 7) & 0x7;
2208         if (!i) {
2209                 host->push_data = dw_mci_push_data16;
2210                 host->pull_data = dw_mci_pull_data16;
2211                 width = 16;
2212                 host->data_shift = 1;
2213         } else if (i == 2) {
2214                 host->push_data = dw_mci_push_data64;
2215                 host->pull_data = dw_mci_pull_data64;
2216                 width = 64;
2217                 host->data_shift = 3;
2218         } else {
2219                 /* Check for a reserved value, and warn if it is */
2220                 WARN((i != 1),
2221                      "HCON reports a reserved host data width!\n"
2222                      "Defaulting to 32-bit access.\n");
2223                 host->push_data = dw_mci_push_data32;
2224                 host->pull_data = dw_mci_pull_data32;
2225                 width = 32;
2226                 host->data_shift = 2;
2227         }
2228
2229         /* Reset all blocks */
2230         if (!mci_wait_reset(host->dev, host))
2231                 return -ENODEV;
2232
2233         host->dma_ops = host->pdata->dma_ops;
2234         dw_mci_init_dma(host);
2235
2236         /* Clear the interrupts for the host controller */
2237         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2238         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2239
2240         /* Put in max timeout */
2241         mci_writel(host, TMOUT, 0xFFFFFFFF);
2242
2243         /*
2244          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
2245          *                          Tx Mark = fifo_size / 2 DMA Size = 8
2246          */
2247         if (!host->pdata->fifo_depth) {
2248                 /*
2249                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2250                  * have been overwritten by the bootloader, just like we're
2251                  * about to do, so if you know the value for your hardware, you
2252                  * should put it in the platform data.
2253                  */
2254                 fifo_size = mci_readl(host, FIFOTH);
2255                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
2256         } else {
2257                 fifo_size = host->pdata->fifo_depth;
2258         }
2259         host->fifo_depth = fifo_size;
2260         host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2261                         ((fifo_size/2) << 0));
2262         mci_writel(host, FIFOTH, host->fifoth_val);
2263
2264         /* disable clock to CIU */
2265         mci_writel(host, CLKENA, 0);
2266         mci_writel(host, CLKSRC, 0);
2267
2268         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
2269         host->card_workqueue = alloc_workqueue("dw-mci-card",
2270                         WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2271         if (!host->card_workqueue)
2272                 goto err_dmaunmap;
2273         INIT_WORK(&host->card_work, dw_mci_work_routine_card);
2274         ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
2275         if (ret)
2276                 goto err_workqueue;
2277
2278         if (host->pdata->num_slots)
2279                 host->num_slots = host->pdata->num_slots;
2280         else
2281                 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2282
2283         /*
2284          * Enable interrupts for command done, data over, data empty, card det,
2285          * receive ready and error such as transmit, receive timeout, crc error
2286          */
2287         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2288         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2289                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2290                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2291         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2292
2293         dev_info(host->dev, "DW MMC controller at irq %d, "
2294                  "%d bit host data width, "
2295                  "%u deep fifo\n",
2296                  host->irq, width, fifo_size);
2297
2298         /* We need at least one slot to succeed */
2299         for (i = 0; i < host->num_slots; i++) {
2300                 ret = dw_mci_init_slot(host, i);
2301                 if (ret) {
2302                         ret = -ENODEV;
2303                         goto err_init_slot;
2304                 }
2305         }
2306
2307         /*
2308          * In 2.40a spec, Data offset is changed.
2309          * Need to check the version-id and set data-offset for DATA register.
2310          */
2311         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2312         dev_info(host->dev, "Version ID is %04x\n", host->verid);
2313
2314         if (host->verid < DW_MMC_240A)
2315                 host->data_offset = DATA_OFFSET;
2316         else
2317                 host->data_offset = DATA_240A_OFFSET;
2318
2319         if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
2320                 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
2321
2322         return 0;
2323
2324 err_init_slot:
2325         /* De-init any initialized slots */
2326         while (i > 0) {
2327                 if (host->slot[i])
2328                         dw_mci_cleanup_slot(host->slot[i], i);
2329                 i--;
2330         }
2331         free_irq(host->irq, host);
2332
2333 err_workqueue:
2334         destroy_workqueue(host->card_workqueue);
2335
2336 err_dmaunmap:
2337         if (host->use_dma && host->dma_ops->exit)
2338                 host->dma_ops->exit(host);
2339         dma_free_coherent(host->dev, PAGE_SIZE,
2340                           host->sg_cpu, host->sg_dma);
2341
2342         if (host->vmmc) {
2343                 regulator_disable(host->vmmc);
2344                 regulator_put(host->vmmc);
2345         }
2346         kfree(host);
2347
2348 err_clk:
2349         clk_disable(host->ciu_clk);
2350         clk_disable(host->biu_clk);
2351         clk_put(host->ciu_clk);
2352         clk_put(host->biu_clk);
2353         return ret;
2354 }
2355 EXPORT_SYMBOL(dw_mci_probe);
2356
2357 void dw_mci_remove(struct dw_mci *host)
2358 {
2359         int i;
2360
2361         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2362         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2363
2364         for (i = 0; i < host->num_slots; i++) {
2365                 dev_dbg(host->dev, "remove slot %d\n", i);
2366                 if (host->slot[i])
2367                         dw_mci_cleanup_slot(host->slot[i], i);
2368         }
2369
2370         /* disable clock to CIU */
2371         mci_writel(host, CLKENA, 0);
2372         mci_writel(host, CLKSRC, 0);
2373
2374         free_irq(host->irq, host);
2375         destroy_workqueue(host->card_workqueue);
2376         dma_free_coherent(host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
2377
2378         if (host->use_dma && host->dma_ops->exit)
2379                 host->dma_ops->exit(host);
2380
2381         if (host->vmmc) {
2382                 regulator_disable(host->vmmc);
2383                 regulator_put(host->vmmc);
2384         }
2385
2386         clk_disable(host->ciu_clk);
2387         clk_disable(host->biu_clk);
2388         clk_put(host->ciu_clk);
2389         clk_put(host->biu_clk);
2390 }
2391 EXPORT_SYMBOL(dw_mci_remove);
2392
2393
2394
2395 #ifdef CONFIG_PM_SLEEP
2396 /*
2397  * TODO: we should probably disable the clock to the card in the suspend path.
2398  */
2399 int dw_mci_suspend(struct dw_mci *host)
2400 {
2401         int i, ret = 0;
2402
2403         for (i = 0; i < host->num_slots; i++) {
2404                 struct dw_mci_slot *slot = host->slot[i];
2405                 if (!slot)
2406                         continue;
2407                 ret = mmc_suspend_host(slot->mmc);
2408                 if (ret < 0) {
2409                         while (--i >= 0) {
2410                                 slot = host->slot[i];
2411                                 if (slot)
2412                                         mmc_resume_host(host->slot[i]->mmc);
2413                         }
2414                         return ret;
2415                 }
2416         }
2417
2418         if (host->vmmc)
2419                 regulator_disable(host->vmmc);
2420
2421         return 0;
2422 }
2423 EXPORT_SYMBOL(dw_mci_suspend);
2424
2425 int dw_mci_resume(struct dw_mci *host)
2426 {
2427         int i, ret;
2428
2429         if (host->vmmc)
2430                 regulator_enable(host->vmmc);
2431
2432
2433         if (!mci_wait_reset(host->dev, host)) {
2434                 ret = -ENODEV;
2435                 return ret;
2436         }
2437
2438         if (host->use_dma && host->dma_ops->init)
2439                 host->dma_ops->init(host);
2440
2441         /* Restore the old value at FIFOTH register */
2442         mci_writel(host, FIFOTH, host->fifoth_val);
2443
2444         mci_writel(host, RINTSTS, 0xFFFFFFFF);
2445         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2446                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2447                    DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2448         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2449
2450         for (i = 0; i < host->num_slots; i++) {
2451                 struct dw_mci_slot *slot = host->slot[i];
2452                 if (!slot)
2453                         continue;
2454                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2455                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2456                         dw_mci_setup_bus(slot, true);
2457                 }
2458
2459                 ret = mmc_resume_host(host->slot[i]->mmc);
2460                 if (ret < 0)
2461                         return ret;
2462         }
2463         return 0;
2464 }
2465 EXPORT_SYMBOL(dw_mci_resume);
2466 #endif /* CONFIG_PM_SLEEP */
2467
2468 static int __init dw_mci_init(void)
2469 {
2470         printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2471         return 0;
2472 }
2473
2474 static void __exit dw_mci_exit(void)
2475 {
2476 }
2477
2478 module_init(dw_mci_init);
2479 module_exit(dw_mci_exit);
2480
2481 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2482 MODULE_AUTHOR("NXP Semiconductor VietNam");
2483 MODULE_AUTHOR("Imagination Technologies Ltd");
2484 MODULE_LICENSE("GPL v2");