drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/ioport.h>
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/slab.h>
  27 #include <linux/stat.h>
  28 #include <linux/delay.h>
  29 #include <linux/irq.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/host.h>
  32 #include <linux/mmc/mmc.h>
  33 #include <linux/mmc/sd.h>
  34 #include <linux/mmc/sdio.h>
  35 #include <linux/mmc/dw_mmc.h>
  36 #include <linux/bitops.h>
  37 #include <linux/regulator/consumer.h>
  38 #include <linux/of.h>
  39 #include <linux/of_gpio.h>
  40 #include <linux/mmc/slot-gpio.h>
  41
  42 #include "dw_mmc.h"
  43
  44 /* Common flag combinations */
  45 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  46                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  47                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  48 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  49                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  50 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  51                                  DW_MCI_CMD_ERROR_FLAGS)
  52 #define DW_MCI_SEND_STATUS      1
  53 #define DW_MCI_RECV_STATUS      2
  54 #define DW_MCI_DMA_THRESHOLD    16
  55
  56 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  57 #define DW_MCI_FREQ_MIN 400000          /* unit: HZ */
  58
  59 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  60                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  61                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  62                                  SDMMC_IDMAC_INT_TI)
  63
  64 #define DESC_RING_BUF_SZ        PAGE_SIZE
  65
  66 struct idmac_desc_64addr {
  67         u32             des0;   /* Control Descriptor */
  68
  69         u32             des1;   /* Reserved */
  70
  71         u32             des2;   /*Buffer sizes */
  72 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  73         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  74          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  75
  76         u32             des3;   /* Reserved */
  77
  78         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  79         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  80
  81         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  82         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  83 };
  84
  85 struct idmac_desc {
  86         __le32          des0;   /* Control Descriptor */
  87 #define IDMAC_DES0_DIC  BIT(1)
  88 #define IDMAC_DES0_LD   BIT(2)
  89 #define IDMAC_DES0_FD   BIT(3)
  90 #define IDMAC_DES0_CH   BIT(4)
  91 #define IDMAC_DES0_ER   BIT(5)
  92 #define IDMAC_DES0_CES  BIT(30)
  93 #define IDMAC_DES0_OWN  BIT(31)
  94
  95         __le32          des1;   /* Buffer sizes */
  96 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  97         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
  98
  99         __le32          des2;   /* buffer 1 physical address */
 100
 101         __le32          des3;   /* buffer 2 physical address */
 102 };
 103
 104 /* Each descriptor can transfer up to 4KB of data in chained mode */
 105 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 106
 107 static bool dw_mci_reset(struct dw_mci *host);
 108 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
 109 static int dw_mci_card_busy(struct mmc_host *mmc);
 110 static int dw_mci_get_cd(struct mmc_host *mmc);
 111
 112 #if defined(CONFIG_DEBUG_FS)
 113 static int dw_mci_req_show(struct seq_file *s, void *v)
 114 {
 115         struct dw_mci_slot *slot = s->private;
 116         struct mmc_request *mrq;
 117         struct mmc_command *cmd;
 118         struct mmc_command *stop;
 119         struct mmc_data *data;
 120
 121         /* Make sure we get a consistent snapshot */
 122         spin_lock_bh(&slot->host->lock);
 123         mrq = slot->mrq;
 124
 125         if (mrq) {
 126                 cmd = mrq->cmd;
 127                 data = mrq->data;
 128                 stop = mrq->stop;
 129
 130                 if (cmd)
 131                         seq_printf(s,
 132                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 133                                    cmd->opcode, cmd->arg, cmd->flags,
 134                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 135                                    cmd->resp[2], cmd->error);
 136                 if (data)
 137                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 138                                    data->bytes_xfered, data->blocks,
 139                                    data->blksz, data->flags, data->error);
 140                 if (stop)
 141                         seq_printf(s,
 142                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 143                                    stop->opcode, stop->arg, stop->flags,
 144                                    stop->resp[0], stop->resp[1], stop->resp[2],
 145                                    stop->resp[2], stop->error);
 146         }
 147
 148         spin_unlock_bh(&slot->host->lock);
 149
 150         return 0;
 151 }
 152
 153 static int dw_mci_req_open(struct inode *inode, struct file *file)
 154 {
 155         return single_open(file, dw_mci_req_show, inode->i_private);
 156 }
 157
 158 static const struct file_operations dw_mci_req_fops = {
 159         .owner          = THIS_MODULE,
 160         .open           = dw_mci_req_open,
 161         .read           = seq_read,
 162         .llseek         = seq_lseek,
 163         .release        = single_release,
 164 };
 165
 166 static int dw_mci_regs_show(struct seq_file *s, void *v)
 167 {
 168         seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
 170         seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
 171         seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
 172         seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
 173         seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
 234
 235 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 236 {
 237         struct mmc_data *data;
 238         struct dw_mci_slot *slot = mmc_priv(mmc);
 239         struct dw_mci *host = slot->host;
 240         u32 cmdr;
 241
 242         cmd->error = -EINPROGRESS;
 243         cmdr = cmd->opcode;
 244
 245         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 246             cmd->opcode == MMC_GO_IDLE_STATE ||
 247             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 248             (cmd->opcode == SD_IO_RW_DIRECT &&
 249              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 250                 cmdr |= SDMMC_CMD_STOP;
 251         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 252                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 253
 254         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 255                 u32 clk_en_a;
 256
 257                 /* Special bit makes CMD11 not die */
 258                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 259
 260                 /* Change state to continue to handle CMD11 weirdness */
 261                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 262                 slot->host->state = STATE_SENDING_CMD11;
 263
 264                 /*
 265                  * We need to disable low power mode (automatic clock stop)
 266                  * while doing voltage switch so we don't confuse the card,
 267                  * since stopping the clock is a specific part of the UHS
 268                  * voltage change dance.
 269                  *
 270                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 271                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 272                  * ever called with a non-zero clock.  That shouldn't happen
 273                  * until the voltage change is all done.
 274                  */
 275                 clk_en_a = mci_readl(host, CLKENA);
 276                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 277                 mci_writel(host, CLKENA, clk_en_a);
 278                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 279                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 280         }
 281
 282         if (cmd->flags & MMC_RSP_PRESENT) {
 283                 /* We expect a response, so set this bit */
 284                 cmdr |= SDMMC_CMD_RESP_EXP;
 285                 if (cmd->flags & MMC_RSP_136)
 286                         cmdr |= SDMMC_CMD_RESP_LONG;
 287         }
 288
 289         if (cmd->flags & MMC_RSP_CRC)
 290                 cmdr |= SDMMC_CMD_RESP_CRC;
 291
 292         data = cmd->data;
 293         if (data) {
 294                 cmdr |= SDMMC_CMD_DAT_EXP;
 295                 if (data->flags & MMC_DATA_WRITE)
 296                         cmdr |= SDMMC_CMD_DAT_WR;
 297         }
 298
 299         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 300                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 301
 302         return cmdr;
 303 }
 304
 305 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 306 {
 307         struct mmc_command *stop;
 308         u32 cmdr;
 309
 310         if (!cmd->data)
 311                 return 0;
 312
 313         stop = &host->stop_abort;
 314         cmdr = cmd->opcode;
 315         memset(stop, 0, sizeof(struct mmc_command));
 316
 317         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 318             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 319             cmdr == MMC_WRITE_BLOCK ||
 320             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 321             cmdr == MMC_SEND_TUNING_BLOCK ||
 322             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 323                 stop->opcode = MMC_STOP_TRANSMISSION;
 324                 stop->arg = 0;
 325                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 326         } else if (cmdr == SD_IO_RW_EXTENDED) {
 327                 stop->opcode = SD_IO_RW_DIRECT;
 328                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 329                              ((cmd->arg >> 28) & 0x7);
 330                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 331         } else {
 332                 return 0;
 333         }
 334
 335         cmdr = stop->opcode | SDMMC_CMD_STOP |
 336                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 337
 338         return cmdr;
 339 }
 340
 341 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 342 {
 343         unsigned long timeout = jiffies + msecs_to_jiffies(500);
 344
 345         /*
 346          * Databook says that before issuing a new data transfer command
 347          * we need to check to see if the card is busy.  Data transfer commands
 348          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 349          *
 350          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 351          * expected.
 352          */
 353         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 354             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 355                 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
 356                         if (time_after(jiffies, timeout)) {
 357                                 /* Command will fail; we'll pass error then */
 358                                 dev_err(host->dev, "Busy; trying anyway\n");
 359                                 break;
 360                         }
 361                         udelay(10);
 362                 }
 363         }
 364 }
 365
 366 static void dw_mci_start_command(struct dw_mci *host,
 367                                  struct mmc_command *cmd, u32 cmd_flags)
 368 {
 369         host->cmd = cmd;
 370         dev_vdbg(host->dev,
 371                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 372                  cmd->arg, cmd_flags);
 373
 374         mci_writel(host, CMDARG, cmd->arg);
 375         wmb(); /* drain writebuffer */
 376         dw_mci_wait_while_busy(host, cmd_flags);
 377
 378         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 379 }
 380
 381 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 382 {
 383         struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
 384
 385         dw_mci_start_command(host, stop, host->stop_cmdr);
 386 }
 387
 388 /* DMA interface functions */
 389 static void dw_mci_stop_dma(struct dw_mci *host)
 390 {
 391         if (host->using_dma) {
 392                 host->dma_ops->stop(host);
 393                 host->dma_ops->cleanup(host);
 394         }
 395
 396         /* Data transfer was stopped by the interrupt handler */
 397         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 398 }
 399
 400 static int dw_mci_get_dma_dir(struct mmc_data *data)
 401 {
 402         if (data->flags & MMC_DATA_WRITE)
 403                 return DMA_TO_DEVICE;
 404         else
 405                 return DMA_FROM_DEVICE;
 406 }
 407
 408 static void dw_mci_dma_cleanup(struct dw_mci *host)
 409 {
 410         struct mmc_data *data = host->data;
 411
 412         if (data)
 413                 if (!data->host_cookie)
 414                         dma_unmap_sg(host->dev,
 415                                      data->sg,
 416                                      data->sg_len,
 417                                      dw_mci_get_dma_dir(data));
 418 }
 419
 420 static void dw_mci_idmac_reset(struct dw_mci *host)
 421 {
 422         u32 bmod = mci_readl(host, BMOD);
 423         /* Software reset of DMA */
 424         bmod |= SDMMC_IDMAC_SWRESET;
 425         mci_writel(host, BMOD, bmod);
 426 }
 427
 428 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 429 {
 430         u32 temp;
 431
 432         /* Disable and reset the IDMAC interface */
 433         temp = mci_readl(host, CTRL);
 434         temp &= ~SDMMC_CTRL_USE_IDMAC;
 435         temp |= SDMMC_CTRL_DMA_RESET;
 436         mci_writel(host, CTRL, temp);
 437
 438         /* Stop the IDMAC running */
 439         temp = mci_readl(host, BMOD);
 440         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 441         temp |= SDMMC_IDMAC_SWRESET;
 442         mci_writel(host, BMOD, temp);
 443 }
 444
 445 static void dw_mci_dmac_complete_dma(void *arg)
 446 {
 447         struct dw_mci *host = arg;
 448         struct mmc_data *data = host->data;
 449
 450         dev_vdbg(host->dev, "DMA complete\n");
 451
 452         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 453             data && (data->flags & MMC_DATA_READ))
 454                 /* Invalidate cache after read */
 455                 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
 456                                     data->sg,
 457                                     data->sg_len,
 458                                     DMA_FROM_DEVICE);
 459
 460         host->dma_ops->cleanup(host);
 461
 462         /*
 463          * If the card was removed, data will be NULL. No point in trying to
 464          * send the stop command or waiting for NBUSY in this case.
 465          */
 466         if (data) {
 467                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 468                 tasklet_schedule(&host->tasklet);
 469         }
 470 }
 471
 472 static int dw_mci_idmac_init(struct dw_mci *host)
 473 {
 474         int i;
 475
 476         if (host->dma_64bit_address == 1) {
 477                 struct idmac_desc_64addr *p;
 478                 /* Number of descriptors in the ring buffer */
 479                 host->ring_size =
 480                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 481
 482                 /* Forward link the descriptor list */
 483                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 484                                                                 i++, p++) {
 485                         p->des6 = (host->sg_dma +
 486                                         (sizeof(struct idmac_desc_64addr) *
 487                                                         (i + 1))) & 0xffffffff;
 488
 489                         p->des7 = (u64)(host->sg_dma +
 490                                         (sizeof(struct idmac_desc_64addr) *
 491                                                         (i + 1))) >> 32;
 492                         /* Initialize reserved and buffer size fields to "0" */
 493                         p->des1 = 0;
 494                         p->des2 = 0;
 495                         p->des3 = 0;
 496                 }
 497
 498                 /* Set the last descriptor as the end-of-ring descriptor */
 499                 p->des6 = host->sg_dma & 0xffffffff;
 500                 p->des7 = (u64)host->sg_dma >> 32;
 501                 p->des0 = IDMAC_DES0_ER;
 502
 503         } else {
 504                 struct idmac_desc *p;
 505                 /* Number of descriptors in the ring buffer */
 506                 host->ring_size =
 507                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 508
 509                 /* Forward link the descriptor list */
 510                 for (i = 0, p = host->sg_cpu;
 511                      i < host->ring_size - 1;
 512                      i++, p++) {
 513                         p->des3 = cpu_to_le32(host->sg_dma +
 514                                         (sizeof(struct idmac_desc) * (i + 1)));
 515                         p->des1 = 0;
 516                 }
 517
 518                 /* Set the last descriptor as the end-of-ring descriptor */
 519                 p->des3 = cpu_to_le32(host->sg_dma);
 520                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 521         }
 522
 523         dw_mci_idmac_reset(host);
 524
 525         if (host->dma_64bit_address == 1) {
 526                 /* Mask out interrupts - get Tx & Rx complete only */
 527                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 528                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 529                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 530
 531                 /* Set the descriptor base address */
 532                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 533                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 534
 535         } else {
 536                 /* Mask out interrupts - get Tx & Rx complete only */
 537                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 538                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 539                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 540
 541                 /* Set the descriptor base address */
 542                 mci_writel(host, DBADDR, host->sg_dma);
 543         }
 544
 545         return 0;
 546 }
 547
 548 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 549                                          struct mmc_data *data,
 550                                          unsigned int sg_len)
 551 {
 552         unsigned int desc_len;
 553         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 554         unsigned long timeout;
 555         int i;
 556
 557         desc_first = desc_last = desc = host->sg_cpu;
 558
 559         for (i = 0; i < sg_len; i++) {
 560                 unsigned int length = sg_dma_len(&data->sg[i]);
 561
 562                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 563
 564                 for ( ; length ; desc++) {
 565                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 566                                    length : DW_MCI_DESC_DATA_LENGTH;
 567
 568                         length -= desc_len;
 569
 570                         /*
 571                          * Wait for the former clear OWN bit operation
 572                          * of IDMAC to make sure that this descriptor
 573                          * isn't still owned by IDMAC as IDMAC's write
 574                          * ops and CPU's read ops are asynchronous.
 575                          */
 576                         timeout = jiffies + msecs_to_jiffies(100);
 577                         while (readl(&desc->des0) & IDMAC_DES0_OWN) {
 578                                 if (time_after(jiffies, timeout))
 579                                         goto err_own_bit;
 580                                 udelay(10);
 581                         }
 582
 583                         /*
 584                          * Set the OWN bit and disable interrupts
 585                          * for this descriptor
 586                          */
 587                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 588                                                 IDMAC_DES0_CH;
 589
 590                         /* Buffer length */
 591                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 592
 593                         /* Physical address to DMA to/from */
 594                         desc->des4 = mem_addr & 0xffffffff;
 595                         desc->des5 = mem_addr >> 32;
 596
 597                         /* Update physical address for the next desc */
 598                         mem_addr += desc_len;
 599
 600                         /* Save pointer to the last descriptor */
 601                         desc_last = desc;
 602                 }
 603         }
 604
 605         /* Set first descriptor */
 606         desc_first->des0 |= IDMAC_DES0_FD;
 607
 608         /* Set last descriptor */
 609         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 610         desc_last->des0 |= IDMAC_DES0_LD;
 611
 612         return 0;
 613 err_own_bit:
 614         /* restore the descriptor chain as it's polluted */
 615         dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
 616         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 617         dw_mci_idmac_init(host);
 618         return -EINVAL;
 619 }
 620
 621
 622 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 623                                          struct mmc_data *data,
 624                                          unsigned int sg_len)
 625 {
 626         unsigned int desc_len;
 627         struct idmac_desc *desc_first, *desc_last, *desc;
 628         unsigned long timeout;
 629         int i;
 630
 631         desc_first = desc_last = desc = host->sg_cpu;
 632
 633         for (i = 0; i < sg_len; i++) {
 634                 unsigned int length = sg_dma_len(&data->sg[i]);
 635
 636                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 637
 638                 for ( ; length ; desc++) {
 639                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 640                                    length : DW_MCI_DESC_DATA_LENGTH;
 641
 642                         length -= desc_len;
 643
 644                         /*
 645                          * Wait for the former clear OWN bit operation
 646                          * of IDMAC to make sure that this descriptor
 647                          * isn't still owned by IDMAC as IDMAC's write
 648                          * ops and CPU's read ops are asynchronous.
 649                          */
 650                         timeout = jiffies + msecs_to_jiffies(100);
 651                         while (readl(&desc->des0) &
 652                                cpu_to_le32(IDMAC_DES0_OWN)) {
 653                                 if (time_after(jiffies, timeout))
 654                                         goto err_own_bit;
 655                                 udelay(10);
 656                         }
 657
 658                         /*
 659                          * Set the OWN bit and disable interrupts
 660                          * for this descriptor
 661                          */
 662                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 663                                                  IDMAC_DES0_DIC |
 664                                                  IDMAC_DES0_CH);
 665
 666                         /* Buffer length */
 667                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 668
 669                         /* Physical address to DMA to/from */
 670                         desc->des2 = cpu_to_le32(mem_addr);
 671
 672                         /* Update physical address for the next desc */
 673                         mem_addr += desc_len;
 674
 675                         /* Save pointer to the last descriptor */
 676                         desc_last = desc;
 677                 }
 678         }
 679
 680         /* Set first descriptor */
 681         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 682
 683         /* Set last descriptor */
 684         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 685                                        IDMAC_DES0_DIC));
 686         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 687
 688         return 0;
 689 err_own_bit:
 690         /* restore the descriptor chain as it's polluted */
 691         dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
 692         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 693         dw_mci_idmac_init(host);
 694         return -EINVAL;
 695 }
 696
 697 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 698 {
 699         u32 temp;
 700         int ret;
 701
 702         if (host->dma_64bit_address == 1)
 703                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 704         else
 705                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 706
 707         if (ret)
 708                 goto out;
 709
 710         /* drain writebuffer */
 711         wmb();
 712
 713         /* Make sure to reset DMA in case we did PIO before this */
 714         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 715         dw_mci_idmac_reset(host);
 716
 717         /* Select IDMAC interface */
 718         temp = mci_readl(host, CTRL);
 719         temp |= SDMMC_CTRL_USE_IDMAC;
 720         mci_writel(host, CTRL, temp);
 721
 722         /* drain writebuffer */
 723         wmb();
 724
 725         /* Enable the IDMAC */
 726         temp = mci_readl(host, BMOD);
 727         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 728         mci_writel(host, BMOD, temp);
 729
 730         /* Start it running */
 731         mci_writel(host, PLDMND, 1);
 732
 733 out:
 734         return ret;
 735 }
 736
 737 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 738         .init = dw_mci_idmac_init,
 739         .start = dw_mci_idmac_start_dma,
 740         .stop = dw_mci_idmac_stop_dma,
 741         .complete = dw_mci_dmac_complete_dma,
 742         .cleanup = dw_mci_dma_cleanup,
 743 };
 744
 745 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 746 {
 747         dmaengine_terminate_async(host->dms->ch);
 748 }
 749
 750 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 751                                             unsigned int sg_len)
 752 {
 753         struct dma_slave_config cfg;
 754         struct dma_async_tx_descriptor *desc = NULL;
 755         struct scatterlist *sgl = host->data->sg;
 756         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 757         u32 sg_elems = host->data->sg_len;
 758         u32 fifoth_val;
 759         u32 fifo_offset = host->fifo_reg - host->regs;
 760         int ret = 0;
 761
 762         /* Set external dma config: burst size, burst width */
 763         cfg.dst_addr = host->phy_regs + fifo_offset;
 764         cfg.src_addr = cfg.dst_addr;
 765         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 766         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 767
 768         /* Match burst msize with external dma config */
 769         fifoth_val = mci_readl(host, FIFOTH);
 770         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 771         cfg.src_maxburst = cfg.dst_maxburst;
 772
 773         if (host->data->flags & MMC_DATA_WRITE)
 774                 cfg.direction = DMA_MEM_TO_DEV;
 775         else
 776                 cfg.direction = DMA_DEV_TO_MEM;
 777
 778         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 779         if (ret) {
 780                 dev_err(host->dev, "Failed to config edmac.\n");
 781                 return -EBUSY;
 782         }
 783
 784         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 785                                        sg_len, cfg.direction,
 786                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 787         if (!desc) {
 788                 dev_err(host->dev, "Can't prepare slave sg.\n");
 789                 return -EBUSY;
 790         }
 791
 792         /* Set dw_mci_dmac_complete_dma as callback */
 793         desc->callback = dw_mci_dmac_complete_dma;
 794         desc->callback_param = (void *)host;
 795         dmaengine_submit(desc);
 796
 797         /* Flush cache before write */
 798         if (host->data->flags & MMC_DATA_WRITE)
 799                 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
 800                                        sg_elems, DMA_TO_DEVICE);
 801
 802         dma_async_issue_pending(host->dms->ch);
 803
 804         return 0;
 805 }
 806
 807 static int dw_mci_edmac_init(struct dw_mci *host)
 808 {
 809         /* Request external dma channel */
 810         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 811         if (!host->dms)
 812                 return -ENOMEM;
 813
 814         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 815         if (!host->dms->ch) {
 816                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 817                 kfree(host->dms);
 818                 host->dms = NULL;
 819                 return -ENXIO;
 820         }
 821
 822         return 0;
 823 }
 824
 825 static void dw_mci_edmac_exit(struct dw_mci *host)
 826 {
 827         if (host->dms) {
 828                 if (host->dms->ch) {
 829                         dma_release_channel(host->dms->ch);
 830                         host->dms->ch = NULL;
 831                 }
 832                 kfree(host->dms);
 833                 host->dms = NULL;
 834         }
 835 }
 836
 837 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 838         .init = dw_mci_edmac_init,
 839         .exit = dw_mci_edmac_exit,
 840         .start = dw_mci_edmac_start_dma,
 841         .stop = dw_mci_edmac_stop_dma,
 842         .complete = dw_mci_dmac_complete_dma,
 843         .cleanup = dw_mci_dma_cleanup,
 844 };
 845
 846 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 847                                    struct mmc_data *data,
 848                                    bool next)
 849 {
 850         struct scatterlist *sg;
 851         unsigned int i, sg_len;
 852
 853         if (!next && data->host_cookie)
 854                 return data->host_cookie;
 855
 856         /*
 857          * We don't do DMA on "complex" transfers, i.e. with
 858          * non-word-aligned buffers or lengths. Also, we don't bother
 859          * with all the DMA setup overhead for short transfers.
 860          */
 861         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 862                 return -EINVAL;
 863
 864         if (data->blksz & 3)
 865                 return -EINVAL;
 866
 867         for_each_sg(data->sg, sg, data->sg_len, i) {
 868                 if (sg->offset & 3 || sg->length & 3)
 869                         return -EINVAL;
 870         }
 871
 872         sg_len = dma_map_sg(host->dev,
 873                             data->sg,
 874                             data->sg_len,
 875                             dw_mci_get_dma_dir(data));
 876         if (sg_len == 0)
 877                 return -EINVAL;
 878
 879         if (next)
 880                 data->host_cookie = sg_len;
 881
 882         return sg_len;
 883 }
 884
 885 static void dw_mci_pre_req(struct mmc_host *mmc,
 886                            struct mmc_request *mrq,
 887                            bool is_first_req)
 888 {
 889         struct dw_mci_slot *slot = mmc_priv(mmc);
 890         struct mmc_data *data = mrq->data;
 891
 892         if (!slot->host->use_dma || !data)
 893                 return;
 894
 895         if (data->host_cookie) {
 896                 data->host_cookie = 0;
 897                 return;
 898         }
 899
 900         if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
 901                 data->host_cookie = 0;
 902 }
 903
 904 static void dw_mci_post_req(struct mmc_host *mmc,
 905                             struct mmc_request *mrq,
 906                             int err)
 907 {
 908         struct dw_mci_slot *slot = mmc_priv(mmc);
 909         struct mmc_data *data = mrq->data;
 910
 911         if (!slot->host->use_dma || !data)
 912                 return;
 913
 914         if (data->host_cookie)
 915                 dma_unmap_sg(slot->host->dev,
 916                              data->sg,
 917                              data->sg_len,
 918                              dw_mci_get_dma_dir(data));
 919         data->host_cookie = 0;
 920 }
 921
 922 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 923 {
 924         unsigned int blksz = data->blksz;
 925         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 926         u32 fifo_width = 1 << host->data_shift;
 927         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 928         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 929         int idx = ARRAY_SIZE(mszs) - 1;
 930
 931         /* pio should ship this scenario */
 932         if (!host->use_dma)
 933                 return;
 934
 935         tx_wmark = (host->fifo_depth) / 2;
 936         tx_wmark_invers = host->fifo_depth - tx_wmark;
 937
 938         /*
 939          * MSIZE is '1',
 940          * if blksz is not a multiple of the FIFO width
 941          */
 942         if (blksz % fifo_width)
 943                 goto done;
 944
 945         do {
 946                 if (!((blksz_depth % mszs[idx]) ||
 947                      (tx_wmark_invers % mszs[idx]))) {
 948                         msize = idx;
 949                         rx_wmark = mszs[idx] - 1;
 950                         break;
 951                 }
 952         } while (--idx > 0);
 953         /*
 954          * If idx is '0', it won't be tried
 955          * Thus, initial values are uesed
 956          */
 957 done:
 958         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
 959         mci_writel(host, FIFOTH, fifoth_val);
 960 }
 961
 962 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
 963 {
 964         unsigned int blksz = data->blksz;
 965         u32 blksz_depth, fifo_depth;
 966         u16 thld_size;
 967         u8 enable;
 968
 969         /*
 970          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
 971          * in the FIFO region, so we really shouldn't access it).
 972          */
 973         if (host->verid < DW_MMC_240A ||
 974                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
 975                 return;
 976
 977         /*
 978          * Card write Threshold is introduced since 2.80a
 979          * It's used when HS400 mode is enabled.
 980          */
 981         if (data->flags & MMC_DATA_WRITE &&
 982                 !(host->timing != MMC_TIMING_MMC_HS400))
 983                 return;
 984
 985         if (data->flags & MMC_DATA_WRITE)
 986                 enable = SDMMC_CARD_WR_THR_EN;
 987         else
 988                 enable = SDMMC_CARD_RD_THR_EN;
 989
 990         if (host->timing != MMC_TIMING_MMC_HS200 &&
 991             host->timing != MMC_TIMING_UHS_SDR104)
 992                 goto disable;
 993
 994         blksz_depth = blksz / (1 << host->data_shift);
 995         fifo_depth = host->fifo_depth;
 996
 997         if (blksz_depth > fifo_depth)
 998                 goto disable;
 999
1000         /*
1001          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1002          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1003          * Currently just choose blksz.
1004          */
1005         thld_size = blksz;
1006         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1007         return;
1008
1009 disable:
1010         mci_writel(host, CDTHRCTL, 0);
1011 }
1012
1013 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1014 {
1015         unsigned long irqflags;
1016         int sg_len;
1017         u32 temp;
1018
1019         host->using_dma = 0;
1020
1021         /* If we don't have a channel, we can't do DMA */
1022         if (!host->use_dma)
1023                 return -ENODEV;
1024
1025         sg_len = dw_mci_pre_dma_transfer(host, data, 0);
1026         if (sg_len < 0) {
1027                 host->dma_ops->stop(host);
1028                 return sg_len;
1029         }
1030
1031         host->using_dma = 1;
1032
1033         if (host->use_dma == TRANS_MODE_IDMAC)
1034                 dev_vdbg(host->dev,
1035                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1036                          (unsigned long)host->sg_cpu,
1037                          (unsigned long)host->sg_dma,
1038                          sg_len);
1039
1040         /*
1041          * Decide the MSIZE and RX/TX Watermark.
1042          * If current block size is same with previous size,
1043          * no need to update fifoth.
1044          */
1045         if (host->prev_blksz != data->blksz)
1046                 dw_mci_adjust_fifoth(host, data);
1047
1048         /* Enable the DMA interface */
1049         temp = mci_readl(host, CTRL);
1050         temp |= SDMMC_CTRL_DMA_ENABLE;
1051         mci_writel(host, CTRL, temp);
1052
1053         /* Disable RX/TX IRQs, let DMA handle it */
1054         spin_lock_irqsave(&host->irq_lock, irqflags);
1055         temp = mci_readl(host, INTMASK);
1056         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1057         mci_writel(host, INTMASK, temp);
1058         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1059
1060         if (host->dma_ops->start(host, sg_len)) {
1061                 /* We can't do DMA, try PIO for this one */
1062                 dev_dbg(host->dev,
1063                         "%s: fall back to PIO mode for current transfer\n",
1064                         __func__);
1065                 return -ENODEV;
1066         }
1067
1068         return 0;
1069 }
1070
1071 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1072 {
1073         unsigned long irqflags;
1074         int flags = SG_MITER_ATOMIC;
1075         u32 temp;
1076
1077         data->error = -EINPROGRESS;
1078
1079         WARN_ON(host->data);
1080         host->sg = NULL;
1081         host->data = data;
1082
1083         if (data->flags & MMC_DATA_READ)
1084                 host->dir_status = DW_MCI_RECV_STATUS;
1085         else
1086                 host->dir_status = DW_MCI_SEND_STATUS;
1087
1088         dw_mci_ctrl_thld(host, data);
1089
1090         if (dw_mci_submit_data_dma(host, data)) {
1091                 if (host->data->flags & MMC_DATA_READ)
1092                         flags |= SG_MITER_TO_SG;
1093                 else
1094                         flags |= SG_MITER_FROM_SG;
1095
1096                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1097                 host->sg = data->sg;
1098                 host->part_buf_start = 0;
1099                 host->part_buf_count = 0;
1100
1101                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1102
1103                 spin_lock_irqsave(&host->irq_lock, irqflags);
1104                 temp = mci_readl(host, INTMASK);
1105                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1106                 mci_writel(host, INTMASK, temp);
1107                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1108
1109                 temp = mci_readl(host, CTRL);
1110                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1111                 mci_writel(host, CTRL, temp);
1112
1113                 /*
1114                  * Use the initial fifoth_val for PIO mode.
1115                  * If next issued data may be transfered by DMA mode,
1116                  * prev_blksz should be invalidated.
1117                  */
1118                 mci_writel(host, FIFOTH, host->fifoth_val);
1119                 host->prev_blksz = 0;
1120         } else {
1121                 /*
1122                  * Keep the current block size.
1123                  * It will be used to decide whether to update
1124                  * fifoth register next time.
1125                  */
1126                 host->prev_blksz = data->blksz;
1127         }
1128 }
1129
1130 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1131 {
1132         struct dw_mci *host = slot->host;
1133         unsigned long timeout = jiffies + msecs_to_jiffies(500);
1134         unsigned int cmd_status = 0;
1135
1136         mci_writel(host, CMDARG, arg);
1137         wmb(); /* drain writebuffer */
1138         dw_mci_wait_while_busy(host, cmd);
1139         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1140
1141         while (time_before(jiffies, timeout)) {
1142                 cmd_status = mci_readl(host, CMD);
1143                 if (!(cmd_status & SDMMC_CMD_START))
1144                         return;
1145         }
1146         dev_err(&slot->mmc->class_dev,
1147                 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1148                 cmd, arg, cmd_status);
1149 }
1150
1151 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1152 {
1153         struct dw_mci *host = slot->host;
1154         unsigned int clock = slot->clock;
1155         u32 div;
1156         u32 clk_en_a;
1157         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1158
1159         /* We must continue to set bit 28 in CMD until the change is complete */
1160         if (host->state == STATE_WAITING_CMD11_DONE)
1161                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1162
1163         if (!clock) {
1164                 mci_writel(host, CLKENA, 0);
1165                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1166         } else if (clock != host->current_speed || force_clkinit) {
1167                 div = host->bus_hz / clock;
1168                 if (host->bus_hz % clock && host->bus_hz > clock)
1169                         /*
1170                          * move the + 1 after the divide to prevent
1171                          * over-clocking the card.
1172                          */
1173                         div += 1;
1174
1175                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1176
1177                 if (clock != slot->__clk_old || force_clkinit)
1178                         dev_info(&slot->mmc->class_dev,
1179                                  "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1180                                  slot->id, host->bus_hz, clock,
1181                                  div ? ((host->bus_hz / div) >> 1) :
1182                                  host->bus_hz, div);
1183
1184                 /* disable clock */
1185                 mci_writel(host, CLKENA, 0);
1186                 mci_writel(host, CLKSRC, 0);
1187
1188                 /* inform CIU */
1189                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1190
1191                 /* set clock to desired speed */
1192                 mci_writel(host, CLKDIV, div);
1193
1194                 /* inform CIU */
1195                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1196
1197                 /* enable clock; only low power if no SDIO */
1198                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1199                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1200                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1201                 mci_writel(host, CLKENA, clk_en_a);
1202
1203                 /* inform CIU */
1204                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1205
1206                 /* keep the last clock value that was requested from core */
1207                 slot->__clk_old = clock;
1208         }
1209
1210         host->current_speed = clock;
1211
1212         /* Set the current slot bus width */
1213         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1214 }
1215
1216 static void __dw_mci_start_request(struct dw_mci *host,
1217                                    struct dw_mci_slot *slot,
1218                                    struct mmc_command *cmd)
1219 {
1220         struct mmc_request *mrq;
1221         struct mmc_data *data;
1222         u32 cmdflags;
1223
1224         mrq = slot->mrq;
1225
1226         host->cur_slot = slot;
1227         host->mrq = mrq;
1228
1229         host->pending_events = 0;
1230         host->completed_events = 0;
1231         host->cmd_status = 0;
1232         host->data_status = 0;
1233         host->dir_status = 0;
1234
1235         data = cmd->data;
1236         if (data) {
1237                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1238                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1239                 mci_writel(host, BLKSIZ, data->blksz);
1240         }
1241
1242         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1243
1244         /* this is the first command, send the initialization clock */
1245         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1246                 cmdflags |= SDMMC_CMD_INIT;
1247
1248         if (data) {
1249                 dw_mci_submit_data(host, data);
1250                 wmb(); /* drain writebuffer */
1251         }
1252
1253         dw_mci_start_command(host, cmd, cmdflags);
1254
1255         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1256                 unsigned long irqflags;
1257
1258                 /*
1259                  * Databook says to fail after 2ms w/ no response, but evidence
1260                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1261                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1262                  * is just about to roll over.
1263                  *
1264                  * We do this whole thing under spinlock and only if the
1265                  * command hasn't already completed (indicating the the irq
1266                  * already ran so we don't want the timeout).
1267                  */
1268                 spin_lock_irqsave(&host->irq_lock, irqflags);
1269                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1270                         mod_timer(&host->cmd11_timer,
1271                                 jiffies + msecs_to_jiffies(500) + 1);
1272                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1273         }
1274
1275         if (mrq->stop)
1276                 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
1277         else
1278                 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1279 }
1280
1281 static void dw_mci_start_request(struct dw_mci *host,
1282                                  struct dw_mci_slot *slot)
1283 {
1284         struct mmc_request *mrq = slot->mrq;
1285         struct mmc_command *cmd;
1286
1287         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1288         __dw_mci_start_request(host, slot, cmd);
1289 }
1290
1291 /* must be called with host->lock held */
1292 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1293                                  struct mmc_request *mrq)
1294 {
1295         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1296                  host->state);
1297
1298         slot->mrq = mrq;
1299
1300         if (host->state == STATE_WAITING_CMD11_DONE) {
1301                 dev_warn(&slot->mmc->class_dev,
1302                          "Voltage change didn't complete\n");
1303                 /*
1304                  * this case isn't expected to happen, so we can
1305                  * either crash here or just try to continue on
1306                  * in the closest possible state
1307                  */
1308                 host->state = STATE_IDLE;
1309         }
1310
1311         if (host->state == STATE_IDLE) {
1312                 host->state = STATE_SENDING_CMD;
1313                 dw_mci_start_request(host, slot);
1314         } else {
1315                 list_add_tail(&slot->queue_node, &host->queue);
1316         }
1317 }
1318
1319 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1320 {
1321         struct dw_mci_slot *slot = mmc_priv(mmc);
1322         struct dw_mci *host = slot->host;
1323
1324         WARN_ON(slot->mrq);
1325
1326         /*
1327          * The check for card presence and queueing of the request must be
1328          * atomic, otherwise the card could be removed in between and the
1329          * request wouldn't fail until another card was inserted.
1330          */
1331
1332         if (!dw_mci_get_cd(mmc)) {
1333                 mrq->cmd->error = -ENOMEDIUM;
1334                 mmc_request_done(mmc, mrq);
1335                 return;
1336         }
1337
1338         spin_lock_bh(&host->lock);
1339
1340         dw_mci_queue_request(host, slot, mrq);
1341
1342         spin_unlock_bh(&host->lock);
1343 }
1344
1345 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1346 {
1347         struct dw_mci_slot *slot = mmc_priv(mmc);
1348         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1349         u32 regs;
1350         int ret;
1351
1352         switch (ios->bus_width) {
1353         case MMC_BUS_WIDTH_4:
1354                 slot->ctype = SDMMC_CTYPE_4BIT;
1355                 break;
1356         case MMC_BUS_WIDTH_8:
1357                 slot->ctype = SDMMC_CTYPE_8BIT;
1358                 break;
1359         default:
1360                 /* set default 1 bit mode */
1361                 slot->ctype = SDMMC_CTYPE_1BIT;
1362         }
1363
1364         regs = mci_readl(slot->host, UHS_REG);
1365
1366         /* DDR mode set */
1367         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1368             ios->timing == MMC_TIMING_UHS_DDR50 ||
1369             ios->timing == MMC_TIMING_MMC_HS400)
1370                 regs |= ((0x1 << slot->id) << 16);
1371         else
1372                 regs &= ~((0x1 << slot->id) << 16);
1373
1374         mci_writel(slot->host, UHS_REG, regs);
1375         slot->host->timing = ios->timing;
1376
1377         /*
1378          * Use mirror of ios->clock to prevent race with mmc
1379          * core ios update when finding the minimum.
1380          */
1381         slot->clock = ios->clock;
1382
1383         if (drv_data && drv_data->set_ios)
1384                 drv_data->set_ios(slot->host, ios);
1385
1386         switch (ios->power_mode) {
1387         case MMC_POWER_UP:
1388                 if (!IS_ERR(mmc->supply.vmmc)) {
1389                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1390                                         ios->vdd);
1391                         if (ret) {
1392                                 dev_err(slot->host->dev,
1393                                         "failed to enable vmmc regulator\n");
1394                                 /*return, if failed turn on vmmc*/
1395                                 return;
1396                         }
1397                 }
1398                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1399                 regs = mci_readl(slot->host, PWREN);
1400                 regs |= (1 << slot->id);
1401                 mci_writel(slot->host, PWREN, regs);
1402                 break;
1403         case MMC_POWER_ON:
1404                 if (!slot->host->vqmmc_enabled) {
1405                         if (!IS_ERR(mmc->supply.vqmmc)) {
1406                                 ret = regulator_enable(mmc->supply.vqmmc);
1407                                 if (ret < 0)
1408                                         dev_err(slot->host->dev,
1409                                                 "failed to enable vqmmc\n");
1410                                 else
1411                                         slot->host->vqmmc_enabled = true;
1412
1413                         } else {
1414                                 /* Keep track so we don't reset again */
1415                                 slot->host->vqmmc_enabled = true;
1416                         }
1417
1418                         /* Reset our state machine after powering on */
1419                         dw_mci_ctrl_reset(slot->host,
1420                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1421                 }
1422
1423                 /* Adjust clock / bus width after power is up */
1424                 dw_mci_setup_bus(slot, false);
1425
1426                 break;
1427         case MMC_POWER_OFF:
1428                 /* Turn clock off before power goes down */
1429                 dw_mci_setup_bus(slot, false);
1430
1431                 if (!IS_ERR(mmc->supply.vmmc))
1432                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1433
1434                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1435                         regulator_disable(mmc->supply.vqmmc);
1436                 slot->host->vqmmc_enabled = false;
1437
1438                 regs = mci_readl(slot->host, PWREN);
1439                 regs &= ~(1 << slot->id);
1440                 mci_writel(slot->host, PWREN, regs);
1441                 break;
1442         default:
1443                 break;
1444         }
1445
1446         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1447                 slot->host->state = STATE_IDLE;
1448 }
1449
1450 static int dw_mci_card_busy(struct mmc_host *mmc)
1451 {
1452         struct dw_mci_slot *slot = mmc_priv(mmc);
1453         u32 status;
1454
1455         /*
1456          * Check the busy bit which is low when DAT[3:0]
1457          * (the data lines) are 0000
1458          */
1459         status = mci_readl(slot->host, STATUS);
1460
1461         return !!(status & SDMMC_STATUS_BUSY);
1462 }
1463
1464 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1465 {
1466         struct dw_mci_slot *slot = mmc_priv(mmc);
1467         struct dw_mci *host = slot->host;
1468         const struct dw_mci_drv_data *drv_data = host->drv_data;
1469         u32 uhs;
1470         u32 v18 = SDMMC_UHS_18V << slot->id;
1471         int ret;
1472
1473         if (drv_data && drv_data->switch_voltage)
1474                 return drv_data->switch_voltage(mmc, ios);
1475
1476         /*
1477          * Program the voltage.  Note that some instances of dw_mmc may use
1478          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1479          * does no harm but you need to set the regulator directly.  Try both.
1480          */
1481         uhs = mci_readl(host, UHS_REG);
1482         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1483                 uhs &= ~v18;
1484         else
1485                 uhs |= v18;
1486
1487         if (!IS_ERR(mmc->supply.vqmmc)) {
1488                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1489
1490                 if (ret) {
1491                         dev_dbg(&mmc->class_dev,
1492                                          "Regulator set error %d - %s V\n",
1493                                          ret, uhs & v18 ? "1.8" : "3.3");
1494                         return ret;
1495                 }
1496         }
1497         mci_writel(host, UHS_REG, uhs);
1498
1499         return 0;
1500 }
1501
1502 static int dw_mci_get_ro(struct mmc_host *mmc)
1503 {
1504         int read_only;
1505         struct dw_mci_slot *slot = mmc_priv(mmc);
1506         int gpio_ro = mmc_gpio_get_ro(mmc);
1507
1508         /* Use platform get_ro function, else try on board write protect */
1509         if (gpio_ro >= 0)
1510                 read_only = gpio_ro;
1511         else
1512                 read_only =
1513                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1514
1515         dev_dbg(&mmc->class_dev, "card is %s\n",
1516                 read_only ? "read-only" : "read-write");
1517
1518         return read_only;
1519 }
1520
1521 static int dw_mci_get_cd(struct mmc_host *mmc)
1522 {
1523         int present;
1524         struct dw_mci_slot *slot = mmc_priv(mmc);
1525         struct dw_mci *host = slot->host;
1526         int gpio_cd = mmc_gpio_get_cd(mmc);
1527
1528         /* Use platform get_cd function, else try onboard card detect */
1529         if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
1530                 present = 1;
1531         else if (gpio_cd >= 0)
1532                 present = gpio_cd;
1533         else
1534                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1535                         == 0 ? 1 : 0;
1536
1537         spin_lock_bh(&host->lock);
1538         if (present) {
1539                 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1540                 dev_dbg(&mmc->class_dev, "card is present\n");
1541         } else {
1542                 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1543                 dev_dbg(&mmc->class_dev, "card is not present\n");
1544         }
1545         spin_unlock_bh(&host->lock);
1546
1547         return present;
1548 }
1549
1550 static void dw_mci_hw_reset(struct mmc_host *mmc)
1551 {
1552         struct dw_mci_slot *slot = mmc_priv(mmc);
1553         struct dw_mci *host = slot->host;
1554         int reset;
1555
1556         if (host->use_dma == TRANS_MODE_IDMAC)
1557                 dw_mci_idmac_reset(host);
1558
1559         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1560                                      SDMMC_CTRL_FIFO_RESET))
1561                 return;
1562
1563         /*
1564          * According to eMMC spec, card reset procedure:
1565          * tRstW >= 1us:   RST_n pulse width
1566          * tRSCA >= 200us: RST_n to Command time
1567          * tRSTH >= 1us:   RST_n high period
1568          */
1569         reset = mci_readl(host, RST_N);
1570         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1571         mci_writel(host, RST_N, reset);
1572         usleep_range(1, 2);
1573         reset |= SDMMC_RST_HWACTIVE << slot->id;
1574         mci_writel(host, RST_N, reset);
1575         usleep_range(200, 300);
1576 }
1577
1578 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1579 {
1580         struct dw_mci_slot *slot = mmc_priv(mmc);
1581         struct dw_mci *host = slot->host;
1582
1583         /*
1584          * Low power mode will stop the card clock when idle.  According to the
1585          * description of the CLKENA register we should disable low power mode
1586          * for SDIO cards if we need SDIO interrupts to work.
1587          */
1588         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1589                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1590                 u32 clk_en_a_old;
1591                 u32 clk_en_a;
1592
1593                 clk_en_a_old = mci_readl(host, CLKENA);
1594
1595                 if (card->type == MMC_TYPE_SDIO ||
1596                     card->type == MMC_TYPE_SD_COMBO) {
1597                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1598                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1599                 } else {
1600                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1601                         clk_en_a = clk_en_a_old | clken_low_pwr;
1602                 }
1603
1604                 if (clk_en_a != clk_en_a_old) {
1605                         mci_writel(host, CLKENA, clk_en_a);
1606                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1607                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1608                 }
1609         }
1610 }
1611
1612 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1613 {
1614         struct dw_mci_slot *slot = mmc_priv(mmc);
1615         struct dw_mci *host = slot->host;
1616         unsigned long irqflags;
1617         u32 int_mask;
1618
1619         spin_lock_irqsave(&host->irq_lock, irqflags);
1620
1621         /* Enable/disable Slot Specific SDIO interrupt */
1622         int_mask = mci_readl(host, INTMASK);
1623         if (enb)
1624                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1625         else
1626                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1627         mci_writel(host, INTMASK, int_mask);
1628
1629         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1630 }
1631
1632 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1633 {
1634         struct dw_mci_slot *slot = mmc_priv(mmc);
1635         struct dw_mci *host = slot->host;
1636         const struct dw_mci_drv_data *drv_data = host->drv_data;
1637         int err = -EINVAL;
1638
1639         if (drv_data && drv_data->execute_tuning)
1640                 err = drv_data->execute_tuning(slot, opcode);
1641         return err;
1642 }
1643
1644 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1645                                        struct mmc_ios *ios)
1646 {
1647         struct dw_mci_slot *slot = mmc_priv(mmc);
1648         struct dw_mci *host = slot->host;
1649         const struct dw_mci_drv_data *drv_data = host->drv_data;
1650
1651         if (drv_data && drv_data->prepare_hs400_tuning)
1652                 return drv_data->prepare_hs400_tuning(host, ios);
1653
1654         return 0;
1655 }
1656
1657 static const struct mmc_host_ops dw_mci_ops = {
1658         .request                = dw_mci_request,
1659         .pre_req                = dw_mci_pre_req,
1660         .post_req               = dw_mci_post_req,
1661         .set_ios                = dw_mci_set_ios,
1662         .get_ro                 = dw_mci_get_ro,
1663         .get_cd                 = dw_mci_get_cd,
1664         .hw_reset               = dw_mci_hw_reset,
1665         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1666         .execute_tuning         = dw_mci_execute_tuning,
1667         .card_busy              = dw_mci_card_busy,
1668         .start_signal_voltage_switch = dw_mci_switch_voltage,
1669         .init_card              = dw_mci_init_card,
1670         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1671 };
1672
1673 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1674         __releases(&host->lock)
1675         __acquires(&host->lock)
1676 {
1677         struct dw_mci_slot *slot;
1678         struct mmc_host *prev_mmc = host->cur_slot->mmc;
1679
1680         WARN_ON(host->cmd || host->data);
1681
1682         host->cur_slot->mrq = NULL;
1683         host->mrq = NULL;
1684         if (!list_empty(&host->queue)) {
1685                 slot = list_entry(host->queue.next,
1686                                   struct dw_mci_slot, queue_node);
1687                 list_del(&slot->queue_node);
1688                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1689                          mmc_hostname(slot->mmc));
1690                 host->state = STATE_SENDING_CMD;
1691                 dw_mci_start_request(host, slot);
1692         } else {
1693                 dev_vdbg(host->dev, "list empty\n");
1694
1695                 if (host->state == STATE_SENDING_CMD11)
1696                         host->state = STATE_WAITING_CMD11_DONE;
1697                 else
1698                         host->state = STATE_IDLE;
1699         }
1700
1701         spin_unlock(&host->lock);
1702         mmc_request_done(prev_mmc, mrq);
1703         spin_lock(&host->lock);
1704 }
1705
1706 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1707 {
1708         u32 status = host->cmd_status;
1709
1710         host->cmd_status = 0;
1711
1712         /* Read the response from the card (up to 16 bytes) */
1713         if (cmd->flags & MMC_RSP_PRESENT) {
1714                 if (cmd->flags & MMC_RSP_136) {
1715                         cmd->resp[3] = mci_readl(host, RESP0);
1716                         cmd->resp[2] = mci_readl(host, RESP1);
1717                         cmd->resp[1] = mci_readl(host, RESP2);
1718                         cmd->resp[0] = mci_readl(host, RESP3);
1719                 } else {
1720                         cmd->resp[0] = mci_readl(host, RESP0);
1721                         cmd->resp[1] = 0;
1722                         cmd->resp[2] = 0;
1723                         cmd->resp[3] = 0;
1724                 }
1725         }
1726
1727         if (status & SDMMC_INT_RTO)
1728                 cmd->error = -ETIMEDOUT;
1729         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1730                 cmd->error = -EILSEQ;
1731         else if (status & SDMMC_INT_RESP_ERR)
1732                 cmd->error = -EIO;
1733         else
1734                 cmd->error = 0;
1735
1736         return cmd->error;
1737 }
1738
1739 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1740 {
1741         u32 status = host->data_status;
1742
1743         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1744                 if (status & SDMMC_INT_DRTO) {
1745                         data->error = -ETIMEDOUT;
1746                 } else if (status & SDMMC_INT_DCRC) {
1747                         data->error = -EILSEQ;
1748                 } else if (status & SDMMC_INT_EBE) {
1749                         if (host->dir_status ==
1750                                 DW_MCI_SEND_STATUS) {
1751                                 /*
1752                                  * No data CRC status was returned.
1753                                  * The number of bytes transferred
1754                                  * will be exaggerated in PIO mode.
1755                                  */
1756                                 data->bytes_xfered = 0;
1757                                 data->error = -ETIMEDOUT;
1758                         } else if (host->dir_status ==
1759                                         DW_MCI_RECV_STATUS) {
1760                                 data->error = -EILSEQ;
1761                         }
1762                 } else {
1763                         /* SDMMC_INT_SBE is included */
1764                         data->error = -EILSEQ;
1765                 }
1766
1767                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1768
1769                 /*
1770                  * After an error, there may be data lingering
1771                  * in the FIFO
1772                  */
1773                 dw_mci_reset(host);
1774         } else {
1775                 data->bytes_xfered = data->blocks * data->blksz;
1776                 data->error = 0;
1777         }
1778
1779         return data->error;
1780 }
1781
1782 static void dw_mci_set_drto(struct dw_mci *host)
1783 {
1784         unsigned int drto_clks;
1785         unsigned int drto_ms;
1786
1787         drto_clks = mci_readl(host, TMOUT) >> 8;
1788         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1789
1790         /* add a bit spare time */
1791         drto_ms += 10;
1792
1793         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1794 }
1795
1796 static void dw_mci_tasklet_func(unsigned long priv)
1797 {
1798         struct dw_mci *host = (struct dw_mci *)priv;
1799         struct mmc_data *data;
1800         struct mmc_command *cmd;
1801         struct mmc_request *mrq;
1802         enum dw_mci_state state;
1803         enum dw_mci_state prev_state;
1804         unsigned int err;
1805
1806         spin_lock(&host->lock);
1807
1808         state = host->state;
1809         data = host->data;
1810         mrq = host->mrq;
1811
1812         do {
1813                 prev_state = state;
1814
1815                 switch (state) {
1816                 case STATE_IDLE:
1817                 case STATE_WAITING_CMD11_DONE:
1818                         break;
1819
1820                 case STATE_SENDING_CMD11:
1821                 case STATE_SENDING_CMD:
1822                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1823                                                 &host->pending_events))
1824                                 break;
1825
1826                         cmd = host->cmd;
1827                         host->cmd = NULL;
1828                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1829                         err = dw_mci_command_complete(host, cmd);
1830                         if (cmd == mrq->sbc && !err) {
1831                                 prev_state = state = STATE_SENDING_CMD;
1832                                 __dw_mci_start_request(host, host->cur_slot,
1833                                                        mrq->cmd);
1834                                 goto unlock;
1835                         }
1836
1837                         if (cmd->data && err) {
1838                                 /*
1839                                  * During UHS tuning sequence, sending the stop
1840                                  * command after the response CRC error would
1841                                  * throw the system into a confused state
1842                                  * causing all future tuning phases to report
1843                                  * failure.
1844                                  *
1845                                  * In such case controller will move into a data
1846                                  * transfer state after a response error or
1847                                  * response CRC error. Let's let that finish
1848                                  * before trying to send a stop, so we'll go to
1849                                  * STATE_SENDING_DATA.
1850                                  *
1851                                  * Although letting the data transfer take place
1852                                  * will waste a bit of time (we already know
1853                                  * the command was bad), it can't cause any
1854                                  * errors since it's possible it would have
1855                                  * taken place anyway if this tasklet got
1856                                  * delayed. Allowing the transfer to take place
1857                                  * avoids races and keeps things simple.
1858                                  */
1859                                 if ((err != -ETIMEDOUT) &&
1860                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1861                                         state = STATE_SENDING_DATA;
1862                                         continue;
1863                                 }
1864
1865                                 dw_mci_stop_dma(host);
1866                                 send_stop_abort(host, data);
1867                                 state = STATE_SENDING_STOP;
1868                                 break;
1869                         }
1870
1871                         if (!cmd->data || err) {
1872                                 dw_mci_request_end(host, mrq);
1873                                 goto unlock;
1874                         }
1875
1876                         prev_state = state = STATE_SENDING_DATA;
1877                         /* fall through */
1878
1879                 case STATE_SENDING_DATA:
1880                         /*
1881                          * We could get a data error and never a transfer
1882                          * complete so we'd better check for it here.
1883                          *
1884                          * Note that we don't really care if we also got a
1885                          * transfer complete; stopping the DMA and sending an
1886                          * abort won't hurt.
1887                          */
1888                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1889                                                &host->pending_events)) {
1890                                 dw_mci_stop_dma(host);
1891                                 if (data->stop ||
1892                                     !(host->data_status & (SDMMC_INT_DRTO |
1893                                                            SDMMC_INT_EBE)))
1894                                         send_stop_abort(host, data);
1895                                 state = STATE_DATA_ERROR;
1896                                 break;
1897                         }
1898
1899                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1900                                                 &host->pending_events)) {
1901                                 /*
1902                                  * If all data-related interrupts don't come
1903                                  * within the given time in reading data state.
1904                                  */
1905                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1906                                         dw_mci_set_drto(host);
1907                                 break;
1908                         }
1909
1910                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1911
1912                         /*
1913                          * Handle an EVENT_DATA_ERROR that might have shown up
1914                          * before the transfer completed.  This might not have
1915                          * been caught by the check above because the interrupt
1916                          * could have gone off between the previous check and
1917                          * the check for transfer complete.
1918                          *
1919                          * Technically this ought not be needed assuming we
1920                          * get a DATA_COMPLETE eventually (we'll notice the
1921                          * error and end the request), but it shouldn't hurt.
1922                          *
1923                          * This has the advantage of sending the stop command.
1924                          */
1925                         if (test_and_clear_bit(EVENT_DATA_ERROR,
1926                                                &host->pending_events)) {
1927                                 dw_mci_stop_dma(host);
1928                                 if (data->stop ||
1929                                     !(host->data_status & (SDMMC_INT_DRTO |
1930                                                            SDMMC_INT_EBE)))
1931                                         send_stop_abort(host, data);
1932                                 state = STATE_DATA_ERROR;
1933                                 break;
1934                         }
1935                         prev_state = state = STATE_DATA_BUSY;
1936
1937                         /* fall through */
1938
1939                 case STATE_DATA_BUSY:
1940                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1941                                                 &host->pending_events)) {
1942                                 /*
1943                                  * If data error interrupt comes but data over
1944                                  * interrupt doesn't come within the given time.
1945                                  * in reading data state.
1946                                  */
1947                                 if (host->dir_status == DW_MCI_RECV_STATUS)
1948                                         dw_mci_set_drto(host);
1949                                 break;
1950                         }
1951
1952                         host->data = NULL;
1953                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1954                         err = dw_mci_data_complete(host, data);
1955
1956                         if (!err) {
1957                                 if (!data->stop || mrq->sbc) {
1958                                         if (mrq->sbc && data->stop)
1959                                                 data->stop->error = 0;
1960                                         dw_mci_request_end(host, mrq);
1961                                         goto unlock;
1962                                 }
1963
1964                                 /* stop command for open-ended transfer*/
1965                                 if (data->stop)
1966                                         send_stop_abort(host, data);
1967                         } else {
1968                                 /*
1969                                  * If we don't have a command complete now we'll
1970                                  * never get one since we just reset everything;
1971                                  * better end the request.
1972                                  *
1973                                  * If we do have a command complete we'll fall
1974                                  * through to the SENDING_STOP command and
1975                                  * everything will be peachy keen.
1976                                  */
1977                                 if (!test_bit(EVENT_CMD_COMPLETE,
1978                                               &host->pending_events)) {
1979                                         host->cmd = NULL;
1980                                         dw_mci_request_end(host, mrq);
1981                                         goto unlock;
1982                                 }
1983                         }
1984
1985                         /*
1986                          * If err has non-zero,
1987                          * stop-abort command has been already issued.
1988                          */
1989                         prev_state = state = STATE_SENDING_STOP;
1990
1991                         /* fall through */
1992
1993                 case STATE_SENDING_STOP:
1994                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1995                                                 &host->pending_events))
1996                                 break;
1997
1998                         /* CMD error in data command */
1999                         if (mrq->cmd->error && mrq->data)
2000                                 dw_mci_reset(host);
2001
2002                         host->cmd = NULL;
2003                         host->data = NULL;
2004
2005                         if (mrq->stop)
2006                                 dw_mci_command_complete(host, mrq->stop);
2007                         else
2008                                 host->cmd_status = 0;
2009
2010                         dw_mci_request_end(host, mrq);
2011                         goto unlock;
2012
2013                 case STATE_DATA_ERROR:
2014                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2015                                                 &host->pending_events))
2016                                 break;
2017
2018                         state = STATE_DATA_BUSY;
2019                         break;
2020                 }
2021         } while (state != prev_state);
2022
2023         host->state = state;
2024 unlock:
2025         spin_unlock(&host->lock);
2026
2027 }
2028
2029 /* push final bytes to part_buf, only use during push */
2030 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2031 {
2032         memcpy((void *)&host->part_buf, buf, cnt);
2033         host->part_buf_count = cnt;
2034 }
2035
2036 /* append bytes to part_buf, only use during push */
2037 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2038 {
2039         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2040         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2041         host->part_buf_count += cnt;
2042         return cnt;
2043 }
2044
2045 /* pull first bytes from part_buf, only use during pull */
2046 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2047 {
2048         cnt = min_t(int, cnt, host->part_buf_count);
2049         if (cnt) {
2050                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2051                        cnt);
2052                 host->part_buf_count -= cnt;
2053                 host->part_buf_start += cnt;
2054         }
2055         return cnt;
2056 }
2057
2058 /* pull final bytes from the part_buf, assuming it's just been filled */
2059 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2060 {
2061         memcpy(buf, &host->part_buf, cnt);
2062         host->part_buf_start = cnt;
2063         host->part_buf_count = (1 << host->data_shift) - cnt;
2064 }
2065
2066 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2067 {
2068         struct mmc_data *data = host->data;
2069         int init_cnt = cnt;
2070
2071         /* try and push anything in the part_buf */
2072         if (unlikely(host->part_buf_count)) {
2073                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2074
2075                 buf += len;
2076                 cnt -= len;
2077                 if (host->part_buf_count == 2) {
2078                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2079                         host->part_buf_count = 0;
2080                 }
2081         }
2082 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2083         if (unlikely((unsigned long)buf & 0x1)) {
2084                 while (cnt >= 2) {
2085                         u16 aligned_buf[64];
2086                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2087                         int items = len >> 1;
2088                         int i;
2089                         /* memcpy from input buffer into aligned buffer */
2090                         memcpy(aligned_buf, buf, len);
2091                         buf += len;
2092                         cnt -= len;
2093                         /* push data from aligned buffer into fifo */
2094                         for (i = 0; i < items; ++i)
2095                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2096                 }
2097         } else
2098 #endif
2099         {
2100                 u16 *pdata = buf;
2101
2102                 for (; cnt >= 2; cnt -= 2)
2103                         mci_fifo_writew(host->fifo_reg, *pdata++);
2104                 buf = pdata;
2105         }
2106         /* put anything remaining in the part_buf */
2107         if (cnt) {
2108                 dw_mci_set_part_bytes(host, buf, cnt);
2109                  /* Push data if we have reached the expected data length */
2110                 if ((data->bytes_xfered + init_cnt) ==
2111                     (data->blksz * data->blocks))
2112                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2113         }
2114 }
2115
2116 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2117 {
2118 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2119         if (unlikely((unsigned long)buf & 0x1)) {
2120                 while (cnt >= 2) {
2121                         /* pull data from fifo into aligned buffer */
2122                         u16 aligned_buf[64];
2123                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2124                         int items = len >> 1;
2125                         int i;
2126
2127                         for (i = 0; i < items; ++i)
2128                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2129                         /* memcpy from aligned buffer into output buffer */
2130                         memcpy(buf, aligned_buf, len);
2131                         buf += len;
2132                         cnt -= len;
2133                 }
2134         } else
2135 #endif
2136         {
2137                 u16 *pdata = buf;
2138
2139                 for (; cnt >= 2; cnt -= 2)
2140                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2141                 buf = pdata;
2142         }
2143         if (cnt) {
2144                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2145                 dw_mci_pull_final_bytes(host, buf, cnt);
2146         }
2147 }
2148
2149 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2150 {
2151         struct mmc_data *data = host->data;
2152         int init_cnt = cnt;
2153
2154         /* try and push anything in the part_buf */
2155         if (unlikely(host->part_buf_count)) {
2156                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2157
2158                 buf += len;
2159                 cnt -= len;
2160                 if (host->part_buf_count == 4) {
2161                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2162                         host->part_buf_count = 0;
2163                 }
2164         }
2165 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2166         if (unlikely((unsigned long)buf & 0x3)) {
2167                 while (cnt >= 4) {
2168                         u32 aligned_buf[32];
2169                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2170                         int items = len >> 2;
2171                         int i;
2172                         /* memcpy from input buffer into aligned buffer */
2173                         memcpy(aligned_buf, buf, len);
2174                         buf += len;
2175                         cnt -= len;
2176                         /* push data from aligned buffer into fifo */
2177                         for (i = 0; i < items; ++i)
2178                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2179                 }
2180         } else
2181 #endif
2182         {
2183                 u32 *pdata = buf;
2184
2185                 for (; cnt >= 4; cnt -= 4)
2186                         mci_fifo_writel(host->fifo_reg, *pdata++);
2187                 buf = pdata;
2188         }
2189         /* put anything remaining in the part_buf */
2190         if (cnt) {
2191                 dw_mci_set_part_bytes(host, buf, cnt);
2192                  /* Push data if we have reached the expected data length */
2193                 if ((data->bytes_xfered + init_cnt) ==
2194                     (data->blksz * data->blocks))
2195                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2196         }
2197 }
2198
2199 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2200 {
2201 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2202         if (unlikely((unsigned long)buf & 0x3)) {
2203                 while (cnt >= 4) {
2204                         /* pull data from fifo into aligned buffer */
2205                         u32 aligned_buf[32];
2206                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2207                         int items = len >> 2;
2208                         int i;
2209
2210                         for (i = 0; i < items; ++i)
2211                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2212                         /* memcpy from aligned buffer into output buffer */
2213                         memcpy(buf, aligned_buf, len);
2214                         buf += len;
2215                         cnt -= len;
2216                 }
2217         } else
2218 #endif
2219         {
2220                 u32 *pdata = buf;
2221
2222                 for (; cnt >= 4; cnt -= 4)
2223                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2224                 buf = pdata;
2225         }
2226         if (cnt) {
2227                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2228                 dw_mci_pull_final_bytes(host, buf, cnt);
2229         }
2230 }
2231
2232 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2233 {
2234         struct mmc_data *data = host->data;
2235         int init_cnt = cnt;
2236
2237         /* try and push anything in the part_buf */
2238         if (unlikely(host->part_buf_count)) {
2239                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2240
2241                 buf += len;
2242                 cnt -= len;
2243
2244                 if (host->part_buf_count == 8) {
2245                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2246                         host->part_buf_count = 0;
2247                 }
2248         }
2249 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2250         if (unlikely((unsigned long)buf & 0x7)) {
2251                 while (cnt >= 8) {
2252                         u64 aligned_buf[16];
2253                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2254                         int items = len >> 3;
2255                         int i;
2256                         /* memcpy from input buffer into aligned buffer */
2257                         memcpy(aligned_buf, buf, len);
2258                         buf += len;
2259                         cnt -= len;
2260                         /* push data from aligned buffer into fifo */
2261                         for (i = 0; i < items; ++i)
2262                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2263                 }
2264         } else
2265 #endif
2266         {
2267                 u64 *pdata = buf;
2268
2269                 for (; cnt >= 8; cnt -= 8)
2270                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2271                 buf = pdata;
2272         }
2273         /* put anything remaining in the part_buf */
2274         if (cnt) {
2275                 dw_mci_set_part_bytes(host, buf, cnt);
2276                 /* Push data if we have reached the expected data length */
2277                 if ((data->bytes_xfered + init_cnt) ==
2278                     (data->blksz * data->blocks))
2279                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2280         }
2281 }
2282
2283 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2284 {
2285 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2286         if (unlikely((unsigned long)buf & 0x7)) {
2287                 while (cnt >= 8) {
2288                         /* pull data from fifo into aligned buffer */
2289                         u64 aligned_buf[16];
2290                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2291                         int items = len >> 3;
2292                         int i;
2293
2294                         for (i = 0; i < items; ++i)
2295                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2296
2297                         /* memcpy from aligned buffer into output buffer */
2298                         memcpy(buf, aligned_buf, len);
2299                         buf += len;
2300                         cnt -= len;
2301                 }
2302         } else
2303 #endif
2304         {
2305                 u64 *pdata = buf;
2306
2307                 for (; cnt >= 8; cnt -= 8)
2308                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2309                 buf = pdata;
2310         }
2311         if (cnt) {
2312                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2313                 dw_mci_pull_final_bytes(host, buf, cnt);
2314         }
2315 }
2316
2317 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2318 {
2319         int len;
2320
2321         /* get remaining partial bytes */
2322         len = dw_mci_pull_part_bytes(host, buf, cnt);
2323         if (unlikely(len == cnt))
2324                 return;
2325         buf += len;
2326         cnt -= len;
2327
2328         /* get the rest of the data */
2329         host->pull_data(host, buf, cnt);
2330 }
2331
2332 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2333 {
2334         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2335         void *buf;
2336         unsigned int offset;
2337         struct mmc_data *data = host->data;
2338         int shift = host->data_shift;
2339         u32 status;
2340         unsigned int len;
2341         unsigned int remain, fcnt;
2342
2343         do {
2344                 if (!sg_miter_next(sg_miter))
2345                         goto done;
2346
2347                 host->sg = sg_miter->piter.sg;
2348                 buf = sg_miter->addr;
2349                 remain = sg_miter->length;
2350                 offset = 0;
2351
2352                 do {
2353                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2354                                         << shift) + host->part_buf_count;
2355                         len = min(remain, fcnt);
2356                         if (!len)
2357                                 break;
2358                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2359                         data->bytes_xfered += len;
2360                         offset += len;
2361                         remain -= len;
2362                 } while (remain);
2363
2364                 sg_miter->consumed = offset;
2365                 status = mci_readl(host, MINTSTS);
2366                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2367         /* if the RXDR is ready read again */
2368         } while ((status & SDMMC_INT_RXDR) ||
2369                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2370
2371         if (!remain) {
2372                 if (!sg_miter_next(sg_miter))
2373                         goto done;
2374                 sg_miter->consumed = 0;
2375         }
2376         sg_miter_stop(sg_miter);
2377         return;
2378
2379 done:
2380         sg_miter_stop(sg_miter);
2381         host->sg = NULL;
2382         smp_wmb(); /* drain writebuffer */
2383         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2384 }
2385
2386 static void dw_mci_write_data_pio(struct dw_mci *host)
2387 {
2388         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2389         void *buf;
2390         unsigned int offset;
2391         struct mmc_data *data = host->data;
2392         int shift = host->data_shift;
2393         u32 status;
2394         unsigned int len;
2395         unsigned int fifo_depth = host->fifo_depth;
2396         unsigned int remain, fcnt;
2397
2398         do {
2399                 if (!sg_miter_next(sg_miter))
2400                         goto done;
2401
2402                 host->sg = sg_miter->piter.sg;
2403                 buf = sg_miter->addr;
2404                 remain = sg_miter->length;
2405                 offset = 0;
2406
2407                 do {
2408                         fcnt = ((fifo_depth -
2409                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2410                                         << shift) - host->part_buf_count;
2411                         len = min(remain, fcnt);
2412                         if (!len)
2413                                 break;
2414                         host->push_data(host, (void *)(buf + offset), len);
2415                         data->bytes_xfered += len;
2416                         offset += len;
2417                         remain -= len;
2418                 } while (remain);
2419
2420                 sg_miter->consumed = offset;
2421                 status = mci_readl(host, MINTSTS);
2422                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2423         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2424
2425         if (!remain) {
2426                 if (!sg_miter_next(sg_miter))
2427                         goto done;
2428                 sg_miter->consumed = 0;
2429         }
2430         sg_miter_stop(sg_miter);
2431         return;
2432
2433 done:
2434         sg_miter_stop(sg_miter);
2435         host->sg = NULL;
2436         smp_wmb(); /* drain writebuffer */
2437         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2438 }
2439
2440 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2441 {
2442         if (!host->cmd_status)
2443                 host->cmd_status = status;
2444
2445         smp_wmb(); /* drain writebuffer */
2446
2447         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2448         tasklet_schedule(&host->tasklet);
2449 }
2450
2451 static void dw_mci_handle_cd(struct dw_mci *host)
2452 {
2453         int i;
2454
2455         for (i = 0; i < host->num_slots; i++) {
2456                 struct dw_mci_slot *slot = host->slot[i];
2457
2458                 if (!slot)
2459                         continue;
2460
2461                 if (slot->mmc->ops->card_event)
2462                         slot->mmc->ops->card_event(slot->mmc);
2463                 mmc_detect_change(slot->mmc,
2464                         msecs_to_jiffies(host->pdata->detect_delay_ms));
2465         }
2466 }
2467
2468 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2469 {
2470         struct dw_mci *host = dev_id;
2471         u32 pending;
2472         int i;
2473
2474         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2475
2476         if (pending) {
2477                 /* Check volt switch first, since it can look like an error */
2478                 if ((host->state == STATE_SENDING_CMD11) &&
2479                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2480                         unsigned long irqflags;
2481
2482                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2483                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2484
2485                         /*
2486                          * Hold the lock; we know cmd11_timer can't be kicked
2487                          * off after the lock is released, so safe to delete.
2488                          */
2489                         spin_lock_irqsave(&host->irq_lock, irqflags);
2490                         dw_mci_cmd_interrupt(host, pending);
2491                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2492
2493                         del_timer(&host->cmd11_timer);
2494                 }
2495
2496                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2497                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2498                         host->cmd_status = pending;
2499                         smp_wmb(); /* drain writebuffer */
2500                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2501                 }
2502
2503                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2504                         /* if there is an error report DATA_ERROR */
2505                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2506                         host->data_status = pending;
2507                         smp_wmb(); /* drain writebuffer */
2508                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2509                         tasklet_schedule(&host->tasklet);
2510                 }
2511
2512                 if (pending & SDMMC_INT_DATA_OVER) {
2513                         del_timer(&host->dto_timer);
2514
2515                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2516                         if (!host->data_status)
2517                                 host->data_status = pending;
2518                         smp_wmb(); /* drain writebuffer */
2519                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2520                                 if (host->sg != NULL)
2521                                         dw_mci_read_data_pio(host, true);
2522                         }
2523                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2524                         tasklet_schedule(&host->tasklet);
2525                 }
2526
2527                 if (pending & SDMMC_INT_RXDR) {
2528                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2529                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2530                                 dw_mci_read_data_pio(host, false);
2531                 }
2532
2533                 if (pending & SDMMC_INT_TXDR) {
2534                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2535                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2536                                 dw_mci_write_data_pio(host);
2537                 }
2538
2539                 if (pending & SDMMC_INT_CMD_DONE) {
2540                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2541                         dw_mci_cmd_interrupt(host, pending);
2542                 }
2543
2544                 if (pending & SDMMC_INT_CD) {
2545                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2546                         dw_mci_handle_cd(host);
2547                 }
2548
2549                 /* Handle SDIO Interrupts */
2550                 for (i = 0; i < host->num_slots; i++) {
2551                         struct dw_mci_slot *slot = host->slot[i];
2552
2553                         if (!slot)
2554                                 continue;
2555
2556                         if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2557                                 mci_writel(host, RINTSTS,
2558                                            SDMMC_INT_SDIO(slot->sdio_id));
2559                                 mmc_signal_sdio_irq(slot->mmc);
2560                         }
2561                 }
2562
2563         }
2564
2565         if (host->use_dma != TRANS_MODE_IDMAC)
2566                 return IRQ_HANDLED;
2567
2568         /* Handle IDMA interrupts */
2569         if (host->dma_64bit_address == 1) {
2570                 pending = mci_readl(host, IDSTS64);
2571                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2572                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2573                                                         SDMMC_IDMAC_INT_RI);
2574                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2575                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2576                                 host->dma_ops->complete((void *)host);
2577                 }
2578         } else {
2579                 pending = mci_readl(host, IDSTS);
2580                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2581                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2582                                                         SDMMC_IDMAC_INT_RI);
2583                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2584                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2585                                 host->dma_ops->complete((void *)host);
2586                 }
2587         }
2588
2589         return IRQ_HANDLED;
2590 }
2591
2592 static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
2593 {
2594         struct mmc_host *mmc;
2595         struct dw_mci_slot *slot;
2596         const struct dw_mci_drv_data *drv_data = host->drv_data;
2597         int ctrl_id, ret;
2598         u32 freq[2];
2599
2600         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2601         if (!mmc)
2602                 return -ENOMEM;
2603
2604         slot = mmc_priv(mmc);
2605         slot->id = id;
2606         slot->sdio_id = host->sdio_id0 + id;
2607         slot->mmc = mmc;
2608         slot->host = host;
2609         host->slot[id] = slot;
2610
2611         mmc->ops = &dw_mci_ops;
2612         if (of_property_read_u32_array(host->dev->of_node,
2613                                        "clock-freq-min-max", freq, 2)) {
2614                 mmc->f_min = DW_MCI_FREQ_MIN;
2615                 mmc->f_max = DW_MCI_FREQ_MAX;
2616         } else {
2617                 mmc->f_min = freq[0];
2618                 mmc->f_max = freq[1];
2619         }
2620
2621         /*if there are external regulators, get them*/
2622         ret = mmc_regulator_get_supply(mmc);
2623         if (ret == -EPROBE_DEFER)
2624                 goto err_host_allocated;
2625
2626         if (!mmc->ocr_avail)
2627                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2628
2629         if (host->pdata->caps)
2630                 mmc->caps = host->pdata->caps;
2631
2632         /*
2633          * Support MMC_CAP_ERASE by default.
2634          * It needs to use trim/discard/erase commands.
2635          */
2636         mmc->caps |= MMC_CAP_ERASE;
2637
2638         if (host->pdata->pm_caps)
2639                 mmc->pm_caps = host->pdata->pm_caps;
2640
2641         if (host->dev->of_node) {
2642                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2643                 if (ctrl_id < 0)
2644                         ctrl_id = 0;
2645         } else {
2646                 ctrl_id = to_platform_device(host->dev)->id;
2647         }
2648         if (drv_data && drv_data->caps)
2649                 mmc->caps |= drv_data->caps[ctrl_id];
2650
2651         if (host->pdata->caps2)
2652                 mmc->caps2 = host->pdata->caps2;
2653
2654         ret = mmc_of_parse(mmc);
2655         if (ret)
2656                 goto err_host_allocated;
2657
2658         /* Useful defaults if platform data is unset. */
2659         if (host->use_dma == TRANS_MODE_IDMAC) {
2660                 mmc->max_segs = host->ring_size;
2661                 mmc->max_blk_size = 65535;
2662                 mmc->max_seg_size = 0x1000;
2663                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2664                 mmc->max_blk_count = mmc->max_req_size / 512;
2665         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2666                 mmc->max_segs = 64;
2667                 mmc->max_blk_size = 65535;
2668                 mmc->max_blk_count = 65535;
2669                 mmc->max_req_size =
2670                                 mmc->max_blk_size * mmc->max_blk_count;
2671                 mmc->max_seg_size = mmc->max_req_size;
2672         } else {
2673                 /* TRANS_MODE_PIO */
2674                 mmc->max_segs = 64;
2675                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2676                 mmc->max_blk_count = 512;
2677                 mmc->max_req_size = mmc->max_blk_size *
2678                                     mmc->max_blk_count;
2679                 mmc->max_seg_size = mmc->max_req_size;
2680         }
2681
2682         dw_mci_get_cd(mmc);
2683
2684         ret = mmc_add_host(mmc);
2685         if (ret)
2686                 goto err_host_allocated;
2687
2688 #if defined(CONFIG_DEBUG_FS)
2689         dw_mci_init_debugfs(slot);
2690 #endif
2691
2692         return 0;
2693
2694 err_host_allocated:
2695         mmc_free_host(mmc);
2696         return ret;
2697 }
2698
2699 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2700 {
2701         /* Debugfs stuff is cleaned up by mmc core */
2702         mmc_remove_host(slot->mmc);
2703         slot->host->slot[id] = NULL;
2704         mmc_free_host(slot->mmc);
2705 }
2706
2707 static void dw_mci_init_dma(struct dw_mci *host)
2708 {
2709         int addr_config;
2710         struct device *dev = host->dev;
2711         struct device_node *np = dev->of_node;
2712
2713         /*
2714         * Check tansfer mode from HCON[17:16]
2715         * Clear the ambiguous description of dw_mmc databook:
2716         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2717         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2718         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2719         * 2b'11: Non DW DMA Interface -> pio only
2720         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2721         * simpler request/acknowledge handshake mechanism and both of them
2722         * are regarded as external dma master for dw_mmc.
2723         */
2724         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2725         if (host->use_dma == DMA_INTERFACE_IDMA) {
2726                 host->use_dma = TRANS_MODE_IDMAC;
2727         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2728                    host->use_dma == DMA_INTERFACE_GDMA) {
2729                 host->use_dma = TRANS_MODE_EDMAC;
2730         } else {
2731                 goto no_dma;
2732         }
2733
2734         /* Determine which DMA interface to use */
2735         if (host->use_dma == TRANS_MODE_IDMAC) {
2736                 /*
2737                 * Check ADDR_CONFIG bit in HCON to find
2738                 * IDMAC address bus width
2739                 */
2740                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2741
2742                 if (addr_config == 1) {
2743                         /* host supports IDMAC in 64-bit address mode */
2744                         host->dma_64bit_address = 1;
2745                         dev_info(host->dev,
2746                                  "IDMAC supports 64-bit address mode.\n");
2747                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2748                                 dma_set_coherent_mask(host->dev,
2749                                                       DMA_BIT_MASK(64));
2750                 } else {
2751                         /* host supports IDMAC in 32-bit address mode */
2752                         host->dma_64bit_address = 0;
2753                         dev_info(host->dev,
2754                                  "IDMAC supports 32-bit address mode.\n");
2755                 }
2756
2757                 /* Alloc memory for sg translation */
2758                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2759                                                    DESC_RING_BUF_SZ,
2760                                                    &host->sg_dma, GFP_KERNEL);
2761                 if (!host->sg_cpu) {
2762                         dev_err(host->dev,
2763                                 "%s: could not alloc DMA memory\n",
2764                                 __func__);
2765                         goto no_dma;
2766                 }
2767
2768                 host->dma_ops = &dw_mci_idmac_ops;
2769                 dev_info(host->dev, "Using internal DMA controller.\n");
2770         } else {
2771                 /* TRANS_MODE_EDMAC: check dma bindings again */
2772                 if ((of_property_count_strings(np, "dma-names") < 0) ||
2773                     (!of_find_property(np, "dmas", NULL))) {
2774                         goto no_dma;
2775                 }
2776                 host->dma_ops = &dw_mci_edmac_ops;
2777                 dev_info(host->dev, "Using external DMA controller.\n");
2778         }
2779
2780         if (host->dma_ops->init && host->dma_ops->start &&
2781             host->dma_ops->stop && host->dma_ops->cleanup) {
2782                 if (host->dma_ops->init(host)) {
2783                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2784                                 __func__);
2785                         goto no_dma;
2786                 }
2787         } else {
2788                 dev_err(host->dev, "DMA initialization not found.\n");
2789                 goto no_dma;
2790         }
2791
2792         return;
2793
2794 no_dma:
2795         dev_info(host->dev, "Using PIO mode.\n");
2796         host->use_dma = TRANS_MODE_PIO;
2797 }
2798
2799 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
2800 {
2801         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2802         u32 ctrl;
2803
2804         ctrl = mci_readl(host, CTRL);
2805         ctrl |= reset;
2806         mci_writel(host, CTRL, ctrl);
2807
2808         /* wait till resets clear */
2809         do {
2810                 ctrl = mci_readl(host, CTRL);
2811                 if (!(ctrl & reset))
2812                         return true;
2813         } while (time_before(jiffies, timeout));
2814
2815         dev_err(host->dev,
2816                 "Timeout resetting block (ctrl reset %#x)\n",
2817                 ctrl & reset);
2818
2819         return false;
2820 }
2821
2822 static bool dw_mci_reset(struct dw_mci *host)
2823 {
2824         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2825         bool ret = false;
2826
2827         /*
2828          * Reseting generates a block interrupt, hence setting
2829          * the scatter-gather pointer to NULL.
2830          */
2831         if (host->sg) {
2832                 sg_miter_stop(&host->sg_miter);
2833                 host->sg = NULL;
2834         }
2835
2836         if (host->use_dma)
2837                 flags |= SDMMC_CTRL_DMA_RESET;
2838
2839         if (dw_mci_ctrl_reset(host, flags)) {
2840                 /*
2841                  * In all cases we clear the RAWINTS register to clear any
2842                  * interrupts.
2843                  */
2844                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2845
2846                 /* if using dma we wait for dma_req to clear */
2847                 if (host->use_dma) {
2848                         unsigned long timeout = jiffies + msecs_to_jiffies(500);
2849                         u32 status;
2850
2851                         do {
2852                                 status = mci_readl(host, STATUS);
2853                                 if (!(status & SDMMC_STATUS_DMA_REQ))
2854                                         break;
2855                                 cpu_relax();
2856                         } while (time_before(jiffies, timeout));
2857
2858                         if (status & SDMMC_STATUS_DMA_REQ) {
2859                                 dev_err(host->dev,
2860                                         "%s: Timeout waiting for dma_req to clear during reset\n",
2861                                         __func__);
2862                                 goto ciu_out;
2863                         }
2864
2865                         /* when using DMA next we reset the fifo again */
2866                         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2867                                 goto ciu_out;
2868                 }
2869         } else {
2870                 /* if the controller reset bit did clear, then set clock regs */
2871                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2872                         dev_err(host->dev,
2873                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
2874                                 __func__);
2875                         goto ciu_out;
2876                 }
2877         }
2878
2879         if (host->use_dma == TRANS_MODE_IDMAC)
2880                 /* It is also recommended that we reset and reprogram idmac */
2881                 dw_mci_idmac_reset(host);
2882
2883         ret = true;
2884
2885 ciu_out:
2886         /* After a CTRL reset we need to have CIU set clock registers  */
2887         mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2888
2889         return ret;
2890 }
2891
2892 static void dw_mci_cmd11_timer(unsigned long arg)
2893 {
2894         struct dw_mci *host = (struct dw_mci *)arg;
2895
2896         if (host->state != STATE_SENDING_CMD11) {
2897                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2898                 return;
2899         }
2900
2901         host->cmd_status = SDMMC_INT_RTO;
2902         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2903         tasklet_schedule(&host->tasklet);
2904 }
2905
2906 static void dw_mci_dto_timer(unsigned long arg)
2907 {
2908         struct dw_mci *host = (struct dw_mci *)arg;
2909
2910         switch (host->state) {
2911         case STATE_SENDING_DATA:
2912         case STATE_DATA_BUSY:
2913                 /*
2914                  * If DTO interrupt does NOT come in sending data state,
2915                  * we should notify the driver to terminate current transfer
2916                  * and report a data timeout to the core.
2917                  */
2918                 host->data_status = SDMMC_INT_DRTO;
2919                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2920                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2921                 tasklet_schedule(&host->tasklet);
2922                 break;
2923         default:
2924                 break;
2925         }
2926 }
2927
2928 #ifdef CONFIG_OF
2929 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2930 {
2931         struct dw_mci_board *pdata;
2932         struct device *dev = host->dev;
2933         struct device_node *np = dev->of_node;
2934         const struct dw_mci_drv_data *drv_data = host->drv_data;
2935         int ret;
2936         u32 clock_frequency;
2937
2938         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2939         if (!pdata)
2940                 return ERR_PTR(-ENOMEM);
2941
2942         /* find reset controller when exist */
2943         pdata->rstc = devm_reset_control_get_optional(dev, NULL);
2944         if (IS_ERR(pdata->rstc)) {
2945                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2946                         return ERR_PTR(-EPROBE_DEFER);
2947         }
2948
2949         /* find out number of slots supported */
2950         of_property_read_u32(np, "num-slots", &pdata->num_slots);
2951
2952         if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2953                 dev_info(dev,
2954                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2955
2956         of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2957
2958         if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2959                 pdata->bus_hz = clock_frequency;
2960
2961         if (drv_data && drv_data->parse_dt) {
2962                 ret = drv_data->parse_dt(host);
2963                 if (ret)
2964                         return ERR_PTR(ret);
2965         }
2966
2967         return pdata;
2968 }
2969
2970 #else /* CONFIG_OF */
2971 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2972 {
2973         return ERR_PTR(-EINVAL);
2974 }
2975 #endif /* CONFIG_OF */
2976
2977 static void dw_mci_enable_cd(struct dw_mci *host)
2978 {
2979         unsigned long irqflags;
2980         u32 temp;
2981         int i;
2982         struct dw_mci_slot *slot;
2983
2984         /*
2985          * No need for CD if all slots have a non-error GPIO
2986          * as well as broken card detection is found.
2987          */
2988         for (i = 0; i < host->num_slots; i++) {
2989                 slot = host->slot[i];
2990                 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2991                         return;
2992
2993                 if (mmc_gpio_get_cd(slot->mmc) < 0)
2994                         break;
2995         }
2996         if (i == host->num_slots)
2997                 return;
2998
2999         spin_lock_irqsave(&host->irq_lock, irqflags);
3000         temp = mci_readl(host, INTMASK);
3001         temp  |= SDMMC_INT_CD;
3002         mci_writel(host, INTMASK, temp);
3003         spin_unlock_irqrestore(&host->irq_lock, irqflags);
3004 }
3005
3006 int dw_mci_probe(struct dw_mci *host)
3007 {
3008         const struct dw_mci_drv_data *drv_data = host->drv_data;
3009         int width, i, ret = 0;
3010         u32 fifo_size;
3011         int init_slots = 0;
3012
3013         if (!host->pdata) {
3014                 host->pdata = dw_mci_parse_dt(host);
3015                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3016                         return -EPROBE_DEFER;
3017                 } else if (IS_ERR(host->pdata)) {
3018                         dev_err(host->dev, "platform data not available\n");
3019                         return -EINVAL;
3020                 }
3021         }
3022
3023         host->biu_clk = devm_clk_get(host->dev, "biu");
3024         if (IS_ERR(host->biu_clk)) {
3025                 dev_dbg(host->dev, "biu clock not available\n");
3026         } else {
3027                 ret = clk_prepare_enable(host->biu_clk);
3028                 if (ret) {
3029                         dev_err(host->dev, "failed to enable biu clock\n");
3030                         return ret;
3031                 }
3032         }
3033
3034         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3035         if (IS_ERR(host->ciu_clk)) {
3036                 dev_dbg(host->dev, "ciu clock not available\n");
3037                 host->bus_hz = host->pdata->bus_hz;
3038         } else {
3039                 ret = clk_prepare_enable(host->ciu_clk);
3040                 if (ret) {
3041                         dev_err(host->dev, "failed to enable ciu clock\n");
3042                         goto err_clk_biu;
3043                 }
3044
3045                 if (host->pdata->bus_hz) {
3046                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3047                         if (ret)
3048                                 dev_warn(host->dev,
3049                                          "Unable to set bus rate to %uHz\n",
3050                                          host->pdata->bus_hz);
3051                 }
3052                 host->bus_hz = clk_get_rate(host->ciu_clk);
3053         }
3054
3055         if (!host->bus_hz) {
3056                 dev_err(host->dev,
3057                         "Platform data must supply bus speed\n");
3058                 ret = -ENODEV;
3059                 goto err_clk_ciu;
3060         }
3061
3062         if (drv_data && drv_data->init) {
3063                 ret = drv_data->init(host);
3064                 if (ret) {
3065                         dev_err(host->dev,
3066                                 "implementation specific init failed\n");
3067                         goto err_clk_ciu;
3068                 }
3069         }
3070
3071         if (!IS_ERR(host->pdata->rstc)) {
3072                 reset_control_assert(host->pdata->rstc);
3073                 usleep_range(10, 50);
3074                 reset_control_deassert(host->pdata->rstc);
3075         }
3076
3077         setup_timer(&host->cmd11_timer,
3078                     dw_mci_cmd11_timer, (unsigned long)host);
3079
3080         setup_timer(&host->dto_timer,
3081                     dw_mci_dto_timer, (unsigned long)host);
3082
3083         spin_lock_init(&host->lock);
3084         spin_lock_init(&host->irq_lock);
3085         INIT_LIST_HEAD(&host->queue);
3086
3087         /*
3088          * Get the host data width - this assumes that HCON has been set with
3089          * the correct values.
3090          */
3091         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3092         if (!i) {
3093                 host->push_data = dw_mci_push_data16;
3094                 host->pull_data = dw_mci_pull_data16;
3095                 width = 16;
3096                 host->data_shift = 1;
3097         } else if (i == 2) {
3098                 host->push_data = dw_mci_push_data64;
3099                 host->pull_data = dw_mci_pull_data64;
3100                 width = 64;
3101                 host->data_shift = 3;
3102         } else {
3103                 /* Check for a reserved value, and warn if it is */
3104                 WARN((i != 1),
3105                      "HCON reports a reserved host data width!\n"
3106                      "Defaulting to 32-bit access.\n");
3107                 host->push_data = dw_mci_push_data32;
3108                 host->pull_data = dw_mci_pull_data32;
3109                 width = 32;
3110                 host->data_shift = 2;
3111         }
3112
3113         /* Reset all blocks */
3114         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3115                 ret = -ENODEV;
3116                 goto err_clk_ciu;
3117         }
3118
3119         host->dma_ops = host->pdata->dma_ops;
3120         dw_mci_init_dma(host);
3121
3122         /* Clear the interrupts for the host controller */
3123         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3124         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3125
3126         /* Put in max timeout */
3127         mci_writel(host, TMOUT, 0xFFFFFFFF);
3128
3129         /*
3130          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3131          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3132          */
3133         if (!host->pdata->fifo_depth) {
3134                 /*
3135                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3136                  * have been overwritten by the bootloader, just like we're
3137                  * about to do, so if you know the value for your hardware, you
3138                  * should put it in the platform data.
3139                  */
3140                 fifo_size = mci_readl(host, FIFOTH);
3141                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3142         } else {
3143                 fifo_size = host->pdata->fifo_depth;
3144         }
3145         host->fifo_depth = fifo_size;
3146         host->fifoth_val =
3147                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3148         mci_writel(host, FIFOTH, host->fifoth_val);
3149
3150         /* disable clock to CIU */
3151         mci_writel(host, CLKENA, 0);
3152         mci_writel(host, CLKSRC, 0);
3153
3154         /*
3155          * In 2.40a spec, Data offset is changed.
3156          * Need to check the version-id and set data-offset for DATA register.
3157          */
3158         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3159         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3160
3161         if (host->verid < DW_MMC_240A)
3162                 host->fifo_reg = host->regs + DATA_OFFSET;
3163         else
3164                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3165
3166         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3167         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3168                                host->irq_flags, "dw-mci", host);
3169         if (ret)
3170                 goto err_dmaunmap;
3171
3172         if (host->pdata->num_slots)
3173                 host->num_slots = host->pdata->num_slots;
3174         else
3175                 host->num_slots = 1;
3176
3177         if (host->num_slots < 1 ||
3178             host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3179                 dev_err(host->dev,
3180                         "Platform data must supply correct num_slots.\n");
3181                 ret = -ENODEV;
3182                 goto err_clk_ciu;
3183         }
3184
3185         /*
3186          * Enable interrupts for command done, data over, data empty,
3187          * receive ready and error such as transmit, receive timeout, crc error
3188          */
3189         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3190                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3191                    DW_MCI_ERROR_FLAGS);
3192         /* Enable mci interrupt */
3193         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3194
3195         dev_info(host->dev,
3196                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3197                  host->irq, width, fifo_size);
3198
3199         /* We need at least one slot to succeed */
3200         for (i = 0; i < host->num_slots; i++) {
3201                 ret = dw_mci_init_slot(host, i);
3202                 if (ret)
3203                         dev_dbg(host->dev, "slot %d init failed\n", i);
3204                 else
3205                         init_slots++;
3206         }
3207
3208         if (init_slots) {
3209                 dev_info(host->dev, "%d slots initialized\n", init_slots);
3210         } else {
3211                 dev_dbg(host->dev,
3212                         "attempted to initialize %d slots, but failed on all\n",
3213                         host->num_slots);
3214                 goto err_dmaunmap;
3215         }
3216
3217         /* Now that slots are all setup, we can enable card detect */
3218         dw_mci_enable_cd(host);
3219
3220         return 0;
3221
3222 err_dmaunmap:
3223         if (host->use_dma && host->dma_ops->exit)
3224                 host->dma_ops->exit(host);
3225
3226         if (!IS_ERR(host->pdata->rstc))
3227                 reset_control_assert(host->pdata->rstc);
3228
3229 err_clk_ciu:
3230         clk_disable_unprepare(host->ciu_clk);
3231
3232 err_clk_biu:
3233         clk_disable_unprepare(host->biu_clk);
3234
3235         return ret;
3236 }
3237 EXPORT_SYMBOL(dw_mci_probe);
3238
3239 void dw_mci_remove(struct dw_mci *host)
3240 {
3241         int i;
3242
3243         for (i = 0; i < host->num_slots; i++) {
3244                 dev_dbg(host->dev, "remove slot %d\n", i);
3245                 if (host->slot[i])
3246                         dw_mci_cleanup_slot(host->slot[i], i);
3247         }
3248
3249         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3250         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3251
3252         /* disable clock to CIU */
3253         mci_writel(host, CLKENA, 0);
3254         mci_writel(host, CLKSRC, 0);
3255
3256         if (host->use_dma && host->dma_ops->exit)
3257                 host->dma_ops->exit(host);
3258
3259         if (!IS_ERR(host->pdata->rstc))
3260                 reset_control_assert(host->pdata->rstc);
3261
3262         clk_disable_unprepare(host->ciu_clk);
3263         clk_disable_unprepare(host->biu_clk);
3264 }
3265 EXPORT_SYMBOL(dw_mci_remove);
3266
3267
3268
3269 #ifdef CONFIG_PM_SLEEP
3270 /*
3271  * TODO: we should probably disable the clock to the card in the suspend path.
3272  */
3273 int dw_mci_suspend(struct dw_mci *host)
3274 {
3275         if (host->use_dma && host->dma_ops->exit)
3276                 host->dma_ops->exit(host);
3277
3278         return 0;
3279 }
3280 EXPORT_SYMBOL(dw_mci_suspend);
3281
3282 int dw_mci_resume(struct dw_mci *host)
3283 {
3284         int i, ret;
3285
3286         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3287                 ret = -ENODEV;
3288                 return ret;
3289         }
3290
3291         if (host->use_dma && host->dma_ops->init)
3292                 host->dma_ops->init(host);
3293
3294         /*
3295          * Restore the initial value at FIFOTH register
3296          * And Invalidate the prev_blksz with zero
3297          */
3298         mci_writel(host, FIFOTH, host->fifoth_val);
3299         host->prev_blksz = 0;
3300
3301         /* Put in max timeout */
3302         mci_writel(host, TMOUT, 0xFFFFFFFF);
3303
3304         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3305         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3306                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3307                    DW_MCI_ERROR_FLAGS);
3308         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3309
3310         for (i = 0; i < host->num_slots; i++) {
3311                 struct dw_mci_slot *slot = host->slot[i];
3312
3313                 if (!slot)
3314                         continue;
3315                 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3316                         dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3317                         dw_mci_setup_bus(slot, true);
3318                 }
3319         }
3320
3321         /* Now that slots are all setup, we can enable card detect */
3322         dw_mci_enable_cd(host);
3323
3324         return 0;
3325 }
3326 EXPORT_SYMBOL(dw_mci_resume);
3327 #endif /* CONFIG_PM_SLEEP */
3328
3329 static int __init dw_mci_init(void)
3330 {
3331         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3332         return 0;
3333 }
3334
3335 static void __exit dw_mci_exit(void)
3336 {
3337 }
3338
3339 module_init(dw_mci_init);
3340 module_exit(dw_mci_exit);
3341
3342 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3343 MODULE_AUTHOR("NXP Semiconductor VietNam");
3344 MODULE_AUTHOR("Imagination Technologies Ltd");
3345 MODULE_LICENSE("GPL v2");