drivers/mmc/host/sdhci-esdhc-imx.c

   1 /*
   2  * Freescale eSDHC i.MX controller driver for the platform bus.
   3  *
   4  * derived from the OF-version.
   5  *
   6  * Copyright (c) 2010 Pengutronix e.K.
   7  *   Author: Wolfram Sang <w.sang@pengutronix.de>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License.
  12  */
  13
  14 #include <linux/io.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/gpio.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/mmc/mmc.h>
  23 #include <linux/mmc/sdio.h>
  24 #include <linux/mmc/slot-gpio.h>
  25 #include <linux/of.h>
  26 #include <linux/of_device.h>
  27 #include <linux/of_gpio.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/platform_data/mmc-esdhc-imx.h>
  30 #include "sdhci-pltfm.h"
  31 #include "sdhci-esdhc.h"
  32
  33 #define ESDHC_CTRL_D3CD                 0x08
  34 /* VENDOR SPEC register */
  35 #define ESDHC_VENDOR_SPEC               0xc0
  36 #define  ESDHC_VENDOR_SPEC_SDIO_QUIRK   (1 << 1)
  37 #define  ESDHC_VENDOR_SPEC_VSELECT      (1 << 1)
  38 #define  ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
  39 #define ESDHC_WTMK_LVL                  0x44
  40 #define ESDHC_MIX_CTRL                  0x48
  41 #define  ESDHC_MIX_CTRL_DDREN           (1 << 3)
  42 #define  ESDHC_MIX_CTRL_AC23EN          (1 << 7)
  43 #define  ESDHC_MIX_CTRL_EXE_TUNE        (1 << 22)
  44 #define  ESDHC_MIX_CTRL_SMPCLK_SEL      (1 << 23)
  45 #define  ESDHC_MIX_CTRL_FBCLK_SEL       (1 << 25)
  46 /* Bits 3 and 6 are not SDHCI standard definitions */
  47 #define  ESDHC_MIX_CTRL_SDHCI_MASK      0xb7
  48 /* Tuning bits */
  49 #define  ESDHC_MIX_CTRL_TUNING_MASK     0x03c00000
  50
  51 /* dll control register */
  52 #define ESDHC_DLL_CTRL                  0x60
  53 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT    9
  54 #define ESDHC_DLL_OVERRIDE_EN_SHIFT     8
  55
  56 /* tune control register */
  57 #define ESDHC_TUNE_CTRL_STATUS          0x68
  58 #define  ESDHC_TUNE_CTRL_STEP           1
  59 #define  ESDHC_TUNE_CTRL_MIN            0
  60 #define  ESDHC_TUNE_CTRL_MAX            ((1 << 7) - 1)
  61
  62 #define ESDHC_TUNING_CTRL               0xcc
  63 #define ESDHC_STD_TUNING_EN             (1 << 24)
  64 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
  65 #define ESDHC_TUNING_START_TAP          0x1
  66
  67 #define ESDHC_TUNING_BLOCK_PATTERN_LEN  64
  68
  69 /* pinctrl state */
  70 #define ESDHC_PINCTRL_STATE_100MHZ      "state_100mhz"
  71 #define ESDHC_PINCTRL_STATE_200MHZ      "state_200mhz"
  72
  73 /*
  74  * Our interpretation of the SDHCI_HOST_CONTROL register
  75  */
  76 #define ESDHC_CTRL_4BITBUS              (0x1 << 1)
  77 #define ESDHC_CTRL_8BITBUS              (0x2 << 1)
  78 #define ESDHC_CTRL_BUSWIDTH_MASK        (0x3 << 1)
  79
  80 /*
  81  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
  82  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
  83  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
  84  * Define this macro DMA error INT for fsl eSDHC
  85  */
  86 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR   (1 << 28)
  87
  88 /*
  89  * The CMDTYPE of the CMD register (offset 0xE) should be set to
  90  * "11" when the STOP CMD12 is issued on imx53 to abort one
  91  * open ended multi-blk IO. Otherwise the TC INT wouldn't
  92  * be generated.
  93  * In exact block transfer, the controller doesn't complete the
  94  * operations automatically as required at the end of the
  95  * transfer and remains on hold if the abort command is not sent.
  96  * As a result, the TC flag is not asserted and SW  received timeout
  97  * exeception. Bit1 of Vendor Spec registor is used to fix it.
  98  */
  99 #define ESDHC_FLAG_MULTIBLK_NO_INT      BIT(1)
 100 /*
 101  * The flag enables the workaround for ESDHC errata ENGcm07207 which
 102  * affects i.MX25 and i.MX35.
 103  */
 104 #define ESDHC_FLAG_ENGCM07207           BIT(2)
 105 /*
 106  * The flag tells that the ESDHC controller is an USDHC block that is
 107  * integrated on the i.MX6 series.
 108  */
 109 #define ESDHC_FLAG_USDHC                BIT(3)
 110 /* The IP supports manual tuning process */
 111 #define ESDHC_FLAG_MAN_TUNING           BIT(4)
 112 /* The IP supports standard tuning process */
 113 #define ESDHC_FLAG_STD_TUNING           BIT(5)
 114 /* The IP has SDHCI_CAPABILITIES_1 register */
 115 #define ESDHC_FLAG_HAVE_CAP1            BIT(6)
 116
 117 struct esdhc_soc_data {
 118         u32 flags;
 119 };
 120
 121 static struct esdhc_soc_data esdhc_imx25_data = {
 122         .flags = ESDHC_FLAG_ENGCM07207,
 123 };
 124
 125 static struct esdhc_soc_data esdhc_imx35_data = {
 126         .flags = ESDHC_FLAG_ENGCM07207,
 127 };
 128
 129 static struct esdhc_soc_data esdhc_imx51_data = {
 130         .flags = 0,
 131 };
 132
 133 static struct esdhc_soc_data esdhc_imx53_data = {
 134         .flags = ESDHC_FLAG_MULTIBLK_NO_INT,
 135 };
 136
 137 static struct esdhc_soc_data usdhc_imx6q_data = {
 138         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING,
 139 };
 140
 141 static struct esdhc_soc_data usdhc_imx6sl_data = {
 142         .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
 143                         | ESDHC_FLAG_HAVE_CAP1,
 144 };
 145
 146 struct pltfm_imx_data {
 147         u32 scratchpad;
 148         struct pinctrl *pinctrl;
 149         struct pinctrl_state *pins_default;
 150         struct pinctrl_state *pins_100mhz;
 151         struct pinctrl_state *pins_200mhz;
 152         const struct esdhc_soc_data *socdata;
 153         struct esdhc_platform_data boarddata;
 154         struct clk *clk_ipg;
 155         struct clk *clk_ahb;
 156         struct clk *clk_per;
 157         enum {
 158                 NO_CMD_PENDING,      /* no multiblock command pending*/
 159                 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
 160                 WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
 161         } multiblock_status;
 162         u32 uhs_mode;
 163         u32 is_ddr;
 164 };
 165
 166 static struct platform_device_id imx_esdhc_devtype[] = {
 167         {
 168                 .name = "sdhci-esdhc-imx25",
 169                 .driver_data = (kernel_ulong_t) &esdhc_imx25_data,
 170         }, {
 171                 .name = "sdhci-esdhc-imx35",
 172                 .driver_data = (kernel_ulong_t) &esdhc_imx35_data,
 173         }, {
 174                 .name = "sdhci-esdhc-imx51",
 175                 .driver_data = (kernel_ulong_t) &esdhc_imx51_data,
 176         }, {
 177                 /* sentinel */
 178         }
 179 };
 180 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
 181
 182 static const struct of_device_id imx_esdhc_dt_ids[] = {
 183         { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
 184         { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
 185         { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
 186         { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
 187         { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
 188         { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
 189         { /* sentinel */ }
 190 };
 191 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
 192
 193 static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
 194 {
 195         return data->socdata == &esdhc_imx25_data;
 196 }
 197
 198 static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
 199 {
 200         return data->socdata == &esdhc_imx53_data;
 201 }
 202
 203 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
 204 {
 205         return data->socdata == &usdhc_imx6q_data;
 206 }
 207
 208 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data)
 209 {
 210         return !!(data->socdata->flags & ESDHC_FLAG_USDHC);
 211 }
 212
 213 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
 214 {
 215         void __iomem *base = host->ioaddr + (reg & ~0x3);
 216         u32 shift = (reg & 0x3) * 8;
 217
 218         writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
 219 }
 220
 221 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 222 {
 223         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 224         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 225         u32 val = readl(host->ioaddr + reg);
 226
 227         if (unlikely(reg == SDHCI_PRESENT_STATE)) {
 228                 u32 fsl_prss = val;
 229                 /* save the least 20 bits */
 230                 val = fsl_prss & 0x000FFFFF;
 231                 /* move dat[0-3] bits */
 232                 val |= (fsl_prss & 0x0F000000) >> 4;
 233                 /* move cmd line bit */
 234                 val |= (fsl_prss & 0x00800000) << 1;
 235         }
 236
 237         if (unlikely(reg == SDHCI_CAPABILITIES)) {
 238                 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
 239                 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 240                         val &= 0xffff0000;
 241
 242                 /* In FSL esdhc IC module, only bit20 is used to indicate the
 243                  * ADMA2 capability of esdhc, but this bit is messed up on
 244                  * some SOCs (e.g. on MX25, MX35 this bit is set, but they
 245                  * don't actually support ADMA2). So set the BROKEN_ADMA
 246                  * uirk on MX25/35 platforms.
 247                  */
 248
 249                 if (val & SDHCI_CAN_DO_ADMA1) {
 250                         val &= ~SDHCI_CAN_DO_ADMA1;
 251                         val |= SDHCI_CAN_DO_ADMA2;
 252                 }
 253         }
 254
 255         if (unlikely(reg == SDHCI_CAPABILITIES_1)) {
 256                 if (esdhc_is_usdhc(imx_data)) {
 257                         if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1)
 258                                 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF;
 259                         else
 260                                 /* imx6q/dl does not have cap_1 register, fake one */
 261                                 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
 262                                         | SDHCI_SUPPORT_SDR50
 263                                         | SDHCI_USE_SDR50_TUNING;
 264                 }
 265         }
 266
 267         if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) {
 268                 val = 0;
 269                 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT;
 270                 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT;
 271                 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT;
 272         }
 273
 274         if (unlikely(reg == SDHCI_INT_STATUS)) {
 275                 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) {
 276                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 277                         val |= SDHCI_INT_ADMA_ERROR;
 278                 }
 279
 280                 /*
 281                  * mask off the interrupt we get in response to the manually
 282                  * sent CMD12
 283                  */
 284                 if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
 285                     ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
 286                         val &= ~SDHCI_INT_RESPONSE;
 287                         writel(SDHCI_INT_RESPONSE, host->ioaddr +
 288                                                    SDHCI_INT_STATUS);
 289                         imx_data->multiblock_status = NO_CMD_PENDING;
 290                 }
 291         }
 292
 293         return val;
 294 }
 295
 296 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
 297 {
 298         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 299         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 300         u32 data;
 301
 302         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 303                 if (val & SDHCI_INT_CARD_INT) {
 304                         /*
 305                          * Clear and then set D3CD bit to avoid missing the
 306                          * card interrupt.  This is a eSDHC controller problem
 307                          * so we need to apply the following workaround: clear
 308                          * and set D3CD bit will make eSDHC re-sample the card
 309                          * interrupt. In case a card interrupt was lost,
 310                          * re-sample it by the following steps.
 311                          */
 312                         data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
 313                         data &= ~ESDHC_CTRL_D3CD;
 314                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 315                         data |= ESDHC_CTRL_D3CD;
 316                         writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
 317                 }
 318         }
 319
 320         if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 321                                 && (reg == SDHCI_INT_STATUS)
 322                                 && (val & SDHCI_INT_DATA_END))) {
 323                         u32 v;
 324                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 325                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 326                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 327
 328                         if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
 329                         {
 330                                 /* send a manual CMD12 with RESPTYP=none */
 331                                 data = MMC_STOP_TRANSMISSION << 24 |
 332                                        SDHCI_CMD_ABORTCMD << 16;
 333                                 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
 334                                 imx_data->multiblock_status = WAIT_FOR_INT;
 335                         }
 336         }
 337
 338         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
 339                 if (val & SDHCI_INT_ADMA_ERROR) {
 340                         val &= ~SDHCI_INT_ADMA_ERROR;
 341                         val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR;
 342                 }
 343         }
 344
 345         writel(val, host->ioaddr + reg);
 346 }
 347
 348 static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
 349 {
 350         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 351         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 352         u16 ret = 0;
 353         u32 val;
 354
 355         if (unlikely(reg == SDHCI_HOST_VERSION)) {
 356                 reg ^= 2;
 357                 if (esdhc_is_usdhc(imx_data)) {
 358                         /*
 359                          * The usdhc register returns a wrong host version.
 360                          * Correct it here.
 361                          */
 362                         return SDHCI_SPEC_300;
 363                 }
 364         }
 365
 366         if (unlikely(reg == SDHCI_HOST_CONTROL2)) {
 367                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 368                 if (val & ESDHC_VENDOR_SPEC_VSELECT)
 369                         ret |= SDHCI_CTRL_VDD_180;
 370
 371                 if (esdhc_is_usdhc(imx_data)) {
 372                         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
 373                                 val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 374                         else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
 375                                 /* the std tuning bits is in ACMD12_ERR for imx6sl */
 376                                 val = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 377                 }
 378
 379                 if (val & ESDHC_MIX_CTRL_EXE_TUNE)
 380                         ret |= SDHCI_CTRL_EXEC_TUNING;
 381                 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL)
 382                         ret |= SDHCI_CTRL_TUNED_CLK;
 383
 384                 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK);
 385                 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
 386
 387                 return ret;
 388         }
 389
 390         if (unlikely(reg == SDHCI_TRANSFER_MODE)) {
 391                 if (esdhc_is_usdhc(imx_data)) {
 392                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 393                         ret = m & ESDHC_MIX_CTRL_SDHCI_MASK;
 394                         /* Swap AC23 bit */
 395                         if (m & ESDHC_MIX_CTRL_AC23EN) {
 396                                 ret &= ~ESDHC_MIX_CTRL_AC23EN;
 397                                 ret |= SDHCI_TRNS_AUTO_CMD23;
 398                         }
 399                 } else {
 400                         ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE);
 401                 }
 402
 403                 return ret;
 404         }
 405
 406         return readw(host->ioaddr + reg);
 407 }
 408
 409 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
 410 {
 411         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 412         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 413         u32 new_val = 0;
 414
 415         switch (reg) {
 416         case SDHCI_CLOCK_CONTROL:
 417                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 418                 if (val & SDHCI_CLOCK_CARD_EN)
 419                         new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 420                 else
 421                         new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON;
 422                         writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 423                 return;
 424         case SDHCI_HOST_CONTROL2:
 425                 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 426                 if (val & SDHCI_CTRL_VDD_180)
 427                         new_val |= ESDHC_VENDOR_SPEC_VSELECT;
 428                 else
 429                         new_val &= ~ESDHC_VENDOR_SPEC_VSELECT;
 430                 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC);
 431                 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK;
 432                 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) {
 433                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 434                         if (val & SDHCI_CTRL_TUNED_CLK)
 435                                 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 436                         else
 437                                 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 438                         writel(new_val , host->ioaddr + ESDHC_MIX_CTRL);
 439                 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) {
 440                         u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR);
 441                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 442                         if (val & SDHCI_CTRL_TUNED_CLK) {
 443                                 v |= ESDHC_MIX_CTRL_SMPCLK_SEL;
 444                         } else {
 445                                 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL;
 446                                 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL;
 447                         }
 448
 449                         if (val & SDHCI_CTRL_EXEC_TUNING) {
 450                                 v |= ESDHC_MIX_CTRL_EXE_TUNE;
 451                                 m |= ESDHC_MIX_CTRL_FBCLK_SEL;
 452                         } else {
 453                                 v &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 454                         }
 455
 456                         writel(v, host->ioaddr + SDHCI_ACMD12_ERR);
 457                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 458                 }
 459                 return;
 460         case SDHCI_TRANSFER_MODE:
 461                 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
 462                                 && (host->cmd->opcode == SD_IO_RW_EXTENDED)
 463                                 && (host->cmd->data->blocks > 1)
 464                                 && (host->cmd->data->flags & MMC_DATA_READ)) {
 465                         u32 v;
 466                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 467                         v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK;
 468                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
 469                 }
 470
 471                 if (esdhc_is_usdhc(imx_data)) {
 472                         u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL);
 473                         /* Swap AC23 bit */
 474                         if (val & SDHCI_TRNS_AUTO_CMD23) {
 475                                 val &= ~SDHCI_TRNS_AUTO_CMD23;
 476                                 val |= ESDHC_MIX_CTRL_AC23EN;
 477                         }
 478                         m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK);
 479                         writel(m, host->ioaddr + ESDHC_MIX_CTRL);
 480                 } else {
 481                         /*
 482                          * Postpone this write, we must do it together with a
 483                          * command write that is down below.
 484                          */
 485                         imx_data->scratchpad = val;
 486                 }
 487                 return;
 488         case SDHCI_COMMAND:
 489                 if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
 490                         val |= SDHCI_CMD_ABORTCMD;
 491
 492                 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
 493                     (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
 494                         imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
 495
 496                 if (esdhc_is_usdhc(imx_data))
 497                         writel(val << 16,
 498                                host->ioaddr + SDHCI_TRANSFER_MODE);
 499                 else
 500                         writel(val << 16 | imx_data->scratchpad,
 501                                host->ioaddr + SDHCI_TRANSFER_MODE);
 502                 return;
 503         case SDHCI_BLOCK_SIZE:
 504                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 505                 break;
 506         }
 507         esdhc_clrset_le(host, 0xffff, val, reg);
 508 }
 509
 510 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
 511 {
 512         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 513         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 514         u32 new_val;
 515         u32 mask;
 516
 517         switch (reg) {
 518         case SDHCI_POWER_CONTROL:
 519                 /*
 520                  * FSL put some DMA bits here
 521                  * If your board has a regulator, code should be here
 522                  */
 523                 return;
 524         case SDHCI_HOST_CONTROL:
 525                 /* FSL messed up here, so we need to manually compose it. */
 526                 new_val = val & SDHCI_CTRL_LED;
 527                 /* ensure the endianness */
 528                 new_val |= ESDHC_HOST_CONTROL_LE;
 529                 /* bits 8&9 are reserved on mx25 */
 530                 if (!is_imx25_esdhc(imx_data)) {
 531                         /* DMA mode bits are shifted */
 532                         new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
 533                 }
 534
 535                 /*
 536                  * Do not touch buswidth bits here. This is done in
 537                  * esdhc_pltfm_bus_width.
 538                  * Do not touch the D3CD bit either which is used for the
 539                  * SDIO interrupt errata workaround.
 540                  */
 541                 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 542
 543                 esdhc_clrset_le(host, mask, new_val, reg);
 544                 return;
 545         }
 546         esdhc_clrset_le(host, 0xff, val, reg);
 547
 548         /*
 549          * The esdhc has a design violation to SDHC spec which tells
 550          * that software reset should not affect card detection circuit.
 551          * But esdhc clears its SYSCTL register bits [0..2] during the
 552          * software reset.  This will stop those clocks that card detection
 553          * circuit relies on.  To work around it, we turn the clocks on back
 554          * to keep card detection circuit functional.
 555          */
 556         if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) {
 557                 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
 558                 /*
 559                  * The reset on usdhc fails to clear MIX_CTRL register.
 560                  * Do it manually here.
 561                  */
 562                 if (esdhc_is_usdhc(imx_data)) {
 563                         /* the tuning bits should be kept during reset */
 564                         new_val = readl(host->ioaddr + ESDHC_MIX_CTRL);
 565                         writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK,
 566                                         host->ioaddr + ESDHC_MIX_CTRL);
 567                         imx_data->is_ddr = 0;
 568                 }
 569         }
 570 }
 571
 572 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
 573 {
 574         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 575         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 576         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 577
 578         u32 f_host = clk_get_rate(pltfm_host->clk);
 579
 580         if (boarddata->f_max && (boarddata->f_max < f_host))
 581                 return boarddata->f_max;
 582         else
 583                 return f_host;
 584 }
 585
 586 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
 587 {
 588         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 589
 590         return clk_get_rate(pltfm_host->clk) / 256 / 16;
 591 }
 592
 593 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host,
 594                                          unsigned int clock)
 595 {
 596         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 597         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 598         unsigned int host_clock = clk_get_rate(pltfm_host->clk);
 599         int pre_div = 2;
 600         int div = 1;
 601         u32 temp, val;
 602
 603         if (clock == 0) {
 604                 if (esdhc_is_usdhc(imx_data)) {
 605                         val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 606                         writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 607                                         host->ioaddr + ESDHC_VENDOR_SPEC);
 608                 }
 609                 goto out;
 610         }
 611
 612         if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr)
 613                 pre_div = 1;
 614
 615         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 616         temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 617                 | ESDHC_CLOCK_MASK);
 618         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 619
 620         while (host_clock / pre_div / 16 > clock && pre_div < 256)
 621                 pre_div *= 2;
 622
 623         while (host_clock / pre_div / div > clock && div < 16)
 624                 div++;
 625
 626         host->mmc->actual_clock = host_clock / pre_div / div;
 627         dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
 628                 clock, host->mmc->actual_clock);
 629
 630         if (imx_data->is_ddr)
 631                 pre_div >>= 2;
 632         else
 633                 pre_div >>= 1;
 634         div--;
 635
 636         temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL);
 637         temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN
 638                 | (div << ESDHC_DIVIDER_SHIFT)
 639                 | (pre_div << ESDHC_PREDIV_SHIFT));
 640         sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL);
 641
 642         if (esdhc_is_usdhc(imx_data)) {
 643                 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
 644                 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON,
 645                 host->ioaddr + ESDHC_VENDOR_SPEC);
 646         }
 647
 648         mdelay(1);
 649 out:
 650         host->clock = clock;
 651 }
 652
 653 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
 654 {
 655         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 656         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 657         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 658
 659         switch (boarddata->wp_type) {
 660         case ESDHC_WP_GPIO:
 661                 return mmc_gpio_get_ro(host->mmc);
 662         case ESDHC_WP_CONTROLLER:
 663                 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
 664                                SDHCI_WRITE_PROTECT);
 665         case ESDHC_WP_NONE:
 666                 break;
 667         }
 668
 669         return -ENOSYS;
 670 }
 671
 672 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
 673 {
 674         u32 ctrl;
 675
 676         switch (width) {
 677         case MMC_BUS_WIDTH_8:
 678                 ctrl = ESDHC_CTRL_8BITBUS;
 679                 break;
 680         case MMC_BUS_WIDTH_4:
 681                 ctrl = ESDHC_CTRL_4BITBUS;
 682                 break;
 683         default:
 684                 ctrl = 0;
 685                 break;
 686         }
 687
 688         esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl,
 689                         SDHCI_HOST_CONTROL);
 690
 691         return 0;
 692 }
 693
 694 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val)
 695 {
 696         u32 reg;
 697
 698         /* FIXME: delay a bit for card to be ready for next tuning due to errors */
 699         mdelay(1);
 700
 701         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 702         reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL |
 703                         ESDHC_MIX_CTRL_FBCLK_SEL;
 704         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 705         writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS);
 706         dev_dbg(mmc_dev(host->mmc),
 707                 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
 708                         val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS));
 709 }
 710
 711 static void esdhc_request_done(struct mmc_request *mrq)
 712 {
 713         complete(&mrq->completion);
 714 }
 715
 716 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode)
 717 {
 718         struct mmc_command cmd = {0};
 719         struct mmc_request mrq = {0};
 720         struct mmc_data data = {0};
 721         struct scatterlist sg;
 722         char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN];
 723
 724         cmd.opcode = opcode;
 725         cmd.arg = 0;
 726         cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
 727
 728         data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN;
 729         data.blocks = 1;
 730         data.flags = MMC_DATA_READ;
 731         data.sg = &sg;
 732         data.sg_len = 1;
 733
 734         sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern));
 735
 736         mrq.cmd = &cmd;
 737         mrq.cmd->mrq = &mrq;
 738         mrq.data = &data;
 739         mrq.data->mrq = &mrq;
 740         mrq.cmd->data = mrq.data;
 741
 742         mrq.done = esdhc_request_done;
 743         init_completion(&(mrq.completion));
 744
 745         disable_irq(host->irq);
 746         spin_lock(&host->lock);
 747         host->mrq = &mrq;
 748
 749         sdhci_send_command(host, mrq.cmd);
 750
 751         spin_unlock(&host->lock);
 752         enable_irq(host->irq);
 753
 754         wait_for_completion(&mrq.completion);
 755
 756         if (cmd.error)
 757                 return cmd.error;
 758         if (data.error)
 759                 return data.error;
 760
 761         return 0;
 762 }
 763
 764 static void esdhc_post_tuning(struct sdhci_host *host)
 765 {
 766         u32 reg;
 767
 768         reg = readl(host->ioaddr + ESDHC_MIX_CTRL);
 769         reg &= ~ESDHC_MIX_CTRL_EXE_TUNE;
 770         writel(reg, host->ioaddr + ESDHC_MIX_CTRL);
 771 }
 772
 773 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode)
 774 {
 775         int min, max, avg, ret;
 776
 777         /* find the mininum delay first which can pass tuning */
 778         min = ESDHC_TUNE_CTRL_MIN;
 779         while (min < ESDHC_TUNE_CTRL_MAX) {
 780                 esdhc_prepare_tuning(host, min);
 781                 if (!esdhc_send_tuning_cmd(host, opcode))
 782                         break;
 783                 min += ESDHC_TUNE_CTRL_STEP;
 784         }
 785
 786         /* find the maxinum delay which can not pass tuning */
 787         max = min + ESDHC_TUNE_CTRL_STEP;
 788         while (max < ESDHC_TUNE_CTRL_MAX) {
 789                 esdhc_prepare_tuning(host, max);
 790                 if (esdhc_send_tuning_cmd(host, opcode)) {
 791                         max -= ESDHC_TUNE_CTRL_STEP;
 792                         break;
 793                 }
 794                 max += ESDHC_TUNE_CTRL_STEP;
 795         }
 796
 797         /* use average delay to get the best timing */
 798         avg = (min + max) / 2;
 799         esdhc_prepare_tuning(host, avg);
 800         ret = esdhc_send_tuning_cmd(host, opcode);
 801         esdhc_post_tuning(host);
 802
 803         dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n",
 804                 ret ? "failed" : "passed", avg, ret);
 805
 806         return ret;
 807 }
 808
 809 static int esdhc_change_pinstate(struct sdhci_host *host,
 810                                                 unsigned int uhs)
 811 {
 812         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 813         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 814         struct pinctrl_state *pinctrl;
 815
 816         dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs);
 817
 818         if (IS_ERR(imx_data->pinctrl) ||
 819                 IS_ERR(imx_data->pins_default) ||
 820                 IS_ERR(imx_data->pins_100mhz) ||
 821                 IS_ERR(imx_data->pins_200mhz))
 822                 return -EINVAL;
 823
 824         switch (uhs) {
 825         case MMC_TIMING_UHS_SDR50:
 826                 pinctrl = imx_data->pins_100mhz;
 827                 break;
 828         case MMC_TIMING_UHS_SDR104:
 829         case MMC_TIMING_MMC_HS200:
 830                 pinctrl = imx_data->pins_200mhz;
 831                 break;
 832         default:
 833                 /* back to default state for other legacy timing */
 834                 pinctrl = imx_data->pins_default;
 835         }
 836
 837         return pinctrl_select_state(imx_data->pinctrl, pinctrl);
 838 }
 839
 840 static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
 841 {
 842         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 843         struct pltfm_imx_data *imx_data = pltfm_host->priv;
 844         struct esdhc_platform_data *boarddata = &imx_data->boarddata;
 845
 846         switch (uhs) {
 847         case MMC_TIMING_UHS_SDR12:
 848                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12;
 849                 break;
 850         case MMC_TIMING_UHS_SDR25:
 851                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25;
 852                 break;
 853         case MMC_TIMING_UHS_SDR50:
 854                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50;
 855                 break;
 856         case MMC_TIMING_UHS_SDR104:
 857         case MMC_TIMING_MMC_HS200:
 858                 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104;
 859                 break;
 860         case MMC_TIMING_UHS_DDR50:
 861                 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50;
 862                 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
 863                                 ESDHC_MIX_CTRL_DDREN,
 864                                 host->ioaddr + ESDHC_MIX_CTRL);
 865                 imx_data->is_ddr = 1;
 866                 if (boarddata->delay_line) {
 867                         u32 v;
 868                         v = boarddata->delay_line <<
 869                                 ESDHC_DLL_OVERRIDE_VAL_SHIFT |
 870                                 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT);
 871                         if (is_imx53_esdhc(imx_data))
 872                                 v <<= 1;
 873                         writel(v, host->ioaddr + ESDHC_DLL_CTRL);
 874                 }
 875                 break;
 876         }
 877
 878         return esdhc_change_pinstate(host, uhs);
 879 }
 880
 881 static struct sdhci_ops sdhci_esdhc_ops = {
 882         .read_l = esdhc_readl_le,
 883         .read_w = esdhc_readw_le,
 884         .write_l = esdhc_writel_le,
 885         .write_w = esdhc_writew_le,
 886         .write_b = esdhc_writeb_le,
 887         .set_clock = esdhc_pltfm_set_clock,
 888         .get_max_clock = esdhc_pltfm_get_max_clock,
 889         .get_min_clock = esdhc_pltfm_get_min_clock,
 890         .get_ro = esdhc_pltfm_get_ro,
 891         .platform_bus_width = esdhc_pltfm_bus_width,
 892         .set_uhs_signaling = esdhc_set_uhs_signaling,
 893 };
 894
 895 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
 896         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
 897                         | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
 898                         | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
 899                         | SDHCI_QUIRK_BROKEN_CARD_DETECTION,
 900         .ops = &sdhci_esdhc_ops,
 901 };
 902
 903 #ifdef CONFIG_OF
 904 static int
 905 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 906                          struct esdhc_platform_data *boarddata)
 907 {
 908         struct device_node *np = pdev->dev.of_node;
 909
 910         if (!np)
 911                 return -ENODEV;
 912
 913         if (of_get_property(np, "non-removable", NULL))
 914                 boarddata->cd_type = ESDHC_CD_PERMANENT;
 915
 916         if (of_get_property(np, "fsl,cd-controller", NULL))
 917                 boarddata->cd_type = ESDHC_CD_CONTROLLER;
 918
 919         if (of_get_property(np, "fsl,wp-controller", NULL))
 920                 boarddata->wp_type = ESDHC_WP_CONTROLLER;
 921
 922         boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
 923         if (gpio_is_valid(boarddata->cd_gpio))
 924                 boarddata->cd_type = ESDHC_CD_GPIO;
 925
 926         boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
 927         if (gpio_is_valid(boarddata->wp_gpio))
 928                 boarddata->wp_type = ESDHC_WP_GPIO;
 929
 930         of_property_read_u32(np, "bus-width", &boarddata->max_bus_width);
 931
 932         of_property_read_u32(np, "max-frequency", &boarddata->f_max);
 933
 934         if (of_find_property(np, "no-1-8-v", NULL))
 935                 boarddata->support_vsel = false;
 936         else
 937                 boarddata->support_vsel = true;
 938
 939         if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line))
 940                 boarddata->delay_line = 0;
 941
 942         return 0;
 943 }
 944 #else
 945 static inline int
 946 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
 947                          struct esdhc_platform_data *boarddata)
 948 {
 949         return -ENODEV;
 950 }
 951 #endif
 952
 953 static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
 954 {
 955         const struct of_device_id *of_id =
 956                         of_match_device(imx_esdhc_dt_ids, &pdev->dev);
 957         struct sdhci_pltfm_host *pltfm_host;
 958         struct sdhci_host *host;
 959         struct esdhc_platform_data *boarddata;
 960         int err;
 961         struct pltfm_imx_data *imx_data;
 962
 963         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0);
 964         if (IS_ERR(host))
 965                 return PTR_ERR(host);
 966
 967         pltfm_host = sdhci_priv(host);
 968
 969         imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL);
 970         if (!imx_data) {
 971                 err = -ENOMEM;
 972                 goto free_sdhci;
 973         }
 974
 975         imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *)
 976                                                   pdev->id_entry->driver_data;
 977         pltfm_host->priv = imx_data;
 978
 979         imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
 980         if (IS_ERR(imx_data->clk_ipg)) {
 981                 err = PTR_ERR(imx_data->clk_ipg);
 982                 goto free_sdhci;
 983         }
 984
 985         imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
 986         if (IS_ERR(imx_data->clk_ahb)) {
 987                 err = PTR_ERR(imx_data->clk_ahb);
 988                 goto free_sdhci;
 989         }
 990
 991         imx_data->clk_per = devm_clk_get(&pdev->dev, "per");
 992         if (IS_ERR(imx_data->clk_per)) {
 993                 err = PTR_ERR(imx_data->clk_per);
 994                 goto free_sdhci;
 995         }
 996
 997         pltfm_host->clk = imx_data->clk_per;
 998
 999         clk_prepare_enable(imx_data->clk_per);
1000         clk_prepare_enable(imx_data->clk_ipg);
1001         clk_prepare_enable(imx_data->clk_ahb);
1002
1003         imx_data->pinctrl = devm_pinctrl_get(&pdev->dev);
1004         if (IS_ERR(imx_data->pinctrl)) {
1005                 err = PTR_ERR(imx_data->pinctrl);
1006                 goto disable_clk;
1007         }
1008
1009         imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl,
1010                                                 PINCTRL_STATE_DEFAULT);
1011         if (IS_ERR(imx_data->pins_default)) {
1012                 err = PTR_ERR(imx_data->pins_default);
1013                 dev_err(mmc_dev(host->mmc), "could not get default state\n");
1014                 goto disable_clk;
1015         }
1016
1017         host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
1018
1019         if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207)
1020                 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
1021                 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
1022                         | SDHCI_QUIRK_BROKEN_ADMA;
1023
1024         /*
1025          * The imx6q ROM code will change the default watermark level setting
1026          * to something insane.  Change it back here.
1027          */
1028         if (esdhc_is_usdhc(imx_data)) {
1029                 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL);
1030                 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
1031                 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1032         }
1033
1034         if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING)
1035                 sdhci_esdhc_ops.platform_execute_tuning =
1036                                         esdhc_executing_tuning;
1037
1038         if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING)
1039                 writel(readl(host->ioaddr + ESDHC_TUNING_CTRL) |
1040                         ESDHC_STD_TUNING_EN | ESDHC_TUNING_START_TAP,
1041                         host->ioaddr + ESDHC_TUNING_CTRL);
1042
1043         boarddata = &imx_data->boarddata;
1044         if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
1045                 if (!host->mmc->parent->platform_data) {
1046                         dev_err(mmc_dev(host->mmc), "no board data!\n");
1047                         err = -EINVAL;
1048                         goto disable_clk;
1049                 }
1050                 imx_data->boarddata = *((struct esdhc_platform_data *)
1051                                         host->mmc->parent->platform_data);
1052         }
1053
1054         /* write_protect */
1055         if (boarddata->wp_type == ESDHC_WP_GPIO) {
1056                 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio);
1057                 if (err) {
1058                         dev_err(mmc_dev(host->mmc),
1059                                 "failed to request write-protect gpio!\n");
1060                         goto disable_clk;
1061                 }
1062                 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1063         }
1064
1065         /* card_detect */
1066         switch (boarddata->cd_type) {
1067         case ESDHC_CD_GPIO:
1068                 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0);
1069                 if (err) {
1070                         dev_err(mmc_dev(host->mmc),
1071                                 "failed to request card-detect gpio!\n");
1072                         goto disable_clk;
1073                 }
1074                 /* fall through */
1075
1076         case ESDHC_CD_CONTROLLER:
1077                 /* we have a working card_detect back */
1078                 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
1079                 break;
1080
1081         case ESDHC_CD_PERMANENT:
1082                 host->mmc->caps |= MMC_CAP_NONREMOVABLE;
1083                 break;
1084
1085         case ESDHC_CD_NONE:
1086                 break;
1087         }
1088
1089         switch (boarddata->max_bus_width) {
1090         case 8:
1091                 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA;
1092                 break;
1093         case 4:
1094                 host->mmc->caps |= MMC_CAP_4_BIT_DATA;
1095                 break;
1096         case 1:
1097         default:
1098                 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA;
1099                 break;
1100         }
1101
1102         /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1103         if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) {
1104                 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl,
1105                                                 ESDHC_PINCTRL_STATE_100MHZ);
1106                 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl,
1107                                                 ESDHC_PINCTRL_STATE_200MHZ);
1108                 if (IS_ERR(imx_data->pins_100mhz) ||
1109                                 IS_ERR(imx_data->pins_200mhz)) {
1110                         dev_warn(mmc_dev(host->mmc),
1111                                 "could not get ultra high speed state, work on normal mode\n");
1112                         /* fall back to not support uhs by specify no 1.8v quirk */
1113                         host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1114                 }
1115         } else {
1116                 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1117         }
1118
1119         err = sdhci_add_host(host);
1120         if (err)
1121                 goto disable_clk;
1122
1123         return 0;
1124
1125 disable_clk:
1126         clk_disable_unprepare(imx_data->clk_per);
1127         clk_disable_unprepare(imx_data->clk_ipg);
1128         clk_disable_unprepare(imx_data->clk_ahb);
1129 free_sdhci:
1130         sdhci_pltfm_free(pdev);
1131         return err;
1132 }
1133
1134 static int sdhci_esdhc_imx_remove(struct platform_device *pdev)
1135 {
1136         struct sdhci_host *host = platform_get_drvdata(pdev);
1137         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
1138         struct pltfm_imx_data *imx_data = pltfm_host->priv;
1139         int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
1140
1141         sdhci_remove_host(host, dead);
1142
1143         clk_disable_unprepare(imx_data->clk_per);
1144         clk_disable_unprepare(imx_data->clk_ipg);
1145         clk_disable_unprepare(imx_data->clk_ahb);
1146
1147         sdhci_pltfm_free(pdev);
1148
1149         return 0;
1150 }
1151
1152 static struct platform_driver sdhci_esdhc_imx_driver = {
1153         .driver         = {
1154                 .name   = "sdhci-esdhc-imx",
1155                 .owner  = THIS_MODULE,
1156                 .of_match_table = imx_esdhc_dt_ids,
1157                 .pm     = SDHCI_PLTFM_PMOPS,
1158         },
1159         .id_table       = imx_esdhc_devtype,
1160         .probe          = sdhci_esdhc_imx_probe,
1161         .remove         = sdhci_esdhc_imx_remove,
1162 };
1163
1164 module_platform_driver(sdhci_esdhc_imx_driver);
1165
1166 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1167 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
1168 MODULE_LICENSE("GPL v2");