drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31
  32 #include "sdhci.h"
  33
  34 #define DRIVER_NAME "sdhci"
  35
  36 #define DBG(f, x...) \
  37         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  38
  39 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  40         defined(CONFIG_MMC_SDHCI_MODULE))
  41 #define SDHCI_USE_LEDS_CLASS
  42 #endif
  43
  44 #define MAX_TUNING_LOOP 40
  45
  46 static unsigned int debug_quirks = 0;
  47 static unsigned int debug_quirks2;
  48
  49 static void sdhci_finish_data(struct sdhci_host *);
  50
  51 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  52 static void sdhci_finish_command(struct sdhci_host *);
  53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  54 static void sdhci_tuning_timer(unsigned long data);
  55
  56 #ifdef CONFIG_PM_RUNTIME
  57 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  58 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  59 #else
  60 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  61 {
  62         return 0;
  63 }
  64 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  65 {
  66         return 0;
  67 }
  68 #endif
  69
  70 static void sdhci_dumpregs(struct sdhci_host *host)
  71 {
  72         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  73                 mmc_hostname(host->mmc));
  74
  75         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  76                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  77                 sdhci_readw(host, SDHCI_HOST_VERSION));
  78         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  79                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  80                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  81         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  82                 sdhci_readl(host, SDHCI_ARGUMENT),
  83                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  84         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  85                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  86                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  87         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  88                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  89                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
  90         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
  91                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
  92                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
  93         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
  94                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
  95                 sdhci_readl(host, SDHCI_INT_STATUS));
  96         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_INT_ENABLE),
  98                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
  99         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 100                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 101                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 102         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 103                 sdhci_readl(host, SDHCI_CAPABILITIES),
 104                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 105         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 106                 sdhci_readw(host, SDHCI_COMMAND),
 107                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 108         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 109                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 110
 111         if (host->flags & SDHCI_USE_ADMA)
 112                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 113                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 114                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 115
 116         pr_debug(DRIVER_NAME ": ===========================================\n");
 117 }
 118
 119 /*****************************************************************************\
 120  *                                                                           *
 121  * Low level functions                                                       *
 122  *                                                                           *
 123 \*****************************************************************************/
 124
 125 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 126 {
 127         u32 ier;
 128
 129         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 130         ier &= ~clear;
 131         ier |= set;
 132         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 133         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 134 }
 135
 136 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 137 {
 138         sdhci_clear_set_irqs(host, 0, irqs);
 139 }
 140
 141 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 142 {
 143         sdhci_clear_set_irqs(host, irqs, 0);
 144 }
 145
 146 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 147 {
 148         u32 present, irqs;
 149
 150         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 151             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 152                 return;
 153
 154         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 155                               SDHCI_CARD_PRESENT;
 156         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 157
 158         if (enable)
 159                 sdhci_unmask_irqs(host, irqs);
 160         else
 161                 sdhci_mask_irqs(host, irqs);
 162 }
 163
 164 static void sdhci_enable_card_detection(struct sdhci_host *host)
 165 {
 166         sdhci_set_card_detection(host, true);
 167 }
 168
 169 static void sdhci_disable_card_detection(struct sdhci_host *host)
 170 {
 171         sdhci_set_card_detection(host, false);
 172 }
 173
 174 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 175 {
 176         unsigned long timeout;
 177         u32 uninitialized_var(ier);
 178
 179         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 180                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 181                         SDHCI_CARD_PRESENT))
 182                         return;
 183         }
 184
 185         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 186                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 187
 188         if (host->ops->platform_reset_enter)
 189                 host->ops->platform_reset_enter(host, mask);
 190
 191         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 192
 193         if (mask & SDHCI_RESET_ALL)
 194                 host->clock = 0;
 195
 196         /* Wait max 100 ms */
 197         timeout = 100;
 198
 199         /* hw clears the bit when it's done */
 200         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 201                 if (timeout == 0) {
 202                         pr_err("%s: Reset 0x%x never completed.\n",
 203                                 mmc_hostname(host->mmc), (int)mask);
 204                         sdhci_dumpregs(host);
 205                         return;
 206                 }
 207                 timeout--;
 208                 mdelay(1);
 209         }
 210
 211         if (host->ops->platform_reset_exit)
 212                 host->ops->platform_reset_exit(host, mask);
 213
 214         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 215                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 216
 217         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 218                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 219                         host->ops->enable_dma(host);
 220         }
 221 }
 222
 223 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 224
 225 static void sdhci_init(struct sdhci_host *host, int soft)
 226 {
 227         if (soft)
 228                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 229         else
 230                 sdhci_reset(host, SDHCI_RESET_ALL);
 231
 232         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 233                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 234                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 235                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 236                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 237
 238         if (soft) {
 239                 /* force clock reconfiguration */
 240                 host->clock = 0;
 241                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 242         }
 243 }
 244
 245 static void sdhci_reinit(struct sdhci_host *host)
 246 {
 247         sdhci_init(host, 0);
 248         sdhci_enable_card_detection(host);
 249 }
 250
 251 static void sdhci_activate_led(struct sdhci_host *host)
 252 {
 253         u8 ctrl;
 254
 255         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 256         ctrl |= SDHCI_CTRL_LED;
 257         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 258 }
 259
 260 static void sdhci_deactivate_led(struct sdhci_host *host)
 261 {
 262         u8 ctrl;
 263
 264         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 265         ctrl &= ~SDHCI_CTRL_LED;
 266         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 267 }
 268
 269 #ifdef SDHCI_USE_LEDS_CLASS
 270 static void sdhci_led_control(struct led_classdev *led,
 271         enum led_brightness brightness)
 272 {
 273         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 274         unsigned long flags;
 275
 276         spin_lock_irqsave(&host->lock, flags);
 277
 278         if (host->runtime_suspended)
 279                 goto out;
 280
 281         if (brightness == LED_OFF)
 282                 sdhci_deactivate_led(host);
 283         else
 284                 sdhci_activate_led(host);
 285 out:
 286         spin_unlock_irqrestore(&host->lock, flags);
 287 }
 288 #endif
 289
 290 /*****************************************************************************\
 291  *                                                                           *
 292  * Core functions                                                            *
 293  *                                                                           *
 294 \*****************************************************************************/
 295
 296 static void sdhci_read_block_pio(struct sdhci_host *host)
 297 {
 298         unsigned long flags;
 299         size_t blksize, len, chunk;
 300         u32 uninitialized_var(scratch);
 301         u8 *buf;
 302
 303         DBG("PIO reading\n");
 304
 305         blksize = host->data->blksz;
 306         chunk = 0;
 307
 308         local_irq_save(flags);
 309
 310         while (blksize) {
 311                 if (!sg_miter_next(&host->sg_miter))
 312                         BUG();
 313
 314                 len = min(host->sg_miter.length, blksize);
 315
 316                 blksize -= len;
 317                 host->sg_miter.consumed = len;
 318
 319                 buf = host->sg_miter.addr;
 320
 321                 while (len) {
 322                         if (chunk == 0) {
 323                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 324                                 chunk = 4;
 325                         }
 326
 327                         *buf = scratch & 0xFF;
 328
 329                         buf++;
 330                         scratch >>= 8;
 331                         chunk--;
 332                         len--;
 333                 }
 334         }
 335
 336         sg_miter_stop(&host->sg_miter);
 337
 338         local_irq_restore(flags);
 339 }
 340
 341 static void sdhci_write_block_pio(struct sdhci_host *host)
 342 {
 343         unsigned long flags;
 344         size_t blksize, len, chunk;
 345         u32 scratch;
 346         u8 *buf;
 347
 348         DBG("PIO writing\n");
 349
 350         blksize = host->data->blksz;
 351         chunk = 0;
 352         scratch = 0;
 353
 354         local_irq_save(flags);
 355
 356         while (blksize) {
 357                 if (!sg_miter_next(&host->sg_miter))
 358                         BUG();
 359
 360                 len = min(host->sg_miter.length, blksize);
 361
 362                 blksize -= len;
 363                 host->sg_miter.consumed = len;
 364
 365                 buf = host->sg_miter.addr;
 366
 367                 while (len) {
 368                         scratch |= (u32)*buf << (chunk * 8);
 369
 370                         buf++;
 371                         chunk++;
 372                         len--;
 373
 374                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 375                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 376                                 chunk = 0;
 377                                 scratch = 0;
 378                         }
 379                 }
 380         }
 381
 382         sg_miter_stop(&host->sg_miter);
 383
 384         local_irq_restore(flags);
 385 }
 386
 387 static void sdhci_transfer_pio(struct sdhci_host *host)
 388 {
 389         u32 mask;
 390
 391         BUG_ON(!host->data);
 392
 393         if (host->blocks == 0)
 394                 return;
 395
 396         if (host->data->flags & MMC_DATA_READ)
 397                 mask = SDHCI_DATA_AVAILABLE;
 398         else
 399                 mask = SDHCI_SPACE_AVAILABLE;
 400
 401         /*
 402          * Some controllers (JMicron JMB38x) mess up the buffer bits
 403          * for transfers < 4 bytes. As long as it is just one block,
 404          * we can ignore the bits.
 405          */
 406         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 407                 (host->data->blocks == 1))
 408                 mask = ~0;
 409
 410         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 411                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 412                         udelay(100);
 413
 414                 if (host->data->flags & MMC_DATA_READ)
 415                         sdhci_read_block_pio(host);
 416                 else
 417                         sdhci_write_block_pio(host);
 418
 419                 host->blocks--;
 420                 if (host->blocks == 0)
 421                         break;
 422         }
 423
 424         DBG("PIO transfer complete.\n");
 425 }
 426
 427 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 428 {
 429         local_irq_save(*flags);
 430         return kmap_atomic(sg_page(sg)) + sg->offset;
 431 }
 432
 433 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 434 {
 435         kunmap_atomic(buffer);
 436         local_irq_restore(*flags);
 437 }
 438
 439 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 440 {
 441         __le32 *dataddr = (__le32 __force *)(desc + 4);
 442         __le16 *cmdlen = (__le16 __force *)desc;
 443
 444         /* SDHCI specification says ADMA descriptors should be 4 byte
 445          * aligned, so using 16 or 32bit operations should be safe. */
 446
 447         cmdlen[0] = cpu_to_le16(cmd);
 448         cmdlen[1] = cpu_to_le16(len);
 449
 450         dataddr[0] = cpu_to_le32(addr);
 451 }
 452
 453 static int sdhci_adma_table_pre(struct sdhci_host *host,
 454         struct mmc_data *data)
 455 {
 456         int direction;
 457
 458         u8 *desc;
 459         u8 *align;
 460         dma_addr_t addr;
 461         dma_addr_t align_addr;
 462         int len, offset;
 463
 464         struct scatterlist *sg;
 465         int i;
 466         char *buffer;
 467         unsigned long flags;
 468
 469         /*
 470          * The spec does not specify endianness of descriptor table.
 471          * We currently guess that it is LE.
 472          */
 473
 474         if (data->flags & MMC_DATA_READ)
 475                 direction = DMA_FROM_DEVICE;
 476         else
 477                 direction = DMA_TO_DEVICE;
 478
 479         /*
 480          * The ADMA descriptor table is mapped further down as we
 481          * need to fill it with data first.
 482          */
 483
 484         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 485                 host->align_buffer, 128 * 4, direction);
 486         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 487                 goto fail;
 488         BUG_ON(host->align_addr & 0x3);
 489
 490         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 491                 data->sg, data->sg_len, direction);
 492         if (host->sg_count == 0)
 493                 goto unmap_align;
 494
 495         desc = host->adma_desc;
 496         align = host->align_buffer;
 497
 498         align_addr = host->align_addr;
 499
 500         for_each_sg(data->sg, sg, host->sg_count, i) {
 501                 addr = sg_dma_address(sg);
 502                 len = sg_dma_len(sg);
 503
 504                 /*
 505                  * The SDHCI specification states that ADMA
 506                  * addresses must be 32-bit aligned. If they
 507                  * aren't, then we use a bounce buffer for
 508                  * the (up to three) bytes that screw up the
 509                  * alignment.
 510                  */
 511                 offset = (4 - (addr & 0x3)) & 0x3;
 512                 if (offset) {
 513                         if (data->flags & MMC_DATA_WRITE) {
 514                                 buffer = sdhci_kmap_atomic(sg, &flags);
 515                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 516                                 memcpy(align, buffer, offset);
 517                                 sdhci_kunmap_atomic(buffer, &flags);
 518                         }
 519
 520                         /* tran, valid */
 521                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 522
 523                         BUG_ON(offset > 65536);
 524
 525                         align += 4;
 526                         align_addr += 4;
 527
 528                         desc += 8;
 529
 530                         addr += offset;
 531                         len -= offset;
 532                 }
 533
 534                 BUG_ON(len > 65536);
 535
 536                 /* tran, valid */
 537                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 538                 desc += 8;
 539
 540                 /*
 541                  * If this triggers then we have a calculation bug
 542                  * somewhere. :/
 543                  */
 544                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 545         }
 546
 547         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 548                 /*
 549                 * Mark the last descriptor as the terminating descriptor
 550                 */
 551                 if (desc != host->adma_desc) {
 552                         desc -= 8;
 553                         desc[0] |= 0x2; /* end */
 554                 }
 555         } else {
 556                 /*
 557                 * Add a terminating entry.
 558                 */
 559
 560                 /* nop, end, valid */
 561                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 562         }
 563
 564         /*
 565          * Resync align buffer as we might have changed it.
 566          */
 567         if (data->flags & MMC_DATA_WRITE) {
 568                 dma_sync_single_for_device(mmc_dev(host->mmc),
 569                         host->align_addr, 128 * 4, direction);
 570         }
 571
 572         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 573                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 574         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 575                 goto unmap_entries;
 576         BUG_ON(host->adma_addr & 0x3);
 577
 578         return 0;
 579
 580 unmap_entries:
 581         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 582                 data->sg_len, direction);
 583 unmap_align:
 584         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 585                 128 * 4, direction);
 586 fail:
 587         return -EINVAL;
 588 }
 589
 590 static void sdhci_adma_table_post(struct sdhci_host *host,
 591         struct mmc_data *data)
 592 {
 593         int direction;
 594
 595         struct scatterlist *sg;
 596         int i, size;
 597         u8 *align;
 598         char *buffer;
 599         unsigned long flags;
 600
 601         if (data->flags & MMC_DATA_READ)
 602                 direction = DMA_FROM_DEVICE;
 603         else
 604                 direction = DMA_TO_DEVICE;
 605
 606         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 607                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 608
 609         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 610                 128 * 4, direction);
 611
 612         if (data->flags & MMC_DATA_READ) {
 613                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 614                         data->sg_len, direction);
 615
 616                 align = host->align_buffer;
 617
 618                 for_each_sg(data->sg, sg, host->sg_count, i) {
 619                         if (sg_dma_address(sg) & 0x3) {
 620                                 size = 4 - (sg_dma_address(sg) & 0x3);
 621
 622                                 buffer = sdhci_kmap_atomic(sg, &flags);
 623                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 624                                 memcpy(buffer, align, size);
 625                                 sdhci_kunmap_atomic(buffer, &flags);
 626
 627                                 align += 4;
 628                         }
 629                 }
 630         }
 631
 632         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 633                 data->sg_len, direction);
 634 }
 635
 636 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 637 {
 638         u8 count;
 639         struct mmc_data *data = cmd->data;
 640         unsigned target_timeout, current_timeout;
 641
 642         /*
 643          * If the host controller provides us with an incorrect timeout
 644          * value, just skip the check and use 0xE.  The hardware may take
 645          * longer to time out, but that's much better than having a too-short
 646          * timeout value.
 647          */
 648         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 649                 return 0xE;
 650
 651         /* Unspecified timeout, assume max */
 652         if (!data && !cmd->cmd_timeout_ms)
 653                 return 0xE;
 654
 655         /* timeout in us */
 656         if (!data)
 657                 target_timeout = cmd->cmd_timeout_ms * 1000;
 658         else {
 659                 target_timeout = data->timeout_ns / 1000;
 660                 if (host->clock)
 661                         target_timeout += data->timeout_clks / host->clock;
 662         }
 663
 664         /*
 665          * Figure out needed cycles.
 666          * We do this in steps in order to fit inside a 32 bit int.
 667          * The first step is the minimum timeout, which will have a
 668          * minimum resolution of 6 bits:
 669          * (1) 2^13*1000 > 2^22,
 670          * (2) host->timeout_clk < 2^16
 671          *     =>
 672          *     (1) / (2) > 2^6
 673          */
 674         count = 0;
 675         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 676         while (current_timeout < target_timeout) {
 677                 count++;
 678                 current_timeout <<= 1;
 679                 if (count >= 0xF)
 680                         break;
 681         }
 682
 683         if (count >= 0xF) {
 684                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 685                     mmc_hostname(host->mmc), count, cmd->opcode);
 686                 count = 0xE;
 687         }
 688
 689         return count;
 690 }
 691
 692 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 693 {
 694         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 695         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 696
 697         if (host->flags & SDHCI_REQ_USE_DMA)
 698                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 699         else
 700                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 701 }
 702
 703 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 704 {
 705         u8 count;
 706         u8 ctrl;
 707         struct mmc_data *data = cmd->data;
 708         int ret;
 709
 710         WARN_ON(host->data);
 711
 712         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 713                 count = sdhci_calc_timeout(host, cmd);
 714                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 715         }
 716
 717         if (!data)
 718                 return;
 719
 720         /* Sanity checks */
 721         BUG_ON(data->blksz * data->blocks > 524288);
 722         BUG_ON(data->blksz > host->mmc->max_blk_size);
 723         BUG_ON(data->blocks > 65535);
 724
 725         host->data = data;
 726         host->data_early = 0;
 727         host->data->bytes_xfered = 0;
 728
 729         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 730                 host->flags |= SDHCI_REQ_USE_DMA;
 731
 732         /*
 733          * FIXME: This doesn't account for merging when mapping the
 734          * scatterlist.
 735          */
 736         if (host->flags & SDHCI_REQ_USE_DMA) {
 737                 int broken, i;
 738                 struct scatterlist *sg;
 739
 740                 broken = 0;
 741                 if (host->flags & SDHCI_USE_ADMA) {
 742                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 743                                 broken = 1;
 744                 } else {
 745                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 746                                 broken = 1;
 747                 }
 748
 749                 if (unlikely(broken)) {
 750                         for_each_sg(data->sg, sg, data->sg_len, i) {
 751                                 if (sg->length & 0x3) {
 752                                         DBG("Reverting to PIO because of "
 753                                                 "transfer size (%d)\n",
 754                                                 sg->length);
 755                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 756                                         break;
 757                                 }
 758                         }
 759                 }
 760         }
 761
 762         /*
 763          * The assumption here being that alignment is the same after
 764          * translation to device address space.
 765          */
 766         if (host->flags & SDHCI_REQ_USE_DMA) {
 767                 int broken, i;
 768                 struct scatterlist *sg;
 769
 770                 broken = 0;
 771                 if (host->flags & SDHCI_USE_ADMA) {
 772                         /*
 773                          * As we use 3 byte chunks to work around
 774                          * alignment problems, we need to check this
 775                          * quirk.
 776                          */
 777                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 778                                 broken = 1;
 779                 } else {
 780                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 781                                 broken = 1;
 782                 }
 783
 784                 if (unlikely(broken)) {
 785                         for_each_sg(data->sg, sg, data->sg_len, i) {
 786                                 if (sg->offset & 0x3) {
 787                                         DBG("Reverting to PIO because of "
 788                                                 "bad alignment\n");
 789                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 790                                         break;
 791                                 }
 792                         }
 793                 }
 794         }
 795
 796         if (host->flags & SDHCI_REQ_USE_DMA) {
 797                 if (host->flags & SDHCI_USE_ADMA) {
 798                         ret = sdhci_adma_table_pre(host, data);
 799                         if (ret) {
 800                                 /*
 801                                  * This only happens when someone fed
 802                                  * us an invalid request.
 803                                  */
 804                                 WARN_ON(1);
 805                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 806                         } else {
 807                                 sdhci_writel(host, host->adma_addr,
 808                                         SDHCI_ADMA_ADDRESS);
 809                         }
 810                 } else {
 811                         int sg_cnt;
 812
 813                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 814                                         data->sg, data->sg_len,
 815                                         (data->flags & MMC_DATA_READ) ?
 816                                                 DMA_FROM_DEVICE :
 817                                                 DMA_TO_DEVICE);
 818                         if (sg_cnt == 0) {
 819                                 /*
 820                                  * This only happens when someone fed
 821                                  * us an invalid request.
 822                                  */
 823                                 WARN_ON(1);
 824                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 825                         } else {
 826                                 WARN_ON(sg_cnt != 1);
 827                                 sdhci_writel(host, sg_dma_address(data->sg),
 828                                         SDHCI_DMA_ADDRESS);
 829                         }
 830                 }
 831         }
 832
 833         /*
 834          * Always adjust the DMA selection as some controllers
 835          * (e.g. JMicron) can't do PIO properly when the selection
 836          * is ADMA.
 837          */
 838         if (host->version >= SDHCI_SPEC_200) {
 839                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 840                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 841                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 842                         (host->flags & SDHCI_USE_ADMA))
 843                         ctrl |= SDHCI_CTRL_ADMA32;
 844                 else
 845                         ctrl |= SDHCI_CTRL_SDMA;
 846                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 847         }
 848
 849         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 850                 int flags;
 851
 852                 flags = SG_MITER_ATOMIC;
 853                 if (host->data->flags & MMC_DATA_READ)
 854                         flags |= SG_MITER_TO_SG;
 855                 else
 856                         flags |= SG_MITER_FROM_SG;
 857                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 858                 host->blocks = data->blocks;
 859         }
 860
 861         sdhci_set_transfer_irqs(host);
 862
 863         /* Set the DMA boundary value and block size */
 864         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 865                 data->blksz), SDHCI_BLOCK_SIZE);
 866         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 867 }
 868
 869 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 870         struct mmc_command *cmd)
 871 {
 872         u16 mode;
 873         struct mmc_data *data = cmd->data;
 874
 875         if (data == NULL)
 876                 return;
 877
 878         WARN_ON(!host->data);
 879
 880         mode = SDHCI_TRNS_BLK_CNT_EN;
 881         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 882                 mode |= SDHCI_TRNS_MULTI;
 883                 /*
 884                  * If we are sending CMD23, CMD12 never gets sent
 885                  * on successful completion (so no Auto-CMD12).
 886                  */
 887                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 888                         mode |= SDHCI_TRNS_AUTO_CMD12;
 889                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 890                         mode |= SDHCI_TRNS_AUTO_CMD23;
 891                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 892                 }
 893         }
 894
 895         if (data->flags & MMC_DATA_READ)
 896                 mode |= SDHCI_TRNS_READ;
 897         if (host->flags & SDHCI_REQ_USE_DMA)
 898                 mode |= SDHCI_TRNS_DMA;
 899
 900         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 901 }
 902
 903 static void sdhci_finish_data(struct sdhci_host *host)
 904 {
 905         struct mmc_data *data;
 906
 907         BUG_ON(!host->data);
 908
 909         data = host->data;
 910         host->data = NULL;
 911
 912         if (host->flags & SDHCI_REQ_USE_DMA) {
 913                 if (host->flags & SDHCI_USE_ADMA)
 914                         sdhci_adma_table_post(host, data);
 915                 else {
 916                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 917                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 918                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 919                 }
 920         }
 921
 922         /*
 923          * The specification states that the block count register must
 924          * be updated, but it does not specify at what point in the
 925          * data flow. That makes the register entirely useless to read
 926          * back so we have to assume that nothing made it to the card
 927          * in the event of an error.
 928          */
 929         if (data->error)
 930                 data->bytes_xfered = 0;
 931         else
 932                 data->bytes_xfered = data->blksz * data->blocks;
 933
 934         /*
 935          * Need to send CMD12 if -
 936          * a) open-ended multiblock transfer (no CMD23)
 937          * b) error in multiblock transfer
 938          */
 939         if (data->stop &&
 940             (data->error ||
 941              !host->mrq->sbc)) {
 942
 943                 /*
 944                  * The controller needs a reset of internal state machines
 945                  * upon error conditions.
 946                  */
 947                 if (data->error) {
 948                         sdhci_reset(host, SDHCI_RESET_CMD);
 949                         sdhci_reset(host, SDHCI_RESET_DATA);
 950                 }
 951
 952                 sdhci_send_command(host, data->stop);
 953         } else
 954                 tasklet_schedule(&host->finish_tasklet);
 955 }
 956
 957 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 958 {
 959         int flags;
 960         u32 mask;
 961         unsigned long timeout;
 962
 963         WARN_ON(host->cmd);
 964
 965         /* Wait max 10 ms */
 966         timeout = 10;
 967
 968         mask = SDHCI_CMD_INHIBIT;
 969         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 970                 mask |= SDHCI_DATA_INHIBIT;
 971
 972         /* We shouldn't wait for data inihibit for stop commands, even
 973            though they might use busy signaling */
 974         if (host->mrq->data && (cmd == host->mrq->data->stop))
 975                 mask &= ~SDHCI_DATA_INHIBIT;
 976
 977         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 978                 if (timeout == 0) {
 979                         pr_err("%s: Controller never released "
 980                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 981                         sdhci_dumpregs(host);
 982                         cmd->error = -EIO;
 983                         tasklet_schedule(&host->finish_tasklet);
 984                         return;
 985                 }
 986                 timeout--;
 987                 mdelay(1);
 988         }
 989
 990         mod_timer(&host->timer, jiffies + 10 * HZ);
 991
 992         host->cmd = cmd;
 993
 994         sdhci_prepare_data(host, cmd);
 995
 996         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
 997
 998         sdhci_set_transfer_mode(host, cmd);
 999
1000         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1001                 pr_err("%s: Unsupported response type!\n",
1002                         mmc_hostname(host->mmc));
1003                 cmd->error = -EINVAL;
1004                 tasklet_schedule(&host->finish_tasklet);
1005                 return;
1006         }
1007
1008         if (!(cmd->flags & MMC_RSP_PRESENT))
1009                 flags = SDHCI_CMD_RESP_NONE;
1010         else if (cmd->flags & MMC_RSP_136)
1011                 flags = SDHCI_CMD_RESP_LONG;
1012         else if (cmd->flags & MMC_RSP_BUSY)
1013                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1014         else
1015                 flags = SDHCI_CMD_RESP_SHORT;
1016
1017         if (cmd->flags & MMC_RSP_CRC)
1018                 flags |= SDHCI_CMD_CRC;
1019         if (cmd->flags & MMC_RSP_OPCODE)
1020                 flags |= SDHCI_CMD_INDEX;
1021
1022         /* CMD19 is special in that the Data Present Select should be set */
1023         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1024             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1025                 flags |= SDHCI_CMD_DATA;
1026
1027         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1028 }
1029
1030 static void sdhci_finish_command(struct sdhci_host *host)
1031 {
1032         int i;
1033
1034         BUG_ON(host->cmd == NULL);
1035
1036         if (host->cmd->flags & MMC_RSP_PRESENT) {
1037                 if (host->cmd->flags & MMC_RSP_136) {
1038                         /* CRC is stripped so we need to do some shifting. */
1039                         for (i = 0;i < 4;i++) {
1040                                 host->cmd->resp[i] = sdhci_readl(host,
1041                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1042                                 if (i != 3)
1043                                         host->cmd->resp[i] |=
1044                                                 sdhci_readb(host,
1045                                                 SDHCI_RESPONSE + (3-i)*4-1);
1046                         }
1047                 } else {
1048                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1049                 }
1050         }
1051
1052         host->cmd->error = 0;
1053
1054         /* Finished CMD23, now send actual command. */
1055         if (host->cmd == host->mrq->sbc) {
1056                 host->cmd = NULL;
1057                 sdhci_send_command(host, host->mrq->cmd);
1058         } else {
1059
1060                 /* Processed actual command. */
1061                 if (host->data && host->data_early)
1062                         sdhci_finish_data(host);
1063
1064                 if (!host->cmd->data)
1065                         tasklet_schedule(&host->finish_tasklet);
1066
1067                 host->cmd = NULL;
1068         }
1069 }
1070
1071 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1072 {
1073         int div = 0; /* Initialized for compiler warning */
1074         int real_div = div, clk_mul = 1;
1075         u16 clk = 0;
1076         unsigned long timeout;
1077
1078         if (clock && clock == host->clock)
1079                 return;
1080
1081         host->mmc->actual_clock = 0;
1082
1083         if (host->ops->set_clock) {
1084                 host->ops->set_clock(host, clock);
1085                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1086                         return;
1087         }
1088
1089         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1090
1091         if (clock == 0)
1092                 goto out;
1093
1094         if (host->version >= SDHCI_SPEC_300) {
1095                 /*
1096                  * Check if the Host Controller supports Programmable Clock
1097                  * Mode.
1098                  */
1099                 if (host->clk_mul) {
1100                         u16 ctrl;
1101
1102                         /*
1103                          * We need to figure out whether the Host Driver needs
1104                          * to select Programmable Clock Mode, or the value can
1105                          * be set automatically by the Host Controller based on
1106                          * the Preset Value registers.
1107                          */
1108                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1109                         if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1110                                 for (div = 1; div <= 1024; div++) {
1111                                         if (((host->max_clk * host->clk_mul) /
1112                                               div) <= clock)
1113                                                 break;
1114                                 }
1115                                 /*
1116                                  * Set Programmable Clock Mode in the Clock
1117                                  * Control register.
1118                                  */
1119                                 clk = SDHCI_PROG_CLOCK_MODE;
1120                                 real_div = div;
1121                                 clk_mul = host->clk_mul;
1122                                 div--;
1123                         }
1124                 } else {
1125                         /* Version 3.00 divisors must be a multiple of 2. */
1126                         if (host->max_clk <= clock)
1127                                 div = 1;
1128                         else {
1129                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1130                                      div += 2) {
1131                                         if ((host->max_clk / div) <= clock)
1132                                                 break;
1133                                 }
1134                         }
1135                         real_div = div;
1136                         div >>= 1;
1137                 }
1138         } else {
1139                 /* Version 2.00 divisors must be a power of 2. */
1140                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1141                         if ((host->max_clk / div) <= clock)
1142                                 break;
1143                 }
1144                 real_div = div;
1145                 div >>= 1;
1146         }
1147
1148         if (real_div)
1149                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1150
1151         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1152         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1153                 << SDHCI_DIVIDER_HI_SHIFT;
1154         clk |= SDHCI_CLOCK_INT_EN;
1155         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1156
1157         /* Wait max 20 ms */
1158         timeout = 20;
1159         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1160                 & SDHCI_CLOCK_INT_STABLE)) {
1161                 if (timeout == 0) {
1162                         pr_err("%s: Internal clock never "
1163                                 "stabilised.\n", mmc_hostname(host->mmc));
1164                         sdhci_dumpregs(host);
1165                         return;
1166                 }
1167                 timeout--;
1168                 mdelay(1);
1169         }
1170
1171         clk |= SDHCI_CLOCK_CARD_EN;
1172         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1173
1174 out:
1175         host->clock = clock;
1176 }
1177
1178 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1179 {
1180         u8 pwr = 0;
1181
1182         if (power != (unsigned short)-1) {
1183                 switch (1 << power) {
1184                 case MMC_VDD_165_195:
1185                         pwr = SDHCI_POWER_180;
1186                         break;
1187                 case MMC_VDD_29_30:
1188                 case MMC_VDD_30_31:
1189                         pwr = SDHCI_POWER_300;
1190                         break;
1191                 case MMC_VDD_32_33:
1192                 case MMC_VDD_33_34:
1193                         pwr = SDHCI_POWER_330;
1194                         break;
1195                 default:
1196                         BUG();
1197                 }
1198         }
1199
1200         if (host->pwr == pwr)
1201                 return -1;
1202
1203         host->pwr = pwr;
1204
1205         if (pwr == 0) {
1206                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1207                 return 0;
1208         }
1209
1210         /*
1211          * Spec says that we should clear the power reg before setting
1212          * a new value. Some controllers don't seem to like this though.
1213          */
1214         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1215                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1216
1217         /*
1218          * At least the Marvell CaFe chip gets confused if we set the voltage
1219          * and set turn on power at the same time, so set the voltage first.
1220          */
1221         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1222                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1223
1224         pwr |= SDHCI_POWER_ON;
1225
1226         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1227
1228         /*
1229          * Some controllers need an extra 10ms delay of 10ms before they
1230          * can apply clock after applying power
1231          */
1232         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1233                 mdelay(10);
1234
1235         return power;
1236 }
1237
1238 /*****************************************************************************\
1239  *                                                                           *
1240  * MMC callbacks                                                             *
1241  *                                                                           *
1242 \*****************************************************************************/
1243
1244 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245 {
1246         struct sdhci_host *host;
1247         bool present;
1248         unsigned long flags;
1249         u32 tuning_opcode;
1250
1251         host = mmc_priv(mmc);
1252
1253         sdhci_runtime_pm_get(host);
1254
1255         spin_lock_irqsave(&host->lock, flags);
1256
1257         WARN_ON(host->mrq != NULL);
1258
1259 #ifndef SDHCI_USE_LEDS_CLASS
1260         sdhci_activate_led(host);
1261 #endif
1262
1263         /*
1264          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1265          * requests if Auto-CMD12 is enabled.
1266          */
1267         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1268                 if (mrq->stop) {
1269                         mrq->data->stop = NULL;
1270                         mrq->stop = NULL;
1271                 }
1272         }
1273
1274         host->mrq = mrq;
1275
1276         /* If polling, assume that the card is always present. */
1277         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1278                 present = true;
1279         else
1280                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1281                                 SDHCI_CARD_PRESENT;
1282
1283         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1284                 host->mrq->cmd->error = -ENOMEDIUM;
1285                 tasklet_schedule(&host->finish_tasklet);
1286         } else {
1287                 u32 present_state;
1288
1289                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1290                 /*
1291                  * Check if the re-tuning timer has already expired and there
1292                  * is no on-going data transfer. If so, we need to execute
1293                  * tuning procedure before sending command.
1294                  */
1295                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1296                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1297                         /* eMMC uses cmd21 while sd and sdio use cmd19 */
1298                         tuning_opcode = mmc->card->type == MMC_TYPE_MMC ?
1299                                 MMC_SEND_TUNING_BLOCK_HS200 :
1300                                 MMC_SEND_TUNING_BLOCK;
1301                         spin_unlock_irqrestore(&host->lock, flags);
1302                         sdhci_execute_tuning(mmc, tuning_opcode);
1303                         spin_lock_irqsave(&host->lock, flags);
1304
1305                         /* Restore original mmc_request structure */
1306                         host->mrq = mrq;
1307                 }
1308
1309                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1310                         sdhci_send_command(host, mrq->sbc);
1311                 else
1312                         sdhci_send_command(host, mrq->cmd);
1313         }
1314
1315         mmiowb();
1316         spin_unlock_irqrestore(&host->lock, flags);
1317 }
1318
1319 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1320 {
1321         unsigned long flags;
1322         int vdd_bit = -1;
1323         u8 ctrl;
1324
1325         spin_lock_irqsave(&host->lock, flags);
1326
1327         if (host->flags & SDHCI_DEVICE_DEAD) {
1328                 spin_unlock_irqrestore(&host->lock, flags);
1329                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1330                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1331                 return;
1332         }
1333
1334         /*
1335          * Reset the chip on each power off.
1336          * Should clear out any weird states.
1337          */
1338         if (ios->power_mode == MMC_POWER_OFF) {
1339                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1340                 sdhci_reinit(host);
1341         }
1342
1343         sdhci_set_clock(host, ios->clock);
1344
1345         if (ios->power_mode == MMC_POWER_OFF)
1346                 vdd_bit = sdhci_set_power(host, -1);
1347         else
1348                 vdd_bit = sdhci_set_power(host, ios->vdd);
1349
1350         if (host->vmmc && vdd_bit != -1) {
1351                 spin_unlock_irqrestore(&host->lock, flags);
1352                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1353                 spin_lock_irqsave(&host->lock, flags);
1354         }
1355
1356         if (host->ops->platform_send_init_74_clocks)
1357                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1358
1359         /*
1360          * If your platform has 8-bit width support but is not a v3 controller,
1361          * or if it requires special setup code, you should implement that in
1362          * platform_8bit_width().
1363          */
1364         if (host->ops->platform_8bit_width)
1365                 host->ops->platform_8bit_width(host, ios->bus_width);
1366         else {
1367                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1368                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1369                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1370                         if (host->version >= SDHCI_SPEC_300)
1371                                 ctrl |= SDHCI_CTRL_8BITBUS;
1372                 } else {
1373                         if (host->version >= SDHCI_SPEC_300)
1374                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1375                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1376                                 ctrl |= SDHCI_CTRL_4BITBUS;
1377                         else
1378                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1379                 }
1380                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1381         }
1382
1383         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1384
1385         if ((ios->timing == MMC_TIMING_SD_HS ||
1386              ios->timing == MMC_TIMING_MMC_HS)
1387             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1388                 ctrl |= SDHCI_CTRL_HISPD;
1389         else
1390                 ctrl &= ~SDHCI_CTRL_HISPD;
1391
1392         if (host->version >= SDHCI_SPEC_300) {
1393                 u16 clk, ctrl_2;
1394                 unsigned int clock;
1395
1396                 /* In case of UHS-I modes, set High Speed Enable */
1397                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1398                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1399                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1400                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1401                     (ios->timing == MMC_TIMING_UHS_SDR25))
1402                         ctrl |= SDHCI_CTRL_HISPD;
1403
1404                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1405                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1406                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1407                         /*
1408                          * We only need to set Driver Strength if the
1409                          * preset value enable is not set.
1410                          */
1411                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1412                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1413                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1414                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1415                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1416
1417                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1418                 } else {
1419                         /*
1420                          * According to SDHC Spec v3.00, if the Preset Value
1421                          * Enable in the Host Control 2 register is set, we
1422                          * need to reset SD Clock Enable before changing High
1423                          * Speed Enable to avoid generating clock gliches.
1424                          */
1425
1426                         /* Reset SD Clock Enable */
1427                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1428                         clk &= ~SDHCI_CLOCK_CARD_EN;
1429                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1430
1431                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1432
1433                         /* Re-enable SD Clock */
1434                         clock = host->clock;
1435                         host->clock = 0;
1436                         sdhci_set_clock(host, clock);
1437                 }
1438
1439
1440                 /* Reset SD Clock Enable */
1441                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1442                 clk &= ~SDHCI_CLOCK_CARD_EN;
1443                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1444
1445                 if (host->ops->set_uhs_signaling)
1446                         host->ops->set_uhs_signaling(host, ios->timing);
1447                 else {
1448                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1449                         /* Select Bus Speed Mode for host */
1450                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1451                         if (ios->timing == MMC_TIMING_MMC_HS200)
1452                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1453                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1454                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1455                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1456                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1457                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1458                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1459                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1460                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1461                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1462                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1463                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1464                 }
1465
1466                 /* Re-enable SD Clock */
1467                 clock = host->clock;
1468                 host->clock = 0;
1469                 sdhci_set_clock(host, clock);
1470         } else
1471                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1472
1473         /*
1474          * Some (ENE) controllers go apeshit on some ios operation,
1475          * signalling timeout and CRC errors even on CMD0. Resetting
1476          * it on each ios seems to solve the problem.
1477          */
1478         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1479                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1480
1481         mmiowb();
1482         spin_unlock_irqrestore(&host->lock, flags);
1483 }
1484
1485 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1486 {
1487         struct sdhci_host *host = mmc_priv(mmc);
1488
1489         sdhci_runtime_pm_get(host);
1490         sdhci_do_set_ios(host, ios);
1491         sdhci_runtime_pm_put(host);
1492 }
1493
1494 static int sdhci_check_ro(struct sdhci_host *host)
1495 {
1496         unsigned long flags;
1497         int is_readonly;
1498
1499         spin_lock_irqsave(&host->lock, flags);
1500
1501         if (host->flags & SDHCI_DEVICE_DEAD)
1502                 is_readonly = 0;
1503         else if (host->ops->get_ro)
1504                 is_readonly = host->ops->get_ro(host);
1505         else
1506                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1507                                 & SDHCI_WRITE_PROTECT);
1508
1509         spin_unlock_irqrestore(&host->lock, flags);
1510
1511         /* This quirk needs to be replaced by a callback-function later */
1512         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1513                 !is_readonly : is_readonly;
1514 }
1515
1516 #define SAMPLE_COUNT    5
1517
1518 static int sdhci_do_get_ro(struct sdhci_host *host)
1519 {
1520         int i, ro_count;
1521
1522         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1523                 return sdhci_check_ro(host);
1524
1525         ro_count = 0;
1526         for (i = 0; i < SAMPLE_COUNT; i++) {
1527                 if (sdhci_check_ro(host)) {
1528                         if (++ro_count > SAMPLE_COUNT / 2)
1529                                 return 1;
1530                 }
1531                 msleep(30);
1532         }
1533         return 0;
1534 }
1535
1536 static void sdhci_hw_reset(struct mmc_host *mmc)
1537 {
1538         struct sdhci_host *host = mmc_priv(mmc);
1539
1540         if (host->ops && host->ops->hw_reset)
1541                 host->ops->hw_reset(host);
1542 }
1543
1544 static int sdhci_get_ro(struct mmc_host *mmc)
1545 {
1546         struct sdhci_host *host = mmc_priv(mmc);
1547         int ret;
1548
1549         sdhci_runtime_pm_get(host);
1550         ret = sdhci_do_get_ro(host);
1551         sdhci_runtime_pm_put(host);
1552         return ret;
1553 }
1554
1555 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1556 {
1557         if (host->flags & SDHCI_DEVICE_DEAD)
1558                 goto out;
1559
1560         if (enable)
1561                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1562         else
1563                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1564
1565         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1566         if (host->runtime_suspended)
1567                 goto out;
1568
1569         if (enable)
1570                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1571         else
1572                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1573 out:
1574         mmiowb();
1575 }
1576
1577 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1578 {
1579         struct sdhci_host *host = mmc_priv(mmc);
1580         unsigned long flags;
1581
1582         spin_lock_irqsave(&host->lock, flags);
1583         sdhci_enable_sdio_irq_nolock(host, enable);
1584         spin_unlock_irqrestore(&host->lock, flags);
1585 }
1586
1587 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1588                                                 struct mmc_ios *ios)
1589 {
1590         u8 pwr;
1591         u16 clk, ctrl;
1592         u32 present_state;
1593
1594         /*
1595          * Signal Voltage Switching is only applicable for Host Controllers
1596          * v3.00 and above.
1597          */
1598         if (host->version < SDHCI_SPEC_300)
1599                 return 0;
1600
1601         /*
1602          * We first check whether the request is to set signalling voltage
1603          * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
1604          */
1605         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1606         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1607                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1608                 ctrl &= ~SDHCI_CTRL_VDD_180;
1609                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1610
1611                 /* Wait for 5ms */
1612                 usleep_range(5000, 5500);
1613
1614                 /* 3.3V regulator output should be stable within 5 ms */
1615                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1616                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1617                         return 0;
1618                 else {
1619                         pr_info(DRIVER_NAME ": Switching to 3.3V "
1620                                 "signalling voltage failed\n");
1621                         return -EIO;
1622                 }
1623         } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
1624                   (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
1625                 /* Stop SDCLK */
1626                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1627                 clk &= ~SDHCI_CLOCK_CARD_EN;
1628                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1629
1630                 /* Check whether DAT[3:0] is 0000 */
1631                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1632                 if (!((present_state & SDHCI_DATA_LVL_MASK) >>
1633                        SDHCI_DATA_LVL_SHIFT)) {
1634                         /*
1635                          * Enable 1.8V Signal Enable in the Host Control2
1636                          * register
1637                          */
1638                         ctrl |= SDHCI_CTRL_VDD_180;
1639                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1640
1641                         /* Wait for 5ms */
1642                         usleep_range(5000, 5500);
1643
1644                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1645                         if (ctrl & SDHCI_CTRL_VDD_180) {
1646                                 /* Provide SDCLK again and wait for 1ms*/
1647                                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1648                                 clk |= SDHCI_CLOCK_CARD_EN;
1649                                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1650                                 usleep_range(1000, 1500);
1651
1652                                 /*
1653                                  * If DAT[3:0] level is 1111b, then the card
1654                                  * was successfully switched to 1.8V signaling.
1655                                  */
1656                                 present_state = sdhci_readl(host,
1657                                                         SDHCI_PRESENT_STATE);
1658                                 if ((present_state & SDHCI_DATA_LVL_MASK) ==
1659                                      SDHCI_DATA_LVL_MASK)
1660                                         return 0;
1661                         }
1662                 }
1663
1664                 /*
1665                  * If we are here, that means the switch to 1.8V signaling
1666                  * failed. We power cycle the card, and retry initialization
1667                  * sequence by setting S18R to 0.
1668                  */
1669                 pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
1670                 pwr &= ~SDHCI_POWER_ON;
1671                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1672
1673                 /* Wait for 1ms as per the spec */
1674                 usleep_range(1000, 1500);
1675                 pwr |= SDHCI_POWER_ON;
1676                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1677
1678                 pr_info(DRIVER_NAME ": Switching to 1.8V signalling "
1679                         "voltage failed, retrying with S18R set to 0\n");
1680                 return -EAGAIN;
1681         } else
1682                 /* No signal voltage switch required */
1683                 return 0;
1684 }
1685
1686 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1687         struct mmc_ios *ios)
1688 {
1689         struct sdhci_host *host = mmc_priv(mmc);
1690         int err;
1691
1692         if (host->version < SDHCI_SPEC_300)
1693                 return 0;
1694         sdhci_runtime_pm_get(host);
1695         err = sdhci_do_start_signal_voltage_switch(host, ios);
1696         sdhci_runtime_pm_put(host);
1697         return err;
1698 }
1699
1700 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1701 {
1702         struct sdhci_host *host;
1703         u16 ctrl;
1704         u32 ier;
1705         int tuning_loop_counter = MAX_TUNING_LOOP;
1706         unsigned long timeout;
1707         int err = 0;
1708         bool requires_tuning_nonuhs = false;
1709
1710         host = mmc_priv(mmc);
1711
1712         sdhci_runtime_pm_get(host);
1713         disable_irq(host->irq);
1714         spin_lock(&host->lock);
1715
1716         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1717
1718         /*
1719          * The Host Controller needs tuning only in case of SDR104 mode
1720          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1721          * Capabilities register.
1722          * If the Host Controller supports the HS200 mode then the
1723          * tuning function has to be executed.
1724          */
1725         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1726             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1727              host->flags & SDHCI_HS200_NEEDS_TUNING))
1728                 requires_tuning_nonuhs = true;
1729
1730         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1731             requires_tuning_nonuhs)
1732                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1733         else {
1734                 spin_unlock(&host->lock);
1735                 enable_irq(host->irq);
1736                 sdhci_runtime_pm_put(host);
1737                 return 0;
1738         }
1739
1740         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1741
1742         /*
1743          * As per the Host Controller spec v3.00, tuning command
1744          * generates Buffer Read Ready interrupt, so enable that.
1745          *
1746          * Note: The spec clearly says that when tuning sequence
1747          * is being performed, the controller does not generate
1748          * interrupts other than Buffer Read Ready interrupt. But
1749          * to make sure we don't hit a controller bug, we _only_
1750          * enable Buffer Read Ready interrupt here.
1751          */
1752         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1753         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1754
1755         /*
1756          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1757          * of loops reaches 40 times or a timeout of 150ms occurs.
1758          */
1759         timeout = 150;
1760         do {
1761                 struct mmc_command cmd = {0};
1762                 struct mmc_request mrq = {NULL};
1763
1764                 if (!tuning_loop_counter && !timeout)
1765                         break;
1766
1767                 cmd.opcode = opcode;
1768                 cmd.arg = 0;
1769                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1770                 cmd.retries = 0;
1771                 cmd.data = NULL;
1772                 cmd.error = 0;
1773
1774                 mrq.cmd = &cmd;
1775                 host->mrq = &mrq;
1776
1777                 /*
1778                  * In response to CMD19, the card sends 64 bytes of tuning
1779                  * block to the Host Controller. So we set the block size
1780                  * to 64 here.
1781                  */
1782                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1783                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1784                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1785                                              SDHCI_BLOCK_SIZE);
1786                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1787                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1788                                              SDHCI_BLOCK_SIZE);
1789                 } else {
1790                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1791                                      SDHCI_BLOCK_SIZE);
1792                 }
1793
1794                 /*
1795                  * The tuning block is sent by the card to the host controller.
1796                  * So we set the TRNS_READ bit in the Transfer Mode register.
1797                  * This also takes care of setting DMA Enable and Multi Block
1798                  * Select in the same register to 0.
1799                  */
1800                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1801
1802                 sdhci_send_command(host, &cmd);
1803
1804                 host->cmd = NULL;
1805                 host->mrq = NULL;
1806
1807                 spin_unlock(&host->lock);
1808                 enable_irq(host->irq);
1809
1810                 /* Wait for Buffer Read Ready interrupt */
1811                 wait_event_interruptible_timeout(host->buf_ready_int,
1812                                         (host->tuning_done == 1),
1813                                         msecs_to_jiffies(50));
1814                 disable_irq(host->irq);
1815                 spin_lock(&host->lock);
1816
1817                 if (!host->tuning_done) {
1818                         pr_info(DRIVER_NAME ": Timeout waiting for "
1819                                 "Buffer Read Ready interrupt during tuning "
1820                                 "procedure, falling back to fixed sampling "
1821                                 "clock\n");
1822                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1823                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1824                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1825                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1826
1827                         err = -EIO;
1828                         goto out;
1829                 }
1830
1831                 host->tuning_done = 0;
1832
1833                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1834                 tuning_loop_counter--;
1835                 timeout--;
1836                 mdelay(1);
1837         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1838
1839         /*
1840          * The Host Driver has exhausted the maximum number of loops allowed,
1841          * so use fixed sampling frequency.
1842          */
1843         if (!tuning_loop_counter || !timeout) {
1844                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1845                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1846         } else {
1847                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1848                         pr_info(DRIVER_NAME ": Tuning procedure"
1849                                 " failed, falling back to fixed sampling"
1850                                 " clock\n");
1851                         err = -EIO;
1852                 }
1853         }
1854
1855 out:
1856         /*
1857          * If this is the very first time we are here, we start the retuning
1858          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1859          * flag won't be set, we check this condition before actually starting
1860          * the timer.
1861          */
1862         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1863             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1864                 mod_timer(&host->tuning_timer, jiffies +
1865                         host->tuning_count * HZ);
1866                 /* Tuning mode 1 limits the maximum data length to 4MB */
1867                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1868         } else {
1869                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1870                 /* Reload the new initial value for timer */
1871                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1872                         mod_timer(&host->tuning_timer, jiffies +
1873                                 host->tuning_count * HZ);
1874         }
1875
1876         /*
1877          * In case tuning fails, host controllers which support re-tuning can
1878          * try tuning again at a later time, when the re-tuning timer expires.
1879          * So for these controllers, we return 0. Since there might be other
1880          * controllers who do not have this capability, we return error for
1881          * them.
1882          */
1883         if (err && host->tuning_count &&
1884             host->tuning_mode == SDHCI_TUNING_MODE_1)
1885                 err = 0;
1886
1887         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
1888         spin_unlock(&host->lock);
1889         enable_irq(host->irq);
1890         sdhci_runtime_pm_put(host);
1891
1892         return err;
1893 }
1894
1895 static void sdhci_do_enable_preset_value(struct sdhci_host *host, bool enable)
1896 {
1897         u16 ctrl;
1898         unsigned long flags;
1899
1900         /* Host Controller v3.00 defines preset value registers */
1901         if (host->version < SDHCI_SPEC_300)
1902                 return;
1903
1904         spin_lock_irqsave(&host->lock, flags);
1905
1906         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1907
1908         /*
1909          * We only enable or disable Preset Value if they are not already
1910          * enabled or disabled respectively. Otherwise, we bail out.
1911          */
1912         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1913                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
1914                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1915                 host->flags |= SDHCI_PV_ENABLED;
1916         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1917                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
1918                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1919                 host->flags &= ~SDHCI_PV_ENABLED;
1920         }
1921
1922         spin_unlock_irqrestore(&host->lock, flags);
1923 }
1924
1925 static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
1926 {
1927         struct sdhci_host *host = mmc_priv(mmc);
1928
1929         sdhci_runtime_pm_get(host);
1930         sdhci_do_enable_preset_value(host, enable);
1931         sdhci_runtime_pm_put(host);
1932 }
1933
1934 static const struct mmc_host_ops sdhci_ops = {
1935         .request        = sdhci_request,
1936         .set_ios        = sdhci_set_ios,
1937         .get_ro         = sdhci_get_ro,
1938         .hw_reset       = sdhci_hw_reset,
1939         .enable_sdio_irq = sdhci_enable_sdio_irq,
1940         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
1941         .execute_tuning                 = sdhci_execute_tuning,
1942         .enable_preset_value            = sdhci_enable_preset_value,
1943 };
1944
1945 /*****************************************************************************\
1946  *                                                                           *
1947  * Tasklets                                                                  *
1948  *                                                                           *
1949 \*****************************************************************************/
1950
1951 static void sdhci_tasklet_card(unsigned long param)
1952 {
1953         struct sdhci_host *host;
1954         unsigned long flags;
1955
1956         host = (struct sdhci_host*)param;
1957
1958         spin_lock_irqsave(&host->lock, flags);
1959
1960         /* Check host->mrq first in case we are runtime suspended */
1961         if (host->mrq &&
1962             !(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
1963                 pr_err("%s: Card removed during transfer!\n",
1964                         mmc_hostname(host->mmc));
1965                 pr_err("%s: Resetting controller.\n",
1966                         mmc_hostname(host->mmc));
1967
1968                 sdhci_reset(host, SDHCI_RESET_CMD);
1969                 sdhci_reset(host, SDHCI_RESET_DATA);
1970
1971                 host->mrq->cmd->error = -ENOMEDIUM;
1972                 tasklet_schedule(&host->finish_tasklet);
1973         }
1974
1975         spin_unlock_irqrestore(&host->lock, flags);
1976
1977         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
1978 }
1979
1980 static void sdhci_tasklet_finish(unsigned long param)
1981 {
1982         struct sdhci_host *host;
1983         unsigned long flags;
1984         struct mmc_request *mrq;
1985
1986         host = (struct sdhci_host*)param;
1987
1988         spin_lock_irqsave(&host->lock, flags);
1989
1990         /*
1991          * If this tasklet gets rescheduled while running, it will
1992          * be run again afterwards but without any active request.
1993          */
1994         if (!host->mrq) {
1995                 spin_unlock_irqrestore(&host->lock, flags);
1996                 return;
1997         }
1998
1999         del_timer(&host->timer);
2000
2001         mrq = host->mrq;
2002
2003         /*
2004          * The controller needs a reset of internal state machines
2005          * upon error conditions.
2006          */
2007         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2008             ((mrq->cmd && mrq->cmd->error) ||
2009                  (mrq->data && (mrq->data->error ||
2010                   (mrq->data->stop && mrq->data->stop->error))) ||
2011                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2012
2013                 /* Some controllers need this kick or reset won't work here */
2014                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
2015                         unsigned int clock;
2016
2017                         /* This is to force an update */
2018                         clock = host->clock;
2019                         host->clock = 0;
2020                         sdhci_set_clock(host, clock);
2021                 }
2022
2023                 /* Spec says we should do both at the same time, but Ricoh
2024                    controllers do not like that. */
2025                 sdhci_reset(host, SDHCI_RESET_CMD);
2026                 sdhci_reset(host, SDHCI_RESET_DATA);
2027         }
2028
2029         host->mrq = NULL;
2030         host->cmd = NULL;
2031         host->data = NULL;
2032
2033 #ifndef SDHCI_USE_LEDS_CLASS
2034         sdhci_deactivate_led(host);
2035 #endif
2036
2037         mmiowb();
2038         spin_unlock_irqrestore(&host->lock, flags);
2039
2040         mmc_request_done(host->mmc, mrq);
2041         sdhci_runtime_pm_put(host);
2042 }
2043
2044 static void sdhci_timeout_timer(unsigned long data)
2045 {
2046         struct sdhci_host *host;
2047         unsigned long flags;
2048
2049         host = (struct sdhci_host*)data;
2050
2051         spin_lock_irqsave(&host->lock, flags);
2052
2053         if (host->mrq) {
2054                 pr_err("%s: Timeout waiting for hardware "
2055                         "interrupt.\n", mmc_hostname(host->mmc));
2056                 sdhci_dumpregs(host);
2057
2058                 if (host->data) {
2059                         host->data->error = -ETIMEDOUT;
2060                         sdhci_finish_data(host);
2061                 } else {
2062                         if (host->cmd)
2063                                 host->cmd->error = -ETIMEDOUT;
2064                         else
2065                                 host->mrq->cmd->error = -ETIMEDOUT;
2066
2067                         tasklet_schedule(&host->finish_tasklet);
2068                 }
2069         }
2070
2071         mmiowb();
2072         spin_unlock_irqrestore(&host->lock, flags);
2073 }
2074
2075 static void sdhci_tuning_timer(unsigned long data)
2076 {
2077         struct sdhci_host *host;
2078         unsigned long flags;
2079
2080         host = (struct sdhci_host *)data;
2081
2082         spin_lock_irqsave(&host->lock, flags);
2083
2084         host->flags |= SDHCI_NEEDS_RETUNING;
2085
2086         spin_unlock_irqrestore(&host->lock, flags);
2087 }
2088
2089 /*****************************************************************************\
2090  *                                                                           *
2091  * Interrupt handling                                                        *
2092  *                                                                           *
2093 \*****************************************************************************/
2094
2095 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2096 {
2097         BUG_ON(intmask == 0);
2098
2099         if (!host->cmd) {
2100                 pr_err("%s: Got command interrupt 0x%08x even "
2101                         "though no command operation was in progress.\n",
2102                         mmc_hostname(host->mmc), (unsigned)intmask);
2103                 sdhci_dumpregs(host);
2104                 return;
2105         }
2106
2107         if (intmask & SDHCI_INT_TIMEOUT)
2108                 host->cmd->error = -ETIMEDOUT;
2109         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2110                         SDHCI_INT_INDEX))
2111                 host->cmd->error = -EILSEQ;
2112
2113         if (host->cmd->error) {
2114                 tasklet_schedule(&host->finish_tasklet);
2115                 return;
2116         }
2117
2118         /*
2119          * The host can send and interrupt when the busy state has
2120          * ended, allowing us to wait without wasting CPU cycles.
2121          * Unfortunately this is overloaded on the "data complete"
2122          * interrupt, so we need to take some care when handling
2123          * it.
2124          *
2125          * Note: The 1.0 specification is a bit ambiguous about this
2126          *       feature so there might be some problems with older
2127          *       controllers.
2128          */
2129         if (host->cmd->flags & MMC_RSP_BUSY) {
2130                 if (host->cmd->data)
2131                         DBG("Cannot wait for busy signal when also "
2132                                 "doing a data transfer");
2133                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2134                         return;
2135
2136                 /* The controller does not support the end-of-busy IRQ,
2137                  * fall through and take the SDHCI_INT_RESPONSE */
2138         }
2139
2140         if (intmask & SDHCI_INT_RESPONSE)
2141                 sdhci_finish_command(host);
2142 }
2143
2144 #ifdef CONFIG_MMC_DEBUG
2145 static void sdhci_show_adma_error(struct sdhci_host *host)
2146 {
2147         const char *name = mmc_hostname(host->mmc);
2148         u8 *desc = host->adma_desc;
2149         __le32 *dma;
2150         __le16 *len;
2151         u8 attr;
2152
2153         sdhci_dumpregs(host);
2154
2155         while (true) {
2156                 dma = (__le32 *)(desc + 4);
2157                 len = (__le16 *)(desc + 2);
2158                 attr = *desc;
2159
2160                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2161                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2162
2163                 desc += 8;
2164
2165                 if (attr & 2)
2166                         break;
2167         }
2168 }
2169 #else
2170 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2171 #endif
2172
2173 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2174 {
2175         u32 command;
2176         BUG_ON(intmask == 0);
2177
2178         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2179         if (intmask & SDHCI_INT_DATA_AVAIL) {
2180                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2181                 if (command == MMC_SEND_TUNING_BLOCK ||
2182                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2183                         host->tuning_done = 1;
2184                         wake_up(&host->buf_ready_int);
2185                         return;
2186                 }
2187         }
2188
2189         if (!host->data) {
2190                 /*
2191                  * The "data complete" interrupt is also used to
2192                  * indicate that a busy state has ended. See comment
2193                  * above in sdhci_cmd_irq().
2194                  */
2195                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2196                         if (intmask & SDHCI_INT_DATA_END) {
2197                                 sdhci_finish_command(host);
2198                                 return;
2199                         }
2200                 }
2201
2202                 pr_err("%s: Got data interrupt 0x%08x even "
2203                         "though no data operation was in progress.\n",
2204                         mmc_hostname(host->mmc), (unsigned)intmask);
2205                 sdhci_dumpregs(host);
2206
2207                 return;
2208         }
2209
2210         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2211                 host->data->error = -ETIMEDOUT;
2212         else if (intmask & SDHCI_INT_DATA_END_BIT)
2213                 host->data->error = -EILSEQ;
2214         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2215                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2216                         != MMC_BUS_TEST_R)
2217                 host->data->error = -EILSEQ;
2218         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2219                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2220                 sdhci_show_adma_error(host);
2221                 host->data->error = -EIO;
2222         }
2223
2224         if (host->data->error)
2225                 sdhci_finish_data(host);
2226         else {
2227                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2228                         sdhci_transfer_pio(host);
2229
2230                 /*
2231                  * We currently don't do anything fancy with DMA
2232                  * boundaries, but as we can't disable the feature
2233                  * we need to at least restart the transfer.
2234                  *
2235                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2236                  * should return a valid address to continue from, but as
2237                  * some controllers are faulty, don't trust them.
2238                  */
2239                 if (intmask & SDHCI_INT_DMA_END) {
2240                         u32 dmastart, dmanow;
2241                         dmastart = sg_dma_address(host->data->sg);
2242                         dmanow = dmastart + host->data->bytes_xfered;
2243                         /*
2244                          * Force update to the next DMA block boundary.
2245                          */
2246                         dmanow = (dmanow &
2247                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2248                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2249                         host->data->bytes_xfered = dmanow - dmastart;
2250                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2251                                 " next 0x%08x\n",
2252                                 mmc_hostname(host->mmc), dmastart,
2253                                 host->data->bytes_xfered, dmanow);
2254                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2255                 }
2256
2257                 if (intmask & SDHCI_INT_DATA_END) {
2258                         if (host->cmd) {
2259                                 /*
2260                                  * Data managed to finish before the
2261                                  * command completed. Make sure we do
2262                                  * things in the proper order.
2263                                  */
2264                                 host->data_early = 1;
2265                         } else {
2266                                 sdhci_finish_data(host);
2267                         }
2268                 }
2269         }
2270 }
2271
2272 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2273 {
2274         irqreturn_t result;
2275         struct sdhci_host *host = dev_id;
2276         u32 intmask, unexpected = 0;
2277         int cardint = 0, max_loops = 16;
2278
2279         spin_lock(&host->lock);
2280
2281         if (host->runtime_suspended) {
2282                 spin_unlock(&host->lock);
2283                 pr_warning("%s: got irq while runtime suspended\n",
2284                        mmc_hostname(host->mmc));
2285                 return IRQ_HANDLED;
2286         }
2287
2288         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2289
2290         if (!intmask || intmask == 0xffffffff) {
2291                 result = IRQ_NONE;
2292                 goto out;
2293         }
2294
2295 again:
2296         DBG("*** %s got interrupt: 0x%08x\n",
2297                 mmc_hostname(host->mmc), intmask);
2298
2299         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2300                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2301                               SDHCI_CARD_PRESENT;
2302
2303                 /*
2304                  * There is a observation on i.mx esdhc.  INSERT bit will be
2305                  * immediately set again when it gets cleared, if a card is
2306                  * inserted.  We have to mask the irq to prevent interrupt
2307                  * storm which will freeze the system.  And the REMOVE gets
2308                  * the same situation.
2309                  *
2310                  * More testing are needed here to ensure it works for other
2311                  * platforms though.
2312                  */
2313                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2314                                                 SDHCI_INT_CARD_REMOVE);
2315                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2316                                                   SDHCI_INT_CARD_INSERT);
2317
2318                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2319                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2320                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2321                 tasklet_schedule(&host->card_tasklet);
2322         }
2323
2324         if (intmask & SDHCI_INT_CMD_MASK) {
2325                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2326                         SDHCI_INT_STATUS);
2327                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2328         }
2329
2330         if (intmask & SDHCI_INT_DATA_MASK) {
2331                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2332                         SDHCI_INT_STATUS);
2333                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2334         }
2335
2336         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2337
2338         intmask &= ~SDHCI_INT_ERROR;
2339
2340         if (intmask & SDHCI_INT_BUS_POWER) {
2341                 pr_err("%s: Card is consuming too much power!\n",
2342                         mmc_hostname(host->mmc));
2343                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2344         }
2345
2346         intmask &= ~SDHCI_INT_BUS_POWER;
2347
2348         if (intmask & SDHCI_INT_CARD_INT)
2349                 cardint = 1;
2350
2351         intmask &= ~SDHCI_INT_CARD_INT;
2352
2353         if (intmask) {
2354                 unexpected |= intmask;
2355                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2356         }
2357
2358         result = IRQ_HANDLED;
2359
2360         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2361         if (intmask && --max_loops)
2362                 goto again;
2363 out:
2364         spin_unlock(&host->lock);
2365
2366         if (unexpected) {
2367                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2368                            mmc_hostname(host->mmc), unexpected);
2369                 sdhci_dumpregs(host);
2370         }
2371         /*
2372          * We have to delay this as it calls back into the driver.
2373          */
2374         if (cardint)
2375                 mmc_signal_sdio_irq(host->mmc);
2376
2377         return result;
2378 }
2379
2380 /*****************************************************************************\
2381  *                                                                           *
2382  * Suspend/resume                                                            *
2383  *                                                                           *
2384 \*****************************************************************************/
2385
2386 #ifdef CONFIG_PM
2387
2388 int sdhci_suspend_host(struct sdhci_host *host)
2389 {
2390         int ret;
2391         bool has_tuning_timer;
2392
2393         if (host->ops->platform_suspend)
2394                 host->ops->platform_suspend(host);
2395
2396         sdhci_disable_card_detection(host);
2397
2398         /* Disable tuning since we are suspending */
2399         has_tuning_timer = host->version >= SDHCI_SPEC_300 &&
2400                 host->tuning_count && host->tuning_mode == SDHCI_TUNING_MODE_1;
2401         if (has_tuning_timer) {
2402                 del_timer_sync(&host->tuning_timer);
2403                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2404         }
2405
2406         ret = mmc_suspend_host(host->mmc);
2407         if (ret) {
2408                 if (has_tuning_timer) {
2409                         host->flags |= SDHCI_NEEDS_RETUNING;
2410                         mod_timer(&host->tuning_timer, jiffies +
2411                                         host->tuning_count * HZ);
2412                 }
2413
2414                 sdhci_enable_card_detection(host);
2415
2416                 return ret;
2417         }
2418
2419         free_irq(host->irq, host);
2420
2421         return ret;
2422 }
2423
2424 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2425
2426 int sdhci_resume_host(struct sdhci_host *host)
2427 {
2428         int ret;
2429
2430         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2431                 if (host->ops->enable_dma)
2432                         host->ops->enable_dma(host);
2433         }
2434
2435         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2436                           mmc_hostname(host->mmc), host);
2437         if (ret)
2438                 return ret;
2439
2440         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2441             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2442                 /* Card keeps power but host controller does not */
2443                 sdhci_init(host, 0);
2444                 host->pwr = 0;
2445                 host->clock = 0;
2446                 sdhci_do_set_ios(host, &host->mmc->ios);
2447         } else {
2448                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2449                 mmiowb();
2450         }
2451
2452         ret = mmc_resume_host(host->mmc);
2453         sdhci_enable_card_detection(host);
2454
2455         if (host->ops->platform_resume)
2456                 host->ops->platform_resume(host);
2457
2458         /* Set the re-tuning expiration flag */
2459         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2460             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2461                 host->flags |= SDHCI_NEEDS_RETUNING;
2462
2463         return ret;
2464 }
2465
2466 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2467
2468 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2469 {
2470         u8 val;
2471         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2472         val |= SDHCI_WAKE_ON_INT;
2473         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2474 }
2475
2476 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2477
2478 #endif /* CONFIG_PM */
2479
2480 #ifdef CONFIG_PM_RUNTIME
2481
2482 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2483 {
2484         return pm_runtime_get_sync(host->mmc->parent);
2485 }
2486
2487 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2488 {
2489         pm_runtime_mark_last_busy(host->mmc->parent);
2490         return pm_runtime_put_autosuspend(host->mmc->parent);
2491 }
2492
2493 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2494 {
2495         unsigned long flags;
2496         int ret = 0;
2497
2498         /* Disable tuning since we are suspending */
2499         if (host->version >= SDHCI_SPEC_300 &&
2500             host->tuning_mode == SDHCI_TUNING_MODE_1) {
2501                 del_timer_sync(&host->tuning_timer);
2502                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2503         }
2504
2505         spin_lock_irqsave(&host->lock, flags);
2506         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2507         spin_unlock_irqrestore(&host->lock, flags);
2508
2509         synchronize_irq(host->irq);
2510
2511         spin_lock_irqsave(&host->lock, flags);
2512         host->runtime_suspended = true;
2513         spin_unlock_irqrestore(&host->lock, flags);
2514
2515         return ret;
2516 }
2517 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2518
2519 int sdhci_runtime_resume_host(struct sdhci_host *host)
2520 {
2521         unsigned long flags;
2522         int ret = 0, host_flags = host->flags;
2523
2524         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2525                 if (host->ops->enable_dma)
2526                         host->ops->enable_dma(host);
2527         }
2528
2529         sdhci_init(host, 0);
2530
2531         /* Force clock and power re-program */
2532         host->pwr = 0;
2533         host->clock = 0;
2534         sdhci_do_set_ios(host, &host->mmc->ios);
2535
2536         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2537         if (host_flags & SDHCI_PV_ENABLED)
2538                 sdhci_do_enable_preset_value(host, true);
2539
2540         /* Set the re-tuning expiration flag */
2541         if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
2542             (host->tuning_mode == SDHCI_TUNING_MODE_1))
2543                 host->flags |= SDHCI_NEEDS_RETUNING;
2544
2545         spin_lock_irqsave(&host->lock, flags);
2546
2547         host->runtime_suspended = false;
2548
2549         /* Enable SDIO IRQ */
2550         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2551                 sdhci_enable_sdio_irq_nolock(host, true);
2552
2553         /* Enable Card Detection */
2554         sdhci_enable_card_detection(host);
2555
2556         spin_unlock_irqrestore(&host->lock, flags);
2557
2558         return ret;
2559 }
2560 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2561
2562 #endif
2563
2564 /*****************************************************************************\
2565  *                                                                           *
2566  * Device allocation/registration                                            *
2567  *                                                                           *
2568 \*****************************************************************************/
2569
2570 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2571         size_t priv_size)
2572 {
2573         struct mmc_host *mmc;
2574         struct sdhci_host *host;
2575
2576         WARN_ON(dev == NULL);
2577
2578         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2579         if (!mmc)
2580                 return ERR_PTR(-ENOMEM);
2581
2582         host = mmc_priv(mmc);
2583         host->mmc = mmc;
2584
2585         return host;
2586 }
2587
2588 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2589
2590 int sdhci_add_host(struct sdhci_host *host)
2591 {
2592         struct mmc_host *mmc;
2593         u32 caps[2] = {0, 0};
2594         u32 max_current_caps;
2595         unsigned int ocr_avail;
2596         int ret;
2597
2598         WARN_ON(host == NULL);
2599         if (host == NULL)
2600                 return -EINVAL;
2601
2602         mmc = host->mmc;
2603
2604         if (debug_quirks)
2605                 host->quirks = debug_quirks;
2606         if (debug_quirks2)
2607                 host->quirks2 = debug_quirks2;
2608
2609         sdhci_reset(host, SDHCI_RESET_ALL);
2610
2611         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2612         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2613                                 >> SDHCI_SPEC_VER_SHIFT;
2614         if (host->version > SDHCI_SPEC_300) {
2615                 pr_err("%s: Unknown controller version (%d). "
2616                         "You may experience problems.\n", mmc_hostname(mmc),
2617                         host->version);
2618         }
2619
2620         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2621                 sdhci_readl(host, SDHCI_CAPABILITIES);
2622
2623         if (host->version >= SDHCI_SPEC_300)
2624                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2625                         host->caps1 :
2626                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2627
2628         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2629                 host->flags |= SDHCI_USE_SDMA;
2630         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2631                 DBG("Controller doesn't have SDMA capability\n");
2632         else
2633                 host->flags |= SDHCI_USE_SDMA;
2634
2635         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2636                 (host->flags & SDHCI_USE_SDMA)) {
2637                 DBG("Disabling DMA as it is marked broken\n");
2638                 host->flags &= ~SDHCI_USE_SDMA;
2639         }
2640
2641         if ((host->version >= SDHCI_SPEC_200) &&
2642                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2643                 host->flags |= SDHCI_USE_ADMA;
2644
2645         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2646                 (host->flags & SDHCI_USE_ADMA)) {
2647                 DBG("Disabling ADMA as it is marked broken\n");
2648                 host->flags &= ~SDHCI_USE_ADMA;
2649         }
2650
2651         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2652                 if (host->ops->enable_dma) {
2653                         if (host->ops->enable_dma(host)) {
2654                                 pr_warning("%s: No suitable DMA "
2655                                         "available. Falling back to PIO.\n",
2656                                         mmc_hostname(mmc));
2657                                 host->flags &=
2658                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2659                         }
2660                 }
2661         }
2662
2663         if (host->flags & SDHCI_USE_ADMA) {
2664                 /*
2665                  * We need to allocate descriptors for all sg entries
2666                  * (128) and potentially one alignment transfer for
2667                  * each of those entries.
2668                  */
2669                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2670                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2671                 if (!host->adma_desc || !host->align_buffer) {
2672                         kfree(host->adma_desc);
2673                         kfree(host->align_buffer);
2674                         pr_warning("%s: Unable to allocate ADMA "
2675                                 "buffers. Falling back to standard DMA.\n",
2676                                 mmc_hostname(mmc));
2677                         host->flags &= ~SDHCI_USE_ADMA;
2678                 }
2679         }
2680
2681         /*
2682          * If we use DMA, then it's up to the caller to set the DMA
2683          * mask, but PIO does not need the hw shim so we set a new
2684          * mask here in that case.
2685          */
2686         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2687                 host->dma_mask = DMA_BIT_MASK(64);
2688                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2689         }
2690
2691         if (host->version >= SDHCI_SPEC_300)
2692                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2693                         >> SDHCI_CLOCK_BASE_SHIFT;
2694         else
2695                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2696                         >> SDHCI_CLOCK_BASE_SHIFT;
2697
2698         host->max_clk *= 1000000;
2699         if (host->max_clk == 0 || host->quirks &
2700                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2701                 if (!host->ops->get_max_clock) {
2702                         pr_err("%s: Hardware doesn't specify base clock "
2703                                "frequency.\n", mmc_hostname(mmc));
2704                         return -ENODEV;
2705                 }
2706                 host->max_clk = host->ops->get_max_clock(host);
2707         }
2708
2709         /*
2710          * In case of Host Controller v3.00, find out whether clock
2711          * multiplier is supported.
2712          */
2713         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2714                         SDHCI_CLOCK_MUL_SHIFT;
2715
2716         /*
2717          * In case the value in Clock Multiplier is 0, then programmable
2718          * clock mode is not supported, otherwise the actual clock
2719          * multiplier is one more than the value of Clock Multiplier
2720          * in the Capabilities Register.
2721          */
2722         if (host->clk_mul)
2723                 host->clk_mul += 1;
2724
2725         /*
2726          * Set host parameters.
2727          */
2728         mmc->ops = &sdhci_ops;
2729         mmc->f_max = host->max_clk;
2730         if (host->ops->get_min_clock)
2731                 mmc->f_min = host->ops->get_min_clock(host);
2732         else if (host->version >= SDHCI_SPEC_300) {
2733                 if (host->clk_mul) {
2734                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2735                         mmc->f_max = host->max_clk * host->clk_mul;
2736                 } else
2737                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2738         } else
2739                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2740
2741         host->timeout_clk =
2742                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2743         if (host->timeout_clk == 0) {
2744                 if (host->ops->get_timeout_clock) {
2745                         host->timeout_clk = host->ops->get_timeout_clock(host);
2746                 } else if (!(host->quirks &
2747                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2748                         pr_err("%s: Hardware doesn't specify timeout clock "
2749                                "frequency.\n", mmc_hostname(mmc));
2750                         return -ENODEV;
2751                 }
2752         }
2753         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2754                 host->timeout_clk *= 1000;
2755
2756         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2757                 host->timeout_clk = mmc->f_max / 1000;
2758
2759         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2760
2761         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2762
2763         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2764                 host->flags |= SDHCI_AUTO_CMD12;
2765
2766         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2767         if ((host->version >= SDHCI_SPEC_300) &&
2768             ((host->flags & SDHCI_USE_ADMA) ||
2769              !(host->flags & SDHCI_USE_SDMA))) {
2770                 host->flags |= SDHCI_AUTO_CMD23;
2771                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2772         } else {
2773                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2774         }
2775
2776         /*
2777          * A controller may support 8-bit width, but the board itself
2778          * might not have the pins brought out.  Boards that support
2779          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2780          * their platform code before calling sdhci_add_host(), and we
2781          * won't assume 8-bit width for hosts without that CAP.
2782          */
2783         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2784                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2785
2786         if (caps[0] & SDHCI_CAN_DO_HISPD)
2787                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2788
2789         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2790             mmc_card_is_removable(mmc))
2791                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2792
2793         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2794         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2795                        SDHCI_SUPPORT_DDR50))
2796                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2797
2798         /* SDR104 supports also implies SDR50 support */
2799         if (caps[1] & SDHCI_SUPPORT_SDR104)
2800                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2801         else if (caps[1] & SDHCI_SUPPORT_SDR50)
2802                 mmc->caps |= MMC_CAP_UHS_SDR50;
2803
2804         if (caps[1] & SDHCI_SUPPORT_DDR50)
2805                 mmc->caps |= MMC_CAP_UHS_DDR50;
2806
2807         /* Does the host need tuning for SDR50? */
2808         if (caps[1] & SDHCI_USE_SDR50_TUNING)
2809                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
2810
2811         /* Does the host need tuning for HS200? */
2812         if (mmc->caps2 & MMC_CAP2_HS200)
2813                 host->flags |= SDHCI_HS200_NEEDS_TUNING;
2814
2815         /* Driver Type(s) (A, C, D) supported by the host */
2816         if (caps[1] & SDHCI_DRIVER_TYPE_A)
2817                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
2818         if (caps[1] & SDHCI_DRIVER_TYPE_C)
2819                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
2820         if (caps[1] & SDHCI_DRIVER_TYPE_D)
2821                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
2822
2823         /*
2824          * If Power Off Notify capability is enabled by the host,
2825          * set notify to short power off notify timeout value.
2826          */
2827         if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
2828                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
2829         else
2830                 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
2831
2832         /* Initial value for re-tuning timer count */
2833         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
2834                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
2835
2836         /*
2837          * In case Re-tuning Timer is not disabled, the actual value of
2838          * re-tuning timer will be 2 ^ (n - 1).
2839          */
2840         if (host->tuning_count)
2841                 host->tuning_count = 1 << (host->tuning_count - 1);
2842
2843         /* Re-tuning mode supported by the Host Controller */
2844         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
2845                              SDHCI_RETUNING_MODE_SHIFT;
2846
2847         ocr_avail = 0;
2848
2849         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
2850         if (IS_ERR(host->vmmc)) {
2851                 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
2852                 host->vmmc = NULL;
2853         }
2854
2855 #ifdef CONFIG_REGULATOR
2856         if (host->vmmc) {
2857                 ret = regulator_is_supported_voltage(host->vmmc, 3300000,
2858                         3300000);
2859                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
2860                         caps[0] &= ~SDHCI_CAN_VDD_330;
2861                 ret = regulator_is_supported_voltage(host->vmmc, 3000000,
2862                         3000000);
2863                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
2864                         caps[0] &= ~SDHCI_CAN_VDD_300;
2865                 ret = regulator_is_supported_voltage(host->vmmc, 1800000,
2866                         1800000);
2867                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
2868                         caps[0] &= ~SDHCI_CAN_VDD_180;
2869         }
2870 #endif /* CONFIG_REGULATOR */
2871
2872         /*
2873          * According to SD Host Controller spec v3.00, if the Host System
2874          * can afford more than 150mA, Host Driver should set XPC to 1. Also
2875          * the value is meaningful only if Voltage Support in the Capabilities
2876          * register is set. The actual current value is 4 times the register
2877          * value.
2878          */
2879         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
2880         if (!max_current_caps && host->vmmc) {
2881                 u32 curr = regulator_get_current_limit(host->vmmc);
2882                 if (curr > 0) {
2883
2884                         /* convert to SDHCI_MAX_CURRENT format */
2885                         curr = curr/1000;  /* convert to mA */
2886                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
2887
2888                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
2889                         max_current_caps =
2890                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
2891                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
2892                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
2893                 }
2894         }
2895
2896         if (caps[0] & SDHCI_CAN_VDD_330) {
2897                 int max_current_330;
2898
2899                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
2900
2901                 max_current_330 = ((max_current_caps &
2902                                    SDHCI_MAX_CURRENT_330_MASK) >>
2903                                    SDHCI_MAX_CURRENT_330_SHIFT) *
2904                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2905
2906                 if (max_current_330 > 150)
2907                         mmc->caps |= MMC_CAP_SET_XPC_330;
2908         }
2909         if (caps[0] & SDHCI_CAN_VDD_300) {
2910                 int max_current_300;
2911
2912                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
2913
2914                 max_current_300 = ((max_current_caps &
2915                                    SDHCI_MAX_CURRENT_300_MASK) >>
2916                                    SDHCI_MAX_CURRENT_300_SHIFT) *
2917                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2918
2919                 if (max_current_300 > 150)
2920                         mmc->caps |= MMC_CAP_SET_XPC_300;
2921         }
2922         if (caps[0] & SDHCI_CAN_VDD_180) {
2923                 int max_current_180;
2924
2925                 ocr_avail |= MMC_VDD_165_195;
2926
2927                 max_current_180 = ((max_current_caps &
2928                                    SDHCI_MAX_CURRENT_180_MASK) >>
2929                                    SDHCI_MAX_CURRENT_180_SHIFT) *
2930                                    SDHCI_MAX_CURRENT_MULTIPLIER;
2931
2932                 if (max_current_180 > 150)
2933                         mmc->caps |= MMC_CAP_SET_XPC_180;
2934
2935                 /* Maximum current capabilities of the host at 1.8V */
2936                 if (max_current_180 >= 800)
2937                         mmc->caps |= MMC_CAP_MAX_CURRENT_800;
2938                 else if (max_current_180 >= 600)
2939                         mmc->caps |= MMC_CAP_MAX_CURRENT_600;
2940                 else if (max_current_180 >= 400)
2941                         mmc->caps |= MMC_CAP_MAX_CURRENT_400;
2942                 else if (max_current_180 >= 200)
2943                         mmc->caps |= MMC_CAP_MAX_CURRENT_200;
2944         }
2945
2946         mmc->ocr_avail = ocr_avail;
2947         mmc->ocr_avail_sdio = ocr_avail;
2948         if (host->ocr_avail_sdio)
2949                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
2950         mmc->ocr_avail_sd = ocr_avail;
2951         if (host->ocr_avail_sd)
2952                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
2953         else /* normal SD controllers don't support 1.8V */
2954                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
2955         mmc->ocr_avail_mmc = ocr_avail;
2956         if (host->ocr_avail_mmc)
2957                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
2958
2959         if (mmc->ocr_avail == 0) {
2960                 pr_err("%s: Hardware doesn't report any "
2961                         "support voltages.\n", mmc_hostname(mmc));
2962                 return -ENODEV;
2963         }
2964
2965         spin_lock_init(&host->lock);
2966
2967         /*
2968          * Maximum number of segments. Depends on if the hardware
2969          * can do scatter/gather or not.
2970          */
2971         if (host->flags & SDHCI_USE_ADMA)
2972                 mmc->max_segs = 128;
2973         else if (host->flags & SDHCI_USE_SDMA)
2974                 mmc->max_segs = 1;
2975         else /* PIO */
2976                 mmc->max_segs = 128;
2977
2978         /*
2979          * Maximum number of sectors in one transfer. Limited by DMA boundary
2980          * size (512KiB).
2981          */
2982         mmc->max_req_size = 524288;
2983
2984         /*
2985          * Maximum segment size. Could be one segment with the maximum number
2986          * of bytes. When doing hardware scatter/gather, each entry cannot
2987          * be larger than 64 KiB though.
2988          */
2989         if (host->flags & SDHCI_USE_ADMA) {
2990                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
2991                         mmc->max_seg_size = 65535;
2992                 else
2993                         mmc->max_seg_size = 65536;
2994         } else {
2995                 mmc->max_seg_size = mmc->max_req_size;
2996         }
2997
2998         /*
2999          * Maximum block size. This varies from controller to controller and
3000          * is specified in the capabilities register.
3001          */
3002         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3003                 mmc->max_blk_size = 2;
3004         } else {
3005                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3006                                 SDHCI_MAX_BLOCK_SHIFT;
3007                 if (mmc->max_blk_size >= 3) {
3008                         pr_warning("%s: Invalid maximum block size, "
3009                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3010                         mmc->max_blk_size = 0;
3011                 }
3012         }
3013
3014         mmc->max_blk_size = 512 << mmc->max_blk_size;
3015
3016         /*
3017          * Maximum block count.
3018          */
3019         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3020
3021         /*
3022          * Init tasklets.
3023          */
3024         tasklet_init(&host->card_tasklet,
3025                 sdhci_tasklet_card, (unsigned long)host);
3026         tasklet_init(&host->finish_tasklet,
3027                 sdhci_tasklet_finish, (unsigned long)host);
3028
3029         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3030
3031         if (host->version >= SDHCI_SPEC_300) {
3032                 init_waitqueue_head(&host->buf_ready_int);
3033
3034                 /* Initialize re-tuning timer */
3035                 init_timer(&host->tuning_timer);
3036                 host->tuning_timer.data = (unsigned long)host;
3037                 host->tuning_timer.function = sdhci_tuning_timer;
3038         }
3039
3040         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3041                 mmc_hostname(mmc), host);
3042         if (ret) {
3043                 pr_err("%s: Failed to request IRQ %d: %d\n",
3044                        mmc_hostname(mmc), host->irq, ret);
3045                 goto untasklet;
3046         }
3047
3048         sdhci_init(host, 0);
3049
3050 #ifdef CONFIG_MMC_DEBUG
3051         sdhci_dumpregs(host);
3052 #endif
3053
3054 #ifdef SDHCI_USE_LEDS_CLASS
3055         snprintf(host->led_name, sizeof(host->led_name),
3056                 "%s::", mmc_hostname(mmc));
3057         host->led.name = host->led_name;
3058         host->led.brightness = LED_OFF;
3059         host->led.default_trigger = mmc_hostname(mmc);
3060         host->led.brightness_set = sdhci_led_control;
3061
3062         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3063         if (ret) {
3064                 pr_err("%s: Failed to register LED device: %d\n",
3065                        mmc_hostname(mmc), ret);
3066                 goto reset;
3067         }
3068 #endif
3069
3070         mmiowb();
3071
3072         mmc_add_host(mmc);
3073
3074         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3075                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3076                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3077                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3078
3079         sdhci_enable_card_detection(host);
3080
3081         return 0;
3082
3083 #ifdef SDHCI_USE_LEDS_CLASS
3084 reset:
3085         sdhci_reset(host, SDHCI_RESET_ALL);
3086         free_irq(host->irq, host);
3087 #endif
3088 untasklet:
3089         tasklet_kill(&host->card_tasklet);
3090         tasklet_kill(&host->finish_tasklet);
3091
3092         return ret;
3093 }
3094
3095 EXPORT_SYMBOL_GPL(sdhci_add_host);
3096
3097 void sdhci_remove_host(struct sdhci_host *host, int dead)
3098 {
3099         unsigned long flags;
3100
3101         if (dead) {
3102                 spin_lock_irqsave(&host->lock, flags);
3103
3104                 host->flags |= SDHCI_DEVICE_DEAD;
3105
3106                 if (host->mrq) {
3107                         pr_err("%s: Controller removed during "
3108                                 " transfer!\n", mmc_hostname(host->mmc));
3109
3110                         host->mrq->cmd->error = -ENOMEDIUM;
3111                         tasklet_schedule(&host->finish_tasklet);
3112                 }
3113
3114                 spin_unlock_irqrestore(&host->lock, flags);
3115         }
3116
3117         sdhci_disable_card_detection(host);
3118
3119         mmc_remove_host(host->mmc);
3120
3121 #ifdef SDHCI_USE_LEDS_CLASS
3122         led_classdev_unregister(&host->led);
3123 #endif
3124
3125         if (!dead)
3126                 sdhci_reset(host, SDHCI_RESET_ALL);
3127
3128         free_irq(host->irq, host);
3129
3130         del_timer_sync(&host->timer);
3131         if (host->version >= SDHCI_SPEC_300)
3132                 del_timer_sync(&host->tuning_timer);
3133
3134         tasklet_kill(&host->card_tasklet);
3135         tasklet_kill(&host->finish_tasklet);
3136
3137         if (host->vmmc)
3138                 regulator_put(host->vmmc);
3139
3140         kfree(host->adma_desc);
3141         kfree(host->align_buffer);
3142
3143         host->adma_desc = NULL;
3144         host->align_buffer = NULL;
3145 }
3146
3147 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3148
3149 void sdhci_free_host(struct sdhci_host *host)
3150 {
3151         mmc_free_host(host->mmc);
3152 }
3153
3154 EXPORT_SYMBOL_GPL(sdhci_free_host);
3155
3156 /*****************************************************************************\
3157  *                                                                           *
3158  * Driver init/exit                                                          *
3159  *                                                                           *
3160 \*****************************************************************************/
3161
3162 static int __init sdhci_drv_init(void)
3163 {
3164         pr_info(DRIVER_NAME
3165                 ": Secure Digital Host Controller Interface driver\n");
3166         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3167
3168         return 0;
3169 }
3170
3171 static void __exit sdhci_drv_exit(void)
3172 {
3173 }
3174
3175 module_init(sdhci_drv_init);
3176 module_exit(sdhci_drv_exit);
3177
3178 module_param(debug_quirks, uint, 0444);
3179 module_param(debug_quirks2, uint, 0444);
3180
3181 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3182 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3183 MODULE_LICENSE("GPL");
3184
3185 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3186 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");