drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/sdio.h>
  32 #include <linux/mmc/slot-gpio.h>
  33
  34 #include "sdhci.h"
  35
  36 #define DRIVER_NAME "sdhci"
  37
  38 #define DBG(f, x...) \
  39         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  40
  41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  42         defined(CONFIG_MMC_SDHCI_MODULE))
  43 #define SDHCI_USE_LEDS_CLASS
  44 #endif
  45
  46 #define MAX_TUNING_LOOP 40
  47
  48 static unsigned int debug_quirks = 0;
  49 static unsigned int debug_quirks2;
  50
  51 static void sdhci_finish_data(struct sdhci_host *);
  52
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
  57                                         struct mmc_data *data);
  58 static int sdhci_do_get_cd(struct sdhci_host *host);
  59
  60 #ifdef CONFIG_PM
  61 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  62 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  64 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  65 #else
  66 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  67 {
  68         return 0;
  69 }
  70 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  71 {
  72         return 0;
  73 }
  74 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  75 {
  76 }
  77 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  78 {
  79 }
  80 #endif
  81
  82 static void sdhci_dumpregs(struct sdhci_host *host)
  83 {
  84         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  85                 mmc_hostname(host->mmc));
  86
  87         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  88                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  89                 sdhci_readw(host, SDHCI_HOST_VERSION));
  90         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  91                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  92                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  93         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  94                 sdhci_readl(host, SDHCI_ARGUMENT),
  95                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  96         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  97                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  98                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  99         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
 100                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 101                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 102         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 103                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 104                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 105         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 106                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 107                 sdhci_readl(host, SDHCI_INT_STATUS));
 108         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 109                 sdhci_readl(host, SDHCI_INT_ENABLE),
 110                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 111         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 112                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 113                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 114         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 115                 sdhci_readl(host, SDHCI_CAPABILITIES),
 116                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 117         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 118                 sdhci_readw(host, SDHCI_COMMAND),
 119                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 120         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 121                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 122
 123         if (host->flags & SDHCI_USE_ADMA) {
 124                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 125                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
 126                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 127                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
 128                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 129                 else
 130                         pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 131                                  readl(host->ioaddr + SDHCI_ADMA_ERROR),
 132                                  readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 133         }
 134
 135         pr_debug(DRIVER_NAME ": ===========================================\n");
 136 }
 137
 138 /*****************************************************************************\
 139  *                                                                           *
 140  * Low level functions                                                       *
 141  *                                                                           *
 142 \*****************************************************************************/
 143
 144 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 145 {
 146         u32 present;
 147
 148         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 149             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 150                 return;
 151
 152         if (enable) {
 153                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 154                                       SDHCI_CARD_PRESENT;
 155
 156                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 157                                        SDHCI_INT_CARD_INSERT;
 158         } else {
 159                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 160         }
 161
 162         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 163         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 164 }
 165
 166 static void sdhci_enable_card_detection(struct sdhci_host *host)
 167 {
 168         sdhci_set_card_detection(host, true);
 169 }
 170
 171 static void sdhci_disable_card_detection(struct sdhci_host *host)
 172 {
 173         sdhci_set_card_detection(host, false);
 174 }
 175
 176 void sdhci_reset(struct sdhci_host *host, u8 mask)
 177 {
 178         unsigned long timeout;
 179
 180         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 181
 182         if (mask & SDHCI_RESET_ALL) {
 183                 host->clock = 0;
 184                 /* Reset-all turns off SD Bus Power */
 185                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 186                         sdhci_runtime_pm_bus_off(host);
 187         }
 188
 189         /* Wait max 100 ms */
 190         timeout = 100;
 191
 192         /* hw clears the bit when it's done */
 193         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 194                 if (timeout == 0) {
 195                         pr_err("%s: Reset 0x%x never completed.\n",
 196                                 mmc_hostname(host->mmc), (int)mask);
 197                         sdhci_dumpregs(host);
 198                         return;
 199                 }
 200                 timeout--;
 201                 mdelay(1);
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(sdhci_reset);
 205
 206 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 207 {
 208         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 209                 if (!sdhci_do_get_cd(host))
 210                         return;
 211         }
 212
 213         host->ops->reset(host, mask);
 214
 215         if (mask & SDHCI_RESET_ALL) {
 216                 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 217                         if (host->ops->enable_dma)
 218                                 host->ops->enable_dma(host);
 219                 }
 220
 221                 /* Resetting the controller clears many */
 222                 host->preset_enabled = false;
 223         }
 224 }
 225
 226 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 227
 228 static void sdhci_init(struct sdhci_host *host, int soft)
 229 {
 230         if (soft)
 231                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 232         else
 233                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 234
 235         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 236                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 237                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 238                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 239                     SDHCI_INT_RESPONSE;
 240
 241         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 242         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 243
 244         if (soft) {
 245                 /* force clock reconfiguration */
 246                 host->clock = 0;
 247                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 248         }
 249 }
 250
 251 static void sdhci_reinit(struct sdhci_host *host)
 252 {
 253         sdhci_init(host, 0);
 254         sdhci_enable_card_detection(host);
 255 }
 256
 257 static void sdhci_activate_led(struct sdhci_host *host)
 258 {
 259         u8 ctrl;
 260
 261         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 262         ctrl |= SDHCI_CTRL_LED;
 263         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 264 }
 265
 266 static void sdhci_deactivate_led(struct sdhci_host *host)
 267 {
 268         u8 ctrl;
 269
 270         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 271         ctrl &= ~SDHCI_CTRL_LED;
 272         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 273 }
 274
 275 #ifdef SDHCI_USE_LEDS_CLASS
 276 static void sdhci_led_control(struct led_classdev *led,
 277         enum led_brightness brightness)
 278 {
 279         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 280         unsigned long flags;
 281
 282         spin_lock_irqsave(&host->lock, flags);
 283
 284         if (host->runtime_suspended)
 285                 goto out;
 286
 287         if (brightness == LED_OFF)
 288                 sdhci_deactivate_led(host);
 289         else
 290                 sdhci_activate_led(host);
 291 out:
 292         spin_unlock_irqrestore(&host->lock, flags);
 293 }
 294 #endif
 295
 296 /*****************************************************************************\
 297  *                                                                           *
 298  * Core functions                                                            *
 299  *                                                                           *
 300 \*****************************************************************************/
 301
 302 static void sdhci_read_block_pio(struct sdhci_host *host)
 303 {
 304         unsigned long flags;
 305         size_t blksize, len, chunk;
 306         u32 uninitialized_var(scratch);
 307         u8 *buf;
 308
 309         DBG("PIO reading\n");
 310
 311         blksize = host->data->blksz;
 312         chunk = 0;
 313
 314         local_irq_save(flags);
 315
 316         while (blksize) {
 317                 BUG_ON(!sg_miter_next(&host->sg_miter));
 318
 319                 len = min(host->sg_miter.length, blksize);
 320
 321                 blksize -= len;
 322                 host->sg_miter.consumed = len;
 323
 324                 buf = host->sg_miter.addr;
 325
 326                 while (len) {
 327                         if (chunk == 0) {
 328                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 329                                 chunk = 4;
 330                         }
 331
 332                         *buf = scratch & 0xFF;
 333
 334                         buf++;
 335                         scratch >>= 8;
 336                         chunk--;
 337                         len--;
 338                 }
 339         }
 340
 341         sg_miter_stop(&host->sg_miter);
 342
 343         local_irq_restore(flags);
 344 }
 345
 346 static void sdhci_write_block_pio(struct sdhci_host *host)
 347 {
 348         unsigned long flags;
 349         size_t blksize, len, chunk;
 350         u32 scratch;
 351         u8 *buf;
 352
 353         DBG("PIO writing\n");
 354
 355         blksize = host->data->blksz;
 356         chunk = 0;
 357         scratch = 0;
 358
 359         local_irq_save(flags);
 360
 361         while (blksize) {
 362                 BUG_ON(!sg_miter_next(&host->sg_miter));
 363
 364                 len = min(host->sg_miter.length, blksize);
 365
 366                 blksize -= len;
 367                 host->sg_miter.consumed = len;
 368
 369                 buf = host->sg_miter.addr;
 370
 371                 while (len) {
 372                         scratch |= (u32)*buf << (chunk * 8);
 373
 374                         buf++;
 375                         chunk++;
 376                         len--;
 377
 378                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 379                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 380                                 chunk = 0;
 381                                 scratch = 0;
 382                         }
 383                 }
 384         }
 385
 386         sg_miter_stop(&host->sg_miter);
 387
 388         local_irq_restore(flags);
 389 }
 390
 391 static void sdhci_transfer_pio(struct sdhci_host *host)
 392 {
 393         u32 mask;
 394
 395         BUG_ON(!host->data);
 396
 397         if (host->blocks == 0)
 398                 return;
 399
 400         if (host->data->flags & MMC_DATA_READ)
 401                 mask = SDHCI_DATA_AVAILABLE;
 402         else
 403                 mask = SDHCI_SPACE_AVAILABLE;
 404
 405         /*
 406          * Some controllers (JMicron JMB38x) mess up the buffer bits
 407          * for transfers < 4 bytes. As long as it is just one block,
 408          * we can ignore the bits.
 409          */
 410         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 411                 (host->data->blocks == 1))
 412                 mask = ~0;
 413
 414         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 415                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 416                         udelay(100);
 417
 418                 if (host->data->flags & MMC_DATA_READ)
 419                         sdhci_read_block_pio(host);
 420                 else
 421                         sdhci_write_block_pio(host);
 422
 423                 host->blocks--;
 424                 if (host->blocks == 0)
 425                         break;
 426         }
 427
 428         DBG("PIO transfer complete.\n");
 429 }
 430
 431 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 432 {
 433         local_irq_save(*flags);
 434         return kmap_atomic(sg_page(sg)) + sg->offset;
 435 }
 436
 437 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 438 {
 439         kunmap_atomic(buffer);
 440         local_irq_restore(*flags);
 441 }
 442
 443 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
 444                                   dma_addr_t addr, int len, unsigned cmd)
 445 {
 446         struct sdhci_adma2_64_desc *dma_desc = desc;
 447
 448         /* 32-bit and 64-bit descriptors have these members in same position */
 449         dma_desc->cmd = cpu_to_le16(cmd);
 450         dma_desc->len = cpu_to_le16(len);
 451         dma_desc->addr_lo = cpu_to_le32((u32)addr);
 452
 453         if (host->flags & SDHCI_USE_64_BIT_DMA)
 454                 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
 455 }
 456
 457 static void sdhci_adma_mark_end(void *desc)
 458 {
 459         struct sdhci_adma2_64_desc *dma_desc = desc;
 460
 461         /* 32-bit and 64-bit descriptors have 'cmd' in same position */
 462         dma_desc->cmd |= cpu_to_le16(ADMA2_END);
 463 }
 464
 465 static int sdhci_adma_table_pre(struct sdhci_host *host,
 466         struct mmc_data *data)
 467 {
 468         int direction;
 469
 470         void *desc;
 471         void *align;
 472         dma_addr_t addr;
 473         dma_addr_t align_addr;
 474         int len, offset;
 475
 476         struct scatterlist *sg;
 477         int i;
 478         char *buffer;
 479         unsigned long flags;
 480
 481         /*
 482          * The spec does not specify endianness of descriptor table.
 483          * We currently guess that it is LE.
 484          */
 485
 486         if (data->flags & MMC_DATA_READ)
 487                 direction = DMA_FROM_DEVICE;
 488         else
 489                 direction = DMA_TO_DEVICE;
 490
 491         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 492                 host->align_buffer, host->align_buffer_sz, direction);
 493         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 494                 goto fail;
 495         BUG_ON(host->align_addr & SDHCI_ADMA2_MASK);
 496
 497         host->sg_count = sdhci_pre_dma_transfer(host, data);
 498         if (host->sg_count < 0)
 499                 goto unmap_align;
 500
 501         desc = host->adma_table;
 502         align = host->align_buffer;
 503
 504         align_addr = host->align_addr;
 505
 506         for_each_sg(data->sg, sg, host->sg_count, i) {
 507                 addr = sg_dma_address(sg);
 508                 len = sg_dma_len(sg);
 509
 510                 /*
 511                  * The SDHCI specification states that ADMA
 512                  * addresses must be 32-bit aligned. If they
 513                  * aren't, then we use a bounce buffer for
 514                  * the (up to three) bytes that screw up the
 515                  * alignment.
 516                  */
 517                 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
 518                          SDHCI_ADMA2_MASK;
 519                 if (offset) {
 520                         if (data->flags & MMC_DATA_WRITE) {
 521                                 buffer = sdhci_kmap_atomic(sg, &flags);
 522                                 memcpy(align, buffer, offset);
 523                                 sdhci_kunmap_atomic(buffer, &flags);
 524                         }
 525
 526                         /* tran, valid */
 527                         sdhci_adma_write_desc(host, desc, align_addr, offset,
 528                                               ADMA2_TRAN_VALID);
 529
 530                         BUG_ON(offset > 65536);
 531
 532                         align += SDHCI_ADMA2_ALIGN;
 533                         align_addr += SDHCI_ADMA2_ALIGN;
 534
 535                         desc += host->desc_sz;
 536
 537                         addr += offset;
 538                         len -= offset;
 539                 }
 540
 541                 BUG_ON(len > 65536);
 542
 543                 if (len) {
 544                         /* tran, valid */
 545                         sdhci_adma_write_desc(host, desc, addr, len,
 546                                               ADMA2_TRAN_VALID);
 547                         desc += host->desc_sz;
 548                 }
 549
 550                 /*
 551                  * If this triggers then we have a calculation bug
 552                  * somewhere. :/
 553                  */
 554                 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
 555         }
 556
 557         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 558                 /*
 559                 * Mark the last descriptor as the terminating descriptor
 560                 */
 561                 if (desc != host->adma_table) {
 562                         desc -= host->desc_sz;
 563                         sdhci_adma_mark_end(desc);
 564                 }
 565         } else {
 566                 /*
 567                 * Add a terminating entry.
 568                 */
 569
 570                 /* nop, end, valid */
 571                 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
 572         }
 573
 574         /*
 575          * Resync align buffer as we might have changed it.
 576          */
 577         if (data->flags & MMC_DATA_WRITE) {
 578                 dma_sync_single_for_device(mmc_dev(host->mmc),
 579                         host->align_addr, host->align_buffer_sz, direction);
 580         }
 581
 582         return 0;
 583
 584 unmap_align:
 585         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 586                 host->align_buffer_sz, direction);
 587 fail:
 588         return -EINVAL;
 589 }
 590
 591 static void sdhci_adma_table_post(struct sdhci_host *host,
 592         struct mmc_data *data)
 593 {
 594         int direction;
 595
 596         struct scatterlist *sg;
 597         int i, size;
 598         void *align;
 599         char *buffer;
 600         unsigned long flags;
 601         bool has_unaligned;
 602
 603         if (data->flags & MMC_DATA_READ)
 604                 direction = DMA_FROM_DEVICE;
 605         else
 606                 direction = DMA_TO_DEVICE;
 607
 608         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 609                 host->align_buffer_sz, direction);
 610
 611         /* Do a quick scan of the SG list for any unaligned mappings */
 612         has_unaligned = false;
 613         for_each_sg(data->sg, sg, host->sg_count, i)
 614                 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 615                         has_unaligned = true;
 616                         break;
 617                 }
 618
 619         if (has_unaligned && data->flags & MMC_DATA_READ) {
 620                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 621                         data->sg_len, direction);
 622
 623                 align = host->align_buffer;
 624
 625                 for_each_sg(data->sg, sg, host->sg_count, i) {
 626                         if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
 627                                 size = SDHCI_ADMA2_ALIGN -
 628                                        (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
 629
 630                                 buffer = sdhci_kmap_atomic(sg, &flags);
 631                                 memcpy(buffer, align, size);
 632                                 sdhci_kunmap_atomic(buffer, &flags);
 633
 634                                 align += SDHCI_ADMA2_ALIGN;
 635                         }
 636                 }
 637         }
 638
 639         if (data->host_cookie == COOKIE_MAPPED) {
 640                 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 641                         data->sg_len, direction);
 642                 data->host_cookie = COOKIE_UNMAPPED;
 643         }
 644 }
 645
 646 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 647 {
 648         u8 count;
 649         struct mmc_data *data = cmd->data;
 650         unsigned target_timeout, current_timeout;
 651
 652         /*
 653          * If the host controller provides us with an incorrect timeout
 654          * value, just skip the check and use 0xE.  The hardware may take
 655          * longer to time out, but that's much better than having a too-short
 656          * timeout value.
 657          */
 658         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 659                 return 0xE;
 660
 661         /* Unspecified timeout, assume max */
 662         if (!data && !cmd->busy_timeout)
 663                 return 0xE;
 664
 665         /* timeout in us */
 666         if (!data)
 667                 target_timeout = cmd->busy_timeout * 1000;
 668         else {
 669                 target_timeout = data->timeout_ns / 1000;
 670                 if (host->clock)
 671                         target_timeout += data->timeout_clks / host->clock;
 672         }
 673
 674         /*
 675          * Figure out needed cycles.
 676          * We do this in steps in order to fit inside a 32 bit int.
 677          * The first step is the minimum timeout, which will have a
 678          * minimum resolution of 6 bits:
 679          * (1) 2^13*1000 > 2^22,
 680          * (2) host->timeout_clk < 2^16
 681          *     =>
 682          *     (1) / (2) > 2^6
 683          */
 684         count = 0;
 685         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 686         while (current_timeout < target_timeout) {
 687                 count++;
 688                 current_timeout <<= 1;
 689                 if (count >= 0xF)
 690                         break;
 691         }
 692
 693         if (count >= 0xF) {
 694                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 695                     mmc_hostname(host->mmc), count, cmd->opcode);
 696                 count = 0xE;
 697         }
 698
 699         return count;
 700 }
 701
 702 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 703 {
 704         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 705         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 706
 707         if (host->flags & SDHCI_REQ_USE_DMA)
 708                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 709         else
 710                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 711
 712         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 713         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 714 }
 715
 716 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 717 {
 718         u8 count;
 719
 720         if (host->ops->set_timeout) {
 721                 host->ops->set_timeout(host, cmd);
 722         } else {
 723                 count = sdhci_calc_timeout(host, cmd);
 724                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 725         }
 726 }
 727
 728 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 729 {
 730         u8 ctrl;
 731         struct mmc_data *data = cmd->data;
 732         int ret;
 733
 734         WARN_ON(host->data);
 735
 736         if (data || (cmd->flags & MMC_RSP_BUSY))
 737                 sdhci_set_timeout(host, cmd);
 738
 739         if (!data)
 740                 return;
 741
 742         /* Sanity checks */
 743         BUG_ON(data->blksz * data->blocks > 524288);
 744         BUG_ON(data->blksz > host->mmc->max_blk_size);
 745         BUG_ON(data->blocks > 65535);
 746
 747         host->data = data;
 748         host->data_early = 0;
 749         host->data->bytes_xfered = 0;
 750
 751         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 752                 host->flags |= SDHCI_REQ_USE_DMA;
 753
 754         /*
 755          * FIXME: This doesn't account for merging when mapping the
 756          * scatterlist.
 757          */
 758         if (host->flags & SDHCI_REQ_USE_DMA) {
 759                 int broken, i;
 760                 struct scatterlist *sg;
 761
 762                 broken = 0;
 763                 if (host->flags & SDHCI_USE_ADMA) {
 764                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 765                                 broken = 1;
 766                 } else {
 767                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 768                                 broken = 1;
 769                 }
 770
 771                 if (unlikely(broken)) {
 772                         for_each_sg(data->sg, sg, data->sg_len, i) {
 773                                 if (sg->length & 0x3) {
 774                                         DBG("Reverting to PIO because of transfer size (%d)\n",
 775                                                 sg->length);
 776                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 777                                         break;
 778                                 }
 779                         }
 780                 }
 781         }
 782
 783         /*
 784          * The assumption here being that alignment is the same after
 785          * translation to device address space.
 786          */
 787         if (host->flags & SDHCI_REQ_USE_DMA) {
 788                 int broken, i;
 789                 struct scatterlist *sg;
 790
 791                 broken = 0;
 792                 if (host->flags & SDHCI_USE_ADMA) {
 793                         /*
 794                          * As we use 3 byte chunks to work around
 795                          * alignment problems, we need to check this
 796                          * quirk.
 797                          */
 798                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 799                                 broken = 1;
 800                 } else {
 801                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 802                                 broken = 1;
 803                 }
 804
 805                 if (unlikely(broken)) {
 806                         for_each_sg(data->sg, sg, data->sg_len, i) {
 807                                 if (sg->offset & 0x3) {
 808                                         DBG("Reverting to PIO because of bad alignment\n");
 809                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 810                                         break;
 811                                 }
 812                         }
 813                 }
 814         }
 815
 816         if (host->flags & SDHCI_REQ_USE_DMA) {
 817                 if (host->flags & SDHCI_USE_ADMA) {
 818                         ret = sdhci_adma_table_pre(host, data);
 819                         if (ret) {
 820                                 /*
 821                                  * This only happens when someone fed
 822                                  * us an invalid request.
 823                                  */
 824                                 WARN_ON(1);
 825                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 826                         } else {
 827                                 sdhci_writel(host, host->adma_addr,
 828                                         SDHCI_ADMA_ADDRESS);
 829                                 if (host->flags & SDHCI_USE_64_BIT_DMA)
 830                                         sdhci_writel(host,
 831                                                      (u64)host->adma_addr >> 32,
 832                                                      SDHCI_ADMA_ADDRESS_HI);
 833                         }
 834                 } else {
 835                         int sg_cnt;
 836
 837                         sg_cnt = sdhci_pre_dma_transfer(host, data);
 838                         if (sg_cnt <= 0) {
 839                                 /*
 840                                  * This only happens when someone fed
 841                                  * us an invalid request.
 842                                  */
 843                                 WARN_ON(1);
 844                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 845                         } else {
 846                                 WARN_ON(sg_cnt != 1);
 847                                 sdhci_writel(host, sg_dma_address(data->sg),
 848                                         SDHCI_DMA_ADDRESS);
 849                         }
 850                 }
 851         }
 852
 853         /*
 854          * Always adjust the DMA selection as some controllers
 855          * (e.g. JMicron) can't do PIO properly when the selection
 856          * is ADMA.
 857          */
 858         if (host->version >= SDHCI_SPEC_200) {
 859                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 860                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 861                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 862                         (host->flags & SDHCI_USE_ADMA)) {
 863                         if (host->flags & SDHCI_USE_64_BIT_DMA)
 864                                 ctrl |= SDHCI_CTRL_ADMA64;
 865                         else
 866                                 ctrl |= SDHCI_CTRL_ADMA32;
 867                 } else {
 868                         ctrl |= SDHCI_CTRL_SDMA;
 869                 }
 870                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 871         }
 872
 873         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 874                 int flags;
 875
 876                 flags = SG_MITER_ATOMIC;
 877                 if (host->data->flags & MMC_DATA_READ)
 878                         flags |= SG_MITER_TO_SG;
 879                 else
 880                         flags |= SG_MITER_FROM_SG;
 881                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 882                 host->blocks = data->blocks;
 883         }
 884
 885         sdhci_set_transfer_irqs(host);
 886
 887         /* Set the DMA boundary value and block size */
 888         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 889                 data->blksz), SDHCI_BLOCK_SIZE);
 890         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 891 }
 892
 893 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 894         struct mmc_command *cmd)
 895 {
 896         u16 mode = 0;
 897         struct mmc_data *data = cmd->data;
 898
 899         if (data == NULL) {
 900                 if (host->quirks2 &
 901                         SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
 902                         sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
 903                 } else {
 904                 /* clear Auto CMD settings for no data CMDs */
 905                         mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 906                         sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 907                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 908                 }
 909                 return;
 910         }
 911
 912         WARN_ON(!host->data);
 913
 914         if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
 915                 mode = SDHCI_TRNS_BLK_CNT_EN;
 916
 917         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 918                 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
 919                 /*
 920                  * If we are sending CMD23, CMD12 never gets sent
 921                  * on successful completion (so no Auto-CMD12).
 922                  */
 923                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
 924                     (cmd->opcode != SD_IO_RW_EXTENDED))
 925                         mode |= SDHCI_TRNS_AUTO_CMD12;
 926                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 927                         mode |= SDHCI_TRNS_AUTO_CMD23;
 928                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 929                 }
 930         }
 931
 932         if (data->flags & MMC_DATA_READ)
 933                 mode |= SDHCI_TRNS_READ;
 934         if (host->flags & SDHCI_REQ_USE_DMA)
 935                 mode |= SDHCI_TRNS_DMA;
 936
 937         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 938 }
 939
 940 static void sdhci_finish_data(struct sdhci_host *host)
 941 {
 942         struct mmc_data *data;
 943
 944         BUG_ON(!host->data);
 945
 946         data = host->data;
 947         host->data = NULL;
 948
 949         if (host->flags & SDHCI_REQ_USE_DMA) {
 950                 if (host->flags & SDHCI_USE_ADMA)
 951                         sdhci_adma_table_post(host, data);
 952                 else {
 953                         if (data->host_cookie == COOKIE_MAPPED) {
 954                                 dma_unmap_sg(mmc_dev(host->mmc),
 955                                         data->sg, data->sg_len,
 956                                         (data->flags & MMC_DATA_READ) ?
 957                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 958                                 data->host_cookie = COOKIE_UNMAPPED;
 959                         }
 960                 }
 961         }
 962
 963         /*
 964          * The specification states that the block count register must
 965          * be updated, but it does not specify at what point in the
 966          * data flow. That makes the register entirely useless to read
 967          * back so we have to assume that nothing made it to the card
 968          * in the event of an error.
 969          */
 970         if (data->error)
 971                 data->bytes_xfered = 0;
 972         else
 973                 data->bytes_xfered = data->blksz * data->blocks;
 974
 975         /*
 976          * Need to send CMD12 if -
 977          * a) open-ended multiblock transfer (no CMD23)
 978          * b) error in multiblock transfer
 979          */
 980         if (data->stop &&
 981             (data->error ||
 982              !host->mrq->sbc)) {
 983
 984                 /*
 985                  * The controller needs a reset of internal state machines
 986                  * upon error conditions.
 987                  */
 988                 if (data->error) {
 989                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 990                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 991                 }
 992
 993                 sdhci_send_command(host, data->stop);
 994         } else
 995                 tasklet_schedule(&host->finish_tasklet);
 996 }
 997
 998 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 999 {
1000         int flags;
1001         u32 mask;
1002         unsigned long timeout;
1003
1004         WARN_ON(host->cmd);
1005
1006         /* Initially, a command has no error */
1007         cmd->error = 0;
1008
1009         /* Wait max 10 ms */
1010         timeout = 10;
1011
1012         mask = SDHCI_CMD_INHIBIT;
1013         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1014                 mask |= SDHCI_DATA_INHIBIT;
1015
1016         /* We shouldn't wait for data inihibit for stop commands, even
1017            though they might use busy signaling */
1018         if (host->mrq->data && (cmd == host->mrq->data->stop))
1019                 mask &= ~SDHCI_DATA_INHIBIT;
1020
1021         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1022                 if (timeout == 0) {
1023                         pr_err("%s: Controller never released inhibit bit(s).\n",
1024                                mmc_hostname(host->mmc));
1025                         sdhci_dumpregs(host);
1026                         cmd->error = -EIO;
1027                         tasklet_schedule(&host->finish_tasklet);
1028                         return;
1029                 }
1030                 timeout--;
1031                 mdelay(1);
1032         }
1033
1034         timeout = jiffies;
1035         if (!cmd->data && cmd->busy_timeout > 9000)
1036                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1037         else
1038                 timeout += 10 * HZ;
1039         mod_timer(&host->timer, timeout);
1040
1041         host->cmd = cmd;
1042         host->busy_handle = 0;
1043
1044         sdhci_prepare_data(host, cmd);
1045
1046         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1047
1048         sdhci_set_transfer_mode(host, cmd);
1049
1050         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1051                 pr_err("%s: Unsupported response type!\n",
1052                         mmc_hostname(host->mmc));
1053                 cmd->error = -EINVAL;
1054                 tasklet_schedule(&host->finish_tasklet);
1055                 return;
1056         }
1057
1058         if (!(cmd->flags & MMC_RSP_PRESENT))
1059                 flags = SDHCI_CMD_RESP_NONE;
1060         else if (cmd->flags & MMC_RSP_136)
1061                 flags = SDHCI_CMD_RESP_LONG;
1062         else if (cmd->flags & MMC_RSP_BUSY)
1063                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1064         else
1065                 flags = SDHCI_CMD_RESP_SHORT;
1066
1067         if (cmd->flags & MMC_RSP_CRC)
1068                 flags |= SDHCI_CMD_CRC;
1069         if (cmd->flags & MMC_RSP_OPCODE)
1070                 flags |= SDHCI_CMD_INDEX;
1071
1072         /* CMD19 is special in that the Data Present Select should be set */
1073         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1074             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1075                 flags |= SDHCI_CMD_DATA;
1076
1077         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1078 }
1079 EXPORT_SYMBOL_GPL(sdhci_send_command);
1080
1081 static void sdhci_finish_command(struct sdhci_host *host)
1082 {
1083         int i;
1084
1085         BUG_ON(host->cmd == NULL);
1086
1087         if (host->cmd->flags & MMC_RSP_PRESENT) {
1088                 if (host->cmd->flags & MMC_RSP_136) {
1089                         /* CRC is stripped so we need to do some shifting. */
1090                         for (i = 0;i < 4;i++) {
1091                                 host->cmd->resp[i] = sdhci_readl(host,
1092                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1093                                 if (i != 3)
1094                                         host->cmd->resp[i] |=
1095                                                 sdhci_readb(host,
1096                                                 SDHCI_RESPONSE + (3-i)*4-1);
1097                         }
1098                 } else {
1099                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1100                 }
1101         }
1102
1103         /* Finished CMD23, now send actual command. */
1104         if (host->cmd == host->mrq->sbc) {
1105                 host->cmd = NULL;
1106                 sdhci_send_command(host, host->mrq->cmd);
1107         } else {
1108
1109                 /* Processed actual command. */
1110                 if (host->data && host->data_early)
1111                         sdhci_finish_data(host);
1112
1113                 if (!host->cmd->data)
1114                         tasklet_schedule(&host->finish_tasklet);
1115
1116                 host->cmd = NULL;
1117         }
1118 }
1119
1120 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1121 {
1122         u16 preset = 0;
1123
1124         switch (host->timing) {
1125         case MMC_TIMING_UHS_SDR12:
1126                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1127                 break;
1128         case MMC_TIMING_UHS_SDR25:
1129                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1130                 break;
1131         case MMC_TIMING_UHS_SDR50:
1132                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1133                 break;
1134         case MMC_TIMING_UHS_SDR104:
1135         case MMC_TIMING_MMC_HS200:
1136                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1137                 break;
1138         case MMC_TIMING_UHS_DDR50:
1139         case MMC_TIMING_MMC_DDR52:
1140                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1141                 break;
1142         case MMC_TIMING_MMC_HS400:
1143                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1144                 break;
1145         default:
1146                 pr_warn("%s: Invalid UHS-I mode selected\n",
1147                         mmc_hostname(host->mmc));
1148                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1149                 break;
1150         }
1151         return preset;
1152 }
1153
1154 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1155 {
1156         int div = 0; /* Initialized for compiler warning */
1157         int real_div = div, clk_mul = 1;
1158         u16 clk = 0;
1159         unsigned long timeout;
1160         bool switch_base_clk = false;
1161
1162         host->mmc->actual_clock = 0;
1163
1164         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1165         if (host->quirks2 & SDHCI_QUIRK2_NEED_DELAY_AFTER_INT_CLK_RST)
1166                 mdelay(1);
1167
1168         if (clock == 0)
1169                 return;
1170
1171         if (host->version >= SDHCI_SPEC_300) {
1172                 if (host->preset_enabled) {
1173                         u16 pre_val;
1174
1175                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1176                         pre_val = sdhci_get_preset_value(host);
1177                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1178                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1179                         if (host->clk_mul &&
1180                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1181                                 clk = SDHCI_PROG_CLOCK_MODE;
1182                                 real_div = div + 1;
1183                                 clk_mul = host->clk_mul;
1184                         } else {
1185                                 real_div = max_t(int, 1, div << 1);
1186                         }
1187                         goto clock_set;
1188                 }
1189
1190                 /*
1191                  * Check if the Host Controller supports Programmable Clock
1192                  * Mode.
1193                  */
1194                 if (host->clk_mul) {
1195                         for (div = 1; div <= 1024; div++) {
1196                                 if ((host->max_clk * host->clk_mul / div)
1197                                         <= clock)
1198                                         break;
1199                         }
1200                         if ((host->max_clk * host->clk_mul / div) <= clock) {
1201                                 /*
1202                                  * Set Programmable Clock Mode in the Clock
1203                                  * Control register.
1204                                  */
1205                                 clk = SDHCI_PROG_CLOCK_MODE;
1206                                 real_div = div;
1207                                 clk_mul = host->clk_mul;
1208                                 div--;
1209                         } else {
1210                                 /*
1211                                  * Divisor can be too small to reach clock
1212                                  * speed requirement. Then use the base clock.
1213                                  */
1214                                 switch_base_clk = true;
1215                         }
1216                 }
1217
1218                 if (!host->clk_mul || switch_base_clk) {
1219                         /* Version 3.00 divisors must be a multiple of 2. */
1220                         if (host->max_clk <= clock)
1221                                 div = 1;
1222                         else {
1223                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1224                                      div += 2) {
1225                                         if ((host->max_clk / div) <= clock)
1226                                                 break;
1227                                 }
1228                         }
1229                         real_div = div;
1230                         div >>= 1;
1231                         if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1232                                 && !div && host->max_clk <= 25000000)
1233                                 div = 1;
1234                 }
1235         } else {
1236                 /* Version 2.00 divisors must be a power of 2. */
1237                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1238                         if ((host->max_clk / div) <= clock)
1239                                 break;
1240                 }
1241                 real_div = div;
1242                 div >>= 1;
1243         }
1244
1245 clock_set:
1246         if (real_div)
1247                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1248         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1249         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1250                 << SDHCI_DIVIDER_HI_SHIFT;
1251         clk |= SDHCI_CLOCK_INT_EN;
1252         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1253
1254         /* Wait max 20 ms */
1255         timeout = 20;
1256         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1257                 & SDHCI_CLOCK_INT_STABLE)) {
1258                 if (timeout == 0) {
1259                         pr_err("%s: Internal clock never stabilised.\n",
1260                                mmc_hostname(host->mmc));
1261                         sdhci_dumpregs(host);
1262                         return;
1263                 }
1264                 timeout--;
1265                 mdelay(1);
1266         }
1267
1268         clk |= SDHCI_CLOCK_CARD_EN;
1269         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1270 }
1271 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1272
1273 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1274                             unsigned short vdd)
1275 {
1276         struct mmc_host *mmc = host->mmc;
1277         u8 pwr = 0;
1278
1279         if (mode != MMC_POWER_OFF) {
1280                 switch (1 << vdd) {
1281                 case MMC_VDD_165_195:
1282                         pwr = SDHCI_POWER_180;
1283                         break;
1284                 case MMC_VDD_29_30:
1285                 case MMC_VDD_30_31:
1286                         pwr = SDHCI_POWER_300;
1287                         break;
1288                 case MMC_VDD_32_33:
1289                 case MMC_VDD_33_34:
1290                         pwr = SDHCI_POWER_330;
1291                         break;
1292                 default:
1293                         WARN(1, "%s: Invalid vdd %#x\n",
1294                              mmc_hostname(host->mmc), vdd);
1295                         break;
1296                 }
1297         }
1298
1299         if (host->pwr == pwr)
1300                 return;
1301
1302         host->pwr = pwr;
1303
1304         if (pwr == 0) {
1305                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1306                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307                         sdhci_runtime_pm_bus_off(host);
1308                 vdd = 0;
1309         } else {
1310                 /*
1311                  * Spec says that we should clear the power reg before setting
1312                  * a new value. Some controllers don't seem to like this though.
1313                  */
1314                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1315                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1316
1317                 /*
1318                  * At least the Marvell CaFe chip gets confused if we set the
1319                  * voltage and set turn on power at the same time, so set the
1320                  * voltage first.
1321                  */
1322                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1323                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1324
1325                 pwr |= SDHCI_POWER_ON;
1326
1327                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1328
1329                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1330                         sdhci_runtime_pm_bus_on(host);
1331
1332                 /*
1333                  * Some controllers need an extra 10ms delay of 10ms before
1334                  * they can apply clock after applying power
1335                  */
1336                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1337                         mdelay(10);
1338         }
1339
1340         if (!IS_ERR(mmc->supply.vmmc)) {
1341                 spin_unlock_irq(&host->lock);
1342                 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1343                 spin_lock_irq(&host->lock);
1344         }
1345 }
1346
1347 /*****************************************************************************\
1348  *                                                                           *
1349  * MMC callbacks                                                             *
1350  *                                                                           *
1351 \*****************************************************************************/
1352
1353 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1354 {
1355         struct sdhci_host *host;
1356         int present;
1357         unsigned long flags;
1358
1359         host = mmc_priv(mmc);
1360
1361         sdhci_runtime_pm_get(host);
1362
1363         /* Firstly check card presence */
1364         present = mmc->ops->get_cd(mmc);
1365
1366         spin_lock_irqsave(&host->lock, flags);
1367
1368         WARN_ON(host->mrq != NULL);
1369
1370 #ifndef SDHCI_USE_LEDS_CLASS
1371         sdhci_activate_led(host);
1372 #endif
1373
1374         /*
1375          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1376          * requests if Auto-CMD12 is enabled.
1377          */
1378         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1379                 if (mrq->stop) {
1380                         mrq->data->stop = NULL;
1381                         mrq->stop = NULL;
1382                 }
1383         }
1384
1385         host->mrq = mrq;
1386
1387         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1388                 host->mrq->cmd->error = -ENOMEDIUM;
1389                 tasklet_schedule(&host->finish_tasklet);
1390         } else {
1391                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1392                         sdhci_send_command(host, mrq->sbc);
1393                 else
1394                         sdhci_send_command(host, mrq->cmd);
1395         }
1396
1397         mmiowb();
1398         spin_unlock_irqrestore(&host->lock, flags);
1399 }
1400
1401 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1402 {
1403         u8 ctrl;
1404
1405         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1406         if (width == MMC_BUS_WIDTH_8) {
1407                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1408                 if (host->version >= SDHCI_SPEC_300)
1409                         ctrl |= SDHCI_CTRL_8BITBUS;
1410         } else {
1411                 if (host->version >= SDHCI_SPEC_300)
1412                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1413                 if (width == MMC_BUS_WIDTH_4)
1414                         ctrl |= SDHCI_CTRL_4BITBUS;
1415                 else
1416                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1417         }
1418         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1419 }
1420 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1421
1422 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1423 {
1424         u16 ctrl_2;
1425
1426         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1427         /* Select Bus Speed Mode for host */
1428         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1429         if ((timing == MMC_TIMING_MMC_HS200) ||
1430             (timing == MMC_TIMING_UHS_SDR104))
1431                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1432         else if (timing == MMC_TIMING_UHS_SDR12)
1433                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1434         else if (timing == MMC_TIMING_UHS_SDR25)
1435                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1436         else if (timing == MMC_TIMING_UHS_SDR50)
1437                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1438         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1439                  (timing == MMC_TIMING_MMC_DDR52))
1440                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1441         else if (timing == MMC_TIMING_MMC_HS400)
1442                 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1443         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1444 }
1445 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1446
1447 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1448 {
1449         unsigned long flags;
1450         u8 ctrl;
1451         struct mmc_host *mmc = host->mmc;
1452
1453         spin_lock_irqsave(&host->lock, flags);
1454
1455         if (host->flags & SDHCI_DEVICE_DEAD) {
1456                 spin_unlock_irqrestore(&host->lock, flags);
1457                 if (!IS_ERR(mmc->supply.vmmc) &&
1458                     ios->power_mode == MMC_POWER_OFF)
1459                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1460                 return;
1461         }
1462
1463         /*
1464          * Reset the chip on each power off.
1465          * Should clear out any weird states.
1466          */
1467         if (ios->power_mode == MMC_POWER_OFF) {
1468                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1469                 sdhci_reinit(host);
1470         }
1471
1472         if (host->version >= SDHCI_SPEC_300 &&
1473                 (ios->power_mode == MMC_POWER_UP) &&
1474                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1475                 sdhci_enable_preset_value(host, false);
1476
1477         if (!ios->clock || ios->clock != host->clock) {
1478                 host->ops->set_clock(host, ios->clock);
1479                 host->clock = ios->clock;
1480
1481                 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1482                     host->clock) {
1483                         host->timeout_clk = host->mmc->actual_clock ?
1484                                                 host->mmc->actual_clock / 1000 :
1485                                                 host->clock / 1000;
1486                         host->mmc->max_busy_timeout =
1487                                 host->ops->get_max_timeout_count ?
1488                                 host->ops->get_max_timeout_count(host) :
1489                                 1 << 27;
1490                         host->mmc->max_busy_timeout /= host->timeout_clk;
1491                 }
1492         }
1493
1494         sdhci_set_power(host, ios->power_mode, ios->vdd);
1495
1496         if (host->ops->platform_send_init_74_clocks)
1497                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1498
1499         host->ops->set_bus_width(host, ios->bus_width);
1500
1501         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1502
1503         if ((ios->timing == MMC_TIMING_SD_HS ||
1504              ios->timing == MMC_TIMING_MMC_HS)
1505             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1506                 ctrl |= SDHCI_CTRL_HISPD;
1507         else
1508                 ctrl &= ~SDHCI_CTRL_HISPD;
1509
1510         if (host->version >= SDHCI_SPEC_300) {
1511                 u16 clk, ctrl_2;
1512
1513                 /* In case of UHS-I modes, set High Speed Enable */
1514                 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1515                     (ios->timing == MMC_TIMING_MMC_HS200) ||
1516                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1517                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1518                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1519                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1520                     (ios->timing == MMC_TIMING_UHS_SDR25))
1521                         ctrl |= SDHCI_CTRL_HISPD;
1522
1523                 if (!host->preset_enabled) {
1524                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1525                         /*
1526                          * We only need to set Driver Strength if the
1527                          * preset value enable is not set.
1528                          */
1529                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1530                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1531                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1532                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1533                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1534                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1535                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1536                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1537                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1538                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1539                         else {
1540                                 pr_warn("%s: invalid driver type, default to driver type B\n",
1541                                         mmc_hostname(mmc));
1542                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1543                         }
1544
1545                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1546                 } else {
1547                         /*
1548                          * According to SDHC Spec v3.00, if the Preset Value
1549                          * Enable in the Host Control 2 register is set, we
1550                          * need to reset SD Clock Enable before changing High
1551                          * Speed Enable to avoid generating clock gliches.
1552                          */
1553
1554                         /* Reset SD Clock Enable */
1555                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1556                         clk &= ~SDHCI_CLOCK_CARD_EN;
1557                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1558
1559                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1560
1561                         /* Re-enable SD Clock */
1562                         host->ops->set_clock(host, host->clock);
1563                 }
1564
1565                 /* Reset SD Clock Enable */
1566                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1567                 clk &= ~SDHCI_CLOCK_CARD_EN;
1568                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1569
1570                 host->ops->set_uhs_signaling(host, ios->timing);
1571                 host->timing = ios->timing;
1572
1573                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1574                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1575                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1576                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1577                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1578                                  (ios->timing == MMC_TIMING_UHS_DDR50) ||
1579                                  (ios->timing == MMC_TIMING_MMC_DDR52))) {
1580                         u16 preset;
1581
1582                         sdhci_enable_preset_value(host, true);
1583                         preset = sdhci_get_preset_value(host);
1584                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1585                                 >> SDHCI_PRESET_DRV_SHIFT;
1586                 }
1587
1588                 /* Re-enable SD Clock */
1589                 host->ops->set_clock(host, host->clock);
1590         } else
1591                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1592
1593         /*
1594          * Some (ENE) controllers go apeshit on some ios operation,
1595          * signalling timeout and CRC errors even on CMD0. Resetting
1596          * it on each ios seems to solve the problem.
1597          */
1598         if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1599                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1600
1601         mmiowb();
1602         spin_unlock_irqrestore(&host->lock, flags);
1603 }
1604
1605 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1606 {
1607         struct sdhci_host *host = mmc_priv(mmc);
1608
1609         sdhci_runtime_pm_get(host);
1610         sdhci_do_set_ios(host, ios);
1611         sdhci_runtime_pm_put(host);
1612 }
1613
1614 static int sdhci_do_get_cd(struct sdhci_host *host)
1615 {
1616         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1617
1618         if (host->flags & SDHCI_DEVICE_DEAD)
1619                 return 0;
1620
1621         /* If nonremovable, assume that the card is always present. */
1622         if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1623                 return 1;
1624
1625         /*
1626          * Try slot gpio detect, if defined it take precedence
1627          * over build in controller functionality
1628          */
1629         if (!IS_ERR_VALUE(gpio_cd))
1630                 return !!gpio_cd;
1631
1632         /* If polling, assume that the card is always present. */
1633         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1634                 return 1;
1635
1636         /* Host native card detect */
1637         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1638 }
1639
1640 static int sdhci_get_cd(struct mmc_host *mmc)
1641 {
1642         struct sdhci_host *host = mmc_priv(mmc);
1643         int ret;
1644
1645         sdhci_runtime_pm_get(host);
1646         ret = sdhci_do_get_cd(host);
1647         sdhci_runtime_pm_put(host);
1648         return ret;
1649 }
1650
1651 static int sdhci_check_ro(struct sdhci_host *host)
1652 {
1653         unsigned long flags;
1654         int is_readonly;
1655
1656         spin_lock_irqsave(&host->lock, flags);
1657
1658         if (host->flags & SDHCI_DEVICE_DEAD)
1659                 is_readonly = 0;
1660         else if (host->ops->get_ro)
1661                 is_readonly = host->ops->get_ro(host);
1662         else
1663                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1664                                 & SDHCI_WRITE_PROTECT);
1665
1666         spin_unlock_irqrestore(&host->lock, flags);
1667
1668         /* This quirk needs to be replaced by a callback-function later */
1669         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1670                 !is_readonly : is_readonly;
1671 }
1672
1673 #define SAMPLE_COUNT    5
1674
1675 static int sdhci_do_get_ro(struct sdhci_host *host)
1676 {
1677         int i, ro_count;
1678
1679         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1680                 return sdhci_check_ro(host);
1681
1682         ro_count = 0;
1683         for (i = 0; i < SAMPLE_COUNT; i++) {
1684                 if (sdhci_check_ro(host)) {
1685                         if (++ro_count > SAMPLE_COUNT / 2)
1686                                 return 1;
1687                 }
1688                 msleep(30);
1689         }
1690         return 0;
1691 }
1692
1693 static void sdhci_hw_reset(struct mmc_host *mmc)
1694 {
1695         struct sdhci_host *host = mmc_priv(mmc);
1696
1697         if (host->ops && host->ops->hw_reset)
1698                 host->ops->hw_reset(host);
1699 }
1700
1701 static int sdhci_get_ro(struct mmc_host *mmc)
1702 {
1703         struct sdhci_host *host = mmc_priv(mmc);
1704         int ret;
1705
1706         sdhci_runtime_pm_get(host);
1707         ret = sdhci_do_get_ro(host);
1708         sdhci_runtime_pm_put(host);
1709         return ret;
1710 }
1711
1712 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1713 {
1714         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1715                 if (enable)
1716                         host->ier |= SDHCI_INT_CARD_INT;
1717                 else
1718                         host->ier &= ~SDHCI_INT_CARD_INT;
1719
1720                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1721                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1722                 mmiowb();
1723         }
1724 }
1725
1726 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1727 {
1728         struct sdhci_host *host = mmc_priv(mmc);
1729         unsigned long flags;
1730
1731         sdhci_runtime_pm_get(host);
1732
1733         spin_lock_irqsave(&host->lock, flags);
1734         if (enable)
1735                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1736         else
1737                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1738
1739         sdhci_enable_sdio_irq_nolock(host, enable);
1740         spin_unlock_irqrestore(&host->lock, flags);
1741
1742         sdhci_runtime_pm_put(host);
1743 }
1744
1745 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1746                                                 struct mmc_ios *ios)
1747 {
1748         struct mmc_host *mmc = host->mmc;
1749         u16 ctrl;
1750         int ret;
1751
1752         /*
1753          * Signal Voltage Switching is only applicable for Host Controllers
1754          * v3.00 and above.
1755          */
1756         if (host->version < SDHCI_SPEC_300)
1757                 return 0;
1758
1759         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1760
1761         switch (ios->signal_voltage) {
1762         case MMC_SIGNAL_VOLTAGE_330:
1763                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1764                 ctrl &= ~SDHCI_CTRL_VDD_180;
1765                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1766
1767                 if (!IS_ERR(mmc->supply.vqmmc)) {
1768                         ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1769                                                     3600000);
1770                         if (ret) {
1771                                 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1772                                         mmc_hostname(mmc));
1773                                 return -EIO;
1774                         }
1775                 }
1776                 /* Wait for 5ms */
1777                 usleep_range(5000, 5500);
1778
1779                 /* 3.3V regulator output should be stable within 5 ms */
1780                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1781                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1782                         return 0;
1783
1784                 pr_warn("%s: 3.3V regulator output did not became stable\n",
1785                         mmc_hostname(mmc));
1786
1787                 return -EAGAIN;
1788         case MMC_SIGNAL_VOLTAGE_180:
1789                 if (!IS_ERR(mmc->supply.vqmmc)) {
1790                         ret = regulator_set_voltage(mmc->supply.vqmmc,
1791                                         1700000, 1950000);
1792                         if (ret) {
1793                                 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1794                                         mmc_hostname(mmc));
1795                                 return -EIO;
1796                         }
1797                 }
1798
1799                 /*
1800                  * Enable 1.8V Signal Enable in the Host Control2
1801                  * register
1802                  */
1803                 ctrl |= SDHCI_CTRL_VDD_180;
1804                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1805
1806                 /* Some controller need to do more when switching */
1807                 if (host->ops->voltage_switch)
1808                         host->ops->voltage_switch(host);
1809
1810                 /* 1.8V regulator output should be stable within 5 ms */
1811                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1812                 if (ctrl & SDHCI_CTRL_VDD_180)
1813                         return 0;
1814
1815                 pr_warn("%s: 1.8V regulator output did not became stable\n",
1816                         mmc_hostname(mmc));
1817
1818                 return -EAGAIN;
1819         case MMC_SIGNAL_VOLTAGE_120:
1820                 if (!IS_ERR(mmc->supply.vqmmc)) {
1821                         ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1822                                                     1300000);
1823                         if (ret) {
1824                                 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1825                                         mmc_hostname(mmc));
1826                                 return -EIO;
1827                         }
1828                 }
1829                 return 0;
1830         default:
1831                 /* No signal voltage switch required */
1832                 return 0;
1833         }
1834 }
1835
1836 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1837         struct mmc_ios *ios)
1838 {
1839         struct sdhci_host *host = mmc_priv(mmc);
1840         int err;
1841
1842         if (host->version < SDHCI_SPEC_300)
1843                 return 0;
1844         sdhci_runtime_pm_get(host);
1845         err = sdhci_do_start_signal_voltage_switch(host, ios);
1846         sdhci_runtime_pm_put(host);
1847         return err;
1848 }
1849
1850 static int sdhci_card_busy(struct mmc_host *mmc)
1851 {
1852         struct sdhci_host *host = mmc_priv(mmc);
1853         u32 present_state;
1854
1855         sdhci_runtime_pm_get(host);
1856         /* Check whether DAT[3:0] is 0000 */
1857         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1858         sdhci_runtime_pm_put(host);
1859
1860         return !(present_state & SDHCI_DATA_LVL_MASK);
1861 }
1862
1863 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1864 {
1865         struct sdhci_host *host = mmc_priv(mmc);
1866         unsigned long flags;
1867
1868         spin_lock_irqsave(&host->lock, flags);
1869         host->flags |= SDHCI_HS400_TUNING;
1870         spin_unlock_irqrestore(&host->lock, flags);
1871
1872         return 0;
1873 }
1874
1875 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1876 {
1877         struct sdhci_host *host = mmc_priv(mmc);
1878         u16 ctrl;
1879         int tuning_loop_counter = MAX_TUNING_LOOP;
1880         int err = 0;
1881         unsigned long flags;
1882         unsigned int tuning_count = 0;
1883         bool hs400_tuning;
1884
1885         sdhci_runtime_pm_get(host);
1886         spin_lock_irqsave(&host->lock, flags);
1887
1888         hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1889         host->flags &= ~SDHCI_HS400_TUNING;
1890
1891         if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1892                 tuning_count = host->tuning_count;
1893
1894         /*
1895          * The Host Controller needs tuning in case of SDR104 and DDR50
1896          * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1897          * the Capabilities register.
1898          * If the Host Controller supports the HS200 mode then the
1899          * tuning function has to be executed.
1900          */
1901         switch (host->timing) {
1902         /* HS400 tuning is done in HS200 mode */
1903         case MMC_TIMING_MMC_HS400:
1904                 err = -EINVAL;
1905                 goto out_unlock;
1906
1907         case MMC_TIMING_MMC_HS200:
1908                 /*
1909                  * Periodic re-tuning for HS400 is not expected to be needed, so
1910                  * disable it here.
1911                  */
1912                 if (hs400_tuning)
1913                         tuning_count = 0;
1914                 break;
1915
1916         case MMC_TIMING_UHS_SDR104:
1917         case MMC_TIMING_UHS_DDR50:
1918                 break;
1919
1920         case MMC_TIMING_UHS_SDR50:
1921                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1922                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1923                         break;
1924                 /* FALLTHROUGH */
1925
1926         default:
1927                 goto out_unlock;
1928         }
1929
1930         if (host->ops->platform_execute_tuning) {
1931                 spin_unlock_irqrestore(&host->lock, flags);
1932                 err = host->ops->platform_execute_tuning(host, opcode);
1933                 sdhci_runtime_pm_put(host);
1934                 return err;
1935         }
1936
1937         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1938         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1939         if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1940                 ctrl |= SDHCI_CTRL_TUNED_CLK;
1941         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1942
1943         /*
1944          * As per the Host Controller spec v3.00, tuning command
1945          * generates Buffer Read Ready interrupt, so enable that.
1946          *
1947          * Note: The spec clearly says that when tuning sequence
1948          * is being performed, the controller does not generate
1949          * interrupts other than Buffer Read Ready interrupt. But
1950          * to make sure we don't hit a controller bug, we _only_
1951          * enable Buffer Read Ready interrupt here.
1952          */
1953         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1954         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1955
1956         /*
1957          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1958          * of loops reaches 40 times or a timeout of 150ms occurs.
1959          */
1960         do {
1961                 struct mmc_command cmd = {0};
1962                 struct mmc_request mrq = {NULL};
1963
1964                 cmd.opcode = opcode;
1965                 cmd.arg = 0;
1966                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1967                 cmd.retries = 0;
1968                 cmd.data = NULL;
1969                 cmd.error = 0;
1970
1971                 if (tuning_loop_counter-- == 0)
1972                         break;
1973
1974                 mrq.cmd = &cmd;
1975                 host->mrq = &mrq;
1976
1977                 /*
1978                  * In response to CMD19, the card sends 64 bytes of tuning
1979                  * block to the Host Controller. So we set the block size
1980                  * to 64 here.
1981                  */
1982                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1983                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1984                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1985                                              SDHCI_BLOCK_SIZE);
1986                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1987                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1988                                              SDHCI_BLOCK_SIZE);
1989                 } else {
1990                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1991                                      SDHCI_BLOCK_SIZE);
1992                 }
1993
1994                 /*
1995                  * The tuning block is sent by the card to the host controller.
1996                  * So we set the TRNS_READ bit in the Transfer Mode register.
1997                  * This also takes care of setting DMA Enable and Multi Block
1998                  * Select in the same register to 0.
1999                  */
2000                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
2001
2002                 sdhci_send_command(host, &cmd);
2003
2004                 host->cmd = NULL;
2005                 host->mrq = NULL;
2006
2007                 spin_unlock_irqrestore(&host->lock, flags);
2008                 /* Wait for Buffer Read Ready interrupt */
2009                 wait_event_interruptible_timeout(host->buf_ready_int,
2010                                         (host->tuning_done == 1),
2011                                         msecs_to_jiffies(50));
2012                 spin_lock_irqsave(&host->lock, flags);
2013
2014                 if (!host->tuning_done) {
2015                         pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2016                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2017                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2018                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2019                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2020
2021                         err = -EIO;
2022                         goto out;
2023                 }
2024
2025                 host->tuning_done = 0;
2026
2027                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2028
2029                 /* eMMC spec does not require a delay between tuning cycles */
2030                 if (opcode == MMC_SEND_TUNING_BLOCK)
2031                         mdelay(1);
2032         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2033
2034         /*
2035          * The Host Driver has exhausted the maximum number of loops allowed,
2036          * so use fixed sampling frequency.
2037          */
2038         if (tuning_loop_counter < 0) {
2039                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2040                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2041         }
2042         if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2043                 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2044                 err = -EIO;
2045         }
2046
2047 out:
2048         if (tuning_count) {
2049                 /*
2050                  * In case tuning fails, host controllers which support
2051                  * re-tuning can try tuning again at a later time, when the
2052                  * re-tuning timer expires.  So for these controllers, we
2053                  * return 0. Since there might be other controllers who do not
2054                  * have this capability, we return error for them.
2055                  */
2056                 err = 0;
2057         }
2058
2059         host->mmc->retune_period = err ? 0 : tuning_count;
2060
2061         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2062         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2063 out_unlock:
2064         spin_unlock_irqrestore(&host->lock, flags);
2065         sdhci_runtime_pm_put(host);
2066
2067         return err;
2068 }
2069
2070 static int sdhci_select_drive_strength(struct mmc_card *card,
2071                                        unsigned int max_dtr, int host_drv,
2072                                        int card_drv, int *drv_type)
2073 {
2074         struct sdhci_host *host = mmc_priv(card->host);
2075
2076         if (!host->ops->select_drive_strength)
2077                 return 0;
2078
2079         return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2080                                                 card_drv, drv_type);
2081 }
2082
2083 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2084 {
2085         /* Host Controller v3.00 defines preset value registers */
2086         if (host->version < SDHCI_SPEC_300)
2087                 return;
2088
2089         /*
2090          * We only enable or disable Preset Value if they are not already
2091          * enabled or disabled respectively. Otherwise, we bail out.
2092          */
2093         if (host->preset_enabled != enable) {
2094                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2095
2096                 if (enable)
2097                         ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2098                 else
2099                         ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2100
2101                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2102
2103                 if (enable)
2104                         host->flags |= SDHCI_PV_ENABLED;
2105                 else
2106                         host->flags &= ~SDHCI_PV_ENABLED;
2107
2108                 host->preset_enabled = enable;
2109         }
2110 }
2111
2112 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2113                                 int err)
2114 {
2115         struct sdhci_host *host = mmc_priv(mmc);
2116         struct mmc_data *data = mrq->data;
2117
2118         if (host->flags & SDHCI_REQ_USE_DMA) {
2119                 if (data->host_cookie == COOKIE_GIVEN ||
2120                                 data->host_cookie == COOKIE_MAPPED)
2121                         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2122                                          data->flags & MMC_DATA_WRITE ?
2123                                          DMA_TO_DEVICE : DMA_FROM_DEVICE);
2124                 data->host_cookie = COOKIE_UNMAPPED;
2125         }
2126 }
2127
2128 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2129                                        struct mmc_data *data)
2130 {
2131         int sg_count;
2132
2133         if (data->host_cookie == COOKIE_MAPPED) {
2134                 data->host_cookie = COOKIE_GIVEN;
2135                 return data->sg_count;
2136         }
2137
2138         WARN_ON(data->host_cookie == COOKIE_GIVEN);
2139
2140         sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2141                                 data->flags & MMC_DATA_WRITE ?
2142                                 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2143
2144         if (sg_count == 0)
2145                 return -ENOSPC;
2146
2147         data->sg_count = sg_count;
2148         data->host_cookie = COOKIE_MAPPED;
2149
2150         return sg_count;
2151 }
2152
2153 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2154                                bool is_first_req)
2155 {
2156         struct sdhci_host *host = mmc_priv(mmc);
2157
2158         mrq->data->host_cookie = COOKIE_UNMAPPED;
2159
2160         if (host->flags & SDHCI_REQ_USE_DMA)
2161                 sdhci_pre_dma_transfer(host, mrq->data);
2162 }
2163
2164 static void sdhci_card_event(struct mmc_host *mmc)
2165 {
2166         struct sdhci_host *host = mmc_priv(mmc);
2167         unsigned long flags;
2168         int present;
2169
2170         /* First check if client has provided their own card event */
2171         if (host->ops->card_event)
2172                 host->ops->card_event(host);
2173
2174         present = sdhci_do_get_cd(host);
2175
2176         spin_lock_irqsave(&host->lock, flags);
2177
2178         /* Check host->mrq first in case we are runtime suspended */
2179         if (host->mrq && !present) {
2180                 pr_err("%s: Card removed during transfer!\n",
2181                         mmc_hostname(host->mmc));
2182                 pr_err("%s: Resetting controller.\n",
2183                         mmc_hostname(host->mmc));
2184
2185                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2186                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2187
2188                 host->mrq->cmd->error = -ENOMEDIUM;
2189                 tasklet_schedule(&host->finish_tasklet);
2190         }
2191
2192         spin_unlock_irqrestore(&host->lock, flags);
2193 }
2194
2195 static const struct mmc_host_ops sdhci_ops = {
2196         .request        = sdhci_request,
2197         .post_req       = sdhci_post_req,
2198         .pre_req        = sdhci_pre_req,
2199         .set_ios        = sdhci_set_ios,
2200         .get_cd         = sdhci_get_cd,
2201         .get_ro         = sdhci_get_ro,
2202         .hw_reset       = sdhci_hw_reset,
2203         .enable_sdio_irq = sdhci_enable_sdio_irq,
2204         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2205         .prepare_hs400_tuning           = sdhci_prepare_hs400_tuning,
2206         .execute_tuning                 = sdhci_execute_tuning,
2207         .select_drive_strength          = sdhci_select_drive_strength,
2208         .card_event                     = sdhci_card_event,
2209         .card_busy      = sdhci_card_busy,
2210 };
2211
2212 /*****************************************************************************\
2213  *                                                                           *
2214  * Tasklets                                                                  *
2215  *                                                                           *
2216 \*****************************************************************************/
2217
2218 static void sdhci_tasklet_finish(unsigned long param)
2219 {
2220         struct sdhci_host *host;
2221         unsigned long flags;
2222         struct mmc_request *mrq;
2223
2224         host = (struct sdhci_host*)param;
2225
2226         spin_lock_irqsave(&host->lock, flags);
2227
2228         /*
2229          * If this tasklet gets rescheduled while running, it will
2230          * be run again afterwards but without any active request.
2231          */
2232         if (!host->mrq) {
2233                 spin_unlock_irqrestore(&host->lock, flags);
2234                 return;
2235         }
2236
2237         del_timer(&host->timer);
2238
2239         mrq = host->mrq;
2240
2241         /*
2242          * The controller needs a reset of internal state machines
2243          * upon error conditions.
2244          */
2245         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2246             ((mrq->cmd && mrq->cmd->error) ||
2247              (mrq->sbc && mrq->sbc->error) ||
2248              (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2249                             (mrq->data->stop && mrq->data->stop->error))) ||
2250              (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2251
2252                 /* Some controllers need this kick or reset won't work here */
2253                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2254                         /* This is to force an update */
2255                         host->ops->set_clock(host, host->clock);
2256
2257                 /* Spec says we should do both at the same time, but Ricoh
2258                    controllers do not like that. */
2259                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2260                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2261         }
2262
2263         host->mrq = NULL;
2264         host->cmd = NULL;
2265         host->data = NULL;
2266
2267 #ifndef SDHCI_USE_LEDS_CLASS
2268         sdhci_deactivate_led(host);
2269 #endif
2270
2271         mmiowb();
2272         spin_unlock_irqrestore(&host->lock, flags);
2273
2274         mmc_request_done(host->mmc, mrq);
2275         sdhci_runtime_pm_put(host);
2276 }
2277
2278 static void sdhci_timeout_timer(unsigned long data)
2279 {
2280         struct sdhci_host *host;
2281         unsigned long flags;
2282
2283         host = (struct sdhci_host*)data;
2284
2285         spin_lock_irqsave(&host->lock, flags);
2286
2287         if (host->mrq) {
2288                 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2289                        mmc_hostname(host->mmc));
2290                 sdhci_dumpregs(host);
2291
2292                 if (host->data) {
2293                         host->data->error = -ETIMEDOUT;
2294                         sdhci_finish_data(host);
2295                 } else {
2296                         if (host->cmd)
2297                                 host->cmd->error = -ETIMEDOUT;
2298                         else
2299                                 host->mrq->cmd->error = -ETIMEDOUT;
2300
2301                         tasklet_schedule(&host->finish_tasklet);
2302                 }
2303         }
2304
2305         mmiowb();
2306         spin_unlock_irqrestore(&host->lock, flags);
2307 }
2308
2309 /*****************************************************************************\
2310  *                                                                           *
2311  * Interrupt handling                                                        *
2312  *                                                                           *
2313 \*****************************************************************************/
2314
2315 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2316 {
2317         BUG_ON(intmask == 0);
2318
2319         if (!host->cmd) {
2320                 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2321                        mmc_hostname(host->mmc), (unsigned)intmask);
2322                 sdhci_dumpregs(host);
2323                 return;
2324         }
2325
2326         if (intmask & SDHCI_INT_TIMEOUT)
2327                 host->cmd->error = -ETIMEDOUT;
2328         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2329                         SDHCI_INT_INDEX))
2330                 host->cmd->error = -EILSEQ;
2331
2332         if (host->cmd->error) {
2333                 tasklet_schedule(&host->finish_tasklet);
2334                 return;
2335         }
2336
2337         /*
2338          * The host can send and interrupt when the busy state has
2339          * ended, allowing us to wait without wasting CPU cycles.
2340          * Unfortunately this is overloaded on the "data complete"
2341          * interrupt, so we need to take some care when handling
2342          * it.
2343          *
2344          * Note: The 1.0 specification is a bit ambiguous about this
2345          *       feature so there might be some problems with older
2346          *       controllers.
2347          */
2348         if (host->cmd->flags & MMC_RSP_BUSY) {
2349                 if (host->cmd->data)
2350                         DBG("Cannot wait for busy signal when also doing a data transfer");
2351                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2352                                 && !host->busy_handle) {
2353                         /* Mark that command complete before busy is ended */
2354                         host->busy_handle = 1;
2355                         return;
2356                 }
2357
2358                 /* The controller does not support the end-of-busy IRQ,
2359                  * fall through and take the SDHCI_INT_RESPONSE */
2360         } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2361                    host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2362                 *mask &= ~SDHCI_INT_DATA_END;
2363         }
2364
2365         if (intmask & SDHCI_INT_RESPONSE)
2366                 sdhci_finish_command(host);
2367 }
2368
2369 #ifdef CONFIG_MMC_DEBUG
2370 static void sdhci_adma_show_error(struct sdhci_host *host)
2371 {
2372         const char *name = mmc_hostname(host->mmc);
2373         void *desc = host->adma_table;
2374
2375         sdhci_dumpregs(host);
2376
2377         while (true) {
2378                 struct sdhci_adma2_64_desc *dma_desc = desc;
2379
2380                 if (host->flags & SDHCI_USE_64_BIT_DMA)
2381                         DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2382                             name, desc, le32_to_cpu(dma_desc->addr_hi),
2383                             le32_to_cpu(dma_desc->addr_lo),
2384                             le16_to_cpu(dma_desc->len),
2385                             le16_to_cpu(dma_desc->cmd));
2386                 else
2387                         DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2388                             name, desc, le32_to_cpu(dma_desc->addr_lo),
2389                             le16_to_cpu(dma_desc->len),
2390                             le16_to_cpu(dma_desc->cmd));
2391
2392                 desc += host->desc_sz;
2393
2394                 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2395                         break;
2396         }
2397 }
2398 #else
2399 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2400 #endif
2401
2402 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2403 {
2404         u32 command;
2405         BUG_ON(intmask == 0);
2406
2407         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2408         if (intmask & SDHCI_INT_DATA_AVAIL) {
2409                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2410                 if (command == MMC_SEND_TUNING_BLOCK ||
2411                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2412                         host->tuning_done = 1;
2413                         wake_up(&host->buf_ready_int);
2414                         return;
2415                 }
2416         }
2417
2418         if (!host->data) {
2419                 /*
2420                  * The "data complete" interrupt is also used to
2421                  * indicate that a busy state has ended. See comment
2422                  * above in sdhci_cmd_irq().
2423                  */
2424                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2425                         if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2426                                 host->cmd->error = -ETIMEDOUT;
2427                                 tasklet_schedule(&host->finish_tasklet);
2428                                 return;
2429                         }
2430                         if (intmask & SDHCI_INT_DATA_END) {
2431                                 /*
2432                                  * Some cards handle busy-end interrupt
2433                                  * before the command completed, so make
2434                                  * sure we do things in the proper order.
2435                                  */
2436                                 if (host->busy_handle)
2437                                         sdhci_finish_command(host);
2438                                 else
2439                                         host->busy_handle = 1;
2440                                 return;
2441                         }
2442                 }
2443
2444                 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2445                        mmc_hostname(host->mmc), (unsigned)intmask);
2446                 sdhci_dumpregs(host);
2447
2448                 return;
2449         }
2450
2451         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2452                 host->data->error = -ETIMEDOUT;
2453         else if (intmask & SDHCI_INT_DATA_END_BIT)
2454                 host->data->error = -EILSEQ;
2455         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2456                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2457                         != MMC_BUS_TEST_R)
2458                 host->data->error = -EILSEQ;
2459         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2460                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2461                 sdhci_adma_show_error(host);
2462                 host->data->error = -EIO;
2463                 if (host->ops->adma_workaround)
2464                         host->ops->adma_workaround(host, intmask);
2465         }
2466
2467         if (host->data->error)
2468                 sdhci_finish_data(host);
2469         else {
2470                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2471                         sdhci_transfer_pio(host);
2472
2473                 /*
2474                  * We currently don't do anything fancy with DMA
2475                  * boundaries, but as we can't disable the feature
2476                  * we need to at least restart the transfer.
2477                  *
2478                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2479                  * should return a valid address to continue from, but as
2480                  * some controllers are faulty, don't trust them.
2481                  */
2482                 if (intmask & SDHCI_INT_DMA_END) {
2483                         u32 dmastart, dmanow;
2484                         dmastart = sg_dma_address(host->data->sg);
2485                         dmanow = dmastart + host->data->bytes_xfered;
2486                         /*
2487                          * Force update to the next DMA block boundary.
2488                          */
2489                         dmanow = (dmanow &
2490                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2491                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2492                         host->data->bytes_xfered = dmanow - dmastart;
2493                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2494                                 " next 0x%08x\n",
2495                                 mmc_hostname(host->mmc), dmastart,
2496                                 host->data->bytes_xfered, dmanow);
2497                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2498                 }
2499
2500                 if (intmask & SDHCI_INT_DATA_END) {
2501                         if (host->cmd) {
2502                                 /*
2503                                  * Data managed to finish before the
2504                                  * command completed. Make sure we do
2505                                  * things in the proper order.
2506                                  */
2507                                 host->data_early = 1;
2508                         } else {
2509                                 sdhci_finish_data(host);
2510                         }
2511                 }
2512         }
2513 }
2514
2515 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2516 {
2517         irqreturn_t result = IRQ_NONE;
2518         struct sdhci_host *host = dev_id;
2519         u32 intmask, mask, unexpected = 0;
2520         int max_loops = 16;
2521
2522         spin_lock(&host->lock);
2523
2524         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2525                 spin_unlock(&host->lock);
2526                 return IRQ_NONE;
2527         }
2528
2529         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2530         if (!intmask || intmask == 0xffffffff) {
2531                 result = IRQ_NONE;
2532                 goto out;
2533         }
2534
2535         do {
2536                 /* Clear selected interrupts. */
2537                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2538                                   SDHCI_INT_BUS_POWER);
2539                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2540
2541                 DBG("*** %s got interrupt: 0x%08x\n",
2542                         mmc_hostname(host->mmc), intmask);
2543
2544                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2545                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2546                                       SDHCI_CARD_PRESENT;
2547
2548                         /*
2549                          * There is a observation on i.mx esdhc.  INSERT
2550                          * bit will be immediately set again when it gets
2551                          * cleared, if a card is inserted.  We have to mask
2552                          * the irq to prevent interrupt storm which will
2553                          * freeze the system.  And the REMOVE gets the
2554                          * same situation.
2555                          *
2556                          * More testing are needed here to ensure it works
2557                          * for other platforms though.
2558                          */
2559                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2560                                        SDHCI_INT_CARD_REMOVE);
2561                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2562                                                SDHCI_INT_CARD_INSERT;
2563                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2564                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2565
2566                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2567                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2568
2569                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2570                                                        SDHCI_INT_CARD_REMOVE);
2571                         result = IRQ_WAKE_THREAD;
2572                 }
2573
2574                 if (intmask & SDHCI_INT_CMD_MASK)
2575                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2576                                       &intmask);
2577
2578                 if (intmask & SDHCI_INT_DATA_MASK)
2579                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2580
2581                 if (intmask & SDHCI_INT_BUS_POWER)
2582                         pr_err("%s: Card is consuming too much power!\n",
2583                                 mmc_hostname(host->mmc));
2584
2585                 if (intmask & SDHCI_INT_CARD_INT) {
2586                         sdhci_enable_sdio_irq_nolock(host, false);
2587                         host->thread_isr |= SDHCI_INT_CARD_INT;
2588                         result = IRQ_WAKE_THREAD;
2589                 }
2590
2591                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2592                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2593                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2594                              SDHCI_INT_CARD_INT);
2595
2596                 if (intmask) {
2597                         unexpected |= intmask;
2598                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2599                 }
2600
2601                 if (result == IRQ_NONE)
2602                         result = IRQ_HANDLED;
2603
2604                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2605         } while (intmask && --max_loops);
2606 out:
2607         spin_unlock(&host->lock);
2608
2609         if (unexpected) {
2610                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2611                            mmc_hostname(host->mmc), unexpected);
2612                 sdhci_dumpregs(host);
2613         }
2614
2615         return result;
2616 }
2617
2618 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2619 {
2620         struct sdhci_host *host = dev_id;
2621         unsigned long flags;
2622         u32 isr;
2623
2624         spin_lock_irqsave(&host->lock, flags);
2625         isr = host->thread_isr;
2626         host->thread_isr = 0;
2627         spin_unlock_irqrestore(&host->lock, flags);
2628
2629         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2630                 sdhci_card_event(host->mmc);
2631                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2632         }
2633
2634         if (isr & SDHCI_INT_CARD_INT) {
2635                 sdio_run_irqs(host->mmc);
2636
2637                 spin_lock_irqsave(&host->lock, flags);
2638                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2639                         sdhci_enable_sdio_irq_nolock(host, true);
2640                 spin_unlock_irqrestore(&host->lock, flags);
2641         }
2642
2643         return isr ? IRQ_HANDLED : IRQ_NONE;
2644 }
2645
2646 /*****************************************************************************\
2647  *                                                                           *
2648  * Suspend/resume                                                            *
2649  *                                                                           *
2650 \*****************************************************************************/
2651
2652 #ifdef CONFIG_PM
2653 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2654 {
2655         u8 val;
2656         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2657                         | SDHCI_WAKE_ON_INT;
2658
2659         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2660         val |= mask ;
2661         /* Avoid fake wake up */
2662         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2663                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2664         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2665 }
2666 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2667
2668 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2669 {
2670         u8 val;
2671         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2672                         | SDHCI_WAKE_ON_INT;
2673
2674         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2675         val &= ~mask;
2676         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2677 }
2678
2679 int sdhci_suspend_host(struct sdhci_host *host)
2680 {
2681         sdhci_disable_card_detection(host);
2682
2683         mmc_retune_timer_stop(host->mmc);
2684         mmc_retune_needed(host->mmc);
2685
2686         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2687                 host->ier = 0;
2688                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2689                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2690                 free_irq(host->irq, host);
2691         } else {
2692                 sdhci_enable_irq_wakeups(host);
2693                 enable_irq_wake(host->irq);
2694         }
2695         return 0;
2696 }
2697
2698 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2699
2700 int sdhci_resume_host(struct sdhci_host *host)
2701 {
2702         int ret = 0;
2703
2704         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2705                 if (host->ops->enable_dma)
2706                         host->ops->enable_dma(host);
2707         }
2708
2709         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2710             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2711                 /* Card keeps power but host controller does not */
2712                 sdhci_init(host, 0);
2713                 host->pwr = 0;
2714                 host->clock = 0;
2715                 sdhci_do_set_ios(host, &host->mmc->ios);
2716         } else {
2717                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2718                 mmiowb();
2719         }
2720
2721         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2722                 ret = request_threaded_irq(host->irq, sdhci_irq,
2723                                            sdhci_thread_irq, IRQF_SHARED,
2724                                            mmc_hostname(host->mmc), host);
2725                 if (ret)
2726                         return ret;
2727         } else {
2728                 sdhci_disable_irq_wakeups(host);
2729                 disable_irq_wake(host->irq);
2730         }
2731
2732         sdhci_enable_card_detection(host);
2733
2734         return ret;
2735 }
2736
2737 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2738
2739 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2740 {
2741         return pm_runtime_get_sync(host->mmc->parent);
2742 }
2743
2744 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2745 {
2746         pm_runtime_mark_last_busy(host->mmc->parent);
2747         return pm_runtime_put_autosuspend(host->mmc->parent);
2748 }
2749
2750 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2751 {
2752         if (host->bus_on)
2753                 return;
2754         host->bus_on = true;
2755         pm_runtime_get_noresume(host->mmc->parent);
2756 }
2757
2758 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2759 {
2760         if (!host->bus_on)
2761                 return;
2762         host->bus_on = false;
2763         pm_runtime_put_noidle(host->mmc->parent);
2764 }
2765
2766 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2767 {
2768         unsigned long flags;
2769
2770         mmc_retune_timer_stop(host->mmc);
2771         mmc_retune_needed(host->mmc);
2772
2773         spin_lock_irqsave(&host->lock, flags);
2774         host->ier &= SDHCI_INT_CARD_INT;
2775         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2776         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2777         spin_unlock_irqrestore(&host->lock, flags);
2778
2779         synchronize_hardirq(host->irq);
2780
2781         spin_lock_irqsave(&host->lock, flags);
2782         host->runtime_suspended = true;
2783         spin_unlock_irqrestore(&host->lock, flags);
2784
2785         return 0;
2786 }
2787 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2788
2789 int sdhci_runtime_resume_host(struct sdhci_host *host)
2790 {
2791         unsigned long flags;
2792         int host_flags = host->flags;
2793
2794         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2795                 if (host->ops->enable_dma)
2796                         host->ops->enable_dma(host);
2797         }
2798
2799         sdhci_init(host, 0);
2800
2801         /* Force clock and power re-program */
2802         host->pwr = 0;
2803         host->clock = 0;
2804         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2805         sdhci_do_set_ios(host, &host->mmc->ios);
2806
2807         if ((host_flags & SDHCI_PV_ENABLED) &&
2808                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2809                 spin_lock_irqsave(&host->lock, flags);
2810                 sdhci_enable_preset_value(host, true);
2811                 spin_unlock_irqrestore(&host->lock, flags);
2812         }
2813
2814         spin_lock_irqsave(&host->lock, flags);
2815
2816         host->runtime_suspended = false;
2817
2818         /* Enable SDIO IRQ */
2819         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2820                 sdhci_enable_sdio_irq_nolock(host, true);
2821
2822         /* Enable Card Detection */
2823         sdhci_enable_card_detection(host);
2824
2825         spin_unlock_irqrestore(&host->lock, flags);
2826
2827         return 0;
2828 }
2829 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2830
2831 #endif /* CONFIG_PM */
2832
2833 /*****************************************************************************\
2834  *                                                                           *
2835  * Device allocation/registration                                            *
2836  *                                                                           *
2837 \*****************************************************************************/
2838
2839 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2840         size_t priv_size)
2841 {
2842         struct mmc_host *mmc;
2843         struct sdhci_host *host;
2844
2845         WARN_ON(dev == NULL);
2846
2847         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2848         if (!mmc)
2849                 return ERR_PTR(-ENOMEM);
2850
2851         host = mmc_priv(mmc);
2852         host->mmc = mmc;
2853         host->mmc_host_ops = sdhci_ops;
2854         mmc->ops = &host->mmc_host_ops;
2855
2856         return host;
2857 }
2858
2859 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2860
2861 int sdhci_add_host(struct sdhci_host *host)
2862 {
2863         struct mmc_host *mmc;
2864         u32 caps[2] = {0, 0};
2865         u32 max_current_caps;
2866         unsigned int ocr_avail;
2867         unsigned int override_timeout_clk;
2868         u32 max_clk;
2869         int ret;
2870
2871         WARN_ON(host == NULL);
2872         if (host == NULL)
2873                 return -EINVAL;
2874
2875         mmc = host->mmc;
2876
2877         if (debug_quirks)
2878                 host->quirks = debug_quirks;
2879         if (debug_quirks2)
2880                 host->quirks2 = debug_quirks2;
2881
2882         override_timeout_clk = host->timeout_clk;
2883
2884         sdhci_do_reset(host, SDHCI_RESET_ALL);
2885
2886         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2887         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2888                                 >> SDHCI_SPEC_VER_SHIFT;
2889         if (host->version > SDHCI_SPEC_300) {
2890                 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2891                        mmc_hostname(mmc), host->version);
2892         }
2893
2894         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2895                 sdhci_readl(host, SDHCI_CAPABILITIES);
2896
2897         if (host->version >= SDHCI_SPEC_300)
2898                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2899                         host->caps1 :
2900                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2901
2902         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2903                 host->flags |= SDHCI_USE_SDMA;
2904         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2905                 DBG("Controller doesn't have SDMA capability\n");
2906         else
2907                 host->flags |= SDHCI_USE_SDMA;
2908
2909         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2910                 (host->flags & SDHCI_USE_SDMA)) {
2911                 DBG("Disabling DMA as it is marked broken\n");
2912                 host->flags &= ~SDHCI_USE_SDMA;
2913         }
2914
2915         if ((host->version >= SDHCI_SPEC_200) &&
2916                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2917                 host->flags |= SDHCI_USE_ADMA;
2918
2919         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2920                 (host->flags & SDHCI_USE_ADMA)) {
2921                 DBG("Disabling ADMA as it is marked broken\n");
2922                 host->flags &= ~SDHCI_USE_ADMA;
2923         }
2924
2925         /*
2926          * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2927          * and *must* do 64-bit DMA.  A driver has the opportunity to change
2928          * that during the first call to ->enable_dma().  Similarly
2929          * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2930          * implement.
2931          */
2932         if (caps[0] & SDHCI_CAN_64BIT)
2933                 host->flags |= SDHCI_USE_64_BIT_DMA;
2934
2935         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2936                 if (host->ops->enable_dma) {
2937                         if (host->ops->enable_dma(host)) {
2938                                 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2939                                         mmc_hostname(mmc));
2940                                 host->flags &=
2941                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2942                         }
2943                 }
2944         }
2945
2946         /* SDMA does not support 64-bit DMA */
2947         if (host->flags & SDHCI_USE_64_BIT_DMA)
2948                 host->flags &= ~SDHCI_USE_SDMA;
2949
2950         if (host->flags & SDHCI_USE_ADMA) {
2951                 /*
2952                  * The DMA descriptor table size is calculated as the maximum
2953                  * number of segments times 2, to allow for an alignment
2954                  * descriptor for each segment, plus 1 for a nop end descriptor,
2955                  * all multipled by the descriptor size.
2956                  */
2957                 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2958                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2959                                               SDHCI_ADMA2_64_DESC_SZ;
2960                         host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2961                 } else {
2962                         host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2963                                               SDHCI_ADMA2_32_DESC_SZ;
2964                         host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2965                 }
2966                 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2967                                                       host->adma_table_sz,
2968                                                       &host->adma_addr,
2969                                                       GFP_KERNEL);
2970                 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2971                 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2972                 if (!host->adma_table || !host->align_buffer) {
2973                         if (host->adma_table)
2974                                 dma_free_coherent(mmc_dev(mmc),
2975                                                   host->adma_table_sz,
2976                                                   host->adma_table,
2977                                                   host->adma_addr);
2978                         kfree(host->align_buffer);
2979                         pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2980                                 mmc_hostname(mmc));
2981                         host->flags &= ~SDHCI_USE_ADMA;
2982                         host->adma_table = NULL;
2983                         host->align_buffer = NULL;
2984                 } else if (host->adma_addr & (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2985                         pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2986                                 mmc_hostname(mmc));
2987                         host->flags &= ~SDHCI_USE_ADMA;
2988                         dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2989                                           host->adma_table, host->adma_addr);
2990                         kfree(host->align_buffer);
2991                         host->adma_table = NULL;
2992                         host->align_buffer = NULL;
2993                 }
2994         }
2995
2996         /*
2997          * If we use DMA, then it's up to the caller to set the DMA
2998          * mask, but PIO does not need the hw shim so we set a new
2999          * mask here in that case.
3000          */
3001         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
3002                 host->dma_mask = DMA_BIT_MASK(64);
3003                 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3004         }
3005
3006         if (host->version >= SDHCI_SPEC_300)
3007                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3008                         >> SDHCI_CLOCK_BASE_SHIFT;
3009         else
3010                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3011                         >> SDHCI_CLOCK_BASE_SHIFT;
3012
3013         host->max_clk *= 1000000;
3014         if (host->max_clk == 0 || host->quirks &
3015                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3016                 if (!host->ops->get_max_clock) {
3017                         pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3018                                mmc_hostname(mmc));
3019                         return -ENODEV;
3020                 }
3021                 host->max_clk = host->ops->get_max_clock(host);
3022         }
3023
3024         /*
3025          * In case of Host Controller v3.00, find out whether clock
3026          * multiplier is supported.
3027          */
3028         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3029                         SDHCI_CLOCK_MUL_SHIFT;
3030
3031         /*
3032          * In case the value in Clock Multiplier is 0, then programmable
3033          * clock mode is not supported, otherwise the actual clock
3034          * multiplier is one more than the value of Clock Multiplier
3035          * in the Capabilities Register.
3036          */
3037         if (host->clk_mul)
3038                 host->clk_mul += 1;
3039
3040         /*
3041          * Set host parameters.
3042          */
3043         max_clk = host->max_clk;
3044
3045         if (host->ops->get_min_clock)
3046                 mmc->f_min = host->ops->get_min_clock(host);
3047         else if (host->version >= SDHCI_SPEC_300) {
3048                 if (host->clk_mul) {
3049                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3050                         max_clk = host->max_clk * host->clk_mul;
3051                 } else
3052                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3053         } else
3054                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3055
3056         if (!mmc->f_max || (mmc->f_max && (mmc->f_max > max_clk)))
3057                 mmc->f_max = max_clk;
3058
3059         if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3060                 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3061                                         SDHCI_TIMEOUT_CLK_SHIFT;
3062                 if (host->timeout_clk == 0) {
3063                         if (host->ops->get_timeout_clock) {
3064                                 host->timeout_clk =
3065                                         host->ops->get_timeout_clock(host);
3066                         } else {
3067                                 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3068                                         mmc_hostname(mmc));
3069                                 return -ENODEV;
3070                         }
3071                 }
3072
3073                 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3074                         host->timeout_clk *= 1000;
3075
3076                 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3077                         host->ops->get_max_timeout_count(host) : 1 << 27;
3078                 mmc->max_busy_timeout /= host->timeout_clk;
3079         }
3080
3081         if (override_timeout_clk)
3082                 host->timeout_clk = override_timeout_clk;
3083
3084         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3085         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3086
3087         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3088                 host->flags |= SDHCI_AUTO_CMD12;
3089
3090         /* Auto-CMD23 stuff only works in ADMA or PIO. */
3091         if ((host->version >= SDHCI_SPEC_300) &&
3092             ((host->flags & SDHCI_USE_ADMA) ||
3093              !(host->flags & SDHCI_USE_SDMA)) &&
3094              !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3095                 host->flags |= SDHCI_AUTO_CMD23;
3096                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3097         } else {
3098                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3099         }
3100
3101         /*
3102          * A controller may support 8-bit width, but the board itself
3103          * might not have the pins brought out.  Boards that support
3104          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3105          * their platform code before calling sdhci_add_host(), and we
3106          * won't assume 8-bit width for hosts without that CAP.
3107          */
3108         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3109                 mmc->caps |= MMC_CAP_4_BIT_DATA;
3110
3111         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3112                 mmc->caps &= ~MMC_CAP_CMD23;
3113
3114         if (caps[0] & SDHCI_CAN_DO_HISPD)
3115                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3116
3117         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3118             !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3119             IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3120                 mmc->caps |= MMC_CAP_NEEDS_POLL;
3121
3122         /* If there are external regulators, get them */
3123         if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3124                 return -EPROBE_DEFER;
3125
3126         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3127         if (!IS_ERR(mmc->supply.vqmmc)) {
3128                 ret = regulator_enable(mmc->supply.vqmmc);
3129                 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3130                                                     1950000))
3131                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3132                                         SDHCI_SUPPORT_SDR50 |
3133                                         SDHCI_SUPPORT_DDR50);
3134                 if (ret) {
3135                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3136                                 mmc_hostname(mmc), ret);
3137                         mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3138                 }
3139         }
3140
3141         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3142                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3143                        SDHCI_SUPPORT_DDR50);
3144
3145         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3146         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3147                        SDHCI_SUPPORT_DDR50))
3148                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3149
3150         /* SDR104 supports also implies SDR50 support */
3151         if (caps[1] & SDHCI_SUPPORT_SDR104) {
3152                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3153                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3154                  * field can be promoted to support HS200.
3155                  */
3156                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3157                         mmc->caps2 |= MMC_CAP2_HS200;
3158         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3159                 mmc->caps |= MMC_CAP_UHS_SDR50;
3160
3161         if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3162             (caps[1] & SDHCI_SUPPORT_HS400))
3163                 mmc->caps2 |= MMC_CAP2_HS400;
3164
3165         if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3166             (IS_ERR(mmc->supply.vqmmc) ||
3167              !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3168                                              1300000)))
3169                 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3170
3171         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3172                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3173                 mmc->caps |= MMC_CAP_UHS_DDR50;
3174
3175         /* Does the host need tuning for SDR50? */
3176         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3177                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3178
3179         /* Does the host need tuning for SDR104 / HS200? */
3180         if (mmc->caps2 & MMC_CAP2_HS200)
3181                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3182
3183         /* Driver Type(s) (A, C, D) supported by the host */
3184         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3185                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3186         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3187                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3188         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3189                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3190
3191         /* Initial value for re-tuning timer count */
3192         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3193                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3194
3195         /*
3196          * In case Re-tuning Timer is not disabled, the actual value of
3197          * re-tuning timer will be 2 ^ (n - 1).
3198          */
3199         if (host->tuning_count)
3200                 host->tuning_count = 1 << (host->tuning_count - 1);
3201
3202         /* Re-tuning mode supported by the Host Controller */
3203         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3204                              SDHCI_RETUNING_MODE_SHIFT;
3205
3206         ocr_avail = 0;
3207
3208         /*
3209          * According to SD Host Controller spec v3.00, if the Host System
3210          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3211          * the value is meaningful only if Voltage Support in the Capabilities
3212          * register is set. The actual current value is 4 times the register
3213          * value.
3214          */
3215         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3216         if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3217                 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3218                 if (curr > 0) {
3219
3220                         /* convert to SDHCI_MAX_CURRENT format */
3221                         curr = curr/1000;  /* convert to mA */
3222                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3223
3224                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3225                         max_current_caps =
3226                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3227                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3228                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3229                 }
3230         }
3231
3232         if (caps[0] & SDHCI_CAN_VDD_330) {
3233                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3234
3235                 mmc->max_current_330 = ((max_current_caps &
3236                                    SDHCI_MAX_CURRENT_330_MASK) >>
3237                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3238                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3239         }
3240         if (caps[0] & SDHCI_CAN_VDD_300) {
3241                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3242
3243                 mmc->max_current_300 = ((max_current_caps &
3244                                    SDHCI_MAX_CURRENT_300_MASK) >>
3245                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3246                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3247         }
3248         if (caps[0] & SDHCI_CAN_VDD_180) {
3249                 ocr_avail |= MMC_VDD_165_195;
3250
3251                 mmc->max_current_180 = ((max_current_caps &
3252                                    SDHCI_MAX_CURRENT_180_MASK) >>
3253                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3254                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3255         }
3256
3257         /* If OCR set by host, use it instead. */
3258         if (host->ocr_mask)
3259                 ocr_avail = host->ocr_mask;
3260
3261         /* If OCR set by external regulators, give it highest prio. */
3262         if (mmc->ocr_avail)
3263                 ocr_avail = mmc->ocr_avail;
3264
3265         mmc->ocr_avail = ocr_avail;
3266         mmc->ocr_avail_sdio = ocr_avail;
3267         if (host->ocr_avail_sdio)
3268                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3269         mmc->ocr_avail_sd = ocr_avail;
3270         if (host->ocr_avail_sd)
3271                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3272         else /* normal SD controllers don't support 1.8V */
3273                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3274         mmc->ocr_avail_mmc = ocr_avail;
3275         if (host->ocr_avail_mmc)
3276                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3277
3278         if (mmc->ocr_avail == 0) {
3279                 pr_err("%s: Hardware doesn't report any support voltages.\n",
3280                        mmc_hostname(mmc));
3281                 return -ENODEV;
3282         }
3283
3284         spin_lock_init(&host->lock);
3285
3286         /*
3287          * Maximum number of segments. Depends on if the hardware
3288          * can do scatter/gather or not.
3289          */
3290         if (host->flags & SDHCI_USE_ADMA)
3291                 mmc->max_segs = SDHCI_MAX_SEGS;
3292         else if (host->flags & SDHCI_USE_SDMA)
3293                 mmc->max_segs = 1;
3294         else /* PIO */
3295                 mmc->max_segs = SDHCI_MAX_SEGS;
3296
3297         /*
3298          * Maximum number of sectors in one transfer. Limited by SDMA boundary
3299          * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3300          * is less anyway.
3301          */
3302         mmc->max_req_size = 524288;
3303
3304         /*
3305          * Maximum segment size. Could be one segment with the maximum number
3306          * of bytes. When doing hardware scatter/gather, each entry cannot
3307          * be larger than 64 KiB though.
3308          */
3309         if (host->flags & SDHCI_USE_ADMA) {
3310                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3311                         mmc->max_seg_size = 65535;
3312                 else
3313                         mmc->max_seg_size = 65536;
3314         } else {
3315                 mmc->max_seg_size = mmc->max_req_size;
3316         }
3317
3318         /*
3319          * Maximum block size. This varies from controller to controller and
3320          * is specified in the capabilities register.
3321          */
3322         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3323                 mmc->max_blk_size = 2;
3324         } else {
3325                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3326                                 SDHCI_MAX_BLOCK_SHIFT;
3327                 if (mmc->max_blk_size >= 3) {
3328                         pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3329                                 mmc_hostname(mmc));
3330                         mmc->max_blk_size = 0;
3331                 }
3332         }
3333
3334         mmc->max_blk_size = 512 << mmc->max_blk_size;
3335
3336         /*
3337          * Maximum block count.
3338          */
3339         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3340
3341         /*
3342          * Init tasklets.
3343          */
3344         tasklet_init(&host->finish_tasklet,
3345                 sdhci_tasklet_finish, (unsigned long)host);
3346
3347         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3348
3349         init_waitqueue_head(&host->buf_ready_int);
3350
3351         sdhci_init(host, 0);
3352
3353         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3354                                    IRQF_SHARED, mmc_hostname(mmc), host);
3355         if (ret) {
3356                 pr_err("%s: Failed to request IRQ %d: %d\n",
3357                        mmc_hostname(mmc), host->irq, ret);
3358                 goto untasklet;
3359         }
3360
3361 #ifdef CONFIG_MMC_DEBUG
3362         sdhci_dumpregs(host);
3363 #endif
3364
3365 #ifdef SDHCI_USE_LEDS_CLASS
3366         snprintf(host->led_name, sizeof(host->led_name),
3367                 "%s::", mmc_hostname(mmc));
3368         host->led.name = host->led_name;
3369         host->led.brightness = LED_OFF;
3370         host->led.default_trigger = mmc_hostname(mmc);
3371         host->led.brightness_set = sdhci_led_control;
3372
3373         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3374         if (ret) {
3375                 pr_err("%s: Failed to register LED device: %d\n",
3376                        mmc_hostname(mmc), ret);
3377                 goto reset;
3378         }
3379 #endif
3380
3381         mmiowb();
3382
3383         mmc_add_host(mmc);
3384
3385         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3386                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3387                 (host->flags & SDHCI_USE_ADMA) ?
3388                 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3389                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3390
3391         sdhci_enable_card_detection(host);
3392
3393         return 0;
3394
3395 #ifdef SDHCI_USE_LEDS_CLASS
3396 reset:
3397         sdhci_do_reset(host, SDHCI_RESET_ALL);
3398         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3399         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3400         free_irq(host->irq, host);
3401 #endif
3402 untasklet:
3403         tasklet_kill(&host->finish_tasklet);
3404
3405         return ret;
3406 }
3407
3408 EXPORT_SYMBOL_GPL(sdhci_add_host);
3409
3410 void sdhci_remove_host(struct sdhci_host *host, int dead)
3411 {
3412         struct mmc_host *mmc = host->mmc;
3413         unsigned long flags;
3414
3415         if (dead) {
3416                 spin_lock_irqsave(&host->lock, flags);
3417
3418                 host->flags |= SDHCI_DEVICE_DEAD;
3419
3420                 if (host->mrq) {
3421                         pr_err("%s: Controller removed during "
3422                                 " transfer!\n", mmc_hostname(mmc));
3423
3424                         host->mrq->cmd->error = -ENOMEDIUM;
3425                         tasklet_schedule(&host->finish_tasklet);
3426                 }
3427
3428                 spin_unlock_irqrestore(&host->lock, flags);
3429         }
3430
3431         sdhci_disable_card_detection(host);
3432
3433         mmc_remove_host(mmc);
3434
3435 #ifdef SDHCI_USE_LEDS_CLASS
3436         led_classdev_unregister(&host->led);
3437 #endif
3438
3439         if (!dead)
3440                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3441
3442         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3443         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3444         free_irq(host->irq, host);
3445
3446         del_timer_sync(&host->timer);
3447
3448         tasklet_kill(&host->finish_tasklet);
3449
3450         if (!IS_ERR(mmc->supply.vqmmc))
3451                 regulator_disable(mmc->supply.vqmmc);
3452
3453         if (host->adma_table)
3454                 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3455                                   host->adma_table, host->adma_addr);
3456         kfree(host->align_buffer);
3457
3458         host->adma_table = NULL;
3459         host->align_buffer = NULL;
3460 }
3461
3462 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3463
3464 void sdhci_free_host(struct sdhci_host *host)
3465 {
3466         mmc_free_host(host->mmc);
3467 }
3468
3469 EXPORT_SYMBOL_GPL(sdhci_free_host);
3470
3471 /*****************************************************************************\
3472  *                                                                           *
3473  * Driver init/exit                                                          *
3474  *                                                                           *
3475 \*****************************************************************************/
3476
3477 static int __init sdhci_drv_init(void)
3478 {
3479         pr_info(DRIVER_NAME
3480                 ": Secure Digital Host Controller Interface driver\n");
3481         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3482
3483         return 0;
3484 }
3485
3486 static void __exit sdhci_drv_exit(void)
3487 {
3488 }
3489
3490 module_init(sdhci_drv_init);
3491 module_exit(sdhci_drv_exit);
3492
3493 module_param(debug_quirks, uint, 0444);
3494 module_param(debug_quirks2, uint, 0444);
3495
3496 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3497 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3498 MODULE_LICENSE("GPL");
3499
3500 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3501 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");