drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 static unsigned int debug_quirks = 0;
  48 static unsigned int debug_quirks2;
  49
  50 static void sdhci_finish_data(struct sdhci_host *);
  51
  52 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  53 static void sdhci_finish_command(struct sdhci_host *);
  54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  55 static void sdhci_tuning_timer(unsigned long data);
  56 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  57
  58 #ifdef CONFIG_PM_RUNTIME
  59 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  60 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  61 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  62 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  63 #else
  64 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  65 {
  66         return 0;
  67 }
  68 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  69 {
  70         return 0;
  71 }
  72 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  73 {
  74 }
  75 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  76 {
  77 }
  78 #endif
  79
  80 static void sdhci_dumpregs(struct sdhci_host *host)
  81 {
  82         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  83                 mmc_hostname(host->mmc));
  84
  85         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  86                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  87                 sdhci_readw(host, SDHCI_HOST_VERSION));
  88         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  89                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  90                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  91         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  92                 sdhci_readl(host, SDHCI_ARGUMENT),
  93                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  94         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  95                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  96                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  97         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  98                 sdhci_readb(host, SDHCI_POWER_CONTROL),
  99                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 100         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 101                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 102                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 103         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 104                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 105                 sdhci_readl(host, SDHCI_INT_STATUS));
 106         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 107                 sdhci_readl(host, SDHCI_INT_ENABLE),
 108                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 109         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 110                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 111                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 112         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 113                 sdhci_readl(host, SDHCI_CAPABILITIES),
 114                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 115         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 116                 sdhci_readw(host, SDHCI_COMMAND),
 117                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 118         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 119                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 120
 121         if (host->flags & SDHCI_USE_ADMA)
 122                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 123                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 124                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 125
 126         pr_debug(DRIVER_NAME ": ===========================================\n");
 127 }
 128
 129 /*****************************************************************************\
 130  *                                                                           *
 131  * Low level functions                                                       *
 132  *                                                                           *
 133 \*****************************************************************************/
 134
 135 static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set)
 136 {
 137         u32 ier;
 138
 139         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 140         ier &= ~clear;
 141         ier |= set;
 142         sdhci_writel(host, ier, SDHCI_INT_ENABLE);
 143         sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
 144 }
 145
 146 static void sdhci_unmask_irqs(struct sdhci_host *host, u32 irqs)
 147 {
 148         sdhci_clear_set_irqs(host, 0, irqs);
 149 }
 150
 151 static void sdhci_mask_irqs(struct sdhci_host *host, u32 irqs)
 152 {
 153         sdhci_clear_set_irqs(host, irqs, 0);
 154 }
 155
 156 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 157 {
 158         u32 present, irqs;
 159
 160         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 161             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 162                 return;
 163
 164         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 165                               SDHCI_CARD_PRESENT;
 166         irqs = present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT;
 167
 168         if (enable)
 169                 sdhci_unmask_irqs(host, irqs);
 170         else
 171                 sdhci_mask_irqs(host, irqs);
 172 }
 173
 174 static void sdhci_enable_card_detection(struct sdhci_host *host)
 175 {
 176         sdhci_set_card_detection(host, true);
 177 }
 178
 179 static void sdhci_disable_card_detection(struct sdhci_host *host)
 180 {
 181         sdhci_set_card_detection(host, false);
 182 }
 183
 184 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 185 {
 186         unsigned long timeout;
 187         u32 uninitialized_var(ier);
 188
 189         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 190                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 191                         SDHCI_CARD_PRESENT))
 192                         return;
 193         }
 194
 195         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 196                 ier = sdhci_readl(host, SDHCI_INT_ENABLE);
 197
 198         if (host->ops->platform_reset_enter)
 199                 host->ops->platform_reset_enter(host, mask);
 200
 201         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 202
 203         if (mask & SDHCI_RESET_ALL) {
 204                 host->clock = 0;
 205                 /* Reset-all turns off SD Bus Power */
 206                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 207                         sdhci_runtime_pm_bus_off(host);
 208         }
 209
 210         /* Wait max 100 ms */
 211         timeout = 100;
 212
 213         /* hw clears the bit when it's done */
 214         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 215                 if (timeout == 0) {
 216                         pr_err("%s: Reset 0x%x never completed.\n",
 217                                 mmc_hostname(host->mmc), (int)mask);
 218                         sdhci_dumpregs(host);
 219                         return;
 220                 }
 221                 timeout--;
 222                 mdelay(1);
 223         }
 224
 225         if (host->ops->platform_reset_exit)
 226                 host->ops->platform_reset_exit(host, mask);
 227
 228         if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
 229                 sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
 230
 231         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 232                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 233                         host->ops->enable_dma(host);
 234         }
 235 }
 236
 237 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 238
 239 static void sdhci_init(struct sdhci_host *host, int soft)
 240 {
 241         if (soft)
 242                 sdhci_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 243         else
 244                 sdhci_reset(host, SDHCI_RESET_ALL);
 245
 246         sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK,
 247                 SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 248                 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
 249                 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
 250                 SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE);
 251
 252         if (soft) {
 253                 /* force clock reconfiguration */
 254                 host->clock = 0;
 255                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 256         }
 257 }
 258
 259 static void sdhci_reinit(struct sdhci_host *host)
 260 {
 261         sdhci_init(host, 0);
 262         /*
 263          * Retuning stuffs are affected by different cards inserted and only
 264          * applicable to UHS-I cards. So reset these fields to their initial
 265          * value when card is removed.
 266          */
 267         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 268                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 269
 270                 del_timer_sync(&host->tuning_timer);
 271                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 272                 host->mmc->max_blk_count =
 273                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 274         }
 275         sdhci_enable_card_detection(host);
 276 }
 277
 278 static void sdhci_activate_led(struct sdhci_host *host)
 279 {
 280         u8 ctrl;
 281
 282         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 283         ctrl |= SDHCI_CTRL_LED;
 284         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 285 }
 286
 287 static void sdhci_deactivate_led(struct sdhci_host *host)
 288 {
 289         u8 ctrl;
 290
 291         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 292         ctrl &= ~SDHCI_CTRL_LED;
 293         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 294 }
 295
 296 #ifdef SDHCI_USE_LEDS_CLASS
 297 static void sdhci_led_control(struct led_classdev *led,
 298         enum led_brightness brightness)
 299 {
 300         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 301         unsigned long flags;
 302
 303         spin_lock_irqsave(&host->lock, flags);
 304
 305         if (host->runtime_suspended)
 306                 goto out;
 307
 308         if (brightness == LED_OFF)
 309                 sdhci_deactivate_led(host);
 310         else
 311                 sdhci_activate_led(host);
 312 out:
 313         spin_unlock_irqrestore(&host->lock, flags);
 314 }
 315 #endif
 316
 317 /*****************************************************************************\
 318  *                                                                           *
 319  * Core functions                                                            *
 320  *                                                                           *
 321 \*****************************************************************************/
 322
 323 static void sdhci_read_block_pio(struct sdhci_host *host)
 324 {
 325         unsigned long flags;
 326         size_t blksize, len, chunk;
 327         u32 uninitialized_var(scratch);
 328         u8 *buf;
 329
 330         DBG("PIO reading\n");
 331
 332         blksize = host->data->blksz;
 333         chunk = 0;
 334
 335         local_irq_save(flags);
 336
 337         while (blksize) {
 338                 if (!sg_miter_next(&host->sg_miter))
 339                         BUG();
 340
 341                 len = min(host->sg_miter.length, blksize);
 342
 343                 blksize -= len;
 344                 host->sg_miter.consumed = len;
 345
 346                 buf = host->sg_miter.addr;
 347
 348                 while (len) {
 349                         if (chunk == 0) {
 350                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 351                                 chunk = 4;
 352                         }
 353
 354                         *buf = scratch & 0xFF;
 355
 356                         buf++;
 357                         scratch >>= 8;
 358                         chunk--;
 359                         len--;
 360                 }
 361         }
 362
 363         sg_miter_stop(&host->sg_miter);
 364
 365         local_irq_restore(flags);
 366 }
 367
 368 static void sdhci_write_block_pio(struct sdhci_host *host)
 369 {
 370         unsigned long flags;
 371         size_t blksize, len, chunk;
 372         u32 scratch;
 373         u8 *buf;
 374
 375         DBG("PIO writing\n");
 376
 377         blksize = host->data->blksz;
 378         chunk = 0;
 379         scratch = 0;
 380
 381         local_irq_save(flags);
 382
 383         while (blksize) {
 384                 if (!sg_miter_next(&host->sg_miter))
 385                         BUG();
 386
 387                 len = min(host->sg_miter.length, blksize);
 388
 389                 blksize -= len;
 390                 host->sg_miter.consumed = len;
 391
 392                 buf = host->sg_miter.addr;
 393
 394                 while (len) {
 395                         scratch |= (u32)*buf << (chunk * 8);
 396
 397                         buf++;
 398                         chunk++;
 399                         len--;
 400
 401                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 402                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 403                                 chunk = 0;
 404                                 scratch = 0;
 405                         }
 406                 }
 407         }
 408
 409         sg_miter_stop(&host->sg_miter);
 410
 411         local_irq_restore(flags);
 412 }
 413
 414 static void sdhci_transfer_pio(struct sdhci_host *host)
 415 {
 416         u32 mask;
 417
 418         BUG_ON(!host->data);
 419
 420         if (host->blocks == 0)
 421                 return;
 422
 423         if (host->data->flags & MMC_DATA_READ)
 424                 mask = SDHCI_DATA_AVAILABLE;
 425         else
 426                 mask = SDHCI_SPACE_AVAILABLE;
 427
 428         /*
 429          * Some controllers (JMicron JMB38x) mess up the buffer bits
 430          * for transfers < 4 bytes. As long as it is just one block,
 431          * we can ignore the bits.
 432          */
 433         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 434                 (host->data->blocks == 1))
 435                 mask = ~0;
 436
 437         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 438                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 439                         udelay(100);
 440
 441                 if (host->data->flags & MMC_DATA_READ)
 442                         sdhci_read_block_pio(host);
 443                 else
 444                         sdhci_write_block_pio(host);
 445
 446                 host->blocks--;
 447                 if (host->blocks == 0)
 448                         break;
 449         }
 450
 451         DBG("PIO transfer complete.\n");
 452 }
 453
 454 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 455 {
 456         local_irq_save(*flags);
 457         return kmap_atomic(sg_page(sg)) + sg->offset;
 458 }
 459
 460 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 461 {
 462         kunmap_atomic(buffer);
 463         local_irq_restore(*flags);
 464 }
 465
 466 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 467 {
 468         __le32 *dataddr = (__le32 __force *)(desc + 4);
 469         __le16 *cmdlen = (__le16 __force *)desc;
 470
 471         /* SDHCI specification says ADMA descriptors should be 4 byte
 472          * aligned, so using 16 or 32bit operations should be safe. */
 473
 474         cmdlen[0] = cpu_to_le16(cmd);
 475         cmdlen[1] = cpu_to_le16(len);
 476
 477         dataddr[0] = cpu_to_le32(addr);
 478 }
 479
 480 static int sdhci_adma_table_pre(struct sdhci_host *host,
 481         struct mmc_data *data)
 482 {
 483         int direction;
 484
 485         u8 *desc;
 486         u8 *align;
 487         dma_addr_t addr;
 488         dma_addr_t align_addr;
 489         int len, offset;
 490
 491         struct scatterlist *sg;
 492         int i;
 493         char *buffer;
 494         unsigned long flags;
 495
 496         /*
 497          * The spec does not specify endianness of descriptor table.
 498          * We currently guess that it is LE.
 499          */
 500
 501         if (data->flags & MMC_DATA_READ)
 502                 direction = DMA_FROM_DEVICE;
 503         else
 504                 direction = DMA_TO_DEVICE;
 505
 506         /*
 507          * The ADMA descriptor table is mapped further down as we
 508          * need to fill it with data first.
 509          */
 510
 511         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 512                 host->align_buffer, 128 * 4, direction);
 513         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 514                 goto fail;
 515         BUG_ON(host->align_addr & 0x3);
 516
 517         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 518                 data->sg, data->sg_len, direction);
 519         if (host->sg_count == 0)
 520                 goto unmap_align;
 521
 522         desc = host->adma_desc;
 523         align = host->align_buffer;
 524
 525         align_addr = host->align_addr;
 526
 527         for_each_sg(data->sg, sg, host->sg_count, i) {
 528                 addr = sg_dma_address(sg);
 529                 len = sg_dma_len(sg);
 530
 531                 /*
 532                  * The SDHCI specification states that ADMA
 533                  * addresses must be 32-bit aligned. If they
 534                  * aren't, then we use a bounce buffer for
 535                  * the (up to three) bytes that screw up the
 536                  * alignment.
 537                  */
 538                 offset = (4 - (addr & 0x3)) & 0x3;
 539                 if (offset) {
 540                         if (data->flags & MMC_DATA_WRITE) {
 541                                 buffer = sdhci_kmap_atomic(sg, &flags);
 542                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 543                                 memcpy(align, buffer, offset);
 544                                 sdhci_kunmap_atomic(buffer, &flags);
 545                         }
 546
 547                         /* tran, valid */
 548                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 549
 550                         BUG_ON(offset > 65536);
 551
 552                         align += 4;
 553                         align_addr += 4;
 554
 555                         desc += 8;
 556
 557                         addr += offset;
 558                         len -= offset;
 559                 }
 560
 561                 BUG_ON(len > 65536);
 562
 563                 /* tran, valid */
 564                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 565                 desc += 8;
 566
 567                 /*
 568                  * If this triggers then we have a calculation bug
 569                  * somewhere. :/
 570                  */
 571                 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
 572         }
 573
 574         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 575                 /*
 576                 * Mark the last descriptor as the terminating descriptor
 577                 */
 578                 if (desc != host->adma_desc) {
 579                         desc -= 8;
 580                         desc[0] |= 0x2; /* end */
 581                 }
 582         } else {
 583                 /*
 584                 * Add a terminating entry.
 585                 */
 586
 587                 /* nop, end, valid */
 588                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 589         }
 590
 591         /*
 592          * Resync align buffer as we might have changed it.
 593          */
 594         if (data->flags & MMC_DATA_WRITE) {
 595                 dma_sync_single_for_device(mmc_dev(host->mmc),
 596                         host->align_addr, 128 * 4, direction);
 597         }
 598
 599         host->adma_addr = dma_map_single(mmc_dev(host->mmc),
 600                 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 601         if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
 602                 goto unmap_entries;
 603         BUG_ON(host->adma_addr & 0x3);
 604
 605         return 0;
 606
 607 unmap_entries:
 608         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 609                 data->sg_len, direction);
 610 unmap_align:
 611         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 612                 128 * 4, direction);
 613 fail:
 614         return -EINVAL;
 615 }
 616
 617 static void sdhci_adma_table_post(struct sdhci_host *host,
 618         struct mmc_data *data)
 619 {
 620         int direction;
 621
 622         struct scatterlist *sg;
 623         int i, size;
 624         u8 *align;
 625         char *buffer;
 626         unsigned long flags;
 627
 628         if (data->flags & MMC_DATA_READ)
 629                 direction = DMA_FROM_DEVICE;
 630         else
 631                 direction = DMA_TO_DEVICE;
 632
 633         dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
 634                 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
 635
 636         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 637                 128 * 4, direction);
 638
 639         if (data->flags & MMC_DATA_READ) {
 640                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 641                         data->sg_len, direction);
 642
 643                 align = host->align_buffer;
 644
 645                 for_each_sg(data->sg, sg, host->sg_count, i) {
 646                         if (sg_dma_address(sg) & 0x3) {
 647                                 size = 4 - (sg_dma_address(sg) & 0x3);
 648
 649                                 buffer = sdhci_kmap_atomic(sg, &flags);
 650                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 651                                 memcpy(buffer, align, size);
 652                                 sdhci_kunmap_atomic(buffer, &flags);
 653
 654                                 align += 4;
 655                         }
 656                 }
 657         }
 658
 659         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 660                 data->sg_len, direction);
 661 }
 662
 663 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 664 {
 665         u8 count;
 666         struct mmc_data *data = cmd->data;
 667         unsigned target_timeout, current_timeout;
 668
 669         /*
 670          * If the host controller provides us with an incorrect timeout
 671          * value, just skip the check and use 0xE.  The hardware may take
 672          * longer to time out, but that's much better than having a too-short
 673          * timeout value.
 674          */
 675         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 676                 return 0xE;
 677
 678         /* Unspecified timeout, assume max */
 679         if (!data && !cmd->cmd_timeout_ms)
 680                 return 0xE;
 681
 682         /* timeout in us */
 683         if (!data)
 684                 target_timeout = cmd->cmd_timeout_ms * 1000;
 685         else {
 686                 target_timeout = data->timeout_ns / 1000;
 687                 if (host->clock)
 688                         target_timeout += data->timeout_clks / host->clock;
 689         }
 690
 691         /*
 692          * Figure out needed cycles.
 693          * We do this in steps in order to fit inside a 32 bit int.
 694          * The first step is the minimum timeout, which will have a
 695          * minimum resolution of 6 bits:
 696          * (1) 2^13*1000 > 2^22,
 697          * (2) host->timeout_clk < 2^16
 698          *     =>
 699          *     (1) / (2) > 2^6
 700          */
 701         count = 0;
 702         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 703         while (current_timeout < target_timeout) {
 704                 count++;
 705                 current_timeout <<= 1;
 706                 if (count >= 0xF)
 707                         break;
 708         }
 709
 710         if (count >= 0xF) {
 711                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 712                     mmc_hostname(host->mmc), count, cmd->opcode);
 713                 count = 0xE;
 714         }
 715
 716         return count;
 717 }
 718
 719 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 720 {
 721         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 722         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 723
 724         if (host->flags & SDHCI_REQ_USE_DMA)
 725                 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
 726         else
 727                 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
 728 }
 729
 730 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 731 {
 732         u8 count;
 733         u8 ctrl;
 734         struct mmc_data *data = cmd->data;
 735         int ret;
 736
 737         WARN_ON(host->data);
 738
 739         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 740                 count = sdhci_calc_timeout(host, cmd);
 741                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 742         }
 743
 744         if (!data)
 745                 return;
 746
 747         /* Sanity checks */
 748         BUG_ON(data->blksz * data->blocks > 524288);
 749         BUG_ON(data->blksz > host->mmc->max_blk_size);
 750         BUG_ON(data->blocks > 65535);
 751
 752         host->data = data;
 753         host->data_early = 0;
 754         host->data->bytes_xfered = 0;
 755
 756         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 757                 host->flags |= SDHCI_REQ_USE_DMA;
 758
 759         /*
 760          * FIXME: This doesn't account for merging when mapping the
 761          * scatterlist.
 762          */
 763         if (host->flags & SDHCI_REQ_USE_DMA) {
 764                 int broken, i;
 765                 struct scatterlist *sg;
 766
 767                 broken = 0;
 768                 if (host->flags & SDHCI_USE_ADMA) {
 769                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 770                                 broken = 1;
 771                 } else {
 772                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 773                                 broken = 1;
 774                 }
 775
 776                 if (unlikely(broken)) {
 777                         for_each_sg(data->sg, sg, data->sg_len, i) {
 778                                 if (sg->length & 0x3) {
 779                                         DBG("Reverting to PIO because of "
 780                                                 "transfer size (%d)\n",
 781                                                 sg->length);
 782                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 783                                         break;
 784                                 }
 785                         }
 786                 }
 787         }
 788
 789         /*
 790          * The assumption here being that alignment is the same after
 791          * translation to device address space.
 792          */
 793         if (host->flags & SDHCI_REQ_USE_DMA) {
 794                 int broken, i;
 795                 struct scatterlist *sg;
 796
 797                 broken = 0;
 798                 if (host->flags & SDHCI_USE_ADMA) {
 799                         /*
 800                          * As we use 3 byte chunks to work around
 801                          * alignment problems, we need to check this
 802                          * quirk.
 803                          */
 804                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 805                                 broken = 1;
 806                 } else {
 807                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 808                                 broken = 1;
 809                 }
 810
 811                 if (unlikely(broken)) {
 812                         for_each_sg(data->sg, sg, data->sg_len, i) {
 813                                 if (sg->offset & 0x3) {
 814                                         DBG("Reverting to PIO because of "
 815                                                 "bad alignment\n");
 816                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 817                                         break;
 818                                 }
 819                         }
 820                 }
 821         }
 822
 823         if (host->flags & SDHCI_REQ_USE_DMA) {
 824                 if (host->flags & SDHCI_USE_ADMA) {
 825                         ret = sdhci_adma_table_pre(host, data);
 826                         if (ret) {
 827                                 /*
 828                                  * This only happens when someone fed
 829                                  * us an invalid request.
 830                                  */
 831                                 WARN_ON(1);
 832                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 833                         } else {
 834                                 sdhci_writel(host, host->adma_addr,
 835                                         SDHCI_ADMA_ADDRESS);
 836                         }
 837                 } else {
 838                         int sg_cnt;
 839
 840                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 841                                         data->sg, data->sg_len,
 842                                         (data->flags & MMC_DATA_READ) ?
 843                                                 DMA_FROM_DEVICE :
 844                                                 DMA_TO_DEVICE);
 845                         if (sg_cnt == 0) {
 846                                 /*
 847                                  * This only happens when someone fed
 848                                  * us an invalid request.
 849                                  */
 850                                 WARN_ON(1);
 851                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 852                         } else {
 853                                 WARN_ON(sg_cnt != 1);
 854                                 sdhci_writel(host, sg_dma_address(data->sg),
 855                                         SDHCI_DMA_ADDRESS);
 856                         }
 857                 }
 858         }
 859
 860         /*
 861          * Always adjust the DMA selection as some controllers
 862          * (e.g. JMicron) can't do PIO properly when the selection
 863          * is ADMA.
 864          */
 865         if (host->version >= SDHCI_SPEC_200) {
 866                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 867                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 868                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 869                         (host->flags & SDHCI_USE_ADMA))
 870                         ctrl |= SDHCI_CTRL_ADMA32;
 871                 else
 872                         ctrl |= SDHCI_CTRL_SDMA;
 873                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 874         }
 875
 876         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 877                 int flags;
 878
 879                 flags = SG_MITER_ATOMIC;
 880                 if (host->data->flags & MMC_DATA_READ)
 881                         flags |= SG_MITER_TO_SG;
 882                 else
 883                         flags |= SG_MITER_FROM_SG;
 884                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 885                 host->blocks = data->blocks;
 886         }
 887
 888         sdhci_set_transfer_irqs(host);
 889
 890         /* Set the DMA boundary value and block size */
 891         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 892                 data->blksz), SDHCI_BLOCK_SIZE);
 893         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 894 }
 895
 896 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 897         struct mmc_command *cmd)
 898 {
 899         u16 mode;
 900         struct mmc_data *data = cmd->data;
 901
 902         if (data == NULL)
 903                 return;
 904
 905         WARN_ON(!host->data);
 906
 907         mode = SDHCI_TRNS_BLK_CNT_EN;
 908         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 909                 mode |= SDHCI_TRNS_MULTI;
 910                 /*
 911                  * If we are sending CMD23, CMD12 never gets sent
 912                  * on successful completion (so no Auto-CMD12).
 913                  */
 914                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 915                         mode |= SDHCI_TRNS_AUTO_CMD12;
 916                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 917                         mode |= SDHCI_TRNS_AUTO_CMD23;
 918                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 919                 }
 920         }
 921
 922         if (data->flags & MMC_DATA_READ)
 923                 mode |= SDHCI_TRNS_READ;
 924         if (host->flags & SDHCI_REQ_USE_DMA)
 925                 mode |= SDHCI_TRNS_DMA;
 926
 927         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 928 }
 929
 930 static void sdhci_finish_data(struct sdhci_host *host)
 931 {
 932         struct mmc_data *data;
 933
 934         BUG_ON(!host->data);
 935
 936         data = host->data;
 937         host->data = NULL;
 938
 939         if (host->flags & SDHCI_REQ_USE_DMA) {
 940                 if (host->flags & SDHCI_USE_ADMA)
 941                         sdhci_adma_table_post(host, data);
 942                 else {
 943                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 944                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 945                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 946                 }
 947         }
 948
 949         /*
 950          * The specification states that the block count register must
 951          * be updated, but it does not specify at what point in the
 952          * data flow. That makes the register entirely useless to read
 953          * back so we have to assume that nothing made it to the card
 954          * in the event of an error.
 955          */
 956         if (data->error)
 957                 data->bytes_xfered = 0;
 958         else
 959                 data->bytes_xfered = data->blksz * data->blocks;
 960
 961         /*
 962          * Need to send CMD12 if -
 963          * a) open-ended multiblock transfer (no CMD23)
 964          * b) error in multiblock transfer
 965          */
 966         if (data->stop &&
 967             (data->error ||
 968              !host->mrq->sbc)) {
 969
 970                 /*
 971                  * The controller needs a reset of internal state machines
 972                  * upon error conditions.
 973                  */
 974                 if (data->error) {
 975                         sdhci_reset(host, SDHCI_RESET_CMD);
 976                         sdhci_reset(host, SDHCI_RESET_DATA);
 977                 }
 978
 979                 sdhci_send_command(host, data->stop);
 980         } else
 981                 tasklet_schedule(&host->finish_tasklet);
 982 }
 983
 984 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 985 {
 986         int flags;
 987         u32 mask;
 988         unsigned long timeout;
 989
 990         WARN_ON(host->cmd);
 991
 992         /* Wait max 10 ms */
 993         timeout = 10;
 994
 995         mask = SDHCI_CMD_INHIBIT;
 996         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 997                 mask |= SDHCI_DATA_INHIBIT;
 998
 999         /* We shouldn't wait for data inihibit for stop commands, even
1000            though they might use busy signaling */
1001         if (host->mrq->data && (cmd == host->mrq->data->stop))
1002                 mask &= ~SDHCI_DATA_INHIBIT;
1003
1004         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1005                 if (timeout == 0) {
1006                         pr_err("%s: Controller never released "
1007                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1008                         sdhci_dumpregs(host);
1009                         cmd->error = -EIO;
1010                         tasklet_schedule(&host->finish_tasklet);
1011                         return;
1012                 }
1013                 timeout--;
1014                 mdelay(1);
1015         }
1016
1017         mod_timer(&host->timer, jiffies + 10 * HZ);
1018
1019         host->cmd = cmd;
1020
1021         sdhci_prepare_data(host, cmd);
1022
1023         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1024
1025         sdhci_set_transfer_mode(host, cmd);
1026
1027         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1028                 pr_err("%s: Unsupported response type!\n",
1029                         mmc_hostname(host->mmc));
1030                 cmd->error = -EINVAL;
1031                 tasklet_schedule(&host->finish_tasklet);
1032                 return;
1033         }
1034
1035         if (!(cmd->flags & MMC_RSP_PRESENT))
1036                 flags = SDHCI_CMD_RESP_NONE;
1037         else if (cmd->flags & MMC_RSP_136)
1038                 flags = SDHCI_CMD_RESP_LONG;
1039         else if (cmd->flags & MMC_RSP_BUSY)
1040                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1041         else
1042                 flags = SDHCI_CMD_RESP_SHORT;
1043
1044         if (cmd->flags & MMC_RSP_CRC)
1045                 flags |= SDHCI_CMD_CRC;
1046         if (cmd->flags & MMC_RSP_OPCODE)
1047                 flags |= SDHCI_CMD_INDEX;
1048
1049         /* CMD19 is special in that the Data Present Select should be set */
1050         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1052                 flags |= SDHCI_CMD_DATA;
1053
1054         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1055 }
1056
1057 static void sdhci_finish_command(struct sdhci_host *host)
1058 {
1059         int i;
1060
1061         BUG_ON(host->cmd == NULL);
1062
1063         if (host->cmd->flags & MMC_RSP_PRESENT) {
1064                 if (host->cmd->flags & MMC_RSP_136) {
1065                         /* CRC is stripped so we need to do some shifting. */
1066                         for (i = 0;i < 4;i++) {
1067                                 host->cmd->resp[i] = sdhci_readl(host,
1068                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1069                                 if (i != 3)
1070                                         host->cmd->resp[i] |=
1071                                                 sdhci_readb(host,
1072                                                 SDHCI_RESPONSE + (3-i)*4-1);
1073                         }
1074                 } else {
1075                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1076                 }
1077         }
1078
1079         host->cmd->error = 0;
1080
1081         /* Finished CMD23, now send actual command. */
1082         if (host->cmd == host->mrq->sbc) {
1083                 host->cmd = NULL;
1084                 sdhci_send_command(host, host->mrq->cmd);
1085         } else {
1086
1087                 /* Processed actual command. */
1088                 if (host->data && host->data_early)
1089                         sdhci_finish_data(host);
1090
1091                 if (!host->cmd->data)
1092                         tasklet_schedule(&host->finish_tasklet);
1093
1094                 host->cmd = NULL;
1095         }
1096 }
1097
1098 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1099 {
1100         u16 ctrl, preset = 0;
1101
1102         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1103
1104         switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1105         case SDHCI_CTRL_UHS_SDR12:
1106                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1107                 break;
1108         case SDHCI_CTRL_UHS_SDR25:
1109                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1110                 break;
1111         case SDHCI_CTRL_UHS_SDR50:
1112                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1113                 break;
1114         case SDHCI_CTRL_UHS_SDR104:
1115                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1116                 break;
1117         case SDHCI_CTRL_UHS_DDR50:
1118                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1119                 break;
1120         default:
1121                 pr_warn("%s: Invalid UHS-I mode selected\n",
1122                         mmc_hostname(host->mmc));
1123                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1124                 break;
1125         }
1126         return preset;
1127 }
1128
1129 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1130 {
1131         int div = 0; /* Initialized for compiler warning */
1132         int real_div = div, clk_mul = 1;
1133         u16 clk = 0;
1134         unsigned long timeout;
1135
1136         if (clock && clock == host->clock)
1137                 return;
1138
1139         host->mmc->actual_clock = 0;
1140
1141         if (host->ops->set_clock) {
1142                 host->ops->set_clock(host, clock);
1143                 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1144                         return;
1145         }
1146
1147         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1148
1149         if (clock == 0)
1150                 goto out;
1151
1152         if (host->version >= SDHCI_SPEC_300) {
1153                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1154                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1155                         u16 pre_val;
1156
1157                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1158                         pre_val = sdhci_get_preset_value(host);
1159                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1160                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1161                         if (host->clk_mul &&
1162                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1163                                 clk = SDHCI_PROG_CLOCK_MODE;
1164                                 real_div = div + 1;
1165                                 clk_mul = host->clk_mul;
1166                         } else {
1167                                 real_div = max_t(int, 1, div << 1);
1168                         }
1169                         goto clock_set;
1170                 }
1171
1172                 /*
1173                  * Check if the Host Controller supports Programmable Clock
1174                  * Mode.
1175                  */
1176                 if (host->clk_mul) {
1177                         for (div = 1; div <= 1024; div++) {
1178                                 if ((host->max_clk * host->clk_mul / div)
1179                                         <= clock)
1180                                         break;
1181                         }
1182                         /*
1183                          * Set Programmable Clock Mode in the Clock
1184                          * Control register.
1185                          */
1186                         clk = SDHCI_PROG_CLOCK_MODE;
1187                         real_div = div;
1188                         clk_mul = host->clk_mul;
1189                         div--;
1190                 } else {
1191                         /* Version 3.00 divisors must be a multiple of 2. */
1192                         if (host->max_clk <= clock)
1193                                 div = 1;
1194                         else {
1195                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196                                      div += 2) {
1197                                         if ((host->max_clk / div) <= clock)
1198                                                 break;
1199                                 }
1200                         }
1201                         real_div = div;
1202                         div >>= 1;
1203                 }
1204         } else {
1205                 /* Version 2.00 divisors must be a power of 2. */
1206                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1207                         if ((host->max_clk / div) <= clock)
1208                                 break;
1209                 }
1210                 real_div = div;
1211                 div >>= 1;
1212         }
1213
1214 clock_set:
1215         if (real_div)
1216                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1217
1218         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1219         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1220                 << SDHCI_DIVIDER_HI_SHIFT;
1221         clk |= SDHCI_CLOCK_INT_EN;
1222         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1223
1224         /* Wait max 20 ms */
1225         timeout = 20;
1226         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1227                 & SDHCI_CLOCK_INT_STABLE)) {
1228                 if (timeout == 0) {
1229                         pr_err("%s: Internal clock never "
1230                                 "stabilised.\n", mmc_hostname(host->mmc));
1231                         sdhci_dumpregs(host);
1232                         return;
1233                 }
1234                 timeout--;
1235                 mdelay(1);
1236         }
1237
1238         clk |= SDHCI_CLOCK_CARD_EN;
1239         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1240
1241 out:
1242         host->clock = clock;
1243 }
1244
1245 static inline void sdhci_update_clock(struct sdhci_host *host)
1246 {
1247         unsigned int clock;
1248
1249         clock = host->clock;
1250         host->clock = 0;
1251         sdhci_set_clock(host, clock);
1252 }
1253
1254 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1255 {
1256         u8 pwr = 0;
1257
1258         if (power != (unsigned short)-1) {
1259                 switch (1 << power) {
1260                 case MMC_VDD_165_195:
1261                         pwr = SDHCI_POWER_180;
1262                         break;
1263                 case MMC_VDD_29_30:
1264                 case MMC_VDD_30_31:
1265                         pwr = SDHCI_POWER_300;
1266                         break;
1267                 case MMC_VDD_32_33:
1268                 case MMC_VDD_33_34:
1269                         pwr = SDHCI_POWER_330;
1270                         break;
1271                 default:
1272                         BUG();
1273                 }
1274         }
1275
1276         if (host->pwr == pwr)
1277                 return -1;
1278
1279         host->pwr = pwr;
1280
1281         if (pwr == 0) {
1282                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1283                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1284                         sdhci_runtime_pm_bus_off(host);
1285                 return 0;
1286         }
1287
1288         /*
1289          * Spec says that we should clear the power reg before setting
1290          * a new value. Some controllers don't seem to like this though.
1291          */
1292         if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1293                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1294
1295         /*
1296          * At least the Marvell CaFe chip gets confused if we set the voltage
1297          * and set turn on power at the same time, so set the voltage first.
1298          */
1299         if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1300                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1301
1302         pwr |= SDHCI_POWER_ON;
1303
1304         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1305
1306         if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1307                 sdhci_runtime_pm_bus_on(host);
1308
1309         /*
1310          * Some controllers need an extra 10ms delay of 10ms before they
1311          * can apply clock after applying power
1312          */
1313         if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1314                 mdelay(10);
1315
1316         return power;
1317 }
1318
1319 /*****************************************************************************\
1320  *                                                                           *
1321  * MMC callbacks                                                             *
1322  *                                                                           *
1323 \*****************************************************************************/
1324
1325 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1326 {
1327         struct sdhci_host *host;
1328         int present;
1329         unsigned long flags;
1330         u32 tuning_opcode;
1331
1332         host = mmc_priv(mmc);
1333
1334         sdhci_runtime_pm_get(host);
1335
1336         spin_lock_irqsave(&host->lock, flags);
1337
1338         WARN_ON(host->mrq != NULL);
1339
1340 #ifndef SDHCI_USE_LEDS_CLASS
1341         sdhci_activate_led(host);
1342 #endif
1343
1344         /*
1345          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1346          * requests if Auto-CMD12 is enabled.
1347          */
1348         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1349                 if (mrq->stop) {
1350                         mrq->data->stop = NULL;
1351                         mrq->stop = NULL;
1352                 }
1353         }
1354
1355         host->mrq = mrq;
1356
1357         /*
1358          * Firstly check card presence from cd-gpio.  The return could
1359          * be one of the following possibilities:
1360          *     negative: cd-gpio is not available
1361          *     zero: cd-gpio is used, and card is removed
1362          *     one: cd-gpio is used, and card is present
1363          */
1364         present = mmc_gpio_get_cd(host->mmc);
1365         if (present < 0) {
1366                 /* If polling, assume that the card is always present. */
1367                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1368                         present = 1;
1369                 else
1370                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1371                                         SDHCI_CARD_PRESENT;
1372         }
1373
1374         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1375                 host->mrq->cmd->error = -ENOMEDIUM;
1376                 tasklet_schedule(&host->finish_tasklet);
1377         } else {
1378                 u32 present_state;
1379
1380                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1381                 /*
1382                  * Check if the re-tuning timer has already expired and there
1383                  * is no on-going data transfer. If so, we need to execute
1384                  * tuning procedure before sending command.
1385                  */
1386                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1387                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1388                         if (mmc->card) {
1389                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1390                                 tuning_opcode =
1391                                         mmc->card->type == MMC_TYPE_MMC ?
1392                                         MMC_SEND_TUNING_BLOCK_HS200 :
1393                                         MMC_SEND_TUNING_BLOCK;
1394                                 spin_unlock_irqrestore(&host->lock, flags);
1395                                 sdhci_execute_tuning(mmc, tuning_opcode);
1396                                 spin_lock_irqsave(&host->lock, flags);
1397
1398                                 /* Restore original mmc_request structure */
1399                                 host->mrq = mrq;
1400                         }
1401                 }
1402
1403                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1404                         sdhci_send_command(host, mrq->sbc);
1405                 else
1406                         sdhci_send_command(host, mrq->cmd);
1407         }
1408
1409         mmiowb();
1410         spin_unlock_irqrestore(&host->lock, flags);
1411 }
1412
1413 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1414 {
1415         unsigned long flags;
1416         int vdd_bit = -1;
1417         u8 ctrl;
1418
1419         spin_lock_irqsave(&host->lock, flags);
1420
1421         if (host->flags & SDHCI_DEVICE_DEAD) {
1422                 spin_unlock_irqrestore(&host->lock, flags);
1423                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1424                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1425                 return;
1426         }
1427
1428         /*
1429          * Reset the chip on each power off.
1430          * Should clear out any weird states.
1431          */
1432         if (ios->power_mode == MMC_POWER_OFF) {
1433                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1434                 sdhci_reinit(host);
1435         }
1436
1437         if (host->version >= SDHCI_SPEC_300 &&
1438                 (ios->power_mode == MMC_POWER_UP))
1439                 sdhci_enable_preset_value(host, false);
1440
1441         sdhci_set_clock(host, ios->clock);
1442
1443         if (ios->power_mode == MMC_POWER_OFF)
1444                 vdd_bit = sdhci_set_power(host, -1);
1445         else
1446                 vdd_bit = sdhci_set_power(host, ios->vdd);
1447
1448         if (host->vmmc && vdd_bit != -1) {
1449                 spin_unlock_irqrestore(&host->lock, flags);
1450                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1451                 spin_lock_irqsave(&host->lock, flags);
1452         }
1453
1454         if (host->ops->platform_send_init_74_clocks)
1455                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1456
1457         /*
1458          * If your platform has 8-bit width support but is not a v3 controller,
1459          * or if it requires special setup code, you should implement that in
1460          * platform_bus_width().
1461          */
1462         if (host->ops->platform_bus_width) {
1463                 host->ops->platform_bus_width(host, ios->bus_width);
1464         } else {
1465                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1466                 if (ios->bus_width == MMC_BUS_WIDTH_8) {
1467                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1468                         if (host->version >= SDHCI_SPEC_300)
1469                                 ctrl |= SDHCI_CTRL_8BITBUS;
1470                 } else {
1471                         if (host->version >= SDHCI_SPEC_300)
1472                                 ctrl &= ~SDHCI_CTRL_8BITBUS;
1473                         if (ios->bus_width == MMC_BUS_WIDTH_4)
1474                                 ctrl |= SDHCI_CTRL_4BITBUS;
1475                         else
1476                                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1477                 }
1478                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1479         }
1480
1481         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1482
1483         if ((ios->timing == MMC_TIMING_SD_HS ||
1484              ios->timing == MMC_TIMING_MMC_HS)
1485             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1486                 ctrl |= SDHCI_CTRL_HISPD;
1487         else
1488                 ctrl &= ~SDHCI_CTRL_HISPD;
1489
1490         if (host->version >= SDHCI_SPEC_300) {
1491                 u16 clk, ctrl_2;
1492
1493                 /* In case of UHS-I modes, set High Speed Enable */
1494                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1495                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1496                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1497                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1498                     (ios->timing == MMC_TIMING_UHS_SDR25))
1499                         ctrl |= SDHCI_CTRL_HISPD;
1500
1501                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1502                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1503                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1504                         /*
1505                          * We only need to set Driver Strength if the
1506                          * preset value enable is not set.
1507                          */
1508                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1509                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1510                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1511                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1512                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1513
1514                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1515                 } else {
1516                         /*
1517                          * According to SDHC Spec v3.00, if the Preset Value
1518                          * Enable in the Host Control 2 register is set, we
1519                          * need to reset SD Clock Enable before changing High
1520                          * Speed Enable to avoid generating clock gliches.
1521                          */
1522
1523                         /* Reset SD Clock Enable */
1524                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1525                         clk &= ~SDHCI_CLOCK_CARD_EN;
1526                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1527
1528                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1529
1530                         /* Re-enable SD Clock */
1531                         sdhci_update_clock(host);
1532                 }
1533
1534
1535                 /* Reset SD Clock Enable */
1536                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1537                 clk &= ~SDHCI_CLOCK_CARD_EN;
1538                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1539
1540                 if (host->ops->set_uhs_signaling)
1541                         host->ops->set_uhs_signaling(host, ios->timing);
1542                 else {
1543                         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1544                         /* Select Bus Speed Mode for host */
1545                         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1546                         if (ios->timing == MMC_TIMING_MMC_HS200)
1547                                 ctrl_2 |= SDHCI_CTRL_HS_SDR200;
1548                         else if (ios->timing == MMC_TIMING_UHS_SDR12)
1549                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1550                         else if (ios->timing == MMC_TIMING_UHS_SDR25)
1551                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1552                         else if (ios->timing == MMC_TIMING_UHS_SDR50)
1553                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1554                         else if (ios->timing == MMC_TIMING_UHS_SDR104)
1555                                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1556                         else if (ios->timing == MMC_TIMING_UHS_DDR50)
1557                                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1558                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1559                 }
1560
1561                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1562                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1563                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1564                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1565                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1566                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1567                         u16 preset;
1568
1569                         sdhci_enable_preset_value(host, true);
1570                         preset = sdhci_get_preset_value(host);
1571                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1572                                 >> SDHCI_PRESET_DRV_SHIFT;
1573                 }
1574
1575                 /* Re-enable SD Clock */
1576                 sdhci_update_clock(host);
1577         } else
1578                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1579
1580         /*
1581          * Some (ENE) controllers go apeshit on some ios operation,
1582          * signalling timeout and CRC errors even on CMD0. Resetting
1583          * it on each ios seems to solve the problem.
1584          */
1585         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1586                 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1587
1588         mmiowb();
1589         spin_unlock_irqrestore(&host->lock, flags);
1590 }
1591
1592 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1593 {
1594         struct sdhci_host *host = mmc_priv(mmc);
1595
1596         sdhci_runtime_pm_get(host);
1597         sdhci_do_set_ios(host, ios);
1598         sdhci_runtime_pm_put(host);
1599 }
1600
1601 static int sdhci_do_get_cd(struct sdhci_host *host)
1602 {
1603         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1604
1605         if (host->flags & SDHCI_DEVICE_DEAD)
1606                 return 0;
1607
1608         /* If polling/nonremovable, assume that the card is always present. */
1609         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1610             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1611                 return 1;
1612
1613         /* Try slot gpio detect */
1614         if (!IS_ERR_VALUE(gpio_cd))
1615                 return !!gpio_cd;
1616
1617         /* Host native card detect */
1618         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1619 }
1620
1621 static int sdhci_get_cd(struct mmc_host *mmc)
1622 {
1623         struct sdhci_host *host = mmc_priv(mmc);
1624         int ret;
1625
1626         sdhci_runtime_pm_get(host);
1627         ret = sdhci_do_get_cd(host);
1628         sdhci_runtime_pm_put(host);
1629         return ret;
1630 }
1631
1632 static int sdhci_check_ro(struct sdhci_host *host)
1633 {
1634         unsigned long flags;
1635         int is_readonly;
1636
1637         spin_lock_irqsave(&host->lock, flags);
1638
1639         if (host->flags & SDHCI_DEVICE_DEAD)
1640                 is_readonly = 0;
1641         else if (host->ops->get_ro)
1642                 is_readonly = host->ops->get_ro(host);
1643         else
1644                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1645                                 & SDHCI_WRITE_PROTECT);
1646
1647         spin_unlock_irqrestore(&host->lock, flags);
1648
1649         /* This quirk needs to be replaced by a callback-function later */
1650         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1651                 !is_readonly : is_readonly;
1652 }
1653
1654 #define SAMPLE_COUNT    5
1655
1656 static int sdhci_do_get_ro(struct sdhci_host *host)
1657 {
1658         int i, ro_count;
1659
1660         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1661                 return sdhci_check_ro(host);
1662
1663         ro_count = 0;
1664         for (i = 0; i < SAMPLE_COUNT; i++) {
1665                 if (sdhci_check_ro(host)) {
1666                         if (++ro_count > SAMPLE_COUNT / 2)
1667                                 return 1;
1668                 }
1669                 msleep(30);
1670         }
1671         return 0;
1672 }
1673
1674 static void sdhci_hw_reset(struct mmc_host *mmc)
1675 {
1676         struct sdhci_host *host = mmc_priv(mmc);
1677
1678         if (host->ops && host->ops->hw_reset)
1679                 host->ops->hw_reset(host);
1680 }
1681
1682 static int sdhci_get_ro(struct mmc_host *mmc)
1683 {
1684         struct sdhci_host *host = mmc_priv(mmc);
1685         int ret;
1686
1687         sdhci_runtime_pm_get(host);
1688         ret = sdhci_do_get_ro(host);
1689         sdhci_runtime_pm_put(host);
1690         return ret;
1691 }
1692
1693 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1694 {
1695         if (host->flags & SDHCI_DEVICE_DEAD)
1696                 goto out;
1697
1698         if (enable)
1699                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1700         else
1701                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1702
1703         /* SDIO IRQ will be enabled as appropriate in runtime resume */
1704         if (host->runtime_suspended)
1705                 goto out;
1706
1707         if (enable)
1708                 sdhci_unmask_irqs(host, SDHCI_INT_CARD_INT);
1709         else
1710                 sdhci_mask_irqs(host, SDHCI_INT_CARD_INT);
1711 out:
1712         mmiowb();
1713 }
1714
1715 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1716 {
1717         struct sdhci_host *host = mmc_priv(mmc);
1718         unsigned long flags;
1719
1720         spin_lock_irqsave(&host->lock, flags);
1721         sdhci_enable_sdio_irq_nolock(host, enable);
1722         spin_unlock_irqrestore(&host->lock, flags);
1723 }
1724
1725 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1726                                                 struct mmc_ios *ios)
1727 {
1728         u16 ctrl;
1729         int ret;
1730
1731         /*
1732          * Signal Voltage Switching is only applicable for Host Controllers
1733          * v3.00 and above.
1734          */
1735         if (host->version < SDHCI_SPEC_300)
1736                 return 0;
1737
1738         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1739
1740         switch (ios->signal_voltage) {
1741         case MMC_SIGNAL_VOLTAGE_330:
1742                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1743                 ctrl &= ~SDHCI_CTRL_VDD_180;
1744                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1745
1746                 if (host->vqmmc) {
1747                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1748                         if (ret) {
1749                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1750                                                 " failed\n", mmc_hostname(host->mmc));
1751                                 return -EIO;
1752                         }
1753                 }
1754                 /* Wait for 5ms */
1755                 usleep_range(5000, 5500);
1756
1757                 /* 3.3V regulator output should be stable within 5 ms */
1758                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1759                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1760                         return 0;
1761
1762                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1763                                 mmc_hostname(host->mmc));
1764
1765                 return -EAGAIN;
1766         case MMC_SIGNAL_VOLTAGE_180:
1767                 if (host->vqmmc) {
1768                         ret = regulator_set_voltage(host->vqmmc,
1769                                         1700000, 1950000);
1770                         if (ret) {
1771                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1772                                                 " failed\n", mmc_hostname(host->mmc));
1773                                 return -EIO;
1774                         }
1775                 }
1776
1777                 /*
1778                  * Enable 1.8V Signal Enable in the Host Control2
1779                  * register
1780                  */
1781                 ctrl |= SDHCI_CTRL_VDD_180;
1782                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1783
1784                 /* Wait for 5ms */
1785                 usleep_range(5000, 5500);
1786
1787                 /* 1.8V regulator output should be stable within 5 ms */
1788                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1789                 if (ctrl & SDHCI_CTRL_VDD_180)
1790                         return 0;
1791
1792                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1793                                 mmc_hostname(host->mmc));
1794
1795                 return -EAGAIN;
1796         case MMC_SIGNAL_VOLTAGE_120:
1797                 if (host->vqmmc) {
1798                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1799                         if (ret) {
1800                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1801                                                 " failed\n", mmc_hostname(host->mmc));
1802                                 return -EIO;
1803                         }
1804                 }
1805                 return 0;
1806         default:
1807                 /* No signal voltage switch required */
1808                 return 0;
1809         }
1810 }
1811
1812 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1813         struct mmc_ios *ios)
1814 {
1815         struct sdhci_host *host = mmc_priv(mmc);
1816         int err;
1817
1818         if (host->version < SDHCI_SPEC_300)
1819                 return 0;
1820         sdhci_runtime_pm_get(host);
1821         err = sdhci_do_start_signal_voltage_switch(host, ios);
1822         sdhci_runtime_pm_put(host);
1823         return err;
1824 }
1825
1826 static int sdhci_card_busy(struct mmc_host *mmc)
1827 {
1828         struct sdhci_host *host = mmc_priv(mmc);
1829         u32 present_state;
1830
1831         sdhci_runtime_pm_get(host);
1832         /* Check whether DAT[3:0] is 0000 */
1833         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1834         sdhci_runtime_pm_put(host);
1835
1836         return !(present_state & SDHCI_DATA_LVL_MASK);
1837 }
1838
1839 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1840 {
1841         struct sdhci_host *host;
1842         u16 ctrl;
1843         u32 ier;
1844         int tuning_loop_counter = MAX_TUNING_LOOP;
1845         unsigned long timeout;
1846         int err = 0;
1847         bool requires_tuning_nonuhs = false;
1848
1849         host = mmc_priv(mmc);
1850
1851         sdhci_runtime_pm_get(host);
1852         disable_irq(host->irq);
1853         spin_lock(&host->lock);
1854
1855         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1856
1857         /*
1858          * The Host Controller needs tuning only in case of SDR104 mode
1859          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1860          * Capabilities register.
1861          * If the Host Controller supports the HS200 mode then the
1862          * tuning function has to be executed.
1863          */
1864         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1865             (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1866              host->flags & SDHCI_SDR104_NEEDS_TUNING))
1867                 requires_tuning_nonuhs = true;
1868
1869         if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1870             requires_tuning_nonuhs)
1871                 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1872         else {
1873                 spin_unlock(&host->lock);
1874                 enable_irq(host->irq);
1875                 sdhci_runtime_pm_put(host);
1876                 return 0;
1877         }
1878
1879         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1880
1881         /*
1882          * As per the Host Controller spec v3.00, tuning command
1883          * generates Buffer Read Ready interrupt, so enable that.
1884          *
1885          * Note: The spec clearly says that when tuning sequence
1886          * is being performed, the controller does not generate
1887          * interrupts other than Buffer Read Ready interrupt. But
1888          * to make sure we don't hit a controller bug, we _only_
1889          * enable Buffer Read Ready interrupt here.
1890          */
1891         ier = sdhci_readl(host, SDHCI_INT_ENABLE);
1892         sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
1893
1894         /*
1895          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1896          * of loops reaches 40 times or a timeout of 150ms occurs.
1897          */
1898         timeout = 150;
1899         do {
1900                 struct mmc_command cmd = {0};
1901                 struct mmc_request mrq = {NULL};
1902
1903                 if (!tuning_loop_counter && !timeout)
1904                         break;
1905
1906                 cmd.opcode = opcode;
1907                 cmd.arg = 0;
1908                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1909                 cmd.retries = 0;
1910                 cmd.data = NULL;
1911                 cmd.error = 0;
1912
1913                 mrq.cmd = &cmd;
1914                 host->mrq = &mrq;
1915
1916                 /*
1917                  * In response to CMD19, the card sends 64 bytes of tuning
1918                  * block to the Host Controller. So we set the block size
1919                  * to 64 here.
1920                  */
1921                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1922                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1923                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1924                                              SDHCI_BLOCK_SIZE);
1925                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1926                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1927                                              SDHCI_BLOCK_SIZE);
1928                 } else {
1929                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1930                                      SDHCI_BLOCK_SIZE);
1931                 }
1932
1933                 /*
1934                  * The tuning block is sent by the card to the host controller.
1935                  * So we set the TRNS_READ bit in the Transfer Mode register.
1936                  * This also takes care of setting DMA Enable and Multi Block
1937                  * Select in the same register to 0.
1938                  */
1939                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1940
1941                 sdhci_send_command(host, &cmd);
1942
1943                 host->cmd = NULL;
1944                 host->mrq = NULL;
1945
1946                 spin_unlock(&host->lock);
1947                 enable_irq(host->irq);
1948
1949                 /* Wait for Buffer Read Ready interrupt */
1950                 wait_event_interruptible_timeout(host->buf_ready_int,
1951                                         (host->tuning_done == 1),
1952                                         msecs_to_jiffies(50));
1953                 disable_irq(host->irq);
1954                 spin_lock(&host->lock);
1955
1956                 if (!host->tuning_done) {
1957                         pr_info(DRIVER_NAME ": Timeout waiting for "
1958                                 "Buffer Read Ready interrupt during tuning "
1959                                 "procedure, falling back to fixed sampling "
1960                                 "clock\n");
1961                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1962                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1963                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1964                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1965
1966                         err = -EIO;
1967                         goto out;
1968                 }
1969
1970                 host->tuning_done = 0;
1971
1972                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1973                 tuning_loop_counter--;
1974                 timeout--;
1975                 mdelay(1);
1976         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1977
1978         /*
1979          * The Host Driver has exhausted the maximum number of loops allowed,
1980          * so use fixed sampling frequency.
1981          */
1982         if (!tuning_loop_counter || !timeout) {
1983                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1984                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1985         } else {
1986                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1987                         pr_info(DRIVER_NAME ": Tuning procedure"
1988                                 " failed, falling back to fixed sampling"
1989                                 " clock\n");
1990                         err = -EIO;
1991                 }
1992         }
1993
1994 out:
1995         /*
1996          * If this is the very first time we are here, we start the retuning
1997          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1998          * flag won't be set, we check this condition before actually starting
1999          * the timer.
2000          */
2001         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2002             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2003                 host->flags |= SDHCI_USING_RETUNING_TIMER;
2004                 mod_timer(&host->tuning_timer, jiffies +
2005                         host->tuning_count * HZ);
2006                 /* Tuning mode 1 limits the maximum data length to 4MB */
2007                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2008         } else {
2009                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2010                 /* Reload the new initial value for timer */
2011                 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
2012                         mod_timer(&host->tuning_timer, jiffies +
2013                                 host->tuning_count * HZ);
2014         }
2015
2016         /*
2017          * In case tuning fails, host controllers which support re-tuning can
2018          * try tuning again at a later time, when the re-tuning timer expires.
2019          * So for these controllers, we return 0. Since there might be other
2020          * controllers who do not have this capability, we return error for
2021          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2022          * a retuning timer to do the retuning for the card.
2023          */
2024         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2025                 err = 0;
2026
2027         sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
2028         spin_unlock(&host->lock);
2029         enable_irq(host->irq);
2030         sdhci_runtime_pm_put(host);
2031
2032         return err;
2033 }
2034
2035
2036 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2037 {
2038         u16 ctrl;
2039
2040         /* Host Controller v3.00 defines preset value registers */
2041         if (host->version < SDHCI_SPEC_300)
2042                 return;
2043
2044         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2045
2046         /*
2047          * We only enable or disable Preset Value if they are not already
2048          * enabled or disabled respectively. Otherwise, we bail out.
2049          */
2050         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2051                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2052                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2053                 host->flags |= SDHCI_PV_ENABLED;
2054         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2055                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2056                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2057                 host->flags &= ~SDHCI_PV_ENABLED;
2058         }
2059 }
2060
2061 static void sdhci_card_event(struct mmc_host *mmc)
2062 {
2063         struct sdhci_host *host = mmc_priv(mmc);
2064         unsigned long flags;
2065
2066         spin_lock_irqsave(&host->lock, flags);
2067
2068         /* Check host->mrq first in case we are runtime suspended */
2069         if (host->mrq && !sdhci_do_get_cd(host)) {
2070                 pr_err("%s: Card removed during transfer!\n",
2071                         mmc_hostname(host->mmc));
2072                 pr_err("%s: Resetting controller.\n",
2073                         mmc_hostname(host->mmc));
2074
2075                 sdhci_reset(host, SDHCI_RESET_CMD);
2076                 sdhci_reset(host, SDHCI_RESET_DATA);
2077
2078                 host->mrq->cmd->error = -ENOMEDIUM;
2079                 tasklet_schedule(&host->finish_tasklet);
2080         }
2081
2082         spin_unlock_irqrestore(&host->lock, flags);
2083 }
2084
2085 static const struct mmc_host_ops sdhci_ops = {
2086         .request        = sdhci_request,
2087         .set_ios        = sdhci_set_ios,
2088         .get_cd         = sdhci_get_cd,
2089         .get_ro         = sdhci_get_ro,
2090         .hw_reset       = sdhci_hw_reset,
2091         .enable_sdio_irq = sdhci_enable_sdio_irq,
2092         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2093         .execute_tuning                 = sdhci_execute_tuning,
2094         .card_event                     = sdhci_card_event,
2095         .card_busy      = sdhci_card_busy,
2096 };
2097
2098 /*****************************************************************************\
2099  *                                                                           *
2100  * Tasklets                                                                  *
2101  *                                                                           *
2102 \*****************************************************************************/
2103
2104 static void sdhci_tasklet_card(unsigned long param)
2105 {
2106         struct sdhci_host *host = (struct sdhci_host*)param;
2107
2108         sdhci_card_event(host->mmc);
2109
2110         mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2111 }
2112
2113 static void sdhci_tasklet_finish(unsigned long param)
2114 {
2115         struct sdhci_host *host;
2116         unsigned long flags;
2117         struct mmc_request *mrq;
2118
2119         host = (struct sdhci_host*)param;
2120
2121         spin_lock_irqsave(&host->lock, flags);
2122
2123         /*
2124          * If this tasklet gets rescheduled while running, it will
2125          * be run again afterwards but without any active request.
2126          */
2127         if (!host->mrq) {
2128                 spin_unlock_irqrestore(&host->lock, flags);
2129                 return;
2130         }
2131
2132         del_timer(&host->timer);
2133
2134         mrq = host->mrq;
2135
2136         /*
2137          * The controller needs a reset of internal state machines
2138          * upon error conditions.
2139          */
2140         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2141             ((mrq->cmd && mrq->cmd->error) ||
2142                  (mrq->data && (mrq->data->error ||
2143                   (mrq->data->stop && mrq->data->stop->error))) ||
2144                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2145
2146                 /* Some controllers need this kick or reset won't work here */
2147                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2148                         /* This is to force an update */
2149                         sdhci_update_clock(host);
2150
2151                 /* Spec says we should do both at the same time, but Ricoh
2152                    controllers do not like that. */
2153                 sdhci_reset(host, SDHCI_RESET_CMD);
2154                 sdhci_reset(host, SDHCI_RESET_DATA);
2155         }
2156
2157         host->mrq = NULL;
2158         host->cmd = NULL;
2159         host->data = NULL;
2160
2161 #ifndef SDHCI_USE_LEDS_CLASS
2162         sdhci_deactivate_led(host);
2163 #endif
2164
2165         mmiowb();
2166         spin_unlock_irqrestore(&host->lock, flags);
2167
2168         mmc_request_done(host->mmc, mrq);
2169         sdhci_runtime_pm_put(host);
2170 }
2171
2172 static void sdhci_timeout_timer(unsigned long data)
2173 {
2174         struct sdhci_host *host;
2175         unsigned long flags;
2176
2177         host = (struct sdhci_host*)data;
2178
2179         spin_lock_irqsave(&host->lock, flags);
2180
2181         if (host->mrq) {
2182                 pr_err("%s: Timeout waiting for hardware "
2183                         "interrupt.\n", mmc_hostname(host->mmc));
2184                 sdhci_dumpregs(host);
2185
2186                 if (host->data) {
2187                         host->data->error = -ETIMEDOUT;
2188                         sdhci_finish_data(host);
2189                 } else {
2190                         if (host->cmd)
2191                                 host->cmd->error = -ETIMEDOUT;
2192                         else
2193                                 host->mrq->cmd->error = -ETIMEDOUT;
2194
2195                         tasklet_schedule(&host->finish_tasklet);
2196                 }
2197         }
2198
2199         mmiowb();
2200         spin_unlock_irqrestore(&host->lock, flags);
2201 }
2202
2203 static void sdhci_tuning_timer(unsigned long data)
2204 {
2205         struct sdhci_host *host;
2206         unsigned long flags;
2207
2208         host = (struct sdhci_host *)data;
2209
2210         spin_lock_irqsave(&host->lock, flags);
2211
2212         host->flags |= SDHCI_NEEDS_RETUNING;
2213
2214         spin_unlock_irqrestore(&host->lock, flags);
2215 }
2216
2217 /*****************************************************************************\
2218  *                                                                           *
2219  * Interrupt handling                                                        *
2220  *                                                                           *
2221 \*****************************************************************************/
2222
2223 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2224 {
2225         BUG_ON(intmask == 0);
2226
2227         if (!host->cmd) {
2228                 pr_err("%s: Got command interrupt 0x%08x even "
2229                         "though no command operation was in progress.\n",
2230                         mmc_hostname(host->mmc), (unsigned)intmask);
2231                 sdhci_dumpregs(host);
2232                 return;
2233         }
2234
2235         if (intmask & SDHCI_INT_TIMEOUT)
2236                 host->cmd->error = -ETIMEDOUT;
2237         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2238                         SDHCI_INT_INDEX))
2239                 host->cmd->error = -EILSEQ;
2240
2241         if (host->cmd->error) {
2242                 tasklet_schedule(&host->finish_tasklet);
2243                 return;
2244         }
2245
2246         /*
2247          * The host can send and interrupt when the busy state has
2248          * ended, allowing us to wait without wasting CPU cycles.
2249          * Unfortunately this is overloaded on the "data complete"
2250          * interrupt, so we need to take some care when handling
2251          * it.
2252          *
2253          * Note: The 1.0 specification is a bit ambiguous about this
2254          *       feature so there might be some problems with older
2255          *       controllers.
2256          */
2257         if (host->cmd->flags & MMC_RSP_BUSY) {
2258                 if (host->cmd->data)
2259                         DBG("Cannot wait for busy signal when also "
2260                                 "doing a data transfer");
2261                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2262                         return;
2263
2264                 /* The controller does not support the end-of-busy IRQ,
2265                  * fall through and take the SDHCI_INT_RESPONSE */
2266         }
2267
2268         if (intmask & SDHCI_INT_RESPONSE)
2269                 sdhci_finish_command(host);
2270 }
2271
2272 #ifdef CONFIG_MMC_DEBUG
2273 static void sdhci_show_adma_error(struct sdhci_host *host)
2274 {
2275         const char *name = mmc_hostname(host->mmc);
2276         u8 *desc = host->adma_desc;
2277         __le32 *dma;
2278         __le16 *len;
2279         u8 attr;
2280
2281         sdhci_dumpregs(host);
2282
2283         while (true) {
2284                 dma = (__le32 *)(desc + 4);
2285                 len = (__le16 *)(desc + 2);
2286                 attr = *desc;
2287
2288                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2289                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2290
2291                 desc += 8;
2292
2293                 if (attr & 2)
2294                         break;
2295         }
2296 }
2297 #else
2298 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2299 #endif
2300
2301 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2302 {
2303         u32 command;
2304         BUG_ON(intmask == 0);
2305
2306         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2307         if (intmask & SDHCI_INT_DATA_AVAIL) {
2308                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2309                 if (command == MMC_SEND_TUNING_BLOCK ||
2310                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2311                         host->tuning_done = 1;
2312                         wake_up(&host->buf_ready_int);
2313                         return;
2314                 }
2315         }
2316
2317         if (!host->data) {
2318                 /*
2319                  * The "data complete" interrupt is also used to
2320                  * indicate that a busy state has ended. See comment
2321                  * above in sdhci_cmd_irq().
2322                  */
2323                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2324                         if (intmask & SDHCI_INT_DATA_END) {
2325                                 sdhci_finish_command(host);
2326                                 return;
2327                         }
2328                 }
2329
2330                 pr_err("%s: Got data interrupt 0x%08x even "
2331                         "though no data operation was in progress.\n",
2332                         mmc_hostname(host->mmc), (unsigned)intmask);
2333                 sdhci_dumpregs(host);
2334
2335                 return;
2336         }
2337
2338         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2339                 host->data->error = -ETIMEDOUT;
2340         else if (intmask & SDHCI_INT_DATA_END_BIT)
2341                 host->data->error = -EILSEQ;
2342         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2343                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2344                         != MMC_BUS_TEST_R)
2345                 host->data->error = -EILSEQ;
2346         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2347                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2348                 sdhci_show_adma_error(host);
2349                 host->data->error = -EIO;
2350                 if (host->ops->adma_workaround)
2351                         host->ops->adma_workaround(host, intmask);
2352         }
2353
2354         if (host->data->error)
2355                 sdhci_finish_data(host);
2356         else {
2357                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2358                         sdhci_transfer_pio(host);
2359
2360                 /*
2361                  * We currently don't do anything fancy with DMA
2362                  * boundaries, but as we can't disable the feature
2363                  * we need to at least restart the transfer.
2364                  *
2365                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2366                  * should return a valid address to continue from, but as
2367                  * some controllers are faulty, don't trust them.
2368                  */
2369                 if (intmask & SDHCI_INT_DMA_END) {
2370                         u32 dmastart, dmanow;
2371                         dmastart = sg_dma_address(host->data->sg);
2372                         dmanow = dmastart + host->data->bytes_xfered;
2373                         /*
2374                          * Force update to the next DMA block boundary.
2375                          */
2376                         dmanow = (dmanow &
2377                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2378                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2379                         host->data->bytes_xfered = dmanow - dmastart;
2380                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2381                                 " next 0x%08x\n",
2382                                 mmc_hostname(host->mmc), dmastart,
2383                                 host->data->bytes_xfered, dmanow);
2384                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2385                 }
2386
2387                 if (intmask & SDHCI_INT_DATA_END) {
2388                         if (host->cmd) {
2389                                 /*
2390                                  * Data managed to finish before the
2391                                  * command completed. Make sure we do
2392                                  * things in the proper order.
2393                                  */
2394                                 host->data_early = 1;
2395                         } else {
2396                                 sdhci_finish_data(host);
2397                         }
2398                 }
2399         }
2400 }
2401
2402 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2403 {
2404         irqreturn_t result;
2405         struct sdhci_host *host = dev_id;
2406         u32 intmask, unexpected = 0;
2407         int cardint = 0, max_loops = 16;
2408
2409         spin_lock(&host->lock);
2410
2411         if (host->runtime_suspended) {
2412                 spin_unlock(&host->lock);
2413                 pr_warning("%s: got irq while runtime suspended\n",
2414                        mmc_hostname(host->mmc));
2415                 return IRQ_HANDLED;
2416         }
2417
2418         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2419
2420         if (!intmask || intmask == 0xffffffff) {
2421                 result = IRQ_NONE;
2422                 goto out;
2423         }
2424
2425 again:
2426         DBG("*** %s got interrupt: 0x%08x\n",
2427                 mmc_hostname(host->mmc), intmask);
2428
2429         if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2430                 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2431                               SDHCI_CARD_PRESENT;
2432
2433                 /*
2434                  * There is a observation on i.mx esdhc.  INSERT bit will be
2435                  * immediately set again when it gets cleared, if a card is
2436                  * inserted.  We have to mask the irq to prevent interrupt
2437                  * storm which will freeze the system.  And the REMOVE gets
2438                  * the same situation.
2439                  *
2440                  * More testing are needed here to ensure it works for other
2441                  * platforms though.
2442                  */
2443                 sdhci_mask_irqs(host, present ? SDHCI_INT_CARD_INSERT :
2444                                                 SDHCI_INT_CARD_REMOVE);
2445                 sdhci_unmask_irqs(host, present ? SDHCI_INT_CARD_REMOVE :
2446                                                   SDHCI_INT_CARD_INSERT);
2447
2448                 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2449                              SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2450                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
2451                 tasklet_schedule(&host->card_tasklet);
2452         }
2453
2454         if (intmask & SDHCI_INT_CMD_MASK) {
2455                 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
2456                         SDHCI_INT_STATUS);
2457                 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2458         }
2459
2460         if (intmask & SDHCI_INT_DATA_MASK) {
2461                 sdhci_writel(host, intmask & SDHCI_INT_DATA_MASK,
2462                         SDHCI_INT_STATUS);
2463                 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2464         }
2465
2466         intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
2467
2468         intmask &= ~SDHCI_INT_ERROR;
2469
2470         if (intmask & SDHCI_INT_BUS_POWER) {
2471                 pr_err("%s: Card is consuming too much power!\n",
2472                         mmc_hostname(host->mmc));
2473                 sdhci_writel(host, SDHCI_INT_BUS_POWER, SDHCI_INT_STATUS);
2474         }
2475
2476         intmask &= ~SDHCI_INT_BUS_POWER;
2477
2478         if (intmask & SDHCI_INT_CARD_INT)
2479                 cardint = 1;
2480
2481         intmask &= ~SDHCI_INT_CARD_INT;
2482
2483         if (intmask) {
2484                 unexpected |= intmask;
2485                 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2486         }
2487
2488         result = IRQ_HANDLED;
2489
2490         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2491         if (intmask && --max_loops)
2492                 goto again;
2493 out:
2494         spin_unlock(&host->lock);
2495
2496         if (unexpected) {
2497                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2498                            mmc_hostname(host->mmc), unexpected);
2499                 sdhci_dumpregs(host);
2500         }
2501         /*
2502          * We have to delay this as it calls back into the driver.
2503          */
2504         if (cardint)
2505                 mmc_signal_sdio_irq(host->mmc);
2506
2507         return result;
2508 }
2509
2510 /*****************************************************************************\
2511  *                                                                           *
2512  * Suspend/resume                                                            *
2513  *                                                                           *
2514 \*****************************************************************************/
2515
2516 #ifdef CONFIG_PM
2517 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2518 {
2519         u8 val;
2520         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2521                         | SDHCI_WAKE_ON_INT;
2522
2523         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2524         val |= mask ;
2525         /* Avoid fake wake up */
2526         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2527                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2528         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2529 }
2530 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2531
2532 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2533 {
2534         u8 val;
2535         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2536                         | SDHCI_WAKE_ON_INT;
2537
2538         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2539         val &= ~mask;
2540         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2541 }
2542 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2543
2544 int sdhci_suspend_host(struct sdhci_host *host)
2545 {
2546         int ret;
2547
2548         if (host->ops->platform_suspend)
2549                 host->ops->platform_suspend(host);
2550
2551         sdhci_disable_card_detection(host);
2552
2553         /* Disable tuning since we are suspending */
2554         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2555                 del_timer_sync(&host->tuning_timer);
2556                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2557         }
2558
2559         ret = mmc_suspend_host(host->mmc);
2560         if (ret) {
2561                 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2562                         host->flags |= SDHCI_NEEDS_RETUNING;
2563                         mod_timer(&host->tuning_timer, jiffies +
2564                                         host->tuning_count * HZ);
2565                 }
2566
2567                 sdhci_enable_card_detection(host);
2568
2569                 return ret;
2570         }
2571
2572         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2573                 sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2574                 free_irq(host->irq, host);
2575         } else {
2576                 sdhci_enable_irq_wakeups(host);
2577                 enable_irq_wake(host->irq);
2578         }
2579         return ret;
2580 }
2581
2582 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2583
2584 int sdhci_resume_host(struct sdhci_host *host)
2585 {
2586         int ret;
2587
2588         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2589                 if (host->ops->enable_dma)
2590                         host->ops->enable_dma(host);
2591         }
2592
2593         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2594                 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
2595                                   mmc_hostname(host->mmc), host);
2596                 if (ret)
2597                         return ret;
2598         } else {
2599                 sdhci_disable_irq_wakeups(host);
2600                 disable_irq_wake(host->irq);
2601         }
2602
2603         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2604             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2605                 /* Card keeps power but host controller does not */
2606                 sdhci_init(host, 0);
2607                 host->pwr = 0;
2608                 host->clock = 0;
2609                 sdhci_do_set_ios(host, &host->mmc->ios);
2610         } else {
2611                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2612                 mmiowb();
2613         }
2614
2615         ret = mmc_resume_host(host->mmc);
2616         sdhci_enable_card_detection(host);
2617
2618         if (host->ops->platform_resume)
2619                 host->ops->platform_resume(host);
2620
2621         /* Set the re-tuning expiration flag */
2622         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2623                 host->flags |= SDHCI_NEEDS_RETUNING;
2624
2625         return ret;
2626 }
2627
2628 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2629 #endif /* CONFIG_PM */
2630
2631 #ifdef CONFIG_PM_RUNTIME
2632
2633 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2634 {
2635         return pm_runtime_get_sync(host->mmc->parent);
2636 }
2637
2638 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2639 {
2640         pm_runtime_mark_last_busy(host->mmc->parent);
2641         return pm_runtime_put_autosuspend(host->mmc->parent);
2642 }
2643
2644 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2645 {
2646         if (host->runtime_suspended || host->bus_on)
2647                 return;
2648         host->bus_on = true;
2649         pm_runtime_get_noresume(host->mmc->parent);
2650 }
2651
2652 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2653 {
2654         if (host->runtime_suspended || !host->bus_on)
2655                 return;
2656         host->bus_on = false;
2657         pm_runtime_put_noidle(host->mmc->parent);
2658 }
2659
2660 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2661 {
2662         unsigned long flags;
2663         int ret = 0;
2664
2665         /* Disable tuning since we are suspending */
2666         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2667                 del_timer_sync(&host->tuning_timer);
2668                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2669         }
2670
2671         spin_lock_irqsave(&host->lock, flags);
2672         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
2673         spin_unlock_irqrestore(&host->lock, flags);
2674
2675         synchronize_irq(host->irq);
2676
2677         spin_lock_irqsave(&host->lock, flags);
2678         host->runtime_suspended = true;
2679         spin_unlock_irqrestore(&host->lock, flags);
2680
2681         return ret;
2682 }
2683 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2684
2685 int sdhci_runtime_resume_host(struct sdhci_host *host)
2686 {
2687         unsigned long flags;
2688         int ret = 0, host_flags = host->flags;
2689
2690         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2691                 if (host->ops->enable_dma)
2692                         host->ops->enable_dma(host);
2693         }
2694
2695         sdhci_init(host, 0);
2696
2697         /* Force clock and power re-program */
2698         host->pwr = 0;
2699         host->clock = 0;
2700         sdhci_do_set_ios(host, &host->mmc->ios);
2701
2702         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2703         if ((host_flags & SDHCI_PV_ENABLED) &&
2704                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2705                 spin_lock_irqsave(&host->lock, flags);
2706                 sdhci_enable_preset_value(host, true);
2707                 spin_unlock_irqrestore(&host->lock, flags);
2708         }
2709
2710         /* Set the re-tuning expiration flag */
2711         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2712                 host->flags |= SDHCI_NEEDS_RETUNING;
2713
2714         spin_lock_irqsave(&host->lock, flags);
2715
2716         host->runtime_suspended = false;
2717
2718         /* Enable SDIO IRQ */
2719         if ((host->flags & SDHCI_SDIO_IRQ_ENABLED))
2720                 sdhci_enable_sdio_irq_nolock(host, true);
2721
2722         /* Enable Card Detection */
2723         sdhci_enable_card_detection(host);
2724
2725         spin_unlock_irqrestore(&host->lock, flags);
2726
2727         return ret;
2728 }
2729 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2730
2731 #endif
2732
2733 /*****************************************************************************\
2734  *                                                                           *
2735  * Device allocation/registration                                            *
2736  *                                                                           *
2737 \*****************************************************************************/
2738
2739 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2740         size_t priv_size)
2741 {
2742         struct mmc_host *mmc;
2743         struct sdhci_host *host;
2744
2745         WARN_ON(dev == NULL);
2746
2747         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2748         if (!mmc)
2749                 return ERR_PTR(-ENOMEM);
2750
2751         host = mmc_priv(mmc);
2752         host->mmc = mmc;
2753
2754         return host;
2755 }
2756
2757 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2758
2759 int sdhci_add_host(struct sdhci_host *host)
2760 {
2761         struct mmc_host *mmc;
2762         u32 caps[2] = {0, 0};
2763         u32 max_current_caps;
2764         unsigned int ocr_avail;
2765         int ret;
2766
2767         WARN_ON(host == NULL);
2768         if (host == NULL)
2769                 return -EINVAL;
2770
2771         mmc = host->mmc;
2772
2773         if (debug_quirks)
2774                 host->quirks = debug_quirks;
2775         if (debug_quirks2)
2776                 host->quirks2 = debug_quirks2;
2777
2778         sdhci_reset(host, SDHCI_RESET_ALL);
2779
2780         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2781         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2782                                 >> SDHCI_SPEC_VER_SHIFT;
2783         if (host->version > SDHCI_SPEC_300) {
2784                 pr_err("%s: Unknown controller version (%d). "
2785                         "You may experience problems.\n", mmc_hostname(mmc),
2786                         host->version);
2787         }
2788
2789         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2790                 sdhci_readl(host, SDHCI_CAPABILITIES);
2791
2792         if (host->version >= SDHCI_SPEC_300)
2793                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2794                         host->caps1 :
2795                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2796
2797         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2798                 host->flags |= SDHCI_USE_SDMA;
2799         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2800                 DBG("Controller doesn't have SDMA capability\n");
2801         else
2802                 host->flags |= SDHCI_USE_SDMA;
2803
2804         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2805                 (host->flags & SDHCI_USE_SDMA)) {
2806                 DBG("Disabling DMA as it is marked broken\n");
2807                 host->flags &= ~SDHCI_USE_SDMA;
2808         }
2809
2810         if ((host->version >= SDHCI_SPEC_200) &&
2811                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2812                 host->flags |= SDHCI_USE_ADMA;
2813
2814         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2815                 (host->flags & SDHCI_USE_ADMA)) {
2816                 DBG("Disabling ADMA as it is marked broken\n");
2817                 host->flags &= ~SDHCI_USE_ADMA;
2818         }
2819
2820         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2821                 if (host->ops->enable_dma) {
2822                         if (host->ops->enable_dma(host)) {
2823                                 pr_warning("%s: No suitable DMA "
2824                                         "available. Falling back to PIO.\n",
2825                                         mmc_hostname(mmc));
2826                                 host->flags &=
2827                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2828                         }
2829                 }
2830         }
2831
2832         if (host->flags & SDHCI_USE_ADMA) {
2833                 /*
2834                  * We need to allocate descriptors for all sg entries
2835                  * (128) and potentially one alignment transfer for
2836                  * each of those entries.
2837                  */
2838                 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2839                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2840                 if (!host->adma_desc || !host->align_buffer) {
2841                         kfree(host->adma_desc);
2842                         kfree(host->align_buffer);
2843                         pr_warning("%s: Unable to allocate ADMA "
2844                                 "buffers. Falling back to standard DMA.\n",
2845                                 mmc_hostname(mmc));
2846                         host->flags &= ~SDHCI_USE_ADMA;
2847                 }
2848         }
2849
2850         /*
2851          * If we use DMA, then it's up to the caller to set the DMA
2852          * mask, but PIO does not need the hw shim so we set a new
2853          * mask here in that case.
2854          */
2855         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2856                 host->dma_mask = DMA_BIT_MASK(64);
2857                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2858         }
2859
2860         if (host->version >= SDHCI_SPEC_300)
2861                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2862                         >> SDHCI_CLOCK_BASE_SHIFT;
2863         else
2864                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2865                         >> SDHCI_CLOCK_BASE_SHIFT;
2866
2867         host->max_clk *= 1000000;
2868         if (host->max_clk == 0 || host->quirks &
2869                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2870                 if (!host->ops->get_max_clock) {
2871                         pr_err("%s: Hardware doesn't specify base clock "
2872                                "frequency.\n", mmc_hostname(mmc));
2873                         return -ENODEV;
2874                 }
2875                 host->max_clk = host->ops->get_max_clock(host);
2876         }
2877
2878         /*
2879          * In case of Host Controller v3.00, find out whether clock
2880          * multiplier is supported.
2881          */
2882         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2883                         SDHCI_CLOCK_MUL_SHIFT;
2884
2885         /*
2886          * In case the value in Clock Multiplier is 0, then programmable
2887          * clock mode is not supported, otherwise the actual clock
2888          * multiplier is one more than the value of Clock Multiplier
2889          * in the Capabilities Register.
2890          */
2891         if (host->clk_mul)
2892                 host->clk_mul += 1;
2893
2894         /*
2895          * Set host parameters.
2896          */
2897         mmc->ops = &sdhci_ops;
2898         mmc->f_max = host->max_clk;
2899         if (host->ops->get_min_clock)
2900                 mmc->f_min = host->ops->get_min_clock(host);
2901         else if (host->version >= SDHCI_SPEC_300) {
2902                 if (host->clk_mul) {
2903                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2904                         mmc->f_max = host->max_clk * host->clk_mul;
2905                 } else
2906                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2907         } else
2908                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2909
2910         host->timeout_clk =
2911                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2912         if (host->timeout_clk == 0) {
2913                 if (host->ops->get_timeout_clock) {
2914                         host->timeout_clk = host->ops->get_timeout_clock(host);
2915                 } else if (!(host->quirks &
2916                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2917                         pr_err("%s: Hardware doesn't specify timeout clock "
2918                                "frequency.\n", mmc_hostname(mmc));
2919                         return -ENODEV;
2920                 }
2921         }
2922         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2923                 host->timeout_clk *= 1000;
2924
2925         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2926                 host->timeout_clk = mmc->f_max / 1000;
2927
2928         mmc->max_discard_to = (1 << 27) / host->timeout_clk;
2929
2930         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2931
2932         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2933                 host->flags |= SDHCI_AUTO_CMD12;
2934
2935         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2936         if ((host->version >= SDHCI_SPEC_300) &&
2937             ((host->flags & SDHCI_USE_ADMA) ||
2938              !(host->flags & SDHCI_USE_SDMA))) {
2939                 host->flags |= SDHCI_AUTO_CMD23;
2940                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2941         } else {
2942                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2943         }
2944
2945         /*
2946          * A controller may support 8-bit width, but the board itself
2947          * might not have the pins brought out.  Boards that support
2948          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2949          * their platform code before calling sdhci_add_host(), and we
2950          * won't assume 8-bit width for hosts without that CAP.
2951          */
2952         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2953                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2954
2955         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2956                 mmc->caps &= ~MMC_CAP_CMD23;
2957
2958         if (caps[0] & SDHCI_CAN_DO_HISPD)
2959                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2960
2961         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2962             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2963                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2964
2965         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2966         host->vqmmc = regulator_get(mmc_dev(mmc), "vqmmc");
2967         if (IS_ERR_OR_NULL(host->vqmmc)) {
2968                 if (PTR_ERR(host->vqmmc) < 0) {
2969                         pr_info("%s: no vqmmc regulator found\n",
2970                                 mmc_hostname(mmc));
2971                         host->vqmmc = NULL;
2972                 }
2973         } else {
2974                 ret = regulator_enable(host->vqmmc);
2975                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2976                         1950000))
2977                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2978                                         SDHCI_SUPPORT_SDR50 |
2979                                         SDHCI_SUPPORT_DDR50);
2980                 if (ret) {
2981                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2982                                 mmc_hostname(mmc), ret);
2983                         host->vqmmc = NULL;
2984                 }
2985         }
2986
2987         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2988                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2989                        SDHCI_SUPPORT_DDR50);
2990
2991         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2992         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2993                        SDHCI_SUPPORT_DDR50))
2994                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2995
2996         /* SDR104 supports also implies SDR50 support */
2997         if (caps[1] & SDHCI_SUPPORT_SDR104) {
2998                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2999                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3000                  * field can be promoted to support HS200.
3001                  */
3002                 mmc->caps2 |= MMC_CAP2_HS200;
3003         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3004                 mmc->caps |= MMC_CAP_UHS_SDR50;
3005
3006         if (caps[1] & SDHCI_SUPPORT_DDR50)
3007                 mmc->caps |= MMC_CAP_UHS_DDR50;
3008
3009         /* Does the host need tuning for SDR50? */
3010         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3011                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3012
3013         /* Does the host need tuning for SDR104 / HS200? */
3014         if (mmc->caps2 & MMC_CAP2_HS200)
3015                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3016
3017         /* Driver Type(s) (A, C, D) supported by the host */
3018         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3019                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3020         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3021                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3022         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3023                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3024
3025         /* Initial value for re-tuning timer count */
3026         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3027                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3028
3029         /*
3030          * In case Re-tuning Timer is not disabled, the actual value of
3031          * re-tuning timer will be 2 ^ (n - 1).
3032          */
3033         if (host->tuning_count)
3034                 host->tuning_count = 1 << (host->tuning_count - 1);
3035
3036         /* Re-tuning mode supported by the Host Controller */
3037         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3038                              SDHCI_RETUNING_MODE_SHIFT;
3039
3040         ocr_avail = 0;
3041
3042         host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
3043         if (IS_ERR_OR_NULL(host->vmmc)) {
3044                 if (PTR_ERR(host->vmmc) < 0) {
3045                         pr_info("%s: no vmmc regulator found\n",
3046                                 mmc_hostname(mmc));
3047                         host->vmmc = NULL;
3048                 }
3049         }
3050
3051 #ifdef CONFIG_REGULATOR
3052         /*
3053          * Voltage range check makes sense only if regulator reports
3054          * any voltage value.
3055          */
3056         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3057                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3058                         3600000);
3059                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3060                         caps[0] &= ~SDHCI_CAN_VDD_330;
3061                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3062                         caps[0] &= ~SDHCI_CAN_VDD_300;
3063                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3064                         1950000);
3065                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3066                         caps[0] &= ~SDHCI_CAN_VDD_180;
3067         }
3068 #endif /* CONFIG_REGULATOR */
3069
3070         /*
3071          * According to SD Host Controller spec v3.00, if the Host System
3072          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3073          * the value is meaningful only if Voltage Support in the Capabilities
3074          * register is set. The actual current value is 4 times the register
3075          * value.
3076          */
3077         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3078         if (!max_current_caps && host->vmmc) {
3079                 u32 curr = regulator_get_current_limit(host->vmmc);
3080                 if (curr > 0) {
3081
3082                         /* convert to SDHCI_MAX_CURRENT format */
3083                         curr = curr/1000;  /* convert to mA */
3084                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3085
3086                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3087                         max_current_caps =
3088                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3089                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3090                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3091                 }
3092         }
3093
3094         if (caps[0] & SDHCI_CAN_VDD_330) {
3095                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3096
3097                 mmc->max_current_330 = ((max_current_caps &
3098                                    SDHCI_MAX_CURRENT_330_MASK) >>
3099                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3100                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3101         }
3102         if (caps[0] & SDHCI_CAN_VDD_300) {
3103                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3104
3105                 mmc->max_current_300 = ((max_current_caps &
3106                                    SDHCI_MAX_CURRENT_300_MASK) >>
3107                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3108                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3109         }
3110         if (caps[0] & SDHCI_CAN_VDD_180) {
3111                 ocr_avail |= MMC_VDD_165_195;
3112
3113                 mmc->max_current_180 = ((max_current_caps &
3114                                    SDHCI_MAX_CURRENT_180_MASK) >>
3115                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3116                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3117         }
3118
3119         mmc->ocr_avail = ocr_avail;
3120         mmc->ocr_avail_sdio = ocr_avail;
3121         if (host->ocr_avail_sdio)
3122                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3123         mmc->ocr_avail_sd = ocr_avail;
3124         if (host->ocr_avail_sd)
3125                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3126         else /* normal SD controllers don't support 1.8V */
3127                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3128         mmc->ocr_avail_mmc = ocr_avail;
3129         if (host->ocr_avail_mmc)
3130                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3131
3132         if (mmc->ocr_avail == 0) {
3133                 pr_err("%s: Hardware doesn't report any "
3134                         "support voltages.\n", mmc_hostname(mmc));
3135                 return -ENODEV;
3136         }
3137
3138         spin_lock_init(&host->lock);
3139
3140         /*
3141          * Maximum number of segments. Depends on if the hardware
3142          * can do scatter/gather or not.
3143          */
3144         if (host->flags & SDHCI_USE_ADMA)
3145                 mmc->max_segs = 128;
3146         else if (host->flags & SDHCI_USE_SDMA)
3147                 mmc->max_segs = 1;
3148         else /* PIO */
3149                 mmc->max_segs = 128;
3150
3151         /*
3152          * Maximum number of sectors in one transfer. Limited by DMA boundary
3153          * size (512KiB).
3154          */
3155         mmc->max_req_size = 524288;
3156
3157         /*
3158          * Maximum segment size. Could be one segment with the maximum number
3159          * of bytes. When doing hardware scatter/gather, each entry cannot
3160          * be larger than 64 KiB though.
3161          */
3162         if (host->flags & SDHCI_USE_ADMA) {
3163                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3164                         mmc->max_seg_size = 65535;
3165                 else
3166                         mmc->max_seg_size = 65536;
3167         } else {
3168                 mmc->max_seg_size = mmc->max_req_size;
3169         }
3170
3171         /*
3172          * Maximum block size. This varies from controller to controller and
3173          * is specified in the capabilities register.
3174          */
3175         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3176                 mmc->max_blk_size = 2;
3177         } else {
3178                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3179                                 SDHCI_MAX_BLOCK_SHIFT;
3180                 if (mmc->max_blk_size >= 3) {
3181                         pr_warning("%s: Invalid maximum block size, "
3182                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3183                         mmc->max_blk_size = 0;
3184                 }
3185         }
3186
3187         mmc->max_blk_size = 512 << mmc->max_blk_size;
3188
3189         /*
3190          * Maximum block count.
3191          */
3192         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3193
3194         /*
3195          * Init tasklets.
3196          */
3197         tasklet_init(&host->card_tasklet,
3198                 sdhci_tasklet_card, (unsigned long)host);
3199         tasklet_init(&host->finish_tasklet,
3200                 sdhci_tasklet_finish, (unsigned long)host);
3201
3202         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3203
3204         if (host->version >= SDHCI_SPEC_300) {
3205                 init_waitqueue_head(&host->buf_ready_int);
3206
3207                 /* Initialize re-tuning timer */
3208                 init_timer(&host->tuning_timer);
3209                 host->tuning_timer.data = (unsigned long)host;
3210                 host->tuning_timer.function = sdhci_tuning_timer;
3211         }
3212
3213         ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
3214                 mmc_hostname(mmc), host);
3215         if (ret) {
3216                 pr_err("%s: Failed to request IRQ %d: %d\n",
3217                        mmc_hostname(mmc), host->irq, ret);
3218                 goto untasklet;
3219         }
3220
3221         sdhci_init(host, 0);
3222
3223 #ifdef CONFIG_MMC_DEBUG
3224         sdhci_dumpregs(host);
3225 #endif
3226
3227 #ifdef SDHCI_USE_LEDS_CLASS
3228         snprintf(host->led_name, sizeof(host->led_name),
3229                 "%s::", mmc_hostname(mmc));
3230         host->led.name = host->led_name;
3231         host->led.brightness = LED_OFF;
3232         host->led.default_trigger = mmc_hostname(mmc);
3233         host->led.brightness_set = sdhci_led_control;
3234
3235         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3236         if (ret) {
3237                 pr_err("%s: Failed to register LED device: %d\n",
3238                        mmc_hostname(mmc), ret);
3239                 goto reset;
3240         }
3241 #endif
3242
3243         mmiowb();
3244
3245         mmc_add_host(mmc);
3246
3247         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3248                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3249                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3250                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3251
3252         sdhci_enable_card_detection(host);
3253
3254         return 0;
3255
3256 #ifdef SDHCI_USE_LEDS_CLASS
3257 reset:
3258         sdhci_reset(host, SDHCI_RESET_ALL);
3259         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3260         free_irq(host->irq, host);
3261 #endif
3262 untasklet:
3263         tasklet_kill(&host->card_tasklet);
3264         tasklet_kill(&host->finish_tasklet);
3265
3266         return ret;
3267 }
3268
3269 EXPORT_SYMBOL_GPL(sdhci_add_host);
3270
3271 void sdhci_remove_host(struct sdhci_host *host, int dead)
3272 {
3273         unsigned long flags;
3274
3275         if (dead) {
3276                 spin_lock_irqsave(&host->lock, flags);
3277
3278                 host->flags |= SDHCI_DEVICE_DEAD;
3279
3280                 if (host->mrq) {
3281                         pr_err("%s: Controller removed during "
3282                                 " transfer!\n", mmc_hostname(host->mmc));
3283
3284                         host->mrq->cmd->error = -ENOMEDIUM;
3285                         tasklet_schedule(&host->finish_tasklet);
3286                 }
3287
3288                 spin_unlock_irqrestore(&host->lock, flags);
3289         }
3290
3291         sdhci_disable_card_detection(host);
3292
3293         mmc_remove_host(host->mmc);
3294
3295 #ifdef SDHCI_USE_LEDS_CLASS
3296         led_classdev_unregister(&host->led);
3297 #endif
3298
3299         if (!dead)
3300                 sdhci_reset(host, SDHCI_RESET_ALL);
3301
3302         sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK);
3303         free_irq(host->irq, host);
3304
3305         del_timer_sync(&host->timer);
3306
3307         tasklet_kill(&host->card_tasklet);
3308         tasklet_kill(&host->finish_tasklet);
3309
3310         if (host->vmmc) {
3311                 regulator_disable(host->vmmc);
3312                 regulator_put(host->vmmc);
3313         }
3314
3315         if (host->vqmmc) {
3316                 regulator_disable(host->vqmmc);
3317                 regulator_put(host->vqmmc);
3318         }
3319
3320         kfree(host->adma_desc);
3321         kfree(host->align_buffer);
3322
3323         host->adma_desc = NULL;
3324         host->align_buffer = NULL;
3325 }
3326
3327 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3328
3329 void sdhci_free_host(struct sdhci_host *host)
3330 {
3331         mmc_free_host(host->mmc);
3332 }
3333
3334 EXPORT_SYMBOL_GPL(sdhci_free_host);
3335
3336 /*****************************************************************************\
3337  *                                                                           *
3338  * Driver init/exit                                                          *
3339  *                                                                           *
3340 \*****************************************************************************/
3341
3342 static int __init sdhci_drv_init(void)
3343 {
3344         pr_info(DRIVER_NAME
3345                 ": Secure Digital Host Controller Interface driver\n");
3346         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3347
3348         return 0;
3349 }
3350
3351 static void __exit sdhci_drv_exit(void)
3352 {
3353 }
3354
3355 module_init(sdhci_drv_init);
3356 module_exit(sdhci_drv_exit);
3357
3358 module_param(debug_quirks, uint, 0444);
3359 module_param(debug_quirks2, uint, 0444);
3360
3361 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3362 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3363 MODULE_LICENSE("GPL");
3364
3365 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3366 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");