drivers/mtd/nand/bf5xx_nand.c

   1 /* linux/drivers/mtd/nand/bf5xx_nand.c
   2  *
   3  * Copyright 2006-2008 Analog Devices Inc.
   4  *      http://blackfin.uclinux.org/
   5  *      Bryan Wu <bryan.wu@analog.com>
   6  *
   7  * Blackfin BF5xx on-chip NAND flash controller driver
   8  *
   9  * Derived from drivers/mtd/nand/s3c2410.c
  10  * Copyright (c) 2007 Ben Dooks <ben@simtec.co.uk>
  11  *
  12  * Derived from drivers/mtd/nand/cafe.c
  13  * Copyright © 2006 Red Hat, Inc.
  14  * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
  15  *
  16  * Changelog:
  17  *      12-Jun-2007  Bryan Wu:  Initial version
  18  *      18-Jul-2007  Bryan Wu:
  19  *              - ECC_HW and ECC_SW supported
  20  *              - DMA supported in ECC_HW
  21  *              - YAFFS tested as rootfs in both ECC_HW and ECC_SW
  22  *
  23  * This program is free software; you can redistribute it and/or modify
  24  * it under the terms of the GNU General Public License as published by
  25  * the Free Software Foundation; either version 2 of the License, or
  26  * (at your option) any later version.
  27  *
  28  * This program is distributed in the hope that it will be useful,
  29  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  31  * GNU General Public License for more details.
  32  *
  33  * You should have received a copy of the GNU General Public License
  34  * along with this program; if not, write to the Free Software
  35  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  36 */
  37
  38 #include <linux/module.h>
  39 #include <linux/types.h>
  40 #include <linux/kernel.h>
  41 #include <linux/string.h>
  42 #include <linux/ioport.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/delay.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/err.h>
  47 #include <linux/slab.h>
  48 #include <linux/io.h>
  49 #include <linux/bitops.h>
  50
  51 #include <linux/mtd/mtd.h>
  52 #include <linux/mtd/nand.h>
  53 #include <linux/mtd/nand_ecc.h>
  54 #include <linux/mtd/partitions.h>
  55
  56 #include <asm/blackfin.h>
  57 #include <asm/dma.h>
  58 #include <asm/cacheflush.h>
  59 #include <asm/nand.h>
  60 #include <asm/portmux.h>
  61
  62 #define DRV_NAME        "bf5xx-nand"
  63 #define DRV_VERSION     "1.2"
  64 #define DRV_AUTHOR      "Bryan Wu <bryan.wu@analog.com>"
  65 #define DRV_DESC        "BF5xx on-chip NAND FLash Controller Driver"
  66
  67 /* NFC_STAT Masks */
  68 #define NBUSY       0x01  /* Not Busy */
  69 #define WB_FULL     0x02  /* Write Buffer Full */
  70 #define PG_WR_STAT  0x04  /* Page Write Pending */
  71 #define PG_RD_STAT  0x08  /* Page Read Pending */
  72 #define WB_EMPTY    0x10  /* Write Buffer Empty */
  73
  74 /* NFC_IRQSTAT Masks */
  75 #define NBUSYIRQ    0x01  /* Not Busy IRQ */
  76 #define WB_OVF      0x02  /* Write Buffer Overflow */
  77 #define WB_EDGE     0x04  /* Write Buffer Edge Detect */
  78 #define RD_RDY      0x08  /* Read Data Ready */
  79 #define WR_DONE     0x10  /* Page Write Done */
  80
  81 /* NFC_RST Masks */
  82 #define ECC_RST     0x01  /* ECC (and NFC counters) Reset */
  83
  84 /* NFC_PGCTL Masks */
  85 #define PG_RD_START 0x01  /* Page Read Start */
  86 #define PG_WR_START 0x02  /* Page Write Start */
  87
  88 #ifdef CONFIG_MTD_NAND_BF5XX_HWECC
  89 static int hardware_ecc = 1;
  90 #else
  91 static int hardware_ecc;
  92 #endif
  93
  94 static const unsigned short bfin_nfc_pin_req[] =
  95         {P_NAND_CE,
  96          P_NAND_RB,
  97          P_NAND_D0,
  98          P_NAND_D1,
  99          P_NAND_D2,
 100          P_NAND_D3,
 101          P_NAND_D4,
 102          P_NAND_D5,
 103          P_NAND_D6,
 104          P_NAND_D7,
 105          P_NAND_WE,
 106          P_NAND_RE,
 107          P_NAND_CLE,
 108          P_NAND_ALE,
 109          0};
 110
 111 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 112 static struct nand_ecclayout bootrom_ecclayout = {
 113         .eccbytes = 24,
 114         .eccpos = {
 115                 0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
 116                 0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
 117                 0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
 118                 0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
 119                 0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
 120                 0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
 121                 0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
 122                 0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
 123         },
 124         .oobfree = {
 125                 { 0x8 * 0 + 3, 5 },
 126                 { 0x8 * 1 + 3, 5 },
 127                 { 0x8 * 2 + 3, 5 },
 128                 { 0x8 * 3 + 3, 5 },
 129                 { 0x8 * 4 + 3, 5 },
 130                 { 0x8 * 5 + 3, 5 },
 131                 { 0x8 * 6 + 3, 5 },
 132                 { 0x8 * 7 + 3, 5 },
 133         }
 134 };
 135 #endif
 136
 137 /*
 138  * Data structures for bf5xx nand flash controller driver
 139  */
 140
 141 /* bf5xx nand info */
 142 struct bf5xx_nand_info {
 143         /* mtd info */
 144         struct nand_hw_control          controller;
 145         struct nand_chip                chip;
 146
 147         /* platform info */
 148         struct bf5xx_nand_platform      *platform;
 149
 150         /* device info */
 151         struct device                   *device;
 152
 153         /* DMA stuff */
 154         struct completion               dma_completion;
 155 };
 156
 157 /*
 158  * Conversion functions
 159  */
 160 static struct bf5xx_nand_info *mtd_to_nand_info(struct mtd_info *mtd)
 161 {
 162         return container_of(mtd_to_nand(mtd), struct bf5xx_nand_info,
 163                             chip);
 164 }
 165
 166 static struct bf5xx_nand_info *to_nand_info(struct platform_device *pdev)
 167 {
 168         return platform_get_drvdata(pdev);
 169 }
 170
 171 static struct bf5xx_nand_platform *to_nand_plat(struct platform_device *pdev)
 172 {
 173         return dev_get_platdata(&pdev->dev);
 174 }
 175
 176 /*
 177  * struct nand_chip interface function pointers
 178  */
 179
 180 /*
 181  * bf5xx_nand_hwcontrol
 182  *
 183  * Issue command and address cycles to the chip
 184  */
 185 static void bf5xx_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 186                                    unsigned int ctrl)
 187 {
 188         if (cmd == NAND_CMD_NONE)
 189                 return;
 190
 191         while (bfin_read_NFC_STAT() & WB_FULL)
 192                 cpu_relax();
 193
 194         if (ctrl & NAND_CLE)
 195                 bfin_write_NFC_CMD(cmd);
 196         else if (ctrl & NAND_ALE)
 197                 bfin_write_NFC_ADDR(cmd);
 198         SSYNC();
 199 }
 200
 201 /*
 202  * bf5xx_nand_devready()
 203  *
 204  * returns 0 if the nand is busy, 1 if it is ready
 205  */
 206 static int bf5xx_nand_devready(struct mtd_info *mtd)
 207 {
 208         unsigned short val = bfin_read_NFC_STAT();
 209
 210         if ((val & NBUSY) == NBUSY)
 211                 return 1;
 212         else
 213                 return 0;
 214 }
 215
 216 /*
 217  * ECC functions
 218  * These allow the bf5xx to use the controller's ECC
 219  * generator block to ECC the data as it passes through
 220  */
 221
 222 /*
 223  * ECC error correction function
 224  */
 225 static int bf5xx_nand_correct_data_256(struct mtd_info *mtd, u_char *dat,
 226                                         u_char *read_ecc, u_char *calc_ecc)
 227 {
 228         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 229         u32 syndrome[5];
 230         u32 calced, stored;
 231         int i;
 232         unsigned short failing_bit, failing_byte;
 233         u_char data;
 234
 235         calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
 236         stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
 237
 238         syndrome[0] = (calced ^ stored);
 239
 240         /*
 241          * syndrome 0: all zero
 242          * No error in data
 243          * No action
 244          */
 245         if (!syndrome[0] || !calced || !stored)
 246                 return 0;
 247
 248         /*
 249          * sysdrome 0: only one bit is one
 250          * ECC data was incorrect
 251          * No action
 252          */
 253         if (hweight32(syndrome[0]) == 1) {
 254                 dev_err(info->device, "ECC data was incorrect!\n");
 255                 return -EBADMSG;
 256         }
 257
 258         syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
 259         syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
 260         syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
 261         syndrome[4] = syndrome[2] ^ syndrome[3];
 262
 263         for (i = 0; i < 5; i++)
 264                 dev_info(info->device, "syndrome[%d] 0x%08x\n", i, syndrome[i]);
 265
 266         dev_info(info->device,
 267                 "calced[0x%08x], stored[0x%08x]\n",
 268                 calced, stored);
 269
 270         /*
 271          * sysdrome 0: exactly 11 bits are one, each parity
 272          * and parity' pair is 1 & 0 or 0 & 1.
 273          * 1-bit correctable error
 274          * Correct the error
 275          */
 276         if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
 277                 dev_info(info->device,
 278                         "1-bit correctable error, correct it.\n");
 279                 dev_info(info->device,
 280                         "syndrome[1] 0x%08x\n", syndrome[1]);
 281
 282                 failing_bit = syndrome[1] & 0x7;
 283                 failing_byte = syndrome[1] >> 0x3;
 284                 data = *(dat + failing_byte);
 285                 data = data ^ (0x1 << failing_bit);
 286                 *(dat + failing_byte) = data;
 287
 288                 return 1;
 289         }
 290
 291         /*
 292          * sysdrome 0: random data
 293          * More than 1-bit error, non-correctable error
 294          * Discard data, mark bad block
 295          */
 296         dev_err(info->device,
 297                 "More than 1-bit error, non-correctable error.\n");
 298         dev_err(info->device,
 299                 "Please discard data, mark bad block\n");
 300
 301         return -EBADMSG;
 302 }
 303
 304 static int bf5xx_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 305                                         u_char *read_ecc, u_char *calc_ecc)
 306 {
 307         struct nand_chip *chip = mtd_to_nand(mtd);
 308         int ret, bitflips = 0;
 309
 310         ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 311         if (ret < 0)
 312                 return ret;
 313
 314         bitflips = ret;
 315
 316         /* If ecc size is 512, correct second 256 bytes */
 317         if (chip->ecc.size == 512) {
 318                 dat += 256;
 319                 read_ecc += 3;
 320                 calc_ecc += 3;
 321                 ret = bf5xx_nand_correct_data_256(mtd, dat, read_ecc, calc_ecc);
 322                 if (ret < 0)
 323                         return ret;
 324
 325                 bitflips += ret;
 326         }
 327
 328         return bitflips;
 329 }
 330
 331 static void bf5xx_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 332 {
 333         return;
 334 }
 335
 336 static int bf5xx_nand_calculate_ecc(struct mtd_info *mtd,
 337                 const u_char *dat, u_char *ecc_code)
 338 {
 339         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 340         struct nand_chip *chip = mtd_to_nand(mtd);
 341         u16 ecc0, ecc1;
 342         u32 code[2];
 343         u8 *p;
 344
 345         /* first 3 bytes ECC code for 256 page size */
 346         ecc0 = bfin_read_NFC_ECC0();
 347         ecc1 = bfin_read_NFC_ECC1();
 348
 349         code[0] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 350
 351         dev_dbg(info->device, "returning ecc 0x%08x\n", code[0]);
 352
 353         p = (u8 *) code;
 354         memcpy(ecc_code, p, 3);
 355
 356         /* second 3 bytes ECC code for 512 ecc size */
 357         if (chip->ecc.size == 512) {
 358                 ecc0 = bfin_read_NFC_ECC2();
 359                 ecc1 = bfin_read_NFC_ECC3();
 360                 code[1] = (ecc0 & 0x7ff) | ((ecc1 & 0x7ff) << 11);
 361
 362                 /* second 3 bytes in ecc_code for second 256
 363                  * bytes of 512 page size
 364                  */
 365                 p = (u8 *) (code + 1);
 366                 memcpy((ecc_code + 3), p, 3);
 367                 dev_dbg(info->device, "returning ecc 0x%08x\n", code[1]);
 368         }
 369
 370         return 0;
 371 }
 372
 373 /*
 374  * PIO mode for buffer writing and reading
 375  */
 376 static void bf5xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 377 {
 378         int i;
 379         unsigned short val;
 380
 381         /*
 382          * Data reads are requested by first writing to NFC_DATA_RD
 383          * and then reading back from NFC_READ.
 384          */
 385         for (i = 0; i < len; i++) {
 386                 while (bfin_read_NFC_STAT() & WB_FULL)
 387                         cpu_relax();
 388
 389                 /* Contents do not matter */
 390                 bfin_write_NFC_DATA_RD(0x0000);
 391                 SSYNC();
 392
 393                 while ((bfin_read_NFC_IRQSTAT() & RD_RDY) != RD_RDY)
 394                         cpu_relax();
 395
 396                 buf[i] = bfin_read_NFC_READ();
 397
 398                 val = bfin_read_NFC_IRQSTAT();
 399                 val |= RD_RDY;
 400                 bfin_write_NFC_IRQSTAT(val);
 401                 SSYNC();
 402         }
 403 }
 404
 405 static uint8_t bf5xx_nand_read_byte(struct mtd_info *mtd)
 406 {
 407         uint8_t val;
 408
 409         bf5xx_nand_read_buf(mtd, &val, 1);
 410
 411         return val;
 412 }
 413
 414 static void bf5xx_nand_write_buf(struct mtd_info *mtd,
 415                                 const uint8_t *buf, int len)
 416 {
 417         int i;
 418
 419         for (i = 0; i < len; i++) {
 420                 while (bfin_read_NFC_STAT() & WB_FULL)
 421                         cpu_relax();
 422
 423                 bfin_write_NFC_DATA_WR(buf[i]);
 424                 SSYNC();
 425         }
 426 }
 427
 428 static void bf5xx_nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
 429 {
 430         int i;
 431         u16 *p = (u16 *) buf;
 432         len >>= 1;
 433
 434         /*
 435          * Data reads are requested by first writing to NFC_DATA_RD
 436          * and then reading back from NFC_READ.
 437          */
 438         bfin_write_NFC_DATA_RD(0x5555);
 439
 440         SSYNC();
 441
 442         for (i = 0; i < len; i++)
 443                 p[i] = bfin_read_NFC_READ();
 444 }
 445
 446 static void bf5xx_nand_write_buf16(struct mtd_info *mtd,
 447                                 const uint8_t *buf, int len)
 448 {
 449         int i;
 450         u16 *p = (u16 *) buf;
 451         len >>= 1;
 452
 453         for (i = 0; i < len; i++)
 454                 bfin_write_NFC_DATA_WR(p[i]);
 455
 456         SSYNC();
 457 }
 458
 459 /*
 460  * DMA functions for buffer writing and reading
 461  */
 462 static irqreturn_t bf5xx_nand_dma_irq(int irq, void *dev_id)
 463 {
 464         struct bf5xx_nand_info *info = dev_id;
 465
 466         clear_dma_irqstat(CH_NFC);
 467         disable_dma(CH_NFC);
 468         complete(&info->dma_completion);
 469
 470         return IRQ_HANDLED;
 471 }
 472
 473 static void bf5xx_nand_dma_rw(struct mtd_info *mtd,
 474                                 uint8_t *buf, int is_read)
 475 {
 476         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 477         struct nand_chip *chip = mtd_to_nand(mtd);
 478         unsigned short val;
 479
 480         dev_dbg(info->device, " mtd->%p, buf->%p, is_read %d\n",
 481                         mtd, buf, is_read);
 482
 483         /*
 484          * Before starting a dma transfer, be sure to invalidate/flush
 485          * the cache over the address range of your DMA buffer to
 486          * prevent cache coherency problems. Otherwise very subtle bugs
 487          * can be introduced to your driver.
 488          */
 489         if (is_read)
 490                 invalidate_dcache_range((unsigned int)buf,
 491                                 (unsigned int)(buf + chip->ecc.size));
 492         else
 493                 flush_dcache_range((unsigned int)buf,
 494                                 (unsigned int)(buf + chip->ecc.size));
 495
 496         /*
 497          * This register must be written before each page is
 498          * transferred to generate the correct ECC register
 499          * values.
 500          */
 501         bfin_write_NFC_RST(ECC_RST);
 502         SSYNC();
 503         while (bfin_read_NFC_RST() & ECC_RST)
 504                 cpu_relax();
 505
 506         disable_dma(CH_NFC);
 507         clear_dma_irqstat(CH_NFC);
 508
 509         /* setup DMA register with Blackfin DMA API */
 510         set_dma_config(CH_NFC, 0x0);
 511         set_dma_start_addr(CH_NFC, (unsigned long) buf);
 512
 513         /* The DMAs have different size on BF52x and BF54x */
 514 #ifdef CONFIG_BF52x
 515         set_dma_x_count(CH_NFC, (chip->ecc.size >> 1));
 516         set_dma_x_modify(CH_NFC, 2);
 517         val = DI_EN | WDSIZE_16;
 518 #endif
 519
 520 #ifdef CONFIG_BF54x
 521         set_dma_x_count(CH_NFC, (chip->ecc.size >> 2));
 522         set_dma_x_modify(CH_NFC, 4);
 523         val = DI_EN | WDSIZE_32;
 524 #endif
 525         /* setup write or read operation */
 526         if (is_read)
 527                 val |= WNR;
 528         set_dma_config(CH_NFC, val);
 529         enable_dma(CH_NFC);
 530
 531         /* Start PAGE read/write operation */
 532         if (is_read)
 533                 bfin_write_NFC_PGCTL(PG_RD_START);
 534         else
 535                 bfin_write_NFC_PGCTL(PG_WR_START);
 536         wait_for_completion(&info->dma_completion);
 537 }
 538
 539 static void bf5xx_nand_dma_read_buf(struct mtd_info *mtd,
 540                                         uint8_t *buf, int len)
 541 {
 542         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 543         struct nand_chip *chip = mtd_to_nand(mtd);
 544
 545         dev_dbg(info->device, "mtd->%p, buf->%p, int %d\n", mtd, buf, len);
 546
 547         if (len == chip->ecc.size)
 548                 bf5xx_nand_dma_rw(mtd, buf, 1);
 549         else
 550                 bf5xx_nand_read_buf(mtd, buf, len);
 551 }
 552
 553 static void bf5xx_nand_dma_write_buf(struct mtd_info *mtd,
 554                                 const uint8_t *buf, int len)
 555 {
 556         struct bf5xx_nand_info *info = mtd_to_nand_info(mtd);
 557         struct nand_chip *chip = mtd_to_nand(mtd);
 558
 559         dev_dbg(info->device, "mtd->%p, buf->%p, len %d\n", mtd, buf, len);
 560
 561         if (len == chip->ecc.size)
 562                 bf5xx_nand_dma_rw(mtd, (uint8_t *)buf, 0);
 563         else
 564                 bf5xx_nand_write_buf(mtd, buf, len);
 565 }
 566
 567 static int bf5xx_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
 568                 uint8_t *buf, int oob_required, int page)
 569 {
 570         bf5xx_nand_read_buf(mtd, buf, mtd->writesize);
 571         bf5xx_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 572
 573         return 0;
 574 }
 575
 576 static int bf5xx_nand_write_page_raw(struct mtd_info *mtd,
 577                 struct nand_chip *chip, const uint8_t *buf, int oob_required,
 578                 int page)
 579 {
 580         bf5xx_nand_write_buf(mtd, buf, mtd->writesize);
 581         bf5xx_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 582
 583         return 0;
 584 }
 585
 586 /*
 587  * System initialization functions
 588  */
 589 static int bf5xx_nand_dma_init(struct bf5xx_nand_info *info)
 590 {
 591         int ret;
 592
 593         /* Do not use dma */
 594         if (!hardware_ecc)
 595                 return 0;
 596
 597         init_completion(&info->dma_completion);
 598
 599         /* Request NFC DMA channel */
 600         ret = request_dma(CH_NFC, "BF5XX NFC driver");
 601         if (ret < 0) {
 602                 dev_err(info->device, " unable to get DMA channel\n");
 603                 return ret;
 604         }
 605
 606 #ifdef CONFIG_BF54x
 607         /* Setup DMAC1 channel mux for NFC which shared with SDH */
 608         bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() & ~1);
 609         SSYNC();
 610 #endif
 611
 612         set_dma_callback(CH_NFC, bf5xx_nand_dma_irq, info);
 613
 614         /* Turn off the DMA channel first */
 615         disable_dma(CH_NFC);
 616         return 0;
 617 }
 618
 619 static void bf5xx_nand_dma_remove(struct bf5xx_nand_info *info)
 620 {
 621         /* Free NFC DMA channel */
 622         if (hardware_ecc)
 623                 free_dma(CH_NFC);
 624 }
 625
 626 /*
 627  * BF5XX NFC hardware initialization
 628  *  - pin mux setup
 629  *  - clear interrupt status
 630  */
 631 static int bf5xx_nand_hw_init(struct bf5xx_nand_info *info)
 632 {
 633         int err = 0;
 634         unsigned short val;
 635         struct bf5xx_nand_platform *plat = info->platform;
 636
 637         /* setup NFC_CTL register */
 638         dev_info(info->device,
 639                 "data_width=%d, wr_dly=%d, rd_dly=%d\n",
 640                 (plat->data_width ? 16 : 8),
 641                 plat->wr_dly, plat->rd_dly);
 642
 643         val = (1 << NFC_PG_SIZE_OFFSET) |
 644                 (plat->data_width << NFC_NWIDTH_OFFSET) |
 645                 (plat->rd_dly << NFC_RDDLY_OFFSET) |
 646                 (plat->wr_dly << NFC_WRDLY_OFFSET);
 647         dev_dbg(info->device, "NFC_CTL is 0x%04x\n", val);
 648
 649         bfin_write_NFC_CTL(val);
 650         SSYNC();
 651
 652         /* clear interrupt status */
 653         bfin_write_NFC_IRQMASK(0x0);
 654         SSYNC();
 655         val = bfin_read_NFC_IRQSTAT();
 656         bfin_write_NFC_IRQSTAT(val);
 657         SSYNC();
 658
 659         /* DMA initialization  */
 660         if (bf5xx_nand_dma_init(info))
 661                 err = -ENXIO;
 662
 663         return err;
 664 }
 665
 666 /*
 667  * Device management interface
 668  */
 669 static int bf5xx_nand_add_partition(struct bf5xx_nand_info *info)
 670 {
 671         struct mtd_info *mtd = nand_to_mtd(&info->chip);
 672         struct mtd_partition *parts = info->platform->partitions;
 673         int nr = info->platform->nr_partitions;
 674
 675         return mtd_device_register(mtd, parts, nr);
 676 }
 677
 678 static int bf5xx_nand_remove(struct platform_device *pdev)
 679 {
 680         struct bf5xx_nand_info *info = to_nand_info(pdev);
 681
 682         /* first thing we need to do is release all our mtds
 683          * and their partitions, then go through freeing the
 684          * resources used
 685          */
 686         nand_release(nand_to_mtd(&info->chip));
 687
 688         peripheral_free_list(bfin_nfc_pin_req);
 689         bf5xx_nand_dma_remove(info);
 690
 691         return 0;
 692 }
 693
 694 static int bf5xx_nand_scan(struct mtd_info *mtd)
 695 {
 696         struct nand_chip *chip = mtd_to_nand(mtd);
 697         int ret;
 698
 699         ret = nand_scan_ident(mtd, 1, NULL);
 700         if (ret)
 701                 return ret;
 702
 703         if (hardware_ecc) {
 704                 /*
 705                  * for nand with page size > 512B, think it as several sections with 512B
 706                  */
 707                 if (likely(mtd->writesize >= 512)) {
 708                         chip->ecc.size = 512;
 709                         chip->ecc.bytes = 6;
 710                         chip->ecc.strength = 2;
 711                 } else {
 712                         chip->ecc.size = 256;
 713                         chip->ecc.bytes = 3;
 714                         chip->ecc.strength = 1;
 715                         bfin_write_NFC_CTL(bfin_read_NFC_CTL() & ~(1 << NFC_PG_SIZE_OFFSET));
 716                         SSYNC();
 717                 }
 718         }
 719
 720         return  nand_scan_tail(mtd);
 721 }
 722
 723 /*
 724  * bf5xx_nand_probe
 725  *
 726  * called by device layer when it finds a device matching
 727  * one our driver can handled. This code checks to see if
 728  * it can allocate all necessary resources then calls the
 729  * nand layer to look for devices
 730  */
 731 static int bf5xx_nand_probe(struct platform_device *pdev)
 732 {
 733         struct bf5xx_nand_platform *plat = to_nand_plat(pdev);
 734         struct bf5xx_nand_info *info = NULL;
 735         struct nand_chip *chip = NULL;
 736         struct mtd_info *mtd = NULL;
 737         int err = 0;
 738
 739         dev_dbg(&pdev->dev, "(%p)\n", pdev);
 740
 741         if (!plat) {
 742                 dev_err(&pdev->dev, "no platform specific information\n");
 743                 return -EINVAL;
 744         }
 745
 746         if (peripheral_request_list(bfin_nfc_pin_req, DRV_NAME)) {
 747                 dev_err(&pdev->dev, "requesting Peripherals failed\n");
 748                 return -EFAULT;
 749         }
 750
 751         info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
 752         if (info == NULL) {
 753                 err = -ENOMEM;
 754                 goto out_err;
 755         }
 756
 757         platform_set_drvdata(pdev, info);
 758
 759         spin_lock_init(&info->controller.lock);
 760         init_waitqueue_head(&info->controller.wq);
 761
 762         info->device     = &pdev->dev;
 763         info->platform   = plat;
 764
 765         /* initialise chip data struct */
 766         chip = &info->chip;
 767         mtd = nand_to_mtd(&info->chip);
 768
 769         if (plat->data_width)
 770                 chip->options |= NAND_BUSWIDTH_16;
 771
 772         chip->options |= NAND_CACHEPRG | NAND_SKIP_BBTSCAN;
 773
 774         chip->read_buf = (plat->data_width) ?
 775                 bf5xx_nand_read_buf16 : bf5xx_nand_read_buf;
 776         chip->write_buf = (plat->data_width) ?
 777                 bf5xx_nand_write_buf16 : bf5xx_nand_write_buf;
 778
 779         chip->read_byte    = bf5xx_nand_read_byte;
 780
 781         chip->cmd_ctrl     = bf5xx_nand_hwcontrol;
 782         chip->dev_ready    = bf5xx_nand_devready;
 783
 784         nand_set_controller_data(chip, mtd);
 785         chip->controller   = &info->controller;
 786
 787         chip->IO_ADDR_R    = (void __iomem *) NFC_READ;
 788         chip->IO_ADDR_W    = (void __iomem *) NFC_DATA_WR;
 789
 790         chip->chip_delay   = 0;
 791
 792         /* initialise mtd info data struct */
 793         mtd->dev.parent = &pdev->dev;
 794
 795         /* initialise the hardware */
 796         err = bf5xx_nand_hw_init(info);
 797         if (err)
 798                 goto out_err;
 799
 800         /* setup hardware ECC data struct */
 801         if (hardware_ecc) {
 802 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 803                 chip->ecc.layout = &bootrom_ecclayout;
 804 #endif
 805                 chip->read_buf      = bf5xx_nand_dma_read_buf;
 806                 chip->write_buf     = bf5xx_nand_dma_write_buf;
 807                 chip->ecc.calculate = bf5xx_nand_calculate_ecc;
 808                 chip->ecc.correct   = bf5xx_nand_correct_data;
 809                 chip->ecc.mode      = NAND_ECC_HW;
 810                 chip->ecc.hwctl     = bf5xx_nand_enable_hwecc;
 811                 chip->ecc.read_page_raw = bf5xx_nand_read_page_raw;
 812                 chip->ecc.write_page_raw = bf5xx_nand_write_page_raw;
 813         } else {
 814                 chip->ecc.mode      = NAND_ECC_SOFT;
 815         }
 816
 817         /* scan hardware nand chip and setup mtd info data struct */
 818         if (bf5xx_nand_scan(mtd)) {
 819                 err = -ENXIO;
 820                 goto out_err_nand_scan;
 821         }
 822
 823 #ifdef CONFIG_MTD_NAND_BF5XX_BOOTROM_ECC
 824         chip->badblockpos = 63;
 825 #endif
 826
 827         /* add NAND partition */
 828         bf5xx_nand_add_partition(info);
 829
 830         dev_dbg(&pdev->dev, "initialised ok\n");
 831         return 0;
 832
 833 out_err_nand_scan:
 834         bf5xx_nand_dma_remove(info);
 835 out_err:
 836         peripheral_free_list(bfin_nfc_pin_req);
 837
 838         return err;
 839 }
 840
 841 /* driver device registration */
 842 static struct platform_driver bf5xx_nand_driver = {
 843         .probe          = bf5xx_nand_probe,
 844         .remove         = bf5xx_nand_remove,
 845         .driver         = {
 846                 .name   = DRV_NAME,
 847         },
 848 };
 849
 850 module_platform_driver(bf5xx_nand_driver);
 851
 852 MODULE_LICENSE("GPL");
 853 MODULE_AUTHOR(DRV_AUTHOR);
 854 MODULE_DESCRIPTION(DRV_DESC);
 855 MODULE_ALIAS("platform:" DRV_NAME);