drivers/net/can/pch_can.c

   1 /*
   2  * Copyright (C) 1999 - 2010 Intel Corporation.
   3  * Copyright (C) 2010 OKI SEMICONDUCTOR CO., LTD.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/io.h>
  22 #include <linux/module.h>
  23 #include <linux/sched.h>
  24 #include <linux/pci.h>
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/types.h>
  28 #include <linux/errno.h>
  29 #include <linux/netdevice.h>
  30 #include <linux/skbuff.h>
  31 #include <linux/can.h>
  32 #include <linux/can/dev.h>
  33 #include <linux/can/error.h>
  34
  35 #define PCH_CTRL_INIT           BIT(0) /* The INIT bit of CANCONT register. */
  36 #define PCH_CTRL_IE             BIT(1) /* The IE bit of CAN control register */
  37 #define PCH_CTRL_IE_SIE_EIE     (BIT(3) | BIT(2) | BIT(1))
  38 #define PCH_CTRL_CCE            BIT(6)
  39 #define PCH_CTRL_OPT            BIT(7) /* The OPT bit of CANCONT register. */
  40 #define PCH_OPT_SILENT          BIT(3) /* The Silent bit of CANOPT reg. */
  41 #define PCH_OPT_LBACK           BIT(4) /* The LoopBack bit of CANOPT reg. */
  42
  43 #define PCH_CMASK_RX_TX_SET     0x00f3
  44 #define PCH_CMASK_RX_TX_GET     0x0073
  45 #define PCH_CMASK_ALL           0xff
  46 #define PCH_CMASK_NEWDAT        BIT(2)
  47 #define PCH_CMASK_CLRINTPND     BIT(3)
  48 #define PCH_CMASK_CTRL          BIT(4)
  49 #define PCH_CMASK_ARB           BIT(5)
  50 #define PCH_CMASK_MASK          BIT(6)
  51 #define PCH_CMASK_RDWR          BIT(7)
  52 #define PCH_IF_MCONT_NEWDAT     BIT(15)
  53 #define PCH_IF_MCONT_MSGLOST    BIT(14)
  54 #define PCH_IF_MCONT_INTPND     BIT(13)
  55 #define PCH_IF_MCONT_UMASK      BIT(12)
  56 #define PCH_IF_MCONT_TXIE       BIT(11)
  57 #define PCH_IF_MCONT_RXIE       BIT(10)
  58 #define PCH_IF_MCONT_RMTEN      BIT(9)
  59 #define PCH_IF_MCONT_TXRQXT     BIT(8)
  60 #define PCH_IF_MCONT_EOB        BIT(7)
  61 #define PCH_IF_MCONT_DLC        (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  62 #define PCH_MASK2_MDIR_MXTD     (BIT(14) | BIT(15))
  63 #define PCH_ID2_DIR             BIT(13)
  64 #define PCH_ID2_XTD             BIT(14)
  65 #define PCH_ID_MSGVAL           BIT(15)
  66 #define PCH_IF_CREQ_BUSY        BIT(15)
  67
  68 #define PCH_STATUS_INT          0x8000
  69 #define PCH_REC                 0x00007f00
  70 #define PCH_TEC                 0x000000ff
  71
  72 #define PCH_TX_OK               BIT(3)
  73 #define PCH_RX_OK               BIT(4)
  74 #define PCH_EPASSIV             BIT(5)
  75 #define PCH_EWARN               BIT(6)
  76 #define PCH_BUS_OFF             BIT(7)
  77
  78 /* bit position of certain controller bits. */
  79 #define PCH_BIT_BRP_SHIFT       0
  80 #define PCH_BIT_SJW_SHIFT       6
  81 #define PCH_BIT_TSEG1_SHIFT     8
  82 #define PCH_BIT_TSEG2_SHIFT     12
  83 #define PCH_BIT_BRPE_BRPE_SHIFT 6
  84
  85 #define PCH_MSK_BITT_BRP        0x3f
  86 #define PCH_MSK_BRPE_BRPE       0x3c0
  87 #define PCH_MSK_CTRL_IE_SIE_EIE 0x07
  88 #define PCH_COUNTER_LIMIT       10
  89
  90 #define PCH_CAN_CLK             50000000        /* 50MHz */
  91
  92 /*
  93  * Define the number of message object.
  94  * PCH CAN communications are done via Message RAM.
  95  * The Message RAM consists of 32 message objects.
  96  */
  97 #define PCH_RX_OBJ_NUM          26
  98 #define PCH_TX_OBJ_NUM          6
  99 #define PCH_RX_OBJ_START        1
 100 #define PCH_RX_OBJ_END          PCH_RX_OBJ_NUM
 101 #define PCH_TX_OBJ_START        (PCH_RX_OBJ_END + 1)
 102 #define PCH_TX_OBJ_END          (PCH_RX_OBJ_NUM + PCH_TX_OBJ_NUM)
 103
 104 #define PCH_FIFO_THRESH         16
 105
 106 /* TxRqst2 show status of MsgObjNo.17~32 */
 107 #define PCH_TREQ2_TX_MASK       (((1 << PCH_TX_OBJ_NUM) - 1) <<\
 108                                                         (PCH_RX_OBJ_END - 16))
 109
 110 enum pch_ifreg {
 111         PCH_RX_IFREG,
 112         PCH_TX_IFREG,
 113 };
 114
 115 enum pch_can_err {
 116         PCH_STUF_ERR = 1,
 117         PCH_FORM_ERR,
 118         PCH_ACK_ERR,
 119         PCH_BIT1_ERR,
 120         PCH_BIT0_ERR,
 121         PCH_CRC_ERR,
 122         PCH_LEC_ALL,
 123 };
 124
 125 enum pch_can_mode {
 126         PCH_CAN_ENABLE,
 127         PCH_CAN_DISABLE,
 128         PCH_CAN_ALL,
 129         PCH_CAN_NONE,
 130         PCH_CAN_STOP,
 131         PCH_CAN_RUN,
 132 };
 133
 134 struct pch_can_if_regs {
 135         u32 creq;
 136         u32 cmask;
 137         u32 mask1;
 138         u32 mask2;
 139         u32 id1;
 140         u32 id2;
 141         u32 mcont;
 142         u32 data[4];
 143         u32 rsv[13];
 144 };
 145
 146 struct pch_can_regs {
 147         u32 cont;
 148         u32 stat;
 149         u32 errc;
 150         u32 bitt;
 151         u32 intr;
 152         u32 opt;
 153         u32 brpe;
 154         u32 reserve;
 155         struct pch_can_if_regs ifregs[2]; /* [0]=if1  [1]=if2 */
 156         u32 reserve1[8];
 157         u32 treq1;
 158         u32 treq2;
 159         u32 reserve2[6];
 160         u32 data1;
 161         u32 data2;
 162         u32 reserve3[6];
 163         u32 canipend1;
 164         u32 canipend2;
 165         u32 reserve4[6];
 166         u32 canmval1;
 167         u32 canmval2;
 168         u32 reserve5[37];
 169         u32 srst;
 170 };
 171
 172 struct pch_can_priv {
 173         struct can_priv can;
 174         struct pci_dev *dev;
 175         u32 tx_enable[PCH_TX_OBJ_END];
 176         u32 rx_enable[PCH_TX_OBJ_END];
 177         u32 rx_link[PCH_TX_OBJ_END];
 178         u32 int_enables;
 179         struct net_device *ndev;
 180         struct pch_can_regs __iomem *regs;
 181         struct napi_struct napi;
 182         int tx_obj;     /* Point next Tx Obj index */
 183         int use_msi;
 184 };
 185
 186 static struct can_bittiming_const pch_can_bittiming_const = {
 187         .name = KBUILD_MODNAME,
 188         .tseg1_min = 1,
 189         .tseg1_max = 16,
 190         .tseg2_min = 1,
 191         .tseg2_max = 8,
 192         .sjw_max = 4,
 193         .brp_min = 1,
 194         .brp_max = 1024, /* 6bit + extended 4bit */
 195         .brp_inc = 1,
 196 };
 197
 198 static DEFINE_PCI_DEVICE_TABLE(pch_pci_tbl) = {
 199         {PCI_VENDOR_ID_INTEL, 0x8818, PCI_ANY_ID, PCI_ANY_ID,},
 200         {0,}
 201 };
 202 MODULE_DEVICE_TABLE(pci, pch_pci_tbl);
 203
 204 static inline void pch_can_bit_set(void __iomem *addr, u32 mask)
 205 {
 206         iowrite32(ioread32(addr) | mask, addr);
 207 }
 208
 209 static inline void pch_can_bit_clear(void __iomem *addr, u32 mask)
 210 {
 211         iowrite32(ioread32(addr) & ~mask, addr);
 212 }
 213
 214 static void pch_can_set_run_mode(struct pch_can_priv *priv,
 215                                  enum pch_can_mode mode)
 216 {
 217         switch (mode) {
 218         case PCH_CAN_RUN:
 219                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_INIT);
 220                 break;
 221
 222         case PCH_CAN_STOP:
 223                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_INIT);
 224                 break;
 225
 226         default:
 227                 netdev_err(priv->ndev, "%s -> Invalid Mode.\n", __func__);
 228                 break;
 229         }
 230 }
 231
 232 static void pch_can_set_optmode(struct pch_can_priv *priv)
 233 {
 234         u32 reg_val = ioread32(&priv->regs->opt);
 235
 236         if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 237                 reg_val |= PCH_OPT_SILENT;
 238
 239         if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 240                 reg_val |= PCH_OPT_LBACK;
 241
 242         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_OPT);
 243         iowrite32(reg_val, &priv->regs->opt);
 244 }
 245
 246 static void pch_can_rw_msg_obj(void __iomem *creq_addr, u32 num)
 247 {
 248         int counter = PCH_COUNTER_LIMIT;
 249         u32 ifx_creq;
 250
 251         iowrite32(num, creq_addr);
 252         while (counter) {
 253                 ifx_creq = ioread32(creq_addr) & PCH_IF_CREQ_BUSY;
 254                 if (!ifx_creq)
 255                         break;
 256                 counter--;
 257                 udelay(1);
 258         }
 259         if (!counter)
 260                 pr_err("%s:IF1 BUSY Flag is set forever.\n", __func__);
 261 }
 262
 263 static void pch_can_set_int_enables(struct pch_can_priv *priv,
 264                                     enum pch_can_mode interrupt_no)
 265 {
 266         switch (interrupt_no) {
 267         case PCH_CAN_DISABLE:
 268                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE);
 269                 break;
 270
 271         case PCH_CAN_ALL:
 272                 pch_can_bit_set(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 273                 break;
 274
 275         case PCH_CAN_NONE:
 276                 pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 277                 break;
 278
 279         default:
 280                 netdev_err(priv->ndev, "Invalid interrupt number.\n");
 281                 break;
 282         }
 283 }
 284
 285 static void pch_can_set_rxtx(struct pch_can_priv *priv, u32 buff_num,
 286                              int set, enum pch_ifreg dir)
 287 {
 288         u32 ie;
 289
 290         if (dir)
 291                 ie = PCH_IF_MCONT_TXIE;
 292         else
 293                 ie = PCH_IF_MCONT_RXIE;
 294
 295         /* Reading the Msg buffer from Message RAM to IF1/2 registers. */
 296         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
 297         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
 298
 299         /* Setting the IF1/2MASK1 register to access MsgVal and RxIE bits */
 300         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_ARB | PCH_CMASK_CTRL,
 301                   &priv->regs->ifregs[dir].cmask);
 302
 303         if (set) {
 304                 /* Setting the MsgVal and RxIE/TxIE bits */
 305                 pch_can_bit_set(&priv->regs->ifregs[dir].mcont, ie);
 306                 pch_can_bit_set(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
 307         } else {
 308                 /* Clearing the MsgVal and RxIE/TxIE bits */
 309                 pch_can_bit_clear(&priv->regs->ifregs[dir].mcont, ie);
 310                 pch_can_bit_clear(&priv->regs->ifregs[dir].id2, PCH_ID_MSGVAL);
 311         }
 312
 313         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
 314 }
 315
 316 static void pch_can_set_rx_all(struct pch_can_priv *priv, int set)
 317 {
 318         int i;
 319
 320         /* Traversing to obtain the object configured as receivers. */
 321         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++)
 322                 pch_can_set_rxtx(priv, i, set, PCH_RX_IFREG);
 323 }
 324
 325 static void pch_can_set_tx_all(struct pch_can_priv *priv, int set)
 326 {
 327         int i;
 328
 329         /* Traversing to obtain the object configured as transmit object. */
 330         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
 331                 pch_can_set_rxtx(priv, i, set, PCH_TX_IFREG);
 332 }
 333
 334 static u32 pch_can_int_pending(struct pch_can_priv *priv)
 335 {
 336         return ioread32(&priv->regs->intr) & 0xffff;
 337 }
 338
 339 static void pch_can_clear_if_buffers(struct pch_can_priv *priv)
 340 {
 341         int i; /* Msg Obj ID (1~32) */
 342
 343         for (i = PCH_RX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
 344                 iowrite32(PCH_CMASK_RX_TX_SET, &priv->regs->ifregs[0].cmask);
 345                 iowrite32(0xffff, &priv->regs->ifregs[0].mask1);
 346                 iowrite32(0xffff, &priv->regs->ifregs[0].mask2);
 347                 iowrite32(0x0, &priv->regs->ifregs[0].id1);
 348                 iowrite32(0x0, &priv->regs->ifregs[0].id2);
 349                 iowrite32(0x0, &priv->regs->ifregs[0].mcont);
 350                 iowrite32(0x0, &priv->regs->ifregs[0].data[0]);
 351                 iowrite32(0x0, &priv->regs->ifregs[0].data[1]);
 352                 iowrite32(0x0, &priv->regs->ifregs[0].data[2]);
 353                 iowrite32(0x0, &priv->regs->ifregs[0].data[3]);
 354                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK |
 355                           PCH_CMASK_ARB | PCH_CMASK_CTRL,
 356                           &priv->regs->ifregs[0].cmask);
 357                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
 358         }
 359 }
 360
 361 static void pch_can_config_rx_tx_buffers(struct pch_can_priv *priv)
 362 {
 363         int i;
 364
 365         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
 366                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
 367                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
 368
 369                 iowrite32(0x0, &priv->regs->ifregs[0].id1);
 370                 iowrite32(0x0, &priv->regs->ifregs[0].id2);
 371
 372                 pch_can_bit_set(&priv->regs->ifregs[0].mcont,
 373                                 PCH_IF_MCONT_UMASK);
 374
 375                 /* In case FIFO mode, Last EoB of Rx Obj must be 1 */
 376                 if (i == PCH_RX_OBJ_END)
 377                         pch_can_bit_set(&priv->regs->ifregs[0].mcont,
 378                                         PCH_IF_MCONT_EOB);
 379                 else
 380                         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
 381                                           PCH_IF_MCONT_EOB);
 382
 383                 iowrite32(0, &priv->regs->ifregs[0].mask1);
 384                 pch_can_bit_clear(&priv->regs->ifregs[0].mask2,
 385                                   0x1fff | PCH_MASK2_MDIR_MXTD);
 386
 387                 /* Setting CMASK for writing */
 388                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
 389                           PCH_CMASK_CTRL, &priv->regs->ifregs[0].cmask);
 390
 391                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, i);
 392         }
 393
 394         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++) {
 395                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask);
 396                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
 397
 398                 /* Resetting DIR bit for reception */
 399                 iowrite32(0x0, &priv->regs->ifregs[1].id1);
 400                 iowrite32(PCH_ID2_DIR, &priv->regs->ifregs[1].id2);
 401
 402                 /* Setting EOB bit for transmitter */
 403                 iowrite32(PCH_IF_MCONT_EOB | PCH_IF_MCONT_UMASK,
 404                           &priv->regs->ifregs[1].mcont);
 405
 406                 iowrite32(0, &priv->regs->ifregs[1].mask1);
 407                 pch_can_bit_clear(&priv->regs->ifregs[1].mask2, 0x1fff);
 408
 409                 /* Setting CMASK for writing */
 410                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_MASK | PCH_CMASK_ARB |
 411                           PCH_CMASK_CTRL, &priv->regs->ifregs[1].cmask);
 412
 413                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, i);
 414         }
 415 }
 416
 417 static void pch_can_init(struct pch_can_priv *priv)
 418 {
 419         /* Stopping the Can device. */
 420         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 421
 422         /* Clearing all the message object buffers. */
 423         pch_can_clear_if_buffers(priv);
 424
 425         /* Configuring the respective message object as either rx/tx object. */
 426         pch_can_config_rx_tx_buffers(priv);
 427
 428         /* Enabling the interrupts. */
 429         pch_can_set_int_enables(priv, PCH_CAN_ALL);
 430 }
 431
 432 static void pch_can_release(struct pch_can_priv *priv)
 433 {
 434         /* Stooping the CAN device. */
 435         pch_can_set_run_mode(priv, PCH_CAN_STOP);
 436
 437         /* Disabling the interrupts. */
 438         pch_can_set_int_enables(priv, PCH_CAN_NONE);
 439
 440         /* Disabling all the receive object. */
 441         pch_can_set_rx_all(priv, 0);
 442
 443         /* Disabling all the transmit object. */
 444         pch_can_set_tx_all(priv, 0);
 445 }
 446
 447 /* This function clears interrupt(s) from the CAN device. */
 448 static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask)
 449 {
 450         /* Clear interrupt for transmit object */
 451         if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) {
 452                 /* Setting CMASK for clearing the reception interrupts. */
 453                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
 454                           &priv->regs->ifregs[0].cmask);
 455
 456                 /* Clearing the Dir bit. */
 457                 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
 458
 459                 /* Clearing NewDat & IntPnd */
 460                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
 461                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND);
 462
 463                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, mask);
 464         } else if ((mask >= PCH_TX_OBJ_START) && (mask <= PCH_TX_OBJ_END)) {
 465                 /*
 466                  * Setting CMASK for clearing interrupts for frame transmission.
 467                  */
 468                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL | PCH_CMASK_ARB,
 469                           &priv->regs->ifregs[1].cmask);
 470
 471                 /* Resetting the ID registers. */
 472                 pch_can_bit_set(&priv->regs->ifregs[1].id2,
 473                                PCH_ID2_DIR | (0x7ff << 2));
 474                 iowrite32(0x0, &priv->regs->ifregs[1].id1);
 475
 476                 /* Claring NewDat, TxRqst & IntPnd */
 477                 pch_can_bit_clear(&priv->regs->ifregs[1].mcont,
 478                                   PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_INTPND |
 479                                   PCH_IF_MCONT_TXRQXT);
 480                 pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, mask);
 481         }
 482 }
 483
 484 static void pch_can_reset(struct pch_can_priv *priv)
 485 {
 486         /* write to sw reset register */
 487         iowrite32(1, &priv->regs->srst);
 488         iowrite32(0, &priv->regs->srst);
 489 }
 490
 491 static void pch_can_error(struct net_device *ndev, u32 status)
 492 {
 493         struct sk_buff *skb;
 494         struct pch_can_priv *priv = netdev_priv(ndev);
 495         struct can_frame *cf;
 496         u32 errc, lec;
 497         struct net_device_stats *stats = &(priv->ndev->stats);
 498         enum can_state state = priv->can.state;
 499
 500         skb = alloc_can_err_skb(ndev, &cf);
 501         if (!skb)
 502                 return;
 503
 504         if (status & PCH_BUS_OFF) {
 505                 pch_can_set_tx_all(priv, 0);
 506                 pch_can_set_rx_all(priv, 0);
 507                 state = CAN_STATE_BUS_OFF;
 508                 cf->can_id |= CAN_ERR_BUSOFF;
 509                 can_bus_off(ndev);
 510         }
 511
 512         errc = ioread32(&priv->regs->errc);
 513         /* Warning interrupt. */
 514         if (status & PCH_EWARN) {
 515                 state = CAN_STATE_ERROR_WARNING;
 516                 priv->can.can_stats.error_warning++;
 517                 cf->can_id |= CAN_ERR_CRTL;
 518                 if (((errc & PCH_REC) >> 8) > 96)
 519                         cf->data[1] |= CAN_ERR_CRTL_RX_WARNING;
 520                 if ((errc & PCH_TEC) > 96)
 521                         cf->data[1] |= CAN_ERR_CRTL_TX_WARNING;
 522                 netdev_dbg(ndev,
 523                         "%s -> Error Counter is more than 96.\n", __func__);
 524         }
 525         /* Error passive interrupt. */
 526         if (status & PCH_EPASSIV) {
 527                 priv->can.can_stats.error_passive++;
 528                 state = CAN_STATE_ERROR_PASSIVE;
 529                 cf->can_id |= CAN_ERR_CRTL;
 530                 if (((errc & PCH_REC) >> 8) > 127)
 531                         cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
 532                 if ((errc & PCH_TEC) > 127)
 533                         cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
 534                 netdev_dbg(ndev,
 535                         "%s -> CAN controller is ERROR PASSIVE .\n", __func__);
 536         }
 537
 538         lec = status & PCH_LEC_ALL;
 539         switch (lec) {
 540         case PCH_STUF_ERR:
 541                 cf->data[2] |= CAN_ERR_PROT_STUFF;
 542                 priv->can.can_stats.bus_error++;
 543                 stats->rx_errors++;
 544                 break;
 545         case PCH_FORM_ERR:
 546                 cf->data[2] |= CAN_ERR_PROT_FORM;
 547                 priv->can.can_stats.bus_error++;
 548                 stats->rx_errors++;
 549                 break;
 550         case PCH_ACK_ERR:
 551                 cf->can_id |= CAN_ERR_ACK;
 552                 priv->can.can_stats.bus_error++;
 553                 stats->rx_errors++;
 554                 break;
 555         case PCH_BIT1_ERR:
 556         case PCH_BIT0_ERR:
 557                 cf->data[2] |= CAN_ERR_PROT_BIT;
 558                 priv->can.can_stats.bus_error++;
 559                 stats->rx_errors++;
 560                 break;
 561         case PCH_CRC_ERR:
 562                 cf->data[2] |= CAN_ERR_PROT_LOC_CRC_SEQ |
 563                                CAN_ERR_PROT_LOC_CRC_DEL;
 564                 priv->can.can_stats.bus_error++;
 565                 stats->rx_errors++;
 566                 break;
 567         case PCH_LEC_ALL: /* Written by CPU. No error status */
 568                 break;
 569         }
 570
 571         priv->can.state = state;
 572         netif_rx(skb);
 573
 574         stats->rx_packets++;
 575         stats->rx_bytes += cf->can_dlc;
 576 }
 577
 578 static irqreturn_t pch_can_interrupt(int irq, void *dev_id)
 579 {
 580         struct net_device *ndev = (struct net_device *)dev_id;
 581         struct pch_can_priv *priv = netdev_priv(ndev);
 582
 583         pch_can_set_int_enables(priv, PCH_CAN_NONE);
 584         napi_schedule(&priv->napi);
 585
 586         return IRQ_HANDLED;
 587 }
 588
 589 static void pch_fifo_thresh(struct pch_can_priv *priv, int obj_id)
 590 {
 591         if (obj_id < PCH_FIFO_THRESH) {
 592                 iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL |
 593                           PCH_CMASK_ARB, &priv->regs->ifregs[0].cmask);
 594
 595                 /* Clearing the Dir bit. */
 596                 pch_can_bit_clear(&priv->regs->ifregs[0].id2, PCH_ID2_DIR);
 597
 598                 /* Clearing NewDat & IntPnd */
 599                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
 600                                   PCH_IF_MCONT_INTPND);
 601                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
 602         } else if (obj_id > PCH_FIFO_THRESH) {
 603                 pch_can_int_clr(priv, obj_id);
 604         } else if (obj_id == PCH_FIFO_THRESH) {
 605                 int cnt;
 606                 for (cnt = 0; cnt < PCH_FIFO_THRESH; cnt++)
 607                         pch_can_int_clr(priv, cnt + 1);
 608         }
 609 }
 610
 611 static void pch_can_rx_msg_lost(struct net_device *ndev, int obj_id)
 612 {
 613         struct pch_can_priv *priv = netdev_priv(ndev);
 614         struct net_device_stats *stats = &(priv->ndev->stats);
 615         struct sk_buff *skb;
 616         struct can_frame *cf;
 617
 618         netdev_dbg(priv->ndev, "Msg Obj is overwritten.\n");
 619         pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
 620                           PCH_IF_MCONT_MSGLOST);
 621         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
 622                   &priv->regs->ifregs[0].cmask);
 623         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_id);
 624
 625         skb = alloc_can_err_skb(ndev, &cf);
 626         if (!skb)
 627                 return;
 628
 629         cf->can_id |= CAN_ERR_CRTL;
 630         cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
 631         stats->rx_over_errors++;
 632         stats->rx_errors++;
 633
 634         netif_receive_skb(skb);
 635 }
 636
 637 static int pch_can_rx_normal(struct net_device *ndev, u32 obj_num, int quota)
 638 {
 639         u32 reg;
 640         canid_t id;
 641         int rcv_pkts = 0;
 642         struct sk_buff *skb;
 643         struct can_frame *cf;
 644         struct pch_can_priv *priv = netdev_priv(ndev);
 645         struct net_device_stats *stats = &(priv->ndev->stats);
 646         int i;
 647         u32 id2;
 648         u16 data_reg;
 649
 650         do {
 651                 /* Reading the messsage object from the Message RAM */
 652                 iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
 653                 pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, obj_num);
 654
 655                 /* Reading the MCONT register. */
 656                 reg = ioread32(&priv->regs->ifregs[0].mcont);
 657
 658                 if (reg & PCH_IF_MCONT_EOB)
 659                         break;
 660
 661                 /* If MsgLost bit set. */
 662                 if (reg & PCH_IF_MCONT_MSGLOST) {
 663                         pch_can_rx_msg_lost(ndev, obj_num);
 664                         rcv_pkts++;
 665                         quota--;
 666                         obj_num++;
 667                         continue;
 668                 } else if (!(reg & PCH_IF_MCONT_NEWDAT)) {
 669                         obj_num++;
 670                         continue;
 671                 }
 672
 673                 skb = alloc_can_skb(priv->ndev, &cf);
 674                 if (!skb)
 675                         return -ENOMEM;
 676
 677                 /* Get Received data */
 678                 id2 = ioread32(&priv->regs->ifregs[0].id2);
 679                 if (id2 & PCH_ID2_XTD) {
 680                         id = (ioread32(&priv->regs->ifregs[0].id1) & 0xffff);
 681                         id |= (((id2) & 0x1fff) << 16);
 682                         cf->can_id = id | CAN_EFF_FLAG;
 683                 } else {
 684                         id = (id2 >> 2) & CAN_SFF_MASK;
 685                         cf->can_id = id;
 686                 }
 687
 688                 if (id2 & PCH_ID2_DIR)
 689                         cf->can_id |= CAN_RTR_FLAG;
 690
 691                 cf->can_dlc = get_can_dlc((ioread32(&priv->regs->
 692                                                     ifregs[0].mcont)) & 0xF);
 693
 694                 for (i = 0; i < cf->can_dlc; i += 2) {
 695                         data_reg = ioread16(&priv->regs->ifregs[0].data[i / 2]);
 696                         cf->data[i] = data_reg;
 697                         cf->data[i + 1] = data_reg >> 8;
 698                 }
 699
 700                 netif_receive_skb(skb);
 701                 rcv_pkts++;
 702                 stats->rx_packets++;
 703                 quota--;
 704                 stats->rx_bytes += cf->can_dlc;
 705
 706                 pch_fifo_thresh(priv, obj_num);
 707                 obj_num++;
 708         } while (quota > 0);
 709
 710         return rcv_pkts;
 711 }
 712
 713 static void pch_can_tx_complete(struct net_device *ndev, u32 int_stat)
 714 {
 715         struct pch_can_priv *priv = netdev_priv(ndev);
 716         struct net_device_stats *stats = &(priv->ndev->stats);
 717         u32 dlc;
 718
 719         can_get_echo_skb(ndev, int_stat - PCH_RX_OBJ_END - 1);
 720         iowrite32(PCH_CMASK_RX_TX_GET | PCH_CMASK_CLRINTPND,
 721                   &priv->regs->ifregs[1].cmask);
 722         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, int_stat);
 723         dlc = get_can_dlc(ioread32(&priv->regs->ifregs[1].mcont) &
 724                           PCH_IF_MCONT_DLC);
 725         stats->tx_bytes += dlc;
 726         stats->tx_packets++;
 727         if (int_stat == PCH_TX_OBJ_END)
 728                 netif_wake_queue(ndev);
 729 }
 730
 731 static int pch_can_poll(struct napi_struct *napi, int quota)
 732 {
 733         struct net_device *ndev = napi->dev;
 734         struct pch_can_priv *priv = netdev_priv(ndev);
 735         u32 int_stat;
 736         int rcv_pkts = 0;
 737         u32 reg_stat;
 738
 739         int_stat = pch_can_int_pending(priv);
 740         if (!int_stat)
 741                 goto end;
 742
 743         if (int_stat == PCH_STATUS_INT) {
 744                 reg_stat = ioread32(&priv->regs->stat);
 745                 if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) {
 746                         if (reg_stat & PCH_BUS_OFF ||
 747                            (reg_stat & PCH_LEC_ALL) != PCH_LEC_ALL) {
 748                                 pch_can_error(ndev, reg_stat);
 749                                 quota--;
 750                         }
 751                 }
 752
 753                 if (reg_stat & PCH_TX_OK)
 754                         pch_can_bit_clear(&priv->regs->stat, PCH_TX_OK);
 755
 756                 if (reg_stat & PCH_RX_OK)
 757                         pch_can_bit_clear(&priv->regs->stat, PCH_RX_OK);
 758
 759                 int_stat = pch_can_int_pending(priv);
 760         }
 761
 762         if (quota == 0)
 763                 goto end;
 764
 765         if ((int_stat >= PCH_RX_OBJ_START) && (int_stat <= PCH_RX_OBJ_END)) {
 766                 rcv_pkts += pch_can_rx_normal(ndev, int_stat, quota);
 767                 quota -= rcv_pkts;
 768                 if (quota < 0)
 769                         goto end;
 770         } else if ((int_stat >= PCH_TX_OBJ_START) &&
 771                    (int_stat <= PCH_TX_OBJ_END)) {
 772                 /* Handle transmission interrupt */
 773                 pch_can_tx_complete(ndev, int_stat);
 774         }
 775
 776 end:
 777         napi_complete(napi);
 778         pch_can_set_int_enables(priv, PCH_CAN_ALL);
 779
 780         return rcv_pkts;
 781 }
 782
 783 static int pch_set_bittiming(struct net_device *ndev)
 784 {
 785         struct pch_can_priv *priv = netdev_priv(ndev);
 786         const struct can_bittiming *bt = &priv->can.bittiming;
 787         u32 canbit;
 788         u32 bepe;
 789
 790         /* Setting the CCE bit for accessing the Can Timing register. */
 791         pch_can_bit_set(&priv->regs->cont, PCH_CTRL_CCE);
 792
 793         canbit = (bt->brp - 1) & PCH_MSK_BITT_BRP;
 794         canbit |= (bt->sjw - 1) << PCH_BIT_SJW_SHIFT;
 795         canbit |= (bt->phase_seg1 + bt->prop_seg - 1) << PCH_BIT_TSEG1_SHIFT;
 796         canbit |= (bt->phase_seg2 - 1) << PCH_BIT_TSEG2_SHIFT;
 797         bepe = ((bt->brp - 1) & PCH_MSK_BRPE_BRPE) >> PCH_BIT_BRPE_BRPE_SHIFT;
 798         iowrite32(canbit, &priv->regs->bitt);
 799         iowrite32(bepe, &priv->regs->brpe);
 800         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_CCE);
 801
 802         return 0;
 803 }
 804
 805 static void pch_can_start(struct net_device *ndev)
 806 {
 807         struct pch_can_priv *priv = netdev_priv(ndev);
 808
 809         if (priv->can.state != CAN_STATE_STOPPED)
 810                 pch_can_reset(priv);
 811
 812         pch_set_bittiming(ndev);
 813         pch_can_set_optmode(priv);
 814
 815         pch_can_set_tx_all(priv, 1);
 816         pch_can_set_rx_all(priv, 1);
 817
 818         /* Setting the CAN to run mode. */
 819         pch_can_set_run_mode(priv, PCH_CAN_RUN);
 820
 821         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 822
 823         return;
 824 }
 825
 826 static int pch_can_do_set_mode(struct net_device *ndev, enum can_mode mode)
 827 {
 828         int ret = 0;
 829
 830         switch (mode) {
 831         case CAN_MODE_START:
 832                 pch_can_start(ndev);
 833                 netif_wake_queue(ndev);
 834                 break;
 835         default:
 836                 ret = -EOPNOTSUPP;
 837                 break;
 838         }
 839
 840         return ret;
 841 }
 842
 843 static int pch_can_open(struct net_device *ndev)
 844 {
 845         struct pch_can_priv *priv = netdev_priv(ndev);
 846         int retval;
 847
 848         /* Regstering the interrupt. */
 849         retval = request_irq(priv->dev->irq, pch_can_interrupt, IRQF_SHARED,
 850                              ndev->name, ndev);
 851         if (retval) {
 852                 netdev_err(ndev, "request_irq failed.\n");
 853                 goto req_irq_err;
 854         }
 855
 856         /* Open common can device */
 857         retval = open_candev(ndev);
 858         if (retval) {
 859                 netdev_err(ndev, "open_candev() failed %d\n", retval);
 860                 goto err_open_candev;
 861         }
 862
 863         pch_can_init(priv);
 864         pch_can_start(ndev);
 865         napi_enable(&priv->napi);
 866         netif_start_queue(ndev);
 867
 868         return 0;
 869
 870 err_open_candev:
 871         free_irq(priv->dev->irq, ndev);
 872 req_irq_err:
 873         pch_can_release(priv);
 874
 875         return retval;
 876 }
 877
 878 static int pch_close(struct net_device *ndev)
 879 {
 880         struct pch_can_priv *priv = netdev_priv(ndev);
 881
 882         netif_stop_queue(ndev);
 883         napi_disable(&priv->napi);
 884         pch_can_release(priv);
 885         free_irq(priv->dev->irq, ndev);
 886         close_candev(ndev);
 887         priv->can.state = CAN_STATE_STOPPED;
 888         return 0;
 889 }
 890
 891 static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev)
 892 {
 893         struct pch_can_priv *priv = netdev_priv(ndev);
 894         struct can_frame *cf = (struct can_frame *)skb->data;
 895         int tx_obj_no;
 896         int i;
 897         u32 id2;
 898
 899         if (can_dropped_invalid_skb(ndev, skb))
 900                 return NETDEV_TX_OK;
 901
 902         if (priv->tx_obj == PCH_TX_OBJ_END) {
 903                 if (ioread32(&priv->regs->treq2) & PCH_TREQ2_TX_MASK)
 904                         netif_stop_queue(ndev);
 905
 906                 tx_obj_no = priv->tx_obj;
 907                 priv->tx_obj = PCH_TX_OBJ_START;
 908         } else {
 909                 tx_obj_no = priv->tx_obj;
 910                 priv->tx_obj++;
 911         }
 912
 913         /* Setting the CMASK register. */
 914         pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL);
 915
 916         /* If ID extended is set. */
 917         if (cf->can_id & CAN_EFF_FLAG) {
 918                 iowrite32(cf->can_id & 0xffff, &priv->regs->ifregs[1].id1);
 919                 id2 = ((cf->can_id >> 16) & 0x1fff) | PCH_ID2_XTD;
 920         } else {
 921                 iowrite32(0, &priv->regs->ifregs[1].id1);
 922                 id2 = (cf->can_id & CAN_SFF_MASK) << 2;
 923         }
 924
 925         id2 |= PCH_ID_MSGVAL;
 926
 927         /* If remote frame has to be transmitted.. */
 928         if (cf->can_id & CAN_RTR_FLAG)
 929                 id2 &= ~PCH_ID2_DIR;
 930         else
 931                 id2 |= PCH_ID2_DIR;
 932
 933         iowrite32(id2, &priv->regs->ifregs[1].id2);
 934
 935         /* Copy data to register */
 936         for (i = 0; i < cf->can_dlc; i += 2) {
 937                 iowrite16(cf->data[i] | (cf->data[i + 1] << 8),
 938                           &priv->regs->ifregs[1].data[i / 2]);
 939         }
 940
 941         can_put_echo_skb(skb, ndev, tx_obj_no - PCH_RX_OBJ_END - 1);
 942
 943         /* Set the size of the data. Update if2_mcont */
 944         iowrite32(cf->can_dlc | PCH_IF_MCONT_NEWDAT | PCH_IF_MCONT_TXRQXT |
 945                   PCH_IF_MCONT_TXIE, &priv->regs->ifregs[1].mcont);
 946
 947         pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no);
 948
 949         return NETDEV_TX_OK;
 950 }
 951
 952 static const struct net_device_ops pch_can_netdev_ops = {
 953         .ndo_open               = pch_can_open,
 954         .ndo_stop               = pch_close,
 955         .ndo_start_xmit         = pch_xmit,
 956 };
 957
 958 static void __devexit pch_can_remove(struct pci_dev *pdev)
 959 {
 960         struct net_device *ndev = pci_get_drvdata(pdev);
 961         struct pch_can_priv *priv = netdev_priv(ndev);
 962
 963         unregister_candev(priv->ndev);
 964         pci_iounmap(pdev, priv->regs);
 965         if (priv->use_msi)
 966                 pci_disable_msi(priv->dev);
 967         pci_release_regions(pdev);
 968         pci_disable_device(pdev);
 969         pci_set_drvdata(pdev, NULL);
 970         pch_can_reset(priv);
 971         free_candev(priv->ndev);
 972 }
 973
 974 #ifdef CONFIG_PM
 975 static void pch_can_set_int_custom(struct pch_can_priv *priv)
 976 {
 977         /* Clearing the IE, SIE and EIE bits of Can control register. */
 978         pch_can_bit_clear(&priv->regs->cont, PCH_CTRL_IE_SIE_EIE);
 979
 980         /* Appropriately setting them. */
 981         pch_can_bit_set(&priv->regs->cont,
 982                         ((priv->int_enables & PCH_MSK_CTRL_IE_SIE_EIE) << 1));
 983 }
 984
 985 /* This function retrieves interrupt enabled for the CAN device. */
 986 static u32 pch_can_get_int_enables(struct pch_can_priv *priv)
 987 {
 988         /* Obtaining the status of IE, SIE and EIE interrupt bits. */
 989         return (ioread32(&priv->regs->cont) & PCH_CTRL_IE_SIE_EIE) >> 1;
 990 }
 991
 992 static u32 pch_can_get_rxtx_ir(struct pch_can_priv *priv, u32 buff_num,
 993                                enum pch_ifreg dir)
 994 {
 995         u32 ie, enable;
 996
 997         if (dir)
 998                 ie = PCH_IF_MCONT_RXIE;
 999         else
1000                 ie = PCH_IF_MCONT_TXIE;
1001
1002         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[dir].cmask);
1003         pch_can_rw_msg_obj(&priv->regs->ifregs[dir].creq, buff_num);
1004
1005         if (((ioread32(&priv->regs->ifregs[dir].id2)) & PCH_ID_MSGVAL) &&
1006                         ((ioread32(&priv->regs->ifregs[dir].mcont)) & ie))
1007                 enable = 1;
1008         else
1009                 enable = 0;
1010
1011         return enable;
1012 }
1013
1014 static void pch_can_set_rx_buffer_link(struct pch_can_priv *priv,
1015                                        u32 buffer_num, int set)
1016 {
1017         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1018         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1019         iowrite32(PCH_CMASK_RDWR | PCH_CMASK_CTRL,
1020                   &priv->regs->ifregs[0].cmask);
1021         if (set)
1022                 pch_can_bit_clear(&priv->regs->ifregs[0].mcont,
1023                                   PCH_IF_MCONT_EOB);
1024         else
1025                 pch_can_bit_set(&priv->regs->ifregs[0].mcont, PCH_IF_MCONT_EOB);
1026
1027         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1028 }
1029
1030 static u32 pch_can_get_rx_buffer_link(struct pch_can_priv *priv, u32 buffer_num)
1031 {
1032         u32 link;
1033
1034         iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[0].cmask);
1035         pch_can_rw_msg_obj(&priv->regs->ifregs[0].creq, buffer_num);
1036
1037         if (ioread32(&priv->regs->ifregs[0].mcont) & PCH_IF_MCONT_EOB)
1038                 link = 0;
1039         else
1040                 link = 1;
1041         return link;
1042 }
1043
1044 static int pch_can_get_buffer_status(struct pch_can_priv *priv)
1045 {
1046         return (ioread32(&priv->regs->treq1) & 0xffff) |
1047                (ioread32(&priv->regs->treq2) << 16);
1048 }
1049
1050 static int pch_can_suspend(struct pci_dev *pdev, pm_message_t state)
1051 {
1052         int i;
1053         int retval;
1054         u32 buf_stat;   /* Variable for reading the transmit buffer status. */
1055         int counter = PCH_COUNTER_LIMIT;
1056
1057         struct net_device *dev = pci_get_drvdata(pdev);
1058         struct pch_can_priv *priv = netdev_priv(dev);
1059
1060         /* Stop the CAN controller */
1061         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1062
1063         /* Indicate that we are aboutto/in suspend */
1064         priv->can.state = CAN_STATE_STOPPED;
1065
1066         /* Waiting for all transmission to complete. */
1067         while (counter) {
1068                 buf_stat = pch_can_get_buffer_status(priv);
1069                 if (!buf_stat)
1070                         break;
1071                 counter--;
1072                 udelay(1);
1073         }
1074         if (!counter)
1075                 dev_err(&pdev->dev, "%s -> Transmission time out.\n", __func__);
1076
1077         /* Save interrupt configuration and then disable them */
1078         priv->int_enables = pch_can_get_int_enables(priv);
1079         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1080
1081         /* Save Tx buffer enable state */
1082         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1083                 priv->tx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_TX_IFREG);
1084
1085         /* Disable all Transmit buffers */
1086         pch_can_set_tx_all(priv, 0);
1087
1088         /* Save Rx buffer enable state */
1089         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1090                 priv->rx_enable[i] = pch_can_get_rxtx_ir(priv, i, PCH_RX_IFREG);
1091                 priv->rx_link[i] = pch_can_get_rx_buffer_link(priv, i);
1092         }
1093
1094         /* Disable all Receive buffers */
1095         pch_can_set_rx_all(priv, 0);
1096         retval = pci_save_state(pdev);
1097         if (retval) {
1098                 dev_err(&pdev->dev, "pci_save_state failed.\n");
1099         } else {
1100                 pci_enable_wake(pdev, PCI_D3hot, 0);
1101                 pci_disable_device(pdev);
1102                 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1103         }
1104
1105         return retval;
1106 }
1107
1108 static int pch_can_resume(struct pci_dev *pdev)
1109 {
1110         int i;
1111         int retval;
1112         struct net_device *dev = pci_get_drvdata(pdev);
1113         struct pch_can_priv *priv = netdev_priv(dev);
1114
1115         pci_set_power_state(pdev, PCI_D0);
1116         pci_restore_state(pdev);
1117         retval = pci_enable_device(pdev);
1118         if (retval) {
1119                 dev_err(&pdev->dev, "pci_enable_device failed.\n");
1120                 return retval;
1121         }
1122
1123         pci_enable_wake(pdev, PCI_D3hot, 0);
1124
1125         priv->can.state = CAN_STATE_ERROR_ACTIVE;
1126
1127         /* Disabling all interrupts. */
1128         pch_can_set_int_enables(priv, PCH_CAN_DISABLE);
1129
1130         /* Setting the CAN device in Stop Mode. */
1131         pch_can_set_run_mode(priv, PCH_CAN_STOP);
1132
1133         /* Configuring the transmit and receive buffers. */
1134         pch_can_config_rx_tx_buffers(priv);
1135
1136         /* Restore the CAN state */
1137         pch_set_bittiming(dev);
1138
1139         /* Listen/Active */
1140         pch_can_set_optmode(priv);
1141
1142         /* Enabling the transmit buffer. */
1143         for (i = PCH_TX_OBJ_START; i <= PCH_TX_OBJ_END; i++)
1144                 pch_can_set_rxtx(priv, i, priv->tx_enable[i], PCH_TX_IFREG);
1145
1146         /* Configuring the receive buffer and enabling them. */
1147         for (i = PCH_RX_OBJ_START; i <= PCH_RX_OBJ_END; i++) {
1148                 /* Restore buffer link */
1149                 pch_can_set_rx_buffer_link(priv, i, priv->rx_link[i]);
1150
1151                 /* Restore buffer enables */
1152                 pch_can_set_rxtx(priv, i, priv->rx_enable[i], PCH_RX_IFREG);
1153         }
1154
1155         /* Enable CAN Interrupts */
1156         pch_can_set_int_custom(priv);
1157
1158         /* Restore Run Mode */
1159         pch_can_set_run_mode(priv, PCH_CAN_RUN);
1160
1161         return retval;
1162 }
1163 #else
1164 #define pch_can_suspend NULL
1165 #define pch_can_resume NULL
1166 #endif
1167
1168 static int pch_can_get_berr_counter(const struct net_device *dev,
1169                                     struct can_berr_counter *bec)
1170 {
1171         struct pch_can_priv *priv = netdev_priv(dev);
1172         u32 errc = ioread32(&priv->regs->errc);
1173
1174         bec->txerr = errc & PCH_TEC;
1175         bec->rxerr = (errc & PCH_REC) >> 8;
1176
1177         return 0;
1178 }
1179
1180 static int __devinit pch_can_probe(struct pci_dev *pdev,
1181                                    const struct pci_device_id *id)
1182 {
1183         struct net_device *ndev;
1184         struct pch_can_priv *priv;
1185         int rc;
1186         void __iomem *addr;
1187
1188         rc = pci_enable_device(pdev);
1189         if (rc) {
1190                 dev_err(&pdev->dev, "Failed pci_enable_device %d\n", rc);
1191                 goto probe_exit_endev;
1192         }
1193
1194         rc = pci_request_regions(pdev, KBUILD_MODNAME);
1195         if (rc) {
1196                 dev_err(&pdev->dev, "Failed pci_request_regions %d\n", rc);
1197                 goto probe_exit_pcireq;
1198         }
1199
1200         addr = pci_iomap(pdev, 1, 0);
1201         if (!addr) {
1202                 rc = -EIO;
1203                 dev_err(&pdev->dev, "Failed pci_iomap\n");
1204                 goto probe_exit_ipmap;
1205         }
1206
1207         ndev = alloc_candev(sizeof(struct pch_can_priv), PCH_TX_OBJ_END);
1208         if (!ndev) {
1209                 rc = -ENOMEM;
1210                 dev_err(&pdev->dev, "Failed alloc_candev\n");
1211                 goto probe_exit_alloc_candev;
1212         }
1213
1214         priv = netdev_priv(ndev);
1215         priv->ndev = ndev;
1216         priv->regs = addr;
1217         priv->dev = pdev;
1218         priv->can.bittiming_const = &pch_can_bittiming_const;
1219         priv->can.do_set_mode = pch_can_do_set_mode;
1220         priv->can.do_get_berr_counter = pch_can_get_berr_counter;
1221         priv->can.ctrlmode_supported = CAN_CTRLMODE_LISTENONLY |
1222                                        CAN_CTRLMODE_LOOPBACK;
1223         priv->tx_obj = PCH_TX_OBJ_START; /* Point head of Tx Obj */
1224
1225         ndev->irq = pdev->irq;
1226         ndev->flags |= IFF_ECHO;
1227
1228         pci_set_drvdata(pdev, ndev);
1229         SET_NETDEV_DEV(ndev, &pdev->dev);
1230         ndev->netdev_ops = &pch_can_netdev_ops;
1231         priv->can.clock.freq = PCH_CAN_CLK; /* Hz */
1232
1233         netif_napi_add(ndev, &priv->napi, pch_can_poll, PCH_RX_OBJ_END);
1234
1235         rc = pci_enable_msi(priv->dev);
1236         if (rc) {
1237                 netdev_err(ndev, "PCH CAN opened without MSI\n");
1238                 priv->use_msi = 0;
1239         } else {
1240                 netdev_err(ndev, "PCH CAN opened with MSI\n");
1241                 priv->use_msi = 1;
1242         }
1243
1244         rc = register_candev(ndev);
1245         if (rc) {
1246                 dev_err(&pdev->dev, "Failed register_candev %d\n", rc);
1247                 goto probe_exit_reg_candev;
1248         }
1249
1250         return 0;
1251
1252 probe_exit_reg_candev:
1253         if (priv->use_msi)
1254                 pci_disable_msi(priv->dev);
1255         free_candev(ndev);
1256 probe_exit_alloc_candev:
1257         pci_iounmap(pdev, addr);
1258 probe_exit_ipmap:
1259         pci_release_regions(pdev);
1260 probe_exit_pcireq:
1261         pci_disable_device(pdev);
1262 probe_exit_endev:
1263         return rc;
1264 }
1265
1266 static struct pci_driver pch_can_pci_driver = {
1267         .name = "pch_can",
1268         .id_table = pch_pci_tbl,
1269         .probe = pch_can_probe,
1270         .remove = __devexit_p(pch_can_remove),
1271         .suspend = pch_can_suspend,
1272         .resume = pch_can_resume,
1273 };
1274
1275 static int __init pch_can_pci_init(void)
1276 {
1277         return pci_register_driver(&pch_can_pci_driver);
1278 }
1279 module_init(pch_can_pci_init);
1280
1281 static void __exit pch_can_pci_exit(void)
1282 {
1283         pci_unregister_driver(&pch_can_pci_driver);
1284 }
1285 module_exit(pch_can_pci_exit);
1286
1287 MODULE_DESCRIPTION("Intel EG20T PCH CAN(Controller Area Network) Driver");
1288 MODULE_LICENSE("GPL v2");
1289 MODULE_VERSION("0.94");