2 * net/dsa/mv88e6131.c - Marvell 88e6095/6095f/6131 switch chip support
3 * Copyright (c) 2008-2009 Marvell Semiconductor
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
11 #include <linux/delay.h>
12 #include <linux/jiffies.h>
13 #include <linux/list.h>
14 #include <linux/module.h>
15 #include <linux/netdevice.h>
16 #include <linux/phy.h>
18 #include "mv88e6xxx.h"
20 /* Switch product IDs */
21 #define ID_6085 0x04a0
22 #define ID_6095 0x0950
23 #define ID_6131 0x1060
24 #define ID_6131_B2 0x1066
26 static char *mv88e6131_probe(struct device *host_dev, int sw_addr)
28 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
34 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
36 int ret_masked = ret & 0xfff0;
38 if (ret_masked == ID_6085)
39 return "Marvell 88E6085";
40 if (ret_masked == ID_6095)
41 return "Marvell 88E6095/88E6095F";
42 if (ret == ID_6131_B2)
43 return "Marvell 88E6131 (B2)";
44 if (ret_masked == ID_6131)
45 return "Marvell 88E6131";
51 static int mv88e6131_switch_reset(struct dsa_switch *ds)
55 unsigned long timeout;
57 /* Set all ports to the disabled state. */
58 for (i = 0; i < 11; i++) {
59 ret = REG_READ(REG_PORT(i), 0x04);
60 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
63 /* Wait for transmit queues to drain. */
64 usleep_range(2000, 4000);
66 /* Reset the switch. */
67 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
69 /* Wait up to one second for reset to complete. */
70 timeout = jiffies + 1 * HZ;
71 while (time_before(jiffies, timeout)) {
72 ret = REG_READ(REG_GLOBAL, 0x00);
73 if ((ret & 0xc800) == 0xc800)
76 usleep_range(1000, 2000);
78 if (time_after(jiffies, timeout))
84 static int mv88e6131_setup_global(struct dsa_switch *ds)
89 /* Enable the PHY polling unit, don't discard packets with
90 * excessive collisions, use a weighted fair queueing scheme
91 * to arbitrate between packet queues, set the maximum frame
92 * size to 1632, and mask all interrupt sources.
94 REG_WRITE(REG_GLOBAL, 0x04, 0x4400);
96 /* Set the default address aging time to 5 minutes, and
97 * enable address learn messages to be sent to all message
100 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
102 /* Configure the priority mapping registers. */
103 ret = mv88e6xxx_config_prio(ds);
107 /* Set the VLAN ethertype to 0x8100. */
108 REG_WRITE(REG_GLOBAL, 0x19, 0x8100);
110 /* Disable ARP mirroring, and configure the upstream port as
111 * the port to which ingress and egress monitor frames are to
114 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0);
116 /* Disable cascade port functionality unless this device
117 * is used in a cascade configuration, and set the switch's
120 if (ds->dst->pd->nr_chips > 1)
121 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f));
123 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f));
125 /* Send all frames with destination addresses matching
126 * 01:80:c2:00:00:0x to the CPU port.
128 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
130 /* Ignore removed tag data on doubly tagged packets, disable
131 * flow control messages, force flow control priority to the
132 * highest, and send all special multicast frames to the CPU
133 * port at the highest priority.
135 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
137 /* Program the DSA routing table. */
138 for (i = 0; i < 32; i++) {
142 if (ds->pd->rtable &&
143 i != ds->index && i < ds->dst->pd->nr_chips)
144 nexthop = ds->pd->rtable[i] & 0x1f;
146 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
149 /* Clear all trunk masks. */
150 for (i = 0; i < 8; i++)
151 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7ff);
153 /* Clear all trunk mappings. */
154 for (i = 0; i < 16; i++)
155 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
157 /* Force the priority of IGMP/MLD snoop frames and ARP frames
158 * to the highest setting.
160 REG_WRITE(REG_GLOBAL2, 0x0f, 0x00ff);
165 static int mv88e6131_setup_port(struct dsa_switch *ds, int p)
167 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
168 int addr = REG_PORT(p);
171 /* MAC Forcing register: don't force link, speed, duplex
172 * or flow control state to any particular values on physical
173 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
174 * (100 Mb/s on 6085) full duplex.
176 if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
177 if (ps->id == ID_6085)
178 REG_WRITE(addr, 0x01, 0x003d); /* 100 Mb/s */
180 REG_WRITE(addr, 0x01, 0x003e); /* 1000 Mb/s */
182 REG_WRITE(addr, 0x01, 0x0003);
184 /* Port Control: disable Core Tag, disable Drop-on-Lock,
185 * transmit frames unmodified, disable Header mode,
186 * enable IGMP/MLD snoop, disable DoubleTag, disable VLAN
187 * tunneling, determine priority by looking at 802.1p and
188 * IP priority fields (IP prio has precedence), and set STP
189 * state to Forwarding.
191 * If this is the upstream port for this switch, enable
192 * forwarding of unknown unicasts, and enable DSA tagging
195 * If this is the link to another switch, use DSA tagging
196 * mode, but do not enable forwarding of unknown unicasts.
199 if (p == dsa_upstream_port(ds)) {
201 /* On 6085, unknown multicast forward is controlled
202 * here rather than in Port Control 2 register.
204 if (ps->id == ID_6085)
207 if (ds->dsa_port_mask & (1 << p))
209 REG_WRITE(addr, 0x04, val);
211 /* Port Control 1: disable trunking. Also, if this is the
212 * CPU port, enable learn messages to be sent to this port.
214 REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
216 /* Port based VLAN map: give each port its own address
217 * database, allow the CPU port to talk to each of the 'real'
218 * ports, and allow each of the 'real' ports to only talk to
221 val = (p & 0xf) << 12;
222 if (dsa_is_cpu_port(ds, p))
223 val |= ds->phys_port_mask;
225 val |= 1 << dsa_upstream_port(ds);
226 REG_WRITE(addr, 0x06, val);
228 /* Default VLAN ID and priority: don't set a default VLAN
229 * ID, and set the default packet priority to zero.
231 REG_WRITE(addr, 0x07, 0x0000);
233 /* Port Control 2: don't force a good FCS, don't use
234 * VLAN-based, source address-based or destination
235 * address-based priority overrides, don't let the switch
236 * add or strip 802.1q tags, don't discard tagged or
237 * untagged frames on this port, do a destination address
238 * lookup on received packets as usual, don't send a copy
239 * of all transmitted/received frames on this port to the
240 * CPU, and configure the upstream port number.
242 * If this is the upstream port for this switch, enable
243 * forwarding of unknown multicast addresses.
245 if (ps->id == ID_6085)
246 /* on 6085, bits 3:0 are reserved, bit 6 control ARP
247 * mirroring, and multicast forward is handled in
248 * Port Control register.
250 REG_WRITE(addr, 0x08, 0x0080);
252 val = 0x0080 | dsa_upstream_port(ds);
253 if (p == dsa_upstream_port(ds))
255 REG_WRITE(addr, 0x08, val);
258 /* Rate Control: disable ingress rate limiting. */
259 REG_WRITE(addr, 0x09, 0x0000);
261 /* Rate Control 2: disable egress rate limiting. */
262 REG_WRITE(addr, 0x0a, 0x0000);
264 /* Port Association Vector: when learning source addresses
265 * of packets, add the address to the address database using
266 * a port bitmap that has only the bit for this port set and
267 * the other bits clear.
269 REG_WRITE(addr, 0x0b, 1 << p);
271 /* Tag Remap: use an identity 802.1p prio -> switch prio
274 REG_WRITE(addr, 0x18, 0x3210);
276 /* Tag Remap 2: use an identity 802.1p prio -> switch prio
279 REG_WRITE(addr, 0x19, 0x7654);
284 static int mv88e6131_setup(struct dsa_switch *ds)
286 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
290 mutex_init(&ps->smi_mutex);
291 mv88e6xxx_ppu_state_init(ds);
292 mutex_init(&ps->stats_mutex);
294 ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
296 ret = mv88e6131_switch_reset(ds);
300 /* @@@ initialise vtu and atu */
302 ret = mv88e6131_setup_global(ds);
306 for (i = 0; i < 11; i++) {
307 ret = mv88e6131_setup_port(ds, i);
315 static int mv88e6131_port_to_phy_addr(int port)
317 if (port >= 0 && port <= 11)
323 mv88e6131_phy_read(struct dsa_switch *ds, int port, int regnum)
325 int addr = mv88e6131_port_to_phy_addr(port);
326 return mv88e6xxx_phy_read_ppu(ds, addr, regnum);
330 mv88e6131_phy_write(struct dsa_switch *ds,
331 int port, int regnum, u16 val)
333 int addr = mv88e6131_port_to_phy_addr(port);
334 return mv88e6xxx_phy_write_ppu(ds, addr, regnum, val);
337 static struct mv88e6xxx_hw_stat mv88e6131_hw_stats[] = {
338 { "in_good_octets", 8, 0x00, },
339 { "in_bad_octets", 4, 0x02, },
340 { "in_unicast", 4, 0x04, },
341 { "in_broadcasts", 4, 0x06, },
342 { "in_multicasts", 4, 0x07, },
343 { "in_pause", 4, 0x16, },
344 { "in_undersize", 4, 0x18, },
345 { "in_fragments", 4, 0x19, },
346 { "in_oversize", 4, 0x1a, },
347 { "in_jabber", 4, 0x1b, },
348 { "in_rx_error", 4, 0x1c, },
349 { "in_fcs_error", 4, 0x1d, },
350 { "out_octets", 8, 0x0e, },
351 { "out_unicast", 4, 0x10, },
352 { "out_broadcasts", 4, 0x13, },
353 { "out_multicasts", 4, 0x12, },
354 { "out_pause", 4, 0x15, },
355 { "excessive", 4, 0x11, },
356 { "collisions", 4, 0x1e, },
357 { "deferred", 4, 0x05, },
358 { "single", 4, 0x14, },
359 { "multiple", 4, 0x17, },
360 { "out_fcs_error", 4, 0x03, },
361 { "late", 4, 0x1f, },
362 { "hist_64bytes", 4, 0x08, },
363 { "hist_65_127bytes", 4, 0x09, },
364 { "hist_128_255bytes", 4, 0x0a, },
365 { "hist_256_511bytes", 4, 0x0b, },
366 { "hist_512_1023bytes", 4, 0x0c, },
367 { "hist_1024_max_bytes", 4, 0x0d, },
371 mv88e6131_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
373 mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6131_hw_stats),
374 mv88e6131_hw_stats, port, data);
378 mv88e6131_get_ethtool_stats(struct dsa_switch *ds,
379 int port, uint64_t *data)
381 mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6131_hw_stats),
382 mv88e6131_hw_stats, port, data);
385 static int mv88e6131_get_sset_count(struct dsa_switch *ds)
387 return ARRAY_SIZE(mv88e6131_hw_stats);
390 struct dsa_switch_driver mv88e6131_switch_driver = {
391 .tag_protocol = DSA_TAG_PROTO_DSA,
392 .priv_size = sizeof(struct mv88e6xxx_priv_state),
393 .probe = mv88e6131_probe,
394 .setup = mv88e6131_setup,
395 .set_addr = mv88e6xxx_set_addr_direct,
396 .phy_read = mv88e6131_phy_read,
397 .phy_write = mv88e6131_phy_write,
398 .poll_link = mv88e6xxx_poll_link,
399 .get_strings = mv88e6131_get_strings,
400 .get_ethtool_stats = mv88e6131_get_ethtool_stats,
401 .get_sset_count = mv88e6131_get_sset_count,
404 MODULE_ALIAS("platform:mv88e6085");
405 MODULE_ALIAS("platform:mv88e6095");
406 MODULE_ALIAS("platform:mv88e6095f");
407 MODULE_ALIAS("platform:mv88e6131");