2 * net/dsa/mv88e6352.c - Marvell 88e6352 switch chip support
4 * Copyright (c) 2014 Guenter Roeck
6 * Derived from mv88e6123_61_65.c
7 * Copyright (c) 2008-2009 Marvell Semiconductor
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/delay.h>
16 #include <linux/jiffies.h>
17 #include <linux/list.h>
18 #include <linux/module.h>
19 #include <linux/netdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/phy.h>
23 #include "mv88e6xxx.h"
25 static int mv88e6352_wait(struct dsa_switch *ds, int reg, u16 mask)
27 unsigned long timeout = jiffies + HZ / 10;
29 while (time_before(jiffies, timeout)) {
32 ret = REG_READ(REG_GLOBAL2, reg);
39 usleep_range(1000, 2000);
44 static inline int mv88e6352_phy_wait(struct dsa_switch *ds)
46 return mv88e6352_wait(ds, 0x18, 0x8000);
49 static inline int mv88e6352_eeprom_load_wait(struct dsa_switch *ds)
51 return mv88e6352_wait(ds, 0x14, 0x0800);
54 static inline int mv88e6352_eeprom_busy_wait(struct dsa_switch *ds)
56 return mv88e6352_wait(ds, 0x14, 0x8000);
59 static int __mv88e6352_phy_read(struct dsa_switch *ds, int addr, int regnum)
63 REG_WRITE(REG_GLOBAL2, 0x18, 0x9800 | (addr << 5) | regnum);
65 ret = mv88e6352_phy_wait(ds);
69 return REG_READ(REG_GLOBAL2, 0x19);
72 static int __mv88e6352_phy_write(struct dsa_switch *ds, int addr, int regnum,
75 REG_WRITE(REG_GLOBAL2, 0x19, val);
76 REG_WRITE(REG_GLOBAL2, 0x18, 0x9400 | (addr << 5) | regnum);
78 return mv88e6352_phy_wait(ds);
81 static char *mv88e6352_probe(struct device *host_dev, int sw_addr)
83 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
89 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), 0x03);
91 if ((ret & 0xfff0) == 0x1760)
92 return "Marvell 88E6176";
94 return "Marvell 88E6352 (A0)";
96 return "Marvell 88E6352 (A1)";
97 if ((ret & 0xfff0) == 0x3520)
98 return "Marvell 88E6352";
104 static int mv88e6352_switch_reset(struct dsa_switch *ds)
106 unsigned long timeout;
110 /* Set all ports to the disabled state. */
111 for (i = 0; i < 7; i++) {
112 ret = REG_READ(REG_PORT(i), 0x04);
113 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc);
116 /* Wait for transmit queues to drain. */
117 usleep_range(2000, 4000);
119 /* Reset the switch. Keep PPU active (bit 14, undocumented).
120 * The PPU needs to be active to support indirect phy register
121 * accesses through global registers 0x18 and 0x19.
123 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
125 /* Wait up to one second for reset to complete. */
126 timeout = jiffies + 1 * HZ;
127 while (time_before(jiffies, timeout)) {
128 ret = REG_READ(REG_GLOBAL, 0x00);
129 if ((ret & 0x8800) == 0x8800)
131 usleep_range(1000, 2000);
133 if (time_after(jiffies, timeout))
139 static int mv88e6352_setup_global(struct dsa_switch *ds)
144 /* Discard packets with excessive collisions,
145 * mask all interrupt sources, enable PPU (bit 14, undocumented).
147 REG_WRITE(REG_GLOBAL, 0x04, 0x6000);
149 /* Set the default address aging time to 5 minutes, and
150 * enable address learn messages to be sent to all message
153 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148);
155 /* Configure the priority mapping registers. */
156 ret = mv88e6xxx_config_prio(ds);
160 /* Configure the upstream port, and configure the upstream
161 * port as the port to which ingress and egress monitor frames
164 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110));
166 /* Disable remote management for now, and set the switch's
169 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f);
171 /* Send all frames with destination addresses matching
172 * 01:80:c2:00:00:2x to the CPU port.
174 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff);
176 /* Send all frames with destination addresses matching
177 * 01:80:c2:00:00:0x to the CPU port.
179 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff);
181 /* Disable the loopback filter, disable flow control
182 * messages, disable flood broadcast override, disable
183 * removing of provider tags, disable ATU age violation
184 * interrupts, disable tag flow control, force flow
185 * control priority to the highest, and send all special
186 * multicast frames to the CPU at the highest priority.
188 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff);
190 /* Program the DSA routing table. */
191 for (i = 0; i < 32; i++) {
194 if (i != ds->index && i < ds->dst->pd->nr_chips)
195 nexthop = ds->pd->rtable[i] & 0x1f;
197 REG_WRITE(REG_GLOBAL2, 0x06, 0x8000 | (i << 8) | nexthop);
200 /* Clear all trunk masks. */
201 for (i = 0; i < 8; i++)
202 REG_WRITE(REG_GLOBAL2, 0x07, 0x8000 | (i << 12) | 0x7f);
204 /* Clear all trunk mappings. */
205 for (i = 0; i < 16; i++)
206 REG_WRITE(REG_GLOBAL2, 0x08, 0x8000 | (i << 11));
208 /* Disable ingress rate limiting by resetting all ingress
209 * rate limit registers to their initial state.
211 for (i = 0; i < 7; i++)
212 REG_WRITE(REG_GLOBAL2, 0x09, 0x9000 | (i << 8));
214 /* Initialise cross-chip port VLAN table to reset defaults. */
215 REG_WRITE(REG_GLOBAL2, 0x0b, 0x9000);
217 /* Clear the priority override table. */
218 for (i = 0; i < 16; i++)
219 REG_WRITE(REG_GLOBAL2, 0x0f, 0x8000 | (i << 8));
221 /* @@@ initialise AVB (22/23) watchdog (27) sdet (29) registers */
226 static int mv88e6352_setup_port(struct dsa_switch *ds, int p)
228 int addr = REG_PORT(p);
231 /* MAC Forcing register: don't force link, speed, duplex
232 * or flow control state to any particular values on physical
233 * ports, but force the CPU port and all DSA ports to 1000 Mb/s
236 if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p))
237 REG_WRITE(addr, 0x01, 0x003e);
239 REG_WRITE(addr, 0x01, 0x0003);
241 /* Do not limit the period of time that this port can be
242 * paused for by the remote end or the period of time that
243 * this port can pause the remote end.
245 REG_WRITE(addr, 0x02, 0x0000);
247 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
248 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
249 * tunneling, determine priority by looking at 802.1p and IP
250 * priority fields (IP prio has precedence), and set STP state
253 * If this is the CPU link, use DSA or EDSA tagging depending
254 * on which tagging mode was configured.
256 * If this is a link to another switch, use DSA tagging mode.
258 * If this is the upstream port for this switch, enable
259 * forwarding of unknown unicasts and multicasts.
262 if (dsa_is_cpu_port(ds, p)) {
263 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
268 if (ds->dsa_port_mask & (1 << p))
270 if (p == dsa_upstream_port(ds))
272 REG_WRITE(addr, 0x04, val);
274 /* Port Control 1: disable trunking. Also, if this is the
275 * CPU port, enable learn messages to be sent to this port.
277 REG_WRITE(addr, 0x05, dsa_is_cpu_port(ds, p) ? 0x8000 : 0x0000);
279 /* Port based VLAN map: give each port its own address
280 * database, allow the CPU port to talk to each of the 'real'
281 * ports, and allow each of the 'real' ports to only talk to
284 val = (p & 0xf) << 12;
285 if (dsa_is_cpu_port(ds, p))
286 val |= ds->phys_port_mask;
288 val |= 1 << dsa_upstream_port(ds);
289 REG_WRITE(addr, 0x06, val);
291 /* Default VLAN ID and priority: don't set a default VLAN
292 * ID, and set the default packet priority to zero.
294 REG_WRITE(addr, 0x07, 0x0000);
296 /* Port Control 2: don't force a good FCS, set the maximum
297 * frame size to 10240 bytes, don't let the switch add or
298 * strip 802.1q tags, don't discard tagged or untagged frames
299 * on this port, do a destination address lookup on all
300 * received packets as usual, disable ARP mirroring and don't
301 * send a copy of all transmitted/received frames on this port
304 REG_WRITE(addr, 0x08, 0x2080);
306 /* Egress rate control: disable egress rate control. */
307 REG_WRITE(addr, 0x09, 0x0001);
309 /* Egress rate control 2: disable egress rate control. */
310 REG_WRITE(addr, 0x0a, 0x0000);
312 /* Port Association Vector: when learning source addresses
313 * of packets, add the address to the address database using
314 * a port bitmap that has only the bit for this port set and
315 * the other bits clear.
317 REG_WRITE(addr, 0x0b, 1 << p);
319 /* Port ATU control: disable limiting the number of address
320 * database entries that this port is allowed to use.
322 REG_WRITE(addr, 0x0c, 0x0000);
324 /* Priority Override: disable DA, SA and VTU priority override. */
325 REG_WRITE(addr, 0x0d, 0x0000);
327 /* Port Ethertype: use the Ethertype DSA Ethertype value. */
328 REG_WRITE(addr, 0x0f, ETH_P_EDSA);
330 /* Tag Remap: use an identity 802.1p prio -> switch prio
333 REG_WRITE(addr, 0x18, 0x3210);
335 /* Tag Remap 2: use an identity 802.1p prio -> switch prio
338 REG_WRITE(addr, 0x19, 0x7654);
343 #ifdef CONFIG_NET_DSA_HWMON
345 static int mv88e6352_phy_page_read(struct dsa_switch *ds,
346 int port, int page, int reg)
348 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
351 mutex_lock(&ps->phy_mutex);
352 ret = __mv88e6352_phy_write(ds, port, 0x16, page);
355 ret = __mv88e6352_phy_read(ds, port, reg);
357 __mv88e6352_phy_write(ds, port, 0x16, 0x0);
358 mutex_unlock(&ps->phy_mutex);
362 static int mv88e6352_phy_page_write(struct dsa_switch *ds,
363 int port, int page, int reg, int val)
365 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
368 mutex_lock(&ps->phy_mutex);
369 ret = __mv88e6352_phy_write(ds, port, 0x16, page);
373 ret = __mv88e6352_phy_write(ds, port, reg, val);
375 __mv88e6352_phy_write(ds, port, 0x16, 0x0);
376 mutex_unlock(&ps->phy_mutex);
380 static int mv88e6352_get_temp(struct dsa_switch *ds, int *temp)
386 ret = mv88e6352_phy_page_read(ds, 0, 6, 27);
390 *temp = (ret & 0xff) - 25;
395 static int mv88e6352_get_temp_limit(struct dsa_switch *ds, int *temp)
401 ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
405 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
410 static int mv88e6352_set_temp_limit(struct dsa_switch *ds, int temp)
414 ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
417 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
418 return mv88e6352_phy_page_write(ds, 0, 6, 26,
419 (ret & 0xe0ff) | (temp << 8));
422 static int mv88e6352_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
428 ret = mv88e6352_phy_page_read(ds, 0, 6, 26);
432 *alarm = !!(ret & 0x40);
436 #endif /* CONFIG_NET_DSA_HWMON */
438 static int mv88e6352_setup(struct dsa_switch *ds)
440 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
444 mutex_init(&ps->smi_mutex);
445 mutex_init(&ps->stats_mutex);
446 mutex_init(&ps->phy_mutex);
447 mutex_init(&ps->eeprom_mutex);
449 ps->id = REG_READ(REG_PORT(0), 0x03) & 0xfff0;
451 ret = mv88e6352_switch_reset(ds);
455 /* @@@ initialise vtu and atu */
457 ret = mv88e6352_setup_global(ds);
461 for (i = 0; i < 7; i++) {
462 ret = mv88e6352_setup_port(ds, i);
470 static int mv88e6352_port_to_phy_addr(int port)
472 if (port >= 0 && port <= 4)
478 mv88e6352_phy_read(struct dsa_switch *ds, int port, int regnum)
480 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
481 int addr = mv88e6352_port_to_phy_addr(port);
487 mutex_lock(&ps->phy_mutex);
488 ret = __mv88e6352_phy_read(ds, addr, regnum);
489 mutex_unlock(&ps->phy_mutex);
495 mv88e6352_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
497 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
498 int addr = mv88e6352_port_to_phy_addr(port);
504 mutex_lock(&ps->phy_mutex);
505 ret = __mv88e6352_phy_write(ds, addr, regnum, val);
506 mutex_unlock(&ps->phy_mutex);
511 static struct mv88e6xxx_hw_stat mv88e6352_hw_stats[] = {
512 { "in_good_octets", 8, 0x00, },
513 { "in_bad_octets", 4, 0x02, },
514 { "in_unicast", 4, 0x04, },
515 { "in_broadcasts", 4, 0x06, },
516 { "in_multicasts", 4, 0x07, },
517 { "in_pause", 4, 0x16, },
518 { "in_undersize", 4, 0x18, },
519 { "in_fragments", 4, 0x19, },
520 { "in_oversize", 4, 0x1a, },
521 { "in_jabber", 4, 0x1b, },
522 { "in_rx_error", 4, 0x1c, },
523 { "in_fcs_error", 4, 0x1d, },
524 { "out_octets", 8, 0x0e, },
525 { "out_unicast", 4, 0x10, },
526 { "out_broadcasts", 4, 0x13, },
527 { "out_multicasts", 4, 0x12, },
528 { "out_pause", 4, 0x15, },
529 { "excessive", 4, 0x11, },
530 { "collisions", 4, 0x1e, },
531 { "deferred", 4, 0x05, },
532 { "single", 4, 0x14, },
533 { "multiple", 4, 0x17, },
534 { "out_fcs_error", 4, 0x03, },
535 { "late", 4, 0x1f, },
536 { "hist_64bytes", 4, 0x08, },
537 { "hist_65_127bytes", 4, 0x09, },
538 { "hist_128_255bytes", 4, 0x0a, },
539 { "hist_256_511bytes", 4, 0x0b, },
540 { "hist_512_1023bytes", 4, 0x0c, },
541 { "hist_1024_max_bytes", 4, 0x0d, },
542 { "sw_in_discards", 4, 0x110, },
543 { "sw_in_filtered", 2, 0x112, },
544 { "sw_out_filtered", 2, 0x113, },
547 static int mv88e6352_read_eeprom_word(struct dsa_switch *ds, int addr)
549 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
552 mutex_lock(&ps->eeprom_mutex);
554 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
555 0xc000 | (addr & 0xff));
559 ret = mv88e6352_eeprom_busy_wait(ds);
563 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x15);
565 mutex_unlock(&ps->eeprom_mutex);
569 static int mv88e6352_get_eeprom(struct dsa_switch *ds,
570 struct ethtool_eeprom *eeprom, u8 *data)
576 offset = eeprom->offset;
580 eeprom->magic = 0xc3ec4951;
582 ret = mv88e6352_eeprom_load_wait(ds);
589 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
593 *data++ = (word >> 8) & 0xff;
603 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
607 *data++ = word & 0xff;
608 *data++ = (word >> 8) & 0xff;
618 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
622 *data++ = word & 0xff;
632 static int mv88e6352_eeprom_is_readonly(struct dsa_switch *ds)
636 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2, 0x14);
646 static int mv88e6352_write_eeprom_word(struct dsa_switch *ds, int addr,
649 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
652 mutex_lock(&ps->eeprom_mutex);
654 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x15, data);
658 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, 0x14,
659 0xb000 | (addr & 0xff));
663 ret = mv88e6352_eeprom_busy_wait(ds);
665 mutex_unlock(&ps->eeprom_mutex);
669 static int mv88e6352_set_eeprom(struct dsa_switch *ds,
670 struct ethtool_eeprom *eeprom, u8 *data)
676 if (eeprom->magic != 0xc3ec4951)
679 ret = mv88e6352_eeprom_is_readonly(ds);
683 offset = eeprom->offset;
687 ret = mv88e6352_eeprom_load_wait(ds);
694 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
698 word = (*data++ << 8) | (word & 0xff);
700 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
713 word |= *data++ << 8;
715 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
727 word = mv88e6352_read_eeprom_word(ds, offset >> 1);
731 word = (word & 0xff00) | *data++;
733 ret = mv88e6352_write_eeprom_word(ds, offset >> 1, word);
746 mv88e6352_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
748 mv88e6xxx_get_strings(ds, ARRAY_SIZE(mv88e6352_hw_stats),
749 mv88e6352_hw_stats, port, data);
753 mv88e6352_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
755 mv88e6xxx_get_ethtool_stats(ds, ARRAY_SIZE(mv88e6352_hw_stats),
756 mv88e6352_hw_stats, port, data);
759 static int mv88e6352_get_sset_count(struct dsa_switch *ds)
761 return ARRAY_SIZE(mv88e6352_hw_stats);
764 struct dsa_switch_driver mv88e6352_switch_driver = {
765 .tag_protocol = DSA_TAG_PROTO_EDSA,
766 .priv_size = sizeof(struct mv88e6xxx_priv_state),
767 .probe = mv88e6352_probe,
768 .setup = mv88e6352_setup,
769 .set_addr = mv88e6xxx_set_addr_indirect,
770 .phy_read = mv88e6352_phy_read,
771 .phy_write = mv88e6352_phy_write,
772 .poll_link = mv88e6xxx_poll_link,
773 .get_strings = mv88e6352_get_strings,
774 .get_ethtool_stats = mv88e6352_get_ethtool_stats,
775 .get_sset_count = mv88e6352_get_sset_count,
776 #ifdef CONFIG_NET_DSA_HWMON
777 .get_temp = mv88e6352_get_temp,
778 .get_temp_limit = mv88e6352_get_temp_limit,
779 .set_temp_limit = mv88e6352_set_temp_limit,
780 .get_temp_alarm = mv88e6352_get_temp_alarm,
782 .get_eeprom = mv88e6352_get_eeprom,
783 .set_eeprom = mv88e6352_set_eeprom,
784 .get_regs_len = mv88e6xxx_get_regs_len,
785 .get_regs = mv88e6xxx_get_regs,
788 MODULE_ALIAS("platform:mv88e6352");