2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
31 #include <net/switchdev.h>
32 #include "mv88e6xxx.h"
34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(chip->dev, "Switch registers lock not held!\n");
42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
43 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
45 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
46 * is the only device connected to the SMI master. In this mode it responds to
47 * all 32 possible SMI addresses, and thus maps directly the internal devices.
49 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
50 * multiple devices to share the SMI interface. In this mode it responds to only
51 * 2 registers, used to indirectly access the internal SMI devices.
54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
55 int addr, int reg, u16 *val)
60 return chip->smi_ops->read(chip, addr, reg, val);
63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 val)
69 return chip->smi_ops->write(chip, addr, reg, val);
72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 *val)
77 ret = mdiobus_read_nested(chip->bus, addr, reg);
86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
87 int addr, int reg, u16 val)
91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
99 .read = mv88e6xxx_smi_single_chip_read,
100 .write = mv88e6xxx_smi_single_chip_write,
103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
108 for (i = 0; i < 16; i++) {
109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
113 if ((ret & SMI_CMD_BUSY) == 0)
120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
121 int addr, int reg, u16 *val)
125 /* Wait for the bus to become free. */
126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
130 /* Transmit the read command. */
131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
136 /* Wait for the read command to complete. */
137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
152 int addr, int reg, u16 val)
156 /* Wait for the bus to become free. */
157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
161 /* Transmit the data to write. */
162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
166 /* Transmit the write command. */
167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
172 /* Wait for the write command to complete. */
173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
181 .read = mv88e6xxx_smi_multi_chip_read,
182 .write = mv88e6xxx_smi_multi_chip_write,
185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
186 int addr, int reg, u16 *val)
190 assert_reg_lock(chip);
192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
203 int addr, int reg, u16 val)
207 assert_reg_lock(chip);
209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
219 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
222 unsigned long timeout = jiffies + HZ / 10;
224 while (time_before(jiffies, timeout)) {
228 err = mv88e6xxx_read(chip, addr, reg, &val);
235 usleep_range(1000, 2000);
241 /* Indirect write to single pointer-data register with an Update bit */
242 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
248 /* Wait until the previous operation is completed */
249 for (i = 0; i < 16; ++i) {
250 err = mv88e6xxx_read(chip, addr, reg, &val);
254 if (!(val & BIT(15)))
261 /* Set the Update bit to trigger a write operation */
262 val = BIT(15) | update;
264 return mv88e6xxx_write(chip, addr, reg, val);
267 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
272 err = mv88e6xxx_read(chip, addr, reg, &val);
279 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
282 return mv88e6xxx_write(chip, addr, reg, val);
285 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
286 int addr, int regnum)
289 return _mv88e6xxx_reg_read(chip, addr, regnum);
293 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
294 int addr, int regnum, u16 val)
297 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
301 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
304 unsigned long timeout;
306 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
310 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
311 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
315 timeout = jiffies + 1 * HZ;
316 while (time_before(jiffies, timeout)) {
317 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
321 usleep_range(1000, 2000);
322 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
323 GLOBAL_STATUS_PPU_POLLING)
330 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
333 unsigned long timeout;
335 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
339 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
340 ret | GLOBAL_CONTROL_PPU_ENABLE);
344 timeout = jiffies + 1 * HZ;
345 while (time_before(jiffies, timeout)) {
346 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
350 usleep_range(1000, 2000);
351 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
352 GLOBAL_STATUS_PPU_POLLING)
359 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
361 struct mv88e6xxx_chip *chip;
363 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
365 mutex_lock(&chip->reg_lock);
367 if (mutex_trylock(&chip->ppu_mutex)) {
368 if (mv88e6xxx_ppu_enable(chip) == 0)
369 chip->ppu_disabled = 0;
370 mutex_unlock(&chip->ppu_mutex);
373 mutex_unlock(&chip->reg_lock);
376 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
378 struct mv88e6xxx_chip *chip = (void *)_ps;
380 schedule_work(&chip->ppu_work);
383 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
387 mutex_lock(&chip->ppu_mutex);
389 /* If the PHY polling unit is enabled, disable it so that
390 * we can access the PHY registers. If it was already
391 * disabled, cancel the timer that is going to re-enable
394 if (!chip->ppu_disabled) {
395 ret = mv88e6xxx_ppu_disable(chip);
397 mutex_unlock(&chip->ppu_mutex);
400 chip->ppu_disabled = 1;
402 del_timer(&chip->ppu_timer);
409 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
411 /* Schedule a timer to re-enable the PHY polling unit. */
412 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
413 mutex_unlock(&chip->ppu_mutex);
416 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
418 mutex_init(&chip->ppu_mutex);
419 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
420 init_timer(&chip->ppu_timer);
421 chip->ppu_timer.data = (unsigned long)chip;
422 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
425 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
430 ret = mv88e6xxx_ppu_access_get(chip);
432 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
433 mv88e6xxx_ppu_access_put(chip);
439 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
444 ret = mv88e6xxx_ppu_access_get(chip);
446 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
447 mv88e6xxx_ppu_access_put(chip);
453 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
455 return chip->info->family == MV88E6XXX_FAMILY_6065;
458 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
460 return chip->info->family == MV88E6XXX_FAMILY_6095;
463 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
465 return chip->info->family == MV88E6XXX_FAMILY_6097;
468 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
470 return chip->info->family == MV88E6XXX_FAMILY_6165;
473 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
475 return chip->info->family == MV88E6XXX_FAMILY_6185;
478 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
480 return chip->info->family == MV88E6XXX_FAMILY_6320;
483 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
485 return chip->info->family == MV88E6XXX_FAMILY_6351;
488 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
490 return chip->info->family == MV88E6XXX_FAMILY_6352;
493 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
495 return chip->info->num_databases;
498 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
500 /* Does the device have dedicated FID registers for ATU and VTU ops? */
501 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
502 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
508 /* We expect the switch to perform auto negotiation if there is a real
509 * phy. However, in the case of a fixed link phy, we force the port
510 * settings from the fixed link settings.
512 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
513 struct phy_device *phydev)
515 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
519 if (!phy_is_pseudo_fixed_link(phydev))
522 mutex_lock(&chip->reg_lock);
524 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
528 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
529 PORT_PCS_CTRL_FORCE_LINK |
530 PORT_PCS_CTRL_DUPLEX_FULL |
531 PORT_PCS_CTRL_FORCE_DUPLEX |
532 PORT_PCS_CTRL_UNFORCED);
534 reg |= PORT_PCS_CTRL_FORCE_LINK;
536 reg |= PORT_PCS_CTRL_LINK_UP;
538 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
541 switch (phydev->speed) {
543 reg |= PORT_PCS_CTRL_1000;
546 reg |= PORT_PCS_CTRL_100;
549 reg |= PORT_PCS_CTRL_10;
552 pr_info("Unknown speed");
556 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
557 if (phydev->duplex == DUPLEX_FULL)
558 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
560 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
561 (port >= chip->info->num_ports - 2)) {
562 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
563 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
564 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
565 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
566 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
567 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
568 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
570 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
573 mutex_unlock(&chip->reg_lock);
576 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
581 for (i = 0; i < 10; i++) {
582 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
583 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
590 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
594 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
595 port = (port + 1) << 5;
597 /* Snapshot the hardware statistics counters for this port. */
598 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
599 GLOBAL_STATS_OP_CAPTURE_PORT |
600 GLOBAL_STATS_OP_HIST_RX_TX | port);
604 /* Wait for the snapshotting to complete. */
605 ret = _mv88e6xxx_stats_wait(chip);
612 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
620 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
621 GLOBAL_STATS_OP_READ_CAPTURED |
622 GLOBAL_STATS_OP_HIST_RX_TX | stat);
626 ret = _mv88e6xxx_stats_wait(chip);
630 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
636 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
643 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
644 { "in_good_octets", 8, 0x00, BANK0, },
645 { "in_bad_octets", 4, 0x02, BANK0, },
646 { "in_unicast", 4, 0x04, BANK0, },
647 { "in_broadcasts", 4, 0x06, BANK0, },
648 { "in_multicasts", 4, 0x07, BANK0, },
649 { "in_pause", 4, 0x16, BANK0, },
650 { "in_undersize", 4, 0x18, BANK0, },
651 { "in_fragments", 4, 0x19, BANK0, },
652 { "in_oversize", 4, 0x1a, BANK0, },
653 { "in_jabber", 4, 0x1b, BANK0, },
654 { "in_rx_error", 4, 0x1c, BANK0, },
655 { "in_fcs_error", 4, 0x1d, BANK0, },
656 { "out_octets", 8, 0x0e, BANK0, },
657 { "out_unicast", 4, 0x10, BANK0, },
658 { "out_broadcasts", 4, 0x13, BANK0, },
659 { "out_multicasts", 4, 0x12, BANK0, },
660 { "out_pause", 4, 0x15, BANK0, },
661 { "excessive", 4, 0x11, BANK0, },
662 { "collisions", 4, 0x1e, BANK0, },
663 { "deferred", 4, 0x05, BANK0, },
664 { "single", 4, 0x14, BANK0, },
665 { "multiple", 4, 0x17, BANK0, },
666 { "out_fcs_error", 4, 0x03, BANK0, },
667 { "late", 4, 0x1f, BANK0, },
668 { "hist_64bytes", 4, 0x08, BANK0, },
669 { "hist_65_127bytes", 4, 0x09, BANK0, },
670 { "hist_128_255bytes", 4, 0x0a, BANK0, },
671 { "hist_256_511bytes", 4, 0x0b, BANK0, },
672 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
673 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
674 { "sw_in_discards", 4, 0x10, PORT, },
675 { "sw_in_filtered", 2, 0x12, PORT, },
676 { "sw_out_filtered", 2, 0x13, PORT, },
677 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
679 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
682 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
683 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
684 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
685 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
686 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
687 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
688 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
689 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
690 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
691 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
692 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
693 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
694 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
695 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
696 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
697 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
705 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
706 struct mv88e6xxx_hw_stat *stat)
708 switch (stat->type) {
712 return mv88e6xxx_6320_family(chip);
714 return mv88e6xxx_6095_family(chip) ||
715 mv88e6xxx_6185_family(chip) ||
716 mv88e6xxx_6097_family(chip) ||
717 mv88e6xxx_6165_family(chip) ||
718 mv88e6xxx_6351_family(chip) ||
719 mv88e6xxx_6352_family(chip);
724 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
725 struct mv88e6xxx_hw_stat *s,
735 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
740 if (s->sizeof_stat == 4) {
741 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
750 _mv88e6xxx_stats_read(chip, s->reg, &low);
751 if (s->sizeof_stat == 8)
752 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
754 value = (((u64)high) << 16) | low;
758 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
761 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
762 struct mv88e6xxx_hw_stat *stat;
765 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
766 stat = &mv88e6xxx_hw_stats[i];
767 if (mv88e6xxx_has_stat(chip, stat)) {
768 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
775 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
777 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
778 struct mv88e6xxx_hw_stat *stat;
781 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
782 stat = &mv88e6xxx_hw_stats[i];
783 if (mv88e6xxx_has_stat(chip, stat))
789 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
792 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
793 struct mv88e6xxx_hw_stat *stat;
797 mutex_lock(&chip->reg_lock);
799 ret = _mv88e6xxx_stats_snapshot(chip, port);
801 mutex_unlock(&chip->reg_lock);
804 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
805 stat = &mv88e6xxx_hw_stats[i];
806 if (mv88e6xxx_has_stat(chip, stat)) {
807 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
812 mutex_unlock(&chip->reg_lock);
815 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
817 return 32 * sizeof(u16);
820 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
821 struct ethtool_regs *regs, void *_p)
823 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
829 memset(p, 0xff, 32 * sizeof(u16));
831 mutex_lock(&chip->reg_lock);
833 for (i = 0; i < 32; i++) {
836 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
841 mutex_unlock(&chip->reg_lock);
844 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
846 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
850 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
852 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
855 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
856 int addr, int regnum)
861 err = mv88e6xxx_g2_smi_phy_read(chip, addr, regnum, &val);
868 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
869 int addr, int regnum, u16 val)
871 return mv88e6xxx_g2_smi_phy_write(chip, addr, regnum, val);
874 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
875 struct ethtool_eee *e)
877 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
880 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
883 mutex_lock(&chip->reg_lock);
885 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
889 e->eee_enabled = !!(reg & 0x0200);
890 e->tx_lpi_enabled = !!(reg & 0x0100);
892 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
896 e->eee_active = !!(reg & PORT_STATUS_EEE);
900 mutex_unlock(&chip->reg_lock);
904 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
905 struct phy_device *phydev, struct ethtool_eee *e)
907 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
911 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
914 mutex_lock(&chip->reg_lock);
916 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
923 if (e->tx_lpi_enabled)
926 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
928 mutex_unlock(&chip->reg_lock);
933 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
937 if (mv88e6xxx_has_fid_reg(chip)) {
938 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
942 } else if (mv88e6xxx_num_databases(chip) == 256) {
943 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
944 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
948 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
950 ((fid << 8) & 0xf000));
954 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
958 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
962 return _mv88e6xxx_atu_wait(chip);
965 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
966 struct mv88e6xxx_atu_entry *entry)
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
982 data |= (entry->portv_trunkid << shift) & mask;
985 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
988 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
989 struct mv88e6xxx_atu_entry *entry,
995 err = _mv88e6xxx_atu_wait(chip);
999 err = _mv88e6xxx_atu_data_write(chip, entry);
1004 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1005 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1007 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1008 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1011 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1014 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1015 u16 fid, bool static_too)
1017 struct mv88e6xxx_atu_entry entry = {
1019 .state = 0, /* EntryState bits must be 0 */
1022 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1025 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1026 int from_port, int to_port, bool static_too)
1028 struct mv88e6xxx_atu_entry entry = {
1033 /* EntryState bits must be 0xF */
1034 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1036 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1037 entry.portv_trunkid = (to_port & 0x0f) << 4;
1038 entry.portv_trunkid |= from_port & 0x0f;
1040 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1043 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1044 int port, bool static_too)
1046 /* Destination port 0xF means remove the entries */
1047 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1050 static const char * const mv88e6xxx_port_state_names[] = {
1051 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1052 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1053 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1054 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1057 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1060 struct dsa_switch *ds = chip->ds;
1064 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
1070 if (oldstate != state) {
1071 /* Flush forwarding database if we're moving a port
1072 * from Learning or Forwarding state to Disabled or
1073 * Blocking or Listening state.
1075 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1076 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1077 (state == PORT_CONTROL_STATE_DISABLED ||
1078 state == PORT_CONTROL_STATE_BLOCKING)) {
1079 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1084 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1085 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1090 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1091 mv88e6xxx_port_state_names[state],
1092 mv88e6xxx_port_state_names[oldstate]);
1098 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1100 struct net_device *bridge = chip->ports[port].bridge_dev;
1101 const u16 mask = (1 << chip->info->num_ports) - 1;
1102 struct dsa_switch *ds = chip->ds;
1103 u16 output_ports = 0;
1107 /* allow CPU port or DSA link(s) to send frames to every port */
1108 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1109 output_ports = mask;
1111 for (i = 0; i < chip->info->num_ports; ++i) {
1112 /* allow sending frames to every group member */
1113 if (bridge && chip->ports[i].bridge_dev == bridge)
1114 output_ports |= BIT(i);
1116 /* allow sending frames to CPU port and DSA link(s) */
1117 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1118 output_ports |= BIT(i);
1122 /* prevent frames from going back out of the port they came in on */
1123 output_ports &= ~BIT(port);
1125 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1130 reg |= output_ports & mask;
1132 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1135 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1138 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1143 case BR_STATE_DISABLED:
1144 stp_state = PORT_CONTROL_STATE_DISABLED;
1146 case BR_STATE_BLOCKING:
1147 case BR_STATE_LISTENING:
1148 stp_state = PORT_CONTROL_STATE_BLOCKING;
1150 case BR_STATE_LEARNING:
1151 stp_state = PORT_CONTROL_STATE_LEARNING;
1153 case BR_STATE_FORWARDING:
1155 stp_state = PORT_CONTROL_STATE_FORWARDING;
1159 mutex_lock(&chip->reg_lock);
1160 err = _mv88e6xxx_port_state(chip, port, stp_state);
1161 mutex_unlock(&chip->reg_lock);
1164 netdev_err(ds->ports[port].netdev,
1165 "failed to update state to %s\n",
1166 mv88e6xxx_port_state_names[stp_state]);
1169 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1172 struct dsa_switch *ds = chip->ds;
1176 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1180 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1183 ret &= ~PORT_DEFAULT_VLAN_MASK;
1184 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1186 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1187 PORT_DEFAULT_VLAN, ret);
1191 netdev_dbg(ds->ports[port].netdev,
1192 "DefaultVID %d (was %d)\n", *new, pvid);
1201 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1202 int port, u16 *pvid)
1204 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1207 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1210 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1213 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1215 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1216 GLOBAL_VTU_OP_BUSY);
1219 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1223 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1227 return _mv88e6xxx_vtu_wait(chip);
1230 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1234 ret = _mv88e6xxx_vtu_wait(chip);
1238 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1241 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1242 struct mv88e6xxx_vtu_stu_entry *entry,
1243 unsigned int nibble_offset)
1249 for (i = 0; i < 3; ++i) {
1250 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1251 GLOBAL_VTU_DATA_0_3 + i);
1258 for (i = 0; i < chip->info->num_ports; ++i) {
1259 unsigned int shift = (i % 4) * 4 + nibble_offset;
1260 u16 reg = regs[i / 4];
1262 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1268 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1269 struct mv88e6xxx_vtu_stu_entry *entry)
1271 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1274 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1275 struct mv88e6xxx_vtu_stu_entry *entry)
1277 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1280 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1281 struct mv88e6xxx_vtu_stu_entry *entry,
1282 unsigned int nibble_offset)
1284 u16 regs[3] = { 0 };
1288 for (i = 0; i < chip->info->num_ports; ++i) {
1289 unsigned int shift = (i % 4) * 4 + nibble_offset;
1290 u8 data = entry->data[i];
1292 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1295 for (i = 0; i < 3; ++i) {
1296 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1297 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1305 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1306 struct mv88e6xxx_vtu_stu_entry *entry)
1308 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1311 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1312 struct mv88e6xxx_vtu_stu_entry *entry)
1314 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1317 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1319 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1320 vid & GLOBAL_VTU_VID_MASK);
1323 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1324 struct mv88e6xxx_vtu_stu_entry *entry)
1326 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1329 ret = _mv88e6xxx_vtu_wait(chip);
1333 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1337 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1341 next.vid = ret & GLOBAL_VTU_VID_MASK;
1342 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1345 ret = mv88e6xxx_vtu_data_read(chip, &next);
1349 if (mv88e6xxx_has_fid_reg(chip)) {
1350 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1355 next.fid = ret & GLOBAL_VTU_FID_MASK;
1356 } else if (mv88e6xxx_num_databases(chip) == 256) {
1357 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1358 * VTU DBNum[3:0] are located in VTU Operation 3:0
1360 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1365 next.fid = (ret & 0xf00) >> 4;
1366 next.fid |= ret & 0xf;
1369 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1370 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1375 next.sid = ret & GLOBAL_VTU_SID_MASK;
1383 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1384 struct switchdev_obj_port_vlan *vlan,
1385 int (*cb)(struct switchdev_obj *obj))
1387 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1388 struct mv88e6xxx_vtu_stu_entry next;
1392 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1395 mutex_lock(&chip->reg_lock);
1397 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1401 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1406 err = _mv88e6xxx_vtu_getnext(chip, &next);
1413 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1416 /* reinit and dump this VLAN obj */
1417 vlan->vid_begin = next.vid;
1418 vlan->vid_end = next.vid;
1421 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1422 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1424 if (next.vid == pvid)
1425 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1427 err = cb(&vlan->obj);
1430 } while (next.vid < GLOBAL_VTU_VID_MASK);
1433 mutex_unlock(&chip->reg_lock);
1438 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1439 struct mv88e6xxx_vtu_stu_entry *entry)
1441 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1445 ret = _mv88e6xxx_vtu_wait(chip);
1452 /* Write port member tags */
1453 ret = mv88e6xxx_vtu_data_write(chip, entry);
1457 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1458 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1459 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1465 if (mv88e6xxx_has_fid_reg(chip)) {
1466 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1467 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1471 } else if (mv88e6xxx_num_databases(chip) == 256) {
1472 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1473 * VTU DBNum[3:0] are located in VTU Operation 3:0
1475 op |= (entry->fid & 0xf0) << 8;
1476 op |= entry->fid & 0xf;
1479 reg = GLOBAL_VTU_VID_VALID;
1481 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1482 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1486 return _mv88e6xxx_vtu_cmd(chip, op);
1489 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1490 struct mv88e6xxx_vtu_stu_entry *entry)
1492 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1495 ret = _mv88e6xxx_vtu_wait(chip);
1499 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1500 sid & GLOBAL_VTU_SID_MASK);
1504 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1508 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1512 next.sid = ret & GLOBAL_VTU_SID_MASK;
1514 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1518 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1521 ret = mv88e6xxx_stu_data_read(chip, &next);
1530 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1531 struct mv88e6xxx_vtu_stu_entry *entry)
1536 ret = _mv88e6xxx_vtu_wait(chip);
1543 /* Write port states */
1544 ret = mv88e6xxx_stu_data_write(chip, entry);
1548 reg = GLOBAL_VTU_VID_VALID;
1550 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1554 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1555 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1559 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1562 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1565 struct dsa_switch *ds = chip->ds;
1570 if (mv88e6xxx_num_databases(chip) == 4096)
1572 else if (mv88e6xxx_num_databases(chip) == 256)
1577 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1578 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1582 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1585 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1586 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1588 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1594 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1595 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1599 fid |= (ret & upper_mask) << 4;
1603 ret |= (*new >> 4) & upper_mask;
1605 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1610 netdev_dbg(ds->ports[port].netdev,
1611 "FID %d (was %d)\n", *new, fid);
1620 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1623 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1626 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1629 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1632 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1634 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1635 struct mv88e6xxx_vtu_stu_entry vlan;
1638 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1640 /* Set every FID bit used by the (un)bridged ports */
1641 for (i = 0; i < chip->info->num_ports; ++i) {
1642 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1646 set_bit(*fid, fid_bitmap);
1649 /* Set every FID bit used by the VLAN entries */
1650 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1655 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1662 set_bit(vlan.fid, fid_bitmap);
1663 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1665 /* The reset value 0x000 is used to indicate that multiple address
1666 * databases are not needed. Return the next positive available.
1668 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1669 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1672 /* Clear the database */
1673 return _mv88e6xxx_atu_flush(chip, *fid, true);
1676 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1677 struct mv88e6xxx_vtu_stu_entry *entry)
1679 struct dsa_switch *ds = chip->ds;
1680 struct mv88e6xxx_vtu_stu_entry vlan = {
1686 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1690 /* exclude all ports except the CPU and DSA ports */
1691 for (i = 0; i < chip->info->num_ports; ++i)
1692 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1693 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1694 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1696 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1697 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1698 struct mv88e6xxx_vtu_stu_entry vstp;
1700 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1701 * implemented, only one STU entry is needed to cover all VTU
1702 * entries. Thus, validate the SID 0.
1705 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1709 if (vstp.sid != vlan.sid || !vstp.valid) {
1710 memset(&vstp, 0, sizeof(vstp));
1712 vstp.sid = vlan.sid;
1714 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1724 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1725 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1732 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1736 err = _mv88e6xxx_vtu_getnext(chip, entry);
1740 if (entry->vid != vid || !entry->valid) {
1743 /* -ENOENT would've been more appropriate, but switchdev expects
1744 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1747 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1753 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1754 u16 vid_begin, u16 vid_end)
1756 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1757 struct mv88e6xxx_vtu_stu_entry vlan;
1763 mutex_lock(&chip->reg_lock);
1765 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1770 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1777 if (vlan.vid > vid_end)
1780 for (i = 0; i < chip->info->num_ports; ++i) {
1781 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1785 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1788 if (chip->ports[i].bridge_dev ==
1789 chip->ports[port].bridge_dev)
1790 break; /* same bridge, check next VLAN */
1792 netdev_warn(ds->ports[port].netdev,
1793 "hardware VLAN %d already used by %s\n",
1795 netdev_name(chip->ports[i].bridge_dev));
1799 } while (vlan.vid < vid_end);
1802 mutex_unlock(&chip->reg_lock);
1807 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1808 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1809 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1810 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1811 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1814 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1815 bool vlan_filtering)
1817 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1818 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1819 PORT_CONTROL_2_8021Q_DISABLED;
1822 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1825 mutex_lock(&chip->reg_lock);
1827 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1831 old = ret & PORT_CONTROL_2_8021Q_MASK;
1834 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1835 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1837 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1842 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1843 mv88e6xxx_port_8021q_mode_names[new],
1844 mv88e6xxx_port_8021q_mode_names[old]);
1849 mutex_unlock(&chip->reg_lock);
1855 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1856 const struct switchdev_obj_port_vlan *vlan,
1857 struct switchdev_trans *trans)
1859 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1862 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1865 /* If the requested port doesn't belong to the same bridge as the VLAN
1866 * members, do not support it (yet) and fallback to software VLAN.
1868 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1873 /* We don't need any dynamic resource from the kernel (yet),
1874 * so skip the prepare phase.
1879 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1880 u16 vid, bool untagged)
1882 struct mv88e6xxx_vtu_stu_entry vlan;
1885 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1889 vlan.data[port] = untagged ?
1890 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1891 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1893 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1896 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1897 const struct switchdev_obj_port_vlan *vlan,
1898 struct switchdev_trans *trans)
1900 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1901 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1902 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1905 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1908 mutex_lock(&chip->reg_lock);
1910 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1911 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1912 netdev_err(ds->ports[port].netdev,
1913 "failed to add VLAN %d%c\n",
1914 vid, untagged ? 'u' : 't');
1916 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1917 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1920 mutex_unlock(&chip->reg_lock);
1923 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1926 struct dsa_switch *ds = chip->ds;
1927 struct mv88e6xxx_vtu_stu_entry vlan;
1930 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1934 /* Tell switchdev if this VLAN is handled in software */
1935 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1938 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1940 /* keep the VLAN unless all ports are excluded */
1942 for (i = 0; i < chip->info->num_ports; ++i) {
1943 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1946 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1952 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1956 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1959 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1960 const struct switchdev_obj_port_vlan *vlan)
1962 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1966 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1969 mutex_lock(&chip->reg_lock);
1971 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1975 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1976 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1981 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
1988 mutex_unlock(&chip->reg_lock);
1993 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
1994 const unsigned char *addr)
1998 for (i = 0; i < 3; i++) {
1999 ret = _mv88e6xxx_reg_write(
2000 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2001 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2009 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2010 unsigned char *addr)
2014 for (i = 0; i < 3; i++) {
2015 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2016 GLOBAL_ATU_MAC_01 + i);
2019 addr[i * 2] = ret >> 8;
2020 addr[i * 2 + 1] = ret & 0xff;
2026 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2027 struct mv88e6xxx_atu_entry *entry)
2031 ret = _mv88e6xxx_atu_wait(chip);
2035 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2039 ret = _mv88e6xxx_atu_data_write(chip, entry);
2043 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2046 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2047 const unsigned char *addr, u16 vid,
2050 struct mv88e6xxx_atu_entry entry = { 0 };
2051 struct mv88e6xxx_vtu_stu_entry vlan;
2054 /* Null VLAN ID corresponds to the port private database */
2056 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2058 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2062 entry.fid = vlan.fid;
2063 entry.state = state;
2064 ether_addr_copy(entry.mac, addr);
2065 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2066 entry.trunk = false;
2067 entry.portv_trunkid = BIT(port);
2070 return _mv88e6xxx_atu_load(chip, &entry);
2073 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2074 const struct switchdev_obj_port_fdb *fdb,
2075 struct switchdev_trans *trans)
2077 /* We don't need any dynamic resource from the kernel (yet),
2078 * so skip the prepare phase.
2083 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2084 const struct switchdev_obj_port_fdb *fdb,
2085 struct switchdev_trans *trans)
2087 int state = is_multicast_ether_addr(fdb->addr) ?
2088 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2089 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2090 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2092 mutex_lock(&chip->reg_lock);
2093 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2094 netdev_err(ds->ports[port].netdev,
2095 "failed to load MAC address\n");
2096 mutex_unlock(&chip->reg_lock);
2099 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2100 const struct switchdev_obj_port_fdb *fdb)
2102 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2105 mutex_lock(&chip->reg_lock);
2106 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2107 GLOBAL_ATU_DATA_STATE_UNUSED);
2108 mutex_unlock(&chip->reg_lock);
2113 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2114 struct mv88e6xxx_atu_entry *entry)
2116 struct mv88e6xxx_atu_entry next = { 0 };
2121 ret = _mv88e6xxx_atu_wait(chip);
2125 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2129 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2133 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2137 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2138 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2139 unsigned int mask, shift;
2141 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2143 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2144 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2147 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2148 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2151 next.portv_trunkid = (ret & mask) >> shift;
2158 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2159 u16 fid, u16 vid, int port,
2160 struct switchdev_obj_port_fdb *fdb,
2161 int (*cb)(struct switchdev_obj *obj))
2163 struct mv88e6xxx_atu_entry addr = {
2164 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2168 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2173 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2177 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2180 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2181 bool is_static = addr.state ==
2182 (is_multicast_ether_addr(addr.mac) ?
2183 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2184 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2187 ether_addr_copy(fdb->addr, addr.mac);
2188 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2190 err = cb(&fdb->obj);
2194 } while (!is_broadcast_ether_addr(addr.mac));
2199 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2200 struct switchdev_obj_port_fdb *fdb,
2201 int (*cb)(struct switchdev_obj *obj))
2203 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2204 struct mv88e6xxx_vtu_stu_entry vlan = {
2205 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2210 mutex_lock(&chip->reg_lock);
2212 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2213 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2217 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2221 /* Dump VLANs' Filtering Information Databases */
2222 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2227 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2234 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2238 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2241 mutex_unlock(&chip->reg_lock);
2246 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2247 struct net_device *bridge)
2249 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2252 mutex_lock(&chip->reg_lock);
2254 /* Assign the bridge and remap each port's VLANTable */
2255 chip->ports[port].bridge_dev = bridge;
2257 for (i = 0; i < chip->info->num_ports; ++i) {
2258 if (chip->ports[i].bridge_dev == bridge) {
2259 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2265 mutex_unlock(&chip->reg_lock);
2270 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2272 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2273 struct net_device *bridge = chip->ports[port].bridge_dev;
2276 mutex_lock(&chip->reg_lock);
2278 /* Unassign the bridge and remap each port's VLANTable */
2279 chip->ports[port].bridge_dev = NULL;
2281 for (i = 0; i < chip->info->num_ports; ++i)
2282 if (i == port || chip->ports[i].bridge_dev == bridge)
2283 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2284 netdev_warn(ds->ports[i].netdev,
2285 "failed to remap\n");
2287 mutex_unlock(&chip->reg_lock);
2290 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2291 int port, int page, int reg, int val)
2295 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2297 goto restore_page_0;
2299 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2301 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2306 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2307 int port, int page, int reg)
2311 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2313 goto restore_page_0;
2315 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2317 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2322 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2324 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2325 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2326 struct gpio_desc *gpiod = chip->reset;
2327 unsigned long timeout;
2331 /* Set all ports to the disabled state. */
2332 for (i = 0; i < chip->info->num_ports; i++) {
2333 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2337 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2343 /* Wait for transmit queues to drain. */
2344 usleep_range(2000, 4000);
2346 /* If there is a gpio connected to the reset pin, toggle it */
2348 gpiod_set_value_cansleep(gpiod, 1);
2349 usleep_range(10000, 20000);
2350 gpiod_set_value_cansleep(gpiod, 0);
2351 usleep_range(10000, 20000);
2354 /* Reset the switch. Keep the PPU active if requested. The PPU
2355 * needs to be active to support indirect phy register access
2356 * through global registers 0x18 and 0x19.
2359 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2361 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2365 /* Wait up to one second for reset to complete. */
2366 timeout = jiffies + 1 * HZ;
2367 while (time_before(jiffies, timeout)) {
2368 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2372 if ((ret & is_reset) == is_reset)
2374 usleep_range(1000, 2000);
2376 if (time_after(jiffies, timeout))
2384 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2388 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2389 PAGE_FIBER_SERDES, MII_BMCR);
2393 if (ret & BMCR_PDOWN) {
2395 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2396 PAGE_FIBER_SERDES, MII_BMCR,
2403 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2406 int addr = chip->info->port_base_addr + port;
2408 if (port >= chip->info->num_ports)
2411 return mv88e6xxx_read(chip, addr, reg, val);
2414 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2416 struct dsa_switch *ds = chip->ds;
2420 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2421 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2422 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2423 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2424 /* MAC Forcing register: don't force link, speed,
2425 * duplex or flow control state to any particular
2426 * values on physical ports, but force the CPU port
2427 * and all DSA ports to their maximum bandwidth and
2430 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2431 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2432 reg &= ~PORT_PCS_CTRL_UNFORCED;
2433 reg |= PORT_PCS_CTRL_FORCE_LINK |
2434 PORT_PCS_CTRL_LINK_UP |
2435 PORT_PCS_CTRL_DUPLEX_FULL |
2436 PORT_PCS_CTRL_FORCE_DUPLEX;
2437 if (mv88e6xxx_6065_family(chip))
2438 reg |= PORT_PCS_CTRL_100;
2440 reg |= PORT_PCS_CTRL_1000;
2442 reg |= PORT_PCS_CTRL_UNFORCED;
2445 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2446 PORT_PCS_CTRL, reg);
2451 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2452 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2453 * tunneling, determine priority by looking at 802.1p and IP
2454 * priority fields (IP prio has precedence), and set STP state
2457 * If this is the CPU link, use DSA or EDSA tagging depending
2458 * on which tagging mode was configured.
2460 * If this is a link to another switch, use DSA tagging mode.
2462 * If this is the upstream port for this switch, enable
2463 * forwarding of unknown unicasts and multicasts.
2466 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2467 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2468 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2469 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2470 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2471 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2472 PORT_CONTROL_STATE_FORWARDING;
2473 if (dsa_is_cpu_port(ds, port)) {
2474 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2475 reg |= PORT_CONTROL_DSA_TAG;
2476 if (mv88e6xxx_6352_family(chip) ||
2477 mv88e6xxx_6351_family(chip) ||
2478 mv88e6xxx_6165_family(chip) ||
2479 mv88e6xxx_6097_family(chip) ||
2480 mv88e6xxx_6320_family(chip)) {
2481 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2482 PORT_CONTROL_FORWARD_UNKNOWN |
2483 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2486 if (mv88e6xxx_6352_family(chip) ||
2487 mv88e6xxx_6351_family(chip) ||
2488 mv88e6xxx_6165_family(chip) ||
2489 mv88e6xxx_6097_family(chip) ||
2490 mv88e6xxx_6095_family(chip) ||
2491 mv88e6xxx_6065_family(chip) ||
2492 mv88e6xxx_6185_family(chip) ||
2493 mv88e6xxx_6320_family(chip)) {
2494 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2497 if (dsa_is_dsa_port(ds, port)) {
2498 if (mv88e6xxx_6095_family(chip) ||
2499 mv88e6xxx_6185_family(chip))
2500 reg |= PORT_CONTROL_DSA_TAG;
2501 if (mv88e6xxx_6352_family(chip) ||
2502 mv88e6xxx_6351_family(chip) ||
2503 mv88e6xxx_6165_family(chip) ||
2504 mv88e6xxx_6097_family(chip) ||
2505 mv88e6xxx_6320_family(chip)) {
2506 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2509 if (port == dsa_upstream_port(ds))
2510 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2511 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2514 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2520 /* If this port is connected to a SerDes, make sure the SerDes is not
2523 if (mv88e6xxx_6352_family(chip)) {
2524 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2527 ret &= PORT_STATUS_CMODE_MASK;
2528 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2529 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2530 (ret == PORT_STATUS_CMODE_SGMII)) {
2531 ret = mv88e6xxx_power_on_serdes(chip);
2537 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2538 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2539 * untagged frames on this port, do a destination address lookup on all
2540 * received packets as usual, disable ARP mirroring and don't send a
2541 * copy of all transmitted/received frames on this port to the CPU.
2544 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2545 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2546 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2547 mv88e6xxx_6185_family(chip))
2548 reg = PORT_CONTROL_2_MAP_DA;
2550 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2551 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2552 reg |= PORT_CONTROL_2_JUMBO_10240;
2554 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2555 /* Set the upstream port this port should use */
2556 reg |= dsa_upstream_port(ds);
2557 /* enable forwarding of unknown multicast addresses to
2560 if (port == dsa_upstream_port(ds))
2561 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2564 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2567 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2568 PORT_CONTROL_2, reg);
2573 /* Port Association Vector: when learning source addresses
2574 * of packets, add the address to the address database using
2575 * a port bitmap that has only the bit for this port set and
2576 * the other bits clear.
2579 /* Disable learning for CPU port */
2580 if (dsa_is_cpu_port(ds, port))
2583 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2588 /* Egress rate control 2: disable egress rate control. */
2589 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2594 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2595 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2596 mv88e6xxx_6320_family(chip)) {
2597 /* Do not limit the period of time that this port can
2598 * be paused for by the remote end or the period of
2599 * time that this port can pause the remote end.
2601 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2602 PORT_PAUSE_CTRL, 0x0000);
2606 /* Port ATU control: disable limiting the number of
2607 * address database entries that this port is allowed
2610 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2611 PORT_ATU_CONTROL, 0x0000);
2612 /* Priority Override: disable DA, SA and VTU priority
2615 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2616 PORT_PRI_OVERRIDE, 0x0000);
2620 /* Port Ethertype: use the Ethertype DSA Ethertype
2623 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2624 PORT_ETH_TYPE, ETH_P_EDSA);
2627 /* Tag Remap: use an identity 802.1p prio -> switch
2630 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2631 PORT_TAG_REGMAP_0123, 0x3210);
2635 /* Tag Remap 2: use an identity 802.1p prio -> switch
2638 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2639 PORT_TAG_REGMAP_4567, 0x7654);
2644 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2645 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2646 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2647 mv88e6xxx_6320_family(chip)) {
2648 /* Rate Control: disable ingress rate limiting. */
2649 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2650 PORT_RATE_CONTROL, 0x0001);
2655 /* Port Control 1: disable trunking, disable sending
2656 * learning messages to this port.
2658 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2663 /* Port based VLAN map: give each port the same default address
2664 * database, and allow bidirectional communication between the
2665 * CPU and DSA port(s), and the other ports.
2667 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2671 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2675 /* Default VLAN ID and priority: don't set a default VLAN
2676 * ID, and set the default packet priority to zero.
2678 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2686 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2690 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2691 (addr[0] << 8) | addr[1]);
2695 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2696 (addr[2] << 8) | addr[3]);
2700 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2701 (addr[4] << 8) | addr[5]);
2704 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2707 const unsigned int coeff = chip->info->age_time_coeff;
2708 const unsigned int min = 0x01 * coeff;
2709 const unsigned int max = 0xff * coeff;
2714 if (msecs < min || msecs > max)
2717 /* Round to nearest multiple of coeff */
2718 age_time = (msecs + coeff / 2) / coeff;
2720 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2724 /* AgeTime is 11:4 bits */
2726 val |= age_time << 4;
2728 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2731 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2732 unsigned int ageing_time)
2734 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2737 mutex_lock(&chip->reg_lock);
2738 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2739 mutex_unlock(&chip->reg_lock);
2744 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2746 struct dsa_switch *ds = chip->ds;
2747 u32 upstream_port = dsa_upstream_port(ds);
2751 /* Enable the PHY Polling Unit if present, don't discard any packets,
2752 * and mask all interrupt sources.
2755 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2756 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2757 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2759 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2763 /* Configure the upstream port, and configure it as the port to which
2764 * ingress and egress and ARP monitor frames are to be sent.
2766 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2767 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2768 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2769 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2774 /* Disable remote management, and set the switch's DSA device number. */
2775 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2776 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2777 (ds->index & 0x1f));
2781 /* Clear all the VTU and STU entries */
2782 err = _mv88e6xxx_vtu_stu_flush(chip);
2786 /* Set the default address aging time to 5 minutes, and
2787 * enable address learn messages to be sent to all message
2790 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2791 GLOBAL_ATU_CONTROL_LEARN2ALL);
2795 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2799 /* Clear all ATU entries */
2800 err = _mv88e6xxx_atu_flush(chip, 0, true);
2804 /* Configure the IP ToS mapping registers. */
2805 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2808 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2811 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2814 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2817 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2820 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2823 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2826 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2830 /* Configure the IEEE 802.1p priority mapping register. */
2831 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2835 /* Clear the statistics counters for all ports */
2836 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2837 GLOBAL_STATS_OP_FLUSH_ALL);
2841 /* Wait for the flush to complete. */
2842 err = _mv88e6xxx_stats_wait(chip);
2849 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2850 int target, int port)
2852 u16 val = (target << 8) | (port & 0xf);
2854 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2857 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2862 /* Initialize the routing port to the 32 possible target devices */
2863 for (target = 0; target < 32; ++target) {
2866 if (target < DSA_MAX_SWITCHES) {
2867 port = chip->ds->rtable[target];
2868 if (port == DSA_RTABLE_NONE)
2872 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2880 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2881 bool hask, u16 mask)
2883 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2884 u16 val = (num << 12) | (mask & port_mask);
2887 val |= GLOBAL2_TRUNK_MASK_HASK;
2889 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2892 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2895 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2896 u16 val = (id << 11) | (map & port_mask);
2898 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2901 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2903 const u16 port_mask = BIT(chip->info->num_ports) - 1;
2906 /* Clear all eight possible Trunk Mask vectors */
2907 for (i = 0; i < 8; ++i) {
2908 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2913 /* Clear all sixteen possible Trunk ID routing vectors */
2914 for (i = 0; i < 16; ++i) {
2915 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2923 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2927 /* Init all Ingress Rate Limit resources of all ports */
2928 for (port = 0; port < chip->info->num_ports; ++port) {
2929 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2930 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2931 GLOBAL2_IRL_CMD_OP_INIT_ALL |
2936 /* Wait for the operation to complete */
2937 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2938 GLOBAL2_IRL_CMD_BUSY);
2946 /* Indirect write to the Switch MAC/WoL/WoF register */
2947 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2948 unsigned int pointer, u8 data)
2950 u16 val = (pointer << 8) | data;
2952 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2955 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2959 for (i = 0; i < 6; i++) {
2960 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2968 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2971 u16 val = (pointer << 8) | (data & 0x7);
2973 return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2976 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2980 /* Clear all sixteen possible Priority Override entries */
2981 for (i = 0; i < 16; i++) {
2982 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2990 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
2992 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
2993 GLOBAL2_EEPROM_CMD_BUSY |
2994 GLOBAL2_EEPROM_CMD_RUNNING);
2997 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3001 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3005 return mv88e6xxx_g2_eeprom_wait(chip);
3008 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3011 u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3014 err = mv88e6xxx_g2_eeprom_wait(chip);
3018 err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3022 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3025 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3028 u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3031 err = mv88e6xxx_g2_eeprom_wait(chip);
3035 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3039 return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3042 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3044 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3045 GLOBAL2_SMI_PHY_CMD_BUSY);
3048 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3052 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3056 return mv88e6xxx_g2_smi_phy_wait(chip);
3059 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3062 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3065 err = mv88e6xxx_g2_smi_phy_wait(chip);
3069 err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3073 return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3076 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3079 u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3082 err = mv88e6xxx_g2_smi_phy_wait(chip);
3086 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3090 return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3093 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3098 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3099 /* Consider the frames with reserved multicast destination
3100 * addresses matching 01:80:c2:00:00:2x as MGMT.
3102 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3108 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3109 /* Consider the frames with reserved multicast destination
3110 * addresses matching 01:80:c2:00:00:0x as MGMT.
3112 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3118 /* Ignore removed tag data on doubly tagged packets, disable
3119 * flow control messages, force flow control priority to the
3120 * highest, and send all special multicast frames to the CPU
3121 * port at the highest priority.
3123 reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3124 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3125 mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3126 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3127 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3131 /* Program the DSA routing table. */
3132 err = mv88e6xxx_g2_set_device_mapping(chip);
3136 /* Clear all trunk masks and mapping. */
3137 err = mv88e6xxx_g2_clear_trunk(chip);
3141 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3142 /* Disable ingress rate limiting by resetting all per port
3143 * ingress rate limit resources to their initial state.
3145 err = mv88e6xxx_g2_clear_irl(chip);
3150 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3151 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3152 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3153 GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3158 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3159 /* Clear the priority override table. */
3160 err = mv88e6xxx_g2_clear_pot(chip);
3168 static int mv88e6xxx_setup(struct dsa_switch *ds)
3170 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3175 ds->slave_mii_bus = chip->mdio_bus;
3177 mutex_lock(&chip->reg_lock);
3179 err = mv88e6xxx_switch_reset(chip);
3183 /* Setup Switch Port Registers */
3184 for (i = 0; i < chip->info->num_ports; i++) {
3185 err = mv88e6xxx_setup_port(chip, i);
3190 /* Setup Switch Global 1 Registers */
3191 err = mv88e6xxx_g1_setup(chip);
3195 /* Setup Switch Global 2 Registers */
3196 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3197 err = mv88e6xxx_g2_setup(chip);
3203 mutex_unlock(&chip->reg_lock);
3208 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3210 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3213 mutex_lock(&chip->reg_lock);
3215 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3216 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3217 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3219 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3221 mutex_unlock(&chip->reg_lock);
3226 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3229 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3232 mutex_lock(&chip->reg_lock);
3233 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3234 mutex_unlock(&chip->reg_lock);
3239 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3242 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3245 mutex_lock(&chip->reg_lock);
3246 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3247 mutex_unlock(&chip->reg_lock);
3252 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3254 if (port >= 0 && port < chip->info->num_ports)
3259 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3261 struct mv88e6xxx_chip *chip = bus->priv;
3262 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3268 mutex_lock(&chip->reg_lock);
3270 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3271 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3272 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY))
3273 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3275 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3277 mutex_unlock(&chip->reg_lock);
3281 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3284 struct mv88e6xxx_chip *chip = bus->priv;
3285 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3291 mutex_lock(&chip->reg_lock);
3293 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3294 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3295 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY))
3296 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3298 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3300 mutex_unlock(&chip->reg_lock);
3304 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3305 struct device_node *np)
3308 struct mii_bus *bus;
3311 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3312 mv88e6xxx_ppu_state_init(chip);
3315 chip->mdio_np = of_get_child_by_name(np, "mdio");
3317 bus = devm_mdiobus_alloc(chip->dev);
3321 bus->priv = (void *)chip;
3323 bus->name = np->full_name;
3324 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3326 bus->name = "mv88e6xxx SMI";
3327 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3330 bus->read = mv88e6xxx_mdio_read;
3331 bus->write = mv88e6xxx_mdio_write;
3332 bus->parent = chip->dev;
3335 err = of_mdiobus_register(bus, chip->mdio_np);
3337 err = mdiobus_register(bus);
3339 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3342 chip->mdio_bus = bus;
3348 of_node_put(chip->mdio_np);
3353 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3356 struct mii_bus *bus = chip->mdio_bus;
3358 mdiobus_unregister(bus);
3361 of_node_put(chip->mdio_np);
3364 #ifdef CONFIG_NET_DSA_HWMON
3366 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3368 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3374 mutex_lock(&chip->reg_lock);
3376 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3380 /* Enable temperature sensor */
3381 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3385 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3389 /* Wait for temperature to stabilize */
3390 usleep_range(10000, 12000);
3392 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3398 /* Disable temperature sensor */
3399 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3403 *temp = ((val & 0x1f) - 5) * 5;
3406 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3407 mutex_unlock(&chip->reg_lock);
3411 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3413 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3414 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3419 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3423 *temp = (ret & 0xff) - 25;
3428 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3430 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3432 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3435 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3436 return mv88e63xx_get_temp(ds, temp);
3438 return mv88e61xx_get_temp(ds, temp);
3441 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3443 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3444 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3447 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3452 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3456 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3461 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3463 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3464 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3467 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3470 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3473 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3474 return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3475 (ret & 0xe0ff) | (temp << 8));
3478 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3480 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3481 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3484 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3489 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3493 *alarm = !!(ret & 0x40);
3497 #endif /* CONFIG_NET_DSA_HWMON */
3499 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3501 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3503 return chip->eeprom_len;
3506 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3507 struct ethtool_eeprom *eeprom, u8 *data)
3509 unsigned int offset = eeprom->offset;
3510 unsigned int len = eeprom->len;
3517 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3521 *data++ = (val >> 8) & 0xff;
3529 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3533 *data++ = val & 0xff;
3534 *data++ = (val >> 8) & 0xff;
3542 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3546 *data++ = val & 0xff;
3556 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3557 struct ethtool_eeprom *eeprom, u8 *data)
3559 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3562 mutex_lock(&chip->reg_lock);
3564 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3565 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3569 mutex_unlock(&chip->reg_lock);
3574 eeprom->magic = 0xc3ec4951;
3579 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3580 struct ethtool_eeprom *eeprom, u8 *data)
3582 unsigned int offset = eeprom->offset;
3583 unsigned int len = eeprom->len;
3587 /* Ensure the RO WriteEn bit is set */
3588 err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3592 if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3598 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3602 val = (*data++ << 8) | (val & 0xff);
3604 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3615 val |= *data++ << 8;
3617 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3627 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3631 val = (val & 0xff00) | *data++;
3633 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3645 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3646 struct ethtool_eeprom *eeprom, u8 *data)
3648 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3651 if (eeprom->magic != 0xc3ec4951)
3654 mutex_lock(&chip->reg_lock);
3656 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3657 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3661 mutex_unlock(&chip->reg_lock);
3666 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3668 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3669 .family = MV88E6XXX_FAMILY_6097,
3670 .name = "Marvell 88E6085",
3671 .num_databases = 4096,
3673 .port_base_addr = 0x10,
3674 .age_time_coeff = 15000,
3675 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3679 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3680 .family = MV88E6XXX_FAMILY_6095,
3681 .name = "Marvell 88E6095/88E6095F",
3682 .num_databases = 256,
3684 .port_base_addr = 0x10,
3685 .age_time_coeff = 15000,
3686 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3690 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3691 .family = MV88E6XXX_FAMILY_6165,
3692 .name = "Marvell 88E6123",
3693 .num_databases = 4096,
3695 .port_base_addr = 0x10,
3696 .age_time_coeff = 15000,
3697 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3701 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3702 .family = MV88E6XXX_FAMILY_6185,
3703 .name = "Marvell 88E6131",
3704 .num_databases = 256,
3706 .port_base_addr = 0x10,
3707 .age_time_coeff = 15000,
3708 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3712 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3713 .family = MV88E6XXX_FAMILY_6165,
3714 .name = "Marvell 88E6161",
3715 .num_databases = 4096,
3717 .port_base_addr = 0x10,
3718 .age_time_coeff = 15000,
3719 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3723 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3724 .family = MV88E6XXX_FAMILY_6165,
3725 .name = "Marvell 88E6165",
3726 .num_databases = 4096,
3728 .port_base_addr = 0x10,
3729 .age_time_coeff = 15000,
3730 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3734 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3735 .family = MV88E6XXX_FAMILY_6351,
3736 .name = "Marvell 88E6171",
3737 .num_databases = 4096,
3739 .port_base_addr = 0x10,
3740 .age_time_coeff = 15000,
3741 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3745 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3746 .family = MV88E6XXX_FAMILY_6352,
3747 .name = "Marvell 88E6172",
3748 .num_databases = 4096,
3750 .port_base_addr = 0x10,
3751 .age_time_coeff = 15000,
3752 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3756 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3757 .family = MV88E6XXX_FAMILY_6351,
3758 .name = "Marvell 88E6175",
3759 .num_databases = 4096,
3761 .port_base_addr = 0x10,
3762 .age_time_coeff = 15000,
3763 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3767 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3768 .family = MV88E6XXX_FAMILY_6352,
3769 .name = "Marvell 88E6176",
3770 .num_databases = 4096,
3772 .port_base_addr = 0x10,
3773 .age_time_coeff = 15000,
3774 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3778 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3779 .family = MV88E6XXX_FAMILY_6185,
3780 .name = "Marvell 88E6185",
3781 .num_databases = 256,
3783 .port_base_addr = 0x10,
3784 .age_time_coeff = 15000,
3785 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3789 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3790 .family = MV88E6XXX_FAMILY_6352,
3791 .name = "Marvell 88E6240",
3792 .num_databases = 4096,
3794 .port_base_addr = 0x10,
3795 .age_time_coeff = 15000,
3796 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3800 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3801 .family = MV88E6XXX_FAMILY_6320,
3802 .name = "Marvell 88E6320",
3803 .num_databases = 4096,
3805 .port_base_addr = 0x10,
3806 .age_time_coeff = 15000,
3807 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3811 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3812 .family = MV88E6XXX_FAMILY_6320,
3813 .name = "Marvell 88E6321",
3814 .num_databases = 4096,
3816 .port_base_addr = 0x10,
3817 .age_time_coeff = 15000,
3818 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3822 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3823 .family = MV88E6XXX_FAMILY_6351,
3824 .name = "Marvell 88E6350",
3825 .num_databases = 4096,
3827 .port_base_addr = 0x10,
3828 .age_time_coeff = 15000,
3829 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3833 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3834 .family = MV88E6XXX_FAMILY_6351,
3835 .name = "Marvell 88E6351",
3836 .num_databases = 4096,
3838 .port_base_addr = 0x10,
3839 .age_time_coeff = 15000,
3840 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3844 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3845 .family = MV88E6XXX_FAMILY_6352,
3846 .name = "Marvell 88E6352",
3847 .num_databases = 4096,
3849 .port_base_addr = 0x10,
3850 .age_time_coeff = 15000,
3851 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3855 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3859 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3860 if (mv88e6xxx_table[i].prod_num == prod_num)
3861 return &mv88e6xxx_table[i];
3866 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3868 const struct mv88e6xxx_info *info;
3869 unsigned int prod_num, rev;
3873 mutex_lock(&chip->reg_lock);
3874 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3875 mutex_unlock(&chip->reg_lock);
3879 prod_num = (id & 0xfff0) >> 4;
3882 info = mv88e6xxx_lookup_info(prod_num);
3886 /* Update the compatible info with the probed one */
3889 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3890 chip->info->prod_num, chip->info->name, rev);
3895 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3897 struct mv88e6xxx_chip *chip;
3899 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3905 mutex_init(&chip->reg_lock);
3910 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3911 struct mii_bus *bus, int sw_addr)
3913 /* ADDR[0] pin is unavailable externally and considered zero */
3918 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3919 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3920 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3925 chip->sw_addr = sw_addr;
3930 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3931 struct device *host_dev, int sw_addr,
3934 struct mv88e6xxx_chip *chip;
3935 struct mii_bus *bus;
3938 bus = dsa_host_dev_to_mii_bus(host_dev);
3942 chip = mv88e6xxx_alloc_chip(dsa_dev);
3946 /* Legacy SMI probing will only support chips similar to 88E6085 */
3947 chip->info = &mv88e6xxx_table[MV88E6085];
3949 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3953 err = mv88e6xxx_detect(chip);
3957 err = mv88e6xxx_mdio_register(chip, NULL);
3963 return chip->info->name;
3965 devm_kfree(dsa_dev, chip);
3970 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3971 .tag_protocol = DSA_TAG_PROTO_EDSA,
3972 .probe = mv88e6xxx_drv_probe,
3973 .setup = mv88e6xxx_setup,
3974 .set_addr = mv88e6xxx_set_addr,
3975 .adjust_link = mv88e6xxx_adjust_link,
3976 .get_strings = mv88e6xxx_get_strings,
3977 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3978 .get_sset_count = mv88e6xxx_get_sset_count,
3979 .set_eee = mv88e6xxx_set_eee,
3980 .get_eee = mv88e6xxx_get_eee,
3981 #ifdef CONFIG_NET_DSA_HWMON
3982 .get_temp = mv88e6xxx_get_temp,
3983 .get_temp_limit = mv88e6xxx_get_temp_limit,
3984 .set_temp_limit = mv88e6xxx_set_temp_limit,
3985 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3987 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3988 .get_eeprom = mv88e6xxx_get_eeprom,
3989 .set_eeprom = mv88e6xxx_set_eeprom,
3990 .get_regs_len = mv88e6xxx_get_regs_len,
3991 .get_regs = mv88e6xxx_get_regs,
3992 .set_ageing_time = mv88e6xxx_set_ageing_time,
3993 .port_bridge_join = mv88e6xxx_port_bridge_join,
3994 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3995 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3996 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3997 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3998 .port_vlan_add = mv88e6xxx_port_vlan_add,
3999 .port_vlan_del = mv88e6xxx_port_vlan_del,
4000 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
4001 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
4002 .port_fdb_add = mv88e6xxx_port_fdb_add,
4003 .port_fdb_del = mv88e6xxx_port_fdb_del,
4004 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
4007 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4008 struct device_node *np)
4010 struct device *dev = chip->dev;
4011 struct dsa_switch *ds;
4013 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4019 ds->drv = &mv88e6xxx_switch_driver;
4021 dev_set_drvdata(dev, ds);
4023 return dsa_register_switch(ds, np);
4026 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4028 dsa_unregister_switch(chip->ds);
4031 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4033 struct device *dev = &mdiodev->dev;
4034 struct device_node *np = dev->of_node;
4035 const struct mv88e6xxx_info *compat_info;
4036 struct mv88e6xxx_chip *chip;
4040 compat_info = of_device_get_match_data(dev);
4044 chip = mv88e6xxx_alloc_chip(dev);
4048 chip->info = compat_info;
4050 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4054 err = mv88e6xxx_detect(chip);
4058 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4059 if (IS_ERR(chip->reset))
4060 return PTR_ERR(chip->reset);
4062 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4063 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4064 chip->eeprom_len = eeprom_len;
4066 err = mv88e6xxx_mdio_register(chip, np);
4070 err = mv88e6xxx_register_switch(chip, np);
4072 mv88e6xxx_mdio_unregister(chip);
4079 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4081 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4082 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4084 mv88e6xxx_unregister_switch(chip);
4085 mv88e6xxx_mdio_unregister(chip);
4088 static const struct of_device_id mv88e6xxx_of_match[] = {
4090 .compatible = "marvell,mv88e6085",
4091 .data = &mv88e6xxx_table[MV88E6085],
4096 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4098 static struct mdio_driver mv88e6xxx_driver = {
4099 .probe = mv88e6xxx_probe,
4100 .remove = mv88e6xxx_remove,
4102 .name = "mv88e6085",
4103 .of_match_table = mv88e6xxx_of_match,
4107 static int __init mv88e6xxx_init(void)
4109 register_switch_driver(&mv88e6xxx_switch_driver);
4110 return mdio_driver_register(&mv88e6xxx_driver);
4112 module_init(mv88e6xxx_init);
4114 static void __exit mv88e6xxx_cleanup(void)
4116 mdio_driver_unregister(&mv88e6xxx_driver);
4117 unregister_switch_driver(&mv88e6xxx_switch_driver);
4119 module_exit(mv88e6xxx_cleanup);
4121 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4122 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4123 MODULE_LICENSE("GPL");