drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg,
 220                           u16 mask)
 221 {
 222         unsigned long timeout = jiffies + HZ / 10;
 223
 224         while (time_before(jiffies, timeout)) {
 225                 u16 val;
 226                 int err;
 227
 228                 err = mv88e6xxx_read(chip, addr, reg, &val);
 229                 if (err)
 230                         return err;
 231
 232                 if (!(val & mask))
 233                         return 0;
 234
 235                 usleep_range(1000, 2000);
 236         }
 237
 238         return -ETIMEDOUT;
 239 }
 240
 241 /* Indirect write to single pointer-data register with an Update bit */
 242 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 243                             u16 update)
 244 {
 245         u16 val;
 246         int i, err;
 247
 248         /* Wait until the previous operation is completed */
 249         for (i = 0; i < 16; ++i) {
 250                 err = mv88e6xxx_read(chip, addr, reg, &val);
 251                 if (err)
 252                         return err;
 253
 254                 if (!(val & BIT(15)))
 255                         break;
 256         }
 257
 258         if (i == 16)
 259                 return -ETIMEDOUT;
 260
 261         /* Set the Update bit to trigger a write operation */
 262         val = BIT(15) | update;
 263
 264         return mv88e6xxx_write(chip, addr, reg, val);
 265 }
 266
 267 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 268 {
 269         u16 val;
 270         int err;
 271
 272         err = mv88e6xxx_read(chip, addr, reg, &val);
 273         if (err)
 274                 return err;
 275
 276         return val;
 277 }
 278
 279 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 280                                 int reg, u16 val)
 281 {
 282         return mv88e6xxx_write(chip, addr, reg, val);
 283 }
 284
 285 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
 286                                       int addr, int regnum)
 287 {
 288         if (addr >= 0)
 289                 return _mv88e6xxx_reg_read(chip, addr, regnum);
 290         return 0xffff;
 291 }
 292
 293 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
 294                                        int addr, int regnum, u16 val)
 295 {
 296         if (addr >= 0)
 297                 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
 298         return 0;
 299 }
 300
 301 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 302 {
 303         int ret;
 304         unsigned long timeout;
 305
 306         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 307         if (ret < 0)
 308                 return ret;
 309
 310         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 311                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 312         if (ret)
 313                 return ret;
 314
 315         timeout = jiffies + 1 * HZ;
 316         while (time_before(jiffies, timeout)) {
 317                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 318                 if (ret < 0)
 319                         return ret;
 320
 321                 usleep_range(1000, 2000);
 322                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 323                     GLOBAL_STATUS_PPU_POLLING)
 324                         return 0;
 325         }
 326
 327         return -ETIMEDOUT;
 328 }
 329
 330 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 331 {
 332         int ret, err;
 333         unsigned long timeout;
 334
 335         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 336         if (ret < 0)
 337                 return ret;
 338
 339         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 340                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 341         if (err)
 342                 return err;
 343
 344         timeout = jiffies + 1 * HZ;
 345         while (time_before(jiffies, timeout)) {
 346                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 347                 if (ret < 0)
 348                         return ret;
 349
 350                 usleep_range(1000, 2000);
 351                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 352                     GLOBAL_STATUS_PPU_POLLING)
 353                         return 0;
 354         }
 355
 356         return -ETIMEDOUT;
 357 }
 358
 359 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 360 {
 361         struct mv88e6xxx_chip *chip;
 362
 363         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 364
 365         mutex_lock(&chip->reg_lock);
 366
 367         if (mutex_trylock(&chip->ppu_mutex)) {
 368                 if (mv88e6xxx_ppu_enable(chip) == 0)
 369                         chip->ppu_disabled = 0;
 370                 mutex_unlock(&chip->ppu_mutex);
 371         }
 372
 373         mutex_unlock(&chip->reg_lock);
 374 }
 375
 376 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 377 {
 378         struct mv88e6xxx_chip *chip = (void *)_ps;
 379
 380         schedule_work(&chip->ppu_work);
 381 }
 382
 383 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 384 {
 385         int ret;
 386
 387         mutex_lock(&chip->ppu_mutex);
 388
 389         /* If the PHY polling unit is enabled, disable it so that
 390          * we can access the PHY registers.  If it was already
 391          * disabled, cancel the timer that is going to re-enable
 392          * it.
 393          */
 394         if (!chip->ppu_disabled) {
 395                 ret = mv88e6xxx_ppu_disable(chip);
 396                 if (ret < 0) {
 397                         mutex_unlock(&chip->ppu_mutex);
 398                         return ret;
 399                 }
 400                 chip->ppu_disabled = 1;
 401         } else {
 402                 del_timer(&chip->ppu_timer);
 403                 ret = 0;
 404         }
 405
 406         return ret;
 407 }
 408
 409 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 410 {
 411         /* Schedule a timer to re-enable the PHY polling unit. */
 412         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 413         mutex_unlock(&chip->ppu_mutex);
 414 }
 415
 416 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 417 {
 418         mutex_init(&chip->ppu_mutex);
 419         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 420         init_timer(&chip->ppu_timer);
 421         chip->ppu_timer.data = (unsigned long)chip;
 422         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 423 }
 424
 425 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
 426                                    int regnum)
 427 {
 428         int ret;
 429
 430         ret = mv88e6xxx_ppu_access_get(chip);
 431         if (ret >= 0) {
 432                 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
 433                 mv88e6xxx_ppu_access_put(chip);
 434         }
 435
 436         return ret;
 437 }
 438
 439 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
 440                                     int regnum, u16 val)
 441 {
 442         int ret;
 443
 444         ret = mv88e6xxx_ppu_access_get(chip);
 445         if (ret >= 0) {
 446                 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
 447                 mv88e6xxx_ppu_access_put(chip);
 448         }
 449
 450         return ret;
 451 }
 452
 453 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 454 {
 455         return chip->info->family == MV88E6XXX_FAMILY_6065;
 456 }
 457
 458 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 459 {
 460         return chip->info->family == MV88E6XXX_FAMILY_6095;
 461 }
 462
 463 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 464 {
 465         return chip->info->family == MV88E6XXX_FAMILY_6097;
 466 }
 467
 468 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 469 {
 470         return chip->info->family == MV88E6XXX_FAMILY_6165;
 471 }
 472
 473 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 474 {
 475         return chip->info->family == MV88E6XXX_FAMILY_6185;
 476 }
 477
 478 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 479 {
 480         return chip->info->family == MV88E6XXX_FAMILY_6320;
 481 }
 482
 483 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 484 {
 485         return chip->info->family == MV88E6XXX_FAMILY_6351;
 486 }
 487
 488 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 489 {
 490         return chip->info->family == MV88E6XXX_FAMILY_6352;
 491 }
 492
 493 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 494 {
 495         return chip->info->num_databases;
 496 }
 497
 498 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 499 {
 500         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 501         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 502             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 503                 return true;
 504
 505         return false;
 506 }
 507
 508 /* We expect the switch to perform auto negotiation if there is a real
 509  * phy. However, in the case of a fixed link phy, we force the port
 510  * settings from the fixed link settings.
 511  */
 512 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 513                                   struct phy_device *phydev)
 514 {
 515         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 516         u32 reg;
 517         int ret;
 518
 519         if (!phy_is_pseudo_fixed_link(phydev))
 520                 return;
 521
 522         mutex_lock(&chip->reg_lock);
 523
 524         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 525         if (ret < 0)
 526                 goto out;
 527
 528         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 529                       PORT_PCS_CTRL_FORCE_LINK |
 530                       PORT_PCS_CTRL_DUPLEX_FULL |
 531                       PORT_PCS_CTRL_FORCE_DUPLEX |
 532                       PORT_PCS_CTRL_UNFORCED);
 533
 534         reg |= PORT_PCS_CTRL_FORCE_LINK;
 535         if (phydev->link)
 536                 reg |= PORT_PCS_CTRL_LINK_UP;
 537
 538         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 539                 goto out;
 540
 541         switch (phydev->speed) {
 542         case SPEED_1000:
 543                 reg |= PORT_PCS_CTRL_1000;
 544                 break;
 545         case SPEED_100:
 546                 reg |= PORT_PCS_CTRL_100;
 547                 break;
 548         case SPEED_10:
 549                 reg |= PORT_PCS_CTRL_10;
 550                 break;
 551         default:
 552                 pr_info("Unknown speed");
 553                 goto out;
 554         }
 555
 556         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 557         if (phydev->duplex == DUPLEX_FULL)
 558                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 559
 560         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 561             (port >= chip->info->num_ports - 2)) {
 562                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 563                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 564                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 565                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 566                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 567                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 568                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 569         }
 570         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 571
 572 out:
 573         mutex_unlock(&chip->reg_lock);
 574 }
 575
 576 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 577 {
 578         int ret;
 579         int i;
 580
 581         for (i = 0; i < 10; i++) {
 582                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 583                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 584                         return 0;
 585         }
 586
 587         return -ETIMEDOUT;
 588 }
 589
 590 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 591 {
 592         int ret;
 593
 594         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 595                 port = (port + 1) << 5;
 596
 597         /* Snapshot the hardware statistics counters for this port. */
 598         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 599                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 600                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 601         if (ret < 0)
 602                 return ret;
 603
 604         /* Wait for the snapshotting to complete. */
 605         ret = _mv88e6xxx_stats_wait(chip);
 606         if (ret < 0)
 607                 return ret;
 608
 609         return 0;
 610 }
 611
 612 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 613                                   int stat, u32 *val)
 614 {
 615         u32 _val;
 616         int ret;
 617
 618         *val = 0;
 619
 620         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 621                                    GLOBAL_STATS_OP_READ_CAPTURED |
 622                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 623         if (ret < 0)
 624                 return;
 625
 626         ret = _mv88e6xxx_stats_wait(chip);
 627         if (ret < 0)
 628                 return;
 629
 630         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 631         if (ret < 0)
 632                 return;
 633
 634         _val = ret << 16;
 635
 636         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 637         if (ret < 0)
 638                 return;
 639
 640         *val = _val | ret;
 641 }
 642
 643 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 644         { "in_good_octets",     8, 0x00, BANK0, },
 645         { "in_bad_octets",      4, 0x02, BANK0, },
 646         { "in_unicast",         4, 0x04, BANK0, },
 647         { "in_broadcasts",      4, 0x06, BANK0, },
 648         { "in_multicasts",      4, 0x07, BANK0, },
 649         { "in_pause",           4, 0x16, BANK0, },
 650         { "in_undersize",       4, 0x18, BANK0, },
 651         { "in_fragments",       4, 0x19, BANK0, },
 652         { "in_oversize",        4, 0x1a, BANK0, },
 653         { "in_jabber",          4, 0x1b, BANK0, },
 654         { "in_rx_error",        4, 0x1c, BANK0, },
 655         { "in_fcs_error",       4, 0x1d, BANK0, },
 656         { "out_octets",         8, 0x0e, BANK0, },
 657         { "out_unicast",        4, 0x10, BANK0, },
 658         { "out_broadcasts",     4, 0x13, BANK0, },
 659         { "out_multicasts",     4, 0x12, BANK0, },
 660         { "out_pause",          4, 0x15, BANK0, },
 661         { "excessive",          4, 0x11, BANK0, },
 662         { "collisions",         4, 0x1e, BANK0, },
 663         { "deferred",           4, 0x05, BANK0, },
 664         { "single",             4, 0x14, BANK0, },
 665         { "multiple",           4, 0x17, BANK0, },
 666         { "out_fcs_error",      4, 0x03, BANK0, },
 667         { "late",               4, 0x1f, BANK0, },
 668         { "hist_64bytes",       4, 0x08, BANK0, },
 669         { "hist_65_127bytes",   4, 0x09, BANK0, },
 670         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 671         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 672         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 673         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 674         { "sw_in_discards",     4, 0x10, PORT, },
 675         { "sw_in_filtered",     2, 0x12, PORT, },
 676         { "sw_out_filtered",    2, 0x13, PORT, },
 677         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 678         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 679         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 680         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 681         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 682         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 683         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 684         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 685         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 686         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 687         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 688         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 689         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 690         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 691         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 692         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 693         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 694         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 695         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 696         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 697         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 698         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 699         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 700         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 701         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 702         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 703 };
 704
 705 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 706                                struct mv88e6xxx_hw_stat *stat)
 707 {
 708         switch (stat->type) {
 709         case BANK0:
 710                 return true;
 711         case BANK1:
 712                 return mv88e6xxx_6320_family(chip);
 713         case PORT:
 714                 return mv88e6xxx_6095_family(chip) ||
 715                         mv88e6xxx_6185_family(chip) ||
 716                         mv88e6xxx_6097_family(chip) ||
 717                         mv88e6xxx_6165_family(chip) ||
 718                         mv88e6xxx_6351_family(chip) ||
 719                         mv88e6xxx_6352_family(chip);
 720         }
 721         return false;
 722 }
 723
 724 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 725                                             struct mv88e6xxx_hw_stat *s,
 726                                             int port)
 727 {
 728         u32 low;
 729         u32 high = 0;
 730         int ret;
 731         u64 value;
 732
 733         switch (s->type) {
 734         case PORT:
 735                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 736                 if (ret < 0)
 737                         return UINT64_MAX;
 738
 739                 low = ret;
 740                 if (s->sizeof_stat == 4) {
 741                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 742                                                   s->reg + 1);
 743                         if (ret < 0)
 744                                 return UINT64_MAX;
 745                         high = ret;
 746                 }
 747                 break;
 748         case BANK0:
 749         case BANK1:
 750                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 751                 if (s->sizeof_stat == 8)
 752                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 753         }
 754         value = (((u64)high) << 16) | low;
 755         return value;
 756 }
 757
 758 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 759                                   uint8_t *data)
 760 {
 761         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 762         struct mv88e6xxx_hw_stat *stat;
 763         int i, j;
 764
 765         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 766                 stat = &mv88e6xxx_hw_stats[i];
 767                 if (mv88e6xxx_has_stat(chip, stat)) {
 768                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 769                                ETH_GSTRING_LEN);
 770                         j++;
 771                 }
 772         }
 773 }
 774
 775 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 776 {
 777         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 778         struct mv88e6xxx_hw_stat *stat;
 779         int i, j;
 780
 781         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 782                 stat = &mv88e6xxx_hw_stats[i];
 783                 if (mv88e6xxx_has_stat(chip, stat))
 784                         j++;
 785         }
 786         return j;
 787 }
 788
 789 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 790                                         uint64_t *data)
 791 {
 792         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 793         struct mv88e6xxx_hw_stat *stat;
 794         int ret;
 795         int i, j;
 796
 797         mutex_lock(&chip->reg_lock);
 798
 799         ret = _mv88e6xxx_stats_snapshot(chip, port);
 800         if (ret < 0) {
 801                 mutex_unlock(&chip->reg_lock);
 802                 return;
 803         }
 804         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 805                 stat = &mv88e6xxx_hw_stats[i];
 806                 if (mv88e6xxx_has_stat(chip, stat)) {
 807                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 808                         j++;
 809                 }
 810         }
 811
 812         mutex_unlock(&chip->reg_lock);
 813 }
 814
 815 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 816 {
 817         return 32 * sizeof(u16);
 818 }
 819
 820 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 821                                struct ethtool_regs *regs, void *_p)
 822 {
 823         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 824         u16 *p = _p;
 825         int i;
 826
 827         regs->version = 0;
 828
 829         memset(p, 0xff, 32 * sizeof(u16));
 830
 831         mutex_lock(&chip->reg_lock);
 832
 833         for (i = 0; i < 32; i++) {
 834                 int ret;
 835
 836                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 837                 if (ret >= 0)
 838                         p[i] = ret;
 839         }
 840
 841         mutex_unlock(&chip->reg_lock);
 842 }
 843
 844 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
 845 {
 846         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
 847                               GLOBAL_ATU_OP_BUSY);
 848 }
 849
 850 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
 851                                      int reg, u16 *val);
 852 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
 853                                       int reg, u16 val);
 854
 855 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
 856                                         int addr, int regnum)
 857 {
 858         u16 val;
 859         int err;
 860
 861         err = mv88e6xxx_g2_smi_phy_read(chip, addr, regnum, &val);
 862         if (err)
 863                 return err;
 864
 865         return val;
 866 }
 867
 868 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
 869                                          int addr, int regnum, u16 val)
 870 {
 871         return mv88e6xxx_g2_smi_phy_write(chip, addr, regnum, val);
 872 }
 873
 874 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
 875                              struct ethtool_eee *e)
 876 {
 877         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 878         int reg;
 879
 880         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 881                 return -EOPNOTSUPP;
 882
 883         mutex_lock(&chip->reg_lock);
 884
 885         reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 886         if (reg < 0)
 887                 goto out;
 888
 889         e->eee_enabled = !!(reg & 0x0200);
 890         e->tx_lpi_enabled = !!(reg & 0x0100);
 891
 892         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
 893         if (reg < 0)
 894                 goto out;
 895
 896         e->eee_active = !!(reg & PORT_STATUS_EEE);
 897         reg = 0;
 898
 899 out:
 900         mutex_unlock(&chip->reg_lock);
 901         return reg;
 902 }
 903
 904 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
 905                              struct phy_device *phydev, struct ethtool_eee *e)
 906 {
 907         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 908         int reg;
 909         int ret;
 910
 911         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
 912                 return -EOPNOTSUPP;
 913
 914         mutex_lock(&chip->reg_lock);
 915
 916         ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
 917         if (ret < 0)
 918                 goto out;
 919
 920         reg = ret & ~0x0300;
 921         if (e->eee_enabled)
 922                 reg |= 0x0200;
 923         if (e->tx_lpi_enabled)
 924                 reg |= 0x0100;
 925
 926         ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
 927 out:
 928         mutex_unlock(&chip->reg_lock);
 929
 930         return ret;
 931 }
 932
 933 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
 934 {
 935         int ret;
 936
 937         if (mv88e6xxx_has_fid_reg(chip)) {
 938                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
 939                                            fid);
 940                 if (ret < 0)
 941                         return ret;
 942         } else if (mv88e6xxx_num_databases(chip) == 256) {
 943                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
 944                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
 945                 if (ret < 0)
 946                         return ret;
 947
 948                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
 949                                            (ret & 0xfff) |
 950                                            ((fid << 8) & 0xf000));
 951                 if (ret < 0)
 952                         return ret;
 953
 954                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
 955                 cmd |= fid & 0xf;
 956         }
 957
 958         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
 959         if (ret < 0)
 960                 return ret;
 961
 962         return _mv88e6xxx_atu_wait(chip);
 963 }
 964
 965 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
 966                                      struct mv88e6xxx_atu_entry *entry)
 967 {
 968         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
 969
 970         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
 971                 unsigned int mask, shift;
 972
 973                 if (entry->trunk) {
 974                         data |= GLOBAL_ATU_DATA_TRUNK;
 975                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
 976                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
 977                 } else {
 978                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
 979                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
 980                 }
 981
 982                 data |= (entry->portv_trunkid << shift) & mask;
 983         }
 984
 985         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
 986 }
 987
 988 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
 989                                      struct mv88e6xxx_atu_entry *entry,
 990                                      bool static_too)
 991 {
 992         int op;
 993         int err;
 994
 995         err = _mv88e6xxx_atu_wait(chip);
 996         if (err)
 997                 return err;
 998
 999         err = _mv88e6xxx_atu_data_write(chip, entry);
1000         if (err)
1001                 return err;
1002
1003         if (entry->fid) {
1004                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1005                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1006         } else {
1007                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1008                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1009         }
1010
1011         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1012 }
1013
1014 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1015                                 u16 fid, bool static_too)
1016 {
1017         struct mv88e6xxx_atu_entry entry = {
1018                 .fid = fid,
1019                 .state = 0, /* EntryState bits must be 0 */
1020         };
1021
1022         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1023 }
1024
1025 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1026                                int from_port, int to_port, bool static_too)
1027 {
1028         struct mv88e6xxx_atu_entry entry = {
1029                 .trunk = false,
1030                 .fid = fid,
1031         };
1032
1033         /* EntryState bits must be 0xF */
1034         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1035
1036         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1037         entry.portv_trunkid = (to_port & 0x0f) << 4;
1038         entry.portv_trunkid |= from_port & 0x0f;
1039
1040         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1041 }
1042
1043 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1044                                  int port, bool static_too)
1045 {
1046         /* Destination port 0xF means remove the entries */
1047         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1048 }
1049
1050 static const char * const mv88e6xxx_port_state_names[] = {
1051         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1052         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1053         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1054         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1055 };
1056
1057 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1058                                  u8 state)
1059 {
1060         struct dsa_switch *ds = chip->ds;
1061         int reg, ret = 0;
1062         u8 oldstate;
1063
1064         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1065         if (reg < 0)
1066                 return reg;
1067
1068         oldstate = reg & PORT_CONTROL_STATE_MASK;
1069
1070         if (oldstate != state) {
1071                 /* Flush forwarding database if we're moving a port
1072                  * from Learning or Forwarding state to Disabled or
1073                  * Blocking or Listening state.
1074                  */
1075                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1076                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1077                     (state == PORT_CONTROL_STATE_DISABLED ||
1078                      state == PORT_CONTROL_STATE_BLOCKING)) {
1079                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1080                         if (ret)
1081                                 return ret;
1082                 }
1083
1084                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1085                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1086                                            reg);
1087                 if (ret)
1088                         return ret;
1089
1090                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1091                            mv88e6xxx_port_state_names[state],
1092                            mv88e6xxx_port_state_names[oldstate]);
1093         }
1094
1095         return ret;
1096 }
1097
1098 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1099 {
1100         struct net_device *bridge = chip->ports[port].bridge_dev;
1101         const u16 mask = (1 << chip->info->num_ports) - 1;
1102         struct dsa_switch *ds = chip->ds;
1103         u16 output_ports = 0;
1104         int reg;
1105         int i;
1106
1107         /* allow CPU port or DSA link(s) to send frames to every port */
1108         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1109                 output_ports = mask;
1110         } else {
1111                 for (i = 0; i < chip->info->num_ports; ++i) {
1112                         /* allow sending frames to every group member */
1113                         if (bridge && chip->ports[i].bridge_dev == bridge)
1114                                 output_ports |= BIT(i);
1115
1116                         /* allow sending frames to CPU port and DSA link(s) */
1117                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1118                                 output_ports |= BIT(i);
1119                 }
1120         }
1121
1122         /* prevent frames from going back out of the port they came in on */
1123         output_ports &= ~BIT(port);
1124
1125         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1126         if (reg < 0)
1127                 return reg;
1128
1129         reg &= ~mask;
1130         reg |= output_ports & mask;
1131
1132         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1133 }
1134
1135 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1136                                          u8 state)
1137 {
1138         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1139         int stp_state;
1140         int err;
1141
1142         switch (state) {
1143         case BR_STATE_DISABLED:
1144                 stp_state = PORT_CONTROL_STATE_DISABLED;
1145                 break;
1146         case BR_STATE_BLOCKING:
1147         case BR_STATE_LISTENING:
1148                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1149                 break;
1150         case BR_STATE_LEARNING:
1151                 stp_state = PORT_CONTROL_STATE_LEARNING;
1152                 break;
1153         case BR_STATE_FORWARDING:
1154         default:
1155                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1156                 break;
1157         }
1158
1159         mutex_lock(&chip->reg_lock);
1160         err = _mv88e6xxx_port_state(chip, port, stp_state);
1161         mutex_unlock(&chip->reg_lock);
1162
1163         if (err)
1164                 netdev_err(ds->ports[port].netdev,
1165                            "failed to update state to %s\n",
1166                            mv88e6xxx_port_state_names[stp_state]);
1167 }
1168
1169 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1170                                 u16 *new, u16 *old)
1171 {
1172         struct dsa_switch *ds = chip->ds;
1173         u16 pvid;
1174         int ret;
1175
1176         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1177         if (ret < 0)
1178                 return ret;
1179
1180         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1181
1182         if (new) {
1183                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1184                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1185
1186                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1187                                            PORT_DEFAULT_VLAN, ret);
1188                 if (ret < 0)
1189                         return ret;
1190
1191                 netdev_dbg(ds->ports[port].netdev,
1192                            "DefaultVID %d (was %d)\n", *new, pvid);
1193         }
1194
1195         if (old)
1196                 *old = pvid;
1197
1198         return 0;
1199 }
1200
1201 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1202                                     int port, u16 *pvid)
1203 {
1204         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1205 }
1206
1207 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1208                                     int port, u16 pvid)
1209 {
1210         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1211 }
1212
1213 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1214 {
1215         return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1216                               GLOBAL_VTU_OP_BUSY);
1217 }
1218
1219 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1220 {
1221         int ret;
1222
1223         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1224         if (ret < 0)
1225                 return ret;
1226
1227         return _mv88e6xxx_vtu_wait(chip);
1228 }
1229
1230 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1231 {
1232         int ret;
1233
1234         ret = _mv88e6xxx_vtu_wait(chip);
1235         if (ret < 0)
1236                 return ret;
1237
1238         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1239 }
1240
1241 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1242                                         struct mv88e6xxx_vtu_stu_entry *entry,
1243                                         unsigned int nibble_offset)
1244 {
1245         u16 regs[3];
1246         int i;
1247         int ret;
1248
1249         for (i = 0; i < 3; ++i) {
1250                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1251                                           GLOBAL_VTU_DATA_0_3 + i);
1252                 if (ret < 0)
1253                         return ret;
1254
1255                 regs[i] = ret;
1256         }
1257
1258         for (i = 0; i < chip->info->num_ports; ++i) {
1259                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1260                 u16 reg = regs[i / 4];
1261
1262                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1269                                    struct mv88e6xxx_vtu_stu_entry *entry)
1270 {
1271         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1272 }
1273
1274 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1275                                    struct mv88e6xxx_vtu_stu_entry *entry)
1276 {
1277         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1278 }
1279
1280 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1281                                          struct mv88e6xxx_vtu_stu_entry *entry,
1282                                          unsigned int nibble_offset)
1283 {
1284         u16 regs[3] = { 0 };
1285         int i;
1286         int ret;
1287
1288         for (i = 0; i < chip->info->num_ports; ++i) {
1289                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1290                 u8 data = entry->data[i];
1291
1292                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1293         }
1294
1295         for (i = 0; i < 3; ++i) {
1296                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1297                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1298                 if (ret < 0)
1299                         return ret;
1300         }
1301
1302         return 0;
1303 }
1304
1305 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1306                                     struct mv88e6xxx_vtu_stu_entry *entry)
1307 {
1308         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1309 }
1310
1311 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1312                                     struct mv88e6xxx_vtu_stu_entry *entry)
1313 {
1314         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1315 }
1316
1317 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1318 {
1319         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1320                                     vid & GLOBAL_VTU_VID_MASK);
1321 }
1322
1323 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1324                                   struct mv88e6xxx_vtu_stu_entry *entry)
1325 {
1326         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1327         int ret;
1328
1329         ret = _mv88e6xxx_vtu_wait(chip);
1330         if (ret < 0)
1331                 return ret;
1332
1333         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1334         if (ret < 0)
1335                 return ret;
1336
1337         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1338         if (ret < 0)
1339                 return ret;
1340
1341         next.vid = ret & GLOBAL_VTU_VID_MASK;
1342         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1343
1344         if (next.valid) {
1345                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1346                 if (ret < 0)
1347                         return ret;
1348
1349                 if (mv88e6xxx_has_fid_reg(chip)) {
1350                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1351                                                   GLOBAL_VTU_FID);
1352                         if (ret < 0)
1353                                 return ret;
1354
1355                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1356                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1357                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1358                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1359                          */
1360                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1361                                                   GLOBAL_VTU_OP);
1362                         if (ret < 0)
1363                                 return ret;
1364
1365                         next.fid = (ret & 0xf00) >> 4;
1366                         next.fid |= ret & 0xf;
1367                 }
1368
1369                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1370                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1371                                                   GLOBAL_VTU_SID);
1372                         if (ret < 0)
1373                                 return ret;
1374
1375                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1376                 }
1377         }
1378
1379         *entry = next;
1380         return 0;
1381 }
1382
1383 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1384                                     struct switchdev_obj_port_vlan *vlan,
1385                                     int (*cb)(struct switchdev_obj *obj))
1386 {
1387         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1388         struct mv88e6xxx_vtu_stu_entry next;
1389         u16 pvid;
1390         int err;
1391
1392         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1393                 return -EOPNOTSUPP;
1394
1395         mutex_lock(&chip->reg_lock);
1396
1397         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1398         if (err)
1399                 goto unlock;
1400
1401         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1402         if (err)
1403                 goto unlock;
1404
1405         do {
1406                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1407                 if (err)
1408                         break;
1409
1410                 if (!next.valid)
1411                         break;
1412
1413                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1414                         continue;
1415
1416                 /* reinit and dump this VLAN obj */
1417                 vlan->vid_begin = next.vid;
1418                 vlan->vid_end = next.vid;
1419                 vlan->flags = 0;
1420
1421                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1422                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1423
1424                 if (next.vid == pvid)
1425                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1426
1427                 err = cb(&vlan->obj);
1428                 if (err)
1429                         break;
1430         } while (next.vid < GLOBAL_VTU_VID_MASK);
1431
1432 unlock:
1433         mutex_unlock(&chip->reg_lock);
1434
1435         return err;
1436 }
1437
1438 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1439                                     struct mv88e6xxx_vtu_stu_entry *entry)
1440 {
1441         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1442         u16 reg = 0;
1443         int ret;
1444
1445         ret = _mv88e6xxx_vtu_wait(chip);
1446         if (ret < 0)
1447                 return ret;
1448
1449         if (!entry->valid)
1450                 goto loadpurge;
1451
1452         /* Write port member tags */
1453         ret = mv88e6xxx_vtu_data_write(chip, entry);
1454         if (ret < 0)
1455                 return ret;
1456
1457         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1458                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1459                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1460                                            reg);
1461                 if (ret < 0)
1462                         return ret;
1463         }
1464
1465         if (mv88e6xxx_has_fid_reg(chip)) {
1466                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1467                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1468                                            reg);
1469                 if (ret < 0)
1470                         return ret;
1471         } else if (mv88e6xxx_num_databases(chip) == 256) {
1472                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1473                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1474                  */
1475                 op |= (entry->fid & 0xf0) << 8;
1476                 op |= entry->fid & 0xf;
1477         }
1478
1479         reg = GLOBAL_VTU_VID_VALID;
1480 loadpurge:
1481         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1482         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1483         if (ret < 0)
1484                 return ret;
1485
1486         return _mv88e6xxx_vtu_cmd(chip, op);
1487 }
1488
1489 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1490                                   struct mv88e6xxx_vtu_stu_entry *entry)
1491 {
1492         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1493         int ret;
1494
1495         ret = _mv88e6xxx_vtu_wait(chip);
1496         if (ret < 0)
1497                 return ret;
1498
1499         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1500                                    sid & GLOBAL_VTU_SID_MASK);
1501         if (ret < 0)
1502                 return ret;
1503
1504         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1505         if (ret < 0)
1506                 return ret;
1507
1508         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1509         if (ret < 0)
1510                 return ret;
1511
1512         next.sid = ret & GLOBAL_VTU_SID_MASK;
1513
1514         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1515         if (ret < 0)
1516                 return ret;
1517
1518         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1519
1520         if (next.valid) {
1521                 ret = mv88e6xxx_stu_data_read(chip, &next);
1522                 if (ret < 0)
1523                         return ret;
1524         }
1525
1526         *entry = next;
1527         return 0;
1528 }
1529
1530 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1531                                     struct mv88e6xxx_vtu_stu_entry *entry)
1532 {
1533         u16 reg = 0;
1534         int ret;
1535
1536         ret = _mv88e6xxx_vtu_wait(chip);
1537         if (ret < 0)
1538                 return ret;
1539
1540         if (!entry->valid)
1541                 goto loadpurge;
1542
1543         /* Write port states */
1544         ret = mv88e6xxx_stu_data_write(chip, entry);
1545         if (ret < 0)
1546                 return ret;
1547
1548         reg = GLOBAL_VTU_VID_VALID;
1549 loadpurge:
1550         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1551         if (ret < 0)
1552                 return ret;
1553
1554         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1555         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1556         if (ret < 0)
1557                 return ret;
1558
1559         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1560 }
1561
1562 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1563                                u16 *new, u16 *old)
1564 {
1565         struct dsa_switch *ds = chip->ds;
1566         u16 upper_mask;
1567         u16 fid;
1568         int ret;
1569
1570         if (mv88e6xxx_num_databases(chip) == 4096)
1571                 upper_mask = 0xff;
1572         else if (mv88e6xxx_num_databases(chip) == 256)
1573                 upper_mask = 0xf;
1574         else
1575                 return -EOPNOTSUPP;
1576
1577         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1578         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1579         if (ret < 0)
1580                 return ret;
1581
1582         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1583
1584         if (new) {
1585                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1586                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1587
1588                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1589                                            ret);
1590                 if (ret < 0)
1591                         return ret;
1592         }
1593
1594         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1595         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1596         if (ret < 0)
1597                 return ret;
1598
1599         fid |= (ret & upper_mask) << 4;
1600
1601         if (new) {
1602                 ret &= ~upper_mask;
1603                 ret |= (*new >> 4) & upper_mask;
1604
1605                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1606                                            ret);
1607                 if (ret < 0)
1608                         return ret;
1609
1610                 netdev_dbg(ds->ports[port].netdev,
1611                            "FID %d (was %d)\n", *new, fid);
1612         }
1613
1614         if (old)
1615                 *old = fid;
1616
1617         return 0;
1618 }
1619
1620 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1621                                    int port, u16 *fid)
1622 {
1623         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1624 }
1625
1626 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1627                                    int port, u16 fid)
1628 {
1629         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1630 }
1631
1632 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1633 {
1634         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1635         struct mv88e6xxx_vtu_stu_entry vlan;
1636         int i, err;
1637
1638         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1639
1640         /* Set every FID bit used by the (un)bridged ports */
1641         for (i = 0; i < chip->info->num_ports; ++i) {
1642                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1643                 if (err)
1644                         return err;
1645
1646                 set_bit(*fid, fid_bitmap);
1647         }
1648
1649         /* Set every FID bit used by the VLAN entries */
1650         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1651         if (err)
1652                 return err;
1653
1654         do {
1655                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1656                 if (err)
1657                         return err;
1658
1659                 if (!vlan.valid)
1660                         break;
1661
1662                 set_bit(vlan.fid, fid_bitmap);
1663         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1664
1665         /* The reset value 0x000 is used to indicate that multiple address
1666          * databases are not needed. Return the next positive available.
1667          */
1668         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1669         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1670                 return -ENOSPC;
1671
1672         /* Clear the database */
1673         return _mv88e6xxx_atu_flush(chip, *fid, true);
1674 }
1675
1676 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1677                               struct mv88e6xxx_vtu_stu_entry *entry)
1678 {
1679         struct dsa_switch *ds = chip->ds;
1680         struct mv88e6xxx_vtu_stu_entry vlan = {
1681                 .valid = true,
1682                 .vid = vid,
1683         };
1684         int i, err;
1685
1686         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1687         if (err)
1688                 return err;
1689
1690         /* exclude all ports except the CPU and DSA ports */
1691         for (i = 0; i < chip->info->num_ports; ++i)
1692                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1693                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1694                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1695
1696         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1697             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1698                 struct mv88e6xxx_vtu_stu_entry vstp;
1699
1700                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1701                  * implemented, only one STU entry is needed to cover all VTU
1702                  * entries. Thus, validate the SID 0.
1703                  */
1704                 vlan.sid = 0;
1705                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1706                 if (err)
1707                         return err;
1708
1709                 if (vstp.sid != vlan.sid || !vstp.valid) {
1710                         memset(&vstp, 0, sizeof(vstp));
1711                         vstp.valid = true;
1712                         vstp.sid = vlan.sid;
1713
1714                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1715                         if (err)
1716                                 return err;
1717                 }
1718         }
1719
1720         *entry = vlan;
1721         return 0;
1722 }
1723
1724 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1725                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1726 {
1727         int err;
1728
1729         if (!vid)
1730                 return -EINVAL;
1731
1732         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1733         if (err)
1734                 return err;
1735
1736         err = _mv88e6xxx_vtu_getnext(chip, entry);
1737         if (err)
1738                 return err;
1739
1740         if (entry->vid != vid || !entry->valid) {
1741                 if (!creat)
1742                         return -EOPNOTSUPP;
1743                 /* -ENOENT would've been more appropriate, but switchdev expects
1744                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1745                  */
1746
1747                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1748         }
1749
1750         return err;
1751 }
1752
1753 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1754                                         u16 vid_begin, u16 vid_end)
1755 {
1756         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1757         struct mv88e6xxx_vtu_stu_entry vlan;
1758         int i, err;
1759
1760         if (!vid_begin)
1761                 return -EOPNOTSUPP;
1762
1763         mutex_lock(&chip->reg_lock);
1764
1765         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1766         if (err)
1767                 goto unlock;
1768
1769         do {
1770                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1771                 if (err)
1772                         goto unlock;
1773
1774                 if (!vlan.valid)
1775                         break;
1776
1777                 if (vlan.vid > vid_end)
1778                         break;
1779
1780                 for (i = 0; i < chip->info->num_ports; ++i) {
1781                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1782                                 continue;
1783
1784                         if (vlan.data[i] ==
1785                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1786                                 continue;
1787
1788                         if (chip->ports[i].bridge_dev ==
1789                             chip->ports[port].bridge_dev)
1790                                 break; /* same bridge, check next VLAN */
1791
1792                         netdev_warn(ds->ports[port].netdev,
1793                                     "hardware VLAN %d already used by %s\n",
1794                                     vlan.vid,
1795                                     netdev_name(chip->ports[i].bridge_dev));
1796                         err = -EOPNOTSUPP;
1797                         goto unlock;
1798                 }
1799         } while (vlan.vid < vid_end);
1800
1801 unlock:
1802         mutex_unlock(&chip->reg_lock);
1803
1804         return err;
1805 }
1806
1807 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1808         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1809         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1810         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1811         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1812 };
1813
1814 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1815                                          bool vlan_filtering)
1816 {
1817         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1818         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1819                 PORT_CONTROL_2_8021Q_DISABLED;
1820         int ret;
1821
1822         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1823                 return -EOPNOTSUPP;
1824
1825         mutex_lock(&chip->reg_lock);
1826
1827         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
1828         if (ret < 0)
1829                 goto unlock;
1830
1831         old = ret & PORT_CONTROL_2_8021Q_MASK;
1832
1833         if (new != old) {
1834                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1835                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1836
1837                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
1838                                            ret);
1839                 if (ret < 0)
1840                         goto unlock;
1841
1842                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1843                            mv88e6xxx_port_8021q_mode_names[new],
1844                            mv88e6xxx_port_8021q_mode_names[old]);
1845         }
1846
1847         ret = 0;
1848 unlock:
1849         mutex_unlock(&chip->reg_lock);
1850
1851         return ret;
1852 }
1853
1854 static int
1855 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1856                             const struct switchdev_obj_port_vlan *vlan,
1857                             struct switchdev_trans *trans)
1858 {
1859         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1860         int err;
1861
1862         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1863                 return -EOPNOTSUPP;
1864
1865         /* If the requested port doesn't belong to the same bridge as the VLAN
1866          * members, do not support it (yet) and fallback to software VLAN.
1867          */
1868         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1869                                            vlan->vid_end);
1870         if (err)
1871                 return err;
1872
1873         /* We don't need any dynamic resource from the kernel (yet),
1874          * so skip the prepare phase.
1875          */
1876         return 0;
1877 }
1878
1879 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1880                                     u16 vid, bool untagged)
1881 {
1882         struct mv88e6xxx_vtu_stu_entry vlan;
1883         int err;
1884
1885         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1886         if (err)
1887                 return err;
1888
1889         vlan.data[port] = untagged ?
1890                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1891                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1892
1893         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1894 }
1895
1896 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1897                                     const struct switchdev_obj_port_vlan *vlan,
1898                                     struct switchdev_trans *trans)
1899 {
1900         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1901         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1902         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1903         u16 vid;
1904
1905         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1906                 return;
1907
1908         mutex_lock(&chip->reg_lock);
1909
1910         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1911                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1912                         netdev_err(ds->ports[port].netdev,
1913                                    "failed to add VLAN %d%c\n",
1914                                    vid, untagged ? 'u' : 't');
1915
1916         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1917                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1918                            vlan->vid_end);
1919
1920         mutex_unlock(&chip->reg_lock);
1921 }
1922
1923 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1924                                     int port, u16 vid)
1925 {
1926         struct dsa_switch *ds = chip->ds;
1927         struct mv88e6xxx_vtu_stu_entry vlan;
1928         int i, err;
1929
1930         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1931         if (err)
1932                 return err;
1933
1934         /* Tell switchdev if this VLAN is handled in software */
1935         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1936                 return -EOPNOTSUPP;
1937
1938         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1939
1940         /* keep the VLAN unless all ports are excluded */
1941         vlan.valid = false;
1942         for (i = 0; i < chip->info->num_ports; ++i) {
1943                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1944                         continue;
1945
1946                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1947                         vlan.valid = true;
1948                         break;
1949                 }
1950         }
1951
1952         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1953         if (err)
1954                 return err;
1955
1956         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
1957 }
1958
1959 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1960                                    const struct switchdev_obj_port_vlan *vlan)
1961 {
1962         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1963         u16 pvid, vid;
1964         int err = 0;
1965
1966         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1967                 return -EOPNOTSUPP;
1968
1969         mutex_lock(&chip->reg_lock);
1970
1971         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1972         if (err)
1973                 goto unlock;
1974
1975         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1976                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1977                 if (err)
1978                         goto unlock;
1979
1980                 if (vid == pvid) {
1981                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
1982                         if (err)
1983                                 goto unlock;
1984                 }
1985         }
1986
1987 unlock:
1988         mutex_unlock(&chip->reg_lock);
1989
1990         return err;
1991 }
1992
1993 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
1994                                     const unsigned char *addr)
1995 {
1996         int i, ret;
1997
1998         for (i = 0; i < 3; i++) {
1999                 ret = _mv88e6xxx_reg_write(
2000                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2001                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2002                 if (ret < 0)
2003                         return ret;
2004         }
2005
2006         return 0;
2007 }
2008
2009 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2010                                    unsigned char *addr)
2011 {
2012         int i, ret;
2013
2014         for (i = 0; i < 3; i++) {
2015                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2016                                           GLOBAL_ATU_MAC_01 + i);
2017                 if (ret < 0)
2018                         return ret;
2019                 addr[i * 2] = ret >> 8;
2020                 addr[i * 2 + 1] = ret & 0xff;
2021         }
2022
2023         return 0;
2024 }
2025
2026 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2027                                struct mv88e6xxx_atu_entry *entry)
2028 {
2029         int ret;
2030
2031         ret = _mv88e6xxx_atu_wait(chip);
2032         if (ret < 0)
2033                 return ret;
2034
2035         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2036         if (ret < 0)
2037                 return ret;
2038
2039         ret = _mv88e6xxx_atu_data_write(chip, entry);
2040         if (ret < 0)
2041                 return ret;
2042
2043         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2044 }
2045
2046 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2047                                     const unsigned char *addr, u16 vid,
2048                                     u8 state)
2049 {
2050         struct mv88e6xxx_atu_entry entry = { 0 };
2051         struct mv88e6xxx_vtu_stu_entry vlan;
2052         int err;
2053
2054         /* Null VLAN ID corresponds to the port private database */
2055         if (vid == 0)
2056                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2057         else
2058                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2059         if (err)
2060                 return err;
2061
2062         entry.fid = vlan.fid;
2063         entry.state = state;
2064         ether_addr_copy(entry.mac, addr);
2065         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2066                 entry.trunk = false;
2067                 entry.portv_trunkid = BIT(port);
2068         }
2069
2070         return _mv88e6xxx_atu_load(chip, &entry);
2071 }
2072
2073 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2074                                       const struct switchdev_obj_port_fdb *fdb,
2075                                       struct switchdev_trans *trans)
2076 {
2077         /* We don't need any dynamic resource from the kernel (yet),
2078          * so skip the prepare phase.
2079          */
2080         return 0;
2081 }
2082
2083 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2084                                    const struct switchdev_obj_port_fdb *fdb,
2085                                    struct switchdev_trans *trans)
2086 {
2087         int state = is_multicast_ether_addr(fdb->addr) ?
2088                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2089                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2090         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2091
2092         mutex_lock(&chip->reg_lock);
2093         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2094                 netdev_err(ds->ports[port].netdev,
2095                            "failed to load MAC address\n");
2096         mutex_unlock(&chip->reg_lock);
2097 }
2098
2099 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2100                                   const struct switchdev_obj_port_fdb *fdb)
2101 {
2102         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2103         int ret;
2104
2105         mutex_lock(&chip->reg_lock);
2106         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2107                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2108         mutex_unlock(&chip->reg_lock);
2109
2110         return ret;
2111 }
2112
2113 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2114                                   struct mv88e6xxx_atu_entry *entry)
2115 {
2116         struct mv88e6xxx_atu_entry next = { 0 };
2117         int ret;
2118
2119         next.fid = fid;
2120
2121         ret = _mv88e6xxx_atu_wait(chip);
2122         if (ret < 0)
2123                 return ret;
2124
2125         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2126         if (ret < 0)
2127                 return ret;
2128
2129         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2130         if (ret < 0)
2131                 return ret;
2132
2133         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2134         if (ret < 0)
2135                 return ret;
2136
2137         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2138         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2139                 unsigned int mask, shift;
2140
2141                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2142                         next.trunk = true;
2143                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2144                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2145                 } else {
2146                         next.trunk = false;
2147                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2148                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2149                 }
2150
2151                 next.portv_trunkid = (ret & mask) >> shift;
2152         }
2153
2154         *entry = next;
2155         return 0;
2156 }
2157
2158 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2159                                         u16 fid, u16 vid, int port,
2160                                         struct switchdev_obj_port_fdb *fdb,
2161                                         int (*cb)(struct switchdev_obj *obj))
2162 {
2163         struct mv88e6xxx_atu_entry addr = {
2164                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2165         };
2166         int err;
2167
2168         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2169         if (err)
2170                 return err;
2171
2172         do {
2173                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2174                 if (err)
2175                         break;
2176
2177                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2178                         break;
2179
2180                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2181                         bool is_static = addr.state ==
2182                                 (is_multicast_ether_addr(addr.mac) ?
2183                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2184                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2185
2186                         fdb->vid = vid;
2187                         ether_addr_copy(fdb->addr, addr.mac);
2188                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2189
2190                         err = cb(&fdb->obj);
2191                         if (err)
2192                                 break;
2193                 }
2194         } while (!is_broadcast_ether_addr(addr.mac));
2195
2196         return err;
2197 }
2198
2199 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2200                                    struct switchdev_obj_port_fdb *fdb,
2201                                    int (*cb)(struct switchdev_obj *obj))
2202 {
2203         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2204         struct mv88e6xxx_vtu_stu_entry vlan = {
2205                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2206         };
2207         u16 fid;
2208         int err;
2209
2210         mutex_lock(&chip->reg_lock);
2211
2212         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2213         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2214         if (err)
2215                 goto unlock;
2216
2217         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2218         if (err)
2219                 goto unlock;
2220
2221         /* Dump VLANs' Filtering Information Databases */
2222         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2223         if (err)
2224                 goto unlock;
2225
2226         do {
2227                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2228                 if (err)
2229                         break;
2230
2231                 if (!vlan.valid)
2232                         break;
2233
2234                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2235                                                    port, fdb, cb);
2236                 if (err)
2237                         break;
2238         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2239
2240 unlock:
2241         mutex_unlock(&chip->reg_lock);
2242
2243         return err;
2244 }
2245
2246 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2247                                       struct net_device *bridge)
2248 {
2249         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2250         int i, err = 0;
2251
2252         mutex_lock(&chip->reg_lock);
2253
2254         /* Assign the bridge and remap each port's VLANTable */
2255         chip->ports[port].bridge_dev = bridge;
2256
2257         for (i = 0; i < chip->info->num_ports; ++i) {
2258                 if (chip->ports[i].bridge_dev == bridge) {
2259                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2260                         if (err)
2261                                 break;
2262                 }
2263         }
2264
2265         mutex_unlock(&chip->reg_lock);
2266
2267         return err;
2268 }
2269
2270 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2271 {
2272         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2273         struct net_device *bridge = chip->ports[port].bridge_dev;
2274         int i;
2275
2276         mutex_lock(&chip->reg_lock);
2277
2278         /* Unassign the bridge and remap each port's VLANTable */
2279         chip->ports[port].bridge_dev = NULL;
2280
2281         for (i = 0; i < chip->info->num_ports; ++i)
2282                 if (i == port || chip->ports[i].bridge_dev == bridge)
2283                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2284                                 netdev_warn(ds->ports[i].netdev,
2285                                             "failed to remap\n");
2286
2287         mutex_unlock(&chip->reg_lock);
2288 }
2289
2290 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2291                                       int port, int page, int reg, int val)
2292 {
2293         int ret;
2294
2295         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2296         if (ret < 0)
2297                 goto restore_page_0;
2298
2299         ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2300 restore_page_0:
2301         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2302
2303         return ret;
2304 }
2305
2306 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2307                                      int port, int page, int reg)
2308 {
2309         int ret;
2310
2311         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2312         if (ret < 0)
2313                 goto restore_page_0;
2314
2315         ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2316 restore_page_0:
2317         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2318
2319         return ret;
2320 }
2321
2322 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2323 {
2324         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2325         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2326         struct gpio_desc *gpiod = chip->reset;
2327         unsigned long timeout;
2328         int ret;
2329         int i;
2330
2331         /* Set all ports to the disabled state. */
2332         for (i = 0; i < chip->info->num_ports; i++) {
2333                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2334                 if (ret < 0)
2335                         return ret;
2336
2337                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2338                                            ret & 0xfffc);
2339                 if (ret)
2340                         return ret;
2341         }
2342
2343         /* Wait for transmit queues to drain. */
2344         usleep_range(2000, 4000);
2345
2346         /* If there is a gpio connected to the reset pin, toggle it */
2347         if (gpiod) {
2348                 gpiod_set_value_cansleep(gpiod, 1);
2349                 usleep_range(10000, 20000);
2350                 gpiod_set_value_cansleep(gpiod, 0);
2351                 usleep_range(10000, 20000);
2352         }
2353
2354         /* Reset the switch. Keep the PPU active if requested. The PPU
2355          * needs to be active to support indirect phy register access
2356          * through global registers 0x18 and 0x19.
2357          */
2358         if (ppu_active)
2359                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2360         else
2361                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2362         if (ret)
2363                 return ret;
2364
2365         /* Wait up to one second for reset to complete. */
2366         timeout = jiffies + 1 * HZ;
2367         while (time_before(jiffies, timeout)) {
2368                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2369                 if (ret < 0)
2370                         return ret;
2371
2372                 if ((ret & is_reset) == is_reset)
2373                         break;
2374                 usleep_range(1000, 2000);
2375         }
2376         if (time_after(jiffies, timeout))
2377                 ret = -ETIMEDOUT;
2378         else
2379                 ret = 0;
2380
2381         return ret;
2382 }
2383
2384 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2385 {
2386         int ret;
2387
2388         ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2389                                         PAGE_FIBER_SERDES, MII_BMCR);
2390         if (ret < 0)
2391                 return ret;
2392
2393         if (ret & BMCR_PDOWN) {
2394                 ret &= ~BMCR_PDOWN;
2395                 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2396                                                  PAGE_FIBER_SERDES, MII_BMCR,
2397                                                  ret);
2398         }
2399
2400         return ret;
2401 }
2402
2403 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port,
2404                                int reg, u16 *val)
2405 {
2406         int addr = chip->info->port_base_addr + port;
2407
2408         if (port >= chip->info->num_ports)
2409                 return -EINVAL;
2410
2411         return mv88e6xxx_read(chip, addr, reg, val);
2412 }
2413
2414 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2415 {
2416         struct dsa_switch *ds = chip->ds;
2417         int ret;
2418         u16 reg;
2419
2420         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2421             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2422             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2423             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2424                 /* MAC Forcing register: don't force link, speed,
2425                  * duplex or flow control state to any particular
2426                  * values on physical ports, but force the CPU port
2427                  * and all DSA ports to their maximum bandwidth and
2428                  * full duplex.
2429                  */
2430                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2431                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2432                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2433                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2434                                 PORT_PCS_CTRL_LINK_UP |
2435                                 PORT_PCS_CTRL_DUPLEX_FULL |
2436                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2437                         if (mv88e6xxx_6065_family(chip))
2438                                 reg |= PORT_PCS_CTRL_100;
2439                         else
2440                                 reg |= PORT_PCS_CTRL_1000;
2441                 } else {
2442                         reg |= PORT_PCS_CTRL_UNFORCED;
2443                 }
2444
2445                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2446                                            PORT_PCS_CTRL, reg);
2447                 if (ret)
2448                         return ret;
2449         }
2450
2451         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2452          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2453          * tunneling, determine priority by looking at 802.1p and IP
2454          * priority fields (IP prio has precedence), and set STP state
2455          * to Forwarding.
2456          *
2457          * If this is the CPU link, use DSA or EDSA tagging depending
2458          * on which tagging mode was configured.
2459          *
2460          * If this is a link to another switch, use DSA tagging mode.
2461          *
2462          * If this is the upstream port for this switch, enable
2463          * forwarding of unknown unicasts and multicasts.
2464          */
2465         reg = 0;
2466         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2467             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2468             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2469             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2470                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2471                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2472                 PORT_CONTROL_STATE_FORWARDING;
2473         if (dsa_is_cpu_port(ds, port)) {
2474                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2475                         reg |= PORT_CONTROL_DSA_TAG;
2476                 if (mv88e6xxx_6352_family(chip) ||
2477                     mv88e6xxx_6351_family(chip) ||
2478                     mv88e6xxx_6165_family(chip) ||
2479                     mv88e6xxx_6097_family(chip) ||
2480                     mv88e6xxx_6320_family(chip)) {
2481                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2482                                 PORT_CONTROL_FORWARD_UNKNOWN |
2483                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2484                 }
2485
2486                 if (mv88e6xxx_6352_family(chip) ||
2487                     mv88e6xxx_6351_family(chip) ||
2488                     mv88e6xxx_6165_family(chip) ||
2489                     mv88e6xxx_6097_family(chip) ||
2490                     mv88e6xxx_6095_family(chip) ||
2491                     mv88e6xxx_6065_family(chip) ||
2492                     mv88e6xxx_6185_family(chip) ||
2493                     mv88e6xxx_6320_family(chip)) {
2494                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2495                 }
2496         }
2497         if (dsa_is_dsa_port(ds, port)) {
2498                 if (mv88e6xxx_6095_family(chip) ||
2499                     mv88e6xxx_6185_family(chip))
2500                         reg |= PORT_CONTROL_DSA_TAG;
2501                 if (mv88e6xxx_6352_family(chip) ||
2502                     mv88e6xxx_6351_family(chip) ||
2503                     mv88e6xxx_6165_family(chip) ||
2504                     mv88e6xxx_6097_family(chip) ||
2505                     mv88e6xxx_6320_family(chip)) {
2506                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2507                 }
2508
2509                 if (port == dsa_upstream_port(ds))
2510                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2511                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2512         }
2513         if (reg) {
2514                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2515                                            PORT_CONTROL, reg);
2516                 if (ret)
2517                         return ret;
2518         }
2519
2520         /* If this port is connected to a SerDes, make sure the SerDes is not
2521          * powered down.
2522          */
2523         if (mv88e6xxx_6352_family(chip)) {
2524                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2525                 if (ret < 0)
2526                         return ret;
2527                 ret &= PORT_STATUS_CMODE_MASK;
2528                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2529                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2530                     (ret == PORT_STATUS_CMODE_SGMII)) {
2531                         ret = mv88e6xxx_power_on_serdes(chip);
2532                         if (ret < 0)
2533                                 return ret;
2534                 }
2535         }
2536
2537         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2538          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2539          * untagged frames on this port, do a destination address lookup on all
2540          * received packets as usual, disable ARP mirroring and don't send a
2541          * copy of all transmitted/received frames on this port to the CPU.
2542          */
2543         reg = 0;
2544         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2545             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2546             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2547             mv88e6xxx_6185_family(chip))
2548                 reg = PORT_CONTROL_2_MAP_DA;
2549
2550         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2551             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2552                 reg |= PORT_CONTROL_2_JUMBO_10240;
2553
2554         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2555                 /* Set the upstream port this port should use */
2556                 reg |= dsa_upstream_port(ds);
2557                 /* enable forwarding of unknown multicast addresses to
2558                  * the upstream port
2559                  */
2560                 if (port == dsa_upstream_port(ds))
2561                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2562         }
2563
2564         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2565
2566         if (reg) {
2567                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2568                                            PORT_CONTROL_2, reg);
2569                 if (ret)
2570                         return ret;
2571         }
2572
2573         /* Port Association Vector: when learning source addresses
2574          * of packets, add the address to the address database using
2575          * a port bitmap that has only the bit for this port set and
2576          * the other bits clear.
2577          */
2578         reg = 1 << port;
2579         /* Disable learning for CPU port */
2580         if (dsa_is_cpu_port(ds, port))
2581                 reg = 0;
2582
2583         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2584                                    reg);
2585         if (ret)
2586                 return ret;
2587
2588         /* Egress rate control 2: disable egress rate control. */
2589         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2590                                    0x0000);
2591         if (ret)
2592                 return ret;
2593
2594         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2595             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2596             mv88e6xxx_6320_family(chip)) {
2597                 /* Do not limit the period of time that this port can
2598                  * be paused for by the remote end or the period of
2599                  * time that this port can pause the remote end.
2600                  */
2601                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2602                                            PORT_PAUSE_CTRL, 0x0000);
2603                 if (ret)
2604                         return ret;
2605
2606                 /* Port ATU control: disable limiting the number of
2607                  * address database entries that this port is allowed
2608                  * to use.
2609                  */
2610                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2611                                            PORT_ATU_CONTROL, 0x0000);
2612                 /* Priority Override: disable DA, SA and VTU priority
2613                  * override.
2614                  */
2615                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2616                                            PORT_PRI_OVERRIDE, 0x0000);
2617                 if (ret)
2618                         return ret;
2619
2620                 /* Port Ethertype: use the Ethertype DSA Ethertype
2621                  * value.
2622                  */
2623                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2624                                            PORT_ETH_TYPE, ETH_P_EDSA);
2625                 if (ret)
2626                         return ret;
2627                 /* Tag Remap: use an identity 802.1p prio -> switch
2628                  * prio mapping.
2629                  */
2630                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2631                                            PORT_TAG_REGMAP_0123, 0x3210);
2632                 if (ret)
2633                         return ret;
2634
2635                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2636                  * prio mapping.
2637                  */
2638                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2639                                            PORT_TAG_REGMAP_4567, 0x7654);
2640                 if (ret)
2641                         return ret;
2642         }
2643
2644         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2645             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2646             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2647             mv88e6xxx_6320_family(chip)) {
2648                 /* Rate Control: disable ingress rate limiting. */
2649                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2650                                            PORT_RATE_CONTROL, 0x0001);
2651                 if (ret)
2652                         return ret;
2653         }
2654
2655         /* Port Control 1: disable trunking, disable sending
2656          * learning messages to this port.
2657          */
2658         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2659                                    0x0000);
2660         if (ret)
2661                 return ret;
2662
2663         /* Port based VLAN map: give each port the same default address
2664          * database, and allow bidirectional communication between the
2665          * CPU and DSA port(s), and the other ports.
2666          */
2667         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2668         if (ret)
2669                 return ret;
2670
2671         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2672         if (ret)
2673                 return ret;
2674
2675         /* Default VLAN ID and priority: don't set a default VLAN
2676          * ID, and set the default packet priority to zero.
2677          */
2678         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2679                                    0x0000);
2680         if (ret)
2681                 return ret;
2682
2683         return 0;
2684 }
2685
2686 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2687 {
2688         int err;
2689
2690         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2691                               (addr[0] << 8) | addr[1]);
2692         if (err)
2693                 return err;
2694
2695         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2696                               (addr[2] << 8) | addr[3]);
2697         if (err)
2698                 return err;
2699
2700         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2701                                (addr[4] << 8) | addr[5]);
2702 }
2703
2704 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2705                                      unsigned int msecs)
2706 {
2707         const unsigned int coeff = chip->info->age_time_coeff;
2708         const unsigned int min = 0x01 * coeff;
2709         const unsigned int max = 0xff * coeff;
2710         u8 age_time;
2711         u16 val;
2712         int err;
2713
2714         if (msecs < min || msecs > max)
2715                 return -ERANGE;
2716
2717         /* Round to nearest multiple of coeff */
2718         age_time = (msecs + coeff / 2) / coeff;
2719
2720         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2721         if (err)
2722                 return err;
2723
2724         /* AgeTime is 11:4 bits */
2725         val &= ~0xff0;
2726         val |= age_time << 4;
2727
2728         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2729 }
2730
2731 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2732                                      unsigned int ageing_time)
2733 {
2734         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2735         int err;
2736
2737         mutex_lock(&chip->reg_lock);
2738         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2739         mutex_unlock(&chip->reg_lock);
2740
2741         return err;
2742 }
2743
2744 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2745 {
2746         struct dsa_switch *ds = chip->ds;
2747         u32 upstream_port = dsa_upstream_port(ds);
2748         u16 reg;
2749         int err;
2750
2751         /* Enable the PHY Polling Unit if present, don't discard any packets,
2752          * and mask all interrupt sources.
2753          */
2754         reg = 0;
2755         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2756             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2757                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2758
2759         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2760         if (err)
2761                 return err;
2762
2763         /* Configure the upstream port, and configure it as the port to which
2764          * ingress and egress and ARP monitor frames are to be sent.
2765          */
2766         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2767                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2768                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2769         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2770                                    reg);
2771         if (err)
2772                 return err;
2773
2774         /* Disable remote management, and set the switch's DSA device number. */
2775         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2776                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2777                                    (ds->index & 0x1f));
2778         if (err)
2779                 return err;
2780
2781         /* Clear all the VTU and STU entries */
2782         err = _mv88e6xxx_vtu_stu_flush(chip);
2783         if (err < 0)
2784                 return err;
2785
2786         /* Set the default address aging time to 5 minutes, and
2787          * enable address learn messages to be sent to all message
2788          * ports.
2789          */
2790         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2791                               GLOBAL_ATU_CONTROL_LEARN2ALL);
2792         if (err)
2793                 return err;
2794
2795         err = mv88e6xxx_g1_set_age_time(chip, 300000);
2796         if (err)
2797                 return err;
2798
2799         /* Clear all ATU entries */
2800         err = _mv88e6xxx_atu_flush(chip, 0, true);
2801         if (err)
2802                 return err;
2803
2804         /* Configure the IP ToS mapping registers. */
2805         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2806         if (err)
2807                 return err;
2808         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2809         if (err)
2810                 return err;
2811         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2812         if (err)
2813                 return err;
2814         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2815         if (err)
2816                 return err;
2817         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2818         if (err)
2819                 return err;
2820         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2821         if (err)
2822                 return err;
2823         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2824         if (err)
2825                 return err;
2826         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2827         if (err)
2828                 return err;
2829
2830         /* Configure the IEEE 802.1p priority mapping register. */
2831         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2832         if (err)
2833                 return err;
2834
2835         /* Clear the statistics counters for all ports */
2836         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2837                                    GLOBAL_STATS_OP_FLUSH_ALL);
2838         if (err)
2839                 return err;
2840
2841         /* Wait for the flush to complete. */
2842         err = _mv88e6xxx_stats_wait(chip);
2843         if (err)
2844                 return err;
2845
2846         return 0;
2847 }
2848
2849 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
2850                                              int target, int port)
2851 {
2852         u16 val = (target << 8) | (port & 0xf);
2853
2854         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
2855 }
2856
2857 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
2858 {
2859         int target, port;
2860         int err;
2861
2862         /* Initialize the routing port to the 32 possible target devices */
2863         for (target = 0; target < 32; ++target) {
2864                 port = 0xf;
2865
2866                 if (target < DSA_MAX_SWITCHES) {
2867                         port = chip->ds->rtable[target];
2868                         if (port == DSA_RTABLE_NONE)
2869                                 port = 0xf;
2870                 }
2871
2872                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
2873                 if (err)
2874                         break;
2875         }
2876
2877         return err;
2878 }
2879
2880 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
2881                                          bool hask, u16 mask)
2882 {
2883         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2884         u16 val = (num << 12) | (mask & port_mask);
2885
2886         if (hask)
2887                 val |= GLOBAL2_TRUNK_MASK_HASK;
2888
2889         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
2890 }
2891
2892 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
2893                                             u16 map)
2894 {
2895         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2896         u16 val = (id << 11) | (map & port_mask);
2897
2898         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
2899 }
2900
2901 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
2902 {
2903         const u16 port_mask = BIT(chip->info->num_ports) - 1;
2904         int i, err;
2905
2906         /* Clear all eight possible Trunk Mask vectors */
2907         for (i = 0; i < 8; ++i) {
2908                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
2909                 if (err)
2910                         return err;
2911         }
2912
2913         /* Clear all sixteen possible Trunk ID routing vectors */
2914         for (i = 0; i < 16; ++i) {
2915                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
2916                 if (err)
2917                         return err;
2918         }
2919
2920         return 0;
2921 }
2922
2923 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
2924 {
2925         int port, err;
2926
2927         /* Init all Ingress Rate Limit resources of all ports */
2928         for (port = 0; port < chip->info->num_ports; ++port) {
2929                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
2930                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2931                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
2932                                       (port << 8));
2933                 if (err)
2934                         break;
2935
2936                 /* Wait for the operation to complete */
2937                 err = mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
2938                                      GLOBAL2_IRL_CMD_BUSY);
2939                 if (err)
2940                         break;
2941         }
2942
2943         return err;
2944 }
2945
2946 /* Indirect write to the Switch MAC/WoL/WoF register */
2947 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
2948                                          unsigned int pointer, u8 data)
2949 {
2950         u16 val = (pointer << 8) | data;
2951
2952         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
2953 }
2954
2955 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2956 {
2957         int i, err;
2958
2959         for (i = 0; i < 6; i++) {
2960                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
2961                 if (err)
2962                         break;
2963         }
2964
2965         return err;
2966 }
2967
2968 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
2969                                   u8 data)
2970 {
2971         u16 val = (pointer << 8) | (data & 0x7);
2972
2973         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
2974 }
2975
2976 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
2977 {
2978         int i, err;
2979
2980         /* Clear all sixteen possible Priority Override entries */
2981         for (i = 0; i < 16; i++) {
2982                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
2983                 if (err)
2984                         break;
2985         }
2986
2987         return err;
2988 }
2989
2990 static int mv88e6xxx_g2_eeprom_wait(struct mv88e6xxx_chip *chip)
2991 {
2992         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD,
2993                               GLOBAL2_EEPROM_CMD_BUSY |
2994                               GLOBAL2_EEPROM_CMD_RUNNING);
2995 }
2996
2997 static int mv88e6xxx_g2_eeprom_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
2998 {
2999         int err;
3000
3001         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, cmd);
3002         if (err)
3003                 return err;
3004
3005         return mv88e6xxx_g2_eeprom_wait(chip);
3006 }
3007
3008 static int mv88e6xxx_g2_eeprom_read16(struct mv88e6xxx_chip *chip,
3009                                       u8 addr, u16 *data)
3010 {
3011         u16 cmd = GLOBAL2_EEPROM_CMD_OP_READ | addr;
3012         int err;
3013
3014         err = mv88e6xxx_g2_eeprom_wait(chip);
3015         if (err)
3016                 return err;
3017
3018         err = mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3019         if (err)
3020                 return err;
3021
3022         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3023 }
3024
3025 static int mv88e6xxx_g2_eeprom_write16(struct mv88e6xxx_chip *chip,
3026                                        u8 addr, u16 data)
3027 {
3028         u16 cmd = GLOBAL2_EEPROM_CMD_OP_WRITE | addr;
3029         int err;
3030
3031         err = mv88e6xxx_g2_eeprom_wait(chip);
3032         if (err)
3033                 return err;
3034
3035         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
3036         if (err)
3037                 return err;
3038
3039         return mv88e6xxx_g2_eeprom_cmd(chip, cmd);
3040 }
3041
3042 static int mv88e6xxx_g2_smi_phy_wait(struct mv88e6xxx_chip *chip)
3043 {
3044         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD,
3045                               GLOBAL2_SMI_PHY_CMD_BUSY);
3046 }
3047
3048 static int mv88e6xxx_g2_smi_phy_cmd(struct mv88e6xxx_chip *chip, u16 cmd)
3049 {
3050         int err;
3051
3052         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_CMD, cmd);
3053         if (err)
3054                 return err;
3055
3056         return mv88e6xxx_g2_smi_phy_wait(chip);
3057 }
3058
3059 static int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip, int addr,
3060                                      int reg, u16 *val)
3061 {
3062         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_READ_DATA | (addr << 5) | reg;
3063         int err;
3064
3065         err = mv88e6xxx_g2_smi_phy_wait(chip);
3066         if (err)
3067                 return err;
3068
3069         err = mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3070         if (err)
3071                 return err;
3072
3073         return mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3074 }
3075
3076 static int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip, int addr,
3077                                       int reg, u16 val)
3078 {
3079         u16 cmd = GLOBAL2_SMI_PHY_CMD_OP_22_WRITE_DATA | (addr << 5) | reg;
3080         int err;
3081
3082         err = mv88e6xxx_g2_smi_phy_wait(chip);
3083         if (err)
3084                 return err;
3085
3086         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SMI_PHY_DATA, val);
3087         if (err)
3088                 return err;
3089
3090         return mv88e6xxx_g2_smi_phy_cmd(chip, cmd);
3091 }
3092
3093 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3094 {
3095         u16 reg;
3096         int err;
3097
3098         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3099                 /* Consider the frames with reserved multicast destination
3100                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3101                  */
3102                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3103                                       0xffff);
3104                 if (err)
3105                         return err;
3106         }
3107
3108         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3109                 /* Consider the frames with reserved multicast destination
3110                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3111                  */
3112                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3113                                       0xffff);
3114                 if (err)
3115                         return err;
3116         }
3117
3118         /* Ignore removed tag data on doubly tagged packets, disable
3119          * flow control messages, force flow control priority to the
3120          * highest, and send all special multicast frames to the CPU
3121          * port at the highest priority.
3122          */
3123         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3124         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3125             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3126                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3127         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3128         if (err)
3129                 return err;
3130
3131         /* Program the DSA routing table. */
3132         err = mv88e6xxx_g2_set_device_mapping(chip);
3133         if (err)
3134                 return err;
3135
3136         /* Clear all trunk masks and mapping. */
3137         err = mv88e6xxx_g2_clear_trunk(chip);
3138         if (err)
3139                 return err;
3140
3141         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3142                 /* Disable ingress rate limiting by resetting all per port
3143                  * ingress rate limit resources to their initial state.
3144                  */
3145                 err = mv88e6xxx_g2_clear_irl(chip);
3146                         if (err)
3147                                 return err;
3148         }
3149
3150         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3151                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3152                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3153                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3154                 if (err)
3155                         return err;
3156         }
3157
3158         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3159                 /* Clear the priority override table. */
3160                 err = mv88e6xxx_g2_clear_pot(chip);
3161                 if (err)
3162                         return err;
3163         }
3164
3165         return 0;
3166 }
3167
3168 static int mv88e6xxx_setup(struct dsa_switch *ds)
3169 {
3170         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3171         int err;
3172         int i;
3173
3174         chip->ds = ds;
3175         ds->slave_mii_bus = chip->mdio_bus;
3176
3177         mutex_lock(&chip->reg_lock);
3178
3179         err = mv88e6xxx_switch_reset(chip);
3180         if (err)
3181                 goto unlock;
3182
3183         /* Setup Switch Port Registers */
3184         for (i = 0; i < chip->info->num_ports; i++) {
3185                 err = mv88e6xxx_setup_port(chip, i);
3186                 if (err)
3187                         goto unlock;
3188         }
3189
3190         /* Setup Switch Global 1 Registers */
3191         err = mv88e6xxx_g1_setup(chip);
3192         if (err)
3193                 goto unlock;
3194
3195         /* Setup Switch Global 2 Registers */
3196         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3197                 err = mv88e6xxx_g2_setup(chip);
3198                 if (err)
3199                         goto unlock;
3200         }
3201
3202 unlock:
3203         mutex_unlock(&chip->reg_lock);
3204
3205         return err;
3206 }
3207
3208 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3209 {
3210         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3211         int err;
3212
3213         mutex_lock(&chip->reg_lock);
3214
3215         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3216         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3217                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3218         else
3219                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3220
3221         mutex_unlock(&chip->reg_lock);
3222
3223         return err;
3224 }
3225
3226 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3227                                     int reg)
3228 {
3229         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3230         int ret;
3231
3232         mutex_lock(&chip->reg_lock);
3233         ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3234         mutex_unlock(&chip->reg_lock);
3235
3236         return ret;
3237 }
3238
3239 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3240                                      int reg, int val)
3241 {
3242         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3243         int ret;
3244
3245         mutex_lock(&chip->reg_lock);
3246         ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3247         mutex_unlock(&chip->reg_lock);
3248
3249         return ret;
3250 }
3251
3252 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3253 {
3254         if (port >= 0 && port < chip->info->num_ports)
3255                 return port;
3256         return -EINVAL;
3257 }
3258
3259 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3260 {
3261         struct mv88e6xxx_chip *chip = bus->priv;
3262         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3263         int ret;
3264
3265         if (addr < 0)
3266                 return 0xffff;
3267
3268         mutex_lock(&chip->reg_lock);
3269
3270         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3271                 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3272         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY))
3273                 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3274         else
3275                 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3276
3277         mutex_unlock(&chip->reg_lock);
3278         return ret;
3279 }
3280
3281 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3282                                 u16 val)
3283 {
3284         struct mv88e6xxx_chip *chip = bus->priv;
3285         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3286         int ret;
3287
3288         if (addr < 0)
3289                 return 0xffff;
3290
3291         mutex_lock(&chip->reg_lock);
3292
3293         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3294                 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3295         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY))
3296                 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3297         else
3298                 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3299
3300         mutex_unlock(&chip->reg_lock);
3301         return ret;
3302 }
3303
3304 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3305                                    struct device_node *np)
3306 {
3307         static int index;
3308         struct mii_bus *bus;
3309         int err;
3310
3311         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3312                 mv88e6xxx_ppu_state_init(chip);
3313
3314         if (np)
3315                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3316
3317         bus = devm_mdiobus_alloc(chip->dev);
3318         if (!bus)
3319                 return -ENOMEM;
3320
3321         bus->priv = (void *)chip;
3322         if (np) {
3323                 bus->name = np->full_name;
3324                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3325         } else {
3326                 bus->name = "mv88e6xxx SMI";
3327                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3328         }
3329
3330         bus->read = mv88e6xxx_mdio_read;
3331         bus->write = mv88e6xxx_mdio_write;
3332         bus->parent = chip->dev;
3333
3334         if (chip->mdio_np)
3335                 err = of_mdiobus_register(bus, chip->mdio_np);
3336         else
3337                 err = mdiobus_register(bus);
3338         if (err) {
3339                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3340                 goto out;
3341         }
3342         chip->mdio_bus = bus;
3343
3344         return 0;
3345
3346 out:
3347         if (chip->mdio_np)
3348                 of_node_put(chip->mdio_np);
3349
3350         return err;
3351 }
3352
3353 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3354
3355 {
3356         struct mii_bus *bus = chip->mdio_bus;
3357
3358         mdiobus_unregister(bus);
3359
3360         if (chip->mdio_np)
3361                 of_node_put(chip->mdio_np);
3362 }
3363
3364 #ifdef CONFIG_NET_DSA_HWMON
3365
3366 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3367 {
3368         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3369         int ret;
3370         int val;
3371
3372         *temp = 0;
3373
3374         mutex_lock(&chip->reg_lock);
3375
3376         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3377         if (ret < 0)
3378                 goto error;
3379
3380         /* Enable temperature sensor */
3381         ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3382         if (ret < 0)
3383                 goto error;
3384
3385         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3386         if (ret < 0)
3387                 goto error;
3388
3389         /* Wait for temperature to stabilize */
3390         usleep_range(10000, 12000);
3391
3392         val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3393         if (val < 0) {
3394                 ret = val;
3395                 goto error;
3396         }
3397
3398         /* Disable temperature sensor */
3399         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3400         if (ret < 0)
3401                 goto error;
3402
3403         *temp = ((val & 0x1f) - 5) * 5;
3404
3405 error:
3406         mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3407         mutex_unlock(&chip->reg_lock);
3408         return ret;
3409 }
3410
3411 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3412 {
3413         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3414         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3415         int ret;
3416
3417         *temp = 0;
3418
3419         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3420         if (ret < 0)
3421                 return ret;
3422
3423         *temp = (ret & 0xff) - 25;
3424
3425         return 0;
3426 }
3427
3428 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3429 {
3430         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3431
3432         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3433                 return -EOPNOTSUPP;
3434
3435         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3436                 return mv88e63xx_get_temp(ds, temp);
3437
3438         return mv88e61xx_get_temp(ds, temp);
3439 }
3440
3441 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3442 {
3443         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3444         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3445         int ret;
3446
3447         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3448                 return -EOPNOTSUPP;
3449
3450         *temp = 0;
3451
3452         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3453         if (ret < 0)
3454                 return ret;
3455
3456         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3457
3458         return 0;
3459 }
3460
3461 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3462 {
3463         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3464         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3465         int ret;
3466
3467         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3468                 return -EOPNOTSUPP;
3469
3470         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3471         if (ret < 0)
3472                 return ret;
3473         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3474         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3475                                          (ret & 0xe0ff) | (temp << 8));
3476 }
3477
3478 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3479 {
3480         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3481         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3482         int ret;
3483
3484         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3485                 return -EOPNOTSUPP;
3486
3487         *alarm = false;
3488
3489         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3490         if (ret < 0)
3491                 return ret;
3492
3493         *alarm = !!(ret & 0x40);
3494
3495         return 0;
3496 }
3497 #endif /* CONFIG_NET_DSA_HWMON */
3498
3499 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3500 {
3501         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3502
3503         return chip->eeprom_len;
3504 }
3505
3506 static int mv88e6xxx_get_eeprom16(struct mv88e6xxx_chip *chip,
3507                                   struct ethtool_eeprom *eeprom, u8 *data)
3508 {
3509         unsigned int offset = eeprom->offset;
3510         unsigned int len = eeprom->len;
3511         u16 val;
3512         int err;
3513
3514         eeprom->len = 0;
3515
3516         if (offset & 1) {
3517                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3518                 if (err)
3519                         return err;
3520
3521                 *data++ = (val >> 8) & 0xff;
3522
3523                 offset++;
3524                 len--;
3525                 eeprom->len++;
3526         }
3527
3528         while (len >= 2) {
3529                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3530                 if (err)
3531                         return err;
3532
3533                 *data++ = val & 0xff;
3534                 *data++ = (val >> 8) & 0xff;
3535
3536                 offset += 2;
3537                 len -= 2;
3538                 eeprom->len += 2;
3539         }
3540
3541         if (len) {
3542                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3543                 if (err)
3544                         return err;
3545
3546                 *data++ = val & 0xff;
3547
3548                 offset++;
3549                 len--;
3550                 eeprom->len++;
3551         }
3552
3553         return 0;
3554 }
3555
3556 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3557                                 struct ethtool_eeprom *eeprom, u8 *data)
3558 {
3559         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3560         int err;
3561
3562         mutex_lock(&chip->reg_lock);
3563
3564         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3565                 err = mv88e6xxx_get_eeprom16(chip, eeprom, data);
3566         else
3567                 err = -EOPNOTSUPP;
3568
3569         mutex_unlock(&chip->reg_lock);
3570
3571         if (err)
3572                 return err;
3573
3574         eeprom->magic = 0xc3ec4951;
3575
3576         return 0;
3577 }
3578
3579 static int mv88e6xxx_set_eeprom16(struct mv88e6xxx_chip *chip,
3580                                   struct ethtool_eeprom *eeprom, u8 *data)
3581 {
3582         unsigned int offset = eeprom->offset;
3583         unsigned int len = eeprom->len;
3584         u16 val;
3585         int err;
3586
3587         /* Ensure the RO WriteEn bit is set */
3588         err = mv88e6xxx_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_CMD, &val);
3589         if (err)
3590                 return err;
3591
3592         if (!(val & GLOBAL2_EEPROM_CMD_WRITE_EN))
3593                 return -EROFS;
3594
3595         eeprom->len = 0;
3596
3597         if (offset & 1) {
3598                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3599                 if (err)
3600                         return err;
3601
3602                 val = (*data++ << 8) | (val & 0xff);
3603
3604                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3605                 if (err)
3606                         return err;
3607
3608                 offset++;
3609                 len--;
3610                 eeprom->len++;
3611         }
3612
3613         while (len >= 2) {
3614                 val = *data++;
3615                 val |= *data++ << 8;
3616
3617                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3618                 if (err)
3619                         return err;
3620
3621                 offset += 2;
3622                 len -= 2;
3623                 eeprom->len += 2;
3624         }
3625
3626         if (len) {
3627                 err = mv88e6xxx_g2_eeprom_read16(chip, offset >> 1, &val);
3628                 if (err)
3629                         return err;
3630
3631                 val = (val & 0xff00) | *data++;
3632
3633                 err = mv88e6xxx_g2_eeprom_write16(chip, offset >> 1, val);
3634                 if (err)
3635                         return err;
3636
3637                 offset++;
3638                 len--;
3639                 eeprom->len++;
3640         }
3641
3642         return 0;
3643 }
3644
3645 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3646                                 struct ethtool_eeprom *eeprom, u8 *data)
3647 {
3648         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3649         int err;
3650
3651         if (eeprom->magic != 0xc3ec4951)
3652                 return -EINVAL;
3653
3654         mutex_lock(&chip->reg_lock);
3655
3656         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3657                 err = mv88e6xxx_set_eeprom16(chip, eeprom, data);
3658         else
3659                 err = -EOPNOTSUPP;
3660
3661         mutex_unlock(&chip->reg_lock);
3662
3663         return err;
3664 }
3665
3666 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3667         [MV88E6085] = {
3668                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3669                 .family = MV88E6XXX_FAMILY_6097,
3670                 .name = "Marvell 88E6085",
3671                 .num_databases = 4096,
3672                 .num_ports = 10,
3673                 .port_base_addr = 0x10,
3674                 .age_time_coeff = 15000,
3675                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3676         },
3677
3678         [MV88E6095] = {
3679                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3680                 .family = MV88E6XXX_FAMILY_6095,
3681                 .name = "Marvell 88E6095/88E6095F",
3682                 .num_databases = 256,
3683                 .num_ports = 11,
3684                 .port_base_addr = 0x10,
3685                 .age_time_coeff = 15000,
3686                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3687         },
3688
3689         [MV88E6123] = {
3690                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3691                 .family = MV88E6XXX_FAMILY_6165,
3692                 .name = "Marvell 88E6123",
3693                 .num_databases = 4096,
3694                 .num_ports = 3,
3695                 .port_base_addr = 0x10,
3696                 .age_time_coeff = 15000,
3697                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3698         },
3699
3700         [MV88E6131] = {
3701                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3702                 .family = MV88E6XXX_FAMILY_6185,
3703                 .name = "Marvell 88E6131",
3704                 .num_databases = 256,
3705                 .num_ports = 8,
3706                 .port_base_addr = 0x10,
3707                 .age_time_coeff = 15000,
3708                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3709         },
3710
3711         [MV88E6161] = {
3712                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3713                 .family = MV88E6XXX_FAMILY_6165,
3714                 .name = "Marvell 88E6161",
3715                 .num_databases = 4096,
3716                 .num_ports = 6,
3717                 .port_base_addr = 0x10,
3718                 .age_time_coeff = 15000,
3719                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3720         },
3721
3722         [MV88E6165] = {
3723                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3724                 .family = MV88E6XXX_FAMILY_6165,
3725                 .name = "Marvell 88E6165",
3726                 .num_databases = 4096,
3727                 .num_ports = 6,
3728                 .port_base_addr = 0x10,
3729                 .age_time_coeff = 15000,
3730                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3731         },
3732
3733         [MV88E6171] = {
3734                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3735                 .family = MV88E6XXX_FAMILY_6351,
3736                 .name = "Marvell 88E6171",
3737                 .num_databases = 4096,
3738                 .num_ports = 7,
3739                 .port_base_addr = 0x10,
3740                 .age_time_coeff = 15000,
3741                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3742         },
3743
3744         [MV88E6172] = {
3745                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3746                 .family = MV88E6XXX_FAMILY_6352,
3747                 .name = "Marvell 88E6172",
3748                 .num_databases = 4096,
3749                 .num_ports = 7,
3750                 .port_base_addr = 0x10,
3751                 .age_time_coeff = 15000,
3752                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3753         },
3754
3755         [MV88E6175] = {
3756                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3757                 .family = MV88E6XXX_FAMILY_6351,
3758                 .name = "Marvell 88E6175",
3759                 .num_databases = 4096,
3760                 .num_ports = 7,
3761                 .port_base_addr = 0x10,
3762                 .age_time_coeff = 15000,
3763                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3764         },
3765
3766         [MV88E6176] = {
3767                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3768                 .family = MV88E6XXX_FAMILY_6352,
3769                 .name = "Marvell 88E6176",
3770                 .num_databases = 4096,
3771                 .num_ports = 7,
3772                 .port_base_addr = 0x10,
3773                 .age_time_coeff = 15000,
3774                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3775         },
3776
3777         [MV88E6185] = {
3778                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3779                 .family = MV88E6XXX_FAMILY_6185,
3780                 .name = "Marvell 88E6185",
3781                 .num_databases = 256,
3782                 .num_ports = 10,
3783                 .port_base_addr = 0x10,
3784                 .age_time_coeff = 15000,
3785                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3786         },
3787
3788         [MV88E6240] = {
3789                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3790                 .family = MV88E6XXX_FAMILY_6352,
3791                 .name = "Marvell 88E6240",
3792                 .num_databases = 4096,
3793                 .num_ports = 7,
3794                 .port_base_addr = 0x10,
3795                 .age_time_coeff = 15000,
3796                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3797         },
3798
3799         [MV88E6320] = {
3800                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3801                 .family = MV88E6XXX_FAMILY_6320,
3802                 .name = "Marvell 88E6320",
3803                 .num_databases = 4096,
3804                 .num_ports = 7,
3805                 .port_base_addr = 0x10,
3806                 .age_time_coeff = 15000,
3807                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3808         },
3809
3810         [MV88E6321] = {
3811                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3812                 .family = MV88E6XXX_FAMILY_6320,
3813                 .name = "Marvell 88E6321",
3814                 .num_databases = 4096,
3815                 .num_ports = 7,
3816                 .port_base_addr = 0x10,
3817                 .age_time_coeff = 15000,
3818                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3819         },
3820
3821         [MV88E6350] = {
3822                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3823                 .family = MV88E6XXX_FAMILY_6351,
3824                 .name = "Marvell 88E6350",
3825                 .num_databases = 4096,
3826                 .num_ports = 7,
3827                 .port_base_addr = 0x10,
3828                 .age_time_coeff = 15000,
3829                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3830         },
3831
3832         [MV88E6351] = {
3833                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3834                 .family = MV88E6XXX_FAMILY_6351,
3835                 .name = "Marvell 88E6351",
3836                 .num_databases = 4096,
3837                 .num_ports = 7,
3838                 .port_base_addr = 0x10,
3839                 .age_time_coeff = 15000,
3840                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3841         },
3842
3843         [MV88E6352] = {
3844                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3845                 .family = MV88E6XXX_FAMILY_6352,
3846                 .name = "Marvell 88E6352",
3847                 .num_databases = 4096,
3848                 .num_ports = 7,
3849                 .port_base_addr = 0x10,
3850                 .age_time_coeff = 15000,
3851                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3852         },
3853 };
3854
3855 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3856 {
3857         int i;
3858
3859         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3860                 if (mv88e6xxx_table[i].prod_num == prod_num)
3861                         return &mv88e6xxx_table[i];
3862
3863         return NULL;
3864 }
3865
3866 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3867 {
3868         const struct mv88e6xxx_info *info;
3869         unsigned int prod_num, rev;
3870         u16 id;
3871         int err;
3872
3873         mutex_lock(&chip->reg_lock);
3874         err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3875         mutex_unlock(&chip->reg_lock);
3876         if (err)
3877                 return err;
3878
3879         prod_num = (id & 0xfff0) >> 4;
3880         rev = id & 0x000f;
3881
3882         info = mv88e6xxx_lookup_info(prod_num);
3883         if (!info)
3884                 return -ENODEV;
3885
3886         /* Update the compatible info with the probed one */
3887         chip->info = info;
3888
3889         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3890                  chip->info->prod_num, chip->info->name, rev);
3891
3892         return 0;
3893 }
3894
3895 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3896 {
3897         struct mv88e6xxx_chip *chip;
3898
3899         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3900         if (!chip)
3901                 return NULL;
3902
3903         chip->dev = dev;
3904
3905         mutex_init(&chip->reg_lock);
3906
3907         return chip;
3908 }
3909
3910 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3911                               struct mii_bus *bus, int sw_addr)
3912 {
3913         /* ADDR[0] pin is unavailable externally and considered zero */
3914         if (sw_addr & 0x1)
3915                 return -EINVAL;
3916
3917         if (sw_addr == 0)
3918                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3919         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3920                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3921         else
3922                 return -EINVAL;
3923
3924         chip->bus = bus;
3925         chip->sw_addr = sw_addr;
3926
3927         return 0;
3928 }
3929
3930 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3931                                        struct device *host_dev, int sw_addr,
3932                                        void **priv)
3933 {
3934         struct mv88e6xxx_chip *chip;
3935         struct mii_bus *bus;
3936         int err;
3937
3938         bus = dsa_host_dev_to_mii_bus(host_dev);
3939         if (!bus)
3940                 return NULL;
3941
3942         chip = mv88e6xxx_alloc_chip(dsa_dev);
3943         if (!chip)
3944                 return NULL;
3945
3946         /* Legacy SMI probing will only support chips similar to 88E6085 */
3947         chip->info = &mv88e6xxx_table[MV88E6085];
3948
3949         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3950         if (err)
3951                 goto free;
3952
3953         err = mv88e6xxx_detect(chip);
3954         if (err)
3955                 goto free;
3956
3957         err = mv88e6xxx_mdio_register(chip, NULL);
3958         if (err)
3959                 goto free;
3960
3961         *priv = chip;
3962
3963         return chip->info->name;
3964 free:
3965         devm_kfree(dsa_dev, chip);
3966
3967         return NULL;
3968 }
3969
3970 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3971         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3972         .probe                  = mv88e6xxx_drv_probe,
3973         .setup                  = mv88e6xxx_setup,
3974         .set_addr               = mv88e6xxx_set_addr,
3975         .adjust_link            = mv88e6xxx_adjust_link,
3976         .get_strings            = mv88e6xxx_get_strings,
3977         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3978         .get_sset_count         = mv88e6xxx_get_sset_count,
3979         .set_eee                = mv88e6xxx_set_eee,
3980         .get_eee                = mv88e6xxx_get_eee,
3981 #ifdef CONFIG_NET_DSA_HWMON
3982         .get_temp               = mv88e6xxx_get_temp,
3983         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3984         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3985         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3986 #endif
3987         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3988         .get_eeprom             = mv88e6xxx_get_eeprom,
3989         .set_eeprom             = mv88e6xxx_set_eeprom,
3990         .get_regs_len           = mv88e6xxx_get_regs_len,
3991         .get_regs               = mv88e6xxx_get_regs,
3992         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3993         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3994         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3995         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3996         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3997         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3998         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3999         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4000         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
4001         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4002         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4003         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4004         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4005 };
4006
4007 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4008                                      struct device_node *np)
4009 {
4010         struct device *dev = chip->dev;
4011         struct dsa_switch *ds;
4012
4013         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4014         if (!ds)
4015                 return -ENOMEM;
4016
4017         ds->dev = dev;
4018         ds->priv = chip;
4019         ds->drv = &mv88e6xxx_switch_driver;
4020
4021         dev_set_drvdata(dev, ds);
4022
4023         return dsa_register_switch(ds, np);
4024 }
4025
4026 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4027 {
4028         dsa_unregister_switch(chip->ds);
4029 }
4030
4031 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4032 {
4033         struct device *dev = &mdiodev->dev;
4034         struct device_node *np = dev->of_node;
4035         const struct mv88e6xxx_info *compat_info;
4036         struct mv88e6xxx_chip *chip;
4037         u32 eeprom_len;
4038         int err;
4039
4040         compat_info = of_device_get_match_data(dev);
4041         if (!compat_info)
4042                 return -EINVAL;
4043
4044         chip = mv88e6xxx_alloc_chip(dev);
4045         if (!chip)
4046                 return -ENOMEM;
4047
4048         chip->info = compat_info;
4049
4050         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4051         if (err)
4052                 return err;
4053
4054         err = mv88e6xxx_detect(chip);
4055         if (err)
4056                 return err;
4057
4058         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4059         if (IS_ERR(chip->reset))
4060                 return PTR_ERR(chip->reset);
4061
4062         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
4063             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4064                 chip->eeprom_len = eeprom_len;
4065
4066         err = mv88e6xxx_mdio_register(chip, np);
4067         if (err)
4068                 return err;
4069
4070         err = mv88e6xxx_register_switch(chip, np);
4071         if (err) {
4072                 mv88e6xxx_mdio_unregister(chip);
4073                 return err;
4074         }
4075
4076         return 0;
4077 }
4078
4079 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4080 {
4081         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4082         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4083
4084         mv88e6xxx_unregister_switch(chip);
4085         mv88e6xxx_mdio_unregister(chip);
4086 }
4087
4088 static const struct of_device_id mv88e6xxx_of_match[] = {
4089         {
4090                 .compatible = "marvell,mv88e6085",
4091                 .data = &mv88e6xxx_table[MV88E6085],
4092         },
4093         { /* sentinel */ },
4094 };
4095
4096 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4097
4098 static struct mdio_driver mv88e6xxx_driver = {
4099         .probe  = mv88e6xxx_probe,
4100         .remove = mv88e6xxx_remove,
4101         .mdiodrv.driver = {
4102                 .name = "mv88e6085",
4103                 .of_match_table = mv88e6xxx_of_match,
4104         },
4105 };
4106
4107 static int __init mv88e6xxx_init(void)
4108 {
4109         register_switch_driver(&mv88e6xxx_switch_driver);
4110         return mdio_driver_register(&mv88e6xxx_driver);
4111 }
4112 module_init(mv88e6xxx_init);
4113
4114 static void __exit mv88e6xxx_cleanup(void)
4115 {
4116         mdio_driver_unregister(&mv88e6xxx_driver);
4117         unregister_switch_driver(&mv88e6xxx_switch_driver);
4118 }
4119 module_exit(mv88e6xxx_cleanup);
4120
4121 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4122 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4123 MODULE_LICENSE("GPL");