drivers/net/dsa/mv88e6xxx/chip.c

   1 /*
   2  * Marvell 88e6xxx Ethernet switch single-chip support
   3  *
   4  * Copyright (c) 2008 Marvell Semiconductor
   5  *
   6  * Copyright (c) 2015 CMC Electronics, Inc.
   7  *      Added support for VLAN Table Unit operations
   8  *
   9  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include <linux/delay.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_bridge.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/list.h>
  23 #include <linux/mdio.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/of_mdio.h>
  27 #include <linux/netdevice.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/phy.h>
  30 #include <net/dsa.h>
  31 #include <net/switchdev.h>
  32 #include "mv88e6xxx.h"
  33
  34 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
  35 {
  36         if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
  37                 dev_err(chip->dev, "Switch registers lock not held!\n");
  38                 dump_stack();
  39         }
  40 }
  41
  42 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
  43  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
  44  *
  45  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
  46  * is the only device connected to the SMI master. In this mode it responds to
  47  * all 32 possible SMI addresses, and thus maps directly the internal devices.
  48  *
  49  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
  50  * multiple devices to share the SMI interface. In this mode it responds to only
  51  * 2 registers, used to indirectly access the internal SMI devices.
  52  */
  53
  54 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
  55                               int addr, int reg, u16 *val)
  56 {
  57         if (!chip->smi_ops)
  58                 return -EOPNOTSUPP;
  59
  60         return chip->smi_ops->read(chip, addr, reg, val);
  61 }
  62
  63 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
  64                                int addr, int reg, u16 val)
  65 {
  66         if (!chip->smi_ops)
  67                 return -EOPNOTSUPP;
  68
  69         return chip->smi_ops->write(chip, addr, reg, val);
  70 }
  71
  72 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
  73                                           int addr, int reg, u16 *val)
  74 {
  75         int ret;
  76
  77         ret = mdiobus_read_nested(chip->bus, addr, reg);
  78         if (ret < 0)
  79                 return ret;
  80
  81         *val = ret & 0xffff;
  82
  83         return 0;
  84 }
  85
  86 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
  87                                            int addr, int reg, u16 val)
  88 {
  89         int ret;
  90
  91         ret = mdiobus_write_nested(chip->bus, addr, reg, val);
  92         if (ret < 0)
  93                 return ret;
  94
  95         return 0;
  96 }
  97
  98 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
  99         .read = mv88e6xxx_smi_single_chip_read,
 100         .write = mv88e6xxx_smi_single_chip_write,
 101 };
 102
 103 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
 104 {
 105         int ret;
 106         int i;
 107
 108         for (i = 0; i < 16; i++) {
 109                 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
 110                 if (ret < 0)
 111                         return ret;
 112
 113                 if ((ret & SMI_CMD_BUSY) == 0)
 114                         return 0;
 115         }
 116
 117         return -ETIMEDOUT;
 118 }
 119
 120 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
 121                                          int addr, int reg, u16 *val)
 122 {
 123         int ret;
 124
 125         /* Wait for the bus to become free. */
 126         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 127         if (ret < 0)
 128                 return ret;
 129
 130         /* Transmit the read command. */
 131         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 132                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
 133         if (ret < 0)
 134                 return ret;
 135
 136         /* Wait for the read command to complete. */
 137         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 138         if (ret < 0)
 139                 return ret;
 140
 141         /* Read the data. */
 142         ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
 143         if (ret < 0)
 144                 return ret;
 145
 146         *val = ret & 0xffff;
 147
 148         return 0;
 149 }
 150
 151 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
 152                                           int addr, int reg, u16 val)
 153 {
 154         int ret;
 155
 156         /* Wait for the bus to become free. */
 157         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 158         if (ret < 0)
 159                 return ret;
 160
 161         /* Transmit the data to write. */
 162         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
 163         if (ret < 0)
 164                 return ret;
 165
 166         /* Transmit the write command. */
 167         ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
 168                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 169         if (ret < 0)
 170                 return ret;
 171
 172         /* Wait for the write command to complete. */
 173         ret = mv88e6xxx_smi_multi_chip_wait(chip);
 174         if (ret < 0)
 175                 return ret;
 176
 177         return 0;
 178 }
 179
 180 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
 181         .read = mv88e6xxx_smi_multi_chip_read,
 182         .write = mv88e6xxx_smi_multi_chip_write,
 183 };
 184
 185 static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
 186                           int addr, int reg, u16 *val)
 187 {
 188         int err;
 189
 190         assert_reg_lock(chip);
 191
 192         err = mv88e6xxx_smi_read(chip, addr, reg, val);
 193         if (err)
 194                 return err;
 195
 196         dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 197                 addr, reg, *val);
 198
 199         return 0;
 200 }
 201
 202 static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
 203                            int addr, int reg, u16 val)
 204 {
 205         int err;
 206
 207         assert_reg_lock(chip);
 208
 209         err = mv88e6xxx_smi_write(chip, addr, reg, val);
 210         if (err)
 211                 return err;
 212
 213         dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 214                 addr, reg, val);
 215
 216         return 0;
 217 }
 218
 219 /* Indirect write to single pointer-data register with an Update bit */
 220 static int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 221                             u16 update)
 222 {
 223         u16 val;
 224         int i, err;
 225
 226         /* Wait until the previous operation is completed */
 227         for (i = 0; i < 16; ++i) {
 228                 err = mv88e6xxx_read(chip, addr, reg, &val);
 229                 if (err)
 230                         return err;
 231
 232                 if (!(val & BIT(15)))
 233                         break;
 234         }
 235
 236         if (i == 16)
 237                 return -ETIMEDOUT;
 238
 239         /* Set the Update bit to trigger a write operation */
 240         val = BIT(15) | update;
 241
 242         return mv88e6xxx_write(chip, addr, reg, val);
 243 }
 244
 245 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 246 {
 247         u16 val;
 248         int err;
 249
 250         err = mv88e6xxx_read(chip, addr, reg, &val);
 251         if (err)
 252                 return err;
 253
 254         return val;
 255 }
 256
 257 static int mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
 258 {
 259         int ret;
 260
 261         mutex_lock(&chip->reg_lock);
 262         ret = _mv88e6xxx_reg_read(chip, addr, reg);
 263         mutex_unlock(&chip->reg_lock);
 264
 265         return ret;
 266 }
 267
 268 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 269                                 int reg, u16 val)
 270 {
 271         return mv88e6xxx_write(chip, addr, reg, val);
 272 }
 273
 274 static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
 275                                int reg, u16 val)
 276 {
 277         int ret;
 278
 279         mutex_lock(&chip->reg_lock);
 280         ret = _mv88e6xxx_reg_write(chip, addr, reg, val);
 281         mutex_unlock(&chip->reg_lock);
 282
 283         return ret;
 284 }
 285
 286 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
 287                                       int addr, int regnum)
 288 {
 289         if (addr >= 0)
 290                 return _mv88e6xxx_reg_read(chip, addr, regnum);
 291         return 0xffff;
 292 }
 293
 294 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
 295                                        int addr, int regnum, u16 val)
 296 {
 297         if (addr >= 0)
 298                 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
 299         return 0;
 300 }
 301
 302 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
 303 {
 304         int ret;
 305         unsigned long timeout;
 306
 307         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 308         if (ret < 0)
 309                 return ret;
 310
 311         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 312                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 313         if (ret)
 314                 return ret;
 315
 316         timeout = jiffies + 1 * HZ;
 317         while (time_before(jiffies, timeout)) {
 318                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 319                 if (ret < 0)
 320                         return ret;
 321
 322                 usleep_range(1000, 2000);
 323                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 324                     GLOBAL_STATUS_PPU_POLLING)
 325                         return 0;
 326         }
 327
 328         return -ETIMEDOUT;
 329 }
 330
 331 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
 332 {
 333         int ret, err;
 334         unsigned long timeout;
 335
 336         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
 337         if (ret < 0)
 338                 return ret;
 339
 340         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
 341                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 342         if (err)
 343                 return err;
 344
 345         timeout = jiffies + 1 * HZ;
 346         while (time_before(jiffies, timeout)) {
 347                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
 348                 if (ret < 0)
 349                         return ret;
 350
 351                 usleep_range(1000, 2000);
 352                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 353                     GLOBAL_STATUS_PPU_POLLING)
 354                         return 0;
 355         }
 356
 357         return -ETIMEDOUT;
 358 }
 359
 360 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 361 {
 362         struct mv88e6xxx_chip *chip;
 363
 364         chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
 365
 366         mutex_lock(&chip->reg_lock);
 367
 368         if (mutex_trylock(&chip->ppu_mutex)) {
 369                 if (mv88e6xxx_ppu_enable(chip) == 0)
 370                         chip->ppu_disabled = 0;
 371                 mutex_unlock(&chip->ppu_mutex);
 372         }
 373
 374         mutex_unlock(&chip->reg_lock);
 375 }
 376
 377 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 378 {
 379         struct mv88e6xxx_chip *chip = (void *)_ps;
 380
 381         schedule_work(&chip->ppu_work);
 382 }
 383
 384 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
 385 {
 386         int ret;
 387
 388         mutex_lock(&chip->ppu_mutex);
 389
 390         /* If the PHY polling unit is enabled, disable it so that
 391          * we can access the PHY registers.  If it was already
 392          * disabled, cancel the timer that is going to re-enable
 393          * it.
 394          */
 395         if (!chip->ppu_disabled) {
 396                 ret = mv88e6xxx_ppu_disable(chip);
 397                 if (ret < 0) {
 398                         mutex_unlock(&chip->ppu_mutex);
 399                         return ret;
 400                 }
 401                 chip->ppu_disabled = 1;
 402         } else {
 403                 del_timer(&chip->ppu_timer);
 404                 ret = 0;
 405         }
 406
 407         return ret;
 408 }
 409
 410 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
 411 {
 412         /* Schedule a timer to re-enable the PHY polling unit. */
 413         mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
 414         mutex_unlock(&chip->ppu_mutex);
 415 }
 416
 417 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
 418 {
 419         mutex_init(&chip->ppu_mutex);
 420         INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
 421         init_timer(&chip->ppu_timer);
 422         chip->ppu_timer.data = (unsigned long)chip;
 423         chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 424 }
 425
 426 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
 427                                    int regnum)
 428 {
 429         int ret;
 430
 431         ret = mv88e6xxx_ppu_access_get(chip);
 432         if (ret >= 0) {
 433                 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
 434                 mv88e6xxx_ppu_access_put(chip);
 435         }
 436
 437         return ret;
 438 }
 439
 440 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
 441                                     int regnum, u16 val)
 442 {
 443         int ret;
 444
 445         ret = mv88e6xxx_ppu_access_get(chip);
 446         if (ret >= 0) {
 447                 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
 448                 mv88e6xxx_ppu_access_put(chip);
 449         }
 450
 451         return ret;
 452 }
 453
 454 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
 455 {
 456         return chip->info->family == MV88E6XXX_FAMILY_6065;
 457 }
 458
 459 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
 460 {
 461         return chip->info->family == MV88E6XXX_FAMILY_6095;
 462 }
 463
 464 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
 465 {
 466         return chip->info->family == MV88E6XXX_FAMILY_6097;
 467 }
 468
 469 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
 470 {
 471         return chip->info->family == MV88E6XXX_FAMILY_6165;
 472 }
 473
 474 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
 475 {
 476         return chip->info->family == MV88E6XXX_FAMILY_6185;
 477 }
 478
 479 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
 480 {
 481         return chip->info->family == MV88E6XXX_FAMILY_6320;
 482 }
 483
 484 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
 485 {
 486         return chip->info->family == MV88E6XXX_FAMILY_6351;
 487 }
 488
 489 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
 490 {
 491         return chip->info->family == MV88E6XXX_FAMILY_6352;
 492 }
 493
 494 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 495 {
 496         return chip->info->num_databases;
 497 }
 498
 499 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
 500 {
 501         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 502         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
 503             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
 504                 return true;
 505
 506         return false;
 507 }
 508
 509 /* We expect the switch to perform auto negotiation if there is a real
 510  * phy. However, in the case of a fixed link phy, we force the port
 511  * settings from the fixed link settings.
 512  */
 513 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 514                                   struct phy_device *phydev)
 515 {
 516         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 517         u32 reg;
 518         int ret;
 519
 520         if (!phy_is_pseudo_fixed_link(phydev))
 521                 return;
 522
 523         mutex_lock(&chip->reg_lock);
 524
 525         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
 526         if (ret < 0)
 527                 goto out;
 528
 529         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 530                       PORT_PCS_CTRL_FORCE_LINK |
 531                       PORT_PCS_CTRL_DUPLEX_FULL |
 532                       PORT_PCS_CTRL_FORCE_DUPLEX |
 533                       PORT_PCS_CTRL_UNFORCED);
 534
 535         reg |= PORT_PCS_CTRL_FORCE_LINK;
 536         if (phydev->link)
 537                 reg |= PORT_PCS_CTRL_LINK_UP;
 538
 539         if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
 540                 goto out;
 541
 542         switch (phydev->speed) {
 543         case SPEED_1000:
 544                 reg |= PORT_PCS_CTRL_1000;
 545                 break;
 546         case SPEED_100:
 547                 reg |= PORT_PCS_CTRL_100;
 548                 break;
 549         case SPEED_10:
 550                 reg |= PORT_PCS_CTRL_10;
 551                 break;
 552         default:
 553                 pr_info("Unknown speed");
 554                 goto out;
 555         }
 556
 557         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 558         if (phydev->duplex == DUPLEX_FULL)
 559                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 560
 561         if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
 562             (port >= chip->info->num_ports - 2)) {
 563                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 564                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 565                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 566                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 567                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 568                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 569                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 570         }
 571         _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
 572
 573 out:
 574         mutex_unlock(&chip->reg_lock);
 575 }
 576
 577 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
 578 {
 579         int ret;
 580         int i;
 581
 582         for (i = 0; i < 10; i++) {
 583                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
 584                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 585                         return 0;
 586         }
 587
 588         return -ETIMEDOUT;
 589 }
 590
 591 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
 592 {
 593         int ret;
 594
 595         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
 596                 port = (port + 1) << 5;
 597
 598         /* Snapshot the hardware statistics counters for this port. */
 599         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 600                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 601                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 602         if (ret < 0)
 603                 return ret;
 604
 605         /* Wait for the snapshotting to complete. */
 606         ret = _mv88e6xxx_stats_wait(chip);
 607         if (ret < 0)
 608                 return ret;
 609
 610         return 0;
 611 }
 612
 613 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
 614                                   int stat, u32 *val)
 615 {
 616         u32 _val;
 617         int ret;
 618
 619         *val = 0;
 620
 621         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
 622                                    GLOBAL_STATS_OP_READ_CAPTURED |
 623                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 624         if (ret < 0)
 625                 return;
 626
 627         ret = _mv88e6xxx_stats_wait(chip);
 628         if (ret < 0)
 629                 return;
 630
 631         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 632         if (ret < 0)
 633                 return;
 634
 635         _val = ret << 16;
 636
 637         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 638         if (ret < 0)
 639                 return;
 640
 641         *val = _val | ret;
 642 }
 643
 644 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 645         { "in_good_octets",     8, 0x00, BANK0, },
 646         { "in_bad_octets",      4, 0x02, BANK0, },
 647         { "in_unicast",         4, 0x04, BANK0, },
 648         { "in_broadcasts",      4, 0x06, BANK0, },
 649         { "in_multicasts",      4, 0x07, BANK0, },
 650         { "in_pause",           4, 0x16, BANK0, },
 651         { "in_undersize",       4, 0x18, BANK0, },
 652         { "in_fragments",       4, 0x19, BANK0, },
 653         { "in_oversize",        4, 0x1a, BANK0, },
 654         { "in_jabber",          4, 0x1b, BANK0, },
 655         { "in_rx_error",        4, 0x1c, BANK0, },
 656         { "in_fcs_error",       4, 0x1d, BANK0, },
 657         { "out_octets",         8, 0x0e, BANK0, },
 658         { "out_unicast",        4, 0x10, BANK0, },
 659         { "out_broadcasts",     4, 0x13, BANK0, },
 660         { "out_multicasts",     4, 0x12, BANK0, },
 661         { "out_pause",          4, 0x15, BANK0, },
 662         { "excessive",          4, 0x11, BANK0, },
 663         { "collisions",         4, 0x1e, BANK0, },
 664         { "deferred",           4, 0x05, BANK0, },
 665         { "single",             4, 0x14, BANK0, },
 666         { "multiple",           4, 0x17, BANK0, },
 667         { "out_fcs_error",      4, 0x03, BANK0, },
 668         { "late",               4, 0x1f, BANK0, },
 669         { "hist_64bytes",       4, 0x08, BANK0, },
 670         { "hist_65_127bytes",   4, 0x09, BANK0, },
 671         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 672         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 673         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 674         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 675         { "sw_in_discards",     4, 0x10, PORT, },
 676         { "sw_in_filtered",     2, 0x12, PORT, },
 677         { "sw_out_filtered",    2, 0x13, PORT, },
 678         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 679         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 680         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 681         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 682         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 683         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 684         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 685         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 686         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 687         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 688         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 689         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 690         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 691         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 692         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 693         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 694         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 695         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 696         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 697         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 698         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 699         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 700         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 701         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 702         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 703         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 704 };
 705
 706 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
 707                                struct mv88e6xxx_hw_stat *stat)
 708 {
 709         switch (stat->type) {
 710         case BANK0:
 711                 return true;
 712         case BANK1:
 713                 return mv88e6xxx_6320_family(chip);
 714         case PORT:
 715                 return mv88e6xxx_6095_family(chip) ||
 716                         mv88e6xxx_6185_family(chip) ||
 717                         mv88e6xxx_6097_family(chip) ||
 718                         mv88e6xxx_6165_family(chip) ||
 719                         mv88e6xxx_6351_family(chip) ||
 720                         mv88e6xxx_6352_family(chip);
 721         }
 722         return false;
 723 }
 724
 725 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
 726                                             struct mv88e6xxx_hw_stat *s,
 727                                             int port)
 728 {
 729         u32 low;
 730         u32 high = 0;
 731         int ret;
 732         u64 value;
 733
 734         switch (s->type) {
 735         case PORT:
 736                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
 737                 if (ret < 0)
 738                         return UINT64_MAX;
 739
 740                 low = ret;
 741                 if (s->sizeof_stat == 4) {
 742                         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
 743                                                   s->reg + 1);
 744                         if (ret < 0)
 745                                 return UINT64_MAX;
 746                         high = ret;
 747                 }
 748                 break;
 749         case BANK0:
 750         case BANK1:
 751                 _mv88e6xxx_stats_read(chip, s->reg, &low);
 752                 if (s->sizeof_stat == 8)
 753                         _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
 754         }
 755         value = (((u64)high) << 16) | low;
 756         return value;
 757 }
 758
 759 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 760                                   uint8_t *data)
 761 {
 762         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 763         struct mv88e6xxx_hw_stat *stat;
 764         int i, j;
 765
 766         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 767                 stat = &mv88e6xxx_hw_stats[i];
 768                 if (mv88e6xxx_has_stat(chip, stat)) {
 769                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 770                                ETH_GSTRING_LEN);
 771                         j++;
 772                 }
 773         }
 774 }
 775
 776 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 777 {
 778         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 779         struct mv88e6xxx_hw_stat *stat;
 780         int i, j;
 781
 782         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 783                 stat = &mv88e6xxx_hw_stats[i];
 784                 if (mv88e6xxx_has_stat(chip, stat))
 785                         j++;
 786         }
 787         return j;
 788 }
 789
 790 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 791                                         uint64_t *data)
 792 {
 793         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 794         struct mv88e6xxx_hw_stat *stat;
 795         int ret;
 796         int i, j;
 797
 798         mutex_lock(&chip->reg_lock);
 799
 800         ret = _mv88e6xxx_stats_snapshot(chip, port);
 801         if (ret < 0) {
 802                 mutex_unlock(&chip->reg_lock);
 803                 return;
 804         }
 805         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 806                 stat = &mv88e6xxx_hw_stats[i];
 807                 if (mv88e6xxx_has_stat(chip, stat)) {
 808                         data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
 809                         j++;
 810                 }
 811         }
 812
 813         mutex_unlock(&chip->reg_lock);
 814 }
 815
 816 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 817 {
 818         return 32 * sizeof(u16);
 819 }
 820
 821 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 822                                struct ethtool_regs *regs, void *_p)
 823 {
 824         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 825         u16 *p = _p;
 826         int i;
 827
 828         regs->version = 0;
 829
 830         memset(p, 0xff, 32 * sizeof(u16));
 831
 832         mutex_lock(&chip->reg_lock);
 833
 834         for (i = 0; i < 32; i++) {
 835                 int ret;
 836
 837                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
 838                 if (ret >= 0)
 839                         p[i] = ret;
 840         }
 841
 842         mutex_unlock(&chip->reg_lock);
 843 }
 844
 845 static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
 846                            u16 mask)
 847 {
 848         unsigned long timeout = jiffies + HZ / 10;
 849
 850         while (time_before(jiffies, timeout)) {
 851                 int ret;
 852
 853                 ret = _mv88e6xxx_reg_read(chip, reg, offset);
 854                 if (ret < 0)
 855                         return ret;
 856                 if (!(ret & mask))
 857                         return 0;
 858
 859                 usleep_range(1000, 2000);
 860         }
 861         return -ETIMEDOUT;
 862 }
 863
 864 static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg,
 865                           int offset, u16 mask)
 866 {
 867         int ret;
 868
 869         mutex_lock(&chip->reg_lock);
 870         ret = _mv88e6xxx_wait(chip, reg, offset, mask);
 871         mutex_unlock(&chip->reg_lock);
 872
 873         return ret;
 874 }
 875
 876 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
 877 {
 878         return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
 879                                GLOBAL2_SMI_OP_BUSY);
 880 }
 881
 882 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 883 {
 884         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 885
 886         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 887                               GLOBAL2_EEPROM_OP_LOAD);
 888 }
 889
 890 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 891 {
 892         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 893
 894         return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 895                               GLOBAL2_EEPROM_OP_BUSY);
 896 }
 897
 898 static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
 899 {
 900         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 901         int ret;
 902
 903         mutex_lock(&chip->eeprom_mutex);
 904
 905         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 906                                   GLOBAL2_EEPROM_OP_READ |
 907                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 908         if (ret < 0)
 909                 goto error;
 910
 911         ret = mv88e6xxx_eeprom_busy_wait(ds);
 912         if (ret < 0)
 913                 goto error;
 914
 915         ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
 916 error:
 917         mutex_unlock(&chip->eeprom_mutex);
 918         return ret;
 919 }
 920
 921 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
 922 {
 923         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 924
 925         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
 926                 return chip->eeprom_len;
 927
 928         return 0;
 929 }
 930
 931 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
 932                                 struct ethtool_eeprom *eeprom, u8 *data)
 933 {
 934         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
 935         int offset;
 936         int len;
 937         int ret;
 938
 939         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
 940                 return -EOPNOTSUPP;
 941
 942         offset = eeprom->offset;
 943         len = eeprom->len;
 944         eeprom->len = 0;
 945
 946         eeprom->magic = 0xc3ec4951;
 947
 948         ret = mv88e6xxx_eeprom_load_wait(ds);
 949         if (ret < 0)
 950                 return ret;
 951
 952         if (offset & 1) {
 953                 int word;
 954
 955                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 956                 if (word < 0)
 957                         return word;
 958
 959                 *data++ = (word >> 8) & 0xff;
 960
 961                 offset++;
 962                 len--;
 963                 eeprom->len++;
 964         }
 965
 966         while (len >= 2) {
 967                 int word;
 968
 969                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 970                 if (word < 0)
 971                         return word;
 972
 973                 *data++ = word & 0xff;
 974                 *data++ = (word >> 8) & 0xff;
 975
 976                 offset += 2;
 977                 len -= 2;
 978                 eeprom->len += 2;
 979         }
 980
 981         if (len) {
 982                 int word;
 983
 984                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 985                 if (word < 0)
 986                         return word;
 987
 988                 *data++ = word & 0xff;
 989
 990                 offset++;
 991                 len--;
 992                 eeprom->len++;
 993         }
 994
 995         return 0;
 996 }
 997
 998 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
 999 {
1000         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1001         int ret;
1002
1003         ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
1004         if (ret < 0)
1005                 return ret;
1006
1007         if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
1008                 return -EROFS;
1009
1010         return 0;
1011 }
1012
1013 static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1014                                        u16 data)
1015 {
1016         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1017         int ret;
1018
1019         mutex_lock(&chip->eeprom_mutex);
1020
1021         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
1022         if (ret < 0)
1023                 goto error;
1024
1025         ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
1026                                   GLOBAL2_EEPROM_OP_WRITE |
1027                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
1028         if (ret < 0)
1029                 goto error;
1030
1031         ret = mv88e6xxx_eeprom_busy_wait(ds);
1032 error:
1033         mutex_unlock(&chip->eeprom_mutex);
1034         return ret;
1035 }
1036
1037 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1038                                 struct ethtool_eeprom *eeprom, u8 *data)
1039 {
1040         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1041         int offset;
1042         int ret;
1043         int len;
1044
1045         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
1046                 return -EOPNOTSUPP;
1047
1048         if (eeprom->magic != 0xc3ec4951)
1049                 return -EINVAL;
1050
1051         ret = mv88e6xxx_eeprom_is_readonly(ds);
1052         if (ret)
1053                 return ret;
1054
1055         offset = eeprom->offset;
1056         len = eeprom->len;
1057         eeprom->len = 0;
1058
1059         ret = mv88e6xxx_eeprom_load_wait(ds);
1060         if (ret < 0)
1061                 return ret;
1062
1063         if (offset & 1) {
1064                 int word;
1065
1066                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1067                 if (word < 0)
1068                         return word;
1069
1070                 word = (*data++ << 8) | (word & 0xff);
1071
1072                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1073                 if (ret < 0)
1074                         return ret;
1075
1076                 offset++;
1077                 len--;
1078                 eeprom->len++;
1079         }
1080
1081         while (len >= 2) {
1082                 int word;
1083
1084                 word = *data++;
1085                 word |= *data++ << 8;
1086
1087                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1088                 if (ret < 0)
1089                         return ret;
1090
1091                 offset += 2;
1092                 len -= 2;
1093                 eeprom->len += 2;
1094         }
1095
1096         if (len) {
1097                 int word;
1098
1099                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1100                 if (word < 0)
1101                         return word;
1102
1103                 word = (word & 0xff00) | *data++;
1104
1105                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1106                 if (ret < 0)
1107                         return ret;
1108
1109                 offset++;
1110                 len--;
1111                 eeprom->len++;
1112         }
1113
1114         return 0;
1115 }
1116
1117 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1118 {
1119         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
1120                                GLOBAL_ATU_OP_BUSY);
1121 }
1122
1123 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
1124                                         int addr, int regnum)
1125 {
1126         int ret;
1127
1128         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1129                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1130                                    regnum);
1131         if (ret < 0)
1132                 return ret;
1133
1134         ret = mv88e6xxx_mdio_wait(chip);
1135         if (ret < 0)
1136                 return ret;
1137
1138         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1139
1140         return ret;
1141 }
1142
1143 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
1144                                          int addr, int regnum, u16 val)
1145 {
1146         int ret;
1147
1148         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1149         if (ret < 0)
1150                 return ret;
1151
1152         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1153                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1154                                    regnum);
1155
1156         return mv88e6xxx_mdio_wait(chip);
1157 }
1158
1159 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1160                              struct ethtool_eee *e)
1161 {
1162         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1163         int reg;
1164
1165         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1166                 return -EOPNOTSUPP;
1167
1168         mutex_lock(&chip->reg_lock);
1169
1170         reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1171         if (reg < 0)
1172                 goto out;
1173
1174         e->eee_enabled = !!(reg & 0x0200);
1175         e->tx_lpi_enabled = !!(reg & 0x0100);
1176
1177         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
1178         if (reg < 0)
1179                 goto out;
1180
1181         e->eee_active = !!(reg & PORT_STATUS_EEE);
1182         reg = 0;
1183
1184 out:
1185         mutex_unlock(&chip->reg_lock);
1186         return reg;
1187 }
1188
1189 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1190                              struct phy_device *phydev, struct ethtool_eee *e)
1191 {
1192         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1193         int reg;
1194         int ret;
1195
1196         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1197                 return -EOPNOTSUPP;
1198
1199         mutex_lock(&chip->reg_lock);
1200
1201         ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1202         if (ret < 0)
1203                 goto out;
1204
1205         reg = ret & ~0x0300;
1206         if (e->eee_enabled)
1207                 reg |= 0x0200;
1208         if (e->tx_lpi_enabled)
1209                 reg |= 0x0100;
1210
1211         ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
1212 out:
1213         mutex_unlock(&chip->reg_lock);
1214
1215         return ret;
1216 }
1217
1218 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1219 {
1220         int ret;
1221
1222         if (mv88e6xxx_has_fid_reg(chip)) {
1223                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1224                                            fid);
1225                 if (ret < 0)
1226                         return ret;
1227         } else if (mv88e6xxx_num_databases(chip) == 256) {
1228                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1229                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1230                 if (ret < 0)
1231                         return ret;
1232
1233                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1234                                            (ret & 0xfff) |
1235                                            ((fid << 8) & 0xf000));
1236                 if (ret < 0)
1237                         return ret;
1238
1239                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1240                 cmd |= fid & 0xf;
1241         }
1242
1243         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1244         if (ret < 0)
1245                 return ret;
1246
1247         return _mv88e6xxx_atu_wait(chip);
1248 }
1249
1250 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1251                                      struct mv88e6xxx_atu_entry *entry)
1252 {
1253         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1254
1255         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1256                 unsigned int mask, shift;
1257
1258                 if (entry->trunk) {
1259                         data |= GLOBAL_ATU_DATA_TRUNK;
1260                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1261                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1262                 } else {
1263                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1264                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1265                 }
1266
1267                 data |= (entry->portv_trunkid << shift) & mask;
1268         }
1269
1270         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1271 }
1272
1273 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1274                                      struct mv88e6xxx_atu_entry *entry,
1275                                      bool static_too)
1276 {
1277         int op;
1278         int err;
1279
1280         err = _mv88e6xxx_atu_wait(chip);
1281         if (err)
1282                 return err;
1283
1284         err = _mv88e6xxx_atu_data_write(chip, entry);
1285         if (err)
1286                 return err;
1287
1288         if (entry->fid) {
1289                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1290                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1291         } else {
1292                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1293                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1294         }
1295
1296         return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1297 }
1298
1299 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1300                                 u16 fid, bool static_too)
1301 {
1302         struct mv88e6xxx_atu_entry entry = {
1303                 .fid = fid,
1304                 .state = 0, /* EntryState bits must be 0 */
1305         };
1306
1307         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1308 }
1309
1310 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1311                                int from_port, int to_port, bool static_too)
1312 {
1313         struct mv88e6xxx_atu_entry entry = {
1314                 .trunk = false,
1315                 .fid = fid,
1316         };
1317
1318         /* EntryState bits must be 0xF */
1319         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1320
1321         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1322         entry.portv_trunkid = (to_port & 0x0f) << 4;
1323         entry.portv_trunkid |= from_port & 0x0f;
1324
1325         return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1326 }
1327
1328 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1329                                  int port, bool static_too)
1330 {
1331         /* Destination port 0xF means remove the entries */
1332         return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1333 }
1334
1335 static const char * const mv88e6xxx_port_state_names[] = {
1336         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1337         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1338         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1339         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1340 };
1341
1342 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1343                                  u8 state)
1344 {
1345         struct dsa_switch *ds = chip->ds;
1346         int reg, ret = 0;
1347         u8 oldstate;
1348
1349         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1350         if (reg < 0)
1351                 return reg;
1352
1353         oldstate = reg & PORT_CONTROL_STATE_MASK;
1354
1355         if (oldstate != state) {
1356                 /* Flush forwarding database if we're moving a port
1357                  * from Learning or Forwarding state to Disabled or
1358                  * Blocking or Listening state.
1359                  */
1360                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1361                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1362                     (state == PORT_CONTROL_STATE_DISABLED ||
1363                      state == PORT_CONTROL_STATE_BLOCKING)) {
1364                         ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1365                         if (ret)
1366                                 return ret;
1367                 }
1368
1369                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1370                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1371                                            reg);
1372                 if (ret)
1373                         return ret;
1374
1375                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1376                            mv88e6xxx_port_state_names[state],
1377                            mv88e6xxx_port_state_names[oldstate]);
1378         }
1379
1380         return ret;
1381 }
1382
1383 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1384 {
1385         struct net_device *bridge = chip->ports[port].bridge_dev;
1386         const u16 mask = (1 << chip->info->num_ports) - 1;
1387         struct dsa_switch *ds = chip->ds;
1388         u16 output_ports = 0;
1389         int reg;
1390         int i;
1391
1392         /* allow CPU port or DSA link(s) to send frames to every port */
1393         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1394                 output_ports = mask;
1395         } else {
1396                 for (i = 0; i < chip->info->num_ports; ++i) {
1397                         /* allow sending frames to every group member */
1398                         if (bridge && chip->ports[i].bridge_dev == bridge)
1399                                 output_ports |= BIT(i);
1400
1401                         /* allow sending frames to CPU port and DSA link(s) */
1402                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1403                                 output_ports |= BIT(i);
1404                 }
1405         }
1406
1407         /* prevent frames from going back out of the port they came in on */
1408         output_ports &= ~BIT(port);
1409
1410         reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1411         if (reg < 0)
1412                 return reg;
1413
1414         reg &= ~mask;
1415         reg |= output_ports & mask;
1416
1417         return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1418 }
1419
1420 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1421                                          u8 state)
1422 {
1423         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1424         int stp_state;
1425         int err;
1426
1427         switch (state) {
1428         case BR_STATE_DISABLED:
1429                 stp_state = PORT_CONTROL_STATE_DISABLED;
1430                 break;
1431         case BR_STATE_BLOCKING:
1432         case BR_STATE_LISTENING:
1433                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1434                 break;
1435         case BR_STATE_LEARNING:
1436                 stp_state = PORT_CONTROL_STATE_LEARNING;
1437                 break;
1438         case BR_STATE_FORWARDING:
1439         default:
1440                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1441                 break;
1442         }
1443
1444         mutex_lock(&chip->reg_lock);
1445         err = _mv88e6xxx_port_state(chip, port, stp_state);
1446         mutex_unlock(&chip->reg_lock);
1447
1448         if (err)
1449                 netdev_err(ds->ports[port].netdev,
1450                            "failed to update state to %s\n",
1451                            mv88e6xxx_port_state_names[stp_state]);
1452 }
1453
1454 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1455                                 u16 *new, u16 *old)
1456 {
1457         struct dsa_switch *ds = chip->ds;
1458         u16 pvid;
1459         int ret;
1460
1461         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1462         if (ret < 0)
1463                 return ret;
1464
1465         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1466
1467         if (new) {
1468                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1469                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1470
1471                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1472                                            PORT_DEFAULT_VLAN, ret);
1473                 if (ret < 0)
1474                         return ret;
1475
1476                 netdev_dbg(ds->ports[port].netdev,
1477                            "DefaultVID %d (was %d)\n", *new, pvid);
1478         }
1479
1480         if (old)
1481                 *old = pvid;
1482
1483         return 0;
1484 }
1485
1486 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1487                                     int port, u16 *pvid)
1488 {
1489         return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1490 }
1491
1492 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1493                                     int port, u16 pvid)
1494 {
1495         return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1496 }
1497
1498 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1499 {
1500         return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1501                                GLOBAL_VTU_OP_BUSY);
1502 }
1503
1504 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1505 {
1506         int ret;
1507
1508         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1509         if (ret < 0)
1510                 return ret;
1511
1512         return _mv88e6xxx_vtu_wait(chip);
1513 }
1514
1515 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1516 {
1517         int ret;
1518
1519         ret = _mv88e6xxx_vtu_wait(chip);
1520         if (ret < 0)
1521                 return ret;
1522
1523         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1524 }
1525
1526 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1527                                         struct mv88e6xxx_vtu_stu_entry *entry,
1528                                         unsigned int nibble_offset)
1529 {
1530         u16 regs[3];
1531         int i;
1532         int ret;
1533
1534         for (i = 0; i < 3; ++i) {
1535                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1536                                           GLOBAL_VTU_DATA_0_3 + i);
1537                 if (ret < 0)
1538                         return ret;
1539
1540                 regs[i] = ret;
1541         }
1542
1543         for (i = 0; i < chip->info->num_ports; ++i) {
1544                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1545                 u16 reg = regs[i / 4];
1546
1547                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1548         }
1549
1550         return 0;
1551 }
1552
1553 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1554                                    struct mv88e6xxx_vtu_stu_entry *entry)
1555 {
1556         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1557 }
1558
1559 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1560                                    struct mv88e6xxx_vtu_stu_entry *entry)
1561 {
1562         return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1563 }
1564
1565 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1566                                          struct mv88e6xxx_vtu_stu_entry *entry,
1567                                          unsigned int nibble_offset)
1568 {
1569         u16 regs[3] = { 0 };
1570         int i;
1571         int ret;
1572
1573         for (i = 0; i < chip->info->num_ports; ++i) {
1574                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1575                 u8 data = entry->data[i];
1576
1577                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1578         }
1579
1580         for (i = 0; i < 3; ++i) {
1581                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1582                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1583                 if (ret < 0)
1584                         return ret;
1585         }
1586
1587         return 0;
1588 }
1589
1590 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1591                                     struct mv88e6xxx_vtu_stu_entry *entry)
1592 {
1593         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1594 }
1595
1596 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1597                                     struct mv88e6xxx_vtu_stu_entry *entry)
1598 {
1599         return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1600 }
1601
1602 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1603 {
1604         return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1605                                     vid & GLOBAL_VTU_VID_MASK);
1606 }
1607
1608 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1609                                   struct mv88e6xxx_vtu_stu_entry *entry)
1610 {
1611         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1612         int ret;
1613
1614         ret = _mv88e6xxx_vtu_wait(chip);
1615         if (ret < 0)
1616                 return ret;
1617
1618         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1619         if (ret < 0)
1620                 return ret;
1621
1622         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1623         if (ret < 0)
1624                 return ret;
1625
1626         next.vid = ret & GLOBAL_VTU_VID_MASK;
1627         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1628
1629         if (next.valid) {
1630                 ret = mv88e6xxx_vtu_data_read(chip, &next);
1631                 if (ret < 0)
1632                         return ret;
1633
1634                 if (mv88e6xxx_has_fid_reg(chip)) {
1635                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1636                                                   GLOBAL_VTU_FID);
1637                         if (ret < 0)
1638                                 return ret;
1639
1640                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1641                 } else if (mv88e6xxx_num_databases(chip) == 256) {
1642                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1643                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1644                          */
1645                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1646                                                   GLOBAL_VTU_OP);
1647                         if (ret < 0)
1648                                 return ret;
1649
1650                         next.fid = (ret & 0xf00) >> 4;
1651                         next.fid |= ret & 0xf;
1652                 }
1653
1654                 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1655                         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1656                                                   GLOBAL_VTU_SID);
1657                         if (ret < 0)
1658                                 return ret;
1659
1660                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1661                 }
1662         }
1663
1664         *entry = next;
1665         return 0;
1666 }
1667
1668 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1669                                     struct switchdev_obj_port_vlan *vlan,
1670                                     int (*cb)(struct switchdev_obj *obj))
1671 {
1672         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1673         struct mv88e6xxx_vtu_stu_entry next;
1674         u16 pvid;
1675         int err;
1676
1677         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1678                 return -EOPNOTSUPP;
1679
1680         mutex_lock(&chip->reg_lock);
1681
1682         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1683         if (err)
1684                 goto unlock;
1685
1686         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1687         if (err)
1688                 goto unlock;
1689
1690         do {
1691                 err = _mv88e6xxx_vtu_getnext(chip, &next);
1692                 if (err)
1693                         break;
1694
1695                 if (!next.valid)
1696                         break;
1697
1698                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1699                         continue;
1700
1701                 /* reinit and dump this VLAN obj */
1702                 vlan->vid_begin = next.vid;
1703                 vlan->vid_end = next.vid;
1704                 vlan->flags = 0;
1705
1706                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1707                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1708
1709                 if (next.vid == pvid)
1710                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1711
1712                 err = cb(&vlan->obj);
1713                 if (err)
1714                         break;
1715         } while (next.vid < GLOBAL_VTU_VID_MASK);
1716
1717 unlock:
1718         mutex_unlock(&chip->reg_lock);
1719
1720         return err;
1721 }
1722
1723 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1724                                     struct mv88e6xxx_vtu_stu_entry *entry)
1725 {
1726         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1727         u16 reg = 0;
1728         int ret;
1729
1730         ret = _mv88e6xxx_vtu_wait(chip);
1731         if (ret < 0)
1732                 return ret;
1733
1734         if (!entry->valid)
1735                 goto loadpurge;
1736
1737         /* Write port member tags */
1738         ret = mv88e6xxx_vtu_data_write(chip, entry);
1739         if (ret < 0)
1740                 return ret;
1741
1742         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1743                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1744                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1745                                            reg);
1746                 if (ret < 0)
1747                         return ret;
1748         }
1749
1750         if (mv88e6xxx_has_fid_reg(chip)) {
1751                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1752                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1753                                            reg);
1754                 if (ret < 0)
1755                         return ret;
1756         } else if (mv88e6xxx_num_databases(chip) == 256) {
1757                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1758                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1759                  */
1760                 op |= (entry->fid & 0xf0) << 8;
1761                 op |= entry->fid & 0xf;
1762         }
1763
1764         reg = GLOBAL_VTU_VID_VALID;
1765 loadpurge:
1766         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1767         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1768         if (ret < 0)
1769                 return ret;
1770
1771         return _mv88e6xxx_vtu_cmd(chip, op);
1772 }
1773
1774 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1775                                   struct mv88e6xxx_vtu_stu_entry *entry)
1776 {
1777         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1778         int ret;
1779
1780         ret = _mv88e6xxx_vtu_wait(chip);
1781         if (ret < 0)
1782                 return ret;
1783
1784         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1785                                    sid & GLOBAL_VTU_SID_MASK);
1786         if (ret < 0)
1787                 return ret;
1788
1789         ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1790         if (ret < 0)
1791                 return ret;
1792
1793         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1794         if (ret < 0)
1795                 return ret;
1796
1797         next.sid = ret & GLOBAL_VTU_SID_MASK;
1798
1799         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1800         if (ret < 0)
1801                 return ret;
1802
1803         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1804
1805         if (next.valid) {
1806                 ret = mv88e6xxx_stu_data_read(chip, &next);
1807                 if (ret < 0)
1808                         return ret;
1809         }
1810
1811         *entry = next;
1812         return 0;
1813 }
1814
1815 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1816                                     struct mv88e6xxx_vtu_stu_entry *entry)
1817 {
1818         u16 reg = 0;
1819         int ret;
1820
1821         ret = _mv88e6xxx_vtu_wait(chip);
1822         if (ret < 0)
1823                 return ret;
1824
1825         if (!entry->valid)
1826                 goto loadpurge;
1827
1828         /* Write port states */
1829         ret = mv88e6xxx_stu_data_write(chip, entry);
1830         if (ret < 0)
1831                 return ret;
1832
1833         reg = GLOBAL_VTU_VID_VALID;
1834 loadpurge:
1835         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1836         if (ret < 0)
1837                 return ret;
1838
1839         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1840         ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1841         if (ret < 0)
1842                 return ret;
1843
1844         return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1845 }
1846
1847 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1848                                u16 *new, u16 *old)
1849 {
1850         struct dsa_switch *ds = chip->ds;
1851         u16 upper_mask;
1852         u16 fid;
1853         int ret;
1854
1855         if (mv88e6xxx_num_databases(chip) == 4096)
1856                 upper_mask = 0xff;
1857         else if (mv88e6xxx_num_databases(chip) == 256)
1858                 upper_mask = 0xf;
1859         else
1860                 return -EOPNOTSUPP;
1861
1862         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1863         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1864         if (ret < 0)
1865                 return ret;
1866
1867         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1868
1869         if (new) {
1870                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1871                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1872
1873                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1874                                            ret);
1875                 if (ret < 0)
1876                         return ret;
1877         }
1878
1879         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1880         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1881         if (ret < 0)
1882                 return ret;
1883
1884         fid |= (ret & upper_mask) << 4;
1885
1886         if (new) {
1887                 ret &= ~upper_mask;
1888                 ret |= (*new >> 4) & upper_mask;
1889
1890                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1891                                            ret);
1892                 if (ret < 0)
1893                         return ret;
1894
1895                 netdev_dbg(ds->ports[port].netdev,
1896                            "FID %d (was %d)\n", *new, fid);
1897         }
1898
1899         if (old)
1900                 *old = fid;
1901
1902         return 0;
1903 }
1904
1905 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1906                                    int port, u16 *fid)
1907 {
1908         return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1909 }
1910
1911 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1912                                    int port, u16 fid)
1913 {
1914         return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1915 }
1916
1917 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1918 {
1919         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1920         struct mv88e6xxx_vtu_stu_entry vlan;
1921         int i, err;
1922
1923         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1924
1925         /* Set every FID bit used by the (un)bridged ports */
1926         for (i = 0; i < chip->info->num_ports; ++i) {
1927                 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1928                 if (err)
1929                         return err;
1930
1931                 set_bit(*fid, fid_bitmap);
1932         }
1933
1934         /* Set every FID bit used by the VLAN entries */
1935         err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1936         if (err)
1937                 return err;
1938
1939         do {
1940                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1941                 if (err)
1942                         return err;
1943
1944                 if (!vlan.valid)
1945                         break;
1946
1947                 set_bit(vlan.fid, fid_bitmap);
1948         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1949
1950         /* The reset value 0x000 is used to indicate that multiple address
1951          * databases are not needed. Return the next positive available.
1952          */
1953         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1954         if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1955                 return -ENOSPC;
1956
1957         /* Clear the database */
1958         return _mv88e6xxx_atu_flush(chip, *fid, true);
1959 }
1960
1961 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1962                               struct mv88e6xxx_vtu_stu_entry *entry)
1963 {
1964         struct dsa_switch *ds = chip->ds;
1965         struct mv88e6xxx_vtu_stu_entry vlan = {
1966                 .valid = true,
1967                 .vid = vid,
1968         };
1969         int i, err;
1970
1971         err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1972         if (err)
1973                 return err;
1974
1975         /* exclude all ports except the CPU and DSA ports */
1976         for (i = 0; i < chip->info->num_ports; ++i)
1977                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1978                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1979                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1980
1981         if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1982             mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1983                 struct mv88e6xxx_vtu_stu_entry vstp;
1984
1985                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1986                  * implemented, only one STU entry is needed to cover all VTU
1987                  * entries. Thus, validate the SID 0.
1988                  */
1989                 vlan.sid = 0;
1990                 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1991                 if (err)
1992                         return err;
1993
1994                 if (vstp.sid != vlan.sid || !vstp.valid) {
1995                         memset(&vstp, 0, sizeof(vstp));
1996                         vstp.valid = true;
1997                         vstp.sid = vlan.sid;
1998
1999                         err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
2000                         if (err)
2001                                 return err;
2002                 }
2003         }
2004
2005         *entry = vlan;
2006         return 0;
2007 }
2008
2009 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2010                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
2011 {
2012         int err;
2013
2014         if (!vid)
2015                 return -EINVAL;
2016
2017         err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2018         if (err)
2019                 return err;
2020
2021         err = _mv88e6xxx_vtu_getnext(chip, entry);
2022         if (err)
2023                 return err;
2024
2025         if (entry->vid != vid || !entry->valid) {
2026                 if (!creat)
2027                         return -EOPNOTSUPP;
2028                 /* -ENOENT would've been more appropriate, but switchdev expects
2029                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
2030                  */
2031
2032                 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2033         }
2034
2035         return err;
2036 }
2037
2038 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2039                                         u16 vid_begin, u16 vid_end)
2040 {
2041         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2042         struct mv88e6xxx_vtu_stu_entry vlan;
2043         int i, err;
2044
2045         if (!vid_begin)
2046                 return -EOPNOTSUPP;
2047
2048         mutex_lock(&chip->reg_lock);
2049
2050         err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
2051         if (err)
2052                 goto unlock;
2053
2054         do {
2055                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2056                 if (err)
2057                         goto unlock;
2058
2059                 if (!vlan.valid)
2060                         break;
2061
2062                 if (vlan.vid > vid_end)
2063                         break;
2064
2065                 for (i = 0; i < chip->info->num_ports; ++i) {
2066                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2067                                 continue;
2068
2069                         if (vlan.data[i] ==
2070                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2071                                 continue;
2072
2073                         if (chip->ports[i].bridge_dev ==
2074                             chip->ports[port].bridge_dev)
2075                                 break; /* same bridge, check next VLAN */
2076
2077                         netdev_warn(ds->ports[port].netdev,
2078                                     "hardware VLAN %d already used by %s\n",
2079                                     vlan.vid,
2080                                     netdev_name(chip->ports[i].bridge_dev));
2081                         err = -EOPNOTSUPP;
2082                         goto unlock;
2083                 }
2084         } while (vlan.vid < vid_end);
2085
2086 unlock:
2087         mutex_unlock(&chip->reg_lock);
2088
2089         return err;
2090 }
2091
2092 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2093         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2094         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2095         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2096         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2097 };
2098
2099 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2100                                          bool vlan_filtering)
2101 {
2102         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2103         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2104                 PORT_CONTROL_2_8021Q_DISABLED;
2105         int ret;
2106
2107         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2108                 return -EOPNOTSUPP;
2109
2110         mutex_lock(&chip->reg_lock);
2111
2112         ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
2113         if (ret < 0)
2114                 goto unlock;
2115
2116         old = ret & PORT_CONTROL_2_8021Q_MASK;
2117
2118         if (new != old) {
2119                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2120                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2121
2122                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
2123                                            ret);
2124                 if (ret < 0)
2125                         goto unlock;
2126
2127                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
2128                            mv88e6xxx_port_8021q_mode_names[new],
2129                            mv88e6xxx_port_8021q_mode_names[old]);
2130         }
2131
2132         ret = 0;
2133 unlock:
2134         mutex_unlock(&chip->reg_lock);
2135
2136         return ret;
2137 }
2138
2139 static int
2140 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2141                             const struct switchdev_obj_port_vlan *vlan,
2142                             struct switchdev_trans *trans)
2143 {
2144         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2145         int err;
2146
2147         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2148                 return -EOPNOTSUPP;
2149
2150         /* If the requested port doesn't belong to the same bridge as the VLAN
2151          * members, do not support it (yet) and fallback to software VLAN.
2152          */
2153         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2154                                            vlan->vid_end);
2155         if (err)
2156                 return err;
2157
2158         /* We don't need any dynamic resource from the kernel (yet),
2159          * so skip the prepare phase.
2160          */
2161         return 0;
2162 }
2163
2164 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
2165                                     u16 vid, bool untagged)
2166 {
2167         struct mv88e6xxx_vtu_stu_entry vlan;
2168         int err;
2169
2170         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
2171         if (err)
2172                 return err;
2173
2174         vlan.data[port] = untagged ?
2175                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2176                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2177
2178         return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2179 }
2180
2181 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2182                                     const struct switchdev_obj_port_vlan *vlan,
2183                                     struct switchdev_trans *trans)
2184 {
2185         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2186         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2187         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2188         u16 vid;
2189
2190         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2191                 return;
2192
2193         mutex_lock(&chip->reg_lock);
2194
2195         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2196                 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
2197                         netdev_err(ds->ports[port].netdev,
2198                                    "failed to add VLAN %d%c\n",
2199                                    vid, untagged ? 'u' : 't');
2200
2201         if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
2202                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
2203                            vlan->vid_end);
2204
2205         mutex_unlock(&chip->reg_lock);
2206 }
2207
2208 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
2209                                     int port, u16 vid)
2210 {
2211         struct dsa_switch *ds = chip->ds;
2212         struct mv88e6xxx_vtu_stu_entry vlan;
2213         int i, err;
2214
2215         err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2216         if (err)
2217                 return err;
2218
2219         /* Tell switchdev if this VLAN is handled in software */
2220         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2221                 return -EOPNOTSUPP;
2222
2223         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2224
2225         /* keep the VLAN unless all ports are excluded */
2226         vlan.valid = false;
2227         for (i = 0; i < chip->info->num_ports; ++i) {
2228                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2229                         continue;
2230
2231                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2232                         vlan.valid = true;
2233                         break;
2234                 }
2235         }
2236
2237         err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2238         if (err)
2239                 return err;
2240
2241         return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2242 }
2243
2244 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2245                                    const struct switchdev_obj_port_vlan *vlan)
2246 {
2247         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2248         u16 pvid, vid;
2249         int err = 0;
2250
2251         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2252                 return -EOPNOTSUPP;
2253
2254         mutex_lock(&chip->reg_lock);
2255
2256         err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2257         if (err)
2258                 goto unlock;
2259
2260         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2261                 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2262                 if (err)
2263                         goto unlock;
2264
2265                 if (vid == pvid) {
2266                         err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2267                         if (err)
2268                                 goto unlock;
2269                 }
2270         }
2271
2272 unlock:
2273         mutex_unlock(&chip->reg_lock);
2274
2275         return err;
2276 }
2277
2278 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2279                                     const unsigned char *addr)
2280 {
2281         int i, ret;
2282
2283         for (i = 0; i < 3; i++) {
2284                 ret = _mv88e6xxx_reg_write(
2285                         chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2286                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2287                 if (ret < 0)
2288                         return ret;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2295                                    unsigned char *addr)
2296 {
2297         int i, ret;
2298
2299         for (i = 0; i < 3; i++) {
2300                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2301                                           GLOBAL_ATU_MAC_01 + i);
2302                 if (ret < 0)
2303                         return ret;
2304                 addr[i * 2] = ret >> 8;
2305                 addr[i * 2 + 1] = ret & 0xff;
2306         }
2307
2308         return 0;
2309 }
2310
2311 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2312                                struct mv88e6xxx_atu_entry *entry)
2313 {
2314         int ret;
2315
2316         ret = _mv88e6xxx_atu_wait(chip);
2317         if (ret < 0)
2318                 return ret;
2319
2320         ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2321         if (ret < 0)
2322                 return ret;
2323
2324         ret = _mv88e6xxx_atu_data_write(chip, entry);
2325         if (ret < 0)
2326                 return ret;
2327
2328         return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2329 }
2330
2331 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2332                                     const unsigned char *addr, u16 vid,
2333                                     u8 state)
2334 {
2335         struct mv88e6xxx_atu_entry entry = { 0 };
2336         struct mv88e6xxx_vtu_stu_entry vlan;
2337         int err;
2338
2339         /* Null VLAN ID corresponds to the port private database */
2340         if (vid == 0)
2341                 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2342         else
2343                 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2344         if (err)
2345                 return err;
2346
2347         entry.fid = vlan.fid;
2348         entry.state = state;
2349         ether_addr_copy(entry.mac, addr);
2350         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2351                 entry.trunk = false;
2352                 entry.portv_trunkid = BIT(port);
2353         }
2354
2355         return _mv88e6xxx_atu_load(chip, &entry);
2356 }
2357
2358 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2359                                       const struct switchdev_obj_port_fdb *fdb,
2360                                       struct switchdev_trans *trans)
2361 {
2362         /* We don't need any dynamic resource from the kernel (yet),
2363          * so skip the prepare phase.
2364          */
2365         return 0;
2366 }
2367
2368 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2369                                    const struct switchdev_obj_port_fdb *fdb,
2370                                    struct switchdev_trans *trans)
2371 {
2372         int state = is_multicast_ether_addr(fdb->addr) ?
2373                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2374                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2375         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2376
2377         mutex_lock(&chip->reg_lock);
2378         if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2379                 netdev_err(ds->ports[port].netdev,
2380                            "failed to load MAC address\n");
2381         mutex_unlock(&chip->reg_lock);
2382 }
2383
2384 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2385                                   const struct switchdev_obj_port_fdb *fdb)
2386 {
2387         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2388         int ret;
2389
2390         mutex_lock(&chip->reg_lock);
2391         ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2392                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2393         mutex_unlock(&chip->reg_lock);
2394
2395         return ret;
2396 }
2397
2398 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2399                                   struct mv88e6xxx_atu_entry *entry)
2400 {
2401         struct mv88e6xxx_atu_entry next = { 0 };
2402         int ret;
2403
2404         next.fid = fid;
2405
2406         ret = _mv88e6xxx_atu_wait(chip);
2407         if (ret < 0)
2408                 return ret;
2409
2410         ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2411         if (ret < 0)
2412                 return ret;
2413
2414         ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2415         if (ret < 0)
2416                 return ret;
2417
2418         ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2419         if (ret < 0)
2420                 return ret;
2421
2422         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2423         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2424                 unsigned int mask, shift;
2425
2426                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2427                         next.trunk = true;
2428                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2429                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2430                 } else {
2431                         next.trunk = false;
2432                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2433                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2434                 }
2435
2436                 next.portv_trunkid = (ret & mask) >> shift;
2437         }
2438
2439         *entry = next;
2440         return 0;
2441 }
2442
2443 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2444                                         u16 fid, u16 vid, int port,
2445                                         struct switchdev_obj_port_fdb *fdb,
2446                                         int (*cb)(struct switchdev_obj *obj))
2447 {
2448         struct mv88e6xxx_atu_entry addr = {
2449                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2450         };
2451         int err;
2452
2453         err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2454         if (err)
2455                 return err;
2456
2457         do {
2458                 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2459                 if (err)
2460                         break;
2461
2462                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2463                         break;
2464
2465                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2466                         bool is_static = addr.state ==
2467                                 (is_multicast_ether_addr(addr.mac) ?
2468                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2469                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2470
2471                         fdb->vid = vid;
2472                         ether_addr_copy(fdb->addr, addr.mac);
2473                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2474
2475                         err = cb(&fdb->obj);
2476                         if (err)
2477                                 break;
2478                 }
2479         } while (!is_broadcast_ether_addr(addr.mac));
2480
2481         return err;
2482 }
2483
2484 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2485                                    struct switchdev_obj_port_fdb *fdb,
2486                                    int (*cb)(struct switchdev_obj *obj))
2487 {
2488         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2489         struct mv88e6xxx_vtu_stu_entry vlan = {
2490                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2491         };
2492         u16 fid;
2493         int err;
2494
2495         mutex_lock(&chip->reg_lock);
2496
2497         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2498         err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2499         if (err)
2500                 goto unlock;
2501
2502         err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2503         if (err)
2504                 goto unlock;
2505
2506         /* Dump VLANs' Filtering Information Databases */
2507         err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2508         if (err)
2509                 goto unlock;
2510
2511         do {
2512                 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2513                 if (err)
2514                         break;
2515
2516                 if (!vlan.valid)
2517                         break;
2518
2519                 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2520                                                    port, fdb, cb);
2521                 if (err)
2522                         break;
2523         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2524
2525 unlock:
2526         mutex_unlock(&chip->reg_lock);
2527
2528         return err;
2529 }
2530
2531 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2532                                       struct net_device *bridge)
2533 {
2534         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2535         int i, err = 0;
2536
2537         mutex_lock(&chip->reg_lock);
2538
2539         /* Assign the bridge and remap each port's VLANTable */
2540         chip->ports[port].bridge_dev = bridge;
2541
2542         for (i = 0; i < chip->info->num_ports; ++i) {
2543                 if (chip->ports[i].bridge_dev == bridge) {
2544                         err = _mv88e6xxx_port_based_vlan_map(chip, i);
2545                         if (err)
2546                                 break;
2547                 }
2548         }
2549
2550         mutex_unlock(&chip->reg_lock);
2551
2552         return err;
2553 }
2554
2555 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2556 {
2557         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2558         struct net_device *bridge = chip->ports[port].bridge_dev;
2559         int i;
2560
2561         mutex_lock(&chip->reg_lock);
2562
2563         /* Unassign the bridge and remap each port's VLANTable */
2564         chip->ports[port].bridge_dev = NULL;
2565
2566         for (i = 0; i < chip->info->num_ports; ++i)
2567                 if (i == port || chip->ports[i].bridge_dev == bridge)
2568                         if (_mv88e6xxx_port_based_vlan_map(chip, i))
2569                                 netdev_warn(ds->ports[i].netdev,
2570                                             "failed to remap\n");
2571
2572         mutex_unlock(&chip->reg_lock);
2573 }
2574
2575 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2576                                       int port, int page, int reg, int val)
2577 {
2578         int ret;
2579
2580         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2581         if (ret < 0)
2582                 goto restore_page_0;
2583
2584         ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2585 restore_page_0:
2586         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2587
2588         return ret;
2589 }
2590
2591 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2592                                      int port, int page, int reg)
2593 {
2594         int ret;
2595
2596         ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2597         if (ret < 0)
2598                 goto restore_page_0;
2599
2600         ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2601 restore_page_0:
2602         mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2603
2604         return ret;
2605 }
2606
2607 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2608 {
2609         bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2610         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2611         struct gpio_desc *gpiod = chip->reset;
2612         unsigned long timeout;
2613         int ret;
2614         int i;
2615
2616         /* Set all ports to the disabled state. */
2617         for (i = 0; i < chip->info->num_ports; i++) {
2618                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2619                 if (ret < 0)
2620                         return ret;
2621
2622                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2623                                            ret & 0xfffc);
2624                 if (ret)
2625                         return ret;
2626         }
2627
2628         /* Wait for transmit queues to drain. */
2629         usleep_range(2000, 4000);
2630
2631         /* If there is a gpio connected to the reset pin, toggle it */
2632         if (gpiod) {
2633                 gpiod_set_value_cansleep(gpiod, 1);
2634                 usleep_range(10000, 20000);
2635                 gpiod_set_value_cansleep(gpiod, 0);
2636                 usleep_range(10000, 20000);
2637         }
2638
2639         /* Reset the switch. Keep the PPU active if requested. The PPU
2640          * needs to be active to support indirect phy register access
2641          * through global registers 0x18 and 0x19.
2642          */
2643         if (ppu_active)
2644                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2645         else
2646                 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2647         if (ret)
2648                 return ret;
2649
2650         /* Wait up to one second for reset to complete. */
2651         timeout = jiffies + 1 * HZ;
2652         while (time_before(jiffies, timeout)) {
2653                 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2654                 if (ret < 0)
2655                         return ret;
2656
2657                 if ((ret & is_reset) == is_reset)
2658                         break;
2659                 usleep_range(1000, 2000);
2660         }
2661         if (time_after(jiffies, timeout))
2662                 ret = -ETIMEDOUT;
2663         else
2664                 ret = 0;
2665
2666         return ret;
2667 }
2668
2669 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2670 {
2671         int ret;
2672
2673         ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2674                                         PAGE_FIBER_SERDES, MII_BMCR);
2675         if (ret < 0)
2676                 return ret;
2677
2678         if (ret & BMCR_PDOWN) {
2679                 ret &= ~BMCR_PDOWN;
2680                 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2681                                                  PAGE_FIBER_SERDES, MII_BMCR,
2682                                                  ret);
2683         }
2684
2685         return ret;
2686 }
2687
2688 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2689 {
2690         struct dsa_switch *ds = chip->ds;
2691         int ret;
2692         u16 reg;
2693
2694         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2695             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2696             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2697             mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2698                 /* MAC Forcing register: don't force link, speed,
2699                  * duplex or flow control state to any particular
2700                  * values on physical ports, but force the CPU port
2701                  * and all DSA ports to their maximum bandwidth and
2702                  * full duplex.
2703                  */
2704                 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2705                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2706                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2707                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2708                                 PORT_PCS_CTRL_LINK_UP |
2709                                 PORT_PCS_CTRL_DUPLEX_FULL |
2710                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2711                         if (mv88e6xxx_6065_family(chip))
2712                                 reg |= PORT_PCS_CTRL_100;
2713                         else
2714                                 reg |= PORT_PCS_CTRL_1000;
2715                 } else {
2716                         reg |= PORT_PCS_CTRL_UNFORCED;
2717                 }
2718
2719                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2720                                            PORT_PCS_CTRL, reg);
2721                 if (ret)
2722                         return ret;
2723         }
2724
2725         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2726          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2727          * tunneling, determine priority by looking at 802.1p and IP
2728          * priority fields (IP prio has precedence), and set STP state
2729          * to Forwarding.
2730          *
2731          * If this is the CPU link, use DSA or EDSA tagging depending
2732          * on which tagging mode was configured.
2733          *
2734          * If this is a link to another switch, use DSA tagging mode.
2735          *
2736          * If this is the upstream port for this switch, enable
2737          * forwarding of unknown unicasts and multicasts.
2738          */
2739         reg = 0;
2740         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2741             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2742             mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2743             mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2744                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2745                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2746                 PORT_CONTROL_STATE_FORWARDING;
2747         if (dsa_is_cpu_port(ds, port)) {
2748                 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2749                         reg |= PORT_CONTROL_DSA_TAG;
2750                 if (mv88e6xxx_6352_family(chip) ||
2751                     mv88e6xxx_6351_family(chip) ||
2752                     mv88e6xxx_6165_family(chip) ||
2753                     mv88e6xxx_6097_family(chip) ||
2754                     mv88e6xxx_6320_family(chip)) {
2755                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2756                                 PORT_CONTROL_FORWARD_UNKNOWN |
2757                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2758                 }
2759
2760                 if (mv88e6xxx_6352_family(chip) ||
2761                     mv88e6xxx_6351_family(chip) ||
2762                     mv88e6xxx_6165_family(chip) ||
2763                     mv88e6xxx_6097_family(chip) ||
2764                     mv88e6xxx_6095_family(chip) ||
2765                     mv88e6xxx_6065_family(chip) ||
2766                     mv88e6xxx_6185_family(chip) ||
2767                     mv88e6xxx_6320_family(chip)) {
2768                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2769                 }
2770         }
2771         if (dsa_is_dsa_port(ds, port)) {
2772                 if (mv88e6xxx_6095_family(chip) ||
2773                     mv88e6xxx_6185_family(chip))
2774                         reg |= PORT_CONTROL_DSA_TAG;
2775                 if (mv88e6xxx_6352_family(chip) ||
2776                     mv88e6xxx_6351_family(chip) ||
2777                     mv88e6xxx_6165_family(chip) ||
2778                     mv88e6xxx_6097_family(chip) ||
2779                     mv88e6xxx_6320_family(chip)) {
2780                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2781                 }
2782
2783                 if (port == dsa_upstream_port(ds))
2784                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2785                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2786         }
2787         if (reg) {
2788                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2789                                            PORT_CONTROL, reg);
2790                 if (ret)
2791                         return ret;
2792         }
2793
2794         /* If this port is connected to a SerDes, make sure the SerDes is not
2795          * powered down.
2796          */
2797         if (mv88e6xxx_6352_family(chip)) {
2798                 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2799                 if (ret < 0)
2800                         return ret;
2801                 ret &= PORT_STATUS_CMODE_MASK;
2802                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2803                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2804                     (ret == PORT_STATUS_CMODE_SGMII)) {
2805                         ret = mv88e6xxx_power_on_serdes(chip);
2806                         if (ret < 0)
2807                                 return ret;
2808                 }
2809         }
2810
2811         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2812          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2813          * untagged frames on this port, do a destination address lookup on all
2814          * received packets as usual, disable ARP mirroring and don't send a
2815          * copy of all transmitted/received frames on this port to the CPU.
2816          */
2817         reg = 0;
2818         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2819             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2820             mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2821             mv88e6xxx_6185_family(chip))
2822                 reg = PORT_CONTROL_2_MAP_DA;
2823
2824         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2825             mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2826                 reg |= PORT_CONTROL_2_JUMBO_10240;
2827
2828         if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2829                 /* Set the upstream port this port should use */
2830                 reg |= dsa_upstream_port(ds);
2831                 /* enable forwarding of unknown multicast addresses to
2832                  * the upstream port
2833                  */
2834                 if (port == dsa_upstream_port(ds))
2835                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2836         }
2837
2838         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2839
2840         if (reg) {
2841                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2842                                            PORT_CONTROL_2, reg);
2843                 if (ret)
2844                         return ret;
2845         }
2846
2847         /* Port Association Vector: when learning source addresses
2848          * of packets, add the address to the address database using
2849          * a port bitmap that has only the bit for this port set and
2850          * the other bits clear.
2851          */
2852         reg = 1 << port;
2853         /* Disable learning for CPU port */
2854         if (dsa_is_cpu_port(ds, port))
2855                 reg = 0;
2856
2857         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2858                                    reg);
2859         if (ret)
2860                 return ret;
2861
2862         /* Egress rate control 2: disable egress rate control. */
2863         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2864                                    0x0000);
2865         if (ret)
2866                 return ret;
2867
2868         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2869             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2870             mv88e6xxx_6320_family(chip)) {
2871                 /* Do not limit the period of time that this port can
2872                  * be paused for by the remote end or the period of
2873                  * time that this port can pause the remote end.
2874                  */
2875                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2876                                            PORT_PAUSE_CTRL, 0x0000);
2877                 if (ret)
2878                         return ret;
2879
2880                 /* Port ATU control: disable limiting the number of
2881                  * address database entries that this port is allowed
2882                  * to use.
2883                  */
2884                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2885                                            PORT_ATU_CONTROL, 0x0000);
2886                 /* Priority Override: disable DA, SA and VTU priority
2887                  * override.
2888                  */
2889                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2890                                            PORT_PRI_OVERRIDE, 0x0000);
2891                 if (ret)
2892                         return ret;
2893
2894                 /* Port Ethertype: use the Ethertype DSA Ethertype
2895                  * value.
2896                  */
2897                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2898                                            PORT_ETH_TYPE, ETH_P_EDSA);
2899                 if (ret)
2900                         return ret;
2901                 /* Tag Remap: use an identity 802.1p prio -> switch
2902                  * prio mapping.
2903                  */
2904                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2905                                            PORT_TAG_REGMAP_0123, 0x3210);
2906                 if (ret)
2907                         return ret;
2908
2909                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2910                  * prio mapping.
2911                  */
2912                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2913                                            PORT_TAG_REGMAP_4567, 0x7654);
2914                 if (ret)
2915                         return ret;
2916         }
2917
2918         if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2919             mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2920             mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2921             mv88e6xxx_6320_family(chip)) {
2922                 /* Rate Control: disable ingress rate limiting. */
2923                 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2924                                            PORT_RATE_CONTROL, 0x0001);
2925                 if (ret)
2926                         return ret;
2927         }
2928
2929         /* Port Control 1: disable trunking, disable sending
2930          * learning messages to this port.
2931          */
2932         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2933                                    0x0000);
2934         if (ret)
2935                 return ret;
2936
2937         /* Port based VLAN map: give each port the same default address
2938          * database, and allow bidirectional communication between the
2939          * CPU and DSA port(s), and the other ports.
2940          */
2941         ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2942         if (ret)
2943                 return ret;
2944
2945         ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2946         if (ret)
2947                 return ret;
2948
2949         /* Default VLAN ID and priority: don't set a default VLAN
2950          * ID, and set the default packet priority to zero.
2951          */
2952         ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
2953                                    0x0000);
2954         if (ret)
2955                 return ret;
2956
2957         return 0;
2958 }
2959
2960 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2961 {
2962         int err;
2963
2964         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2965                               (addr[0] << 8) | addr[1]);
2966         if (err)
2967                 return err;
2968
2969         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2970                               (addr[2] << 8) | addr[3]);
2971         if (err)
2972                 return err;
2973
2974         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2975                                (addr[4] << 8) | addr[5]);
2976 }
2977
2978 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2979                                      unsigned int msecs)
2980 {
2981         const unsigned int coeff = chip->info->age_time_coeff;
2982         const unsigned int min = 0x01 * coeff;
2983         const unsigned int max = 0xff * coeff;
2984         u8 age_time;
2985         u16 val;
2986         int err;
2987
2988         if (msecs < min || msecs > max)
2989                 return -ERANGE;
2990
2991         /* Round to nearest multiple of coeff */
2992         age_time = (msecs + coeff / 2) / coeff;
2993
2994         err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2995         if (err)
2996                 return err;
2997
2998         /* AgeTime is 11:4 bits */
2999         val &= ~0xff0;
3000         val |= age_time << 4;
3001
3002         return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
3003 }
3004
3005 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
3006                                      unsigned int ageing_time)
3007 {
3008         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3009         int err;
3010
3011         mutex_lock(&chip->reg_lock);
3012         err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
3013         mutex_unlock(&chip->reg_lock);
3014
3015         return err;
3016 }
3017
3018 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
3019 {
3020         struct dsa_switch *ds = chip->ds;
3021         u32 upstream_port = dsa_upstream_port(ds);
3022         u16 reg;
3023         int err;
3024
3025         /* Enable the PHY Polling Unit if present, don't discard any packets,
3026          * and mask all interrupt sources.
3027          */
3028         reg = 0;
3029         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
3030             mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
3031                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
3032
3033         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
3034         if (err)
3035                 return err;
3036
3037         /* Configure the upstream port, and configure it as the port to which
3038          * ingress and egress and ARP monitor frames are to be sent.
3039          */
3040         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
3041                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
3042                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
3043         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
3044                                    reg);
3045         if (err)
3046                 return err;
3047
3048         /* Disable remote management, and set the switch's DSA device number. */
3049         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
3050                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
3051                                    (ds->index & 0x1f));
3052         if (err)
3053                 return err;
3054
3055         /* Clear all the VTU and STU entries */
3056         err = _mv88e6xxx_vtu_stu_flush(chip);
3057         if (err < 0)
3058                 return err;
3059
3060         /* Set the default address aging time to 5 minutes, and
3061          * enable address learn messages to be sent to all message
3062          * ports.
3063          */
3064         err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
3065                               GLOBAL_ATU_CONTROL_LEARN2ALL);
3066         if (err)
3067                 return err;
3068
3069         err = mv88e6xxx_g1_set_age_time(chip, 300000);
3070         if (err)
3071                 return err;
3072
3073         /* Clear all ATU entries */
3074         err = _mv88e6xxx_atu_flush(chip, 0, true);
3075         if (err)
3076                 return err;
3077
3078         /* Configure the IP ToS mapping registers. */
3079         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
3080         if (err)
3081                 return err;
3082         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
3083         if (err)
3084                 return err;
3085         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
3086         if (err)
3087                 return err;
3088         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
3089         if (err)
3090                 return err;
3091         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
3092         if (err)
3093                 return err;
3094         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
3095         if (err)
3096                 return err;
3097         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
3098         if (err)
3099                 return err;
3100         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
3101         if (err)
3102                 return err;
3103
3104         /* Configure the IEEE 802.1p priority mapping register. */
3105         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
3106         if (err)
3107                 return err;
3108
3109         /* Clear the statistics counters for all ports */
3110         err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
3111                                    GLOBAL_STATS_OP_FLUSH_ALL);
3112         if (err)
3113                 return err;
3114
3115         /* Wait for the flush to complete. */
3116         err = _mv88e6xxx_stats_wait(chip);
3117         if (err)
3118                 return err;
3119
3120         return 0;
3121 }
3122
3123 static int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
3124                                              int target, int port)
3125 {
3126         u16 val = (target << 8) | (port & 0xf);
3127
3128         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING, val);
3129 }
3130
3131 static int mv88e6xxx_g2_set_device_mapping(struct mv88e6xxx_chip *chip)
3132 {
3133         int target, port;
3134         int err;
3135
3136         /* Initialize the routing port to the 32 possible target devices */
3137         for (target = 0; target < 32; ++target) {
3138                 port = 0xf;
3139
3140                 if (target < DSA_MAX_SWITCHES) {
3141                         port = chip->ds->rtable[target];
3142                         if (port == DSA_RTABLE_NONE)
3143                                 port = 0xf;
3144                 }
3145
3146                 err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
3147                 if (err)
3148                         break;
3149         }
3150
3151         return err;
3152 }
3153
3154 static int mv88e6xxx_g2_trunk_mask_write(struct mv88e6xxx_chip *chip, int num,
3155                                          bool hask, u16 mask)
3156 {
3157         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3158         u16 val = (num << 12) | (mask & port_mask);
3159
3160         if (hask)
3161                 val |= GLOBAL2_TRUNK_MASK_HASK;
3162
3163         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, val);
3164 }
3165
3166 static int mv88e6xxx_g2_trunk_mapping_write(struct mv88e6xxx_chip *chip, int id,
3167                                             u16 map)
3168 {
3169         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3170         u16 val = (id << 11) | (map & port_mask);
3171
3172         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING, val);
3173 }
3174
3175 static int mv88e6xxx_g2_clear_trunk(struct mv88e6xxx_chip *chip)
3176 {
3177         const u16 port_mask = BIT(chip->info->num_ports) - 1;
3178         int i, err;
3179
3180         /* Clear all eight possible Trunk Mask vectors */
3181         for (i = 0; i < 8; ++i) {
3182                 err = mv88e6xxx_g2_trunk_mask_write(chip, i, false, port_mask);
3183                 if (err)
3184                         return err;
3185         }
3186
3187         /* Clear all sixteen possible Trunk ID routing vectors */
3188         for (i = 0; i < 16; ++i) {
3189                 err = mv88e6xxx_g2_trunk_mapping_write(chip, i, 0);
3190                 if (err)
3191                         return err;
3192         }
3193
3194         return 0;
3195 }
3196
3197 static int mv88e6xxx_g2_clear_irl(struct mv88e6xxx_chip *chip)
3198 {
3199         int port, err;
3200
3201         /* Init all Ingress Rate Limit resources of all ports */
3202         for (port = 0; port < chip->info->num_ports; ++port) {
3203                 /* XXX newer chips (like 88E6390) have different 2-bit ops */
3204                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
3205                                       GLOBAL2_IRL_CMD_OP_INIT_ALL |
3206                                       (port << 8));
3207                 if (err)
3208                         break;
3209
3210                 /* Wait for the operation to complete */
3211                 err = _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_IRL_CMD,
3212                                       GLOBAL2_IRL_CMD_BUSY);
3213                 if (err)
3214                         break;
3215         }
3216
3217         return err;
3218 }
3219
3220 /* Indirect write to the Switch MAC/WoL/WoF register */
3221 static int mv88e6xxx_g2_switch_mac_write(struct mv88e6xxx_chip *chip,
3222                                          unsigned int pointer, u8 data)
3223 {
3224         u16 val = (pointer << 8) | data;
3225
3226         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, val);
3227 }
3228
3229 static int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
3230 {
3231         int i, err;
3232
3233         for (i = 0; i < 6; i++) {
3234                 err = mv88e6xxx_g2_switch_mac_write(chip, i, addr[i]);
3235                 if (err)
3236                         break;
3237         }
3238
3239         return err;
3240 }
3241
3242 static int mv88e6xxx_g2_pot_write(struct mv88e6xxx_chip *chip, int pointer,
3243                                   u8 data)
3244 {
3245         u16 val = (pointer << 8) | (data & 0x7);
3246
3247         return mv88e6xxx_update(chip, REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE, val);
3248 }
3249
3250 static int mv88e6xxx_g2_clear_pot(struct mv88e6xxx_chip *chip)
3251 {
3252         int i, err;
3253
3254         /* Clear all sixteen possible Priority Override entries */
3255         for (i = 0; i < 16; i++) {
3256                 err = mv88e6xxx_g2_pot_write(chip, i, 0);
3257                 if (err)
3258                         break;
3259         }
3260
3261         return err;
3262 }
3263
3264 static int mv88e6xxx_g2_setup(struct mv88e6xxx_chip *chip)
3265 {
3266         u16 reg;
3267         int err;
3268
3269         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X)) {
3270                 /* Consider the frames with reserved multicast destination
3271                  * addresses matching 01:80:c2:00:00:2x as MGMT.
3272                  */
3273                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_2X,
3274                                       0xffff);
3275                 if (err)
3276                         return err;
3277         }
3278
3279         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X)) {
3280                 /* Consider the frames with reserved multicast destination
3281                  * addresses matching 01:80:c2:00:00:0x as MGMT.
3282                  */
3283                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3284                                       0xffff);
3285                 if (err)
3286                         return err;
3287         }
3288
3289         /* Ignore removed tag data on doubly tagged packets, disable
3290          * flow control messages, force flow control priority to the
3291          * highest, and send all special multicast frames to the CPU
3292          * port at the highest priority.
3293          */
3294         reg = GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI | (0x7 << 4);
3295         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_0X) ||
3296             mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_MGMT_EN_2X))
3297                 reg |= GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x7;
3298         err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, reg);
3299         if (err)
3300                 return err;
3301
3302         /* Program the DSA routing table. */
3303         err = mv88e6xxx_g2_set_device_mapping(chip);
3304         if (err)
3305                 return err;
3306
3307         /* Clear all trunk masks and mapping. */
3308         err = mv88e6xxx_g2_clear_trunk(chip);
3309         if (err)
3310                 return err;
3311
3312         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_IRL)) {
3313                 /* Disable ingress rate limiting by resetting all per port
3314                  * ingress rate limit resources to their initial state.
3315                  */
3316                 err = mv88e6xxx_g2_clear_irl(chip);
3317                         if (err)
3318                                 return err;
3319         }
3320
3321         if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_PVT)) {
3322                 /* Initialize Cross-chip Port VLAN Table to reset defaults */
3323                 err = mv88e6xxx_write(chip, REG_GLOBAL2, GLOBAL2_PVT_ADDR,
3324                                       GLOBAL2_PVT_ADDR_OP_INIT_ONES);
3325                 if (err)
3326                         return err;
3327         }
3328
3329         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_POT)) {
3330                 /* Clear the priority override table. */
3331                 err = mv88e6xxx_g2_clear_pot(chip);
3332                 if (err)
3333                         return err;
3334         }
3335
3336         return 0;
3337 }
3338
3339 static int mv88e6xxx_setup(struct dsa_switch *ds)
3340 {
3341         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3342         int err;
3343         int i;
3344
3345         chip->ds = ds;
3346         ds->slave_mii_bus = chip->mdio_bus;
3347
3348         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
3349                 mutex_init(&chip->eeprom_mutex);
3350
3351         mutex_lock(&chip->reg_lock);
3352
3353         err = mv88e6xxx_switch_reset(chip);
3354         if (err)
3355                 goto unlock;
3356
3357         /* Setup Switch Port Registers */
3358         for (i = 0; i < chip->info->num_ports; i++) {
3359                 err = mv88e6xxx_setup_port(chip, i);
3360                 if (err)
3361                         goto unlock;
3362         }
3363
3364         /* Setup Switch Global 1 Registers */
3365         err = mv88e6xxx_g1_setup(chip);
3366         if (err)
3367                 goto unlock;
3368
3369         /* Setup Switch Global 2 Registers */
3370         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
3371                 err = mv88e6xxx_g2_setup(chip);
3372                 if (err)
3373                         goto unlock;
3374         }
3375
3376 unlock:
3377         mutex_unlock(&chip->reg_lock);
3378
3379         return err;
3380 }
3381
3382 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
3383 {
3384         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3385         int err;
3386
3387         mutex_lock(&chip->reg_lock);
3388
3389         /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
3390         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
3391                 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
3392         else
3393                 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
3394
3395         mutex_unlock(&chip->reg_lock);
3396
3397         return err;
3398 }
3399
3400 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3401                                     int reg)
3402 {
3403         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3404         int ret;
3405
3406         mutex_lock(&chip->reg_lock);
3407         ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3408         mutex_unlock(&chip->reg_lock);
3409
3410         return ret;
3411 }
3412
3413 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3414                                      int reg, int val)
3415 {
3416         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3417         int ret;
3418
3419         mutex_lock(&chip->reg_lock);
3420         ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3421         mutex_unlock(&chip->reg_lock);
3422
3423         return ret;
3424 }
3425
3426 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3427 {
3428         if (port >= 0 && port < chip->info->num_ports)
3429                 return port;
3430         return -EINVAL;
3431 }
3432
3433 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3434 {
3435         struct mv88e6xxx_chip *chip = bus->priv;
3436         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3437         int ret;
3438
3439         if (addr < 0)
3440                 return 0xffff;
3441
3442         mutex_lock(&chip->reg_lock);
3443
3444         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3445                 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3446         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3447                 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3448         else
3449                 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3450
3451         mutex_unlock(&chip->reg_lock);
3452         return ret;
3453 }
3454
3455 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3456                                 u16 val)
3457 {
3458         struct mv88e6xxx_chip *chip = bus->priv;
3459         int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3460         int ret;
3461
3462         if (addr < 0)
3463                 return 0xffff;
3464
3465         mutex_lock(&chip->reg_lock);
3466
3467         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3468                 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3469         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3470                 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3471         else
3472                 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3473
3474         mutex_unlock(&chip->reg_lock);
3475         return ret;
3476 }
3477
3478 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3479                                    struct device_node *np)
3480 {
3481         static int index;
3482         struct mii_bus *bus;
3483         int err;
3484
3485         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3486                 mv88e6xxx_ppu_state_init(chip);
3487
3488         if (np)
3489                 chip->mdio_np = of_get_child_by_name(np, "mdio");
3490
3491         bus = devm_mdiobus_alloc(chip->dev);
3492         if (!bus)
3493                 return -ENOMEM;
3494
3495         bus->priv = (void *)chip;
3496         if (np) {
3497                 bus->name = np->full_name;
3498                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3499         } else {
3500                 bus->name = "mv88e6xxx SMI";
3501                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3502         }
3503
3504         bus->read = mv88e6xxx_mdio_read;
3505         bus->write = mv88e6xxx_mdio_write;
3506         bus->parent = chip->dev;
3507
3508         if (chip->mdio_np)
3509                 err = of_mdiobus_register(bus, chip->mdio_np);
3510         else
3511                 err = mdiobus_register(bus);
3512         if (err) {
3513                 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3514                 goto out;
3515         }
3516         chip->mdio_bus = bus;
3517
3518         return 0;
3519
3520 out:
3521         if (chip->mdio_np)
3522                 of_node_put(chip->mdio_np);
3523
3524         return err;
3525 }
3526
3527 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3528
3529 {
3530         struct mii_bus *bus = chip->mdio_bus;
3531
3532         mdiobus_unregister(bus);
3533
3534         if (chip->mdio_np)
3535                 of_node_put(chip->mdio_np);
3536 }
3537
3538 #ifdef CONFIG_NET_DSA_HWMON
3539
3540 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3541 {
3542         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3543         int ret;
3544         int val;
3545
3546         *temp = 0;
3547
3548         mutex_lock(&chip->reg_lock);
3549
3550         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3551         if (ret < 0)
3552                 goto error;
3553
3554         /* Enable temperature sensor */
3555         ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3556         if (ret < 0)
3557                 goto error;
3558
3559         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3560         if (ret < 0)
3561                 goto error;
3562
3563         /* Wait for temperature to stabilize */
3564         usleep_range(10000, 12000);
3565
3566         val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3567         if (val < 0) {
3568                 ret = val;
3569                 goto error;
3570         }
3571
3572         /* Disable temperature sensor */
3573         ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3574         if (ret < 0)
3575                 goto error;
3576
3577         *temp = ((val & 0x1f) - 5) * 5;
3578
3579 error:
3580         mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3581         mutex_unlock(&chip->reg_lock);
3582         return ret;
3583 }
3584
3585 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3586 {
3587         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3588         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3589         int ret;
3590
3591         *temp = 0;
3592
3593         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3594         if (ret < 0)
3595                 return ret;
3596
3597         *temp = (ret & 0xff) - 25;
3598
3599         return 0;
3600 }
3601
3602 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3603 {
3604         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3605
3606         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3607                 return -EOPNOTSUPP;
3608
3609         if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3610                 return mv88e63xx_get_temp(ds, temp);
3611
3612         return mv88e61xx_get_temp(ds, temp);
3613 }
3614
3615 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3616 {
3617         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3618         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3619         int ret;
3620
3621         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3622                 return -EOPNOTSUPP;
3623
3624         *temp = 0;
3625
3626         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3627         if (ret < 0)
3628                 return ret;
3629
3630         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3631
3632         return 0;
3633 }
3634
3635 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3636 {
3637         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3638         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3639         int ret;
3640
3641         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3642                 return -EOPNOTSUPP;
3643
3644         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3645         if (ret < 0)
3646                 return ret;
3647         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3648         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3649                                          (ret & 0xe0ff) | (temp << 8));
3650 }
3651
3652 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3653 {
3654         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3655         int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3656         int ret;
3657
3658         if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3659                 return -EOPNOTSUPP;
3660
3661         *alarm = false;
3662
3663         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3664         if (ret < 0)
3665                 return ret;
3666
3667         *alarm = !!(ret & 0x40);
3668
3669         return 0;
3670 }
3671 #endif /* CONFIG_NET_DSA_HWMON */
3672
3673 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3674         [MV88E6085] = {
3675                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3676                 .family = MV88E6XXX_FAMILY_6097,
3677                 .name = "Marvell 88E6085",
3678                 .num_databases = 4096,
3679                 .num_ports = 10,
3680                 .port_base_addr = 0x10,
3681                 .age_time_coeff = 15000,
3682                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3683         },
3684
3685         [MV88E6095] = {
3686                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3687                 .family = MV88E6XXX_FAMILY_6095,
3688                 .name = "Marvell 88E6095/88E6095F",
3689                 .num_databases = 256,
3690                 .num_ports = 11,
3691                 .port_base_addr = 0x10,
3692                 .age_time_coeff = 15000,
3693                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3694         },
3695
3696         [MV88E6123] = {
3697                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3698                 .family = MV88E6XXX_FAMILY_6165,
3699                 .name = "Marvell 88E6123",
3700                 .num_databases = 4096,
3701                 .num_ports = 3,
3702                 .port_base_addr = 0x10,
3703                 .age_time_coeff = 15000,
3704                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3705         },
3706
3707         [MV88E6131] = {
3708                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3709                 .family = MV88E6XXX_FAMILY_6185,
3710                 .name = "Marvell 88E6131",
3711                 .num_databases = 256,
3712                 .num_ports = 8,
3713                 .port_base_addr = 0x10,
3714                 .age_time_coeff = 15000,
3715                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3716         },
3717
3718         [MV88E6161] = {
3719                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3720                 .family = MV88E6XXX_FAMILY_6165,
3721                 .name = "Marvell 88E6161",
3722                 .num_databases = 4096,
3723                 .num_ports = 6,
3724                 .port_base_addr = 0x10,
3725                 .age_time_coeff = 15000,
3726                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3727         },
3728
3729         [MV88E6165] = {
3730                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3731                 .family = MV88E6XXX_FAMILY_6165,
3732                 .name = "Marvell 88E6165",
3733                 .num_databases = 4096,
3734                 .num_ports = 6,
3735                 .port_base_addr = 0x10,
3736                 .age_time_coeff = 15000,
3737                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3738         },
3739
3740         [MV88E6171] = {
3741                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3742                 .family = MV88E6XXX_FAMILY_6351,
3743                 .name = "Marvell 88E6171",
3744                 .num_databases = 4096,
3745                 .num_ports = 7,
3746                 .port_base_addr = 0x10,
3747                 .age_time_coeff = 15000,
3748                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3749         },
3750
3751         [MV88E6172] = {
3752                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3753                 .family = MV88E6XXX_FAMILY_6352,
3754                 .name = "Marvell 88E6172",
3755                 .num_databases = 4096,
3756                 .num_ports = 7,
3757                 .port_base_addr = 0x10,
3758                 .age_time_coeff = 15000,
3759                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3760         },
3761
3762         [MV88E6175] = {
3763                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3764                 .family = MV88E6XXX_FAMILY_6351,
3765                 .name = "Marvell 88E6175",
3766                 .num_databases = 4096,
3767                 .num_ports = 7,
3768                 .port_base_addr = 0x10,
3769                 .age_time_coeff = 15000,
3770                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3771         },
3772
3773         [MV88E6176] = {
3774                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3775                 .family = MV88E6XXX_FAMILY_6352,
3776                 .name = "Marvell 88E6176",
3777                 .num_databases = 4096,
3778                 .num_ports = 7,
3779                 .port_base_addr = 0x10,
3780                 .age_time_coeff = 15000,
3781                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3782         },
3783
3784         [MV88E6185] = {
3785                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3786                 .family = MV88E6XXX_FAMILY_6185,
3787                 .name = "Marvell 88E6185",
3788                 .num_databases = 256,
3789                 .num_ports = 10,
3790                 .port_base_addr = 0x10,
3791                 .age_time_coeff = 15000,
3792                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3793         },
3794
3795         [MV88E6240] = {
3796                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3797                 .family = MV88E6XXX_FAMILY_6352,
3798                 .name = "Marvell 88E6240",
3799                 .num_databases = 4096,
3800                 .num_ports = 7,
3801                 .port_base_addr = 0x10,
3802                 .age_time_coeff = 15000,
3803                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3804         },
3805
3806         [MV88E6320] = {
3807                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3808                 .family = MV88E6XXX_FAMILY_6320,
3809                 .name = "Marvell 88E6320",
3810                 .num_databases = 4096,
3811                 .num_ports = 7,
3812                 .port_base_addr = 0x10,
3813                 .age_time_coeff = 15000,
3814                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3815         },
3816
3817         [MV88E6321] = {
3818                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3819                 .family = MV88E6XXX_FAMILY_6320,
3820                 .name = "Marvell 88E6321",
3821                 .num_databases = 4096,
3822                 .num_ports = 7,
3823                 .port_base_addr = 0x10,
3824                 .age_time_coeff = 15000,
3825                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3826         },
3827
3828         [MV88E6350] = {
3829                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3830                 .family = MV88E6XXX_FAMILY_6351,
3831                 .name = "Marvell 88E6350",
3832                 .num_databases = 4096,
3833                 .num_ports = 7,
3834                 .port_base_addr = 0x10,
3835                 .age_time_coeff = 15000,
3836                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3837         },
3838
3839         [MV88E6351] = {
3840                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3841                 .family = MV88E6XXX_FAMILY_6351,
3842                 .name = "Marvell 88E6351",
3843                 .num_databases = 4096,
3844                 .num_ports = 7,
3845                 .port_base_addr = 0x10,
3846                 .age_time_coeff = 15000,
3847                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3848         },
3849
3850         [MV88E6352] = {
3851                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3852                 .family = MV88E6XXX_FAMILY_6352,
3853                 .name = "Marvell 88E6352",
3854                 .num_databases = 4096,
3855                 .num_ports = 7,
3856                 .port_base_addr = 0x10,
3857                 .age_time_coeff = 15000,
3858                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3859         },
3860 };
3861
3862 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3863 {
3864         int i;
3865
3866         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3867                 if (mv88e6xxx_table[i].prod_num == prod_num)
3868                         return &mv88e6xxx_table[i];
3869
3870         return NULL;
3871 }
3872
3873 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3874 {
3875         const struct mv88e6xxx_info *info;
3876         int id, prod_num, rev;
3877
3878         id = mv88e6xxx_reg_read(chip, chip->info->port_base_addr,
3879                                 PORT_SWITCH_ID);
3880         if (id < 0)
3881                 return id;
3882
3883         prod_num = (id & 0xfff0) >> 4;
3884         rev = id & 0x000f;
3885
3886         info = mv88e6xxx_lookup_info(prod_num);
3887         if (!info)
3888                 return -ENODEV;
3889
3890         /* Update the compatible info with the probed one */
3891         chip->info = info;
3892
3893         dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3894                  chip->info->prod_num, chip->info->name, rev);
3895
3896         return 0;
3897 }
3898
3899 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3900 {
3901         struct mv88e6xxx_chip *chip;
3902
3903         chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3904         if (!chip)
3905                 return NULL;
3906
3907         chip->dev = dev;
3908
3909         mutex_init(&chip->reg_lock);
3910
3911         return chip;
3912 }
3913
3914 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3915                               struct mii_bus *bus, int sw_addr)
3916 {
3917         /* ADDR[0] pin is unavailable externally and considered zero */
3918         if (sw_addr & 0x1)
3919                 return -EINVAL;
3920
3921         if (sw_addr == 0)
3922                 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3923         else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3924                 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3925         else
3926                 return -EINVAL;
3927
3928         chip->bus = bus;
3929         chip->sw_addr = sw_addr;
3930
3931         return 0;
3932 }
3933
3934 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3935                                        struct device *host_dev, int sw_addr,
3936                                        void **priv)
3937 {
3938         struct mv88e6xxx_chip *chip;
3939         struct mii_bus *bus;
3940         int err;
3941
3942         bus = dsa_host_dev_to_mii_bus(host_dev);
3943         if (!bus)
3944                 return NULL;
3945
3946         chip = mv88e6xxx_alloc_chip(dsa_dev);
3947         if (!chip)
3948                 return NULL;
3949
3950         /* Legacy SMI probing will only support chips similar to 88E6085 */
3951         chip->info = &mv88e6xxx_table[MV88E6085];
3952
3953         err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3954         if (err)
3955                 goto free;
3956
3957         err = mv88e6xxx_detect(chip);
3958         if (err)
3959                 goto free;
3960
3961         err = mv88e6xxx_mdio_register(chip, NULL);
3962         if (err)
3963                 goto free;
3964
3965         *priv = chip;
3966
3967         return chip->info->name;
3968 free:
3969         devm_kfree(dsa_dev, chip);
3970
3971         return NULL;
3972 }
3973
3974 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3975         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3976         .probe                  = mv88e6xxx_drv_probe,
3977         .setup                  = mv88e6xxx_setup,
3978         .set_addr               = mv88e6xxx_set_addr,
3979         .adjust_link            = mv88e6xxx_adjust_link,
3980         .get_strings            = mv88e6xxx_get_strings,
3981         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3982         .get_sset_count         = mv88e6xxx_get_sset_count,
3983         .set_eee                = mv88e6xxx_set_eee,
3984         .get_eee                = mv88e6xxx_get_eee,
3985 #ifdef CONFIG_NET_DSA_HWMON
3986         .get_temp               = mv88e6xxx_get_temp,
3987         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3988         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3989         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3990 #endif
3991         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3992         .get_eeprom             = mv88e6xxx_get_eeprom,
3993         .set_eeprom             = mv88e6xxx_set_eeprom,
3994         .get_regs_len           = mv88e6xxx_get_regs_len,
3995         .get_regs               = mv88e6xxx_get_regs,
3996         .set_ageing_time        = mv88e6xxx_set_ageing_time,
3997         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3998         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3999         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
4000         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
4001         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
4002         .port_vlan_add          = mv88e6xxx_port_vlan_add,
4003         .port_vlan_del          = mv88e6xxx_port_vlan_del,
4004         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
4005         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
4006         .port_fdb_add           = mv88e6xxx_port_fdb_add,
4007         .port_fdb_del           = mv88e6xxx_port_fdb_del,
4008         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4009 };
4010
4011 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
4012                                      struct device_node *np)
4013 {
4014         struct device *dev = chip->dev;
4015         struct dsa_switch *ds;
4016
4017         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
4018         if (!ds)
4019                 return -ENOMEM;
4020
4021         ds->dev = dev;
4022         ds->priv = chip;
4023         ds->drv = &mv88e6xxx_switch_driver;
4024
4025         dev_set_drvdata(dev, ds);
4026
4027         return dsa_register_switch(ds, np);
4028 }
4029
4030 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4031 {
4032         dsa_unregister_switch(chip->ds);
4033 }
4034
4035 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4036 {
4037         struct device *dev = &mdiodev->dev;
4038         struct device_node *np = dev->of_node;
4039         const struct mv88e6xxx_info *compat_info;
4040         struct mv88e6xxx_chip *chip;
4041         u32 eeprom_len;
4042         int err;
4043
4044         compat_info = of_device_get_match_data(dev);
4045         if (!compat_info)
4046                 return -EINVAL;
4047
4048         chip = mv88e6xxx_alloc_chip(dev);
4049         if (!chip)
4050                 return -ENOMEM;
4051
4052         chip->info = compat_info;
4053
4054         err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4055         if (err)
4056                 return err;
4057
4058         err = mv88e6xxx_detect(chip);
4059         if (err)
4060                 return err;
4061
4062         chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
4063         if (IS_ERR(chip->reset))
4064                 return PTR_ERR(chip->reset);
4065
4066         if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM) &&
4067             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
4068                 chip->eeprom_len = eeprom_len;
4069
4070         err = mv88e6xxx_mdio_register(chip, np);
4071         if (err)
4072                 return err;
4073
4074         err = mv88e6xxx_register_switch(chip, np);
4075         if (err) {
4076                 mv88e6xxx_mdio_unregister(chip);
4077                 return err;
4078         }
4079
4080         return 0;
4081 }
4082
4083 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4084 {
4085         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4086         struct mv88e6xxx_chip *chip = ds_to_priv(ds);
4087
4088         mv88e6xxx_unregister_switch(chip);
4089         mv88e6xxx_mdio_unregister(chip);
4090 }
4091
4092 static const struct of_device_id mv88e6xxx_of_match[] = {
4093         {
4094                 .compatible = "marvell,mv88e6085",
4095                 .data = &mv88e6xxx_table[MV88E6085],
4096         },
4097         { /* sentinel */ },
4098 };
4099
4100 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4101
4102 static struct mdio_driver mv88e6xxx_driver = {
4103         .probe  = mv88e6xxx_probe,
4104         .remove = mv88e6xxx_remove,
4105         .mdiodrv.driver = {
4106                 .name = "mv88e6085",
4107                 .of_match_table = mv88e6xxx_of_match,
4108         },
4109 };
4110
4111 static int __init mv88e6xxx_init(void)
4112 {
4113         register_switch_driver(&mv88e6xxx_switch_driver);
4114         return mdio_driver_register(&mv88e6xxx_driver);
4115 }
4116 module_init(mv88e6xxx_init);
4117
4118 static void __exit mv88e6xxx_cleanup(void)
4119 {
4120         mdio_driver_unregister(&mv88e6xxx_driver);
4121         unregister_switch_driver(&mv88e6xxx_switch_driver);
4122 }
4123 module_exit(mv88e6xxx_cleanup);
4124
4125 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4126 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4127 MODULE_LICENSE("GPL");