2 * Marvell 88e6xxx Ethernet switch single-chip support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2015 CMC Electronics, Inc.
7 * Added support for VLAN Table Unit operations
9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/jiffies.h>
22 #include <linux/list.h>
23 #include <linux/mdio.h>
24 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_mdio.h>
27 #include <linux/netdevice.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/phy.h>
31 #include <net/switchdev.h>
33 #include "mv88e6xxx.h"
36 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
38 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
39 dev_err(chip->dev, "Switch registers lock not held!\n");
44 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
45 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
47 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
48 * is the only device connected to the SMI master. In this mode it responds to
49 * all 32 possible SMI addresses, and thus maps directly the internal devices.
51 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
52 * multiple devices to share the SMI interface. In this mode it responds to only
53 * 2 registers, used to indirectly access the internal SMI devices.
56 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
57 int addr, int reg, u16 *val)
62 return chip->smi_ops->read(chip, addr, reg, val);
65 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
66 int addr, int reg, u16 val)
71 return chip->smi_ops->write(chip, addr, reg, val);
74 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
75 int addr, int reg, u16 *val)
79 ret = mdiobus_read_nested(chip->bus, addr, reg);
88 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
89 int addr, int reg, u16 val)
93 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
100 static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
101 .read = mv88e6xxx_smi_single_chip_read,
102 .write = mv88e6xxx_smi_single_chip_write,
105 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
110 for (i = 0; i < 16; i++) {
111 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
115 if ((ret & SMI_CMD_BUSY) == 0)
122 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
123 int addr, int reg, u16 *val)
127 /* Wait for the bus to become free. */
128 ret = mv88e6xxx_smi_multi_chip_wait(chip);
132 /* Transmit the read command. */
133 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
134 SMI_CMD_OP_22_READ | (addr << 5) | reg);
138 /* Wait for the read command to complete. */
139 ret = mv88e6xxx_smi_multi_chip_wait(chip);
144 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
153 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
154 int addr, int reg, u16 val)
158 /* Wait for the bus to become free. */
159 ret = mv88e6xxx_smi_multi_chip_wait(chip);
163 /* Transmit the data to write. */
164 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
168 /* Transmit the write command. */
169 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
170 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
174 /* Wait for the write command to complete. */
175 ret = mv88e6xxx_smi_multi_chip_wait(chip);
182 static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
183 .read = mv88e6xxx_smi_multi_chip_read,
184 .write = mv88e6xxx_smi_multi_chip_write,
187 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
191 assert_reg_lock(chip);
193 err = mv88e6xxx_smi_read(chip, addr, reg, val);
197 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
203 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
207 assert_reg_lock(chip);
209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
219 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
222 int addr = chip->info->port_base_addr + port;
224 return mv88e6xxx_read(chip, addr, reg, val);
227 static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
230 int addr = chip->info->port_base_addr + port;
232 return mv88e6xxx_write(chip, addr, reg, val);
235 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
238 int addr = phy; /* PHY devices addresses start at 0x0 */
243 return chip->phy_ops->read(chip, addr, reg, val);
246 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
249 int addr = phy; /* PHY devices addresses start at 0x0 */
254 return chip->phy_ops->write(chip, addr, reg, val);
257 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page)
259 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE))
262 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
265 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy)
269 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */
270 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER);
272 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n",
277 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
278 u8 page, int reg, u16 *val)
282 /* There is no paging for registers 22 */
286 err = mv88e6xxx_phy_page_get(chip, phy, page);
288 err = mv88e6xxx_phy_read(chip, phy, reg, val);
289 mv88e6xxx_phy_page_put(chip, phy);
295 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
296 u8 page, int reg, u16 val)
300 /* There is no paging for registers 22 */
304 err = mv88e6xxx_phy_page_get(chip, phy, page);
306 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page);
307 mv88e6xxx_phy_page_put(chip, phy);
313 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
315 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
319 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
321 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER,
325 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
329 for (i = 0; i < 16; i++) {
333 err = mv88e6xxx_read(chip, addr, reg, &val);
340 usleep_range(1000, 2000);
343 dev_err(chip->dev, "Timeout while waiting for switch\n");
347 /* Indirect write to single pointer-data register with an Update bit */
348 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
353 /* Wait until the previous operation is completed */
354 err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
358 /* Set the Update bit to trigger a write operation */
359 val = BIT(15) | update;
361 return mv88e6xxx_write(chip, addr, reg, val);
364 static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
369 err = mv88e6xxx_read(chip, addr, reg, &val);
376 static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
379 return mv88e6xxx_write(chip, addr, reg, val);
382 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
387 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
391 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
392 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
396 for (i = 0; i < 16; i++) {
397 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
401 usleep_range(1000, 2000);
402 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
403 GLOBAL_STATUS_PPU_POLLING)
410 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
414 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
418 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
419 ret | GLOBAL_CONTROL_PPU_ENABLE);
423 for (i = 0; i < 16; i++) {
424 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
428 usleep_range(1000, 2000);
429 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
430 GLOBAL_STATUS_PPU_POLLING)
437 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
439 struct mv88e6xxx_chip *chip;
441 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
443 mutex_lock(&chip->reg_lock);
445 if (mutex_trylock(&chip->ppu_mutex)) {
446 if (mv88e6xxx_ppu_enable(chip) == 0)
447 chip->ppu_disabled = 0;
448 mutex_unlock(&chip->ppu_mutex);
451 mutex_unlock(&chip->reg_lock);
454 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
456 struct mv88e6xxx_chip *chip = (void *)_ps;
458 schedule_work(&chip->ppu_work);
461 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
465 mutex_lock(&chip->ppu_mutex);
467 /* If the PHY polling unit is enabled, disable it so that
468 * we can access the PHY registers. If it was already
469 * disabled, cancel the timer that is going to re-enable
472 if (!chip->ppu_disabled) {
473 ret = mv88e6xxx_ppu_disable(chip);
475 mutex_unlock(&chip->ppu_mutex);
478 chip->ppu_disabled = 1;
480 del_timer(&chip->ppu_timer);
487 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
489 /* Schedule a timer to re-enable the PHY polling unit. */
490 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
491 mutex_unlock(&chip->ppu_mutex);
494 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
496 mutex_init(&chip->ppu_mutex);
497 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
498 init_timer(&chip->ppu_timer);
499 chip->ppu_timer.data = (unsigned long)chip;
500 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
503 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip)
505 del_timer_sync(&chip->ppu_timer);
508 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr,
513 err = mv88e6xxx_ppu_access_get(chip);
515 err = mv88e6xxx_read(chip, addr, reg, val);
516 mv88e6xxx_ppu_access_put(chip);
522 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr,
527 err = mv88e6xxx_ppu_access_get(chip);
529 err = mv88e6xxx_write(chip, addr, reg, val);
530 mv88e6xxx_ppu_access_put(chip);
536 static const struct mv88e6xxx_ops mv88e6xxx_phy_ppu_ops = {
537 .read = mv88e6xxx_phy_ppu_read,
538 .write = mv88e6xxx_phy_ppu_write,
541 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
543 return chip->info->family == MV88E6XXX_FAMILY_6065;
546 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
548 return chip->info->family == MV88E6XXX_FAMILY_6095;
551 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
553 return chip->info->family == MV88E6XXX_FAMILY_6097;
556 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
558 return chip->info->family == MV88E6XXX_FAMILY_6165;
561 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
563 return chip->info->family == MV88E6XXX_FAMILY_6185;
566 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
568 return chip->info->family == MV88E6XXX_FAMILY_6320;
571 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
573 return chip->info->family == MV88E6XXX_FAMILY_6351;
576 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
578 return chip->info->family == MV88E6XXX_FAMILY_6352;
581 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
583 return chip->info->num_databases;
586 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
588 /* Does the device have dedicated FID registers for ATU and VTU ops? */
589 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
590 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
596 /* We expect the switch to perform auto negotiation if there is a real
597 * phy. However, in the case of a fixed link phy, we force the port
598 * settings from the fixed link settings.
600 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
601 struct phy_device *phydev)
603 struct mv88e6xxx_chip *chip = ds->priv;
607 if (!phy_is_pseudo_fixed_link(phydev))
610 mutex_lock(&chip->reg_lock);
612 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
616 reg &= ~(PORT_PCS_CTRL_LINK_UP |
617 PORT_PCS_CTRL_FORCE_LINK |
618 PORT_PCS_CTRL_DUPLEX_FULL |
619 PORT_PCS_CTRL_FORCE_DUPLEX |
620 PORT_PCS_CTRL_UNFORCED);
622 reg |= PORT_PCS_CTRL_FORCE_LINK;
624 reg |= PORT_PCS_CTRL_LINK_UP;
626 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
629 switch (phydev->speed) {
631 reg |= PORT_PCS_CTRL_1000;
634 reg |= PORT_PCS_CTRL_100;
637 reg |= PORT_PCS_CTRL_10;
640 pr_info("Unknown speed");
644 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
645 if (phydev->duplex == DUPLEX_FULL)
646 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
648 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
649 (port >= chip->info->num_ports - 2)) {
650 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
651 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
652 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
653 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
654 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
655 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
656 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
658 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
661 mutex_unlock(&chip->reg_lock);
664 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
669 for (i = 0; i < 10; i++) {
670 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
671 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
678 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
682 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
683 port = (port + 1) << 5;
685 /* Snapshot the hardware statistics counters for this port. */
686 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
687 GLOBAL_STATS_OP_CAPTURE_PORT |
688 GLOBAL_STATS_OP_HIST_RX_TX | port);
692 /* Wait for the snapshotting to complete. */
693 ret = _mv88e6xxx_stats_wait(chip);
700 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
708 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
709 GLOBAL_STATS_OP_READ_CAPTURED |
710 GLOBAL_STATS_OP_HIST_RX_TX | stat);
714 ret = _mv88e6xxx_stats_wait(chip);
718 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
724 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
731 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
732 { "in_good_octets", 8, 0x00, BANK0, },
733 { "in_bad_octets", 4, 0x02, BANK0, },
734 { "in_unicast", 4, 0x04, BANK0, },
735 { "in_broadcasts", 4, 0x06, BANK0, },
736 { "in_multicasts", 4, 0x07, BANK0, },
737 { "in_pause", 4, 0x16, BANK0, },
738 { "in_undersize", 4, 0x18, BANK0, },
739 { "in_fragments", 4, 0x19, BANK0, },
740 { "in_oversize", 4, 0x1a, BANK0, },
741 { "in_jabber", 4, 0x1b, BANK0, },
742 { "in_rx_error", 4, 0x1c, BANK0, },
743 { "in_fcs_error", 4, 0x1d, BANK0, },
744 { "out_octets", 8, 0x0e, BANK0, },
745 { "out_unicast", 4, 0x10, BANK0, },
746 { "out_broadcasts", 4, 0x13, BANK0, },
747 { "out_multicasts", 4, 0x12, BANK0, },
748 { "out_pause", 4, 0x15, BANK0, },
749 { "excessive", 4, 0x11, BANK0, },
750 { "collisions", 4, 0x1e, BANK0, },
751 { "deferred", 4, 0x05, BANK0, },
752 { "single", 4, 0x14, BANK0, },
753 { "multiple", 4, 0x17, BANK0, },
754 { "out_fcs_error", 4, 0x03, BANK0, },
755 { "late", 4, 0x1f, BANK0, },
756 { "hist_64bytes", 4, 0x08, BANK0, },
757 { "hist_65_127bytes", 4, 0x09, BANK0, },
758 { "hist_128_255bytes", 4, 0x0a, BANK0, },
759 { "hist_256_511bytes", 4, 0x0b, BANK0, },
760 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
761 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
762 { "sw_in_discards", 4, 0x10, PORT, },
763 { "sw_in_filtered", 2, 0x12, PORT, },
764 { "sw_out_filtered", 2, 0x13, PORT, },
765 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
766 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
767 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
768 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
769 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
770 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
771 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
772 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
773 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
774 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
775 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
776 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
777 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
778 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
779 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
780 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
781 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
782 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
783 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
784 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
785 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
786 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
787 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
788 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
789 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
790 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
793 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
794 struct mv88e6xxx_hw_stat *stat)
796 switch (stat->type) {
800 return mv88e6xxx_6320_family(chip);
802 return mv88e6xxx_6095_family(chip) ||
803 mv88e6xxx_6185_family(chip) ||
804 mv88e6xxx_6097_family(chip) ||
805 mv88e6xxx_6165_family(chip) ||
806 mv88e6xxx_6351_family(chip) ||
807 mv88e6xxx_6352_family(chip);
812 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
813 struct mv88e6xxx_hw_stat *s,
824 err = mv88e6xxx_port_read(chip, port, s->reg, ®);
829 if (s->sizeof_stat == 4) {
830 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®);
838 _mv88e6xxx_stats_read(chip, s->reg, &low);
839 if (s->sizeof_stat == 8)
840 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
842 value = (((u64)high) << 16) | low;
846 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
849 struct mv88e6xxx_chip *chip = ds->priv;
850 struct mv88e6xxx_hw_stat *stat;
853 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
854 stat = &mv88e6xxx_hw_stats[i];
855 if (mv88e6xxx_has_stat(chip, stat)) {
856 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
863 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
865 struct mv88e6xxx_chip *chip = ds->priv;
866 struct mv88e6xxx_hw_stat *stat;
869 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
870 stat = &mv88e6xxx_hw_stats[i];
871 if (mv88e6xxx_has_stat(chip, stat))
877 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
880 struct mv88e6xxx_chip *chip = ds->priv;
881 struct mv88e6xxx_hw_stat *stat;
885 mutex_lock(&chip->reg_lock);
887 ret = _mv88e6xxx_stats_snapshot(chip, port);
889 mutex_unlock(&chip->reg_lock);
892 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
893 stat = &mv88e6xxx_hw_stats[i];
894 if (mv88e6xxx_has_stat(chip, stat)) {
895 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
900 mutex_unlock(&chip->reg_lock);
903 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
905 return 32 * sizeof(u16);
908 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
909 struct ethtool_regs *regs, void *_p)
911 struct mv88e6xxx_chip *chip = ds->priv;
919 memset(p, 0xff, 32 * sizeof(u16));
921 mutex_lock(&chip->reg_lock);
923 for (i = 0; i < 32; i++) {
925 err = mv88e6xxx_port_read(chip, port, i, ®);
930 mutex_unlock(&chip->reg_lock);
933 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
935 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
939 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
940 struct ethtool_eee *e)
942 struct mv88e6xxx_chip *chip = ds->priv;
946 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
949 mutex_lock(&chip->reg_lock);
951 err = mv88e6xxx_phy_read(chip, port, 16, ®);
955 e->eee_enabled = !!(reg & 0x0200);
956 e->tx_lpi_enabled = !!(reg & 0x0100);
958 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
962 e->eee_active = !!(reg & PORT_STATUS_EEE);
964 mutex_unlock(&chip->reg_lock);
969 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
970 struct phy_device *phydev, struct ethtool_eee *e)
972 struct mv88e6xxx_chip *chip = ds->priv;
976 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
979 mutex_lock(&chip->reg_lock);
981 err = mv88e6xxx_phy_read(chip, port, 16, ®);
988 if (e->tx_lpi_enabled)
991 err = mv88e6xxx_phy_write(chip, port, 16, reg);
993 mutex_unlock(&chip->reg_lock);
998 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1002 if (mv88e6xxx_has_fid_reg(chip)) {
1003 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1007 } else if (mv88e6xxx_num_databases(chip) == 256) {
1008 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1009 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1013 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1015 ((fid << 8) & 0xf000));
1019 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1023 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1027 return _mv88e6xxx_atu_wait(chip);
1030 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1031 struct mv88e6xxx_atu_entry *entry)
1033 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1035 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1036 unsigned int mask, shift;
1039 data |= GLOBAL_ATU_DATA_TRUNK;
1040 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1041 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1043 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1044 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1047 data |= (entry->portv_trunkid << shift) & mask;
1050 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1053 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1054 struct mv88e6xxx_atu_entry *entry,
1060 err = _mv88e6xxx_atu_wait(chip);
1064 err = _mv88e6xxx_atu_data_write(chip, entry);
1069 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1070 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1072 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1073 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1076 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1079 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1080 u16 fid, bool static_too)
1082 struct mv88e6xxx_atu_entry entry = {
1084 .state = 0, /* EntryState bits must be 0 */
1087 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1090 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1091 int from_port, int to_port, bool static_too)
1093 struct mv88e6xxx_atu_entry entry = {
1098 /* EntryState bits must be 0xF */
1099 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1101 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1102 entry.portv_trunkid = (to_port & 0x0f) << 4;
1103 entry.portv_trunkid |= from_port & 0x0f;
1105 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1108 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1109 int port, bool static_too)
1111 /* Destination port 0xF means remove the entries */
1112 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1115 static const char * const mv88e6xxx_port_state_names[] = {
1116 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1117 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1118 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1119 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1122 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1125 struct dsa_switch *ds = chip->ds;
1130 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®);
1134 oldstate = reg & PORT_CONTROL_STATE_MASK;
1136 reg &= ~PORT_CONTROL_STATE_MASK;
1139 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
1143 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1144 mv88e6xxx_port_state_names[state],
1145 mv88e6xxx_port_state_names[oldstate]);
1150 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1152 struct net_device *bridge = chip->ports[port].bridge_dev;
1153 const u16 mask = (1 << chip->info->num_ports) - 1;
1154 struct dsa_switch *ds = chip->ds;
1155 u16 output_ports = 0;
1160 /* allow CPU port or DSA link(s) to send frames to every port */
1161 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1162 output_ports = mask;
1164 for (i = 0; i < chip->info->num_ports; ++i) {
1165 /* allow sending frames to every group member */
1166 if (bridge && chip->ports[i].bridge_dev == bridge)
1167 output_ports |= BIT(i);
1169 /* allow sending frames to CPU port and DSA link(s) */
1170 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1171 output_ports |= BIT(i);
1175 /* prevent frames from going back out of the port they came in on */
1176 output_ports &= ~BIT(port);
1178 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
1183 reg |= output_ports & mask;
1185 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1188 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1191 struct mv88e6xxx_chip *chip = ds->priv;
1196 case BR_STATE_DISABLED:
1197 stp_state = PORT_CONTROL_STATE_DISABLED;
1199 case BR_STATE_BLOCKING:
1200 case BR_STATE_LISTENING:
1201 stp_state = PORT_CONTROL_STATE_BLOCKING;
1203 case BR_STATE_LEARNING:
1204 stp_state = PORT_CONTROL_STATE_LEARNING;
1206 case BR_STATE_FORWARDING:
1208 stp_state = PORT_CONTROL_STATE_FORWARDING;
1212 mutex_lock(&chip->reg_lock);
1213 err = _mv88e6xxx_port_state(chip, port, stp_state);
1214 mutex_unlock(&chip->reg_lock);
1217 netdev_err(ds->ports[port].netdev,
1218 "failed to update state to %s\n",
1219 mv88e6xxx_port_state_names[stp_state]);
1222 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1224 struct mv88e6xxx_chip *chip = ds->priv;
1227 mutex_lock(&chip->reg_lock);
1228 err = _mv88e6xxx_atu_remove(chip, 0, port, false);
1229 mutex_unlock(&chip->reg_lock);
1232 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n");
1235 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1238 struct dsa_switch *ds = chip->ds;
1242 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®);
1246 pvid = reg & PORT_DEFAULT_VLAN_MASK;
1249 reg &= ~PORT_DEFAULT_VLAN_MASK;
1250 reg |= *new & PORT_DEFAULT_VLAN_MASK;
1252 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg);
1256 netdev_dbg(ds->ports[port].netdev,
1257 "DefaultVID %d (was %d)\n", *new, pvid);
1266 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1267 int port, u16 *pvid)
1269 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1272 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1275 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1278 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1280 return mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1281 GLOBAL_VTU_OP_BUSY);
1284 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1288 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1292 return _mv88e6xxx_vtu_wait(chip);
1295 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1299 ret = _mv88e6xxx_vtu_wait(chip);
1303 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1306 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1307 struct mv88e6xxx_vtu_stu_entry *entry,
1308 unsigned int nibble_offset)
1314 for (i = 0; i < 3; ++i) {
1315 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1316 GLOBAL_VTU_DATA_0_3 + i);
1323 for (i = 0; i < chip->info->num_ports; ++i) {
1324 unsigned int shift = (i % 4) * 4 + nibble_offset;
1325 u16 reg = regs[i / 4];
1327 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1333 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1334 struct mv88e6xxx_vtu_stu_entry *entry)
1336 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1339 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1340 struct mv88e6xxx_vtu_stu_entry *entry)
1342 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1345 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1346 struct mv88e6xxx_vtu_stu_entry *entry,
1347 unsigned int nibble_offset)
1349 u16 regs[3] = { 0 };
1353 for (i = 0; i < chip->info->num_ports; ++i) {
1354 unsigned int shift = (i % 4) * 4 + nibble_offset;
1355 u8 data = entry->data[i];
1357 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1360 for (i = 0; i < 3; ++i) {
1361 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1362 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1370 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1371 struct mv88e6xxx_vtu_stu_entry *entry)
1373 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1376 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1377 struct mv88e6xxx_vtu_stu_entry *entry)
1379 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1382 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1384 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1385 vid & GLOBAL_VTU_VID_MASK);
1388 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1389 struct mv88e6xxx_vtu_stu_entry *entry)
1391 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1394 ret = _mv88e6xxx_vtu_wait(chip);
1398 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1402 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1406 next.vid = ret & GLOBAL_VTU_VID_MASK;
1407 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1410 ret = mv88e6xxx_vtu_data_read(chip, &next);
1414 if (mv88e6xxx_has_fid_reg(chip)) {
1415 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1420 next.fid = ret & GLOBAL_VTU_FID_MASK;
1421 } else if (mv88e6xxx_num_databases(chip) == 256) {
1422 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1423 * VTU DBNum[3:0] are located in VTU Operation 3:0
1425 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1430 next.fid = (ret & 0xf00) >> 4;
1431 next.fid |= ret & 0xf;
1434 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1435 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1440 next.sid = ret & GLOBAL_VTU_SID_MASK;
1448 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1449 struct switchdev_obj_port_vlan *vlan,
1450 int (*cb)(struct switchdev_obj *obj))
1452 struct mv88e6xxx_chip *chip = ds->priv;
1453 struct mv88e6xxx_vtu_stu_entry next;
1457 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1460 mutex_lock(&chip->reg_lock);
1462 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1466 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1471 err = _mv88e6xxx_vtu_getnext(chip, &next);
1478 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1481 /* reinit and dump this VLAN obj */
1482 vlan->vid_begin = next.vid;
1483 vlan->vid_end = next.vid;
1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1487 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1489 if (next.vid == pvid)
1490 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1492 err = cb(&vlan->obj);
1495 } while (next.vid < GLOBAL_VTU_VID_MASK);
1498 mutex_unlock(&chip->reg_lock);
1503 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1504 struct mv88e6xxx_vtu_stu_entry *entry)
1506 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1510 ret = _mv88e6xxx_vtu_wait(chip);
1517 /* Write port member tags */
1518 ret = mv88e6xxx_vtu_data_write(chip, entry);
1522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1523 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1524 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1530 if (mv88e6xxx_has_fid_reg(chip)) {
1531 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1532 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1536 } else if (mv88e6xxx_num_databases(chip) == 256) {
1537 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1538 * VTU DBNum[3:0] are located in VTU Operation 3:0
1540 op |= (entry->fid & 0xf0) << 8;
1541 op |= entry->fid & 0xf;
1544 reg = GLOBAL_VTU_VID_VALID;
1546 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1547 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1551 return _mv88e6xxx_vtu_cmd(chip, op);
1554 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1555 struct mv88e6xxx_vtu_stu_entry *entry)
1557 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1560 ret = _mv88e6xxx_vtu_wait(chip);
1564 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1565 sid & GLOBAL_VTU_SID_MASK);
1569 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1573 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1577 next.sid = ret & GLOBAL_VTU_SID_MASK;
1579 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1583 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1586 ret = mv88e6xxx_stu_data_read(chip, &next);
1595 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1596 struct mv88e6xxx_vtu_stu_entry *entry)
1601 ret = _mv88e6xxx_vtu_wait(chip);
1608 /* Write port states */
1609 ret = mv88e6xxx_stu_data_write(chip, entry);
1613 reg = GLOBAL_VTU_VID_VALID;
1615 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1619 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1620 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1624 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1627 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1630 struct dsa_switch *ds = chip->ds;
1636 if (mv88e6xxx_num_databases(chip) == 4096)
1638 else if (mv88e6xxx_num_databases(chip) == 256)
1643 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1644 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®);
1648 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1651 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1652 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1654 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg);
1659 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1660 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®);
1664 fid |= (reg & upper_mask) << 4;
1668 reg |= (*new >> 4) & upper_mask;
1670 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg);
1674 netdev_dbg(ds->ports[port].netdev,
1675 "FID %d (was %d)\n", *new, fid);
1684 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1687 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1690 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1693 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1696 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1698 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1699 struct mv88e6xxx_vtu_stu_entry vlan;
1702 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1704 /* Set every FID bit used by the (un)bridged ports */
1705 for (i = 0; i < chip->info->num_ports; ++i) {
1706 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1710 set_bit(*fid, fid_bitmap);
1713 /* Set every FID bit used by the VLAN entries */
1714 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1719 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1726 set_bit(vlan.fid, fid_bitmap);
1727 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1729 /* The reset value 0x000 is used to indicate that multiple address
1730 * databases are not needed. Return the next positive available.
1732 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1733 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1736 /* Clear the database */
1737 return _mv88e6xxx_atu_flush(chip, *fid, true);
1740 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
1741 struct mv88e6xxx_vtu_stu_entry *entry)
1743 struct dsa_switch *ds = chip->ds;
1744 struct mv88e6xxx_vtu_stu_entry vlan = {
1750 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
1754 /* exclude all ports except the CPU and DSA ports */
1755 for (i = 0; i < chip->info->num_ports; ++i)
1756 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1757 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1758 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1760 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
1761 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
1762 struct mv88e6xxx_vtu_stu_entry vstp;
1764 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1765 * implemented, only one STU entry is needed to cover all VTU
1766 * entries. Thus, validate the SID 0.
1769 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
1773 if (vstp.sid != vlan.sid || !vstp.valid) {
1774 memset(&vstp, 0, sizeof(vstp));
1776 vstp.sid = vlan.sid;
1778 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
1788 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1789 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1796 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
1800 err = _mv88e6xxx_vtu_getnext(chip, entry);
1804 if (entry->vid != vid || !entry->valid) {
1807 /* -ENOENT would've been more appropriate, but switchdev expects
1808 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1811 err = _mv88e6xxx_vtu_new(chip, vid, entry);
1817 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1818 u16 vid_begin, u16 vid_end)
1820 struct mv88e6xxx_chip *chip = ds->priv;
1821 struct mv88e6xxx_vtu_stu_entry vlan;
1827 mutex_lock(&chip->reg_lock);
1829 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
1834 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1841 if (vlan.vid > vid_end)
1844 for (i = 0; i < chip->info->num_ports; ++i) {
1845 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1849 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1852 if (chip->ports[i].bridge_dev ==
1853 chip->ports[port].bridge_dev)
1854 break; /* same bridge, check next VLAN */
1856 netdev_warn(ds->ports[port].netdev,
1857 "hardware VLAN %d already used by %s\n",
1859 netdev_name(chip->ports[i].bridge_dev));
1863 } while (vlan.vid < vid_end);
1866 mutex_unlock(&chip->reg_lock);
1871 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1872 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1873 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1874 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1875 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1878 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1879 bool vlan_filtering)
1881 struct mv88e6xxx_chip *chip = ds->priv;
1882 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1883 PORT_CONTROL_2_8021Q_DISABLED;
1887 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1890 mutex_lock(&chip->reg_lock);
1892 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®);
1896 old = reg & PORT_CONTROL_2_8021Q_MASK;
1899 reg &= ~PORT_CONTROL_2_8021Q_MASK;
1900 reg |= new & PORT_CONTROL_2_8021Q_MASK;
1902 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
1906 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
1907 mv88e6xxx_port_8021q_mode_names[new],
1908 mv88e6xxx_port_8021q_mode_names[old]);
1913 mutex_unlock(&chip->reg_lock);
1919 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1920 const struct switchdev_obj_port_vlan *vlan,
1921 struct switchdev_trans *trans)
1923 struct mv88e6xxx_chip *chip = ds->priv;
1926 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1929 /* If the requested port doesn't belong to the same bridge as the VLAN
1930 * members, do not support it (yet) and fallback to software VLAN.
1932 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1937 /* We don't need any dynamic resource from the kernel (yet),
1938 * so skip the prepare phase.
1943 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1944 u16 vid, bool untagged)
1946 struct mv88e6xxx_vtu_stu_entry vlan;
1949 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1953 vlan.data[port] = untagged ?
1954 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1955 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1957 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
1960 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1961 const struct switchdev_obj_port_vlan *vlan,
1962 struct switchdev_trans *trans)
1964 struct mv88e6xxx_chip *chip = ds->priv;
1965 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1966 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1969 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1972 mutex_lock(&chip->reg_lock);
1974 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1975 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
1976 netdev_err(ds->ports[port].netdev,
1977 "failed to add VLAN %d%c\n",
1978 vid, untagged ? 'u' : 't');
1980 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
1981 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
1984 mutex_unlock(&chip->reg_lock);
1987 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1990 struct dsa_switch *ds = chip->ds;
1991 struct mv88e6xxx_vtu_stu_entry vlan;
1994 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1998 /* Tell switchdev if this VLAN is handled in software */
1999 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2002 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2004 /* keep the VLAN unless all ports are excluded */
2006 for (i = 0; i < chip->info->num_ports; ++i) {
2007 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2010 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2016 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2020 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2023 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2024 const struct switchdev_obj_port_vlan *vlan)
2026 struct mv88e6xxx_chip *chip = ds->priv;
2030 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2033 mutex_lock(&chip->reg_lock);
2035 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2039 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2040 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2045 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2052 mutex_unlock(&chip->reg_lock);
2057 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2058 const unsigned char *addr)
2062 for (i = 0; i < 3; i++) {
2063 ret = _mv88e6xxx_reg_write(
2064 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2065 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2073 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2074 unsigned char *addr)
2078 for (i = 0; i < 3; i++) {
2079 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2080 GLOBAL_ATU_MAC_01 + i);
2083 addr[i * 2] = ret >> 8;
2084 addr[i * 2 + 1] = ret & 0xff;
2090 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2091 struct mv88e6xxx_atu_entry *entry)
2095 ret = _mv88e6xxx_atu_wait(chip);
2099 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2103 ret = _mv88e6xxx_atu_data_write(chip, entry);
2107 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2110 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2111 struct mv88e6xxx_atu_entry *entry);
2113 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid,
2114 const u8 *addr, struct mv88e6xxx_atu_entry *entry)
2116 struct mv88e6xxx_atu_entry next;
2119 eth_broadcast_addr(next.mac);
2121 err = _mv88e6xxx_atu_mac_write(chip, next.mac);
2126 err = _mv88e6xxx_atu_getnext(chip, fid, &next);
2130 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2133 if (ether_addr_equal(next.mac, addr)) {
2137 } while (!is_broadcast_ether_addr(next.mac));
2139 memset(entry, 0, sizeof(*entry));
2141 ether_addr_copy(entry->mac, addr);
2146 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
2147 const unsigned char *addr, u16 vid,
2150 struct mv88e6xxx_vtu_stu_entry vlan;
2151 struct mv88e6xxx_atu_entry entry;
2154 /* Null VLAN ID corresponds to the port private database */
2156 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2158 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2162 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry);
2166 /* Purge the ATU entry only if no port is using it anymore */
2167 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) {
2168 entry.portv_trunkid &= ~BIT(port);
2169 if (!entry.portv_trunkid)
2170 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED;
2172 entry.portv_trunkid |= BIT(port);
2173 entry.state = state;
2176 return _mv88e6xxx_atu_load(chip, &entry);
2179 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2180 const struct switchdev_obj_port_fdb *fdb,
2181 struct switchdev_trans *trans)
2183 /* We don't need any dynamic resource from the kernel (yet),
2184 * so skip the prepare phase.
2189 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2190 const struct switchdev_obj_port_fdb *fdb,
2191 struct switchdev_trans *trans)
2193 struct mv88e6xxx_chip *chip = ds->priv;
2195 mutex_lock(&chip->reg_lock);
2196 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2197 GLOBAL_ATU_DATA_STATE_UC_STATIC))
2198 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n");
2199 mutex_unlock(&chip->reg_lock);
2202 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2203 const struct switchdev_obj_port_fdb *fdb)
2205 struct mv88e6xxx_chip *chip = ds->priv;
2208 mutex_lock(&chip->reg_lock);
2209 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid,
2210 GLOBAL_ATU_DATA_STATE_UNUSED);
2211 mutex_unlock(&chip->reg_lock);
2216 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2217 struct mv88e6xxx_atu_entry *entry)
2219 struct mv88e6xxx_atu_entry next = { 0 };
2224 ret = _mv88e6xxx_atu_wait(chip);
2228 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2232 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2236 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2240 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2241 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2242 unsigned int mask, shift;
2244 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2246 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2247 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2250 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2251 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2254 next.portv_trunkid = (ret & mask) >> shift;
2261 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
2262 u16 fid, u16 vid, int port,
2263 struct switchdev_obj *obj,
2264 int (*cb)(struct switchdev_obj *obj))
2266 struct mv88e6xxx_atu_entry addr = {
2267 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2271 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2276 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2280 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2283 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0)
2286 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) {
2287 struct switchdev_obj_port_fdb *fdb;
2289 if (!is_unicast_ether_addr(addr.mac))
2292 fdb = SWITCHDEV_OBJ_PORT_FDB(obj);
2294 ether_addr_copy(fdb->addr, addr.mac);
2295 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC)
2296 fdb->ndm_state = NUD_NOARP;
2298 fdb->ndm_state = NUD_REACHABLE;
2299 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) {
2300 struct switchdev_obj_port_mdb *mdb;
2302 if (!is_multicast_ether_addr(addr.mac))
2305 mdb = SWITCHDEV_OBJ_PORT_MDB(obj);
2307 ether_addr_copy(mdb->addr, addr.mac);
2315 } while (!is_broadcast_ether_addr(addr.mac));
2320 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
2321 struct switchdev_obj *obj,
2322 int (*cb)(struct switchdev_obj *obj))
2324 struct mv88e6xxx_vtu_stu_entry vlan = {
2325 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2330 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2331 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2335 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb);
2339 /* Dump VLANs' Filtering Information Databases */
2340 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2345 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2352 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
2356 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2361 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2362 struct switchdev_obj_port_fdb *fdb,
2363 int (*cb)(struct switchdev_obj *obj))
2365 struct mv88e6xxx_chip *chip = ds->priv;
2368 mutex_lock(&chip->reg_lock);
2369 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb);
2370 mutex_unlock(&chip->reg_lock);
2375 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2376 struct net_device *bridge)
2378 struct mv88e6xxx_chip *chip = ds->priv;
2381 mutex_lock(&chip->reg_lock);
2383 /* Assign the bridge and remap each port's VLANTable */
2384 chip->ports[port].bridge_dev = bridge;
2386 for (i = 0; i < chip->info->num_ports; ++i) {
2387 if (chip->ports[i].bridge_dev == bridge) {
2388 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2394 mutex_unlock(&chip->reg_lock);
2399 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2401 struct mv88e6xxx_chip *chip = ds->priv;
2402 struct net_device *bridge = chip->ports[port].bridge_dev;
2405 mutex_lock(&chip->reg_lock);
2407 /* Unassign the bridge and remap each port's VLANTable */
2408 chip->ports[port].bridge_dev = NULL;
2410 for (i = 0; i < chip->info->num_ports; ++i)
2411 if (i == port || chip->ports[i].bridge_dev == bridge)
2412 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2413 netdev_warn(ds->ports[i].netdev,
2414 "failed to remap\n");
2416 mutex_unlock(&chip->reg_lock);
2419 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2421 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2422 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2423 struct gpio_desc *gpiod = chip->reset;
2424 unsigned long timeout;
2429 /* Set all ports to the disabled state. */
2430 for (i = 0; i < chip->info->num_ports; i++) {
2431 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, ®);
2435 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL,
2441 /* Wait for transmit queues to drain. */
2442 usleep_range(2000, 4000);
2444 /* If there is a gpio connected to the reset pin, toggle it */
2446 gpiod_set_value_cansleep(gpiod, 1);
2447 usleep_range(10000, 20000);
2448 gpiod_set_value_cansleep(gpiod, 0);
2449 usleep_range(10000, 20000);
2452 /* Reset the switch. Keep the PPU active if requested. The PPU
2453 * needs to be active to support indirect phy register access
2454 * through global registers 0x18 and 0x19.
2457 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2459 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2463 /* Wait up to one second for reset to complete. */
2464 timeout = jiffies + 1 * HZ;
2465 while (time_before(jiffies, timeout)) {
2466 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2470 if ((ret & is_reset) == is_reset)
2472 usleep_range(1000, 2000);
2474 if (time_after(jiffies, timeout))
2482 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip)
2487 /* Clear Power Down bit */
2488 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val);
2492 if (val & BMCR_PDOWN) {
2494 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val);
2500 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2502 struct dsa_switch *ds = chip->ds;
2506 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2507 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2508 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2509 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2510 /* MAC Forcing register: don't force link, speed,
2511 * duplex or flow control state to any particular
2512 * values on physical ports, but force the CPU port
2513 * and all DSA ports to their maximum bandwidth and
2516 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®);
2517 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2518 reg &= ~PORT_PCS_CTRL_UNFORCED;
2519 reg |= PORT_PCS_CTRL_FORCE_LINK |
2520 PORT_PCS_CTRL_LINK_UP |
2521 PORT_PCS_CTRL_DUPLEX_FULL |
2522 PORT_PCS_CTRL_FORCE_DUPLEX;
2523 if (mv88e6xxx_6065_family(chip))
2524 reg |= PORT_PCS_CTRL_100;
2526 reg |= PORT_PCS_CTRL_1000;
2528 reg |= PORT_PCS_CTRL_UNFORCED;
2531 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg);
2536 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2537 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2538 * tunneling, determine priority by looking at 802.1p and IP
2539 * priority fields (IP prio has precedence), and set STP state
2542 * If this is the CPU link, use DSA or EDSA tagging depending
2543 * on which tagging mode was configured.
2545 * If this is a link to another switch, use DSA tagging mode.
2547 * If this is the upstream port for this switch, enable
2548 * forwarding of unknown unicasts and multicasts.
2551 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2552 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2553 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2554 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2555 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2556 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2557 PORT_CONTROL_STATE_FORWARDING;
2558 if (dsa_is_cpu_port(ds, port)) {
2559 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
2560 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2561 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2563 reg |= PORT_CONTROL_DSA_TAG;
2564 reg |= PORT_CONTROL_EGRESS_ADD_TAG |
2565 PORT_CONTROL_FORWARD_UNKNOWN;
2567 if (dsa_is_dsa_port(ds, port)) {
2568 if (mv88e6xxx_6095_family(chip) ||
2569 mv88e6xxx_6185_family(chip))
2570 reg |= PORT_CONTROL_DSA_TAG;
2571 if (mv88e6xxx_6352_family(chip) ||
2572 mv88e6xxx_6351_family(chip) ||
2573 mv88e6xxx_6165_family(chip) ||
2574 mv88e6xxx_6097_family(chip) ||
2575 mv88e6xxx_6320_family(chip)) {
2576 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2579 if (port == dsa_upstream_port(ds))
2580 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2581 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2584 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg);
2589 /* If this port is connected to a SerDes, make sure the SerDes is not
2592 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) {
2593 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®);
2596 reg &= PORT_STATUS_CMODE_MASK;
2597 if ((reg == PORT_STATUS_CMODE_100BASE_X) ||
2598 (reg == PORT_STATUS_CMODE_1000BASE_X) ||
2599 (reg == PORT_STATUS_CMODE_SGMII)) {
2600 err = mv88e6xxx_serdes_power_on(chip);
2606 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2607 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2608 * untagged frames on this port, do a destination address lookup on all
2609 * received packets as usual, disable ARP mirroring and don't send a
2610 * copy of all transmitted/received frames on this port to the CPU.
2613 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2614 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2615 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2616 mv88e6xxx_6185_family(chip))
2617 reg = PORT_CONTROL_2_MAP_DA;
2619 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2620 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2621 reg |= PORT_CONTROL_2_JUMBO_10240;
2623 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2624 /* Set the upstream port this port should use */
2625 reg |= dsa_upstream_port(ds);
2626 /* enable forwarding of unknown multicast addresses to
2629 if (port == dsa_upstream_port(ds))
2630 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2633 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2636 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg);
2641 /* Port Association Vector: when learning source addresses
2642 * of packets, add the address to the address database using
2643 * a port bitmap that has only the bit for this port set and
2644 * the other bits clear.
2647 /* Disable learning for CPU port */
2648 if (dsa_is_cpu_port(ds, port))
2651 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg);
2655 /* Egress rate control 2: disable egress rate control. */
2656 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000);
2660 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2661 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2662 mv88e6xxx_6320_family(chip)) {
2663 /* Do not limit the period of time that this port can
2664 * be paused for by the remote end or the period of
2665 * time that this port can pause the remote end.
2667 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000);
2671 /* Port ATU control: disable limiting the number of
2672 * address database entries that this port is allowed
2675 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL,
2677 /* Priority Override: disable DA, SA and VTU priority
2680 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE,
2685 /* Port Ethertype: use the Ethertype DSA Ethertype
2688 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) {
2689 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE,
2695 /* Tag Remap: use an identity 802.1p prio -> switch
2698 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123,
2703 /* Tag Remap 2: use an identity 802.1p prio -> switch
2706 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567,
2712 /* Rate Control: disable ingress rate limiting. */
2713 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2714 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2715 mv88e6xxx_6320_family(chip)) {
2716 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2720 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) {
2721 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL,
2727 /* Port Control 1: disable trunking, disable sending
2728 * learning messages to this port.
2730 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000);
2734 /* Port based VLAN map: give each port the same default address
2735 * database, and allow bidirectional communication between the
2736 * CPU and DSA port(s), and the other ports.
2738 err = _mv88e6xxx_port_fid_set(chip, port, 0);
2742 err = _mv88e6xxx_port_based_vlan_map(chip, port);
2746 /* Default VLAN ID and priority: don't set a default VLAN
2747 * ID, and set the default packet priority to zero.
2749 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000);
2752 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
2756 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
2757 (addr[0] << 8) | addr[1]);
2761 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
2762 (addr[2] << 8) | addr[3]);
2766 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
2767 (addr[4] << 8) | addr[5]);
2770 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip,
2773 const unsigned int coeff = chip->info->age_time_coeff;
2774 const unsigned int min = 0x01 * coeff;
2775 const unsigned int max = 0xff * coeff;
2780 if (msecs < min || msecs > max)
2783 /* Round to nearest multiple of coeff */
2784 age_time = (msecs + coeff / 2) / coeff;
2786 err = mv88e6xxx_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, &val);
2790 /* AgeTime is 11:4 bits */
2792 val |= age_time << 4;
2794 return mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL, val);
2797 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2798 unsigned int ageing_time)
2800 struct mv88e6xxx_chip *chip = ds->priv;
2803 mutex_lock(&chip->reg_lock);
2804 err = mv88e6xxx_g1_set_age_time(chip, ageing_time);
2805 mutex_unlock(&chip->reg_lock);
2810 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
2812 struct dsa_switch *ds = chip->ds;
2813 u32 upstream_port = dsa_upstream_port(ds);
2817 /* Enable the PHY Polling Unit if present, don't discard any packets,
2818 * and mask all interrupt sources.
2821 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
2822 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
2823 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2825 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
2829 /* Configure the upstream port, and configure it as the port to which
2830 * ingress and egress and ARP monitor frames are to be sent.
2832 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2833 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2834 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2835 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
2840 /* Disable remote management, and set the switch's DSA device number. */
2841 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
2842 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2843 (ds->index & 0x1f));
2847 /* Clear all the VTU and STU entries */
2848 err = _mv88e6xxx_vtu_stu_flush(chip);
2852 /* Set the default address aging time to 5 minutes, and
2853 * enable address learn messages to be sent to all message
2856 err = mv88e6xxx_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2857 GLOBAL_ATU_CONTROL_LEARN2ALL);
2861 err = mv88e6xxx_g1_set_age_time(chip, 300000);
2865 /* Clear all ATU entries */
2866 err = _mv88e6xxx_atu_flush(chip, 0, true);
2870 /* Configure the IP ToS mapping registers. */
2871 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2874 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2877 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2880 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2883 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2886 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2889 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2892 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2896 /* Configure the IEEE 802.1p priority mapping register. */
2897 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2901 /* Clear the statistics counters for all ports */
2902 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
2903 GLOBAL_STATS_OP_FLUSH_ALL);
2907 /* Wait for the flush to complete. */
2908 err = _mv88e6xxx_stats_wait(chip);
2915 static int mv88e6xxx_setup(struct dsa_switch *ds)
2917 struct mv88e6xxx_chip *chip = ds->priv;
2922 ds->slave_mii_bus = chip->mdio_bus;
2924 mutex_lock(&chip->reg_lock);
2926 err = mv88e6xxx_switch_reset(chip);
2930 /* Setup Switch Port Registers */
2931 for (i = 0; i < chip->info->num_ports; i++) {
2932 err = mv88e6xxx_setup_port(chip, i);
2937 /* Setup Switch Global 1 Registers */
2938 err = mv88e6xxx_g1_setup(chip);
2942 /* Setup Switch Global 2 Registers */
2943 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) {
2944 err = mv88e6xxx_g2_setup(chip);
2950 mutex_unlock(&chip->reg_lock);
2955 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
2957 struct mv88e6xxx_chip *chip = ds->priv;
2960 mutex_lock(&chip->reg_lock);
2962 /* Has an indirect Switch MAC/WoL/WoF register in Global 2? */
2963 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_SWITCH_MAC))
2964 err = mv88e6xxx_g2_set_switch_mac(chip, addr);
2966 err = mv88e6xxx_g1_set_switch_mac(chip, addr);
2968 mutex_unlock(&chip->reg_lock);
2973 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2975 struct mv88e6xxx_chip *chip = bus->priv;
2979 if (phy >= chip->info->num_ports)
2982 mutex_lock(&chip->reg_lock);
2983 err = mv88e6xxx_phy_read(chip, phy, reg, &val);
2984 mutex_unlock(&chip->reg_lock);
2986 return err ? err : val;
2989 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2991 struct mv88e6xxx_chip *chip = bus->priv;
2994 if (phy >= chip->info->num_ports)
2997 mutex_lock(&chip->reg_lock);
2998 err = mv88e6xxx_phy_write(chip, phy, reg, val);
2999 mutex_unlock(&chip->reg_lock);
3004 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3005 struct device_node *np)
3008 struct mii_bus *bus;
3012 chip->mdio_np = of_get_child_by_name(np, "mdio");
3014 bus = devm_mdiobus_alloc(chip->dev);
3018 bus->priv = (void *)chip;
3020 bus->name = np->full_name;
3021 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3023 bus->name = "mv88e6xxx SMI";
3024 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3027 bus->read = mv88e6xxx_mdio_read;
3028 bus->write = mv88e6xxx_mdio_write;
3029 bus->parent = chip->dev;
3032 err = of_mdiobus_register(bus, chip->mdio_np);
3034 err = mdiobus_register(bus);
3036 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3039 chip->mdio_bus = bus;
3045 of_node_put(chip->mdio_np);
3050 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3053 struct mii_bus *bus = chip->mdio_bus;
3055 mdiobus_unregister(bus);
3058 of_node_put(chip->mdio_np);
3061 #ifdef CONFIG_NET_DSA_HWMON
3063 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3065 struct mv88e6xxx_chip *chip = ds->priv;
3071 mutex_lock(&chip->reg_lock);
3073 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6);
3077 /* Enable temperature sensor */
3078 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3082 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5));
3086 /* Wait for temperature to stabilize */
3087 usleep_range(10000, 12000);
3089 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val);
3093 /* Disable temperature sensor */
3094 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5));
3098 *temp = ((val & 0x1f) - 5) * 5;
3101 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0);
3102 mutex_unlock(&chip->reg_lock);
3106 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3108 struct mv88e6xxx_chip *chip = ds->priv;
3109 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3115 mutex_lock(&chip->reg_lock);
3116 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val);
3117 mutex_unlock(&chip->reg_lock);
3121 *temp = (val & 0xff) - 25;
3126 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3128 struct mv88e6xxx_chip *chip = ds->priv;
3130 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3133 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3134 return mv88e63xx_get_temp(ds, temp);
3136 return mv88e61xx_get_temp(ds, temp);
3139 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3141 struct mv88e6xxx_chip *chip = ds->priv;
3142 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3146 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3151 mutex_lock(&chip->reg_lock);
3152 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3153 mutex_unlock(&chip->reg_lock);
3157 *temp = (((val >> 8) & 0x1f) * 5) - 25;
3162 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3164 struct mv88e6xxx_chip *chip = ds->priv;
3165 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3169 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3172 mutex_lock(&chip->reg_lock);
3173 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3176 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3177 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26,
3178 (val & 0xe0ff) | (temp << 8));
3180 mutex_unlock(&chip->reg_lock);
3185 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3187 struct mv88e6xxx_chip *chip = ds->priv;
3188 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3192 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3197 mutex_lock(&chip->reg_lock);
3198 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val);
3199 mutex_unlock(&chip->reg_lock);
3203 *alarm = !!(val & 0x40);
3207 #endif /* CONFIG_NET_DSA_HWMON */
3209 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
3211 struct mv88e6xxx_chip *chip = ds->priv;
3213 return chip->eeprom_len;
3216 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
3217 struct ethtool_eeprom *eeprom, u8 *data)
3219 struct mv88e6xxx_chip *chip = ds->priv;
3222 mutex_lock(&chip->reg_lock);
3224 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3225 err = mv88e6xxx_g2_get_eeprom16(chip, eeprom, data);
3229 mutex_unlock(&chip->reg_lock);
3234 eeprom->magic = 0xc3ec4951;
3239 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
3240 struct ethtool_eeprom *eeprom, u8 *data)
3242 struct mv88e6xxx_chip *chip = ds->priv;
3245 if (eeprom->magic != 0xc3ec4951)
3248 mutex_lock(&chip->reg_lock);
3250 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16))
3251 err = mv88e6xxx_g2_set_eeprom16(chip, eeprom, data);
3255 mutex_unlock(&chip->reg_lock);
3260 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3262 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3263 .family = MV88E6XXX_FAMILY_6097,
3264 .name = "Marvell 88E6085",
3265 .num_databases = 4096,
3267 .port_base_addr = 0x10,
3268 .age_time_coeff = 15000,
3269 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3273 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3274 .family = MV88E6XXX_FAMILY_6095,
3275 .name = "Marvell 88E6095/88E6095F",
3276 .num_databases = 256,
3278 .port_base_addr = 0x10,
3279 .age_time_coeff = 15000,
3280 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3284 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3285 .family = MV88E6XXX_FAMILY_6165,
3286 .name = "Marvell 88E6123",
3287 .num_databases = 4096,
3289 .port_base_addr = 0x10,
3290 .age_time_coeff = 15000,
3291 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3295 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3296 .family = MV88E6XXX_FAMILY_6185,
3297 .name = "Marvell 88E6131",
3298 .num_databases = 256,
3300 .port_base_addr = 0x10,
3301 .age_time_coeff = 15000,
3302 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3306 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3307 .family = MV88E6XXX_FAMILY_6165,
3308 .name = "Marvell 88E6161",
3309 .num_databases = 4096,
3311 .port_base_addr = 0x10,
3312 .age_time_coeff = 15000,
3313 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3317 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3318 .family = MV88E6XXX_FAMILY_6165,
3319 .name = "Marvell 88E6165",
3320 .num_databases = 4096,
3322 .port_base_addr = 0x10,
3323 .age_time_coeff = 15000,
3324 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3328 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3329 .family = MV88E6XXX_FAMILY_6351,
3330 .name = "Marvell 88E6171",
3331 .num_databases = 4096,
3333 .port_base_addr = 0x10,
3334 .age_time_coeff = 15000,
3335 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3339 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3340 .family = MV88E6XXX_FAMILY_6352,
3341 .name = "Marvell 88E6172",
3342 .num_databases = 4096,
3344 .port_base_addr = 0x10,
3345 .age_time_coeff = 15000,
3346 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3350 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3351 .family = MV88E6XXX_FAMILY_6351,
3352 .name = "Marvell 88E6175",
3353 .num_databases = 4096,
3355 .port_base_addr = 0x10,
3356 .age_time_coeff = 15000,
3357 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3361 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3362 .family = MV88E6XXX_FAMILY_6352,
3363 .name = "Marvell 88E6176",
3364 .num_databases = 4096,
3366 .port_base_addr = 0x10,
3367 .age_time_coeff = 15000,
3368 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3372 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3373 .family = MV88E6XXX_FAMILY_6185,
3374 .name = "Marvell 88E6185",
3375 .num_databases = 256,
3377 .port_base_addr = 0x10,
3378 .age_time_coeff = 15000,
3379 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3383 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3384 .family = MV88E6XXX_FAMILY_6352,
3385 .name = "Marvell 88E6240",
3386 .num_databases = 4096,
3388 .port_base_addr = 0x10,
3389 .age_time_coeff = 15000,
3390 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3394 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3395 .family = MV88E6XXX_FAMILY_6320,
3396 .name = "Marvell 88E6320",
3397 .num_databases = 4096,
3399 .port_base_addr = 0x10,
3400 .age_time_coeff = 15000,
3401 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3405 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3406 .family = MV88E6XXX_FAMILY_6320,
3407 .name = "Marvell 88E6321",
3408 .num_databases = 4096,
3410 .port_base_addr = 0x10,
3411 .age_time_coeff = 15000,
3412 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3416 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3417 .family = MV88E6XXX_FAMILY_6351,
3418 .name = "Marvell 88E6350",
3419 .num_databases = 4096,
3421 .port_base_addr = 0x10,
3422 .age_time_coeff = 15000,
3423 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3427 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3428 .family = MV88E6XXX_FAMILY_6351,
3429 .name = "Marvell 88E6351",
3430 .num_databases = 4096,
3432 .port_base_addr = 0x10,
3433 .age_time_coeff = 15000,
3434 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3438 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3439 .family = MV88E6XXX_FAMILY_6352,
3440 .name = "Marvell 88E6352",
3441 .num_databases = 4096,
3443 .port_base_addr = 0x10,
3444 .age_time_coeff = 15000,
3445 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3449 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3453 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3454 if (mv88e6xxx_table[i].prod_num == prod_num)
3455 return &mv88e6xxx_table[i];
3460 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3462 const struct mv88e6xxx_info *info;
3463 unsigned int prod_num, rev;
3467 mutex_lock(&chip->reg_lock);
3468 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id);
3469 mutex_unlock(&chip->reg_lock);
3473 prod_num = (id & 0xfff0) >> 4;
3476 info = mv88e6xxx_lookup_info(prod_num);
3480 /* Update the compatible info with the probed one */
3483 err = mv88e6xxx_g2_require(chip);
3487 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3488 chip->info->prod_num, chip->info->name, rev);
3493 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3495 struct mv88e6xxx_chip *chip;
3497 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3503 mutex_init(&chip->reg_lock);
3508 static const struct mv88e6xxx_ops mv88e6xxx_g2_smi_phy_ops = {
3509 .read = mv88e6xxx_g2_smi_phy_read,
3510 .write = mv88e6xxx_g2_smi_phy_write,
3513 static const struct mv88e6xxx_ops mv88e6xxx_phy_ops = {
3514 .read = mv88e6xxx_read,
3515 .write = mv88e6xxx_write,
3518 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
3520 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SMI_PHY)) {
3521 chip->phy_ops = &mv88e6xxx_g2_smi_phy_ops;
3522 } else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3523 chip->phy_ops = &mv88e6xxx_phy_ppu_ops;
3524 mv88e6xxx_ppu_state_init(chip);
3526 chip->phy_ops = &mv88e6xxx_phy_ops;
3530 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
3532 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) {
3533 mv88e6xxx_ppu_state_destroy(chip);
3537 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3538 struct mii_bus *bus, int sw_addr)
3540 /* ADDR[0] pin is unavailable externally and considered zero */
3545 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3546 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP))
3547 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3552 chip->sw_addr = sw_addr;
3557 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds)
3559 struct mv88e6xxx_chip *chip = ds->priv;
3561 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA))
3562 return DSA_TAG_PROTO_EDSA;
3564 return DSA_TAG_PROTO_DSA;
3567 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3568 struct device *host_dev, int sw_addr,
3571 struct mv88e6xxx_chip *chip;
3572 struct mii_bus *bus;
3575 bus = dsa_host_dev_to_mii_bus(host_dev);
3579 chip = mv88e6xxx_alloc_chip(dsa_dev);
3583 /* Legacy SMI probing will only support chips similar to 88E6085 */
3584 chip->info = &mv88e6xxx_table[MV88E6085];
3586 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3590 err = mv88e6xxx_detect(chip);
3594 mv88e6xxx_phy_init(chip);
3596 err = mv88e6xxx_mdio_register(chip, NULL);
3602 return chip->info->name;
3604 devm_kfree(dsa_dev, chip);
3609 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
3610 const struct switchdev_obj_port_mdb *mdb,
3611 struct switchdev_trans *trans)
3613 /* We don't need any dynamic resource from the kernel (yet),
3614 * so skip the prepare phase.
3620 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
3621 const struct switchdev_obj_port_mdb *mdb,
3622 struct switchdev_trans *trans)
3624 struct mv88e6xxx_chip *chip = ds->priv;
3626 mutex_lock(&chip->reg_lock);
3627 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3628 GLOBAL_ATU_DATA_STATE_MC_STATIC))
3629 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n");
3630 mutex_unlock(&chip->reg_lock);
3633 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
3634 const struct switchdev_obj_port_mdb *mdb)
3636 struct mv88e6xxx_chip *chip = ds->priv;
3639 mutex_lock(&chip->reg_lock);
3640 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
3641 GLOBAL_ATU_DATA_STATE_UNUSED);
3642 mutex_unlock(&chip->reg_lock);
3647 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port,
3648 struct switchdev_obj_port_mdb *mdb,
3649 int (*cb)(struct switchdev_obj *obj))
3651 struct mv88e6xxx_chip *chip = ds->priv;
3654 mutex_lock(&chip->reg_lock);
3655 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb);
3656 mutex_unlock(&chip->reg_lock);
3661 static struct dsa_switch_ops mv88e6xxx_switch_ops = {
3662 .probe = mv88e6xxx_drv_probe,
3663 .get_tag_protocol = mv88e6xxx_get_tag_protocol,
3664 .setup = mv88e6xxx_setup,
3665 .set_addr = mv88e6xxx_set_addr,
3666 .adjust_link = mv88e6xxx_adjust_link,
3667 .get_strings = mv88e6xxx_get_strings,
3668 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats,
3669 .get_sset_count = mv88e6xxx_get_sset_count,
3670 .set_eee = mv88e6xxx_set_eee,
3671 .get_eee = mv88e6xxx_get_eee,
3672 #ifdef CONFIG_NET_DSA_HWMON
3673 .get_temp = mv88e6xxx_get_temp,
3674 .get_temp_limit = mv88e6xxx_get_temp_limit,
3675 .set_temp_limit = mv88e6xxx_set_temp_limit,
3676 .get_temp_alarm = mv88e6xxx_get_temp_alarm,
3678 .get_eeprom_len = mv88e6xxx_get_eeprom_len,
3679 .get_eeprom = mv88e6xxx_get_eeprom,
3680 .set_eeprom = mv88e6xxx_set_eeprom,
3681 .get_regs_len = mv88e6xxx_get_regs_len,
3682 .get_regs = mv88e6xxx_get_regs,
3683 .set_ageing_time = mv88e6xxx_set_ageing_time,
3684 .port_bridge_join = mv88e6xxx_port_bridge_join,
3685 .port_bridge_leave = mv88e6xxx_port_bridge_leave,
3686 .port_stp_state_set = mv88e6xxx_port_stp_state_set,
3687 .port_fast_age = mv88e6xxx_port_fast_age,
3688 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering,
3689 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare,
3690 .port_vlan_add = mv88e6xxx_port_vlan_add,
3691 .port_vlan_del = mv88e6xxx_port_vlan_del,
3692 .port_vlan_dump = mv88e6xxx_port_vlan_dump,
3693 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare,
3694 .port_fdb_add = mv88e6xxx_port_fdb_add,
3695 .port_fdb_del = mv88e6xxx_port_fdb_del,
3696 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3697 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare,
3698 .port_mdb_add = mv88e6xxx_port_mdb_add,
3699 .port_mdb_del = mv88e6xxx_port_mdb_del,
3700 .port_mdb_dump = mv88e6xxx_port_mdb_dump,
3703 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3704 struct device_node *np)
3706 struct device *dev = chip->dev;
3707 struct dsa_switch *ds;
3709 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3715 ds->ops = &mv88e6xxx_switch_ops;
3717 dev_set_drvdata(dev, ds);
3719 return dsa_register_switch(ds, np);
3722 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3724 dsa_unregister_switch(chip->ds);
3727 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3729 struct device *dev = &mdiodev->dev;
3730 struct device_node *np = dev->of_node;
3731 const struct mv88e6xxx_info *compat_info;
3732 struct mv88e6xxx_chip *chip;
3736 compat_info = of_device_get_match_data(dev);
3740 chip = mv88e6xxx_alloc_chip(dev);
3744 chip->info = compat_info;
3746 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3750 err = mv88e6xxx_detect(chip);
3754 mv88e6xxx_phy_init(chip);
3756 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3757 if (IS_ERR(chip->reset))
3758 return PTR_ERR(chip->reset);
3760 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_EEPROM16) &&
3761 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3762 chip->eeprom_len = eeprom_len;
3764 err = mv88e6xxx_mdio_register(chip, np);
3768 err = mv88e6xxx_register_switch(chip, np);
3770 mv88e6xxx_mdio_unregister(chip);
3777 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3779 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3780 struct mv88e6xxx_chip *chip = ds->priv;
3782 mv88e6xxx_phy_destroy(chip);
3783 mv88e6xxx_unregister_switch(chip);
3784 mv88e6xxx_mdio_unregister(chip);
3787 static const struct of_device_id mv88e6xxx_of_match[] = {
3789 .compatible = "marvell,mv88e6085",
3790 .data = &mv88e6xxx_table[MV88E6085],
3795 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3797 static struct mdio_driver mv88e6xxx_driver = {
3798 .probe = mv88e6xxx_probe,
3799 .remove = mv88e6xxx_remove,
3801 .name = "mv88e6085",
3802 .of_match_table = mv88e6xxx_of_match,
3806 static int __init mv88e6xxx_init(void)
3808 register_switch_driver(&mv88e6xxx_switch_ops);
3809 return mdio_driver_register(&mv88e6xxx_driver);
3811 module_init(mv88e6xxx_init);
3813 static void __exit mv88e6xxx_cleanup(void)
3815 mdio_driver_unregister(&mv88e6xxx_driver);
3816 unregister_switch_driver(&mv88e6xxx_switch_ops);
3818 module_exit(mv88e6xxx_cleanup);
3820 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3821 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3822 MODULE_LICENSE("GPL");