2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
133 return mdiobus_write_nested(bus, addr, reg, val);
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
201 for (i = 0; i < 6; i++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
240 unsigned long timeout;
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
261 unsigned long timeout;
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
280 struct mv88e6xxx_priv_state *ps;
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
296 schedule_work(&ps->ppu_work);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
304 mutex_lock(&ps->ppu_mutex);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
314 mutex_unlock(&ps->ppu_mutex);
317 ps->ppu_disabled = 1;
319 del_timer(&ps->ppu_timer);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
350 ret = mv88e6xxx_ppu_access_get(ds);
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
364 ret = mv88e6xxx_ppu_access_get(ds);
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
489 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
496 if (!phy_is_pseudo_fixed_link(phydev))
499 mutex_lock(&ps->smi_mutex);
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
513 reg |= PORT_PCS_CTRL_LINK_UP;
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
518 switch (phydev->speed) {
520 reg |= PORT_PCS_CTRL_1000;
523 reg |= PORT_PCS_CTRL_100;
526 reg |= PORT_PCS_CTRL_10;
529 pr_info("Unknown speed");
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
550 mutex_unlock(&ps->smi_mutex);
553 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
558 for (i = 0; i < 10; i++) {
559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
567 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
572 port = (port + 1) << 5;
574 /* Snapshot the hardware statistics counters for this port. */
575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
581 /* Wait for the snapshotting to complete. */
582 ret = _mv88e6xxx_stats_wait(ds);
589 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
602 ret = _mv88e6xxx_stats_wait(ds);
606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
619 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
684 switch (stat->type) {
688 return mv88e6xxx_6320_family(ds);
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
700 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
701 struct mv88e6xxx_hw_stat *s,
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
730 value = (((u64)high) << 16) | low;
734 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
736 struct mv88e6xxx_hw_stat *stat;
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
749 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
751 struct mv88e6xxx_hw_stat *stat;
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
763 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
771 mutex_lock(&ps->smi_mutex);
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
775 mutex_unlock(&ps->smi_mutex);
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
786 mutex_unlock(&ps->smi_mutex);
789 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
791 return 32 * sizeof(u16);
794 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
802 memset(p, 0xff, 32 * sizeof(u16));
804 for (i = 0; i < 32; i++) {
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
813 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
816 unsigned long timeout = jiffies + HZ / 10;
818 while (time_before(jiffies, timeout)) {
821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
827 usleep_range(1000, 2000);
832 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
844 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
850 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
856 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
868 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
879 ret = _mv88e6xxx_phy_wait(ds);
883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
886 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
899 return _mv88e6xxx_phy_wait(ds);
902 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
907 mutex_lock(&ps->smi_mutex);
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
920 e->eee_active = !!(reg & PORT_STATUS_EEE);
924 mutex_unlock(&ps->smi_mutex);
928 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
935 mutex_lock(&ps->smi_mutex);
937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
944 if (e->tx_lpi_enabled)
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
949 mutex_unlock(&ps->smi_mutex);
954 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
962 return _mv88e6xxx_atu_wait(ds);
965 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
982 data |= (entry->portv_trunkid << shift) & mask;
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
988 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
995 err = _mv88e6xxx_atu_wait(ds);
999 err = _mv88e6xxx_atu_data_write(ds, entry);
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1016 return _mv88e6xxx_atu_cmd(ds, op);
1019 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1021 struct mv88e6xxx_atu_entry entry = {
1023 .state = 0, /* EntryState bits must be 0 */
1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1029 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1032 struct mv88e6xxx_atu_entry entry = {
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1047 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1054 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1060 mutex_lock(&ps->smi_mutex);
1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1086 mutex_unlock(&ps->smi_mutex);
1090 static int _mv88e6xxx_port_vlan_map_set(struct dsa_switch *ds, int port,
1093 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1094 const u16 mask = (1 << ps->num_ports) - 1;
1097 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1102 reg |= output_ports & mask;
1104 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1107 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1113 case BR_STATE_DISABLED:
1114 stp_state = PORT_CONTROL_STATE_DISABLED;
1116 case BR_STATE_BLOCKING:
1117 case BR_STATE_LISTENING:
1118 stp_state = PORT_CONTROL_STATE_BLOCKING;
1120 case BR_STATE_LEARNING:
1121 stp_state = PORT_CONTROL_STATE_LEARNING;
1123 case BR_STATE_FORWARDING:
1125 stp_state = PORT_CONTROL_STATE_FORWARDING;
1129 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1131 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1132 * so we can not update the port state directly but need to schedule it.
1134 ps->ports[port].state = stp_state;
1135 set_bit(port, &ps->port_state_update_mask);
1136 schedule_work(&ps->bridge_work);
1141 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1145 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1149 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1154 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1156 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1157 pvid & PORT_DEFAULT_VLAN_MASK);
1160 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1162 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1163 GLOBAL_VTU_OP_BUSY);
1166 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1170 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1174 return _mv88e6xxx_vtu_wait(ds);
1177 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1181 ret = _mv88e6xxx_vtu_wait(ds);
1185 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1188 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1189 struct mv88e6xxx_vtu_stu_entry *entry,
1190 unsigned int nibble_offset)
1192 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1197 for (i = 0; i < 3; ++i) {
1198 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1199 GLOBAL_VTU_DATA_0_3 + i);
1206 for (i = 0; i < ps->num_ports; ++i) {
1207 unsigned int shift = (i % 4) * 4 + nibble_offset;
1208 u16 reg = regs[i / 4];
1210 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1216 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1217 struct mv88e6xxx_vtu_stu_entry *entry,
1218 unsigned int nibble_offset)
1220 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1221 u16 regs[3] = { 0 };
1225 for (i = 0; i < ps->num_ports; ++i) {
1226 unsigned int shift = (i % 4) * 4 + nibble_offset;
1227 u8 data = entry->data[i];
1229 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1232 for (i = 0; i < 3; ++i) {
1233 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1234 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1242 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1244 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1245 vid & GLOBAL_VTU_VID_MASK);
1248 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1249 struct mv88e6xxx_vtu_stu_entry *entry)
1251 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1254 ret = _mv88e6xxx_vtu_wait(ds);
1258 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1262 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1266 next.vid = ret & GLOBAL_VTU_VID_MASK;
1267 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1270 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1274 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1275 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1276 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1281 next.fid = ret & GLOBAL_VTU_FID_MASK;
1283 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1288 next.sid = ret & GLOBAL_VTU_SID_MASK;
1296 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1297 struct switchdev_obj_port_vlan *vlan,
1298 int (*cb)(struct switchdev_obj *obj))
1300 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1301 struct mv88e6xxx_vtu_stu_entry next;
1305 mutex_lock(&ps->smi_mutex);
1307 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1311 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1316 err = _mv88e6xxx_vtu_getnext(ds, &next);
1323 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1326 /* reinit and dump this VLAN obj */
1327 vlan->vid_begin = vlan->vid_end = next.vid;
1330 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1331 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1333 if (next.vid == pvid)
1334 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1336 err = cb(&vlan->obj);
1339 } while (next.vid < GLOBAL_VTU_VID_MASK);
1342 mutex_unlock(&ps->smi_mutex);
1347 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1348 struct mv88e6xxx_vtu_stu_entry *entry)
1353 ret = _mv88e6xxx_vtu_wait(ds);
1360 /* Write port member tags */
1361 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1365 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1366 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1367 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1368 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1372 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1373 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1378 reg = GLOBAL_VTU_VID_VALID;
1380 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1381 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1385 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1388 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1389 struct mv88e6xxx_vtu_stu_entry *entry)
1391 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1394 ret = _mv88e6xxx_vtu_wait(ds);
1398 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1399 sid & GLOBAL_VTU_SID_MASK);
1403 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1407 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1411 next.sid = ret & GLOBAL_VTU_SID_MASK;
1413 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1417 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1420 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1429 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1430 struct mv88e6xxx_vtu_stu_entry *entry)
1435 ret = _mv88e6xxx_vtu_wait(ds);
1442 /* Write port states */
1443 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1447 reg = GLOBAL_VTU_VID_VALID;
1449 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1453 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1454 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1458 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1461 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1467 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1468 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1472 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1475 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1476 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1478 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1484 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1485 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1489 fid |= (ret & PORT_CONTROL_1_FID_11_4_MASK) << 4;
1492 ret &= ~PORT_CONTROL_1_FID_11_4_MASK;
1493 ret |= (*new >> 4) & PORT_CONTROL_1_FID_11_4_MASK;
1495 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1500 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1509 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1511 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1514 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1516 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1519 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1521 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1522 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1523 struct mv88e6xxx_vtu_stu_entry vlan;
1526 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1528 /* Set every FID bit used by the (un)bridged ports */
1529 for (i = 0; i < ps->num_ports; ++i) {
1530 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1534 set_bit(*fid, fid_bitmap);
1537 /* Set every FID bit used by the VLAN entries */
1538 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1543 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1550 set_bit(vlan.fid, fid_bitmap);
1551 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1553 /* The reset value 0x000 is used to indicate that multiple address
1554 * databases are not needed. Return the next positive available.
1556 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1557 if (unlikely(*fid == MV88E6XXX_N_FID))
1560 /* Clear the database */
1561 return _mv88e6xxx_atu_flush(ds, *fid, true);
1564 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1565 struct mv88e6xxx_vtu_stu_entry *entry)
1567 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1568 struct mv88e6xxx_vtu_stu_entry vlan = {
1574 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1578 /* exclude all ports except the CPU and DSA ports */
1579 for (i = 0; i < ps->num_ports; ++i)
1580 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1581 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1582 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1584 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1585 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1586 struct mv88e6xxx_vtu_stu_entry vstp;
1588 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1589 * implemented, only one STU entry is needed to cover all VTU
1590 * entries. Thus, validate the SID 0.
1593 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1597 if (vstp.sid != vlan.sid || !vstp.valid) {
1598 memset(&vstp, 0, sizeof(vstp));
1600 vstp.sid = vlan.sid;
1602 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1612 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1613 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1620 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1624 err = _mv88e6xxx_vtu_getnext(ds, entry);
1628 if (entry->vid != vid || !entry->valid) {
1631 /* -ENOENT would've been more appropriate, but switchdev expects
1632 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1635 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1641 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1642 u16 vid_begin, u16 vid_end)
1644 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1645 struct mv88e6xxx_vtu_stu_entry vlan;
1651 mutex_lock(&ps->smi_mutex);
1653 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1658 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1665 if (vlan.vid > vid_end)
1668 for (i = 0; i < ps->num_ports; ++i) {
1669 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1673 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1676 if (ps->ports[i].bridge_dev ==
1677 ps->ports[port].bridge_dev)
1678 break; /* same bridge, check next VLAN */
1680 netdev_warn(ds->ports[port],
1681 "hardware VLAN %d already used by %s\n",
1683 netdev_name(ps->ports[i].bridge_dev));
1687 } while (vlan.vid < vid_end);
1690 mutex_unlock(&ps->smi_mutex);
1695 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1696 const struct switchdev_obj_port_vlan *vlan,
1697 struct switchdev_trans *trans)
1701 /* We reserve a few VLANs to isolate unbridged ports */
1702 if (vlan->vid_end >= 4000)
1705 /* If the requested port doesn't belong to the same bridge as the VLAN
1706 * members, do not support it (yet) and fallback to software VLAN.
1708 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1713 /* We don't need any dynamic resource from the kernel (yet),
1714 * so skip the prepare phase.
1719 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1722 struct mv88e6xxx_vtu_stu_entry vlan;
1725 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1729 vlan.data[port] = untagged ?
1730 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1731 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1733 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1736 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1737 const struct switchdev_obj_port_vlan *vlan,
1738 struct switchdev_trans *trans)
1740 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1741 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1742 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1746 mutex_lock(&ps->smi_mutex);
1748 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1749 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1754 /* no PVID with ranges, otherwise it's a bug */
1756 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1758 mutex_unlock(&ps->smi_mutex);
1763 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1765 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1766 struct mv88e6xxx_vtu_stu_entry vlan;
1769 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1773 /* Tell switchdev if this VLAN is handled in software */
1774 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1777 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1779 /* keep the VLAN unless all ports are excluded */
1781 for (i = 0; i < ps->num_ports; ++i) {
1782 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1785 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1791 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1795 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1798 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1799 const struct switchdev_obj_port_vlan *vlan)
1801 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1802 const u16 defpvid = 4000 + ds->index * DSA_MAX_PORTS + port;
1806 mutex_lock(&ps->smi_mutex);
1808 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1812 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1813 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1818 /* restore reserved VLAN ID */
1819 err = _mv88e6xxx_port_pvid_set(ds, port, defpvid);
1826 mutex_unlock(&ps->smi_mutex);
1831 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1832 const unsigned char *addr)
1836 for (i = 0; i < 3; i++) {
1837 ret = _mv88e6xxx_reg_write(
1838 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1839 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1847 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1851 for (i = 0; i < 3; i++) {
1852 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1853 GLOBAL_ATU_MAC_01 + i);
1856 addr[i * 2] = ret >> 8;
1857 addr[i * 2 + 1] = ret & 0xff;
1863 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1864 struct mv88e6xxx_atu_entry *entry)
1868 ret = _mv88e6xxx_atu_wait(ds);
1872 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1876 ret = _mv88e6xxx_atu_data_write(ds, entry);
1880 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1884 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1887 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1888 const unsigned char *addr, u16 vid,
1891 struct mv88e6xxx_atu_entry entry = { 0 };
1892 struct mv88e6xxx_vtu_stu_entry vlan;
1895 /* Null VLAN ID corresponds to the port private database */
1897 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
1899 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1903 entry.fid = vlan.fid;
1904 entry.state = state;
1905 ether_addr_copy(entry.mac, addr);
1906 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1907 entry.trunk = false;
1908 entry.portv_trunkid = BIT(port);
1911 return _mv88e6xxx_atu_load(ds, &entry);
1914 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1915 const struct switchdev_obj_port_fdb *fdb,
1916 struct switchdev_trans *trans)
1918 /* We don't need any dynamic resource from the kernel (yet),
1919 * so skip the prepare phase.
1924 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1925 const struct switchdev_obj_port_fdb *fdb,
1926 struct switchdev_trans *trans)
1928 int state = is_multicast_ether_addr(fdb->addr) ?
1929 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1930 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1934 mutex_lock(&ps->smi_mutex);
1935 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1936 mutex_unlock(&ps->smi_mutex);
1941 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1942 const struct switchdev_obj_port_fdb *fdb)
1944 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1947 mutex_lock(&ps->smi_mutex);
1948 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1949 GLOBAL_ATU_DATA_STATE_UNUSED);
1950 mutex_unlock(&ps->smi_mutex);
1955 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1956 struct mv88e6xxx_atu_entry *entry)
1958 struct mv88e6xxx_atu_entry next = { 0 };
1963 ret = _mv88e6xxx_atu_wait(ds);
1967 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1971 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1975 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1979 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1983 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1984 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1985 unsigned int mask, shift;
1987 if (ret & GLOBAL_ATU_DATA_TRUNK) {
1989 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1990 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1993 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1994 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1997 next.portv_trunkid = (ret & mask) >> shift;
2004 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2006 struct switchdev_obj_port_fdb *fdb,
2007 int (*cb)(struct switchdev_obj *obj))
2009 struct mv88e6xxx_atu_entry addr = {
2010 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2014 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2019 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2023 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2026 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2027 bool is_static = addr.state ==
2028 (is_multicast_ether_addr(addr.mac) ?
2029 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2030 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2033 ether_addr_copy(fdb->addr, addr.mac);
2034 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2036 err = cb(&fdb->obj);
2040 } while (!is_broadcast_ether_addr(addr.mac));
2045 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2046 struct switchdev_obj_port_fdb *fdb,
2047 int (*cb)(struct switchdev_obj *obj))
2049 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2050 struct mv88e6xxx_vtu_stu_entry vlan = {
2051 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2056 mutex_lock(&ps->smi_mutex);
2058 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2059 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2063 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2067 /* Dump VLANs' Filtering Information Databases */
2068 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2073 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2080 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2084 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2087 mutex_unlock(&ps->smi_mutex);
2092 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2093 struct net_device *bridge)
2095 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2097 ps->ports[port].bridge_dev = bridge;
2102 int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2104 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2106 ps->ports[port].bridge_dev = NULL;
2111 static int mv88e6xxx_setup_port_default_vlan(struct dsa_switch *ds, int port)
2113 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2114 const u16 pvid = 4000 + ds->index * DSA_MAX_PORTS + port;
2117 mutex_lock(&ps->smi_mutex);
2118 err = _mv88e6xxx_port_vlan_add(ds, port, pvid, true);
2120 err = _mv88e6xxx_port_pvid_set(ds, port, pvid);
2121 mutex_unlock(&ps->smi_mutex);
2125 static void mv88e6xxx_bridge_work(struct work_struct *work)
2127 struct mv88e6xxx_priv_state *ps;
2128 struct dsa_switch *ds;
2131 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2132 ds = ((struct dsa_switch *)ps) - 1;
2134 while (ps->port_state_update_mask) {
2135 port = __ffs(ps->port_state_update_mask);
2136 clear_bit(port, &ps->port_state_update_mask);
2137 mv88e6xxx_set_port_state(ds, port, ps->ports[port].state);
2141 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2143 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2147 mutex_lock(&ps->smi_mutex);
2149 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2150 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2151 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2152 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2153 /* MAC Forcing register: don't force link, speed,
2154 * duplex or flow control state to any particular
2155 * values on physical ports, but force the CPU port
2156 * and all DSA ports to their maximum bandwidth and
2159 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2160 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2161 reg &= ~PORT_PCS_CTRL_UNFORCED;
2162 reg |= PORT_PCS_CTRL_FORCE_LINK |
2163 PORT_PCS_CTRL_LINK_UP |
2164 PORT_PCS_CTRL_DUPLEX_FULL |
2165 PORT_PCS_CTRL_FORCE_DUPLEX;
2166 if (mv88e6xxx_6065_family(ds))
2167 reg |= PORT_PCS_CTRL_100;
2169 reg |= PORT_PCS_CTRL_1000;
2171 reg |= PORT_PCS_CTRL_UNFORCED;
2174 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2175 PORT_PCS_CTRL, reg);
2180 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2181 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2182 * tunneling, determine priority by looking at 802.1p and IP
2183 * priority fields (IP prio has precedence), and set STP state
2186 * If this is the CPU link, use DSA or EDSA tagging depending
2187 * on which tagging mode was configured.
2189 * If this is a link to another switch, use DSA tagging mode.
2191 * If this is the upstream port for this switch, enable
2192 * forwarding of unknown unicasts and multicasts.
2195 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2196 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2197 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2198 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2199 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2200 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2201 PORT_CONTROL_STATE_FORWARDING;
2202 if (dsa_is_cpu_port(ds, port)) {
2203 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2204 reg |= PORT_CONTROL_DSA_TAG;
2205 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2206 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2207 mv88e6xxx_6320_family(ds)) {
2208 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2209 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2211 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2212 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2213 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2216 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2217 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2218 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2219 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2220 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2221 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2224 if (dsa_is_dsa_port(ds, port)) {
2225 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2226 reg |= PORT_CONTROL_DSA_TAG;
2227 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2228 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2229 mv88e6xxx_6320_family(ds)) {
2230 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2233 if (port == dsa_upstream_port(ds))
2234 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2235 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2238 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2244 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2245 * 10240 bytes, enable secure 802.1q tags, don't discard tagged or
2246 * untagged frames on this port, do a destination address lookup on all
2247 * received packets as usual, disable ARP mirroring and don't send a
2248 * copy of all transmitted/received frames on this port to the CPU.
2251 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2252 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2253 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2254 reg = PORT_CONTROL_2_MAP_DA;
2256 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2257 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2258 reg |= PORT_CONTROL_2_JUMBO_10240;
2260 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2261 /* Set the upstream port this port should use */
2262 reg |= dsa_upstream_port(ds);
2263 /* enable forwarding of unknown multicast addresses to
2266 if (port == dsa_upstream_port(ds))
2267 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2270 reg |= PORT_CONTROL_2_8021Q_SECURE;
2273 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2274 PORT_CONTROL_2, reg);
2279 /* Port Association Vector: when learning source addresses
2280 * of packets, add the address to the address database using
2281 * a port bitmap that has only the bit for this port set and
2282 * the other bits clear.
2285 /* Disable learning for DSA and CPU ports */
2286 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2287 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2289 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2293 /* Egress rate control 2: disable egress rate control. */
2294 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2299 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2300 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2301 mv88e6xxx_6320_family(ds)) {
2302 /* Do not limit the period of time that this port can
2303 * be paused for by the remote end or the period of
2304 * time that this port can pause the remote end.
2306 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2307 PORT_PAUSE_CTRL, 0x0000);
2311 /* Port ATU control: disable limiting the number of
2312 * address database entries that this port is allowed
2315 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2316 PORT_ATU_CONTROL, 0x0000);
2317 /* Priority Override: disable DA, SA and VTU priority
2320 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2321 PORT_PRI_OVERRIDE, 0x0000);
2325 /* Port Ethertype: use the Ethertype DSA Ethertype
2328 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2329 PORT_ETH_TYPE, ETH_P_EDSA);
2332 /* Tag Remap: use an identity 802.1p prio -> switch
2335 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2336 PORT_TAG_REGMAP_0123, 0x3210);
2340 /* Tag Remap 2: use an identity 802.1p prio -> switch
2343 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2344 PORT_TAG_REGMAP_4567, 0x7654);
2349 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2350 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2351 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2352 mv88e6xxx_6320_family(ds)) {
2353 /* Rate Control: disable ingress rate limiting. */
2354 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2355 PORT_RATE_CONTROL, 0x0001);
2360 /* Port Control 1: disable trunking, disable sending
2361 * learning messages to this port.
2363 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2367 /* Port based VLAN map: give each port its own address
2368 * database, and allow every port to egress frames on all other ports.
2370 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2374 reg = BIT(ps->num_ports) - 1; /* all ports */
2375 reg &= ~BIT(port); /* except itself */
2376 ret = _mv88e6xxx_port_vlan_map_set(ds, port, reg);
2380 /* Default VLAN ID and priority: don't set a default VLAN
2381 * ID, and set the default packet priority to zero.
2383 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2386 mutex_unlock(&ps->smi_mutex);
2390 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2392 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2396 for (i = 0; i < ps->num_ports; i++) {
2397 ret = mv88e6xxx_setup_port(ds, i);
2401 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2404 ret = mv88e6xxx_setup_port_default_vlan(ds, i);
2411 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2413 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2415 mutex_init(&ps->smi_mutex);
2417 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2419 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2424 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2426 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2430 /* Set the default address aging time to 5 minutes, and
2431 * enable address learn messages to be sent to all message
2434 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2435 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2437 /* Configure the IP ToS mapping registers. */
2438 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2439 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2440 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2441 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2442 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2443 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2444 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2445 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2447 /* Configure the IEEE 802.1p priority mapping register. */
2448 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2450 /* Send all frames with destination addresses matching
2451 * 01:80:c2:00:00:0x to the CPU port.
2453 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2455 /* Ignore removed tag data on doubly tagged packets, disable
2456 * flow control messages, force flow control priority to the
2457 * highest, and send all special multicast frames to the CPU
2458 * port at the highest priority.
2460 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2461 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2462 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2464 /* Program the DSA routing table. */
2465 for (i = 0; i < 32; i++) {
2468 if (ds->pd->rtable &&
2469 i != ds->index && i < ds->dst->pd->nr_chips)
2470 nexthop = ds->pd->rtable[i] & 0x1f;
2472 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2473 GLOBAL2_DEVICE_MAPPING_UPDATE |
2474 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2478 /* Clear all trunk masks. */
2479 for (i = 0; i < 8; i++)
2480 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2481 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2482 ((1 << ps->num_ports) - 1));
2484 /* Clear all trunk mappings. */
2485 for (i = 0; i < 16; i++)
2486 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2487 GLOBAL2_TRUNK_MAPPING_UPDATE |
2488 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2490 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2491 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2492 mv88e6xxx_6320_family(ds)) {
2493 /* Send all frames with destination addresses matching
2494 * 01:80:c2:00:00:2x to the CPU port.
2496 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2498 /* Initialise cross-chip port VLAN table to reset
2501 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2503 /* Clear the priority override table. */
2504 for (i = 0; i < 16; i++)
2505 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2509 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2510 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2511 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2512 mv88e6xxx_6320_family(ds)) {
2513 /* Disable ingress rate limiting by resetting all
2514 * ingress rate limit registers to their initial
2517 for (i = 0; i < ps->num_ports; i++)
2518 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2522 /* Clear the statistics counters for all ports */
2523 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2525 /* Wait for the flush to complete. */
2526 mutex_lock(&ps->smi_mutex);
2527 ret = _mv88e6xxx_stats_wait(ds);
2531 /* Clear all ATU entries */
2532 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2536 /* Clear all the VTU and STU entries */
2537 ret = _mv88e6xxx_vtu_stu_flush(ds);
2539 mutex_unlock(&ps->smi_mutex);
2544 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2546 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2547 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2548 struct gpio_desc *gpiod = ds->pd->reset;
2549 unsigned long timeout;
2553 /* Set all ports to the disabled state. */
2554 for (i = 0; i < ps->num_ports; i++) {
2555 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2556 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2559 /* Wait for transmit queues to drain. */
2560 usleep_range(2000, 4000);
2562 /* If there is a gpio connected to the reset pin, toggle it */
2564 gpiod_set_value_cansleep(gpiod, 1);
2565 usleep_range(10000, 20000);
2566 gpiod_set_value_cansleep(gpiod, 0);
2567 usleep_range(10000, 20000);
2570 /* Reset the switch. Keep the PPU active if requested. The PPU
2571 * needs to be active to support indirect phy register access
2572 * through global registers 0x18 and 0x19.
2575 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2577 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2579 /* Wait up to one second for reset to complete. */
2580 timeout = jiffies + 1 * HZ;
2581 while (time_before(jiffies, timeout)) {
2582 ret = REG_READ(REG_GLOBAL, 0x00);
2583 if ((ret & is_reset) == is_reset)
2585 usleep_range(1000, 2000);
2587 if (time_after(jiffies, timeout))
2593 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2595 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2598 mutex_lock(&ps->smi_mutex);
2599 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2602 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2604 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2605 mutex_unlock(&ps->smi_mutex);
2609 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2612 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2615 mutex_lock(&ps->smi_mutex);
2616 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2620 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2622 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2623 mutex_unlock(&ps->smi_mutex);
2627 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2629 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2631 if (port >= 0 && port < ps->num_ports)
2637 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2639 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2640 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2646 mutex_lock(&ps->smi_mutex);
2647 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2648 mutex_unlock(&ps->smi_mutex);
2653 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2655 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2656 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2662 mutex_lock(&ps->smi_mutex);
2663 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2664 mutex_unlock(&ps->smi_mutex);
2669 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2671 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2672 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2678 mutex_lock(&ps->smi_mutex);
2679 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2680 mutex_unlock(&ps->smi_mutex);
2685 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2688 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2689 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2695 mutex_lock(&ps->smi_mutex);
2696 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2697 mutex_unlock(&ps->smi_mutex);
2701 #ifdef CONFIG_NET_DSA_HWMON
2703 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2705 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2711 mutex_lock(&ps->smi_mutex);
2713 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2717 /* Enable temperature sensor */
2718 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2722 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2726 /* Wait for temperature to stabilize */
2727 usleep_range(10000, 12000);
2729 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2735 /* Disable temperature sensor */
2736 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2740 *temp = ((val & 0x1f) - 5) * 5;
2743 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2744 mutex_unlock(&ps->smi_mutex);
2748 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2750 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2755 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2759 *temp = (ret & 0xff) - 25;
2764 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2766 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2767 return mv88e63xx_get_temp(ds, temp);
2769 return mv88e61xx_get_temp(ds, temp);
2772 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2774 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2777 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2782 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2786 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2791 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2793 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2796 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2799 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2802 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2803 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2804 (ret & 0xe0ff) | (temp << 8));
2807 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2809 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2812 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2817 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2821 *alarm = !!(ret & 0x40);
2825 #endif /* CONFIG_NET_DSA_HWMON */
2827 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2828 const struct mv88e6xxx_switch_id *table,
2831 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2837 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2841 /* Look up the exact switch ID */
2842 for (i = 0; i < num; ++i)
2843 if (table[i].id == ret)
2844 return table[i].name;
2846 /* Look up only the product number */
2847 for (i = 0; i < num; ++i) {
2848 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2849 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2850 ret & PORT_SWITCH_ID_REV_MASK,
2851 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2852 return table[i].name;
2859 static int __init mv88e6xxx_init(void)
2861 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2862 register_switch_driver(&mv88e6131_switch_driver);
2864 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2865 register_switch_driver(&mv88e6123_61_65_switch_driver);
2867 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2868 register_switch_driver(&mv88e6352_switch_driver);
2870 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2871 register_switch_driver(&mv88e6171_switch_driver);
2875 module_init(mv88e6xxx_init);
2877 static void __exit mv88e6xxx_cleanup(void)
2879 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2880 unregister_switch_driver(&mv88e6171_switch_driver);
2882 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2883 unregister_switch_driver(&mv88e6352_switch_driver);
2885 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2886 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2888 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2889 unregister_switch_driver(&mv88e6131_switch_driver);
2892 module_exit(mv88e6xxx_cleanup);
2894 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2895 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2896 MODULE_LICENSE("GPL");