drivers/net/dsa/mv88e6xxx.c

   1 /*
   2  * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
   3  * Copyright (c) 2008 Marvell Semiconductor
   4  *
   5  * Copyright (c) 2015 CMC Electronics, Inc.
   6  *      Added support for VLAN Table Unit operations
   7  *
   8  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/ethtool.h>
  19 #include <linux/if_bridge.h>
  20 #include <linux/jiffies.h>
  21 #include <linux/list.h>
  22 #include <linux/mdio.h>
  23 #include <linux/module.h>
  24 #include <linux/of_mdio.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/gpio/consumer.h>
  27 #include <linux/phy.h>
  28 #include <net/dsa.h>
  29 #include <net/switchdev.h>
  30 #include "mv88e6xxx.h"
  31
  32 static void assert_reg_lock(struct mv88e6xxx_priv_state *ps)
  33 {
  34         if (unlikely(!mutex_is_locked(&ps->reg_lock))) {
  35                 dev_err(ps->dev, "Switch registers lock not held!\n");
  36                 dump_stack();
  37         }
  38 }
  39
  40 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
  41  * use all 32 SMI bus addresses on its SMI bus, and all switch registers
  42  * will be directly accessible on some {device address,register address}
  43  * pair.  If the ADDR[4:0] pins are not strapped to zero, the switch
  44  * will only respond to SMI transactions to that specific address, and
  45  * an indirect addressing mechanism needs to be used to access its
  46  * registers.
  47  */
  48 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
  49 {
  50         int ret;
  51         int i;
  52
  53         for (i = 0; i < 16; i++) {
  54                 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
  55                 if (ret < 0)
  56                         return ret;
  57
  58                 if ((ret & SMI_CMD_BUSY) == 0)
  59                         return 0;
  60         }
  61
  62         return -ETIMEDOUT;
  63 }
  64
  65 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
  66                                 int reg)
  67 {
  68         int ret;
  69
  70         if (sw_addr == 0)
  71                 return mdiobus_read_nested(bus, addr, reg);
  72
  73         /* Wait for the bus to become free. */
  74         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  75         if (ret < 0)
  76                 return ret;
  77
  78         /* Transmit the read command. */
  79         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
  80                                    SMI_CMD_OP_22_READ | (addr << 5) | reg);
  81         if (ret < 0)
  82                 return ret;
  83
  84         /* Wait for the read command to complete. */
  85         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
  86         if (ret < 0)
  87                 return ret;
  88
  89         /* Read the data. */
  90         ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
  91         if (ret < 0)
  92                 return ret;
  93
  94         return ret & 0xffff;
  95 }
  96
  97 static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps,
  98                                int addr, int reg)
  99 {
 100         int ret;
 101
 102         assert_reg_lock(ps);
 103
 104         ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
 105         if (ret < 0)
 106                 return ret;
 107
 108         dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 109                 addr, reg, ret);
 110
 111         return ret;
 112 }
 113
 114 static int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr,
 115                               int reg)
 116 {
 117         int ret;
 118
 119         mutex_lock(&ps->reg_lock);
 120         ret = _mv88e6xxx_reg_read(ps, addr, reg);
 121         mutex_unlock(&ps->reg_lock);
 122
 123         return ret;
 124 }
 125
 126 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
 127                                  int reg, u16 val)
 128 {
 129         int ret;
 130
 131         if (sw_addr == 0)
 132                 return mdiobus_write_nested(bus, addr, reg, val);
 133
 134         /* Wait for the bus to become free. */
 135         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 136         if (ret < 0)
 137                 return ret;
 138
 139         /* Transmit the data to write. */
 140         ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
 141         if (ret < 0)
 142                 return ret;
 143
 144         /* Transmit the write command. */
 145         ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
 146                                    SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
 147         if (ret < 0)
 148                 return ret;
 149
 150         /* Wait for the write command to complete. */
 151         ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
 152         if (ret < 0)
 153                 return ret;
 154
 155         return 0;
 156 }
 157
 158 static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
 159                                 int reg, u16 val)
 160 {
 161         assert_reg_lock(ps);
 162
 163         dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
 164                 addr, reg, val);
 165
 166         return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
 167 }
 168
 169 static int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr,
 170                                int reg, u16 val)
 171 {
 172         int ret;
 173
 174         mutex_lock(&ps->reg_lock);
 175         ret = _mv88e6xxx_reg_write(ps, addr, reg, val);
 176         mutex_unlock(&ps->reg_lock);
 177
 178         return ret;
 179 }
 180
 181 static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
 182 {
 183         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 184         int err;
 185
 186         err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01,
 187                                   (addr[0] << 8) | addr[1]);
 188         if (err)
 189                 return err;
 190
 191         err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23,
 192                                   (addr[2] << 8) | addr[3]);
 193         if (err)
 194                 return err;
 195
 196         return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45,
 197                                    (addr[4] << 8) | addr[5]);
 198 }
 199
 200 static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
 201 {
 202         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 203         int ret;
 204         int i;
 205
 206         for (i = 0; i < 6; i++) {
 207                 int j;
 208
 209                 /* Write the MAC address byte. */
 210                 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
 211                                           GLOBAL2_SWITCH_MAC_BUSY |
 212                                           (i << 8) | addr[i]);
 213                 if (ret)
 214                         return ret;
 215
 216                 /* Wait for the write to complete. */
 217                 for (j = 0; j < 16; j++) {
 218                         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2,
 219                                                  GLOBAL2_SWITCH_MAC);
 220                         if (ret < 0)
 221                                 return ret;
 222
 223                         if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
 224                                 break;
 225                 }
 226                 if (j == 16)
 227                         return -ETIMEDOUT;
 228         }
 229
 230         return 0;
 231 }
 232
 233 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
 234 {
 235         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 236
 237         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC))
 238                 return mv88e6xxx_set_addr_indirect(ds, addr);
 239         else
 240                 return mv88e6xxx_set_addr_direct(ds, addr);
 241 }
 242
 243 static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_priv_state *ps,
 244                                       int addr, int regnum)
 245 {
 246         if (addr >= 0)
 247                 return _mv88e6xxx_reg_read(ps, addr, regnum);
 248         return 0xffff;
 249 }
 250
 251 static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_priv_state *ps,
 252                                        int addr, int regnum, u16 val)
 253 {
 254         if (addr >= 0)
 255                 return _mv88e6xxx_reg_write(ps, addr, regnum, val);
 256         return 0;
 257 }
 258
 259 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
 260 {
 261         int ret;
 262         unsigned long timeout;
 263
 264         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
 265         if (ret < 0)
 266                 return ret;
 267
 268         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
 269                                    ret & ~GLOBAL_CONTROL_PPU_ENABLE);
 270         if (ret)
 271                 return ret;
 272
 273         timeout = jiffies + 1 * HZ;
 274         while (time_before(jiffies, timeout)) {
 275                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
 276                 if (ret < 0)
 277                         return ret;
 278
 279                 usleep_range(1000, 2000);
 280                 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
 281                     GLOBAL_STATUS_PPU_POLLING)
 282                         return 0;
 283         }
 284
 285         return -ETIMEDOUT;
 286 }
 287
 288 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
 289 {
 290         int ret, err;
 291         unsigned long timeout;
 292
 293         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL);
 294         if (ret < 0)
 295                 return ret;
 296
 297         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL,
 298                                    ret | GLOBAL_CONTROL_PPU_ENABLE);
 299         if (err)
 300                 return err;
 301
 302         timeout = jiffies + 1 * HZ;
 303         while (time_before(jiffies, timeout)) {
 304                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS);
 305                 if (ret < 0)
 306                         return ret;
 307
 308                 usleep_range(1000, 2000);
 309                 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
 310                     GLOBAL_STATUS_PPU_POLLING)
 311                         return 0;
 312         }
 313
 314         return -ETIMEDOUT;
 315 }
 316
 317 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
 318 {
 319         struct mv88e6xxx_priv_state *ps;
 320
 321         ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
 322
 323         mutex_lock(&ps->reg_lock);
 324
 325         if (mutex_trylock(&ps->ppu_mutex)) {
 326                 if (mv88e6xxx_ppu_enable(ps) == 0)
 327                         ps->ppu_disabled = 0;
 328                 mutex_unlock(&ps->ppu_mutex);
 329         }
 330
 331         mutex_unlock(&ps->reg_lock);
 332 }
 333
 334 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
 335 {
 336         struct mv88e6xxx_priv_state *ps = (void *)_ps;
 337
 338         schedule_work(&ps->ppu_work);
 339 }
 340
 341 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps)
 342 {
 343         int ret;
 344
 345         mutex_lock(&ps->ppu_mutex);
 346
 347         /* If the PHY polling unit is enabled, disable it so that
 348          * we can access the PHY registers.  If it was already
 349          * disabled, cancel the timer that is going to re-enable
 350          * it.
 351          */
 352         if (!ps->ppu_disabled) {
 353                 ret = mv88e6xxx_ppu_disable(ps);
 354                 if (ret < 0) {
 355                         mutex_unlock(&ps->ppu_mutex);
 356                         return ret;
 357                 }
 358                 ps->ppu_disabled = 1;
 359         } else {
 360                 del_timer(&ps->ppu_timer);
 361                 ret = 0;
 362         }
 363
 364         return ret;
 365 }
 366
 367 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps)
 368 {
 369         /* Schedule a timer to re-enable the PHY polling unit. */
 370         mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
 371         mutex_unlock(&ps->ppu_mutex);
 372 }
 373
 374 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps)
 375 {
 376         mutex_init(&ps->ppu_mutex);
 377         INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
 378         init_timer(&ps->ppu_timer);
 379         ps->ppu_timer.data = (unsigned long)ps;
 380         ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
 381 }
 382
 383 static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_priv_state *ps, int addr,
 384                                    int regnum)
 385 {
 386         int ret;
 387
 388         ret = mv88e6xxx_ppu_access_get(ps);
 389         if (ret >= 0) {
 390                 ret = _mv88e6xxx_reg_read(ps, addr, regnum);
 391                 mv88e6xxx_ppu_access_put(ps);
 392         }
 393
 394         return ret;
 395 }
 396
 397 static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_priv_state *ps, int addr,
 398                                     int regnum, u16 val)
 399 {
 400         int ret;
 401
 402         ret = mv88e6xxx_ppu_access_get(ps);
 403         if (ret >= 0) {
 404                 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val);
 405                 mv88e6xxx_ppu_access_put(ps);
 406         }
 407
 408         return ret;
 409 }
 410
 411 static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps)
 412 {
 413         return ps->info->family == MV88E6XXX_FAMILY_6065;
 414 }
 415
 416 static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps)
 417 {
 418         return ps->info->family == MV88E6XXX_FAMILY_6095;
 419 }
 420
 421 static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps)
 422 {
 423         return ps->info->family == MV88E6XXX_FAMILY_6097;
 424 }
 425
 426 static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps)
 427 {
 428         return ps->info->family == MV88E6XXX_FAMILY_6165;
 429 }
 430
 431 static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps)
 432 {
 433         return ps->info->family == MV88E6XXX_FAMILY_6185;
 434 }
 435
 436 static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps)
 437 {
 438         return ps->info->family == MV88E6XXX_FAMILY_6320;
 439 }
 440
 441 static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps)
 442 {
 443         return ps->info->family == MV88E6XXX_FAMILY_6351;
 444 }
 445
 446 static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps)
 447 {
 448         return ps->info->family == MV88E6XXX_FAMILY_6352;
 449 }
 450
 451 static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps)
 452 {
 453         return ps->info->num_databases;
 454 }
 455
 456 static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
 457 {
 458         /* Does the device have dedicated FID registers for ATU and VTU ops? */
 459         if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
 460             mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps))
 461                 return true;
 462
 463         return false;
 464 }
 465
 466 /* We expect the switch to perform auto negotiation if there is a real
 467  * phy. However, in the case of a fixed link phy, we force the port
 468  * settings from the fixed link settings.
 469  */
 470 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
 471                                   struct phy_device *phydev)
 472 {
 473         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 474         u32 reg;
 475         int ret;
 476
 477         if (!phy_is_pseudo_fixed_link(phydev))
 478                 return;
 479
 480         mutex_lock(&ps->reg_lock);
 481
 482         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
 483         if (ret < 0)
 484                 goto out;
 485
 486         reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
 487                       PORT_PCS_CTRL_FORCE_LINK |
 488                       PORT_PCS_CTRL_DUPLEX_FULL |
 489                       PORT_PCS_CTRL_FORCE_DUPLEX |
 490                       PORT_PCS_CTRL_UNFORCED);
 491
 492         reg |= PORT_PCS_CTRL_FORCE_LINK;
 493         if (phydev->link)
 494                 reg |= PORT_PCS_CTRL_LINK_UP;
 495
 496         if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100)
 497                 goto out;
 498
 499         switch (phydev->speed) {
 500         case SPEED_1000:
 501                 reg |= PORT_PCS_CTRL_1000;
 502                 break;
 503         case SPEED_100:
 504                 reg |= PORT_PCS_CTRL_100;
 505                 break;
 506         case SPEED_10:
 507                 reg |= PORT_PCS_CTRL_10;
 508                 break;
 509         default:
 510                 pr_info("Unknown speed");
 511                 goto out;
 512         }
 513
 514         reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
 515         if (phydev->duplex == DUPLEX_FULL)
 516                 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
 517
 518         if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) &&
 519             (port >= ps->info->num_ports - 2)) {
 520                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 521                         reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
 522                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 523                         reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
 524                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 525                         reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
 526                                 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
 527         }
 528         _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg);
 529
 530 out:
 531         mutex_unlock(&ps->reg_lock);
 532 }
 533
 534 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
 535 {
 536         int ret;
 537         int i;
 538
 539         for (i = 0; i < 10; i++) {
 540                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP);
 541                 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
 542                         return 0;
 543         }
 544
 545         return -ETIMEDOUT;
 546 }
 547
 548 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps,
 549                                      int port)
 550 {
 551         int ret;
 552
 553         if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
 554                 port = (port + 1) << 5;
 555
 556         /* Snapshot the hardware statistics counters for this port. */
 557         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
 558                                    GLOBAL_STATS_OP_CAPTURE_PORT |
 559                                    GLOBAL_STATS_OP_HIST_RX_TX | port);
 560         if (ret < 0)
 561                 return ret;
 562
 563         /* Wait for the snapshotting to complete. */
 564         ret = _mv88e6xxx_stats_wait(ps);
 565         if (ret < 0)
 566                 return ret;
 567
 568         return 0;
 569 }
 570
 571 static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
 572                                   int stat, u32 *val)
 573 {
 574         u32 _val;
 575         int ret;
 576
 577         *val = 0;
 578
 579         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
 580                                    GLOBAL_STATS_OP_READ_CAPTURED |
 581                                    GLOBAL_STATS_OP_HIST_RX_TX | stat);
 582         if (ret < 0)
 583                 return;
 584
 585         ret = _mv88e6xxx_stats_wait(ps);
 586         if (ret < 0)
 587                 return;
 588
 589         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
 590         if (ret < 0)
 591                 return;
 592
 593         _val = ret << 16;
 594
 595         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
 596         if (ret < 0)
 597                 return;
 598
 599         *val = _val | ret;
 600 }
 601
 602 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
 603         { "in_good_octets",     8, 0x00, BANK0, },
 604         { "in_bad_octets",      4, 0x02, BANK0, },
 605         { "in_unicast",         4, 0x04, BANK0, },
 606         { "in_broadcasts",      4, 0x06, BANK0, },
 607         { "in_multicasts",      4, 0x07, BANK0, },
 608         { "in_pause",           4, 0x16, BANK0, },
 609         { "in_undersize",       4, 0x18, BANK0, },
 610         { "in_fragments",       4, 0x19, BANK0, },
 611         { "in_oversize",        4, 0x1a, BANK0, },
 612         { "in_jabber",          4, 0x1b, BANK0, },
 613         { "in_rx_error",        4, 0x1c, BANK0, },
 614         { "in_fcs_error",       4, 0x1d, BANK0, },
 615         { "out_octets",         8, 0x0e, BANK0, },
 616         { "out_unicast",        4, 0x10, BANK0, },
 617         { "out_broadcasts",     4, 0x13, BANK0, },
 618         { "out_multicasts",     4, 0x12, BANK0, },
 619         { "out_pause",          4, 0x15, BANK0, },
 620         { "excessive",          4, 0x11, BANK0, },
 621         { "collisions",         4, 0x1e, BANK0, },
 622         { "deferred",           4, 0x05, BANK0, },
 623         { "single",             4, 0x14, BANK0, },
 624         { "multiple",           4, 0x17, BANK0, },
 625         { "out_fcs_error",      4, 0x03, BANK0, },
 626         { "late",               4, 0x1f, BANK0, },
 627         { "hist_64bytes",       4, 0x08, BANK0, },
 628         { "hist_65_127bytes",   4, 0x09, BANK0, },
 629         { "hist_128_255bytes",  4, 0x0a, BANK0, },
 630         { "hist_256_511bytes",  4, 0x0b, BANK0, },
 631         { "hist_512_1023bytes", 4, 0x0c, BANK0, },
 632         { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
 633         { "sw_in_discards",     4, 0x10, PORT, },
 634         { "sw_in_filtered",     2, 0x12, PORT, },
 635         { "sw_out_filtered",    2, 0x13, PORT, },
 636         { "in_discards",        4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 637         { "in_filtered",        4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 638         { "in_accepted",        4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 639         { "in_bad_accepted",    4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 640         { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 641         { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 642         { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 643         { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 644         { "tcam_counter_0",     4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 645         { "tcam_counter_1",     4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 646         { "tcam_counter_2",     4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 647         { "tcam_counter_3",     4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 648         { "in_da_unknown",      4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
 649         { "in_management",      4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 650         { "out_queue_0",        4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 651         { "out_queue_1",        4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 652         { "out_queue_2",        4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 653         { "out_queue_3",        4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 654         { "out_queue_4",        4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 655         { "out_queue_5",        4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 656         { "out_queue_6",        4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 657         { "out_queue_7",        4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 658         { "out_cut_through",    4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
 659         { "out_octets_a",       4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
 660         { "out_octets_b",       4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
 661         { "out_management",     4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
 662 };
 663
 664 static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps,
 665                                struct mv88e6xxx_hw_stat *stat)
 666 {
 667         switch (stat->type) {
 668         case BANK0:
 669                 return true;
 670         case BANK1:
 671                 return mv88e6xxx_6320_family(ps);
 672         case PORT:
 673                 return mv88e6xxx_6095_family(ps) ||
 674                         mv88e6xxx_6185_family(ps) ||
 675                         mv88e6xxx_6097_family(ps) ||
 676                         mv88e6xxx_6165_family(ps) ||
 677                         mv88e6xxx_6351_family(ps) ||
 678                         mv88e6xxx_6352_family(ps);
 679         }
 680         return false;
 681 }
 682
 683 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
 684                                             struct mv88e6xxx_hw_stat *s,
 685                                             int port)
 686 {
 687         u32 low;
 688         u32 high = 0;
 689         int ret;
 690         u64 value;
 691
 692         switch (s->type) {
 693         case PORT:
 694                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg);
 695                 if (ret < 0)
 696                         return UINT64_MAX;
 697
 698                 low = ret;
 699                 if (s->sizeof_stat == 4) {
 700                         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port),
 701                                                   s->reg + 1);
 702                         if (ret < 0)
 703                                 return UINT64_MAX;
 704                         high = ret;
 705                 }
 706                 break;
 707         case BANK0:
 708         case BANK1:
 709                 _mv88e6xxx_stats_read(ps, s->reg, &low);
 710                 if (s->sizeof_stat == 8)
 711                         _mv88e6xxx_stats_read(ps, s->reg + 1, &high);
 712         }
 713         value = (((u64)high) << 16) | low;
 714         return value;
 715 }
 716
 717 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
 718                                   uint8_t *data)
 719 {
 720         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 721         struct mv88e6xxx_hw_stat *stat;
 722         int i, j;
 723
 724         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 725                 stat = &mv88e6xxx_hw_stats[i];
 726                 if (mv88e6xxx_has_stat(ps, stat)) {
 727                         memcpy(data + j * ETH_GSTRING_LEN, stat->string,
 728                                ETH_GSTRING_LEN);
 729                         j++;
 730                 }
 731         }
 732 }
 733
 734 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
 735 {
 736         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 737         struct mv88e6xxx_hw_stat *stat;
 738         int i, j;
 739
 740         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 741                 stat = &mv88e6xxx_hw_stats[i];
 742                 if (mv88e6xxx_has_stat(ps, stat))
 743                         j++;
 744         }
 745         return j;
 746 }
 747
 748 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
 749                                         uint64_t *data)
 750 {
 751         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 752         struct mv88e6xxx_hw_stat *stat;
 753         int ret;
 754         int i, j;
 755
 756         mutex_lock(&ps->reg_lock);
 757
 758         ret = _mv88e6xxx_stats_snapshot(ps, port);
 759         if (ret < 0) {
 760                 mutex_unlock(&ps->reg_lock);
 761                 return;
 762         }
 763         for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
 764                 stat = &mv88e6xxx_hw_stats[i];
 765                 if (mv88e6xxx_has_stat(ps, stat)) {
 766                         data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port);
 767                         j++;
 768                 }
 769         }
 770
 771         mutex_unlock(&ps->reg_lock);
 772 }
 773
 774 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
 775 {
 776         return 32 * sizeof(u16);
 777 }
 778
 779 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
 780                                struct ethtool_regs *regs, void *_p)
 781 {
 782         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 783         u16 *p = _p;
 784         int i;
 785
 786         regs->version = 0;
 787
 788         memset(p, 0xff, 32 * sizeof(u16));
 789
 790         mutex_lock(&ps->reg_lock);
 791
 792         for (i = 0; i < 32; i++) {
 793                 int ret;
 794
 795                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i);
 796                 if (ret >= 0)
 797                         p[i] = ret;
 798         }
 799
 800         mutex_unlock(&ps->reg_lock);
 801 }
 802
 803 static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
 804                            u16 mask)
 805 {
 806         unsigned long timeout = jiffies + HZ / 10;
 807
 808         while (time_before(jiffies, timeout)) {
 809                 int ret;
 810
 811                 ret = _mv88e6xxx_reg_read(ps, reg, offset);
 812                 if (ret < 0)
 813                         return ret;
 814                 if (!(ret & mask))
 815                         return 0;
 816
 817                 usleep_range(1000, 2000);
 818         }
 819         return -ETIMEDOUT;
 820 }
 821
 822 static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg,
 823                           int offset, u16 mask)
 824 {
 825         int ret;
 826
 827         mutex_lock(&ps->reg_lock);
 828         ret = _mv88e6xxx_wait(ps, reg, offset, mask);
 829         mutex_unlock(&ps->reg_lock);
 830
 831         return ret;
 832 }
 833
 834 static int mv88e6xxx_mdio_wait(struct mv88e6xxx_priv_state *ps)
 835 {
 836         return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
 837                                GLOBAL2_SMI_OP_BUSY);
 838 }
 839
 840 static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
 841 {
 842         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 843
 844         return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 845                               GLOBAL2_EEPROM_OP_LOAD);
 846 }
 847
 848 static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
 849 {
 850         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 851
 852         return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 853                               GLOBAL2_EEPROM_OP_BUSY);
 854 }
 855
 856 static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
 857 {
 858         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 859         int ret;
 860
 861         mutex_lock(&ps->eeprom_mutex);
 862
 863         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 864                                   GLOBAL2_EEPROM_OP_READ |
 865                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 866         if (ret < 0)
 867                 goto error;
 868
 869         ret = mv88e6xxx_eeprom_busy_wait(ds);
 870         if (ret < 0)
 871                 goto error;
 872
 873         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
 874 error:
 875         mutex_unlock(&ps->eeprom_mutex);
 876         return ret;
 877 }
 878
 879 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
 880 {
 881         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 882
 883         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
 884                 return ps->eeprom_len;
 885
 886         return 0;
 887 }
 888
 889 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
 890                                 struct ethtool_eeprom *eeprom, u8 *data)
 891 {
 892         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 893         int offset;
 894         int len;
 895         int ret;
 896
 897         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
 898                 return -EOPNOTSUPP;
 899
 900         offset = eeprom->offset;
 901         len = eeprom->len;
 902         eeprom->len = 0;
 903
 904         eeprom->magic = 0xc3ec4951;
 905
 906         ret = mv88e6xxx_eeprom_load_wait(ds);
 907         if (ret < 0)
 908                 return ret;
 909
 910         if (offset & 1) {
 911                 int word;
 912
 913                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 914                 if (word < 0)
 915                         return word;
 916
 917                 *data++ = (word >> 8) & 0xff;
 918
 919                 offset++;
 920                 len--;
 921                 eeprom->len++;
 922         }
 923
 924         while (len >= 2) {
 925                 int word;
 926
 927                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 928                 if (word < 0)
 929                         return word;
 930
 931                 *data++ = word & 0xff;
 932                 *data++ = (word >> 8) & 0xff;
 933
 934                 offset += 2;
 935                 len -= 2;
 936                 eeprom->len += 2;
 937         }
 938
 939         if (len) {
 940                 int word;
 941
 942                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
 943                 if (word < 0)
 944                         return word;
 945
 946                 *data++ = word & 0xff;
 947
 948                 offset++;
 949                 len--;
 950                 eeprom->len++;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
 957 {
 958         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 959         int ret;
 960
 961         ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
 962         if (ret < 0)
 963                 return ret;
 964
 965         if (!(ret & GLOBAL2_EEPROM_OP_WRITE_EN))
 966                 return -EROFS;
 967
 968         return 0;
 969 }
 970
 971 static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
 972                                        u16 data)
 973 {
 974         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 975         int ret;
 976
 977         mutex_lock(&ps->eeprom_mutex);
 978
 979         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
 980         if (ret < 0)
 981                 goto error;
 982
 983         ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
 984                                   GLOBAL2_EEPROM_OP_WRITE |
 985                                   (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
 986         if (ret < 0)
 987                 goto error;
 988
 989         ret = mv88e6xxx_eeprom_busy_wait(ds);
 990 error:
 991         mutex_unlock(&ps->eeprom_mutex);
 992         return ret;
 993 }
 994
 995 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
 996                                 struct ethtool_eeprom *eeprom, u8 *data)
 997 {
 998         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
 999         int offset;
1000         int ret;
1001         int len;
1002
1003         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
1004                 return -EOPNOTSUPP;
1005
1006         if (eeprom->magic != 0xc3ec4951)
1007                 return -EINVAL;
1008
1009         ret = mv88e6xxx_eeprom_is_readonly(ds);
1010         if (ret)
1011                 return ret;
1012
1013         offset = eeprom->offset;
1014         len = eeprom->len;
1015         eeprom->len = 0;
1016
1017         ret = mv88e6xxx_eeprom_load_wait(ds);
1018         if (ret < 0)
1019                 return ret;
1020
1021         if (offset & 1) {
1022                 int word;
1023
1024                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1025                 if (word < 0)
1026                         return word;
1027
1028                 word = (*data++ << 8) | (word & 0xff);
1029
1030                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1031                 if (ret < 0)
1032                         return ret;
1033
1034                 offset++;
1035                 len--;
1036                 eeprom->len++;
1037         }
1038
1039         while (len >= 2) {
1040                 int word;
1041
1042                 word = *data++;
1043                 word |= *data++ << 8;
1044
1045                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1046                 if (ret < 0)
1047                         return ret;
1048
1049                 offset += 2;
1050                 len -= 2;
1051                 eeprom->len += 2;
1052         }
1053
1054         if (len) {
1055                 int word;
1056
1057                 word = mv88e6xxx_read_eeprom_word(ds, offset >> 1);
1058                 if (word < 0)
1059                         return word;
1060
1061                 word = (word & 0xff00) | *data++;
1062
1063                 ret = mv88e6xxx_write_eeprom_word(ds, offset >> 1, word);
1064                 if (ret < 0)
1065                         return ret;
1066
1067                 offset++;
1068                 len--;
1069                 eeprom->len++;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps)
1076 {
1077         return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP,
1078                                GLOBAL_ATU_OP_BUSY);
1079 }
1080
1081 static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_priv_state *ps,
1082                                         int addr, int regnum)
1083 {
1084         int ret;
1085
1086         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1087                                    GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1088                                    regnum);
1089         if (ret < 0)
1090                 return ret;
1091
1092         ret = mv88e6xxx_mdio_wait(ps);
1093         if (ret < 0)
1094                 return ret;
1095
1096         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1097
1098         return ret;
1099 }
1100
1101 static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_priv_state *ps,
1102                                          int addr, int regnum, u16 val)
1103 {
1104         int ret;
1105
1106         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1107         if (ret < 0)
1108                 return ret;
1109
1110         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP,
1111                                    GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1112                                    regnum);
1113
1114         return mv88e6xxx_mdio_wait(ps);
1115 }
1116
1117 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1118                              struct ethtool_eee *e)
1119 {
1120         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1121         int reg;
1122
1123         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1124                 return -EOPNOTSUPP;
1125
1126         mutex_lock(&ps->reg_lock);
1127
1128         reg = mv88e6xxx_mdio_read_indirect(ps, port, 16);
1129         if (reg < 0)
1130                 goto out;
1131
1132         e->eee_enabled = !!(reg & 0x0200);
1133         e->tx_lpi_enabled = !!(reg & 0x0100);
1134
1135         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
1136         if (reg < 0)
1137                 goto out;
1138
1139         e->eee_active = !!(reg & PORT_STATUS_EEE);
1140         reg = 0;
1141
1142 out:
1143         mutex_unlock(&ps->reg_lock);
1144         return reg;
1145 }
1146
1147 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1148                              struct phy_device *phydev, struct ethtool_eee *e)
1149 {
1150         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1151         int reg;
1152         int ret;
1153
1154         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE))
1155                 return -EOPNOTSUPP;
1156
1157         mutex_lock(&ps->reg_lock);
1158
1159         ret = mv88e6xxx_mdio_read_indirect(ps, port, 16);
1160         if (ret < 0)
1161                 goto out;
1162
1163         reg = ret & ~0x0300;
1164         if (e->eee_enabled)
1165                 reg |= 0x0200;
1166         if (e->tx_lpi_enabled)
1167                 reg |= 0x0100;
1168
1169         ret = mv88e6xxx_mdio_write_indirect(ps, port, 16, reg);
1170 out:
1171         mutex_unlock(&ps->reg_lock);
1172
1173         return ret;
1174 }
1175
1176 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
1177 {
1178         int ret;
1179
1180         if (mv88e6xxx_has_fid_reg(ps)) {
1181                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1182                 if (ret < 0)
1183                         return ret;
1184         } else if (mv88e6xxx_num_databases(ps) == 256) {
1185                 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1186                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1187                 if (ret < 0)
1188                         return ret;
1189
1190                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1191                                            (ret & 0xfff) |
1192                                            ((fid << 8) & 0xf000));
1193                 if (ret < 0)
1194                         return ret;
1195
1196                 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1197                 cmd |= fid & 0xf;
1198         }
1199
1200         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1201         if (ret < 0)
1202                 return ret;
1203
1204         return _mv88e6xxx_atu_wait(ps);
1205 }
1206
1207 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
1208                                      struct mv88e6xxx_atu_entry *entry)
1209 {
1210         u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1211
1212         if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1213                 unsigned int mask, shift;
1214
1215                 if (entry->trunk) {
1216                         data |= GLOBAL_ATU_DATA_TRUNK;
1217                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1218                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1219                 } else {
1220                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1221                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1222                 }
1223
1224                 data |= (entry->portv_trunkid << shift) & mask;
1225         }
1226
1227         return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1228 }
1229
1230 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
1231                                      struct mv88e6xxx_atu_entry *entry,
1232                                      bool static_too)
1233 {
1234         int op;
1235         int err;
1236
1237         err = _mv88e6xxx_atu_wait(ps);
1238         if (err)
1239                 return err;
1240
1241         err = _mv88e6xxx_atu_data_write(ps, entry);
1242         if (err)
1243                 return err;
1244
1245         if (entry->fid) {
1246                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1247                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1248         } else {
1249                 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1250                         GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1251         }
1252
1253         return _mv88e6xxx_atu_cmd(ps, entry->fid, op);
1254 }
1255
1256 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1257                                 u16 fid, bool static_too)
1258 {
1259         struct mv88e6xxx_atu_entry entry = {
1260                 .fid = fid,
1261                 .state = 0, /* EntryState bits must be 0 */
1262         };
1263
1264         return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1265 }
1266
1267 static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1268                                int from_port, int to_port, bool static_too)
1269 {
1270         struct mv88e6xxx_atu_entry entry = {
1271                 .trunk = false,
1272                 .fid = fid,
1273         };
1274
1275         /* EntryState bits must be 0xF */
1276         entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1277
1278         /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1279         entry.portv_trunkid = (to_port & 0x0f) << 4;
1280         entry.portv_trunkid |= from_port & 0x0f;
1281
1282         return _mv88e6xxx_atu_flush_move(ps, &entry, static_too);
1283 }
1284
1285 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid,
1286                                  int port, bool static_too)
1287 {
1288         /* Destination port 0xF means remove the entries */
1289         return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too);
1290 }
1291
1292 static const char * const mv88e6xxx_port_state_names[] = {
1293         [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1294         [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1295         [PORT_CONTROL_STATE_LEARNING] = "Learning",
1296         [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1297 };
1298
1299 static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1300                                  u8 state)
1301 {
1302         struct dsa_switch *ds = ps->ds;
1303         int reg, ret = 0;
1304         u8 oldstate;
1305
1306         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL);
1307         if (reg < 0)
1308                 return reg;
1309
1310         oldstate = reg & PORT_CONTROL_STATE_MASK;
1311
1312         if (oldstate != state) {
1313                 /* Flush forwarding database if we're moving a port
1314                  * from Learning or Forwarding state to Disabled or
1315                  * Blocking or Listening state.
1316                  */
1317                 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1318                      oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1319                     (state == PORT_CONTROL_STATE_DISABLED ||
1320                      state == PORT_CONTROL_STATE_BLOCKING)) {
1321                         ret = _mv88e6xxx_atu_remove(ps, 0, port, false);
1322                         if (ret)
1323                                 return ret;
1324                 }
1325
1326                 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1327                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL,
1328                                            reg);
1329                 if (ret)
1330                         return ret;
1331
1332                 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n",
1333                            mv88e6xxx_port_state_names[state],
1334                            mv88e6xxx_port_state_names[oldstate]);
1335         }
1336
1337         return ret;
1338 }
1339
1340 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1341                                           int port)
1342 {
1343         struct net_device *bridge = ps->ports[port].bridge_dev;
1344         const u16 mask = (1 << ps->info->num_ports) - 1;
1345         struct dsa_switch *ds = ps->ds;
1346         u16 output_ports = 0;
1347         int reg;
1348         int i;
1349
1350         /* allow CPU port or DSA link(s) to send frames to every port */
1351         if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1352                 output_ports = mask;
1353         } else {
1354                 for (i = 0; i < ps->info->num_ports; ++i) {
1355                         /* allow sending frames to every group member */
1356                         if (bridge && ps->ports[i].bridge_dev == bridge)
1357                                 output_ports |= BIT(i);
1358
1359                         /* allow sending frames to CPU port and DSA link(s) */
1360                         if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1361                                 output_ports |= BIT(i);
1362                 }
1363         }
1364
1365         /* prevent frames from going back out of the port they came in on */
1366         output_ports &= ~BIT(port);
1367
1368         reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1369         if (reg < 0)
1370                 return reg;
1371
1372         reg &= ~mask;
1373         reg |= output_ports & mask;
1374
1375         return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg);
1376 }
1377
1378 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1379                                          u8 state)
1380 {
1381         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1382         int stp_state;
1383         int err;
1384
1385         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE))
1386                 return;
1387
1388         switch (state) {
1389         case BR_STATE_DISABLED:
1390                 stp_state = PORT_CONTROL_STATE_DISABLED;
1391                 break;
1392         case BR_STATE_BLOCKING:
1393         case BR_STATE_LISTENING:
1394                 stp_state = PORT_CONTROL_STATE_BLOCKING;
1395                 break;
1396         case BR_STATE_LEARNING:
1397                 stp_state = PORT_CONTROL_STATE_LEARNING;
1398                 break;
1399         case BR_STATE_FORWARDING:
1400         default:
1401                 stp_state = PORT_CONTROL_STATE_FORWARDING;
1402                 break;
1403         }
1404
1405         mutex_lock(&ps->reg_lock);
1406         err = _mv88e6xxx_port_state(ps, port, stp_state);
1407         mutex_unlock(&ps->reg_lock);
1408
1409         if (err)
1410                 netdev_err(ds->ports[port].netdev,
1411                            "failed to update state to %s\n",
1412                            mv88e6xxx_port_state_names[stp_state]);
1413 }
1414
1415 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1416                                 u16 *new, u16 *old)
1417 {
1418         struct dsa_switch *ds = ps->ds;
1419         u16 pvid;
1420         int ret;
1421
1422         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN);
1423         if (ret < 0)
1424                 return ret;
1425
1426         pvid = ret & PORT_DEFAULT_VLAN_MASK;
1427
1428         if (new) {
1429                 ret &= ~PORT_DEFAULT_VLAN_MASK;
1430                 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1431
1432                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
1433                                            PORT_DEFAULT_VLAN, ret);
1434                 if (ret < 0)
1435                         return ret;
1436
1437                 netdev_dbg(ds->ports[port].netdev,
1438                            "DefaultVID %d (was %d)\n", *new, pvid);
1439         }
1440
1441         if (old)
1442                 *old = pvid;
1443
1444         return 0;
1445 }
1446
1447 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps,
1448                                     int port, u16 *pvid)
1449 {
1450         return _mv88e6xxx_port_pvid(ps, port, NULL, pvid);
1451 }
1452
1453 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps,
1454                                     int port, u16 pvid)
1455 {
1456         return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL);
1457 }
1458
1459 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps)
1460 {
1461         return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP,
1462                                GLOBAL_VTU_OP_BUSY);
1463 }
1464
1465 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op)
1466 {
1467         int ret;
1468
1469         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op);
1470         if (ret < 0)
1471                 return ret;
1472
1473         return _mv88e6xxx_vtu_wait(ps);
1474 }
1475
1476 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps)
1477 {
1478         int ret;
1479
1480         ret = _mv88e6xxx_vtu_wait(ps);
1481         if (ret < 0)
1482                 return ret;
1483
1484         return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL);
1485 }
1486
1487 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1488                                         struct mv88e6xxx_vtu_stu_entry *entry,
1489                                         unsigned int nibble_offset)
1490 {
1491         u16 regs[3];
1492         int i;
1493         int ret;
1494
1495         for (i = 0; i < 3; ++i) {
1496                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1497                                           GLOBAL_VTU_DATA_0_3 + i);
1498                 if (ret < 0)
1499                         return ret;
1500
1501                 regs[i] = ret;
1502         }
1503
1504         for (i = 0; i < ps->info->num_ports; ++i) {
1505                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1506                 u16 reg = regs[i / 4];
1507
1508                 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1509         }
1510
1511         return 0;
1512 }
1513
1514 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps,
1515                                    struct mv88e6xxx_vtu_stu_entry *entry)
1516 {
1517         return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0);
1518 }
1519
1520 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps,
1521                                    struct mv88e6xxx_vtu_stu_entry *entry)
1522 {
1523         return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2);
1524 }
1525
1526 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1527                                          struct mv88e6xxx_vtu_stu_entry *entry,
1528                                          unsigned int nibble_offset)
1529 {
1530         u16 regs[3] = { 0 };
1531         int i;
1532         int ret;
1533
1534         for (i = 0; i < ps->info->num_ports; ++i) {
1535                 unsigned int shift = (i % 4) * 4 + nibble_offset;
1536                 u8 data = entry->data[i];
1537
1538                 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1539         }
1540
1541         for (i = 0; i < 3; ++i) {
1542                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL,
1543                                            GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1544                 if (ret < 0)
1545                         return ret;
1546         }
1547
1548         return 0;
1549 }
1550
1551 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps,
1552                                     struct mv88e6xxx_vtu_stu_entry *entry)
1553 {
1554         return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0);
1555 }
1556
1557 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps,
1558                                     struct mv88e6xxx_vtu_stu_entry *entry)
1559 {
1560         return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2);
1561 }
1562
1563 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid)
1564 {
1565         return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID,
1566                                     vid & GLOBAL_VTU_VID_MASK);
1567 }
1568
1569 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
1570                                   struct mv88e6xxx_vtu_stu_entry *entry)
1571 {
1572         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1573         int ret;
1574
1575         ret = _mv88e6xxx_vtu_wait(ps);
1576         if (ret < 0)
1577                 return ret;
1578
1579         ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT);
1580         if (ret < 0)
1581                 return ret;
1582
1583         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1584         if (ret < 0)
1585                 return ret;
1586
1587         next.vid = ret & GLOBAL_VTU_VID_MASK;
1588         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1589
1590         if (next.valid) {
1591                 ret = mv88e6xxx_vtu_data_read(ps, &next);
1592                 if (ret < 0)
1593                         return ret;
1594
1595                 if (mv88e6xxx_has_fid_reg(ps)) {
1596                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1597                                                   GLOBAL_VTU_FID);
1598                         if (ret < 0)
1599                                 return ret;
1600
1601                         next.fid = ret & GLOBAL_VTU_FID_MASK;
1602                 } else if (mv88e6xxx_num_databases(ps) == 256) {
1603                         /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1604                          * VTU DBNum[3:0] are located in VTU Operation 3:0
1605                          */
1606                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1607                                                   GLOBAL_VTU_OP);
1608                         if (ret < 0)
1609                                 return ret;
1610
1611                         next.fid = (ret & 0xf00) >> 4;
1612                         next.fid |= ret & 0xf;
1613                 }
1614
1615                 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
1616                         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
1617                                                   GLOBAL_VTU_SID);
1618                         if (ret < 0)
1619                                 return ret;
1620
1621                         next.sid = ret & GLOBAL_VTU_SID_MASK;
1622                 }
1623         }
1624
1625         *entry = next;
1626         return 0;
1627 }
1628
1629 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1630                                     struct switchdev_obj_port_vlan *vlan,
1631                                     int (*cb)(struct switchdev_obj *obj))
1632 {
1633         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1634         struct mv88e6xxx_vtu_stu_entry next;
1635         u16 pvid;
1636         int err;
1637
1638         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
1639                 return -EOPNOTSUPP;
1640
1641         mutex_lock(&ps->reg_lock);
1642
1643         err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
1644         if (err)
1645                 goto unlock;
1646
1647         err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1648         if (err)
1649                 goto unlock;
1650
1651         do {
1652                 err = _mv88e6xxx_vtu_getnext(ps, &next);
1653                 if (err)
1654                         break;
1655
1656                 if (!next.valid)
1657                         break;
1658
1659                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1660                         continue;
1661
1662                 /* reinit and dump this VLAN obj */
1663                 vlan->vid_begin = next.vid;
1664                 vlan->vid_end = next.vid;
1665                 vlan->flags = 0;
1666
1667                 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1668                         vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1669
1670                 if (next.vid == pvid)
1671                         vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1672
1673                 err = cb(&vlan->obj);
1674                 if (err)
1675                         break;
1676         } while (next.vid < GLOBAL_VTU_VID_MASK);
1677
1678 unlock:
1679         mutex_unlock(&ps->reg_lock);
1680
1681         return err;
1682 }
1683
1684 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
1685                                     struct mv88e6xxx_vtu_stu_entry *entry)
1686 {
1687         u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1688         u16 reg = 0;
1689         int ret;
1690
1691         ret = _mv88e6xxx_vtu_wait(ps);
1692         if (ret < 0)
1693                 return ret;
1694
1695         if (!entry->valid)
1696                 goto loadpurge;
1697
1698         /* Write port member tags */
1699         ret = mv88e6xxx_vtu_data_write(ps, entry);
1700         if (ret < 0)
1701                 return ret;
1702
1703         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) {
1704                 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1705                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1706                 if (ret < 0)
1707                         return ret;
1708         }
1709
1710         if (mv88e6xxx_has_fid_reg(ps)) {
1711                 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1712                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1713                 if (ret < 0)
1714                         return ret;
1715         } else if (mv88e6xxx_num_databases(ps) == 256) {
1716                 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1717                  * VTU DBNum[3:0] are located in VTU Operation 3:0
1718                  */
1719                 op |= (entry->fid & 0xf0) << 8;
1720                 op |= entry->fid & 0xf;
1721         }
1722
1723         reg = GLOBAL_VTU_VID_VALID;
1724 loadpurge:
1725         reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1726         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1727         if (ret < 0)
1728                 return ret;
1729
1730         return _mv88e6xxx_vtu_cmd(ps, op);
1731 }
1732
1733 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
1734                                   struct mv88e6xxx_vtu_stu_entry *entry)
1735 {
1736         struct mv88e6xxx_vtu_stu_entry next = { 0 };
1737         int ret;
1738
1739         ret = _mv88e6xxx_vtu_wait(ps);
1740         if (ret < 0)
1741                 return ret;
1742
1743         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID,
1744                                    sid & GLOBAL_VTU_SID_MASK);
1745         if (ret < 0)
1746                 return ret;
1747
1748         ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT);
1749         if (ret < 0)
1750                 return ret;
1751
1752         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID);
1753         if (ret < 0)
1754                 return ret;
1755
1756         next.sid = ret & GLOBAL_VTU_SID_MASK;
1757
1758         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID);
1759         if (ret < 0)
1760                 return ret;
1761
1762         next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1763
1764         if (next.valid) {
1765                 ret = mv88e6xxx_stu_data_read(ps, &next);
1766                 if (ret < 0)
1767                         return ret;
1768         }
1769
1770         *entry = next;
1771         return 0;
1772 }
1773
1774 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
1775                                     struct mv88e6xxx_vtu_stu_entry *entry)
1776 {
1777         u16 reg = 0;
1778         int ret;
1779
1780         ret = _mv88e6xxx_vtu_wait(ps);
1781         if (ret < 0)
1782                 return ret;
1783
1784         if (!entry->valid)
1785                 goto loadpurge;
1786
1787         /* Write port states */
1788         ret = mv88e6xxx_stu_data_write(ps, entry);
1789         if (ret < 0)
1790                 return ret;
1791
1792         reg = GLOBAL_VTU_VID_VALID;
1793 loadpurge:
1794         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1795         if (ret < 0)
1796                 return ret;
1797
1798         reg = entry->sid & GLOBAL_VTU_SID_MASK;
1799         ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1800         if (ret < 0)
1801                 return ret;
1802
1803         return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1804 }
1805
1806 static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1807                                u16 *new, u16 *old)
1808 {
1809         struct dsa_switch *ds = ps->ds;
1810         u16 upper_mask;
1811         u16 fid;
1812         int ret;
1813
1814         if (mv88e6xxx_num_databases(ps) == 4096)
1815                 upper_mask = 0xff;
1816         else if (mv88e6xxx_num_databases(ps) == 256)
1817                 upper_mask = 0xf;
1818         else
1819                 return -EOPNOTSUPP;
1820
1821         /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1822         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN);
1823         if (ret < 0)
1824                 return ret;
1825
1826         fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1827
1828         if (new) {
1829                 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1830                 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1831
1832                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN,
1833                                            ret);
1834                 if (ret < 0)
1835                         return ret;
1836         }
1837
1838         /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1839         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1);
1840         if (ret < 0)
1841                 return ret;
1842
1843         fid |= (ret & upper_mask) << 4;
1844
1845         if (new) {
1846                 ret &= ~upper_mask;
1847                 ret |= (*new >> 4) & upper_mask;
1848
1849                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1,
1850                                            ret);
1851                 if (ret < 0)
1852                         return ret;
1853
1854                 netdev_dbg(ds->ports[port].netdev,
1855                            "FID %d (was %d)\n", *new, fid);
1856         }
1857
1858         if (old)
1859                 *old = fid;
1860
1861         return 0;
1862 }
1863
1864 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps,
1865                                    int port, u16 *fid)
1866 {
1867         return _mv88e6xxx_port_fid(ps, port, NULL, fid);
1868 }
1869
1870 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps,
1871                                    int port, u16 fid)
1872 {
1873         return _mv88e6xxx_port_fid(ps, port, &fid, NULL);
1874 }
1875
1876 static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1877 {
1878         DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1879         struct mv88e6xxx_vtu_stu_entry vlan;
1880         int i, err;
1881
1882         bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1883
1884         /* Set every FID bit used by the (un)bridged ports */
1885         for (i = 0; i < ps->info->num_ports; ++i) {
1886                 err = _mv88e6xxx_port_fid_get(ps, i, fid);
1887                 if (err)
1888                         return err;
1889
1890                 set_bit(*fid, fid_bitmap);
1891         }
1892
1893         /* Set every FID bit used by the VLAN entries */
1894         err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK);
1895         if (err)
1896                 return err;
1897
1898         do {
1899                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
1900                 if (err)
1901                         return err;
1902
1903                 if (!vlan.valid)
1904                         break;
1905
1906                 set_bit(vlan.fid, fid_bitmap);
1907         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1908
1909         /* The reset value 0x000 is used to indicate that multiple address
1910          * databases are not needed. Return the next positive available.
1911          */
1912         *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1913         if (unlikely(*fid >= mv88e6xxx_num_databases(ps)))
1914                 return -ENOSPC;
1915
1916         /* Clear the database */
1917         return _mv88e6xxx_atu_flush(ps, *fid, true);
1918 }
1919
1920 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
1921                               struct mv88e6xxx_vtu_stu_entry *entry)
1922 {
1923         struct dsa_switch *ds = ps->ds;
1924         struct mv88e6xxx_vtu_stu_entry vlan = {
1925                 .valid = true,
1926                 .vid = vid,
1927         };
1928         int i, err;
1929
1930         err = _mv88e6xxx_fid_new(ps, &vlan.fid);
1931         if (err)
1932                 return err;
1933
1934         /* exclude all ports except the CPU and DSA ports */
1935         for (i = 0; i < ps->info->num_ports; ++i)
1936                 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1937                         ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1938                         : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1939
1940         if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) ||
1941             mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) {
1942                 struct mv88e6xxx_vtu_stu_entry vstp;
1943
1944                 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1945                  * implemented, only one STU entry is needed to cover all VTU
1946                  * entries. Thus, validate the SID 0.
1947                  */
1948                 vlan.sid = 0;
1949                 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp);
1950                 if (err)
1951                         return err;
1952
1953                 if (vstp.sid != vlan.sid || !vstp.valid) {
1954                         memset(&vstp, 0, sizeof(vstp));
1955                         vstp.valid = true;
1956                         vstp.sid = vlan.sid;
1957
1958                         err = _mv88e6xxx_stu_loadpurge(ps, &vstp);
1959                         if (err)
1960                                 return err;
1961                 }
1962         }
1963
1964         *entry = vlan;
1965         return 0;
1966 }
1967
1968 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
1969                               struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1970 {
1971         int err;
1972
1973         if (!vid)
1974                 return -EINVAL;
1975
1976         err = _mv88e6xxx_vtu_vid_write(ps, vid - 1);
1977         if (err)
1978                 return err;
1979
1980         err = _mv88e6xxx_vtu_getnext(ps, entry);
1981         if (err)
1982                 return err;
1983
1984         if (entry->vid != vid || !entry->valid) {
1985                 if (!creat)
1986                         return -EOPNOTSUPP;
1987                 /* -ENOENT would've been more appropriate, but switchdev expects
1988                  * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1989                  */
1990
1991                 err = _mv88e6xxx_vtu_new(ps, vid, entry);
1992         }
1993
1994         return err;
1995 }
1996
1997 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1998                                         u16 vid_begin, u16 vid_end)
1999 {
2000         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2001         struct mv88e6xxx_vtu_stu_entry vlan;
2002         int i, err;
2003
2004         if (!vid_begin)
2005                 return -EOPNOTSUPP;
2006
2007         mutex_lock(&ps->reg_lock);
2008
2009         err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1);
2010         if (err)
2011                 goto unlock;
2012
2013         do {
2014                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
2015                 if (err)
2016                         goto unlock;
2017
2018                 if (!vlan.valid)
2019                         break;
2020
2021                 if (vlan.vid > vid_end)
2022                         break;
2023
2024                 for (i = 0; i < ps->info->num_ports; ++i) {
2025                         if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2026                                 continue;
2027
2028                         if (vlan.data[i] ==
2029                             GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2030                                 continue;
2031
2032                         if (ps->ports[i].bridge_dev ==
2033                             ps->ports[port].bridge_dev)
2034                                 break; /* same bridge, check next VLAN */
2035
2036                         netdev_warn(ds->ports[port].netdev,
2037                                     "hardware VLAN %d already used by %s\n",
2038                                     vlan.vid,
2039                                     netdev_name(ps->ports[i].bridge_dev));
2040                         err = -EOPNOTSUPP;
2041                         goto unlock;
2042                 }
2043         } while (vlan.vid < vid_end);
2044
2045 unlock:
2046         mutex_unlock(&ps->reg_lock);
2047
2048         return err;
2049 }
2050
2051 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2052         [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
2053         [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
2054         [PORT_CONTROL_2_8021Q_CHECK] = "Check",
2055         [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
2056 };
2057
2058 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2059                                          bool vlan_filtering)
2060 {
2061         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2062         u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2063                 PORT_CONTROL_2_8021Q_DISABLED;
2064         int ret;
2065
2066         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2067                 return -EOPNOTSUPP;
2068
2069         mutex_lock(&ps->reg_lock);
2070
2071         ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2);
2072         if (ret < 0)
2073                 goto unlock;
2074
2075         old = ret & PORT_CONTROL_2_8021Q_MASK;
2076
2077         if (new != old) {
2078                 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2079                 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2080
2081                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2,
2082                                            ret);
2083                 if (ret < 0)
2084                         goto unlock;
2085
2086                 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n",
2087                            mv88e6xxx_port_8021q_mode_names[new],
2088                            mv88e6xxx_port_8021q_mode_names[old]);
2089         }
2090
2091         ret = 0;
2092 unlock:
2093         mutex_unlock(&ps->reg_lock);
2094
2095         return ret;
2096 }
2097
2098 static int
2099 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2100                             const struct switchdev_obj_port_vlan *vlan,
2101                             struct switchdev_trans *trans)
2102 {
2103         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2104         int err;
2105
2106         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2107                 return -EOPNOTSUPP;
2108
2109         /* If the requested port doesn't belong to the same bridge as the VLAN
2110          * members, do not support it (yet) and fallback to software VLAN.
2111          */
2112         err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
2113                                            vlan->vid_end);
2114         if (err)
2115                 return err;
2116
2117         /* We don't need any dynamic resource from the kernel (yet),
2118          * so skip the prepare phase.
2119          */
2120         return 0;
2121 }
2122
2123 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2124                                     u16 vid, bool untagged)
2125 {
2126         struct mv88e6xxx_vtu_stu_entry vlan;
2127         int err;
2128
2129         err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true);
2130         if (err)
2131                 return err;
2132
2133         vlan.data[port] = untagged ?
2134                 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2135                 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2136
2137         return _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2138 }
2139
2140 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2141                                     const struct switchdev_obj_port_vlan *vlan,
2142                                     struct switchdev_trans *trans)
2143 {
2144         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2145         bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2146         bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2147         u16 vid;
2148
2149         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2150                 return;
2151
2152         mutex_lock(&ps->reg_lock);
2153
2154         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2155                 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged))
2156                         netdev_err(ds->ports[port].netdev,
2157                                    "failed to add VLAN %d%c\n",
2158                                    vid, untagged ? 'u' : 't');
2159
2160         if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end))
2161                 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
2162                            vlan->vid_end);
2163
2164         mutex_unlock(&ps->reg_lock);
2165 }
2166
2167 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2168                                     int port, u16 vid)
2169 {
2170         struct dsa_switch *ds = ps->ds;
2171         struct mv88e6xxx_vtu_stu_entry vlan;
2172         int i, err;
2173
2174         err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2175         if (err)
2176                 return err;
2177
2178         /* Tell switchdev if this VLAN is handled in software */
2179         if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2180                 return -EOPNOTSUPP;
2181
2182         vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2183
2184         /* keep the VLAN unless all ports are excluded */
2185         vlan.valid = false;
2186         for (i = 0; i < ps->info->num_ports; ++i) {
2187                 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2188                         continue;
2189
2190                 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
2191                         vlan.valid = true;
2192                         break;
2193                 }
2194         }
2195
2196         err = _mv88e6xxx_vtu_loadpurge(ps, &vlan);
2197         if (err)
2198                 return err;
2199
2200         return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false);
2201 }
2202
2203 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2204                                    const struct switchdev_obj_port_vlan *vlan)
2205 {
2206         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2207         u16 pvid, vid;
2208         int err = 0;
2209
2210         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU))
2211                 return -EOPNOTSUPP;
2212
2213         mutex_lock(&ps->reg_lock);
2214
2215         err = _mv88e6xxx_port_pvid_get(ps, port, &pvid);
2216         if (err)
2217                 goto unlock;
2218
2219         for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2220                 err = _mv88e6xxx_port_vlan_del(ps, port, vid);
2221                 if (err)
2222                         goto unlock;
2223
2224                 if (vid == pvid) {
2225                         err = _mv88e6xxx_port_pvid_set(ps, port, 0);
2226                         if (err)
2227                                 goto unlock;
2228                 }
2229         }
2230
2231 unlock:
2232         mutex_unlock(&ps->reg_lock);
2233
2234         return err;
2235 }
2236
2237 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
2238                                     const unsigned char *addr)
2239 {
2240         int i, ret;
2241
2242         for (i = 0; i < 3; i++) {
2243                 ret = _mv88e6xxx_reg_write(
2244                         ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2245                         (addr[i * 2] << 8) | addr[i * 2 + 1]);
2246                 if (ret < 0)
2247                         return ret;
2248         }
2249
2250         return 0;
2251 }
2252
2253 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2254                                    unsigned char *addr)
2255 {
2256         int i, ret;
2257
2258         for (i = 0; i < 3; i++) {
2259                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL,
2260                                           GLOBAL_ATU_MAC_01 + i);
2261                 if (ret < 0)
2262                         return ret;
2263                 addr[i * 2] = ret >> 8;
2264                 addr[i * 2 + 1] = ret & 0xff;
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps,
2271                                struct mv88e6xxx_atu_entry *entry)
2272 {
2273         int ret;
2274
2275         ret = _mv88e6xxx_atu_wait(ps);
2276         if (ret < 0)
2277                 return ret;
2278
2279         ret = _mv88e6xxx_atu_mac_write(ps, entry->mac);
2280         if (ret < 0)
2281                 return ret;
2282
2283         ret = _mv88e6xxx_atu_data_write(ps, entry);
2284         if (ret < 0)
2285                 return ret;
2286
2287         return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2288 }
2289
2290 static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
2291                                     const unsigned char *addr, u16 vid,
2292                                     u8 state)
2293 {
2294         struct mv88e6xxx_atu_entry entry = { 0 };
2295         struct mv88e6xxx_vtu_stu_entry vlan;
2296         int err;
2297
2298         /* Null VLAN ID corresponds to the port private database */
2299         if (vid == 0)
2300                 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid);
2301         else
2302                 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false);
2303         if (err)
2304                 return err;
2305
2306         entry.fid = vlan.fid;
2307         entry.state = state;
2308         ether_addr_copy(entry.mac, addr);
2309         if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2310                 entry.trunk = false;
2311                 entry.portv_trunkid = BIT(port);
2312         }
2313
2314         return _mv88e6xxx_atu_load(ps, &entry);
2315 }
2316
2317 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2318                                       const struct switchdev_obj_port_fdb *fdb,
2319                                       struct switchdev_trans *trans)
2320 {
2321         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2322
2323         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2324                 return -EOPNOTSUPP;
2325
2326         /* We don't need any dynamic resource from the kernel (yet),
2327          * so skip the prepare phase.
2328          */
2329         return 0;
2330 }
2331
2332 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2333                                    const struct switchdev_obj_port_fdb *fdb,
2334                                    struct switchdev_trans *trans)
2335 {
2336         int state = is_multicast_ether_addr(fdb->addr) ?
2337                 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2338                 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2339         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2340
2341         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2342                 return;
2343
2344         mutex_lock(&ps->reg_lock);
2345         if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state))
2346                 netdev_err(ds->ports[port].netdev,
2347                            "failed to load MAC address\n");
2348         mutex_unlock(&ps->reg_lock);
2349 }
2350
2351 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2352                                   const struct switchdev_obj_port_fdb *fdb)
2353 {
2354         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2355         int ret;
2356
2357         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2358                 return -EOPNOTSUPP;
2359
2360         mutex_lock(&ps->reg_lock);
2361         ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid,
2362                                        GLOBAL_ATU_DATA_STATE_UNUSED);
2363         mutex_unlock(&ps->reg_lock);
2364
2365         return ret;
2366 }
2367
2368 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
2369                                   struct mv88e6xxx_atu_entry *entry)
2370 {
2371         struct mv88e6xxx_atu_entry next = { 0 };
2372         int ret;
2373
2374         next.fid = fid;
2375
2376         ret = _mv88e6xxx_atu_wait(ps);
2377         if (ret < 0)
2378                 return ret;
2379
2380         ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2381         if (ret < 0)
2382                 return ret;
2383
2384         ret = _mv88e6xxx_atu_mac_read(ps, next.mac);
2385         if (ret < 0)
2386                 return ret;
2387
2388         ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA);
2389         if (ret < 0)
2390                 return ret;
2391
2392         next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2393         if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2394                 unsigned int mask, shift;
2395
2396                 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2397                         next.trunk = true;
2398                         mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2399                         shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2400                 } else {
2401                         next.trunk = false;
2402                         mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2403                         shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2404                 }
2405
2406                 next.portv_trunkid = (ret & mask) >> shift;
2407         }
2408
2409         *entry = next;
2410         return 0;
2411 }
2412
2413 static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2414                                         u16 fid, u16 vid, int port,
2415                                         struct switchdev_obj_port_fdb *fdb,
2416                                         int (*cb)(struct switchdev_obj *obj))
2417 {
2418         struct mv88e6xxx_atu_entry addr = {
2419                 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2420         };
2421         int err;
2422
2423         err = _mv88e6xxx_atu_mac_write(ps, addr.mac);
2424         if (err)
2425                 return err;
2426
2427         do {
2428                 err = _mv88e6xxx_atu_getnext(ps, fid, &addr);
2429                 if (err)
2430                         break;
2431
2432                 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2433                         break;
2434
2435                 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2436                         bool is_static = addr.state ==
2437                                 (is_multicast_ether_addr(addr.mac) ?
2438                                  GLOBAL_ATU_DATA_STATE_MC_STATIC :
2439                                  GLOBAL_ATU_DATA_STATE_UC_STATIC);
2440
2441                         fdb->vid = vid;
2442                         ether_addr_copy(fdb->addr, addr.mac);
2443                         fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2444
2445                         err = cb(&fdb->obj);
2446                         if (err)
2447                                 break;
2448                 }
2449         } while (!is_broadcast_ether_addr(addr.mac));
2450
2451         return err;
2452 }
2453
2454 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2455                                    struct switchdev_obj_port_fdb *fdb,
2456                                    int (*cb)(struct switchdev_obj *obj))
2457 {
2458         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2459         struct mv88e6xxx_vtu_stu_entry vlan = {
2460                 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2461         };
2462         u16 fid;
2463         int err;
2464
2465         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU))
2466                 return -EOPNOTSUPP;
2467
2468         mutex_lock(&ps->reg_lock);
2469
2470         /* Dump port's default Filtering Information Database (VLAN ID 0) */
2471         err = _mv88e6xxx_port_fid_get(ps, port, &fid);
2472         if (err)
2473                 goto unlock;
2474
2475         err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb);
2476         if (err)
2477                 goto unlock;
2478
2479         /* Dump VLANs' Filtering Information Databases */
2480         err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid);
2481         if (err)
2482                 goto unlock;
2483
2484         do {
2485                 err = _mv88e6xxx_vtu_getnext(ps, &vlan);
2486                 if (err)
2487                         break;
2488
2489                 if (!vlan.valid)
2490                         break;
2491
2492                 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port,
2493                                                    fdb, cb);
2494                 if (err)
2495                         break;
2496         } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2497
2498 unlock:
2499         mutex_unlock(&ps->reg_lock);
2500
2501         return err;
2502 }
2503
2504 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2505                                       struct net_device *bridge)
2506 {
2507         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2508         int i, err = 0;
2509
2510         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2511                 return -EOPNOTSUPP;
2512
2513         mutex_lock(&ps->reg_lock);
2514
2515         /* Assign the bridge and remap each port's VLANTable */
2516         ps->ports[port].bridge_dev = bridge;
2517
2518         for (i = 0; i < ps->info->num_ports; ++i) {
2519                 if (ps->ports[i].bridge_dev == bridge) {
2520                         err = _mv88e6xxx_port_based_vlan_map(ps, i);
2521                         if (err)
2522                                 break;
2523                 }
2524         }
2525
2526         mutex_unlock(&ps->reg_lock);
2527
2528         return err;
2529 }
2530
2531 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2532 {
2533         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2534         struct net_device *bridge = ps->ports[port].bridge_dev;
2535         int i;
2536
2537         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE))
2538                 return;
2539
2540         mutex_lock(&ps->reg_lock);
2541
2542         /* Unassign the bridge and remap each port's VLANTable */
2543         ps->ports[port].bridge_dev = NULL;
2544
2545         for (i = 0; i < ps->info->num_ports; ++i)
2546                 if (i == port || ps->ports[i].bridge_dev == bridge)
2547                         if (_mv88e6xxx_port_based_vlan_map(ps, i))
2548                                 netdev_warn(ds->ports[i].netdev,
2549                                             "failed to remap\n");
2550
2551         mutex_unlock(&ps->reg_lock);
2552 }
2553
2554 static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_priv_state *ps,
2555                                       int port, int page, int reg, int val)
2556 {
2557         int ret;
2558
2559         ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page);
2560         if (ret < 0)
2561                 goto restore_page_0;
2562
2563         ret = mv88e6xxx_mdio_write_indirect(ps, port, reg, val);
2564 restore_page_0:
2565         mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0);
2566
2567         return ret;
2568 }
2569
2570 static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_priv_state *ps,
2571                                      int port, int page, int reg)
2572 {
2573         int ret;
2574
2575         ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page);
2576         if (ret < 0)
2577                 goto restore_page_0;
2578
2579         ret = mv88e6xxx_mdio_read_indirect(ps, port, reg);
2580 restore_page_0:
2581         mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0);
2582
2583         return ret;
2584 }
2585
2586 static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2587 {
2588         bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE);
2589         u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2590         struct gpio_desc *gpiod = ps->reset;
2591         unsigned long timeout;
2592         int ret;
2593         int i;
2594
2595         /* Set all ports to the disabled state. */
2596         for (i = 0; i < ps->info->num_ports; i++) {
2597                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL);
2598                 if (ret < 0)
2599                         return ret;
2600
2601                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL,
2602                                            ret & 0xfffc);
2603                 if (ret)
2604                         return ret;
2605         }
2606
2607         /* Wait for transmit queues to drain. */
2608         usleep_range(2000, 4000);
2609
2610         /* If there is a gpio connected to the reset pin, toggle it */
2611         if (gpiod) {
2612                 gpiod_set_value_cansleep(gpiod, 1);
2613                 usleep_range(10000, 20000);
2614                 gpiod_set_value_cansleep(gpiod, 0);
2615                 usleep_range(10000, 20000);
2616         }
2617
2618         /* Reset the switch. Keep the PPU active if requested. The PPU
2619          * needs to be active to support indirect phy register access
2620          * through global registers 0x18 and 0x19.
2621          */
2622         if (ppu_active)
2623                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000);
2624         else
2625                 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400);
2626         if (ret)
2627                 return ret;
2628
2629         /* Wait up to one second for reset to complete. */
2630         timeout = jiffies + 1 * HZ;
2631         while (time_before(jiffies, timeout)) {
2632                 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00);
2633                 if (ret < 0)
2634                         return ret;
2635
2636                 if ((ret & is_reset) == is_reset)
2637                         break;
2638                 usleep_range(1000, 2000);
2639         }
2640         if (time_after(jiffies, timeout))
2641                 ret = -ETIMEDOUT;
2642         else
2643                 ret = 0;
2644
2645         return ret;
2646 }
2647
2648 static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
2649 {
2650         int ret;
2651
2652         ret = _mv88e6xxx_mdio_page_read(ps, REG_FIBER_SERDES,
2653                                         PAGE_FIBER_SERDES, MII_BMCR);
2654         if (ret < 0)
2655                 return ret;
2656
2657         if (ret & BMCR_PDOWN) {
2658                 ret &= ~BMCR_PDOWN;
2659                 ret = _mv88e6xxx_mdio_page_write(ps, REG_FIBER_SERDES,
2660                                                  PAGE_FIBER_SERDES, MII_BMCR,
2661                                                  ret);
2662         }
2663
2664         return ret;
2665 }
2666
2667 static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2668 {
2669         struct dsa_switch *ds = ps->ds;
2670         int ret;
2671         u16 reg;
2672
2673         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2674             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2675             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2676             mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) {
2677                 /* MAC Forcing register: don't force link, speed,
2678                  * duplex or flow control state to any particular
2679                  * values on physical ports, but force the CPU port
2680                  * and all DSA ports to their maximum bandwidth and
2681                  * full duplex.
2682                  */
2683                 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL);
2684                 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2685                         reg &= ~PORT_PCS_CTRL_UNFORCED;
2686                         reg |= PORT_PCS_CTRL_FORCE_LINK |
2687                                 PORT_PCS_CTRL_LINK_UP |
2688                                 PORT_PCS_CTRL_DUPLEX_FULL |
2689                                 PORT_PCS_CTRL_FORCE_DUPLEX;
2690                         if (mv88e6xxx_6065_family(ps))
2691                                 reg |= PORT_PCS_CTRL_100;
2692                         else
2693                                 reg |= PORT_PCS_CTRL_1000;
2694                 } else {
2695                         reg |= PORT_PCS_CTRL_UNFORCED;
2696                 }
2697
2698                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2699                                            PORT_PCS_CTRL, reg);
2700                 if (ret)
2701                         return ret;
2702         }
2703
2704         /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2705          * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2706          * tunneling, determine priority by looking at 802.1p and IP
2707          * priority fields (IP prio has precedence), and set STP state
2708          * to Forwarding.
2709          *
2710          * If this is the CPU link, use DSA or EDSA tagging depending
2711          * on which tagging mode was configured.
2712          *
2713          * If this is a link to another switch, use DSA tagging mode.
2714          *
2715          * If this is the upstream port for this switch, enable
2716          * forwarding of unknown unicasts and multicasts.
2717          */
2718         reg = 0;
2719         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2720             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2721             mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2722             mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps))
2723                 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2724                 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2725                 PORT_CONTROL_STATE_FORWARDING;
2726         if (dsa_is_cpu_port(ds, port)) {
2727                 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2728                         reg |= PORT_CONTROL_DSA_TAG;
2729                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2730                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2731                     mv88e6xxx_6320_family(ps)) {
2732                         reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2733                                 PORT_CONTROL_FORWARD_UNKNOWN |
2734                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2735                 }
2736
2737                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2738                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2739                     mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) ||
2740                     mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) {
2741                         reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2742                 }
2743         }
2744         if (dsa_is_dsa_port(ds, port)) {
2745                 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps))
2746                         reg |= PORT_CONTROL_DSA_TAG;
2747                 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2748                     mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2749                     mv88e6xxx_6320_family(ps)) {
2750                         reg |= PORT_CONTROL_FRAME_MODE_DSA;
2751                 }
2752
2753                 if (port == dsa_upstream_port(ds))
2754                         reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2755                                 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2756         }
2757         if (reg) {
2758                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2759                                            PORT_CONTROL, reg);
2760                 if (ret)
2761                         return ret;
2762         }
2763
2764         /* If this port is connected to a SerDes, make sure the SerDes is not
2765          * powered down.
2766          */
2767         if (mv88e6xxx_6352_family(ps)) {
2768                 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS);
2769                 if (ret < 0)
2770                         return ret;
2771                 ret &= PORT_STATUS_CMODE_MASK;
2772                 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2773                     (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2774                     (ret == PORT_STATUS_CMODE_SGMII)) {
2775                         ret = mv88e6xxx_power_on_serdes(ps);
2776                         if (ret < 0)
2777                                 return ret;
2778                 }
2779         }
2780
2781         /* Port Control 2: don't force a good FCS, set the maximum frame size to
2782          * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2783          * untagged frames on this port, do a destination address lookup on all
2784          * received packets as usual, disable ARP mirroring and don't send a
2785          * copy of all transmitted/received frames on this port to the CPU.
2786          */
2787         reg = 0;
2788         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2789             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2790             mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) ||
2791             mv88e6xxx_6185_family(ps))
2792                 reg = PORT_CONTROL_2_MAP_DA;
2793
2794         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2795             mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps))
2796                 reg |= PORT_CONTROL_2_JUMBO_10240;
2797
2798         if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) {
2799                 /* Set the upstream port this port should use */
2800                 reg |= dsa_upstream_port(ds);
2801                 /* enable forwarding of unknown multicast addresses to
2802                  * the upstream port
2803                  */
2804                 if (port == dsa_upstream_port(ds))
2805                         reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2806         }
2807
2808         reg |= PORT_CONTROL_2_8021Q_DISABLED;
2809
2810         if (reg) {
2811                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2812                                            PORT_CONTROL_2, reg);
2813                 if (ret)
2814                         return ret;
2815         }
2816
2817         /* Port Association Vector: when learning source addresses
2818          * of packets, add the address to the address database using
2819          * a port bitmap that has only the bit for this port set and
2820          * the other bits clear.
2821          */
2822         reg = 1 << port;
2823         /* Disable learning for CPU port */
2824         if (dsa_is_cpu_port(ds, port))
2825                 reg = 0;
2826
2827         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2828         if (ret)
2829                 return ret;
2830
2831         /* Egress rate control 2: disable egress rate control. */
2832         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2,
2833                                    0x0000);
2834         if (ret)
2835                 return ret;
2836
2837         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2838             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2839             mv88e6xxx_6320_family(ps)) {
2840                 /* Do not limit the period of time that this port can
2841                  * be paused for by the remote end or the period of
2842                  * time that this port can pause the remote end.
2843                  */
2844                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2845                                            PORT_PAUSE_CTRL, 0x0000);
2846                 if (ret)
2847                         return ret;
2848
2849                 /* Port ATU control: disable limiting the number of
2850                  * address database entries that this port is allowed
2851                  * to use.
2852                  */
2853                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2854                                            PORT_ATU_CONTROL, 0x0000);
2855                 /* Priority Override: disable DA, SA and VTU priority
2856                  * override.
2857                  */
2858                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2859                                            PORT_PRI_OVERRIDE, 0x0000);
2860                 if (ret)
2861                         return ret;
2862
2863                 /* Port Ethertype: use the Ethertype DSA Ethertype
2864                  * value.
2865                  */
2866                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2867                                            PORT_ETH_TYPE, ETH_P_EDSA);
2868                 if (ret)
2869                         return ret;
2870                 /* Tag Remap: use an identity 802.1p prio -> switch
2871                  * prio mapping.
2872                  */
2873                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2874                                            PORT_TAG_REGMAP_0123, 0x3210);
2875                 if (ret)
2876                         return ret;
2877
2878                 /* Tag Remap 2: use an identity 802.1p prio -> switch
2879                  * prio mapping.
2880                  */
2881                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2882                                            PORT_TAG_REGMAP_4567, 0x7654);
2883                 if (ret)
2884                         return ret;
2885         }
2886
2887         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
2888             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
2889             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
2890             mv88e6xxx_6320_family(ps)) {
2891                 /* Rate Control: disable ingress rate limiting. */
2892                 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port),
2893                                            PORT_RATE_CONTROL, 0x0001);
2894                 if (ret)
2895                         return ret;
2896         }
2897
2898         /* Port Control 1: disable trunking, disable sending
2899          * learning messages to this port.
2900          */
2901         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2902         if (ret)
2903                 return ret;
2904
2905         /* Port based VLAN map: give each port the same default address
2906          * database, and allow bidirectional communication between the
2907          * CPU and DSA port(s), and the other ports.
2908          */
2909         ret = _mv88e6xxx_port_fid_set(ps, port, 0);
2910         if (ret)
2911                 return ret;
2912
2913         ret = _mv88e6xxx_port_based_vlan_map(ps, port);
2914         if (ret)
2915                 return ret;
2916
2917         /* Default VLAN ID and priority: don't set a default VLAN
2918          * ID, and set the default packet priority to zero.
2919          */
2920         ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN,
2921                                    0x0000);
2922         if (ret)
2923                 return ret;
2924
2925         return 0;
2926 }
2927
2928 static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
2929 {
2930         struct dsa_switch *ds = ps->ds;
2931         u32 upstream_port = dsa_upstream_port(ds);
2932         u16 reg;
2933         int err;
2934         int i;
2935
2936         /* Enable the PHY Polling Unit if present, don't discard any packets,
2937          * and mask all interrupt sources.
2938          */
2939         reg = 0;
2940         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) ||
2941             mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE))
2942                 reg |= GLOBAL_CONTROL_PPU_ENABLE;
2943
2944         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg);
2945         if (err)
2946                 return err;
2947
2948         /* Configure the upstream port, and configure it as the port to which
2949          * ingress and egress and ARP monitor frames are to be sent.
2950          */
2951         reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
2952                 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
2953                 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
2954         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg);
2955         if (err)
2956                 return err;
2957
2958         /* Disable remote management, and set the switch's DSA device number. */
2959         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2,
2960                                    GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
2961                                    (ds->index & 0x1f));
2962         if (err)
2963                 return err;
2964
2965         /* Set the default address aging time to 5 minutes, and
2966          * enable address learn messages to be sent to all message
2967          * ports.
2968          */
2969         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2970                                    0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2971         if (err)
2972                 return err;
2973
2974         /* Configure the IP ToS mapping registers. */
2975         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2976         if (err)
2977                 return err;
2978         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2979         if (err)
2980                 return err;
2981         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2982         if (err)
2983                 return err;
2984         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2985         if (err)
2986                 return err;
2987         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2988         if (err)
2989                 return err;
2990         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2991         if (err)
2992                 return err;
2993         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2994         if (err)
2995                 return err;
2996         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2997         if (err)
2998                 return err;
2999
3000         /* Configure the IEEE 802.1p priority mapping register. */
3001         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
3002         if (err)
3003                 return err;
3004
3005         /* Send all frames with destination addresses matching
3006          * 01:80:c2:00:00:0x to the CPU port.
3007          */
3008         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
3009         if (err)
3010                 return err;
3011
3012         /* Ignore removed tag data on doubly tagged packets, disable
3013          * flow control messages, force flow control priority to the
3014          * highest, and send all special multicast frames to the CPU
3015          * port at the highest priority.
3016          */
3017         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
3018                                    0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3019                                    GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3020         if (err)
3021                 return err;
3022
3023         /* Program the DSA routing table. */
3024         for (i = 0; i < 32; i++) {
3025                 int nexthop = 0x1f;
3026
3027                 if (i != ds->index && i < DSA_MAX_SWITCHES)
3028                         nexthop = ds->rtable[i] & 0x1f;
3029
3030                 err = _mv88e6xxx_reg_write(
3031                         ps, REG_GLOBAL2,
3032                         GLOBAL2_DEVICE_MAPPING,
3033                         GLOBAL2_DEVICE_MAPPING_UPDATE |
3034                         (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
3035                 if (err)
3036                         return err;
3037         }
3038
3039         /* Clear all trunk masks. */
3040         for (i = 0; i < 8; i++) {
3041                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
3042                                            0x8000 |
3043                                            (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
3044                                            ((1 << ps->info->num_ports) - 1));
3045                 if (err)
3046                         return err;
3047         }
3048
3049         /* Clear all trunk mappings. */
3050         for (i = 0; i < 16; i++) {
3051                 err = _mv88e6xxx_reg_write(
3052                         ps, REG_GLOBAL2,
3053                         GLOBAL2_TRUNK_MAPPING,
3054                         GLOBAL2_TRUNK_MAPPING_UPDATE |
3055                         (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
3056                 if (err)
3057                         return err;
3058         }
3059
3060         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3061             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3062             mv88e6xxx_6320_family(ps)) {
3063                 /* Send all frames with destination addresses matching
3064                  * 01:80:c2:00:00:2x to the CPU port.
3065                  */
3066                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3067                                            GLOBAL2_MGMT_EN_2X, 0xffff);
3068                 if (err)
3069                         return err;
3070
3071                 /* Initialise cross-chip port VLAN table to reset
3072                  * defaults.
3073                  */
3074                 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3075                                            GLOBAL2_PVT_ADDR, 0x9000);
3076                 if (err)
3077                         return err;
3078
3079                 /* Clear the priority override table. */
3080                 for (i = 0; i < 16; i++) {
3081                         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3082                                                    GLOBAL2_PRIO_OVERRIDE,
3083                                                    0x8000 | (i << 8));
3084                         if (err)
3085                                 return err;
3086                 }
3087         }
3088
3089         if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) ||
3090             mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) ||
3091             mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) ||
3092             mv88e6xxx_6320_family(ps)) {
3093                 /* Disable ingress rate limiting by resetting all
3094                  * ingress rate limit registers to their initial
3095                  * state.
3096                  */
3097                 for (i = 0; i < ps->info->num_ports; i++) {
3098                         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2,
3099                                                    GLOBAL2_INGRESS_OP,
3100                                                    0x9000 | (i << 8));
3101                         if (err)
3102                                 return err;
3103                 }
3104         }
3105
3106         /* Clear the statistics counters for all ports */
3107         err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP,
3108                                    GLOBAL_STATS_OP_FLUSH_ALL);
3109         if (err)
3110                 return err;
3111
3112         /* Wait for the flush to complete. */
3113         err = _mv88e6xxx_stats_wait(ps);
3114         if (err)
3115                 return err;
3116
3117         /* Clear all ATU entries */
3118         err = _mv88e6xxx_atu_flush(ps, 0, true);
3119         if (err)
3120                 return err;
3121
3122         /* Clear all the VTU and STU entries */
3123         err = _mv88e6xxx_vtu_stu_flush(ps);
3124         if (err < 0)
3125                 return err;
3126
3127         return err;
3128 }
3129
3130 static int mv88e6xxx_setup(struct dsa_switch *ds)
3131 {
3132         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3133         int err;
3134         int i;
3135
3136         ps->ds = ds;
3137         ds->slave_mii_bus = ps->mdio_bus;
3138
3139         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM))
3140                 mutex_init(&ps->eeprom_mutex);
3141
3142         mutex_lock(&ps->reg_lock);
3143
3144         err = mv88e6xxx_switch_reset(ps);
3145         if (err)
3146                 goto unlock;
3147
3148         err = mv88e6xxx_setup_global(ps);
3149         if (err)
3150                 goto unlock;
3151
3152         for (i = 0; i < ps->info->num_ports; i++) {
3153                 err = mv88e6xxx_setup_port(ps, i);
3154                 if (err)
3155                         goto unlock;
3156         }
3157
3158 unlock:
3159         mutex_unlock(&ps->reg_lock);
3160
3161         return err;
3162 }
3163
3164 static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3165                                     int reg)
3166 {
3167         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3168         int ret;
3169
3170         mutex_lock(&ps->reg_lock);
3171         ret = _mv88e6xxx_mdio_page_read(ps, port, page, reg);
3172         mutex_unlock(&ps->reg_lock);
3173
3174         return ret;
3175 }
3176
3177 static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3178                                      int reg, int val)
3179 {
3180         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3181         int ret;
3182
3183         mutex_lock(&ps->reg_lock);
3184         ret = _mv88e6xxx_mdio_page_write(ps, port, page, reg, val);
3185         mutex_unlock(&ps->reg_lock);
3186
3187         return ret;
3188 }
3189
3190 static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_priv_state *ps,
3191                                        int port)
3192 {
3193         if (port >= 0 && port < ps->info->num_ports)
3194                 return port;
3195         return -EINVAL;
3196 }
3197
3198 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3199 {
3200         struct mv88e6xxx_priv_state *ps = bus->priv;
3201         int addr = mv88e6xxx_port_to_mdio_addr(ps, port);
3202         int ret;
3203
3204         if (addr < 0)
3205                 return 0xffff;
3206
3207         mutex_lock(&ps->reg_lock);
3208
3209         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3210                 ret = mv88e6xxx_mdio_read_ppu(ps, addr, regnum);
3211         else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3212                 ret = mv88e6xxx_mdio_read_indirect(ps, addr, regnum);
3213         else
3214                 ret = mv88e6xxx_mdio_read_direct(ps, addr, regnum);
3215
3216         mutex_unlock(&ps->reg_lock);
3217         return ret;
3218 }
3219
3220 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3221                                 u16 val)
3222 {
3223         struct mv88e6xxx_priv_state *ps = bus->priv;
3224         int addr = mv88e6xxx_port_to_mdio_addr(ps, port);
3225         int ret;
3226
3227         if (addr < 0)
3228                 return 0xffff;
3229
3230         mutex_lock(&ps->reg_lock);
3231
3232         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3233                 ret = mv88e6xxx_mdio_write_ppu(ps, addr, regnum, val);
3234         else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY))
3235                 ret = mv88e6xxx_mdio_write_indirect(ps, addr, regnum, val);
3236         else
3237                 ret = mv88e6xxx_mdio_write_direct(ps, addr, regnum, val);
3238
3239         mutex_unlock(&ps->reg_lock);
3240         return ret;
3241 }
3242
3243 static int mv88e6xxx_mdio_register(struct mv88e6xxx_priv_state *ps,
3244                                    struct device_node *np)
3245 {
3246         static int index;
3247         struct mii_bus *bus;
3248         int err;
3249
3250         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU))
3251                 mv88e6xxx_ppu_state_init(ps);
3252
3253         if (np)
3254                 ps->mdio_np = of_get_child_by_name(np, "mdio");
3255
3256         bus = devm_mdiobus_alloc(ps->dev);
3257         if (!bus)
3258                 return -ENOMEM;
3259
3260         bus->priv = (void *)ps;
3261         if (np) {
3262                 bus->name = np->full_name;
3263                 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
3264         } else {
3265                 bus->name = "mv88e6xxx SMI";
3266                 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
3267         }
3268
3269         bus->read = mv88e6xxx_mdio_read;
3270         bus->write = mv88e6xxx_mdio_write;
3271         bus->parent = ps->dev;
3272
3273         if (ps->mdio_np)
3274                 err = of_mdiobus_register(bus, ps->mdio_np);
3275         else
3276                 err = mdiobus_register(bus);
3277         if (err) {
3278                 dev_err(ps->dev, "Cannot register MDIO bus (%d)\n", err);
3279                 goto out;
3280         }
3281         ps->mdio_bus = bus;
3282
3283         return 0;
3284
3285 out:
3286         if (ps->mdio_np)
3287                 of_node_put(ps->mdio_np);
3288
3289         return err;
3290 }
3291
3292 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_priv_state *ps)
3293
3294 {
3295         struct mii_bus *bus = ps->mdio_bus;
3296
3297         mdiobus_unregister(bus);
3298
3299         if (ps->mdio_np)
3300                 of_node_put(ps->mdio_np);
3301 }
3302
3303 #ifdef CONFIG_NET_DSA_HWMON
3304
3305 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3306 {
3307         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3308         int ret;
3309         int val;
3310
3311         *temp = 0;
3312
3313         mutex_lock(&ps->reg_lock);
3314
3315         ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x6);
3316         if (ret < 0)
3317                 goto error;
3318
3319         /* Enable temperature sensor */
3320         ret = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a);
3321         if (ret < 0)
3322                 goto error;
3323
3324         ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret | (1 << 5));
3325         if (ret < 0)
3326                 goto error;
3327
3328         /* Wait for temperature to stabilize */
3329         usleep_range(10000, 12000);
3330
3331         val = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a);
3332         if (val < 0) {
3333                 ret = val;
3334                 goto error;
3335         }
3336
3337         /* Disable temperature sensor */
3338         ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret & ~(1 << 5));
3339         if (ret < 0)
3340                 goto error;
3341
3342         *temp = ((val & 0x1f) - 5) * 5;
3343
3344 error:
3345         mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x0);
3346         mutex_unlock(&ps->reg_lock);
3347         return ret;
3348 }
3349
3350 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3351 {
3352         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3353         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3354         int ret;
3355
3356         *temp = 0;
3357
3358         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 27);
3359         if (ret < 0)
3360                 return ret;
3361
3362         *temp = (ret & 0xff) - 25;
3363
3364         return 0;
3365 }
3366
3367 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3368 {
3369         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3370
3371         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP))
3372                 return -EOPNOTSUPP;
3373
3374         if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps))
3375                 return mv88e63xx_get_temp(ds, temp);
3376
3377         return mv88e61xx_get_temp(ds, temp);
3378 }
3379
3380 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3381 {
3382         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3383         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3384         int ret;
3385
3386         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3387                 return -EOPNOTSUPP;
3388
3389         *temp = 0;
3390
3391         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3392         if (ret < 0)
3393                 return ret;
3394
3395         *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3396
3397         return 0;
3398 }
3399
3400 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3401 {
3402         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3403         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3404         int ret;
3405
3406         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3407                 return -EOPNOTSUPP;
3408
3409         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3410         if (ret < 0)
3411                 return ret;
3412         temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3413         return mv88e6xxx_mdio_page_write(ds, phy, 6, 26,
3414                                          (ret & 0xe0ff) | (temp << 8));
3415 }
3416
3417 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3418 {
3419         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3420         int phy = mv88e6xxx_6320_family(ps) ? 3 : 0;
3421         int ret;
3422
3423         if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT))
3424                 return -EOPNOTSUPP;
3425
3426         *alarm = false;
3427
3428         ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
3429         if (ret < 0)
3430                 return ret;
3431
3432         *alarm = !!(ret & 0x40);
3433
3434         return 0;
3435 }
3436 #endif /* CONFIG_NET_DSA_HWMON */
3437
3438 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3439         [MV88E6085] = {
3440                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
3441                 .family = MV88E6XXX_FAMILY_6097,
3442                 .name = "Marvell 88E6085",
3443                 .num_databases = 4096,
3444                 .num_ports = 10,
3445                 .flags = MV88E6XXX_FLAGS_FAMILY_6097,
3446         },
3447
3448         [MV88E6095] = {
3449                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095,
3450                 .family = MV88E6XXX_FAMILY_6095,
3451                 .name = "Marvell 88E6095/88E6095F",
3452                 .num_databases = 256,
3453                 .num_ports = 11,
3454                 .flags = MV88E6XXX_FLAGS_FAMILY_6095,
3455         },
3456
3457         [MV88E6123] = {
3458                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123,
3459                 .family = MV88E6XXX_FAMILY_6165,
3460                 .name = "Marvell 88E6123",
3461                 .num_databases = 4096,
3462                 .num_ports = 3,
3463                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3464         },
3465
3466         [MV88E6131] = {
3467                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131,
3468                 .family = MV88E6XXX_FAMILY_6185,
3469                 .name = "Marvell 88E6131",
3470                 .num_databases = 256,
3471                 .num_ports = 8,
3472                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3473         },
3474
3475         [MV88E6161] = {
3476                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
3477                 .family = MV88E6XXX_FAMILY_6165,
3478                 .name = "Marvell 88E6161",
3479                 .num_databases = 4096,
3480                 .num_ports = 6,
3481                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3482         },
3483
3484         [MV88E6165] = {
3485                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165,
3486                 .family = MV88E6XXX_FAMILY_6165,
3487                 .name = "Marvell 88E6165",
3488                 .num_databases = 4096,
3489                 .num_ports = 6,
3490                 .flags = MV88E6XXX_FLAGS_FAMILY_6165,
3491         },
3492
3493         [MV88E6171] = {
3494                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171,
3495                 .family = MV88E6XXX_FAMILY_6351,
3496                 .name = "Marvell 88E6171",
3497                 .num_databases = 4096,
3498                 .num_ports = 7,
3499                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3500         },
3501
3502         [MV88E6172] = {
3503                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172,
3504                 .family = MV88E6XXX_FAMILY_6352,
3505                 .name = "Marvell 88E6172",
3506                 .num_databases = 4096,
3507                 .num_ports = 7,
3508                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3509         },
3510
3511         [MV88E6175] = {
3512                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175,
3513                 .family = MV88E6XXX_FAMILY_6351,
3514                 .name = "Marvell 88E6175",
3515                 .num_databases = 4096,
3516                 .num_ports = 7,
3517                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3518         },
3519
3520         [MV88E6176] = {
3521                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176,
3522                 .family = MV88E6XXX_FAMILY_6352,
3523                 .name = "Marvell 88E6176",
3524                 .num_databases = 4096,
3525                 .num_ports = 7,
3526                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3527         },
3528
3529         [MV88E6185] = {
3530                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185,
3531                 .family = MV88E6XXX_FAMILY_6185,
3532                 .name = "Marvell 88E6185",
3533                 .num_databases = 256,
3534                 .num_ports = 10,
3535                 .flags = MV88E6XXX_FLAGS_FAMILY_6185,
3536         },
3537
3538         [MV88E6240] = {
3539                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240,
3540                 .family = MV88E6XXX_FAMILY_6352,
3541                 .name = "Marvell 88E6240",
3542                 .num_databases = 4096,
3543                 .num_ports = 7,
3544                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3545         },
3546
3547         [MV88E6320] = {
3548                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320,
3549                 .family = MV88E6XXX_FAMILY_6320,
3550                 .name = "Marvell 88E6320",
3551                 .num_databases = 4096,
3552                 .num_ports = 7,
3553                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3554         },
3555
3556         [MV88E6321] = {
3557                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321,
3558                 .family = MV88E6XXX_FAMILY_6320,
3559                 .name = "Marvell 88E6321",
3560                 .num_databases = 4096,
3561                 .num_ports = 7,
3562                 .flags = MV88E6XXX_FLAGS_FAMILY_6320,
3563         },
3564
3565         [MV88E6350] = {
3566                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
3567                 .family = MV88E6XXX_FAMILY_6351,
3568                 .name = "Marvell 88E6350",
3569                 .num_databases = 4096,
3570                 .num_ports = 7,
3571                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3572         },
3573
3574         [MV88E6351] = {
3575                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351,
3576                 .family = MV88E6XXX_FAMILY_6351,
3577                 .name = "Marvell 88E6351",
3578                 .num_databases = 4096,
3579                 .num_ports = 7,
3580                 .flags = MV88E6XXX_FLAGS_FAMILY_6351,
3581         },
3582
3583         [MV88E6352] = {
3584                 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352,
3585                 .family = MV88E6XXX_FAMILY_6352,
3586                 .name = "Marvell 88E6352",
3587                 .num_databases = 4096,
3588                 .num_ports = 7,
3589                 .flags = MV88E6XXX_FLAGS_FAMILY_6352,
3590         },
3591 };
3592
3593 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3594 {
3595         int i;
3596
3597         for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
3598                 if (mv88e6xxx_table[i].prod_num == prod_num)
3599                         return &mv88e6xxx_table[i];
3600
3601         return NULL;
3602 }
3603
3604 static struct mv88e6xxx_priv_state *mv88e6xxx_alloc_chip(struct device *dev)
3605 {
3606         struct mv88e6xxx_priv_state *ps;
3607
3608         ps = devm_kzalloc(dev, sizeof(*ps), GFP_KERNEL);
3609         if (!ps)
3610                 return NULL;
3611
3612         ps->dev = dev;
3613
3614         mutex_init(&ps->reg_lock);
3615
3616         return ps;
3617 }
3618
3619 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3620                                        struct device *host_dev, int sw_addr,
3621                                        void **priv)
3622 {
3623         const struct mv88e6xxx_info *info;
3624         struct mv88e6xxx_priv_state *ps;
3625         struct mii_bus *bus;
3626         const char *name;
3627         int id, prod_num, rev;
3628         int err;
3629
3630         bus = dsa_host_dev_to_mii_bus(host_dev);
3631         if (!bus)
3632                 return NULL;
3633
3634         ps = mv88e6xxx_alloc_chip(dsa_dev);
3635         if (!ps)
3636                 return NULL;
3637
3638         id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3639         if (id < 0)
3640                 goto free;
3641
3642         prod_num = (id & 0xfff0) >> 4;
3643         rev = id & 0x000f;
3644
3645         info = mv88e6xxx_lookup_info(prod_num);
3646         if (!info)
3647                 goto free;
3648
3649         name = info->name;
3650
3651         ps->bus = bus;
3652         ps->sw_addr = sw_addr;
3653         ps->info = info;
3654
3655         err = mv88e6xxx_mdio_register(ps, NULL);
3656         if (err)
3657                 goto free;
3658
3659         *priv = ps;
3660
3661         dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3662                  prod_num, name, rev);
3663
3664         return name;
3665 free:
3666         devm_kfree(dsa_dev, ps);
3667
3668         return NULL;
3669 }
3670
3671 static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3672         .tag_protocol           = DSA_TAG_PROTO_EDSA,
3673         .probe                  = mv88e6xxx_drv_probe,
3674         .setup                  = mv88e6xxx_setup,
3675         .set_addr               = mv88e6xxx_set_addr,
3676         .adjust_link            = mv88e6xxx_adjust_link,
3677         .get_strings            = mv88e6xxx_get_strings,
3678         .get_ethtool_stats      = mv88e6xxx_get_ethtool_stats,
3679         .get_sset_count         = mv88e6xxx_get_sset_count,
3680         .set_eee                = mv88e6xxx_set_eee,
3681         .get_eee                = mv88e6xxx_get_eee,
3682 #ifdef CONFIG_NET_DSA_HWMON
3683         .get_temp               = mv88e6xxx_get_temp,
3684         .get_temp_limit         = mv88e6xxx_get_temp_limit,
3685         .set_temp_limit         = mv88e6xxx_set_temp_limit,
3686         .get_temp_alarm         = mv88e6xxx_get_temp_alarm,
3687 #endif
3688         .get_eeprom_len         = mv88e6xxx_get_eeprom_len,
3689         .get_eeprom             = mv88e6xxx_get_eeprom,
3690         .set_eeprom             = mv88e6xxx_set_eeprom,
3691         .get_regs_len           = mv88e6xxx_get_regs_len,
3692         .get_regs               = mv88e6xxx_get_regs,
3693         .port_bridge_join       = mv88e6xxx_port_bridge_join,
3694         .port_bridge_leave      = mv88e6xxx_port_bridge_leave,
3695         .port_stp_state_set     = mv88e6xxx_port_stp_state_set,
3696         .port_vlan_filtering    = mv88e6xxx_port_vlan_filtering,
3697         .port_vlan_prepare      = mv88e6xxx_port_vlan_prepare,
3698         .port_vlan_add          = mv88e6xxx_port_vlan_add,
3699         .port_vlan_del          = mv88e6xxx_port_vlan_del,
3700         .port_vlan_dump         = mv88e6xxx_port_vlan_dump,
3701         .port_fdb_prepare       = mv88e6xxx_port_fdb_prepare,
3702         .port_fdb_add           = mv88e6xxx_port_fdb_add,
3703         .port_fdb_del           = mv88e6xxx_port_fdb_del,
3704         .port_fdb_dump          = mv88e6xxx_port_fdb_dump,
3705 };
3706
3707 static int mv88e6xxx_register_switch(struct mv88e6xxx_priv_state *ps,
3708                                      struct device_node *np)
3709 {
3710         struct device *dev = ps->dev;
3711         struct dsa_switch *ds;
3712
3713         ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
3714         if (!ds)
3715                 return -ENOMEM;
3716
3717         ds->dev = dev;
3718         ds->priv = ps;
3719         ds->drv = &mv88e6xxx_switch_driver;
3720
3721         dev_set_drvdata(dev, ds);
3722
3723         return dsa_register_switch(ds, np);
3724 }
3725
3726 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_priv_state *ps)
3727 {
3728         dsa_unregister_switch(ps->ds);
3729 }
3730
3731 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3732 {
3733         struct device *dev = &mdiodev->dev;
3734         struct device_node *np = dev->of_node;
3735         struct mv88e6xxx_priv_state *ps;
3736         int id, prod_num, rev;
3737         u32 eeprom_len;
3738         int err;
3739
3740         ps = mv88e6xxx_alloc_chip(dev);
3741         if (!ps)
3742                 return -ENOMEM;
3743
3744         ps->bus = mdiodev->bus;
3745         ps->sw_addr = mdiodev->addr;
3746
3747         id = mv88e6xxx_reg_read(ps, REG_PORT(0), PORT_SWITCH_ID);
3748         if (id < 0)
3749                 return id;
3750
3751         prod_num = (id & 0xfff0) >> 4;
3752         rev = id & 0x000f;
3753
3754         ps->info = mv88e6xxx_lookup_info(prod_num);
3755         if (!ps->info)
3756                 return -ENODEV;
3757
3758         ps->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3759         if (IS_ERR(ps->reset))
3760                 return PTR_ERR(ps->reset);
3761
3762         if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) &&
3763             !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3764                 ps->eeprom_len = eeprom_len;
3765
3766         err = mv88e6xxx_mdio_register(ps, np);
3767         if (err)
3768                 return err;
3769
3770         err = mv88e6xxx_register_switch(ps, np);
3771         if (err) {
3772                 mv88e6xxx_mdio_unregister(ps);
3773                 return err;
3774         }
3775
3776         dev_info(dev, "switch 0x%x probed: %s, revision %u\n",
3777                  prod_num, ps->info->name, rev);
3778
3779         return 0;
3780 }
3781
3782 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3783 {
3784         struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3785         struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
3786
3787         mv88e6xxx_unregister_switch(ps);
3788         mv88e6xxx_mdio_unregister(ps);
3789 }
3790
3791 static const struct of_device_id mv88e6xxx_of_match[] = {
3792         { .compatible = "marvell,mv88e6085" },
3793         { /* sentinel */ },
3794 };
3795
3796 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
3797
3798 static struct mdio_driver mv88e6xxx_driver = {
3799         .probe  = mv88e6xxx_probe,
3800         .remove = mv88e6xxx_remove,
3801         .mdiodrv.driver = {
3802                 .name = "mv88e6085",
3803                 .of_match_table = mv88e6xxx_of_match,
3804         },
3805 };
3806
3807 static int __init mv88e6xxx_init(void)
3808 {
3809         register_switch_driver(&mv88e6xxx_switch_driver);
3810         return mdio_driver_register(&mv88e6xxx_driver);
3811 }
3812 module_init(mv88e6xxx_init);
3813
3814 static void __exit mv88e6xxx_cleanup(void)
3815 {
3816         mdio_driver_unregister(&mv88e6xxx_driver);
3817         unregister_switch_driver(&mv88e6xxx_switch_driver);
3818 }
3819 module_exit(mv88e6xxx_cleanup);
3820
3821 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3822 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3823 MODULE_LICENSE("GPL");