2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
133 return mdiobus_write_nested(bus, addr, reg, val);
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
201 for (i = 0; i < 6; i++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
240 unsigned long timeout;
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
261 unsigned long timeout;
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
280 struct mv88e6xxx_priv_state *ps;
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
296 schedule_work(&ps->ppu_work);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
304 mutex_lock(&ps->ppu_mutex);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
314 mutex_unlock(&ps->ppu_mutex);
317 ps->ppu_disabled = 1;
319 del_timer(&ps->ppu_timer);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
350 ret = mv88e6xxx_ppu_access_get(ds);
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
364 ret = mv88e6xxx_ppu_access_get(ds);
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
485 /* We expect the switch to perform auto negotiation if there is a real
486 * phy. However, in the case of a fixed link phy, we force the port
487 * settings from the fixed link settings.
489 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
490 struct phy_device *phydev)
492 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
496 if (!phy_is_pseudo_fixed_link(phydev))
499 mutex_lock(&ps->smi_mutex);
501 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
505 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
506 PORT_PCS_CTRL_FORCE_LINK |
507 PORT_PCS_CTRL_DUPLEX_FULL |
508 PORT_PCS_CTRL_FORCE_DUPLEX |
509 PORT_PCS_CTRL_UNFORCED);
511 reg |= PORT_PCS_CTRL_FORCE_LINK;
513 reg |= PORT_PCS_CTRL_LINK_UP;
515 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
518 switch (phydev->speed) {
520 reg |= PORT_PCS_CTRL_1000;
523 reg |= PORT_PCS_CTRL_100;
526 reg |= PORT_PCS_CTRL_10;
529 pr_info("Unknown speed");
533 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
534 if (phydev->duplex == DUPLEX_FULL)
535 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
537 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
538 (port >= ps->num_ports - 2)) {
539 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
540 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
541 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
542 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
543 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
544 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
545 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
547 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
550 mutex_unlock(&ps->smi_mutex);
553 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
558 for (i = 0; i < 10; i++) {
559 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
560 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
567 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
571 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
572 port = (port + 1) << 5;
574 /* Snapshot the hardware statistics counters for this port. */
575 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
576 GLOBAL_STATS_OP_CAPTURE_PORT |
577 GLOBAL_STATS_OP_HIST_RX_TX | port);
581 /* Wait for the snapshotting to complete. */
582 ret = _mv88e6xxx_stats_wait(ds);
589 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
596 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
597 GLOBAL_STATS_OP_READ_CAPTURED |
598 GLOBAL_STATS_OP_HIST_RX_TX | stat);
602 ret = _mv88e6xxx_stats_wait(ds);
606 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
612 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
619 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
620 { "in_good_octets", 8, 0x00, BANK0, },
621 { "in_bad_octets", 4, 0x02, BANK0, },
622 { "in_unicast", 4, 0x04, BANK0, },
623 { "in_broadcasts", 4, 0x06, BANK0, },
624 { "in_multicasts", 4, 0x07, BANK0, },
625 { "in_pause", 4, 0x16, BANK0, },
626 { "in_undersize", 4, 0x18, BANK0, },
627 { "in_fragments", 4, 0x19, BANK0, },
628 { "in_oversize", 4, 0x1a, BANK0, },
629 { "in_jabber", 4, 0x1b, BANK0, },
630 { "in_rx_error", 4, 0x1c, BANK0, },
631 { "in_fcs_error", 4, 0x1d, BANK0, },
632 { "out_octets", 8, 0x0e, BANK0, },
633 { "out_unicast", 4, 0x10, BANK0, },
634 { "out_broadcasts", 4, 0x13, BANK0, },
635 { "out_multicasts", 4, 0x12, BANK0, },
636 { "out_pause", 4, 0x15, BANK0, },
637 { "excessive", 4, 0x11, BANK0, },
638 { "collisions", 4, 0x1e, BANK0, },
639 { "deferred", 4, 0x05, BANK0, },
640 { "single", 4, 0x14, BANK0, },
641 { "multiple", 4, 0x17, BANK0, },
642 { "out_fcs_error", 4, 0x03, BANK0, },
643 { "late", 4, 0x1f, BANK0, },
644 { "hist_64bytes", 4, 0x08, BANK0, },
645 { "hist_65_127bytes", 4, 0x09, BANK0, },
646 { "hist_128_255bytes", 4, 0x0a, BANK0, },
647 { "hist_256_511bytes", 4, 0x0b, BANK0, },
648 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
649 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
650 { "sw_in_discards", 4, 0x10, PORT, },
651 { "sw_in_filtered", 2, 0x12, PORT, },
652 { "sw_out_filtered", 2, 0x13, PORT, },
653 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
678 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
681 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
682 struct mv88e6xxx_hw_stat *stat)
684 switch (stat->type) {
688 return mv88e6xxx_6320_family(ds);
690 return mv88e6xxx_6095_family(ds) ||
691 mv88e6xxx_6185_family(ds) ||
692 mv88e6xxx_6097_family(ds) ||
693 mv88e6xxx_6165_family(ds) ||
694 mv88e6xxx_6351_family(ds) ||
695 mv88e6xxx_6352_family(ds);
700 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
701 struct mv88e6xxx_hw_stat *s,
711 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
716 if (s->sizeof_stat == 4) {
717 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
726 _mv88e6xxx_stats_read(ds, s->reg, &low);
727 if (s->sizeof_stat == 8)
728 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
730 value = (((u64)high) << 16) | low;
734 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
736 struct mv88e6xxx_hw_stat *stat;
739 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
740 stat = &mv88e6xxx_hw_stats[i];
741 if (mv88e6xxx_has_stat(ds, stat)) {
742 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
749 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
751 struct mv88e6xxx_hw_stat *stat;
754 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
755 stat = &mv88e6xxx_hw_stats[i];
756 if (mv88e6xxx_has_stat(ds, stat))
763 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
764 int port, uint64_t *data)
766 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
767 struct mv88e6xxx_hw_stat *stat;
771 mutex_lock(&ps->smi_mutex);
773 ret = _mv88e6xxx_stats_snapshot(ds, port);
775 mutex_unlock(&ps->smi_mutex);
778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
779 stat = &mv88e6xxx_hw_stats[i];
780 if (mv88e6xxx_has_stat(ds, stat)) {
781 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
786 mutex_unlock(&ps->smi_mutex);
789 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
791 return 32 * sizeof(u16);
794 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
795 struct ethtool_regs *regs, void *_p)
802 memset(p, 0xff, 32 * sizeof(u16));
804 for (i = 0; i < 32; i++) {
807 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
813 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
816 unsigned long timeout = jiffies + HZ / 10;
818 while (time_before(jiffies, timeout)) {
821 ret = _mv88e6xxx_reg_read(ds, reg, offset);
827 usleep_range(1000, 2000);
832 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
834 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
837 mutex_lock(&ps->smi_mutex);
838 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
839 mutex_unlock(&ps->smi_mutex);
844 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
846 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
847 GLOBAL2_SMI_OP_BUSY);
850 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
852 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
853 GLOBAL2_EEPROM_OP_LOAD);
856 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
858 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
859 GLOBAL2_EEPROM_OP_BUSY);
862 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
864 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
868 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
873 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
874 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
879 ret = _mv88e6xxx_phy_wait(ds);
883 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
886 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
891 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
895 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
896 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
899 return _mv88e6xxx_phy_wait(ds);
902 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
904 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
907 mutex_lock(&ps->smi_mutex);
909 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
913 e->eee_enabled = !!(reg & 0x0200);
914 e->tx_lpi_enabled = !!(reg & 0x0100);
916 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
920 e->eee_active = !!(reg & PORT_STATUS_EEE);
924 mutex_unlock(&ps->smi_mutex);
928 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
929 struct phy_device *phydev, struct ethtool_eee *e)
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
935 mutex_lock(&ps->smi_mutex);
937 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
944 if (e->tx_lpi_enabled)
947 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
949 mutex_unlock(&ps->smi_mutex);
954 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 cmd)
958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
962 return _mv88e6xxx_atu_wait(ds);
965 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
966 struct mv88e6xxx_atu_entry *entry)
968 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
970 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
971 unsigned int mask, shift;
974 data |= GLOBAL_ATU_DATA_TRUNK;
975 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
976 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
978 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
979 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
982 data |= (entry->portv_trunkid << shift) & mask;
985 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
988 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
989 struct mv88e6xxx_atu_entry *entry,
995 err = _mv88e6xxx_atu_wait(ds);
999 err = _mv88e6xxx_atu_data_write(ds, entry);
1004 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID,
1009 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1010 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1012 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1013 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1016 return _mv88e6xxx_atu_cmd(ds, op);
1019 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1021 struct mv88e6xxx_atu_entry entry = {
1023 .state = 0, /* EntryState bits must be 0 */
1026 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1029 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1030 int to_port, bool static_too)
1032 struct mv88e6xxx_atu_entry entry = {
1037 /* EntryState bits must be 0xF */
1038 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1040 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1041 entry.portv_trunkid = (to_port & 0x0f) << 4;
1042 entry.portv_trunkid |= from_port & 0x0f;
1044 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1047 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1050 /* Destination port 0xF means remove the entries */
1051 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1054 static int mv88e6xxx_set_port_state(struct dsa_switch *ds, int port, u8 state)
1056 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1060 mutex_lock(&ps->smi_mutex);
1062 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1068 oldstate = reg & PORT_CONTROL_STATE_MASK;
1069 if (oldstate != state) {
1070 /* Flush forwarding database if we're moving a port
1071 * from Learning or Forwarding state to Disabled or
1072 * Blocking or Listening state.
1074 if (oldstate >= PORT_CONTROL_STATE_LEARNING &&
1075 state <= PORT_CONTROL_STATE_BLOCKING) {
1076 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1080 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1081 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1086 mutex_unlock(&ps->smi_mutex);
1090 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1092 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1093 struct net_device *bridge = ps->ports[port].bridge_dev;
1094 const u16 mask = (1 << ps->num_ports) - 1;
1095 u16 output_ports = 0;
1099 /* allow CPU port or DSA link(s) to send frames to every port */
1100 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1101 output_ports = mask;
1103 for (i = 0; i < ps->num_ports; ++i) {
1104 /* allow sending frames to every group member */
1105 if (bridge && ps->ports[i].bridge_dev == bridge)
1106 output_ports |= BIT(i);
1108 /* allow sending frames to CPU port and DSA link(s) */
1109 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1110 output_ports |= BIT(i);
1114 /* prevent frames from going back out of the port they came in on */
1115 output_ports &= ~BIT(port);
1117 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1122 reg |= output_ports & mask;
1124 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1127 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1129 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1133 case BR_STATE_DISABLED:
1134 stp_state = PORT_CONTROL_STATE_DISABLED;
1136 case BR_STATE_BLOCKING:
1137 case BR_STATE_LISTENING:
1138 stp_state = PORT_CONTROL_STATE_BLOCKING;
1140 case BR_STATE_LEARNING:
1141 stp_state = PORT_CONTROL_STATE_LEARNING;
1143 case BR_STATE_FORWARDING:
1145 stp_state = PORT_CONTROL_STATE_FORWARDING;
1149 netdev_dbg(ds->ports[port], "port state %d [%d]\n", state, stp_state);
1151 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1152 * so we can not update the port state directly but need to schedule it.
1154 ps->ports[port].state = stp_state;
1155 set_bit(port, &ps->port_state_update_mask);
1156 schedule_work(&ps->bridge_work);
1161 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1165 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1169 *pvid = ret & PORT_DEFAULT_VLAN_MASK;
1174 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1176 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
1177 pvid & PORT_DEFAULT_VLAN_MASK);
1180 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1182 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1183 GLOBAL_VTU_OP_BUSY);
1186 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1190 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1194 return _mv88e6xxx_vtu_wait(ds);
1197 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1201 ret = _mv88e6xxx_vtu_wait(ds);
1205 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1208 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1209 struct mv88e6xxx_vtu_stu_entry *entry,
1210 unsigned int nibble_offset)
1212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1217 for (i = 0; i < 3; ++i) {
1218 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1219 GLOBAL_VTU_DATA_0_3 + i);
1226 for (i = 0; i < ps->num_ports; ++i) {
1227 unsigned int shift = (i % 4) * 4 + nibble_offset;
1228 u16 reg = regs[i / 4];
1230 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1236 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1237 struct mv88e6xxx_vtu_stu_entry *entry,
1238 unsigned int nibble_offset)
1240 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1241 u16 regs[3] = { 0 };
1245 for (i = 0; i < ps->num_ports; ++i) {
1246 unsigned int shift = (i % 4) * 4 + nibble_offset;
1247 u8 data = entry->data[i];
1249 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1252 for (i = 0; i < 3; ++i) {
1253 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1254 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1262 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1264 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1265 vid & GLOBAL_VTU_VID_MASK);
1268 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1269 struct mv88e6xxx_vtu_stu_entry *entry)
1271 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1274 ret = _mv88e6xxx_vtu_wait(ds);
1278 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1282 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1286 next.vid = ret & GLOBAL_VTU_VID_MASK;
1287 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1290 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1294 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1295 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1296 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1301 next.fid = ret & GLOBAL_VTU_FID_MASK;
1303 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1308 next.sid = ret & GLOBAL_VTU_SID_MASK;
1316 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1317 struct switchdev_obj_port_vlan *vlan,
1318 int (*cb)(struct switchdev_obj *obj))
1320 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1321 struct mv88e6xxx_vtu_stu_entry next;
1325 mutex_lock(&ps->smi_mutex);
1327 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1331 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1336 err = _mv88e6xxx_vtu_getnext(ds, &next);
1343 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1346 /* reinit and dump this VLAN obj */
1347 vlan->vid_begin = vlan->vid_end = next.vid;
1350 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1351 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1353 if (next.vid == pvid)
1354 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1356 err = cb(&vlan->obj);
1359 } while (next.vid < GLOBAL_VTU_VID_MASK);
1362 mutex_unlock(&ps->smi_mutex);
1367 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1368 struct mv88e6xxx_vtu_stu_entry *entry)
1373 ret = _mv88e6xxx_vtu_wait(ds);
1380 /* Write port member tags */
1381 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1385 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1386 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1387 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1388 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1392 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1393 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1398 reg = GLOBAL_VTU_VID_VALID;
1400 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1401 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1405 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1408 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1409 struct mv88e6xxx_vtu_stu_entry *entry)
1411 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1414 ret = _mv88e6xxx_vtu_wait(ds);
1418 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1419 sid & GLOBAL_VTU_SID_MASK);
1423 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1427 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1431 next.sid = ret & GLOBAL_VTU_SID_MASK;
1433 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1437 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1440 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1449 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1450 struct mv88e6xxx_vtu_stu_entry *entry)
1455 ret = _mv88e6xxx_vtu_wait(ds);
1462 /* Write port states */
1463 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1467 reg = GLOBAL_VTU_VID_VALID;
1469 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1473 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1474 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1478 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1481 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1487 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1488 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1492 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1495 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1496 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1498 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1504 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1505 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1509 fid |= (ret & PORT_CONTROL_1_FID_11_4_MASK) << 4;
1512 ret &= ~PORT_CONTROL_1_FID_11_4_MASK;
1513 ret |= (*new >> 4) & PORT_CONTROL_1_FID_11_4_MASK;
1515 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1520 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1529 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1531 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1534 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1536 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1539 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1541 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1542 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1543 struct mv88e6xxx_vtu_stu_entry vlan;
1546 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1548 /* Set every FID bit used by the (un)bridged ports */
1549 for (i = 0; i < ps->num_ports; ++i) {
1550 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1554 set_bit(*fid, fid_bitmap);
1557 /* Set every FID bit used by the VLAN entries */
1558 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1563 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1570 set_bit(vlan.fid, fid_bitmap);
1571 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1573 /* The reset value 0x000 is used to indicate that multiple address
1574 * databases are not needed. Return the next positive available.
1576 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1577 if (unlikely(*fid == MV88E6XXX_N_FID))
1580 /* Clear the database */
1581 return _mv88e6xxx_atu_flush(ds, *fid, true);
1584 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1585 struct mv88e6xxx_vtu_stu_entry *entry)
1587 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1588 struct mv88e6xxx_vtu_stu_entry vlan = {
1594 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1598 /* exclude all ports except the CPU and DSA ports */
1599 for (i = 0; i < ps->num_ports; ++i)
1600 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1601 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1602 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1604 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1605 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1606 struct mv88e6xxx_vtu_stu_entry vstp;
1608 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1609 * implemented, only one STU entry is needed to cover all VTU
1610 * entries. Thus, validate the SID 0.
1613 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1617 if (vstp.sid != vlan.sid || !vstp.valid) {
1618 memset(&vstp, 0, sizeof(vstp));
1620 vstp.sid = vlan.sid;
1622 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1632 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1633 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1640 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1644 err = _mv88e6xxx_vtu_getnext(ds, entry);
1648 if (entry->vid != vid || !entry->valid) {
1651 /* -ENOENT would've been more appropriate, but switchdev expects
1652 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1655 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1661 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1662 u16 vid_begin, u16 vid_end)
1664 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1665 struct mv88e6xxx_vtu_stu_entry vlan;
1671 mutex_lock(&ps->smi_mutex);
1673 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1678 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1685 if (vlan.vid > vid_end)
1688 for (i = 0; i < ps->num_ports; ++i) {
1689 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1693 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1696 if (ps->ports[i].bridge_dev ==
1697 ps->ports[port].bridge_dev)
1698 break; /* same bridge, check next VLAN */
1700 netdev_warn(ds->ports[port],
1701 "hardware VLAN %d already used by %s\n",
1703 netdev_name(ps->ports[i].bridge_dev));
1707 } while (vlan.vid < vid_end);
1710 mutex_unlock(&ps->smi_mutex);
1715 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1716 const struct switchdev_obj_port_vlan *vlan,
1717 struct switchdev_trans *trans)
1721 /* If the requested port doesn't belong to the same bridge as the VLAN
1722 * members, do not support it (yet) and fallback to software VLAN.
1724 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1729 /* We don't need any dynamic resource from the kernel (yet),
1730 * so skip the prepare phase.
1735 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1738 struct mv88e6xxx_vtu_stu_entry vlan;
1741 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1745 vlan.data[port] = untagged ?
1746 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1747 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1749 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1752 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1753 const struct switchdev_obj_port_vlan *vlan,
1754 struct switchdev_trans *trans)
1756 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1757 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1758 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1762 mutex_lock(&ps->smi_mutex);
1764 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1765 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1770 /* no PVID with ranges, otherwise it's a bug */
1772 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1774 mutex_unlock(&ps->smi_mutex);
1779 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1781 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1782 struct mv88e6xxx_vtu_stu_entry vlan;
1785 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1789 /* Tell switchdev if this VLAN is handled in software */
1790 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1793 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1795 /* keep the VLAN unless all ports are excluded */
1797 for (i = 0; i < ps->num_ports; ++i) {
1798 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1801 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1807 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1811 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1814 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1815 const struct switchdev_obj_port_vlan *vlan)
1817 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1821 mutex_lock(&ps->smi_mutex);
1823 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1827 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1828 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1833 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1840 mutex_unlock(&ps->smi_mutex);
1845 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1846 const unsigned char *addr)
1850 for (i = 0; i < 3; i++) {
1851 ret = _mv88e6xxx_reg_write(
1852 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1853 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1861 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1865 for (i = 0; i < 3; i++) {
1866 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1867 GLOBAL_ATU_MAC_01 + i);
1870 addr[i * 2] = ret >> 8;
1871 addr[i * 2 + 1] = ret & 0xff;
1877 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1878 struct mv88e6xxx_atu_entry *entry)
1882 ret = _mv88e6xxx_atu_wait(ds);
1886 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
1890 ret = _mv88e6xxx_atu_data_write(ds, entry);
1894 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, entry->fid);
1898 return _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_LOAD_DB);
1901 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
1902 const unsigned char *addr, u16 vid,
1905 struct mv88e6xxx_atu_entry entry = { 0 };
1906 struct mv88e6xxx_vtu_stu_entry vlan;
1909 /* Null VLAN ID corresponds to the port private database */
1911 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
1913 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1917 entry.fid = vlan.fid;
1918 entry.state = state;
1919 ether_addr_copy(entry.mac, addr);
1920 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1921 entry.trunk = false;
1922 entry.portv_trunkid = BIT(port);
1925 return _mv88e6xxx_atu_load(ds, &entry);
1928 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
1929 const struct switchdev_obj_port_fdb *fdb,
1930 struct switchdev_trans *trans)
1932 /* We don't need any dynamic resource from the kernel (yet),
1933 * so skip the prepare phase.
1938 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1939 const struct switchdev_obj_port_fdb *fdb,
1940 struct switchdev_trans *trans)
1942 int state = is_multicast_ether_addr(fdb->addr) ?
1943 GLOBAL_ATU_DATA_STATE_MC_STATIC :
1944 GLOBAL_ATU_DATA_STATE_UC_STATIC;
1945 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1948 mutex_lock(&ps->smi_mutex);
1949 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
1950 mutex_unlock(&ps->smi_mutex);
1955 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1956 const struct switchdev_obj_port_fdb *fdb)
1958 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1961 mutex_lock(&ps->smi_mutex);
1962 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
1963 GLOBAL_ATU_DATA_STATE_UNUSED);
1964 mutex_unlock(&ps->smi_mutex);
1969 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
1970 struct mv88e6xxx_atu_entry *entry)
1972 struct mv88e6xxx_atu_entry next = { 0 };
1977 ret = _mv88e6xxx_atu_wait(ds);
1981 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1985 ret = _mv88e6xxx_atu_cmd(ds, GLOBAL_ATU_OP_GET_NEXT_DB);
1989 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
1993 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
1997 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
1998 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1999 unsigned int mask, shift;
2001 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2003 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2004 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2007 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2008 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2011 next.portv_trunkid = (ret & mask) >> shift;
2018 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2020 struct switchdev_obj_port_fdb *fdb,
2021 int (*cb)(struct switchdev_obj *obj))
2023 struct mv88e6xxx_atu_entry addr = {
2024 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2028 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2033 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2037 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2040 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2041 bool is_static = addr.state ==
2042 (is_multicast_ether_addr(addr.mac) ?
2043 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2044 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2047 ether_addr_copy(fdb->addr, addr.mac);
2048 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2050 err = cb(&fdb->obj);
2054 } while (!is_broadcast_ether_addr(addr.mac));
2059 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2060 struct switchdev_obj_port_fdb *fdb,
2061 int (*cb)(struct switchdev_obj *obj))
2063 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2064 struct mv88e6xxx_vtu_stu_entry vlan = {
2065 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2070 mutex_lock(&ps->smi_mutex);
2072 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2073 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2077 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2081 /* Dump VLANs' Filtering Information Databases */
2082 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2087 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2094 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2098 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2101 mutex_unlock(&ps->smi_mutex);
2106 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2107 struct net_device *bridge)
2109 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2113 mutex_lock(&ps->smi_mutex);
2115 /* Get or create the bridge FID and assign it to the port */
2116 for (i = 0; i < ps->num_ports; ++i)
2117 if (ps->ports[i].bridge_dev == bridge)
2120 if (i < ps->num_ports)
2121 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2123 err = _mv88e6xxx_fid_new(ds, &fid);
2127 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2131 /* Assign the bridge and remap each port's VLANTable */
2132 ps->ports[port].bridge_dev = bridge;
2134 for (i = 0; i < ps->num_ports; ++i) {
2135 if (ps->ports[i].bridge_dev == bridge) {
2136 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2143 mutex_unlock(&ps->smi_mutex);
2148 int mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2150 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2151 struct net_device *bridge = ps->ports[port].bridge_dev;
2155 mutex_lock(&ps->smi_mutex);
2157 /* Give the port a fresh Filtering Information Database */
2158 err = _mv88e6xxx_fid_new(ds, &fid);
2162 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2166 /* Unassign the bridge and remap each port's VLANTable */
2167 ps->ports[port].bridge_dev = NULL;
2169 for (i = 0; i < ps->num_ports; ++i) {
2170 if (i == port || ps->ports[i].bridge_dev == bridge) {
2171 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2178 mutex_unlock(&ps->smi_mutex);
2183 static void mv88e6xxx_bridge_work(struct work_struct *work)
2185 struct mv88e6xxx_priv_state *ps;
2186 struct dsa_switch *ds;
2189 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2190 ds = ((struct dsa_switch *)ps) - 1;
2192 while (ps->port_state_update_mask) {
2193 port = __ffs(ps->port_state_update_mask);
2194 clear_bit(port, &ps->port_state_update_mask);
2195 mv88e6xxx_set_port_state(ds, port, ps->ports[port].state);
2199 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2201 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2205 mutex_lock(&ps->smi_mutex);
2207 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2208 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2209 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2210 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2211 /* MAC Forcing register: don't force link, speed,
2212 * duplex or flow control state to any particular
2213 * values on physical ports, but force the CPU port
2214 * and all DSA ports to their maximum bandwidth and
2217 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2218 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2219 reg &= ~PORT_PCS_CTRL_UNFORCED;
2220 reg |= PORT_PCS_CTRL_FORCE_LINK |
2221 PORT_PCS_CTRL_LINK_UP |
2222 PORT_PCS_CTRL_DUPLEX_FULL |
2223 PORT_PCS_CTRL_FORCE_DUPLEX;
2224 if (mv88e6xxx_6065_family(ds))
2225 reg |= PORT_PCS_CTRL_100;
2227 reg |= PORT_PCS_CTRL_1000;
2229 reg |= PORT_PCS_CTRL_UNFORCED;
2232 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2233 PORT_PCS_CTRL, reg);
2238 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2239 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2240 * tunneling, determine priority by looking at 802.1p and IP
2241 * priority fields (IP prio has precedence), and set STP state
2244 * If this is the CPU link, use DSA or EDSA tagging depending
2245 * on which tagging mode was configured.
2247 * If this is a link to another switch, use DSA tagging mode.
2249 * If this is the upstream port for this switch, enable
2250 * forwarding of unknown unicasts and multicasts.
2253 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2254 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2255 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2256 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2257 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2258 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2259 PORT_CONTROL_STATE_FORWARDING;
2260 if (dsa_is_cpu_port(ds, port)) {
2261 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2262 reg |= PORT_CONTROL_DSA_TAG;
2263 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2264 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2265 mv88e6xxx_6320_family(ds)) {
2266 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2267 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2269 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2270 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2271 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2274 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2275 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2276 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2277 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2278 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2279 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2282 if (dsa_is_dsa_port(ds, port)) {
2283 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2284 reg |= PORT_CONTROL_DSA_TAG;
2285 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2286 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2287 mv88e6xxx_6320_family(ds)) {
2288 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2291 if (port == dsa_upstream_port(ds))
2292 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2293 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2296 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2302 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2303 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2304 * untagged frames on this port, do a destination address lookup on all
2305 * received packets as usual, disable ARP mirroring and don't send a
2306 * copy of all transmitted/received frames on this port to the CPU.
2309 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2310 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2311 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2312 reg = PORT_CONTROL_2_MAP_DA;
2314 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2315 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2316 reg |= PORT_CONTROL_2_JUMBO_10240;
2318 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2319 /* Set the upstream port this port should use */
2320 reg |= dsa_upstream_port(ds);
2321 /* enable forwarding of unknown multicast addresses to
2324 if (port == dsa_upstream_port(ds))
2325 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2328 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2331 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2332 PORT_CONTROL_2, reg);
2337 /* Port Association Vector: when learning source addresses
2338 * of packets, add the address to the address database using
2339 * a port bitmap that has only the bit for this port set and
2340 * the other bits clear.
2343 /* Disable learning for DSA and CPU ports */
2344 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2345 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2347 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2351 /* Egress rate control 2: disable egress rate control. */
2352 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2357 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2358 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2359 mv88e6xxx_6320_family(ds)) {
2360 /* Do not limit the period of time that this port can
2361 * be paused for by the remote end or the period of
2362 * time that this port can pause the remote end.
2364 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2365 PORT_PAUSE_CTRL, 0x0000);
2369 /* Port ATU control: disable limiting the number of
2370 * address database entries that this port is allowed
2373 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2374 PORT_ATU_CONTROL, 0x0000);
2375 /* Priority Override: disable DA, SA and VTU priority
2378 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2379 PORT_PRI_OVERRIDE, 0x0000);
2383 /* Port Ethertype: use the Ethertype DSA Ethertype
2386 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2387 PORT_ETH_TYPE, ETH_P_EDSA);
2390 /* Tag Remap: use an identity 802.1p prio -> switch
2393 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2394 PORT_TAG_REGMAP_0123, 0x3210);
2398 /* Tag Remap 2: use an identity 802.1p prio -> switch
2401 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2402 PORT_TAG_REGMAP_4567, 0x7654);
2407 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2408 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2409 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2410 mv88e6xxx_6320_family(ds)) {
2411 /* Rate Control: disable ingress rate limiting. */
2412 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2413 PORT_RATE_CONTROL, 0x0001);
2418 /* Port Control 1: disable trunking, disable sending
2419 * learning messages to this port.
2421 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2425 /* Port based VLAN map: give each port its own address
2426 * database, and allow bidirectional communication between the
2427 * CPU and DSA port(s), and the other ports.
2429 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2433 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2437 /* Default VLAN ID and priority: don't set a default VLAN
2438 * ID, and set the default packet priority to zero.
2440 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2443 mutex_unlock(&ps->smi_mutex);
2447 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2449 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2453 for (i = 0; i < ps->num_ports; i++) {
2454 ret = mv88e6xxx_setup_port(ds, i);
2461 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2465 mutex_init(&ps->smi_mutex);
2467 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2469 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2474 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2476 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2480 /* Set the default address aging time to 5 minutes, and
2481 * enable address learn messages to be sent to all message
2484 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2485 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2487 /* Configure the IP ToS mapping registers. */
2488 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2489 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2490 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2491 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2492 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2493 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2494 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2495 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2497 /* Configure the IEEE 802.1p priority mapping register. */
2498 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2500 /* Send all frames with destination addresses matching
2501 * 01:80:c2:00:00:0x to the CPU port.
2503 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2505 /* Ignore removed tag data on doubly tagged packets, disable
2506 * flow control messages, force flow control priority to the
2507 * highest, and send all special multicast frames to the CPU
2508 * port at the highest priority.
2510 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2511 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2512 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2514 /* Program the DSA routing table. */
2515 for (i = 0; i < 32; i++) {
2518 if (ds->pd->rtable &&
2519 i != ds->index && i < ds->dst->pd->nr_chips)
2520 nexthop = ds->pd->rtable[i] & 0x1f;
2522 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2523 GLOBAL2_DEVICE_MAPPING_UPDATE |
2524 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2528 /* Clear all trunk masks. */
2529 for (i = 0; i < 8; i++)
2530 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2531 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2532 ((1 << ps->num_ports) - 1));
2534 /* Clear all trunk mappings. */
2535 for (i = 0; i < 16; i++)
2536 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2537 GLOBAL2_TRUNK_MAPPING_UPDATE |
2538 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2540 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2541 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2542 mv88e6xxx_6320_family(ds)) {
2543 /* Send all frames with destination addresses matching
2544 * 01:80:c2:00:00:2x to the CPU port.
2546 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2548 /* Initialise cross-chip port VLAN table to reset
2551 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2553 /* Clear the priority override table. */
2554 for (i = 0; i < 16; i++)
2555 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2559 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2560 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2561 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2562 mv88e6xxx_6320_family(ds)) {
2563 /* Disable ingress rate limiting by resetting all
2564 * ingress rate limit registers to their initial
2567 for (i = 0; i < ps->num_ports; i++)
2568 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2572 /* Clear the statistics counters for all ports */
2573 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2575 /* Wait for the flush to complete. */
2576 mutex_lock(&ps->smi_mutex);
2577 ret = _mv88e6xxx_stats_wait(ds);
2581 /* Clear all ATU entries */
2582 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2586 /* Clear all the VTU and STU entries */
2587 ret = _mv88e6xxx_vtu_stu_flush(ds);
2589 mutex_unlock(&ps->smi_mutex);
2594 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2596 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2597 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2598 struct gpio_desc *gpiod = ds->pd->reset;
2599 unsigned long timeout;
2603 /* Set all ports to the disabled state. */
2604 for (i = 0; i < ps->num_ports; i++) {
2605 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2606 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2609 /* Wait for transmit queues to drain. */
2610 usleep_range(2000, 4000);
2612 /* If there is a gpio connected to the reset pin, toggle it */
2614 gpiod_set_value_cansleep(gpiod, 1);
2615 usleep_range(10000, 20000);
2616 gpiod_set_value_cansleep(gpiod, 0);
2617 usleep_range(10000, 20000);
2620 /* Reset the switch. Keep the PPU active if requested. The PPU
2621 * needs to be active to support indirect phy register access
2622 * through global registers 0x18 and 0x19.
2625 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2627 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2629 /* Wait up to one second for reset to complete. */
2630 timeout = jiffies + 1 * HZ;
2631 while (time_before(jiffies, timeout)) {
2632 ret = REG_READ(REG_GLOBAL, 0x00);
2633 if ((ret & is_reset) == is_reset)
2635 usleep_range(1000, 2000);
2637 if (time_after(jiffies, timeout))
2643 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2645 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2648 mutex_lock(&ps->smi_mutex);
2649 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2652 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2654 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2655 mutex_unlock(&ps->smi_mutex);
2659 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2662 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2665 mutex_lock(&ps->smi_mutex);
2666 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2670 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2672 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2673 mutex_unlock(&ps->smi_mutex);
2677 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2679 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2681 if (port >= 0 && port < ps->num_ports)
2687 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2689 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2690 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2696 mutex_lock(&ps->smi_mutex);
2697 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2698 mutex_unlock(&ps->smi_mutex);
2703 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2705 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2706 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2712 mutex_lock(&ps->smi_mutex);
2713 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2714 mutex_unlock(&ps->smi_mutex);
2719 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2721 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2722 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2728 mutex_lock(&ps->smi_mutex);
2729 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2730 mutex_unlock(&ps->smi_mutex);
2735 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2738 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2739 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2745 mutex_lock(&ps->smi_mutex);
2746 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2747 mutex_unlock(&ps->smi_mutex);
2751 #ifdef CONFIG_NET_DSA_HWMON
2753 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2755 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2761 mutex_lock(&ps->smi_mutex);
2763 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2767 /* Enable temperature sensor */
2768 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2772 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2776 /* Wait for temperature to stabilize */
2777 usleep_range(10000, 12000);
2779 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2785 /* Disable temperature sensor */
2786 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2790 *temp = ((val & 0x1f) - 5) * 5;
2793 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2794 mutex_unlock(&ps->smi_mutex);
2798 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2800 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2805 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2809 *temp = (ret & 0xff) - 25;
2814 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2816 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2817 return mv88e63xx_get_temp(ds, temp);
2819 return mv88e61xx_get_temp(ds, temp);
2822 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2824 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2827 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2832 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2836 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
2841 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
2843 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2846 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2849 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2852 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
2853 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
2854 (ret & 0xe0ff) | (temp << 8));
2857 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
2859 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2862 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
2867 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
2871 *alarm = !!(ret & 0x40);
2875 #endif /* CONFIG_NET_DSA_HWMON */
2877 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
2878 const struct mv88e6xxx_switch_id *table,
2881 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
2887 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
2891 /* Look up the exact switch ID */
2892 for (i = 0; i < num; ++i)
2893 if (table[i].id == ret)
2894 return table[i].name;
2896 /* Look up only the product number */
2897 for (i = 0; i < num; ++i) {
2898 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
2899 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
2900 ret & PORT_SWITCH_ID_REV_MASK,
2901 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
2902 return table[i].name;
2909 static int __init mv88e6xxx_init(void)
2911 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2912 register_switch_driver(&mv88e6131_switch_driver);
2914 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2915 register_switch_driver(&mv88e6123_61_65_switch_driver);
2917 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2918 register_switch_driver(&mv88e6352_switch_driver);
2920 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2921 register_switch_driver(&mv88e6171_switch_driver);
2925 module_init(mv88e6xxx_init);
2927 static void __exit mv88e6xxx_cleanup(void)
2929 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
2930 unregister_switch_driver(&mv88e6171_switch_driver);
2932 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
2933 unregister_switch_driver(&mv88e6352_switch_driver);
2935 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123_61_65)
2936 unregister_switch_driver(&mv88e6123_61_65_switch_driver);
2938 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
2939 unregister_switch_driver(&mv88e6131_switch_driver);
2942 module_exit(mv88e6xxx_cleanup);
2944 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
2945 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
2946 MODULE_LICENSE("GPL");