2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
102 ret = __mv88e6xxx_reg_read(ps->bus, ps->sw_addr, addr, reg);
106 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
112 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
114 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
117 mutex_lock(&ps->smi_mutex);
118 ret = _mv88e6xxx_reg_read(ds, addr, reg);
119 mutex_unlock(&ps->smi_mutex);
124 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
130 return mdiobus_write_nested(bus, addr, reg, val);
132 /* Wait for the bus to become free. */
133 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
137 /* Transmit the data to write. */
138 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
142 /* Transmit the write command. */
143 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
144 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
148 /* Wait for the write command to complete. */
149 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
156 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
159 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
163 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
166 return __mv88e6xxx_reg_write(ps->bus, ps->sw_addr, addr, reg, val);
169 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
171 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
174 mutex_lock(&ps->smi_mutex);
175 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
176 mutex_unlock(&ps->smi_mutex);
181 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
185 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_01,
186 (addr[0] << 8) | addr[1]);
190 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_23,
191 (addr[2] << 8) | addr[3]);
195 return mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_MAC_45,
196 (addr[4] << 8) | addr[5]);
199 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
204 for (i = 0; i < 6; i++) {
207 /* Write the MAC address byte. */
208 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
209 GLOBAL2_SWITCH_MAC_BUSY |
214 /* Wait for the write to complete. */
215 for (j = 0; j < 16; j++) {
216 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL2,
221 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
231 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
234 return _mv88e6xxx_reg_read(ds, addr, regnum);
238 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
242 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
246 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
247 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
250 unsigned long timeout;
252 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
256 ret = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
257 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
261 timeout = jiffies + 1 * HZ;
262 while (time_before(jiffies, timeout)) {
263 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
267 usleep_range(1000, 2000);
268 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
269 GLOBAL_STATUS_PPU_POLLING)
276 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
279 unsigned long timeout;
281 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_CONTROL);
285 err = mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_CONTROL,
286 ret | GLOBAL_CONTROL_PPU_ENABLE);
290 timeout = jiffies + 1 * HZ;
291 while (time_before(jiffies, timeout)) {
292 ret = mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATUS);
296 usleep_range(1000, 2000);
297 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
298 GLOBAL_STATUS_PPU_POLLING)
305 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
307 struct mv88e6xxx_priv_state *ps;
309 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
310 if (mutex_trylock(&ps->ppu_mutex)) {
311 struct dsa_switch *ds = ps->ds;
313 if (mv88e6xxx_ppu_enable(ds) == 0)
314 ps->ppu_disabled = 0;
315 mutex_unlock(&ps->ppu_mutex);
319 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
321 struct mv88e6xxx_priv_state *ps = (void *)_ps;
323 schedule_work(&ps->ppu_work);
326 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
331 mutex_lock(&ps->ppu_mutex);
333 /* If the PHY polling unit is enabled, disable it so that
334 * we can access the PHY registers. If it was already
335 * disabled, cancel the timer that is going to re-enable
338 if (!ps->ppu_disabled) {
339 ret = mv88e6xxx_ppu_disable(ds);
341 mutex_unlock(&ps->ppu_mutex);
344 ps->ppu_disabled = 1;
346 del_timer(&ps->ppu_timer);
353 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
355 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
357 /* Schedule a timer to re-enable the PHY polling unit. */
358 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
359 mutex_unlock(&ps->ppu_mutex);
362 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
364 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
366 mutex_init(&ps->ppu_mutex);
367 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
368 init_timer(&ps->ppu_timer);
369 ps->ppu_timer.data = (unsigned long)ps;
370 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
373 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
377 ret = mv88e6xxx_ppu_access_get(ds);
379 ret = mv88e6xxx_reg_read(ds, addr, regnum);
380 mv88e6xxx_ppu_access_put(ds);
386 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
391 ret = mv88e6xxx_ppu_access_get(ds);
393 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
394 mv88e6xxx_ppu_access_put(ds);
401 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
403 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 return ps->info->family == MV88E6XXX_FAMILY_6065;
408 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
410 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
412 return ps->info->family == MV88E6XXX_FAMILY_6095;
415 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
417 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 return ps->info->family == MV88E6XXX_FAMILY_6097;
422 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
424 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
426 return ps->info->family == MV88E6XXX_FAMILY_6165;
429 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
431 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
433 return ps->info->family == MV88E6XXX_FAMILY_6185;
436 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
438 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
440 return ps->info->family == MV88E6XXX_FAMILY_6320;
443 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
445 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
447 return ps->info->family == MV88E6XXX_FAMILY_6351;
450 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
452 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
454 return ps->info->family == MV88E6XXX_FAMILY_6352;
457 static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
461 return ps->info->num_databases;
464 static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
466 /* Does the device have dedicated FID registers for ATU and VTU ops? */
467 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
468 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
474 static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
476 /* Does the device have STU and dedicated SID registers for VTU ops? */
477 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
478 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
484 /* We expect the switch to perform auto negotiation if there is a real
485 * phy. However, in the case of a fixed link phy, we force the port
486 * settings from the fixed link settings.
488 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
489 struct phy_device *phydev)
491 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
495 if (!phy_is_pseudo_fixed_link(phydev))
498 mutex_lock(&ps->smi_mutex);
500 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
504 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
505 PORT_PCS_CTRL_FORCE_LINK |
506 PORT_PCS_CTRL_DUPLEX_FULL |
507 PORT_PCS_CTRL_FORCE_DUPLEX |
508 PORT_PCS_CTRL_UNFORCED);
510 reg |= PORT_PCS_CTRL_FORCE_LINK;
512 reg |= PORT_PCS_CTRL_LINK_UP;
514 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
517 switch (phydev->speed) {
519 reg |= PORT_PCS_CTRL_1000;
522 reg |= PORT_PCS_CTRL_100;
525 reg |= PORT_PCS_CTRL_10;
528 pr_info("Unknown speed");
532 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
533 if (phydev->duplex == DUPLEX_FULL)
534 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
536 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
537 (port >= ps->info->num_ports - 2)) {
538 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
539 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
540 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
541 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
542 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
543 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
544 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
546 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
549 mutex_unlock(&ps->smi_mutex);
552 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
557 for (i = 0; i < 10; i++) {
558 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
559 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
566 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
570 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
571 port = (port + 1) << 5;
573 /* Snapshot the hardware statistics counters for this port. */
574 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
575 GLOBAL_STATS_OP_CAPTURE_PORT |
576 GLOBAL_STATS_OP_HIST_RX_TX | port);
580 /* Wait for the snapshotting to complete. */
581 ret = _mv88e6xxx_stats_wait(ds);
588 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
595 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
596 GLOBAL_STATS_OP_READ_CAPTURED |
597 GLOBAL_STATS_OP_HIST_RX_TX | stat);
601 ret = _mv88e6xxx_stats_wait(ds);
605 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
611 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
618 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
619 { "in_good_octets", 8, 0x00, BANK0, },
620 { "in_bad_octets", 4, 0x02, BANK0, },
621 { "in_unicast", 4, 0x04, BANK0, },
622 { "in_broadcasts", 4, 0x06, BANK0, },
623 { "in_multicasts", 4, 0x07, BANK0, },
624 { "in_pause", 4, 0x16, BANK0, },
625 { "in_undersize", 4, 0x18, BANK0, },
626 { "in_fragments", 4, 0x19, BANK0, },
627 { "in_oversize", 4, 0x1a, BANK0, },
628 { "in_jabber", 4, 0x1b, BANK0, },
629 { "in_rx_error", 4, 0x1c, BANK0, },
630 { "in_fcs_error", 4, 0x1d, BANK0, },
631 { "out_octets", 8, 0x0e, BANK0, },
632 { "out_unicast", 4, 0x10, BANK0, },
633 { "out_broadcasts", 4, 0x13, BANK0, },
634 { "out_multicasts", 4, 0x12, BANK0, },
635 { "out_pause", 4, 0x15, BANK0, },
636 { "excessive", 4, 0x11, BANK0, },
637 { "collisions", 4, 0x1e, BANK0, },
638 { "deferred", 4, 0x05, BANK0, },
639 { "single", 4, 0x14, BANK0, },
640 { "multiple", 4, 0x17, BANK0, },
641 { "out_fcs_error", 4, 0x03, BANK0, },
642 { "late", 4, 0x1f, BANK0, },
643 { "hist_64bytes", 4, 0x08, BANK0, },
644 { "hist_65_127bytes", 4, 0x09, BANK0, },
645 { "hist_128_255bytes", 4, 0x0a, BANK0, },
646 { "hist_256_511bytes", 4, 0x0b, BANK0, },
647 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
648 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
649 { "sw_in_discards", 4, 0x10, PORT, },
650 { "sw_in_filtered", 2, 0x12, PORT, },
651 { "sw_out_filtered", 2, 0x13, PORT, },
652 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
653 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
654 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
655 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
656 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
657 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
658 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
659 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
660 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
661 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
662 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
663 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
664 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
665 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
666 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
667 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
668 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
669 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
670 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
671 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
672 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
673 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
674 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
675 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
676 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
677 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
680 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
681 struct mv88e6xxx_hw_stat *stat)
683 switch (stat->type) {
687 return mv88e6xxx_6320_family(ds);
689 return mv88e6xxx_6095_family(ds) ||
690 mv88e6xxx_6185_family(ds) ||
691 mv88e6xxx_6097_family(ds) ||
692 mv88e6xxx_6165_family(ds) ||
693 mv88e6xxx_6351_family(ds) ||
694 mv88e6xxx_6352_family(ds);
699 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
700 struct mv88e6xxx_hw_stat *s,
710 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
715 if (s->sizeof_stat == 4) {
716 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
725 _mv88e6xxx_stats_read(ds, s->reg, &low);
726 if (s->sizeof_stat == 8)
727 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
729 value = (((u64)high) << 16) | low;
733 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
735 struct mv88e6xxx_hw_stat *stat;
738 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
739 stat = &mv88e6xxx_hw_stats[i];
740 if (mv88e6xxx_has_stat(ds, stat)) {
741 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
748 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
750 struct mv88e6xxx_hw_stat *stat;
753 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
754 stat = &mv88e6xxx_hw_stats[i];
755 if (mv88e6xxx_has_stat(ds, stat))
762 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
763 int port, uint64_t *data)
765 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
766 struct mv88e6xxx_hw_stat *stat;
770 mutex_lock(&ps->smi_mutex);
772 ret = _mv88e6xxx_stats_snapshot(ds, port);
774 mutex_unlock(&ps->smi_mutex);
777 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
778 stat = &mv88e6xxx_hw_stats[i];
779 if (mv88e6xxx_has_stat(ds, stat)) {
780 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
785 mutex_unlock(&ps->smi_mutex);
788 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
790 return 32 * sizeof(u16);
793 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
794 struct ethtool_regs *regs, void *_p)
801 memset(p, 0xff, 32 * sizeof(u16));
803 for (i = 0; i < 32; i++) {
806 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
812 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
815 unsigned long timeout = jiffies + HZ / 10;
817 while (time_before(jiffies, timeout)) {
820 ret = _mv88e6xxx_reg_read(ds, reg, offset);
826 usleep_range(1000, 2000);
831 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
833 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
836 mutex_lock(&ps->smi_mutex);
837 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
838 mutex_unlock(&ps->smi_mutex);
843 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
845 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
846 GLOBAL2_SMI_OP_BUSY);
849 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
851 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
852 GLOBAL2_EEPROM_OP_LOAD);
855 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
857 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
858 GLOBAL2_EEPROM_OP_BUSY);
861 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
863 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
867 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
872 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
873 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
878 ret = _mv88e6xxx_phy_wait(ds);
882 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
885 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
890 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
894 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
895 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
898 return _mv88e6xxx_phy_wait(ds);
901 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
903 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
906 mutex_lock(&ps->smi_mutex);
908 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
912 e->eee_enabled = !!(reg & 0x0200);
913 e->tx_lpi_enabled = !!(reg & 0x0100);
915 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
919 e->eee_active = !!(reg & PORT_STATUS_EEE);
923 mutex_unlock(&ps->smi_mutex);
927 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
928 struct phy_device *phydev, struct ethtool_eee *e)
930 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
934 mutex_lock(&ps->smi_mutex);
936 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
943 if (e->tx_lpi_enabled)
946 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
948 mutex_unlock(&ps->smi_mutex);
953 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
957 if (mv88e6xxx_has_fid_reg(ds)) {
958 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
961 } else if (mv88e6xxx_num_databases(ds) == 256) {
962 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
963 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL);
967 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
969 ((fid << 8) & 0xf000));
973 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
977 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
981 return _mv88e6xxx_atu_wait(ds);
984 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
985 struct mv88e6xxx_atu_entry *entry)
987 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
989 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
990 unsigned int mask, shift;
993 data |= GLOBAL_ATU_DATA_TRUNK;
994 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
995 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
997 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
998 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1001 data |= (entry->portv_trunkid << shift) & mask;
1004 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1007 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1008 struct mv88e6xxx_atu_entry *entry,
1014 err = _mv88e6xxx_atu_wait(ds);
1018 err = _mv88e6xxx_atu_data_write(ds, entry);
1023 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1024 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1026 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1027 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1030 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
1033 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1035 struct mv88e6xxx_atu_entry entry = {
1037 .state = 0, /* EntryState bits must be 0 */
1040 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1043 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1044 int to_port, bool static_too)
1046 struct mv88e6xxx_atu_entry entry = {
1051 /* EntryState bits must be 0xF */
1052 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1054 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1055 entry.portv_trunkid = (to_port & 0x0f) << 4;
1056 entry.portv_trunkid |= from_port & 0x0f;
1058 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1061 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1064 /* Destination port 0xF means remove the entries */
1065 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1068 static const char * const mv88e6xxx_port_state_names[] = {
1069 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1070 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1071 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1072 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1075 static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
1080 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1084 oldstate = reg & PORT_CONTROL_STATE_MASK;
1086 if (oldstate != state) {
1087 /* Flush forwarding database if we're moving a port
1088 * from Learning or Forwarding state to Disabled or
1089 * Blocking or Listening state.
1091 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1092 oldstate == PORT_CONTROL_STATE_FORWARDING)
1093 && (state == PORT_CONTROL_STATE_DISABLED ||
1094 state == PORT_CONTROL_STATE_BLOCKING)) {
1095 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1100 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1101 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1106 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1107 mv88e6xxx_port_state_names[state],
1108 mv88e6xxx_port_state_names[oldstate]);
1114 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1116 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1117 struct net_device *bridge = ps->ports[port].bridge_dev;
1118 const u16 mask = (1 << ps->info->num_ports) - 1;
1119 u16 output_ports = 0;
1123 /* allow CPU port or DSA link(s) to send frames to every port */
1124 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1125 output_ports = mask;
1127 for (i = 0; i < ps->info->num_ports; ++i) {
1128 /* allow sending frames to every group member */
1129 if (bridge && ps->ports[i].bridge_dev == bridge)
1130 output_ports |= BIT(i);
1132 /* allow sending frames to CPU port and DSA link(s) */
1133 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1134 output_ports |= BIT(i);
1138 /* prevent frames from going back out of the port they came in on */
1139 output_ports &= ~BIT(port);
1141 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1146 reg |= output_ports & mask;
1148 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1151 void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1153 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1157 case BR_STATE_DISABLED:
1158 stp_state = PORT_CONTROL_STATE_DISABLED;
1160 case BR_STATE_BLOCKING:
1161 case BR_STATE_LISTENING:
1162 stp_state = PORT_CONTROL_STATE_BLOCKING;
1164 case BR_STATE_LEARNING:
1165 stp_state = PORT_CONTROL_STATE_LEARNING;
1167 case BR_STATE_FORWARDING:
1169 stp_state = PORT_CONTROL_STATE_FORWARDING;
1173 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
1174 * so we can not update the port state directly but need to schedule it.
1176 ps->ports[port].state = stp_state;
1177 set_bit(port, ps->port_state_update_mask);
1178 schedule_work(&ps->bridge_work);
1181 static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1187 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1191 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1194 ret &= ~PORT_DEFAULT_VLAN_MASK;
1195 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1197 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1198 PORT_DEFAULT_VLAN, ret);
1202 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1212 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1214 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1217 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1219 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
1222 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1224 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1225 GLOBAL_VTU_OP_BUSY);
1228 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1232 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1236 return _mv88e6xxx_vtu_wait(ds);
1239 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1243 ret = _mv88e6xxx_vtu_wait(ds);
1247 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1250 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1251 struct mv88e6xxx_vtu_stu_entry *entry,
1252 unsigned int nibble_offset)
1254 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1259 for (i = 0; i < 3; ++i) {
1260 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1261 GLOBAL_VTU_DATA_0_3 + i);
1268 for (i = 0; i < ps->info->num_ports; ++i) {
1269 unsigned int shift = (i % 4) * 4 + nibble_offset;
1270 u16 reg = regs[i / 4];
1272 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1278 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1279 struct mv88e6xxx_vtu_stu_entry *entry,
1280 unsigned int nibble_offset)
1282 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1283 u16 regs[3] = { 0 };
1287 for (i = 0; i < ps->info->num_ports; ++i) {
1288 unsigned int shift = (i % 4) * 4 + nibble_offset;
1289 u8 data = entry->data[i];
1291 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1294 for (i = 0; i < 3; ++i) {
1295 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1296 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1304 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1306 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1307 vid & GLOBAL_VTU_VID_MASK);
1310 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1311 struct mv88e6xxx_vtu_stu_entry *entry)
1313 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1316 ret = _mv88e6xxx_vtu_wait(ds);
1320 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1324 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1328 next.vid = ret & GLOBAL_VTU_VID_MASK;
1329 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1332 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1336 if (mv88e6xxx_has_fid_reg(ds)) {
1337 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1342 next.fid = ret & GLOBAL_VTU_FID_MASK;
1343 } else if (mv88e6xxx_num_databases(ds) == 256) {
1344 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1345 * VTU DBNum[3:0] are located in VTU Operation 3:0
1347 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1352 next.fid = (ret & 0xf00) >> 4;
1353 next.fid |= ret & 0xf;
1356 if (mv88e6xxx_has_stu(ds)) {
1357 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1362 next.sid = ret & GLOBAL_VTU_SID_MASK;
1370 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1371 struct switchdev_obj_port_vlan *vlan,
1372 int (*cb)(struct switchdev_obj *obj))
1374 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1375 struct mv88e6xxx_vtu_stu_entry next;
1379 mutex_lock(&ps->smi_mutex);
1381 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1385 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1390 err = _mv88e6xxx_vtu_getnext(ds, &next);
1397 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1400 /* reinit and dump this VLAN obj */
1401 vlan->vid_begin = vlan->vid_end = next.vid;
1404 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1405 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1407 if (next.vid == pvid)
1408 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1410 err = cb(&vlan->obj);
1413 } while (next.vid < GLOBAL_VTU_VID_MASK);
1416 mutex_unlock(&ps->smi_mutex);
1421 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1422 struct mv88e6xxx_vtu_stu_entry *entry)
1424 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1428 ret = _mv88e6xxx_vtu_wait(ds);
1435 /* Write port member tags */
1436 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1440 if (mv88e6xxx_has_stu(ds)) {
1441 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1442 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1447 if (mv88e6xxx_has_fid_reg(ds)) {
1448 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1449 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1452 } else if (mv88e6xxx_num_databases(ds) == 256) {
1453 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1454 * VTU DBNum[3:0] are located in VTU Operation 3:0
1456 op |= (entry->fid & 0xf0) << 8;
1457 op |= entry->fid & 0xf;
1460 reg = GLOBAL_VTU_VID_VALID;
1462 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1463 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1467 return _mv88e6xxx_vtu_cmd(ds, op);
1470 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1471 struct mv88e6xxx_vtu_stu_entry *entry)
1473 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1476 ret = _mv88e6xxx_vtu_wait(ds);
1480 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1481 sid & GLOBAL_VTU_SID_MASK);
1485 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1489 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1493 next.sid = ret & GLOBAL_VTU_SID_MASK;
1495 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1499 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1502 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1511 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1512 struct mv88e6xxx_vtu_stu_entry *entry)
1517 ret = _mv88e6xxx_vtu_wait(ds);
1524 /* Write port states */
1525 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1529 reg = GLOBAL_VTU_VID_VALID;
1531 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1535 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1536 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1540 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1543 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1550 if (mv88e6xxx_num_databases(ds) == 4096)
1552 else if (mv88e6xxx_num_databases(ds) == 256)
1557 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1558 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1562 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1565 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1566 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1568 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1574 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1575 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1579 fid |= (ret & upper_mask) << 4;
1583 ret |= (*new >> 4) & upper_mask;
1585 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1590 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1599 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1601 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1604 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1606 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1609 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1611 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1612 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1613 struct mv88e6xxx_vtu_stu_entry vlan;
1616 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1618 /* Set every FID bit used by the (un)bridged ports */
1619 for (i = 0; i < ps->info->num_ports; ++i) {
1620 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1624 set_bit(*fid, fid_bitmap);
1627 /* Set every FID bit used by the VLAN entries */
1628 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1633 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1640 set_bit(vlan.fid, fid_bitmap);
1641 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1643 /* The reset value 0x000 is used to indicate that multiple address
1644 * databases are not needed. Return the next positive available.
1646 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1647 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
1650 /* Clear the database */
1651 return _mv88e6xxx_atu_flush(ds, *fid, true);
1654 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1655 struct mv88e6xxx_vtu_stu_entry *entry)
1657 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1658 struct mv88e6xxx_vtu_stu_entry vlan = {
1664 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1668 /* exclude all ports except the CPU and DSA ports */
1669 for (i = 0; i < ps->info->num_ports; ++i)
1670 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1671 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1672 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1674 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1675 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1676 struct mv88e6xxx_vtu_stu_entry vstp;
1678 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1679 * implemented, only one STU entry is needed to cover all VTU
1680 * entries. Thus, validate the SID 0.
1683 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1687 if (vstp.sid != vlan.sid || !vstp.valid) {
1688 memset(&vstp, 0, sizeof(vstp));
1690 vstp.sid = vlan.sid;
1692 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1702 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1703 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1710 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1714 err = _mv88e6xxx_vtu_getnext(ds, entry);
1718 if (entry->vid != vid || !entry->valid) {
1721 /* -ENOENT would've been more appropriate, but switchdev expects
1722 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1725 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1731 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1732 u16 vid_begin, u16 vid_end)
1734 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1735 struct mv88e6xxx_vtu_stu_entry vlan;
1741 mutex_lock(&ps->smi_mutex);
1743 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1748 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1755 if (vlan.vid > vid_end)
1758 for (i = 0; i < ps->info->num_ports; ++i) {
1759 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1763 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1766 if (ps->ports[i].bridge_dev ==
1767 ps->ports[port].bridge_dev)
1768 break; /* same bridge, check next VLAN */
1770 netdev_warn(ds->ports[port],
1771 "hardware VLAN %d already used by %s\n",
1773 netdev_name(ps->ports[i].bridge_dev));
1777 } while (vlan.vid < vid_end);
1780 mutex_unlock(&ps->smi_mutex);
1785 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1786 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1787 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1788 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1789 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1792 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1793 bool vlan_filtering)
1795 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1796 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1797 PORT_CONTROL_2_8021Q_DISABLED;
1800 mutex_lock(&ps->smi_mutex);
1802 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1806 old = ret & PORT_CONTROL_2_8021Q_MASK;
1809 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1810 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1812 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1817 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1818 mv88e6xxx_port_8021q_mode_names[new],
1819 mv88e6xxx_port_8021q_mode_names[old]);
1824 mutex_unlock(&ps->smi_mutex);
1829 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1830 const struct switchdev_obj_port_vlan *vlan,
1831 struct switchdev_trans *trans)
1835 /* If the requested port doesn't belong to the same bridge as the VLAN
1836 * members, do not support it (yet) and fallback to software VLAN.
1838 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1843 /* We don't need any dynamic resource from the kernel (yet),
1844 * so skip the prepare phase.
1849 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1852 struct mv88e6xxx_vtu_stu_entry vlan;
1855 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1859 vlan.data[port] = untagged ?
1860 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1861 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1863 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1866 void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1867 const struct switchdev_obj_port_vlan *vlan,
1868 struct switchdev_trans *trans)
1870 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1871 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1872 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1875 mutex_lock(&ps->smi_mutex);
1877 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1878 if (_mv88e6xxx_port_vlan_add(ds, port, vid, untagged))
1879 netdev_err(ds->ports[port], "failed to add VLAN %d%c\n",
1880 vid, untagged ? 'u' : 't');
1882 if (pvid && _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end))
1883 netdev_err(ds->ports[port], "failed to set PVID %d\n",
1886 mutex_unlock(&ps->smi_mutex);
1889 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1891 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1892 struct mv88e6xxx_vtu_stu_entry vlan;
1895 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1899 /* Tell switchdev if this VLAN is handled in software */
1900 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1903 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1905 /* keep the VLAN unless all ports are excluded */
1907 for (i = 0; i < ps->info->num_ports; ++i) {
1908 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1911 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1917 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1921 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1924 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1925 const struct switchdev_obj_port_vlan *vlan)
1927 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1931 mutex_lock(&ps->smi_mutex);
1933 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1937 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1938 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1943 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1950 mutex_unlock(&ps->smi_mutex);
1955 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1956 const unsigned char *addr)
1960 for (i = 0; i < 3; i++) {
1961 ret = _mv88e6xxx_reg_write(
1962 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1963 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1971 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1975 for (i = 0; i < 3; i++) {
1976 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1977 GLOBAL_ATU_MAC_01 + i);
1980 addr[i * 2] = ret >> 8;
1981 addr[i * 2 + 1] = ret & 0xff;
1987 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
1988 struct mv88e6xxx_atu_entry *entry)
1992 ret = _mv88e6xxx_atu_wait(ds);
1996 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
2000 ret = _mv88e6xxx_atu_data_write(ds, entry);
2004 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2007 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2008 const unsigned char *addr, u16 vid,
2011 struct mv88e6xxx_atu_entry entry = { 0 };
2012 struct mv88e6xxx_vtu_stu_entry vlan;
2015 /* Null VLAN ID corresponds to the port private database */
2017 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2019 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
2023 entry.fid = vlan.fid;
2024 entry.state = state;
2025 ether_addr_copy(entry.mac, addr);
2026 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2027 entry.trunk = false;
2028 entry.portv_trunkid = BIT(port);
2031 return _mv88e6xxx_atu_load(ds, &entry);
2034 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2035 const struct switchdev_obj_port_fdb *fdb,
2036 struct switchdev_trans *trans)
2038 /* We don't need any dynamic resource from the kernel (yet),
2039 * so skip the prepare phase.
2044 void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2045 const struct switchdev_obj_port_fdb *fdb,
2046 struct switchdev_trans *trans)
2048 int state = is_multicast_ether_addr(fdb->addr) ?
2049 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2050 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2051 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2053 mutex_lock(&ps->smi_mutex);
2054 if (_mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state))
2055 netdev_err(ds->ports[port], "failed to load MAC address\n");
2056 mutex_unlock(&ps->smi_mutex);
2059 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2060 const struct switchdev_obj_port_fdb *fdb)
2062 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2065 mutex_lock(&ps->smi_mutex);
2066 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
2067 GLOBAL_ATU_DATA_STATE_UNUSED);
2068 mutex_unlock(&ps->smi_mutex);
2073 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
2074 struct mv88e6xxx_atu_entry *entry)
2076 struct mv88e6xxx_atu_entry next = { 0 };
2081 ret = _mv88e6xxx_atu_wait(ds);
2085 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2089 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2093 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2097 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2098 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2099 unsigned int mask, shift;
2101 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2103 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2104 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2107 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2108 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2111 next.portv_trunkid = (ret & mask) >> shift;
2118 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2120 struct switchdev_obj_port_fdb *fdb,
2121 int (*cb)(struct switchdev_obj *obj))
2123 struct mv88e6xxx_atu_entry addr = {
2124 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2128 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2133 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2137 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2140 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2141 bool is_static = addr.state ==
2142 (is_multicast_ether_addr(addr.mac) ?
2143 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2144 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2147 ether_addr_copy(fdb->addr, addr.mac);
2148 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2150 err = cb(&fdb->obj);
2154 } while (!is_broadcast_ether_addr(addr.mac));
2159 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2160 struct switchdev_obj_port_fdb *fdb,
2161 int (*cb)(struct switchdev_obj *obj))
2163 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2164 struct mv88e6xxx_vtu_stu_entry vlan = {
2165 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2170 mutex_lock(&ps->smi_mutex);
2172 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2173 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2177 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2181 /* Dump VLANs' Filtering Information Databases */
2182 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2187 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2194 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2198 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2201 mutex_unlock(&ps->smi_mutex);
2206 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2207 struct net_device *bridge)
2209 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2213 mutex_lock(&ps->smi_mutex);
2215 /* Get or create the bridge FID and assign it to the port */
2216 for (i = 0; i < ps->info->num_ports; ++i)
2217 if (ps->ports[i].bridge_dev == bridge)
2220 if (i < ps->info->num_ports)
2221 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2223 err = _mv88e6xxx_fid_new(ds, &fid);
2227 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2231 /* Assign the bridge and remap each port's VLANTable */
2232 ps->ports[port].bridge_dev = bridge;
2234 for (i = 0; i < ps->info->num_ports; ++i) {
2235 if (ps->ports[i].bridge_dev == bridge) {
2236 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2243 mutex_unlock(&ps->smi_mutex);
2248 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2250 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2251 struct net_device *bridge = ps->ports[port].bridge_dev;
2255 mutex_lock(&ps->smi_mutex);
2257 /* Give the port a fresh Filtering Information Database */
2258 if (_mv88e6xxx_fid_new(ds, &fid) ||
2259 _mv88e6xxx_port_fid_set(ds, port, fid))
2260 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
2262 /* Unassign the bridge and remap each port's VLANTable */
2263 ps->ports[port].bridge_dev = NULL;
2265 for (i = 0; i < ps->info->num_ports; ++i)
2266 if (i == port || ps->ports[i].bridge_dev == bridge)
2267 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2268 netdev_warn(ds->ports[i], "failed to remap\n");
2270 mutex_unlock(&ps->smi_mutex);
2273 static void mv88e6xxx_bridge_work(struct work_struct *work)
2275 struct mv88e6xxx_priv_state *ps;
2276 struct dsa_switch *ds;
2279 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2282 mutex_lock(&ps->smi_mutex);
2284 for (port = 0; port < ps->info->num_ports; ++port)
2285 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2286 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2287 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2288 mv88e6xxx_port_state_names[ps->ports[port].state]);
2290 mutex_unlock(&ps->smi_mutex);
2293 static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2298 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2300 goto restore_page_0;
2302 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2304 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2309 static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2314 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2316 goto restore_page_0;
2318 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2320 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2325 static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2329 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2334 if (ret & BMCR_PDOWN) {
2336 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2337 PAGE_FIBER_SERDES, MII_BMCR,
2344 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2346 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2350 mutex_lock(&ps->smi_mutex);
2352 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2353 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2354 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2355 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2356 /* MAC Forcing register: don't force link, speed,
2357 * duplex or flow control state to any particular
2358 * values on physical ports, but force the CPU port
2359 * and all DSA ports to their maximum bandwidth and
2362 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2363 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2364 reg &= ~PORT_PCS_CTRL_UNFORCED;
2365 reg |= PORT_PCS_CTRL_FORCE_LINK |
2366 PORT_PCS_CTRL_LINK_UP |
2367 PORT_PCS_CTRL_DUPLEX_FULL |
2368 PORT_PCS_CTRL_FORCE_DUPLEX;
2369 if (mv88e6xxx_6065_family(ds))
2370 reg |= PORT_PCS_CTRL_100;
2372 reg |= PORT_PCS_CTRL_1000;
2374 reg |= PORT_PCS_CTRL_UNFORCED;
2377 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2378 PORT_PCS_CTRL, reg);
2383 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2384 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2385 * tunneling, determine priority by looking at 802.1p and IP
2386 * priority fields (IP prio has precedence), and set STP state
2389 * If this is the CPU link, use DSA or EDSA tagging depending
2390 * on which tagging mode was configured.
2392 * If this is a link to another switch, use DSA tagging mode.
2394 * If this is the upstream port for this switch, enable
2395 * forwarding of unknown unicasts and multicasts.
2398 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2399 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2400 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2401 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2402 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2403 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2404 PORT_CONTROL_STATE_FORWARDING;
2405 if (dsa_is_cpu_port(ds, port)) {
2406 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2407 reg |= PORT_CONTROL_DSA_TAG;
2408 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2409 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2410 mv88e6xxx_6320_family(ds)) {
2411 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2412 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2414 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2415 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2416 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2419 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2420 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2421 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2422 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2423 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2424 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2427 if (dsa_is_dsa_port(ds, port)) {
2428 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2429 reg |= PORT_CONTROL_DSA_TAG;
2430 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2431 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2432 mv88e6xxx_6320_family(ds)) {
2433 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2436 if (port == dsa_upstream_port(ds))
2437 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2438 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2441 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2447 /* If this port is connected to a SerDes, make sure the SerDes is not
2450 if (mv88e6xxx_6352_family(ds)) {
2451 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2454 ret &= PORT_STATUS_CMODE_MASK;
2455 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2456 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2457 (ret == PORT_STATUS_CMODE_SGMII)) {
2458 ret = mv88e6xxx_power_on_serdes(ds);
2464 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2465 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2466 * untagged frames on this port, do a destination address lookup on all
2467 * received packets as usual, disable ARP mirroring and don't send a
2468 * copy of all transmitted/received frames on this port to the CPU.
2471 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2472 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2473 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds) ||
2474 mv88e6xxx_6185_family(ds))
2475 reg = PORT_CONTROL_2_MAP_DA;
2477 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2478 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2479 reg |= PORT_CONTROL_2_JUMBO_10240;
2481 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2482 /* Set the upstream port this port should use */
2483 reg |= dsa_upstream_port(ds);
2484 /* enable forwarding of unknown multicast addresses to
2487 if (port == dsa_upstream_port(ds))
2488 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2491 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2494 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2495 PORT_CONTROL_2, reg);
2500 /* Port Association Vector: when learning source addresses
2501 * of packets, add the address to the address database using
2502 * a port bitmap that has only the bit for this port set and
2503 * the other bits clear.
2506 /* Disable learning for DSA and CPU ports */
2507 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2508 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2510 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2514 /* Egress rate control 2: disable egress rate control. */
2515 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2520 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2521 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2522 mv88e6xxx_6320_family(ds)) {
2523 /* Do not limit the period of time that this port can
2524 * be paused for by the remote end or the period of
2525 * time that this port can pause the remote end.
2527 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2528 PORT_PAUSE_CTRL, 0x0000);
2532 /* Port ATU control: disable limiting the number of
2533 * address database entries that this port is allowed
2536 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2537 PORT_ATU_CONTROL, 0x0000);
2538 /* Priority Override: disable DA, SA and VTU priority
2541 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2542 PORT_PRI_OVERRIDE, 0x0000);
2546 /* Port Ethertype: use the Ethertype DSA Ethertype
2549 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2550 PORT_ETH_TYPE, ETH_P_EDSA);
2553 /* Tag Remap: use an identity 802.1p prio -> switch
2556 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2557 PORT_TAG_REGMAP_0123, 0x3210);
2561 /* Tag Remap 2: use an identity 802.1p prio -> switch
2564 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2565 PORT_TAG_REGMAP_4567, 0x7654);
2570 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2571 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2572 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2573 mv88e6xxx_6320_family(ds)) {
2574 /* Rate Control: disable ingress rate limiting. */
2575 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2576 PORT_RATE_CONTROL, 0x0001);
2581 /* Port Control 1: disable trunking, disable sending
2582 * learning messages to this port.
2584 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2588 /* Port based VLAN map: give each port its own address
2589 * database, and allow bidirectional communication between the
2590 * CPU and DSA port(s), and the other ports.
2592 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2596 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2600 /* Default VLAN ID and priority: don't set a default VLAN
2601 * ID, and set the default packet priority to zero.
2603 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2606 mutex_unlock(&ps->smi_mutex);
2610 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2612 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2616 for (i = 0; i < ps->info->num_ports; i++) {
2617 ret = mv88e6xxx_setup_port(ds, i);
2624 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2626 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2629 mutex_init(&ps->smi_mutex);
2631 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2636 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2638 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2642 mutex_lock(&ps->smi_mutex);
2643 /* Set the default address aging time to 5 minutes, and
2644 * enable address learn messages to be sent to all message
2647 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
2648 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2652 /* Configure the IP ToS mapping registers. */
2653 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2656 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2659 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2662 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2665 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2668 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2671 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2674 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2678 /* Configure the IEEE 802.1p priority mapping register. */
2679 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2683 /* Send all frames with destination addresses matching
2684 * 01:80:c2:00:00:0x to the CPU port.
2686 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2690 /* Ignore removed tag data on doubly tagged packets, disable
2691 * flow control messages, force flow control priority to the
2692 * highest, and send all special multicast frames to the CPU
2693 * port at the highest priority.
2695 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2696 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2697 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2701 /* Program the DSA routing table. */
2702 for (i = 0; i < 32; i++) {
2705 if (ds->pd->rtable &&
2706 i != ds->index && i < ds->dst->pd->nr_chips)
2707 nexthop = ds->pd->rtable[i] & 0x1f;
2709 err = _mv88e6xxx_reg_write(
2711 GLOBAL2_DEVICE_MAPPING,
2712 GLOBAL2_DEVICE_MAPPING_UPDATE |
2713 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
2718 /* Clear all trunk masks. */
2719 for (i = 0; i < 8; i++) {
2720 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2722 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2723 ((1 << ps->info->num_ports) - 1));
2728 /* Clear all trunk mappings. */
2729 for (i = 0; i < 16; i++) {
2730 err = _mv88e6xxx_reg_write(
2732 GLOBAL2_TRUNK_MAPPING,
2733 GLOBAL2_TRUNK_MAPPING_UPDATE |
2734 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2739 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2740 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2741 mv88e6xxx_6320_family(ds)) {
2742 /* Send all frames with destination addresses matching
2743 * 01:80:c2:00:00:2x to the CPU port.
2745 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2746 GLOBAL2_MGMT_EN_2X, 0xffff);
2750 /* Initialise cross-chip port VLAN table to reset
2753 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2754 GLOBAL2_PVT_ADDR, 0x9000);
2758 /* Clear the priority override table. */
2759 for (i = 0; i < 16; i++) {
2760 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2761 GLOBAL2_PRIO_OVERRIDE,
2768 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2769 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2770 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2771 mv88e6xxx_6320_family(ds)) {
2772 /* Disable ingress rate limiting by resetting all
2773 * ingress rate limit registers to their initial
2776 for (i = 0; i < ps->info->num_ports; i++) {
2777 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL2,
2785 /* Clear the statistics counters for all ports */
2786 err = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
2787 GLOBAL_STATS_OP_FLUSH_ALL);
2791 /* Wait for the flush to complete. */
2792 err = _mv88e6xxx_stats_wait(ds);
2796 /* Clear all ATU entries */
2797 err = _mv88e6xxx_atu_flush(ds, 0, true);
2801 /* Clear all the VTU and STU entries */
2802 err = _mv88e6xxx_vtu_stu_flush(ds);
2804 mutex_unlock(&ps->smi_mutex);
2809 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2811 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2812 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2813 struct gpio_desc *gpiod = ds->pd->reset;
2814 unsigned long timeout;
2818 mutex_lock(&ps->smi_mutex);
2820 /* Set all ports to the disabled state. */
2821 for (i = 0; i < ps->info->num_ports; i++) {
2822 ret = _mv88e6xxx_reg_read(ds, REG_PORT(i), PORT_CONTROL);
2826 ret = _mv88e6xxx_reg_write(ds, REG_PORT(i), PORT_CONTROL,
2832 /* Wait for transmit queues to drain. */
2833 usleep_range(2000, 4000);
2835 /* If there is a gpio connected to the reset pin, toggle it */
2837 gpiod_set_value_cansleep(gpiod, 1);
2838 usleep_range(10000, 20000);
2839 gpiod_set_value_cansleep(gpiod, 0);
2840 usleep_range(10000, 20000);
2843 /* Reset the switch. Keep the PPU active if requested. The PPU
2844 * needs to be active to support indirect phy register access
2845 * through global registers 0x18 and 0x19.
2848 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc000);
2850 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, 0x04, 0xc400);
2854 /* Wait up to one second for reset to complete. */
2855 timeout = jiffies + 1 * HZ;
2856 while (time_before(jiffies, timeout)) {
2857 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, 0x00);
2861 if ((ret & is_reset) == is_reset)
2863 usleep_range(1000, 2000);
2865 if (time_after(jiffies, timeout))
2870 mutex_unlock(&ps->smi_mutex);
2875 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2877 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2880 mutex_lock(&ps->smi_mutex);
2881 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
2882 mutex_unlock(&ps->smi_mutex);
2887 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2890 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2893 mutex_lock(&ps->smi_mutex);
2894 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
2895 mutex_unlock(&ps->smi_mutex);
2900 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2902 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2904 if (port >= 0 && port < ps->info->num_ports)
2910 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2912 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2913 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2919 mutex_lock(&ps->smi_mutex);
2920 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2921 mutex_unlock(&ps->smi_mutex);
2926 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2928 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2929 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2935 mutex_lock(&ps->smi_mutex);
2936 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2937 mutex_unlock(&ps->smi_mutex);
2942 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2944 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2945 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2951 mutex_lock(&ps->smi_mutex);
2952 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2953 mutex_unlock(&ps->smi_mutex);
2958 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2961 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2962 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2968 mutex_lock(&ps->smi_mutex);
2969 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2970 mutex_unlock(&ps->smi_mutex);
2974 #ifdef CONFIG_NET_DSA_HWMON
2976 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2978 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2984 mutex_lock(&ps->smi_mutex);
2986 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2990 /* Enable temperature sensor */
2991 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2995 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2999 /* Wait for temperature to stabilize */
3000 usleep_range(10000, 12000);
3002 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
3008 /* Disable temperature sensor */
3009 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
3013 *temp = ((val & 0x1f) - 5) * 5;
3016 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
3017 mutex_unlock(&ps->smi_mutex);
3021 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3023 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3028 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3032 *temp = (ret & 0xff) - 25;
3037 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3039 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
3040 return mv88e63xx_get_temp(ds, temp);
3042 return mv88e61xx_get_temp(ds, temp);
3045 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3047 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3050 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3055 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3059 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3064 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3066 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3069 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3072 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3075 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3076 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3077 (ret & 0xe0ff) | (temp << 8));
3080 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3082 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3085 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3090 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3094 *alarm = !!(ret & 0x40);
3098 #endif /* CONFIG_NET_DSA_HWMON */
3100 static const struct mv88e6xxx_info *
3101 mv88e6xxx_lookup_info(unsigned int prod_num, const struct mv88e6xxx_info *table,
3106 for (i = 0; i < num; ++i)
3107 if (table[i].prod_num == prod_num)
3113 const char *mv88e6xxx_drv_probe(struct device *dsa_dev, struct device *host_dev,
3114 int sw_addr, void **priv,
3115 const struct mv88e6xxx_info *table,
3118 const struct mv88e6xxx_info *info;
3119 struct mv88e6xxx_priv_state *ps;
3120 struct mii_bus *bus;
3122 int id, prod_num, rev;
3124 bus = dsa_host_dev_to_mii_bus(host_dev);
3128 id = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3132 prod_num = (id & 0xfff0) >> 4;
3135 info = mv88e6xxx_lookup_info(prod_num, table, num);
3141 ps = devm_kzalloc(dsa_dev, sizeof(*ps), GFP_KERNEL);
3146 ps->sw_addr = sw_addr;
3148 ps->id = id & 0xfff0;
3152 dev_info(&ps->bus->dev, "switch 0x%x probed: %s, revision %u\n",
3153 prod_num, name, rev);
3158 static int __init mv88e6xxx_init(void)
3160 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3161 register_switch_driver(&mv88e6131_switch_driver);
3163 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3164 register_switch_driver(&mv88e6123_switch_driver);
3166 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3167 register_switch_driver(&mv88e6352_switch_driver);
3169 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3170 register_switch_driver(&mv88e6171_switch_driver);
3174 module_init(mv88e6xxx_init);
3176 static void __exit mv88e6xxx_cleanup(void)
3178 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3179 unregister_switch_driver(&mv88e6171_switch_driver);
3181 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3182 unregister_switch_driver(&mv88e6352_switch_driver);
3184 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3185 unregister_switch_driver(&mv88e6123_switch_driver);
3187 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3188 unregister_switch_driver(&mv88e6131_switch_driver);
3191 module_exit(mv88e6xxx_cleanup);
3193 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3194 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3195 MODULE_LICENSE("GPL");