2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
133 return mdiobus_write_nested(bus, addr, reg, val);
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
201 for (i = 0; i < 6; i++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
240 unsigned long timeout;
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
261 unsigned long timeout;
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
280 struct mv88e6xxx_priv_state *ps;
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
296 schedule_work(&ps->ppu_work);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
304 mutex_lock(&ps->ppu_mutex);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
314 mutex_unlock(&ps->ppu_mutex);
317 ps->ppu_disabled = 1;
319 del_timer(&ps->ppu_timer);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
350 ret = mv88e6xxx_ppu_access_get(ds);
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
364 ret = mv88e6xxx_ppu_access_get(ds);
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
485 static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
487 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
489 /* The following devices have 4-bit identifiers for 16 databases */
490 if (ps->id == PORT_SWITCH_ID_6061)
493 /* The following devices have 6-bit identifiers for 64 databases */
494 if (ps->id == PORT_SWITCH_ID_6065)
497 /* The following devices have 8-bit identifiers for 256 databases */
498 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
501 /* The following devices have 12-bit identifiers for 4096 databases */
502 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
503 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
509 static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
511 /* Does the device have dedicated FID registers for ATU and VTU ops? */
512 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
513 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
519 static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
521 /* Does the device have STU and dedicated SID registers for VTU ops? */
522 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
523 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
529 /* We expect the switch to perform auto negotiation if there is a real
530 * phy. However, in the case of a fixed link phy, we force the port
531 * settings from the fixed link settings.
533 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
534 struct phy_device *phydev)
536 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
540 if (!phy_is_pseudo_fixed_link(phydev))
543 mutex_lock(&ps->smi_mutex);
545 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
549 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
550 PORT_PCS_CTRL_FORCE_LINK |
551 PORT_PCS_CTRL_DUPLEX_FULL |
552 PORT_PCS_CTRL_FORCE_DUPLEX |
553 PORT_PCS_CTRL_UNFORCED);
555 reg |= PORT_PCS_CTRL_FORCE_LINK;
557 reg |= PORT_PCS_CTRL_LINK_UP;
559 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
562 switch (phydev->speed) {
564 reg |= PORT_PCS_CTRL_1000;
567 reg |= PORT_PCS_CTRL_100;
570 reg |= PORT_PCS_CTRL_10;
573 pr_info("Unknown speed");
577 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
578 if (phydev->duplex == DUPLEX_FULL)
579 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
581 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
582 (port >= ps->num_ports - 2)) {
583 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
584 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
585 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
586 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
587 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
588 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
589 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
591 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
594 mutex_unlock(&ps->smi_mutex);
597 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
602 for (i = 0; i < 10; i++) {
603 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
604 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
611 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
615 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
616 port = (port + 1) << 5;
618 /* Snapshot the hardware statistics counters for this port. */
619 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
620 GLOBAL_STATS_OP_CAPTURE_PORT |
621 GLOBAL_STATS_OP_HIST_RX_TX | port);
625 /* Wait for the snapshotting to complete. */
626 ret = _mv88e6xxx_stats_wait(ds);
633 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
640 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
641 GLOBAL_STATS_OP_READ_CAPTURED |
642 GLOBAL_STATS_OP_HIST_RX_TX | stat);
646 ret = _mv88e6xxx_stats_wait(ds);
650 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
656 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
663 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
664 { "in_good_octets", 8, 0x00, BANK0, },
665 { "in_bad_octets", 4, 0x02, BANK0, },
666 { "in_unicast", 4, 0x04, BANK0, },
667 { "in_broadcasts", 4, 0x06, BANK0, },
668 { "in_multicasts", 4, 0x07, BANK0, },
669 { "in_pause", 4, 0x16, BANK0, },
670 { "in_undersize", 4, 0x18, BANK0, },
671 { "in_fragments", 4, 0x19, BANK0, },
672 { "in_oversize", 4, 0x1a, BANK0, },
673 { "in_jabber", 4, 0x1b, BANK0, },
674 { "in_rx_error", 4, 0x1c, BANK0, },
675 { "in_fcs_error", 4, 0x1d, BANK0, },
676 { "out_octets", 8, 0x0e, BANK0, },
677 { "out_unicast", 4, 0x10, BANK0, },
678 { "out_broadcasts", 4, 0x13, BANK0, },
679 { "out_multicasts", 4, 0x12, BANK0, },
680 { "out_pause", 4, 0x15, BANK0, },
681 { "excessive", 4, 0x11, BANK0, },
682 { "collisions", 4, 0x1e, BANK0, },
683 { "deferred", 4, 0x05, BANK0, },
684 { "single", 4, 0x14, BANK0, },
685 { "multiple", 4, 0x17, BANK0, },
686 { "out_fcs_error", 4, 0x03, BANK0, },
687 { "late", 4, 0x1f, BANK0, },
688 { "hist_64bytes", 4, 0x08, BANK0, },
689 { "hist_65_127bytes", 4, 0x09, BANK0, },
690 { "hist_128_255bytes", 4, 0x0a, BANK0, },
691 { "hist_256_511bytes", 4, 0x0b, BANK0, },
692 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
693 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
694 { "sw_in_discards", 4, 0x10, PORT, },
695 { "sw_in_filtered", 2, 0x12, PORT, },
696 { "sw_out_filtered", 2, 0x13, PORT, },
697 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
704 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
705 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
706 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
707 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
708 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
709 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
710 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
711 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
712 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
713 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
714 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
715 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
716 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
717 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
718 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
719 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
720 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
721 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
722 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
725 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
726 struct mv88e6xxx_hw_stat *stat)
728 switch (stat->type) {
732 return mv88e6xxx_6320_family(ds);
734 return mv88e6xxx_6095_family(ds) ||
735 mv88e6xxx_6185_family(ds) ||
736 mv88e6xxx_6097_family(ds) ||
737 mv88e6xxx_6165_family(ds) ||
738 mv88e6xxx_6351_family(ds) ||
739 mv88e6xxx_6352_family(ds);
744 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
745 struct mv88e6xxx_hw_stat *s,
755 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
760 if (s->sizeof_stat == 4) {
761 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
770 _mv88e6xxx_stats_read(ds, s->reg, &low);
771 if (s->sizeof_stat == 8)
772 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
774 value = (((u64)high) << 16) | low;
778 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
780 struct mv88e6xxx_hw_stat *stat;
783 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
784 stat = &mv88e6xxx_hw_stats[i];
785 if (mv88e6xxx_has_stat(ds, stat)) {
786 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
793 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
795 struct mv88e6xxx_hw_stat *stat;
798 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
799 stat = &mv88e6xxx_hw_stats[i];
800 if (mv88e6xxx_has_stat(ds, stat))
807 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
808 int port, uint64_t *data)
810 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
811 struct mv88e6xxx_hw_stat *stat;
815 mutex_lock(&ps->smi_mutex);
817 ret = _mv88e6xxx_stats_snapshot(ds, port);
819 mutex_unlock(&ps->smi_mutex);
822 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
823 stat = &mv88e6xxx_hw_stats[i];
824 if (mv88e6xxx_has_stat(ds, stat)) {
825 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
830 mutex_unlock(&ps->smi_mutex);
833 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
835 return 32 * sizeof(u16);
838 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
839 struct ethtool_regs *regs, void *_p)
846 memset(p, 0xff, 32 * sizeof(u16));
848 for (i = 0; i < 32; i++) {
851 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
857 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
860 unsigned long timeout = jiffies + HZ / 10;
862 while (time_before(jiffies, timeout)) {
865 ret = _mv88e6xxx_reg_read(ds, reg, offset);
871 usleep_range(1000, 2000);
876 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
878 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
881 mutex_lock(&ps->smi_mutex);
882 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
883 mutex_unlock(&ps->smi_mutex);
888 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
890 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
891 GLOBAL2_SMI_OP_BUSY);
894 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
896 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
897 GLOBAL2_EEPROM_OP_LOAD);
900 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
902 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
903 GLOBAL2_EEPROM_OP_BUSY);
906 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
908 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
912 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
917 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
918 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
923 ret = _mv88e6xxx_phy_wait(ds);
927 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
930 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
935 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
939 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
940 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
943 return _mv88e6xxx_phy_wait(ds);
946 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
951 mutex_lock(&ps->smi_mutex);
953 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
957 e->eee_enabled = !!(reg & 0x0200);
958 e->tx_lpi_enabled = !!(reg & 0x0100);
960 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
964 e->eee_active = !!(reg & PORT_STATUS_EEE);
968 mutex_unlock(&ps->smi_mutex);
972 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
973 struct phy_device *phydev, struct ethtool_eee *e)
975 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
979 mutex_lock(&ps->smi_mutex);
981 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
988 if (e->tx_lpi_enabled)
991 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
993 mutex_unlock(&ps->smi_mutex);
998 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
1002 if (mv88e6xxx_has_fid_reg(ds)) {
1003 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1006 } else if (mv88e6xxx_num_databases(ds) == 256) {
1007 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1008 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1012 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1014 ((fid << 8) & 0xf000));
1018 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */
1022 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1026 return _mv88e6xxx_atu_wait(ds);
1029 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
1030 struct mv88e6xxx_atu_entry *entry)
1032 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1034 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1035 unsigned int mask, shift;
1038 data |= GLOBAL_ATU_DATA_TRUNK;
1039 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1040 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1042 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1043 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1046 data |= (entry->portv_trunkid << shift) & mask;
1049 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1052 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1053 struct mv88e6xxx_atu_entry *entry,
1059 err = _mv88e6xxx_atu_wait(ds);
1063 err = _mv88e6xxx_atu_data_write(ds, entry);
1068 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1069 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1071 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1072 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1075 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
1078 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1080 struct mv88e6xxx_atu_entry entry = {
1082 .state = 0, /* EntryState bits must be 0 */
1085 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1088 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1089 int to_port, bool static_too)
1091 struct mv88e6xxx_atu_entry entry = {
1096 /* EntryState bits must be 0xF */
1097 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1099 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1100 entry.portv_trunkid = (to_port & 0x0f) << 4;
1101 entry.portv_trunkid |= from_port & 0x0f;
1103 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1106 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1109 /* Destination port 0xF means remove the entries */
1110 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1113 static const char * const mv88e6xxx_port_state_names[] = {
1114 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1115 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1116 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1117 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1120 static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
1125 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1129 oldstate = reg & PORT_CONTROL_STATE_MASK;
1131 if (oldstate != state) {
1132 /* Flush forwarding database if we're moving a port
1133 * from Learning or Forwarding state to Disabled or
1134 * Blocking or Listening state.
1136 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1137 oldstate == PORT_CONTROL_STATE_FORWARDING)
1138 && (state == PORT_CONTROL_STATE_DISABLED ||
1139 state == PORT_CONTROL_STATE_BLOCKING)) {
1140 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1145 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1146 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1151 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1152 mv88e6xxx_port_state_names[state],
1153 mv88e6xxx_port_state_names[oldstate]);
1159 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1161 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1162 struct net_device *bridge = ps->ports[port].bridge_dev;
1163 const u16 mask = (1 << ps->num_ports) - 1;
1164 u16 output_ports = 0;
1168 /* allow CPU port or DSA link(s) to send frames to every port */
1169 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1170 output_ports = mask;
1172 for (i = 0; i < ps->num_ports; ++i) {
1173 /* allow sending frames to every group member */
1174 if (bridge && ps->ports[i].bridge_dev == bridge)
1175 output_ports |= BIT(i);
1177 /* allow sending frames to CPU port and DSA link(s) */
1178 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1179 output_ports |= BIT(i);
1183 /* prevent frames from going back out of the port they came in on */
1184 output_ports &= ~BIT(port);
1186 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1191 reg |= output_ports & mask;
1193 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1196 void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1198 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1202 case BR_STATE_DISABLED:
1203 stp_state = PORT_CONTROL_STATE_DISABLED;
1205 case BR_STATE_BLOCKING:
1206 case BR_STATE_LISTENING:
1207 stp_state = PORT_CONTROL_STATE_BLOCKING;
1209 case BR_STATE_LEARNING:
1210 stp_state = PORT_CONTROL_STATE_LEARNING;
1212 case BR_STATE_FORWARDING:
1214 stp_state = PORT_CONTROL_STATE_FORWARDING;
1218 /* mv88e6xxx_port_stp_state_set may be called with softirqs disabled,
1219 * so we can not update the port state directly but need to schedule it.
1221 ps->ports[port].state = stp_state;
1222 set_bit(port, ps->port_state_update_mask);
1223 schedule_work(&ps->bridge_work);
1226 static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1232 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1236 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1239 ret &= ~PORT_DEFAULT_VLAN_MASK;
1240 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1242 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1243 PORT_DEFAULT_VLAN, ret);
1247 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1257 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1259 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1262 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1264 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
1267 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1269 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1270 GLOBAL_VTU_OP_BUSY);
1273 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1277 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1281 return _mv88e6xxx_vtu_wait(ds);
1284 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1288 ret = _mv88e6xxx_vtu_wait(ds);
1292 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1295 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1296 struct mv88e6xxx_vtu_stu_entry *entry,
1297 unsigned int nibble_offset)
1299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1304 for (i = 0; i < 3; ++i) {
1305 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1306 GLOBAL_VTU_DATA_0_3 + i);
1313 for (i = 0; i < ps->num_ports; ++i) {
1314 unsigned int shift = (i % 4) * 4 + nibble_offset;
1315 u16 reg = regs[i / 4];
1317 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1323 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1324 struct mv88e6xxx_vtu_stu_entry *entry,
1325 unsigned int nibble_offset)
1327 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1328 u16 regs[3] = { 0 };
1332 for (i = 0; i < ps->num_ports; ++i) {
1333 unsigned int shift = (i % 4) * 4 + nibble_offset;
1334 u8 data = entry->data[i];
1336 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1339 for (i = 0; i < 3; ++i) {
1340 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1341 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1349 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1351 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1352 vid & GLOBAL_VTU_VID_MASK);
1355 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1356 struct mv88e6xxx_vtu_stu_entry *entry)
1358 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1361 ret = _mv88e6xxx_vtu_wait(ds);
1365 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1369 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1373 next.vid = ret & GLOBAL_VTU_VID_MASK;
1374 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1377 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1381 if (mv88e6xxx_has_fid_reg(ds)) {
1382 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1387 next.fid = ret & GLOBAL_VTU_FID_MASK;
1388 } else if (mv88e6xxx_num_databases(ds) == 256) {
1389 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1390 * VTU DBNum[3:0] are located in VTU Operation 3:0
1392 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1397 next.fid = (ret & 0xf00) >> 4;
1398 next.fid |= ret & 0xf;
1401 if (mv88e6xxx_has_stu(ds)) {
1402 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1407 next.sid = ret & GLOBAL_VTU_SID_MASK;
1415 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1416 struct switchdev_obj_port_vlan *vlan,
1417 int (*cb)(struct switchdev_obj *obj))
1419 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1420 struct mv88e6xxx_vtu_stu_entry next;
1424 mutex_lock(&ps->smi_mutex);
1426 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1430 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1435 err = _mv88e6xxx_vtu_getnext(ds, &next);
1442 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1445 /* reinit and dump this VLAN obj */
1446 vlan->vid_begin = vlan->vid_end = next.vid;
1449 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1450 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1452 if (next.vid == pvid)
1453 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1455 err = cb(&vlan->obj);
1458 } while (next.vid < GLOBAL_VTU_VID_MASK);
1461 mutex_unlock(&ps->smi_mutex);
1466 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1467 struct mv88e6xxx_vtu_stu_entry *entry)
1469 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1473 ret = _mv88e6xxx_vtu_wait(ds);
1480 /* Write port member tags */
1481 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1485 if (mv88e6xxx_has_stu(ds)) {
1486 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1487 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1492 if (mv88e6xxx_has_fid_reg(ds)) {
1493 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1494 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1497 } else if (mv88e6xxx_num_databases(ds) == 256) {
1498 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1499 * VTU DBNum[3:0] are located in VTU Operation 3:0
1501 op |= (entry->fid & 0xf0) << 8;
1502 op |= entry->fid & 0xf;
1505 reg = GLOBAL_VTU_VID_VALID;
1507 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1508 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1512 return _mv88e6xxx_vtu_cmd(ds, op);
1515 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1516 struct mv88e6xxx_vtu_stu_entry *entry)
1518 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1521 ret = _mv88e6xxx_vtu_wait(ds);
1525 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1526 sid & GLOBAL_VTU_SID_MASK);
1530 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1534 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1538 next.sid = ret & GLOBAL_VTU_SID_MASK;
1540 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1544 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1547 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1556 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1557 struct mv88e6xxx_vtu_stu_entry *entry)
1562 ret = _mv88e6xxx_vtu_wait(ds);
1569 /* Write port states */
1570 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1574 reg = GLOBAL_VTU_VID_VALID;
1576 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1580 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1581 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1585 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1588 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1595 if (mv88e6xxx_num_databases(ds) == 4096)
1597 else if (mv88e6xxx_num_databases(ds) == 256)
1602 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1603 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1607 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1610 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1611 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1613 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1619 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1620 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1624 fid |= (ret & upper_mask) << 4;
1628 ret |= (*new >> 4) & upper_mask;
1630 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1635 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1644 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1646 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1649 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1651 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1654 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1656 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1657 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1658 struct mv88e6xxx_vtu_stu_entry vlan;
1661 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1663 /* Set every FID bit used by the (un)bridged ports */
1664 for (i = 0; i < ps->num_ports; ++i) {
1665 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1669 set_bit(*fid, fid_bitmap);
1672 /* Set every FID bit used by the VLAN entries */
1673 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1678 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1685 set_bit(vlan.fid, fid_bitmap);
1686 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1688 /* The reset value 0x000 is used to indicate that multiple address
1689 * databases are not needed. Return the next positive available.
1691 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1692 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
1695 /* Clear the database */
1696 return _mv88e6xxx_atu_flush(ds, *fid, true);
1699 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1700 struct mv88e6xxx_vtu_stu_entry *entry)
1702 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1703 struct mv88e6xxx_vtu_stu_entry vlan = {
1709 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1713 /* exclude all ports except the CPU and DSA ports */
1714 for (i = 0; i < ps->num_ports; ++i)
1715 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1716 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1717 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1719 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1720 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1721 struct mv88e6xxx_vtu_stu_entry vstp;
1723 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1724 * implemented, only one STU entry is needed to cover all VTU
1725 * entries. Thus, validate the SID 0.
1728 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1732 if (vstp.sid != vlan.sid || !vstp.valid) {
1733 memset(&vstp, 0, sizeof(vstp));
1735 vstp.sid = vlan.sid;
1737 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1747 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1748 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1755 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1759 err = _mv88e6xxx_vtu_getnext(ds, entry);
1763 if (entry->vid != vid || !entry->valid) {
1766 /* -ENOENT would've been more appropriate, but switchdev expects
1767 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1770 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1776 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1777 u16 vid_begin, u16 vid_end)
1779 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1780 struct mv88e6xxx_vtu_stu_entry vlan;
1786 mutex_lock(&ps->smi_mutex);
1788 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1793 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1800 if (vlan.vid > vid_end)
1803 for (i = 0; i < ps->num_ports; ++i) {
1804 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1808 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1811 if (ps->ports[i].bridge_dev ==
1812 ps->ports[port].bridge_dev)
1813 break; /* same bridge, check next VLAN */
1815 netdev_warn(ds->ports[port],
1816 "hardware VLAN %d already used by %s\n",
1818 netdev_name(ps->ports[i].bridge_dev));
1822 } while (vlan.vid < vid_end);
1825 mutex_unlock(&ps->smi_mutex);
1830 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1831 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1832 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1833 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1834 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1837 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1838 bool vlan_filtering)
1840 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1841 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1842 PORT_CONTROL_2_8021Q_DISABLED;
1845 mutex_lock(&ps->smi_mutex);
1847 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1851 old = ret & PORT_CONTROL_2_8021Q_MASK;
1854 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1855 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1857 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1862 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1863 mv88e6xxx_port_8021q_mode_names[new],
1864 mv88e6xxx_port_8021q_mode_names[old]);
1869 mutex_unlock(&ps->smi_mutex);
1874 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1875 const struct switchdev_obj_port_vlan *vlan,
1876 struct switchdev_trans *trans)
1880 /* If the requested port doesn't belong to the same bridge as the VLAN
1881 * members, do not support it (yet) and fallback to software VLAN.
1883 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1888 /* We don't need any dynamic resource from the kernel (yet),
1889 * so skip the prepare phase.
1894 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1897 struct mv88e6xxx_vtu_stu_entry vlan;
1900 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1904 vlan.data[port] = untagged ?
1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1908 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1911 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1912 const struct switchdev_obj_port_vlan *vlan,
1913 struct switchdev_trans *trans)
1915 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1921 mutex_lock(&ps->smi_mutex);
1923 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1924 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1929 /* no PVID with ranges, otherwise it's a bug */
1931 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1933 mutex_unlock(&ps->smi_mutex);
1938 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1940 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1941 struct mv88e6xxx_vtu_stu_entry vlan;
1944 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1948 /* Tell switchdev if this VLAN is handled in software */
1949 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1952 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1954 /* keep the VLAN unless all ports are excluded */
1956 for (i = 0; i < ps->num_ports; ++i) {
1957 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1960 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1966 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1970 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1973 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1974 const struct switchdev_obj_port_vlan *vlan)
1976 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1980 mutex_lock(&ps->smi_mutex);
1982 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1986 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1987 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1992 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1999 mutex_unlock(&ps->smi_mutex);
2004 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
2005 const unsigned char *addr)
2009 for (i = 0; i < 3; i++) {
2010 ret = _mv88e6xxx_reg_write(
2011 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2012 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2020 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
2024 for (i = 0; i < 3; i++) {
2025 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
2026 GLOBAL_ATU_MAC_01 + i);
2029 addr[i * 2] = ret >> 8;
2030 addr[i * 2 + 1] = ret & 0xff;
2036 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
2037 struct mv88e6xxx_atu_entry *entry)
2041 ret = _mv88e6xxx_atu_wait(ds);
2045 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
2049 ret = _mv88e6xxx_atu_data_write(ds, entry);
2053 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2056 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2057 const unsigned char *addr, u16 vid,
2060 struct mv88e6xxx_atu_entry entry = { 0 };
2061 struct mv88e6xxx_vtu_stu_entry vlan;
2064 /* Null VLAN ID corresponds to the port private database */
2066 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2068 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
2072 entry.fid = vlan.fid;
2073 entry.state = state;
2074 ether_addr_copy(entry.mac, addr);
2075 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2076 entry.trunk = false;
2077 entry.portv_trunkid = BIT(port);
2080 return _mv88e6xxx_atu_load(ds, &entry);
2083 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2084 const struct switchdev_obj_port_fdb *fdb,
2085 struct switchdev_trans *trans)
2087 /* We don't need any dynamic resource from the kernel (yet),
2088 * so skip the prepare phase.
2093 void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2094 const struct switchdev_obj_port_fdb *fdb,
2095 struct switchdev_trans *trans)
2097 int state = is_multicast_ether_addr(fdb->addr) ?
2098 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2099 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2100 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2102 mutex_lock(&ps->smi_mutex);
2103 if (_mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state))
2104 netdev_err(ds->ports[port], "failed to load MAC address\n");
2105 mutex_unlock(&ps->smi_mutex);
2108 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2109 const struct switchdev_obj_port_fdb *fdb)
2111 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2114 mutex_lock(&ps->smi_mutex);
2115 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
2116 GLOBAL_ATU_DATA_STATE_UNUSED);
2117 mutex_unlock(&ps->smi_mutex);
2122 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
2123 struct mv88e6xxx_atu_entry *entry)
2125 struct mv88e6xxx_atu_entry next = { 0 };
2130 ret = _mv88e6xxx_atu_wait(ds);
2134 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2138 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2142 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2146 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2147 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2148 unsigned int mask, shift;
2150 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2152 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2153 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2156 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2157 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2160 next.portv_trunkid = (ret & mask) >> shift;
2167 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2169 struct switchdev_obj_port_fdb *fdb,
2170 int (*cb)(struct switchdev_obj *obj))
2172 struct mv88e6xxx_atu_entry addr = {
2173 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2177 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2182 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2186 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2189 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2190 bool is_static = addr.state ==
2191 (is_multicast_ether_addr(addr.mac) ?
2192 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2193 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2196 ether_addr_copy(fdb->addr, addr.mac);
2197 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2199 err = cb(&fdb->obj);
2203 } while (!is_broadcast_ether_addr(addr.mac));
2208 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2209 struct switchdev_obj_port_fdb *fdb,
2210 int (*cb)(struct switchdev_obj *obj))
2212 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2213 struct mv88e6xxx_vtu_stu_entry vlan = {
2214 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2219 mutex_lock(&ps->smi_mutex);
2221 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2222 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2226 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2230 /* Dump VLANs' Filtering Information Databases */
2231 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2236 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2243 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2247 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2250 mutex_unlock(&ps->smi_mutex);
2255 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2256 struct net_device *bridge)
2258 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2262 mutex_lock(&ps->smi_mutex);
2264 /* Get or create the bridge FID and assign it to the port */
2265 for (i = 0; i < ps->num_ports; ++i)
2266 if (ps->ports[i].bridge_dev == bridge)
2269 if (i < ps->num_ports)
2270 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2272 err = _mv88e6xxx_fid_new(ds, &fid);
2276 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2280 /* Assign the bridge and remap each port's VLANTable */
2281 ps->ports[port].bridge_dev = bridge;
2283 for (i = 0; i < ps->num_ports; ++i) {
2284 if (ps->ports[i].bridge_dev == bridge) {
2285 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2292 mutex_unlock(&ps->smi_mutex);
2297 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2299 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2300 struct net_device *bridge = ps->ports[port].bridge_dev;
2304 mutex_lock(&ps->smi_mutex);
2306 /* Give the port a fresh Filtering Information Database */
2307 if (_mv88e6xxx_fid_new(ds, &fid) ||
2308 _mv88e6xxx_port_fid_set(ds, port, fid))
2309 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
2311 /* Unassign the bridge and remap each port's VLANTable */
2312 ps->ports[port].bridge_dev = NULL;
2314 for (i = 0; i < ps->num_ports; ++i)
2315 if (i == port || ps->ports[i].bridge_dev == bridge)
2316 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2317 netdev_warn(ds->ports[i], "failed to remap\n");
2319 mutex_unlock(&ps->smi_mutex);
2322 static void mv88e6xxx_bridge_work(struct work_struct *work)
2324 struct mv88e6xxx_priv_state *ps;
2325 struct dsa_switch *ds;
2328 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2329 ds = ((struct dsa_switch *)ps) - 1;
2331 mutex_lock(&ps->smi_mutex);
2333 for (port = 0; port < ps->num_ports; ++port)
2334 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2335 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2336 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2337 mv88e6xxx_port_state_names[ps->ports[port].state]);
2339 mutex_unlock(&ps->smi_mutex);
2342 static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2347 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2349 goto restore_page_0;
2351 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2353 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2358 static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2363 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2365 goto restore_page_0;
2367 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2369 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2374 static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2378 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2383 if (ret & BMCR_PDOWN) {
2385 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2386 PAGE_FIBER_SERDES, MII_BMCR,
2393 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2395 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2399 mutex_lock(&ps->smi_mutex);
2401 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2402 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2403 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2404 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2405 /* MAC Forcing register: don't force link, speed,
2406 * duplex or flow control state to any particular
2407 * values on physical ports, but force the CPU port
2408 * and all DSA ports to their maximum bandwidth and
2411 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2412 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2413 reg &= ~PORT_PCS_CTRL_UNFORCED;
2414 reg |= PORT_PCS_CTRL_FORCE_LINK |
2415 PORT_PCS_CTRL_LINK_UP |
2416 PORT_PCS_CTRL_DUPLEX_FULL |
2417 PORT_PCS_CTRL_FORCE_DUPLEX;
2418 if (mv88e6xxx_6065_family(ds))
2419 reg |= PORT_PCS_CTRL_100;
2421 reg |= PORT_PCS_CTRL_1000;
2423 reg |= PORT_PCS_CTRL_UNFORCED;
2426 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2427 PORT_PCS_CTRL, reg);
2432 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2433 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2434 * tunneling, determine priority by looking at 802.1p and IP
2435 * priority fields (IP prio has precedence), and set STP state
2438 * If this is the CPU link, use DSA or EDSA tagging depending
2439 * on which tagging mode was configured.
2441 * If this is a link to another switch, use DSA tagging mode.
2443 * If this is the upstream port for this switch, enable
2444 * forwarding of unknown unicasts and multicasts.
2447 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2448 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2449 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2450 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2451 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2452 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2453 PORT_CONTROL_STATE_FORWARDING;
2454 if (dsa_is_cpu_port(ds, port)) {
2455 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2456 reg |= PORT_CONTROL_DSA_TAG;
2457 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2458 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2459 mv88e6xxx_6320_family(ds)) {
2460 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2461 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2463 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2464 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2465 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2468 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2469 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2470 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2471 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2472 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2473 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2476 if (dsa_is_dsa_port(ds, port)) {
2477 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2478 reg |= PORT_CONTROL_DSA_TAG;
2479 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2480 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2481 mv88e6xxx_6320_family(ds)) {
2482 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2485 if (port == dsa_upstream_port(ds))
2486 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2487 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2490 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2496 /* If this port is connected to a SerDes, make sure the SerDes is not
2499 if (mv88e6xxx_6352_family(ds)) {
2500 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2503 ret &= PORT_STATUS_CMODE_MASK;
2504 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2505 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2506 (ret == PORT_STATUS_CMODE_SGMII)) {
2507 ret = mv88e6xxx_power_on_serdes(ds);
2513 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2514 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2515 * untagged frames on this port, do a destination address lookup on all
2516 * received packets as usual, disable ARP mirroring and don't send a
2517 * copy of all transmitted/received frames on this port to the CPU.
2520 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2521 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2522 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds) ||
2523 mv88e6xxx_6185_family(ds))
2524 reg = PORT_CONTROL_2_MAP_DA;
2526 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2527 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2528 reg |= PORT_CONTROL_2_JUMBO_10240;
2530 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2531 /* Set the upstream port this port should use */
2532 reg |= dsa_upstream_port(ds);
2533 /* enable forwarding of unknown multicast addresses to
2536 if (port == dsa_upstream_port(ds))
2537 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2540 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2543 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2544 PORT_CONTROL_2, reg);
2549 /* Port Association Vector: when learning source addresses
2550 * of packets, add the address to the address database using
2551 * a port bitmap that has only the bit for this port set and
2552 * the other bits clear.
2555 /* Disable learning for DSA and CPU ports */
2556 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2557 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2559 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2563 /* Egress rate control 2: disable egress rate control. */
2564 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2569 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2570 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2571 mv88e6xxx_6320_family(ds)) {
2572 /* Do not limit the period of time that this port can
2573 * be paused for by the remote end or the period of
2574 * time that this port can pause the remote end.
2576 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2577 PORT_PAUSE_CTRL, 0x0000);
2581 /* Port ATU control: disable limiting the number of
2582 * address database entries that this port is allowed
2585 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2586 PORT_ATU_CONTROL, 0x0000);
2587 /* Priority Override: disable DA, SA and VTU priority
2590 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2591 PORT_PRI_OVERRIDE, 0x0000);
2595 /* Port Ethertype: use the Ethertype DSA Ethertype
2598 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2599 PORT_ETH_TYPE, ETH_P_EDSA);
2602 /* Tag Remap: use an identity 802.1p prio -> switch
2605 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2606 PORT_TAG_REGMAP_0123, 0x3210);
2610 /* Tag Remap 2: use an identity 802.1p prio -> switch
2613 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2614 PORT_TAG_REGMAP_4567, 0x7654);
2619 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2620 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2621 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2622 mv88e6xxx_6320_family(ds)) {
2623 /* Rate Control: disable ingress rate limiting. */
2624 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2625 PORT_RATE_CONTROL, 0x0001);
2630 /* Port Control 1: disable trunking, disable sending
2631 * learning messages to this port.
2633 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2637 /* Port based VLAN map: give each port its own address
2638 * database, and allow bidirectional communication between the
2639 * CPU and DSA port(s), and the other ports.
2641 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2645 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2649 /* Default VLAN ID and priority: don't set a default VLAN
2650 * ID, and set the default packet priority to zero.
2652 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2655 mutex_unlock(&ps->smi_mutex);
2659 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2661 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2665 for (i = 0; i < ps->num_ports; i++) {
2666 ret = mv88e6xxx_setup_port(ds, i);
2673 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2675 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2677 mutex_init(&ps->smi_mutex);
2679 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2681 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2686 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2688 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2692 /* Set the default address aging time to 5 minutes, and
2693 * enable address learn messages to be sent to all message
2696 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2697 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2699 /* Configure the IP ToS mapping registers. */
2700 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2701 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2702 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2703 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2704 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2705 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2706 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2707 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2709 /* Configure the IEEE 802.1p priority mapping register. */
2710 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2712 /* Send all frames with destination addresses matching
2713 * 01:80:c2:00:00:0x to the CPU port.
2715 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2717 /* Ignore removed tag data on doubly tagged packets, disable
2718 * flow control messages, force flow control priority to the
2719 * highest, and send all special multicast frames to the CPU
2720 * port at the highest priority.
2722 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2723 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2724 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2726 /* Program the DSA routing table. */
2727 for (i = 0; i < 32; i++) {
2730 if (ds->pd->rtable &&
2731 i != ds->index && i < ds->dst->pd->nr_chips)
2732 nexthop = ds->pd->rtable[i] & 0x1f;
2734 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2735 GLOBAL2_DEVICE_MAPPING_UPDATE |
2736 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2740 /* Clear all trunk masks. */
2741 for (i = 0; i < 8; i++)
2742 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2743 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2744 ((1 << ps->num_ports) - 1));
2746 /* Clear all trunk mappings. */
2747 for (i = 0; i < 16; i++)
2748 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2749 GLOBAL2_TRUNK_MAPPING_UPDATE |
2750 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2752 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2753 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2754 mv88e6xxx_6320_family(ds)) {
2755 /* Send all frames with destination addresses matching
2756 * 01:80:c2:00:00:2x to the CPU port.
2758 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2760 /* Initialise cross-chip port VLAN table to reset
2763 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2765 /* Clear the priority override table. */
2766 for (i = 0; i < 16; i++)
2767 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2771 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2772 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2773 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2774 mv88e6xxx_6320_family(ds)) {
2775 /* Disable ingress rate limiting by resetting all
2776 * ingress rate limit registers to their initial
2779 for (i = 0; i < ps->num_ports; i++)
2780 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2784 /* Clear the statistics counters for all ports */
2785 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2787 /* Wait for the flush to complete. */
2788 mutex_lock(&ps->smi_mutex);
2789 ret = _mv88e6xxx_stats_wait(ds);
2793 /* Clear all ATU entries */
2794 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2798 /* Clear all the VTU and STU entries */
2799 ret = _mv88e6xxx_vtu_stu_flush(ds);
2801 mutex_unlock(&ps->smi_mutex);
2806 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2808 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2809 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2810 struct gpio_desc *gpiod = ds->pd->reset;
2811 unsigned long timeout;
2815 /* Set all ports to the disabled state. */
2816 for (i = 0; i < ps->num_ports; i++) {
2817 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2818 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2821 /* Wait for transmit queues to drain. */
2822 usleep_range(2000, 4000);
2824 /* If there is a gpio connected to the reset pin, toggle it */
2826 gpiod_set_value_cansleep(gpiod, 1);
2827 usleep_range(10000, 20000);
2828 gpiod_set_value_cansleep(gpiod, 0);
2829 usleep_range(10000, 20000);
2832 /* Reset the switch. Keep the PPU active if requested. The PPU
2833 * needs to be active to support indirect phy register access
2834 * through global registers 0x18 and 0x19.
2837 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2839 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2841 /* Wait up to one second for reset to complete. */
2842 timeout = jiffies + 1 * HZ;
2843 while (time_before(jiffies, timeout)) {
2844 ret = REG_READ(REG_GLOBAL, 0x00);
2845 if ((ret & is_reset) == is_reset)
2847 usleep_range(1000, 2000);
2849 if (time_after(jiffies, timeout))
2855 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2857 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2860 mutex_lock(&ps->smi_mutex);
2861 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
2862 mutex_unlock(&ps->smi_mutex);
2867 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2870 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2873 mutex_lock(&ps->smi_mutex);
2874 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
2875 mutex_unlock(&ps->smi_mutex);
2880 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2882 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2884 if (port >= 0 && port < ps->num_ports)
2890 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2892 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2893 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2899 mutex_lock(&ps->smi_mutex);
2900 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2901 mutex_unlock(&ps->smi_mutex);
2906 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2908 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2909 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2915 mutex_lock(&ps->smi_mutex);
2916 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2917 mutex_unlock(&ps->smi_mutex);
2922 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2924 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2925 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2931 mutex_lock(&ps->smi_mutex);
2932 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2933 mutex_unlock(&ps->smi_mutex);
2938 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2941 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2942 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2948 mutex_lock(&ps->smi_mutex);
2949 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2950 mutex_unlock(&ps->smi_mutex);
2954 #ifdef CONFIG_NET_DSA_HWMON
2956 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2958 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2964 mutex_lock(&ps->smi_mutex);
2966 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2970 /* Enable temperature sensor */
2971 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2975 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2979 /* Wait for temperature to stabilize */
2980 usleep_range(10000, 12000);
2982 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2988 /* Disable temperature sensor */
2989 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2993 *temp = ((val & 0x1f) - 5) * 5;
2996 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2997 mutex_unlock(&ps->smi_mutex);
3001 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3003 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3008 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
3012 *temp = (ret & 0xff) - 25;
3017 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3019 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
3020 return mv88e63xx_get_temp(ds, temp);
3022 return mv88e61xx_get_temp(ds, temp);
3025 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3027 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3030 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3035 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3039 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3044 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3046 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3049 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3052 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3055 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3056 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3057 (ret & 0xe0ff) | (temp << 8));
3060 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3062 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3065 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3070 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3074 *alarm = !!(ret & 0x40);
3078 #endif /* CONFIG_NET_DSA_HWMON */
3080 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
3081 const struct mv88e6xxx_switch_id *table,
3084 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
3090 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3094 /* Look up the exact switch ID */
3095 for (i = 0; i < num; ++i)
3096 if (table[i].id == ret)
3097 return table[i].name;
3099 /* Look up only the product number */
3100 for (i = 0; i < num; ++i) {
3101 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
3102 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
3103 ret & PORT_SWITCH_ID_REV_MASK,
3104 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
3105 return table[i].name;
3112 static int __init mv88e6xxx_init(void)
3114 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3115 register_switch_driver(&mv88e6131_switch_driver);
3117 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3118 register_switch_driver(&mv88e6123_switch_driver);
3120 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3121 register_switch_driver(&mv88e6352_switch_driver);
3123 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3124 register_switch_driver(&mv88e6171_switch_driver);
3128 module_init(mv88e6xxx_init);
3130 static void __exit mv88e6xxx_cleanup(void)
3132 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3133 unregister_switch_driver(&mv88e6171_switch_driver);
3135 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3136 unregister_switch_driver(&mv88e6352_switch_driver);
3138 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3139 unregister_switch_driver(&mv88e6123_switch_driver);
3141 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3142 unregister_switch_driver(&mv88e6131_switch_driver);
3145 module_exit(mv88e6xxx_cleanup);
3147 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3148 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3149 MODULE_LICENSE("GPL");