2 * net/dsa/mv88e6xxx.c - Marvell 88e6xxx switch chip support
3 * Copyright (c) 2008 Marvell Semiconductor
5 * Copyright (c) 2015 CMC Electronics, Inc.
6 * Added support for VLAN Table Unit operations
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/delay.h>
15 #include <linux/etherdevice.h>
16 #include <linux/ethtool.h>
17 #include <linux/if_bridge.h>
18 #include <linux/jiffies.h>
19 #include <linux/list.h>
20 #include <linux/module.h>
21 #include <linux/netdevice.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/phy.h>
25 #include <net/switchdev.h>
26 #include "mv88e6xxx.h"
28 static void assert_smi_lock(struct dsa_switch *ds)
30 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
32 if (unlikely(!mutex_is_locked(&ps->smi_mutex))) {
33 dev_err(ds->master_dev, "SMI lock not held!\n");
38 /* If the switch's ADDR[4:0] strap pins are strapped to zero, it will
39 * use all 32 SMI bus addresses on its SMI bus, and all switch registers
40 * will be directly accessible on some {device address,register address}
41 * pair. If the ADDR[4:0] pins are not strapped to zero, the switch
42 * will only respond to SMI transactions to that specific address, and
43 * an indirect addressing mechanism needs to be used to access its
46 static int mv88e6xxx_reg_wait_ready(struct mii_bus *bus, int sw_addr)
51 for (i = 0; i < 16; i++) {
52 ret = mdiobus_read_nested(bus, sw_addr, SMI_CMD);
56 if ((ret & SMI_CMD_BUSY) == 0)
63 static int __mv88e6xxx_reg_read(struct mii_bus *bus, int sw_addr, int addr,
69 return mdiobus_read_nested(bus, addr, reg);
71 /* Wait for the bus to become free. */
72 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
76 /* Transmit the read command. */
77 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
78 SMI_CMD_OP_22_READ | (addr << 5) | reg);
82 /* Wait for the read command to complete. */
83 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
88 ret = mdiobus_read_nested(bus, sw_addr, SMI_DATA);
95 static int _mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
97 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
105 ret = __mv88e6xxx_reg_read(bus, ds->pd->sw_addr, addr, reg);
109 dev_dbg(ds->master_dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
115 int mv88e6xxx_reg_read(struct dsa_switch *ds, int addr, int reg)
117 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
120 mutex_lock(&ps->smi_mutex);
121 ret = _mv88e6xxx_reg_read(ds, addr, reg);
122 mutex_unlock(&ps->smi_mutex);
127 static int __mv88e6xxx_reg_write(struct mii_bus *bus, int sw_addr, int addr,
133 return mdiobus_write_nested(bus, addr, reg, val);
135 /* Wait for the bus to become free. */
136 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
140 /* Transmit the data to write. */
141 ret = mdiobus_write_nested(bus, sw_addr, SMI_DATA, val);
145 /* Transmit the write command. */
146 ret = mdiobus_write_nested(bus, sw_addr, SMI_CMD,
147 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
151 /* Wait for the write command to complete. */
152 ret = mv88e6xxx_reg_wait_ready(bus, sw_addr);
159 static int _mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg,
162 struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
169 dev_dbg(ds->master_dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
172 return __mv88e6xxx_reg_write(bus, ds->pd->sw_addr, addr, reg, val);
175 int mv88e6xxx_reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
177 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
180 mutex_lock(&ps->smi_mutex);
181 ret = _mv88e6xxx_reg_write(ds, addr, reg, val);
182 mutex_unlock(&ps->smi_mutex);
187 int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
189 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]);
190 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]);
191 REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]);
196 int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
201 for (i = 0; i < 6; i++) {
204 /* Write the MAC address byte. */
205 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
206 GLOBAL2_SWITCH_MAC_BUSY | (i << 8) | addr[i]);
208 /* Wait for the write to complete. */
209 for (j = 0; j < 16; j++) {
210 ret = REG_READ(REG_GLOBAL2, GLOBAL2_SWITCH_MAC);
211 if ((ret & GLOBAL2_SWITCH_MAC_BUSY) == 0)
221 static int _mv88e6xxx_phy_read(struct dsa_switch *ds, int addr, int regnum)
224 return _mv88e6xxx_reg_read(ds, addr, regnum);
228 static int _mv88e6xxx_phy_write(struct dsa_switch *ds, int addr, int regnum,
232 return _mv88e6xxx_reg_write(ds, addr, regnum, val);
236 #ifdef CONFIG_NET_DSA_MV88E6XXX_NEED_PPU
237 static int mv88e6xxx_ppu_disable(struct dsa_switch *ds)
240 unsigned long timeout;
242 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
243 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL,
244 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
246 timeout = jiffies + 1 * HZ;
247 while (time_before(jiffies, timeout)) {
248 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
249 usleep_range(1000, 2000);
250 if ((ret & GLOBAL_STATUS_PPU_MASK) !=
251 GLOBAL_STATUS_PPU_POLLING)
258 static int mv88e6xxx_ppu_enable(struct dsa_switch *ds)
261 unsigned long timeout;
263 ret = REG_READ(REG_GLOBAL, GLOBAL_CONTROL);
264 REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, ret | GLOBAL_CONTROL_PPU_ENABLE);
266 timeout = jiffies + 1 * HZ;
267 while (time_before(jiffies, timeout)) {
268 ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS);
269 usleep_range(1000, 2000);
270 if ((ret & GLOBAL_STATUS_PPU_MASK) ==
271 GLOBAL_STATUS_PPU_POLLING)
278 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
280 struct mv88e6xxx_priv_state *ps;
282 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work);
283 if (mutex_trylock(&ps->ppu_mutex)) {
284 struct dsa_switch *ds = ((struct dsa_switch *)ps) - 1;
286 if (mv88e6xxx_ppu_enable(ds) == 0)
287 ps->ppu_disabled = 0;
288 mutex_unlock(&ps->ppu_mutex);
292 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
294 struct mv88e6xxx_priv_state *ps = (void *)_ps;
296 schedule_work(&ps->ppu_work);
299 static int mv88e6xxx_ppu_access_get(struct dsa_switch *ds)
301 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
304 mutex_lock(&ps->ppu_mutex);
306 /* If the PHY polling unit is enabled, disable it so that
307 * we can access the PHY registers. If it was already
308 * disabled, cancel the timer that is going to re-enable
311 if (!ps->ppu_disabled) {
312 ret = mv88e6xxx_ppu_disable(ds);
314 mutex_unlock(&ps->ppu_mutex);
317 ps->ppu_disabled = 1;
319 del_timer(&ps->ppu_timer);
326 static void mv88e6xxx_ppu_access_put(struct dsa_switch *ds)
328 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
330 /* Schedule a timer to re-enable the PHY polling unit. */
331 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10));
332 mutex_unlock(&ps->ppu_mutex);
335 void mv88e6xxx_ppu_state_init(struct dsa_switch *ds)
337 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
339 mutex_init(&ps->ppu_mutex);
340 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work);
341 init_timer(&ps->ppu_timer);
342 ps->ppu_timer.data = (unsigned long)ps;
343 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
346 int mv88e6xxx_phy_read_ppu(struct dsa_switch *ds, int addr, int regnum)
350 ret = mv88e6xxx_ppu_access_get(ds);
352 ret = mv88e6xxx_reg_read(ds, addr, regnum);
353 mv88e6xxx_ppu_access_put(ds);
359 int mv88e6xxx_phy_write_ppu(struct dsa_switch *ds, int addr,
364 ret = mv88e6xxx_ppu_access_get(ds);
366 ret = mv88e6xxx_reg_write(ds, addr, regnum, val);
367 mv88e6xxx_ppu_access_put(ds);
374 static bool mv88e6xxx_6065_family(struct dsa_switch *ds)
376 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
379 case PORT_SWITCH_ID_6031:
380 case PORT_SWITCH_ID_6061:
381 case PORT_SWITCH_ID_6035:
382 case PORT_SWITCH_ID_6065:
388 static bool mv88e6xxx_6095_family(struct dsa_switch *ds)
390 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
393 case PORT_SWITCH_ID_6092:
394 case PORT_SWITCH_ID_6095:
400 static bool mv88e6xxx_6097_family(struct dsa_switch *ds)
402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
405 case PORT_SWITCH_ID_6046:
406 case PORT_SWITCH_ID_6085:
407 case PORT_SWITCH_ID_6096:
408 case PORT_SWITCH_ID_6097:
414 static bool mv88e6xxx_6165_family(struct dsa_switch *ds)
416 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
419 case PORT_SWITCH_ID_6123:
420 case PORT_SWITCH_ID_6161:
421 case PORT_SWITCH_ID_6165:
427 static bool mv88e6xxx_6185_family(struct dsa_switch *ds)
429 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
432 case PORT_SWITCH_ID_6121:
433 case PORT_SWITCH_ID_6122:
434 case PORT_SWITCH_ID_6152:
435 case PORT_SWITCH_ID_6155:
436 case PORT_SWITCH_ID_6182:
437 case PORT_SWITCH_ID_6185:
438 case PORT_SWITCH_ID_6108:
439 case PORT_SWITCH_ID_6131:
445 static bool mv88e6xxx_6320_family(struct dsa_switch *ds)
447 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
450 case PORT_SWITCH_ID_6320:
451 case PORT_SWITCH_ID_6321:
457 static bool mv88e6xxx_6351_family(struct dsa_switch *ds)
459 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
462 case PORT_SWITCH_ID_6171:
463 case PORT_SWITCH_ID_6175:
464 case PORT_SWITCH_ID_6350:
465 case PORT_SWITCH_ID_6351:
471 static bool mv88e6xxx_6352_family(struct dsa_switch *ds)
473 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
476 case PORT_SWITCH_ID_6172:
477 case PORT_SWITCH_ID_6176:
478 case PORT_SWITCH_ID_6240:
479 case PORT_SWITCH_ID_6352:
485 static unsigned int mv88e6xxx_num_databases(struct dsa_switch *ds)
487 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
489 /* The following devices have 4-bit identifiers for 16 databases */
490 if (ps->id == PORT_SWITCH_ID_6061)
493 /* The following devices have 6-bit identifiers for 64 databases */
494 if (ps->id == PORT_SWITCH_ID_6065)
497 /* The following devices have 8-bit identifiers for 256 databases */
498 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
501 /* The following devices have 12-bit identifiers for 4096 databases */
502 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
503 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
509 static bool mv88e6xxx_has_fid_reg(struct dsa_switch *ds)
511 /* Does the device have dedicated FID registers for ATU and VTU ops? */
512 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
513 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
519 static bool mv88e6xxx_has_stu(struct dsa_switch *ds)
521 /* Does the device have STU and dedicated SID registers for VTU ops? */
522 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
523 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds))
529 /* We expect the switch to perform auto negotiation if there is a real
530 * phy. However, in the case of a fixed link phy, we force the port
531 * settings from the fixed link settings.
533 void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
534 struct phy_device *phydev)
536 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
540 if (!phy_is_pseudo_fixed_link(phydev))
543 mutex_lock(&ps->smi_mutex);
545 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
549 reg = ret & ~(PORT_PCS_CTRL_LINK_UP |
550 PORT_PCS_CTRL_FORCE_LINK |
551 PORT_PCS_CTRL_DUPLEX_FULL |
552 PORT_PCS_CTRL_FORCE_DUPLEX |
553 PORT_PCS_CTRL_UNFORCED);
555 reg |= PORT_PCS_CTRL_FORCE_LINK;
557 reg |= PORT_PCS_CTRL_LINK_UP;
559 if (mv88e6xxx_6065_family(ds) && phydev->speed > SPEED_100)
562 switch (phydev->speed) {
564 reg |= PORT_PCS_CTRL_1000;
567 reg |= PORT_PCS_CTRL_100;
570 reg |= PORT_PCS_CTRL_10;
573 pr_info("Unknown speed");
577 reg |= PORT_PCS_CTRL_FORCE_DUPLEX;
578 if (phydev->duplex == DUPLEX_FULL)
579 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
581 if ((mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds)) &&
582 (port >= ps->num_ports - 2)) {
583 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
584 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
585 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
586 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK;
587 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
588 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
589 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
591 _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_PCS_CTRL, reg);
594 mutex_unlock(&ps->smi_mutex);
597 static int _mv88e6xxx_stats_wait(struct dsa_switch *ds)
602 for (i = 0; i < 10; i++) {
603 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_OP);
604 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
611 static int _mv88e6xxx_stats_snapshot(struct dsa_switch *ds, int port)
615 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
616 port = (port + 1) << 5;
618 /* Snapshot the hardware statistics counters for this port. */
619 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
620 GLOBAL_STATS_OP_CAPTURE_PORT |
621 GLOBAL_STATS_OP_HIST_RX_TX | port);
625 /* Wait for the snapshotting to complete. */
626 ret = _mv88e6xxx_stats_wait(ds);
633 static void _mv88e6xxx_stats_read(struct dsa_switch *ds, int stat, u32 *val)
640 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_STATS_OP,
641 GLOBAL_STATS_OP_READ_CAPTURED |
642 GLOBAL_STATS_OP_HIST_RX_TX | stat);
646 ret = _mv88e6xxx_stats_wait(ds);
650 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
656 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
663 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
664 { "in_good_octets", 8, 0x00, BANK0, },
665 { "in_bad_octets", 4, 0x02, BANK0, },
666 { "in_unicast", 4, 0x04, BANK0, },
667 { "in_broadcasts", 4, 0x06, BANK0, },
668 { "in_multicasts", 4, 0x07, BANK0, },
669 { "in_pause", 4, 0x16, BANK0, },
670 { "in_undersize", 4, 0x18, BANK0, },
671 { "in_fragments", 4, 0x19, BANK0, },
672 { "in_oversize", 4, 0x1a, BANK0, },
673 { "in_jabber", 4, 0x1b, BANK0, },
674 { "in_rx_error", 4, 0x1c, BANK0, },
675 { "in_fcs_error", 4, 0x1d, BANK0, },
676 { "out_octets", 8, 0x0e, BANK0, },
677 { "out_unicast", 4, 0x10, BANK0, },
678 { "out_broadcasts", 4, 0x13, BANK0, },
679 { "out_multicasts", 4, 0x12, BANK0, },
680 { "out_pause", 4, 0x15, BANK0, },
681 { "excessive", 4, 0x11, BANK0, },
682 { "collisions", 4, 0x1e, BANK0, },
683 { "deferred", 4, 0x05, BANK0, },
684 { "single", 4, 0x14, BANK0, },
685 { "multiple", 4, 0x17, BANK0, },
686 { "out_fcs_error", 4, 0x03, BANK0, },
687 { "late", 4, 0x1f, BANK0, },
688 { "hist_64bytes", 4, 0x08, BANK0, },
689 { "hist_65_127bytes", 4, 0x09, BANK0, },
690 { "hist_128_255bytes", 4, 0x0a, BANK0, },
691 { "hist_256_511bytes", 4, 0x0b, BANK0, },
692 { "hist_512_1023bytes", 4, 0x0c, BANK0, },
693 { "hist_1024_max_bytes", 4, 0x0d, BANK0, },
694 { "sw_in_discards", 4, 0x10, PORT, },
695 { "sw_in_filtered", 2, 0x12, PORT, },
696 { "sw_out_filtered", 2, 0x13, PORT, },
697 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, },
698 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, },
699 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, },
700 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, },
701 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, },
702 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, },
703 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, },
704 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, },
705 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, },
706 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, },
707 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, },
708 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, },
709 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, },
710 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, },
711 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, },
712 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, },
713 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, },
714 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, },
715 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, },
716 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, },
717 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, },
718 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, },
719 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, },
720 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, },
721 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, },
722 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
725 static bool mv88e6xxx_has_stat(struct dsa_switch *ds,
726 struct mv88e6xxx_hw_stat *stat)
728 switch (stat->type) {
732 return mv88e6xxx_6320_family(ds);
734 return mv88e6xxx_6095_family(ds) ||
735 mv88e6xxx_6185_family(ds) ||
736 mv88e6xxx_6097_family(ds) ||
737 mv88e6xxx_6165_family(ds) ||
738 mv88e6xxx_6351_family(ds) ||
739 mv88e6xxx_6352_family(ds);
744 static uint64_t _mv88e6xxx_get_ethtool_stat(struct dsa_switch *ds,
745 struct mv88e6xxx_hw_stat *s,
755 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), s->reg);
760 if (s->sizeof_stat == 4) {
761 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port),
770 _mv88e6xxx_stats_read(ds, s->reg, &low);
771 if (s->sizeof_stat == 8)
772 _mv88e6xxx_stats_read(ds, s->reg + 1, &high);
774 value = (((u64)high) << 16) | low;
778 void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
780 struct mv88e6xxx_hw_stat *stat;
783 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
784 stat = &mv88e6xxx_hw_stats[i];
785 if (mv88e6xxx_has_stat(ds, stat)) {
786 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
793 int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
795 struct mv88e6xxx_hw_stat *stat;
798 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
799 stat = &mv88e6xxx_hw_stats[i];
800 if (mv88e6xxx_has_stat(ds, stat))
807 mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds,
808 int port, uint64_t *data)
810 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
811 struct mv88e6xxx_hw_stat *stat;
815 mutex_lock(&ps->smi_mutex);
817 ret = _mv88e6xxx_stats_snapshot(ds, port);
819 mutex_unlock(&ps->smi_mutex);
822 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
823 stat = &mv88e6xxx_hw_stats[i];
824 if (mv88e6xxx_has_stat(ds, stat)) {
825 data[j] = _mv88e6xxx_get_ethtool_stat(ds, stat, port);
830 mutex_unlock(&ps->smi_mutex);
833 int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
835 return 32 * sizeof(u16);
838 void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
839 struct ethtool_regs *regs, void *_p)
846 memset(p, 0xff, 32 * sizeof(u16));
848 for (i = 0; i < 32; i++) {
851 ret = mv88e6xxx_reg_read(ds, REG_PORT(port), i);
857 static int _mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset,
860 unsigned long timeout = jiffies + HZ / 10;
862 while (time_before(jiffies, timeout)) {
865 ret = _mv88e6xxx_reg_read(ds, reg, offset);
871 usleep_range(1000, 2000);
876 static int mv88e6xxx_wait(struct dsa_switch *ds, int reg, int offset, u16 mask)
878 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
881 mutex_lock(&ps->smi_mutex);
882 ret = _mv88e6xxx_wait(ds, reg, offset, mask);
883 mutex_unlock(&ps->smi_mutex);
888 static int _mv88e6xxx_phy_wait(struct dsa_switch *ds)
890 return _mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
891 GLOBAL2_SMI_OP_BUSY);
894 int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
896 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
897 GLOBAL2_EEPROM_OP_LOAD);
900 int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
902 return mv88e6xxx_wait(ds, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
903 GLOBAL2_EEPROM_OP_BUSY);
906 static int _mv88e6xxx_atu_wait(struct dsa_switch *ds)
908 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_ATU_OP,
912 static int _mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int addr,
917 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
918 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
923 ret = _mv88e6xxx_phy_wait(ds);
927 return _mv88e6xxx_reg_read(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA);
930 static int _mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int addr,
935 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
939 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL2, GLOBAL2_SMI_OP,
940 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
943 return _mv88e6xxx_phy_wait(ds);
946 int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
948 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
951 mutex_lock(&ps->smi_mutex);
953 reg = _mv88e6xxx_phy_read_indirect(ds, port, 16);
957 e->eee_enabled = !!(reg & 0x0200);
958 e->tx_lpi_enabled = !!(reg & 0x0100);
960 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
964 e->eee_active = !!(reg & PORT_STATUS_EEE);
968 mutex_unlock(&ps->smi_mutex);
972 int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
973 struct phy_device *phydev, struct ethtool_eee *e)
975 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
979 mutex_lock(&ps->smi_mutex);
981 ret = _mv88e6xxx_phy_read_indirect(ds, port, 16);
988 if (e->tx_lpi_enabled)
991 ret = _mv88e6xxx_phy_write_indirect(ds, port, 16, reg);
993 mutex_unlock(&ps->smi_mutex);
998 static int _mv88e6xxx_atu_cmd(struct dsa_switch *ds, u16 fid, u16 cmd)
1002 if (mv88e6xxx_has_fid_reg(ds)) {
1003 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_FID, fid);
1008 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1012 return _mv88e6xxx_atu_wait(ds);
1015 static int _mv88e6xxx_atu_data_write(struct dsa_switch *ds,
1016 struct mv88e6xxx_atu_entry *entry)
1018 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
1020 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) {
1021 unsigned int mask, shift;
1024 data |= GLOBAL_ATU_DATA_TRUNK;
1025 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
1026 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
1028 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
1029 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
1032 data |= (entry->portv_trunkid << shift) & mask;
1035 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1038 static int _mv88e6xxx_atu_flush_move(struct dsa_switch *ds,
1039 struct mv88e6xxx_atu_entry *entry,
1045 err = _mv88e6xxx_atu_wait(ds);
1049 err = _mv88e6xxx_atu_data_write(ds, entry);
1054 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB :
1055 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB;
1057 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL :
1058 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1061 return _mv88e6xxx_atu_cmd(ds, entry->fid, op);
1064 static int _mv88e6xxx_atu_flush(struct dsa_switch *ds, u16 fid, bool static_too)
1066 struct mv88e6xxx_atu_entry entry = {
1068 .state = 0, /* EntryState bits must be 0 */
1071 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1074 static int _mv88e6xxx_atu_move(struct dsa_switch *ds, u16 fid, int from_port,
1075 int to_port, bool static_too)
1077 struct mv88e6xxx_atu_entry entry = {
1082 /* EntryState bits must be 0xF */
1083 entry.state = GLOBAL_ATU_DATA_STATE_MASK;
1085 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */
1086 entry.portv_trunkid = (to_port & 0x0f) << 4;
1087 entry.portv_trunkid |= from_port & 0x0f;
1089 return _mv88e6xxx_atu_flush_move(ds, &entry, static_too);
1092 static int _mv88e6xxx_atu_remove(struct dsa_switch *ds, u16 fid, int port,
1095 /* Destination port 0xF means remove the entries */
1096 return _mv88e6xxx_atu_move(ds, fid, port, 0x0f, static_too);
1099 static const char * const mv88e6xxx_port_state_names[] = {
1100 [PORT_CONTROL_STATE_DISABLED] = "Disabled",
1101 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening",
1102 [PORT_CONTROL_STATE_LEARNING] = "Learning",
1103 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1106 static int _mv88e6xxx_port_state(struct dsa_switch *ds, int port, u8 state)
1111 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL);
1115 oldstate = reg & PORT_CONTROL_STATE_MASK;
1117 if (oldstate != state) {
1118 /* Flush forwarding database if we're moving a port
1119 * from Learning or Forwarding state to Disabled or
1120 * Blocking or Listening state.
1122 if ((oldstate == PORT_CONTROL_STATE_LEARNING ||
1123 oldstate == PORT_CONTROL_STATE_FORWARDING)
1124 && (state == PORT_CONTROL_STATE_DISABLED ||
1125 state == PORT_CONTROL_STATE_BLOCKING)) {
1126 ret = _mv88e6xxx_atu_remove(ds, 0, port, false);
1131 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1132 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL,
1137 netdev_dbg(ds->ports[port], "PortState %s (was %s)\n",
1138 mv88e6xxx_port_state_names[state],
1139 mv88e6xxx_port_state_names[oldstate]);
1145 static int _mv88e6xxx_port_based_vlan_map(struct dsa_switch *ds, int port)
1147 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1148 struct net_device *bridge = ps->ports[port].bridge_dev;
1149 const u16 mask = (1 << ps->num_ports) - 1;
1150 u16 output_ports = 0;
1154 /* allow CPU port or DSA link(s) to send frames to every port */
1155 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1156 output_ports = mask;
1158 for (i = 0; i < ps->num_ports; ++i) {
1159 /* allow sending frames to every group member */
1160 if (bridge && ps->ports[i].bridge_dev == bridge)
1161 output_ports |= BIT(i);
1163 /* allow sending frames to CPU port and DSA link(s) */
1164 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1165 output_ports |= BIT(i);
1169 /* prevent frames from going back out of the port they came in on */
1170 output_ports &= ~BIT(port);
1172 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1177 reg |= output_ports & mask;
1179 return _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN, reg);
1182 int mv88e6xxx_port_stp_update(struct dsa_switch *ds, int port, u8 state)
1184 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1188 case BR_STATE_DISABLED:
1189 stp_state = PORT_CONTROL_STATE_DISABLED;
1191 case BR_STATE_BLOCKING:
1192 case BR_STATE_LISTENING:
1193 stp_state = PORT_CONTROL_STATE_BLOCKING;
1195 case BR_STATE_LEARNING:
1196 stp_state = PORT_CONTROL_STATE_LEARNING;
1198 case BR_STATE_FORWARDING:
1200 stp_state = PORT_CONTROL_STATE_FORWARDING;
1204 /* mv88e6xxx_port_stp_update may be called with softirqs disabled,
1205 * so we can not update the port state directly but need to schedule it.
1207 ps->ports[port].state = stp_state;
1208 set_bit(port, ps->port_state_update_mask);
1209 schedule_work(&ps->bridge_work);
1214 static int _mv88e6xxx_port_pvid(struct dsa_switch *ds, int port, u16 *new,
1220 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_DEFAULT_VLAN);
1224 pvid = ret & PORT_DEFAULT_VLAN_MASK;
1227 ret &= ~PORT_DEFAULT_VLAN_MASK;
1228 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1230 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
1231 PORT_DEFAULT_VLAN, ret);
1235 netdev_dbg(ds->ports[port], "DefaultVID %d (was %d)\n", *new,
1245 static int _mv88e6xxx_port_pvid_get(struct dsa_switch *ds, int port, u16 *pvid)
1247 return _mv88e6xxx_port_pvid(ds, port, NULL, pvid);
1250 static int _mv88e6xxx_port_pvid_set(struct dsa_switch *ds, int port, u16 pvid)
1252 return _mv88e6xxx_port_pvid(ds, port, &pvid, NULL);
1255 static int _mv88e6xxx_vtu_wait(struct dsa_switch *ds)
1257 return _mv88e6xxx_wait(ds, REG_GLOBAL, GLOBAL_VTU_OP,
1258 GLOBAL_VTU_OP_BUSY);
1261 static int _mv88e6xxx_vtu_cmd(struct dsa_switch *ds, u16 op)
1265 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_OP, op);
1269 return _mv88e6xxx_vtu_wait(ds);
1272 static int _mv88e6xxx_vtu_stu_flush(struct dsa_switch *ds)
1276 ret = _mv88e6xxx_vtu_wait(ds);
1280 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_FLUSH_ALL);
1283 static int _mv88e6xxx_vtu_stu_data_read(struct dsa_switch *ds,
1284 struct mv88e6xxx_vtu_stu_entry *entry,
1285 unsigned int nibble_offset)
1287 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1292 for (i = 0; i < 3; ++i) {
1293 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1294 GLOBAL_VTU_DATA_0_3 + i);
1301 for (i = 0; i < ps->num_ports; ++i) {
1302 unsigned int shift = (i % 4) * 4 + nibble_offset;
1303 u16 reg = regs[i / 4];
1305 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK;
1311 static int _mv88e6xxx_vtu_stu_data_write(struct dsa_switch *ds,
1312 struct mv88e6xxx_vtu_stu_entry *entry,
1313 unsigned int nibble_offset)
1315 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1316 u16 regs[3] = { 0 };
1320 for (i = 0; i < ps->num_ports; ++i) {
1321 unsigned int shift = (i % 4) * 4 + nibble_offset;
1322 u8 data = entry->data[i];
1324 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift;
1327 for (i = 0; i < 3; ++i) {
1328 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL,
1329 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1337 static int _mv88e6xxx_vtu_vid_write(struct dsa_switch *ds, u16 vid)
1339 return _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID,
1340 vid & GLOBAL_VTU_VID_MASK);
1343 static int _mv88e6xxx_vtu_getnext(struct dsa_switch *ds,
1344 struct mv88e6xxx_vtu_stu_entry *entry)
1346 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1349 ret = _mv88e6xxx_vtu_wait(ds);
1353 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_GET_NEXT);
1357 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1361 next.vid = ret & GLOBAL_VTU_VID_MASK;
1362 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1365 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 0);
1369 if (mv88e6xxx_has_fid_reg(ds)) {
1370 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1375 next.fid = ret & GLOBAL_VTU_FID_MASK;
1378 if (mv88e6xxx_has_stu(ds)) {
1379 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1384 next.sid = ret & GLOBAL_VTU_SID_MASK;
1392 int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1393 struct switchdev_obj_port_vlan *vlan,
1394 int (*cb)(struct switchdev_obj *obj))
1396 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1397 struct mv88e6xxx_vtu_stu_entry next;
1401 mutex_lock(&ps->smi_mutex);
1403 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1407 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1412 err = _mv88e6xxx_vtu_getnext(ds, &next);
1419 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1422 /* reinit and dump this VLAN obj */
1423 vlan->vid_begin = vlan->vid_end = next.vid;
1426 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED)
1427 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1429 if (next.vid == pvid)
1430 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1432 err = cb(&vlan->obj);
1435 } while (next.vid < GLOBAL_VTU_VID_MASK);
1438 mutex_unlock(&ps->smi_mutex);
1443 static int _mv88e6xxx_vtu_loadpurge(struct dsa_switch *ds,
1444 struct mv88e6xxx_vtu_stu_entry *entry)
1449 ret = _mv88e6xxx_vtu_wait(ds);
1456 /* Write port member tags */
1457 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 0);
1461 if (mv88e6xxx_has_stu(ds)) {
1462 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1463 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1468 if (mv88e6xxx_has_fid_reg(ds)) {
1469 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1470 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_FID, reg);
1475 reg = GLOBAL_VTU_VID_VALID;
1477 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1478 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1482 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
1485 static int _mv88e6xxx_stu_getnext(struct dsa_switch *ds, u8 sid,
1486 struct mv88e6xxx_vtu_stu_entry *entry)
1488 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1491 ret = _mv88e6xxx_vtu_wait(ds);
1495 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID,
1496 sid & GLOBAL_VTU_SID_MASK);
1500 ret = _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_GET_NEXT);
1504 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_SID);
1508 next.sid = ret & GLOBAL_VTU_SID_MASK;
1510 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_VTU_VID);
1514 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1517 ret = _mv88e6xxx_vtu_stu_data_read(ds, &next, 2);
1526 static int _mv88e6xxx_stu_loadpurge(struct dsa_switch *ds,
1527 struct mv88e6xxx_vtu_stu_entry *entry)
1532 ret = _mv88e6xxx_vtu_wait(ds);
1539 /* Write port states */
1540 ret = _mv88e6xxx_vtu_stu_data_write(ds, entry, 2);
1544 reg = GLOBAL_VTU_VID_VALID;
1546 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1550 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1551 ret = _mv88e6xxx_reg_write(ds, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1555 return _mv88e6xxx_vtu_cmd(ds, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1558 static int _mv88e6xxx_port_fid(struct dsa_switch *ds, int port, u16 *new,
1565 if (mv88e6xxx_num_databases(ds) == 4096)
1570 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1571 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_BASE_VLAN);
1575 fid = (ret & PORT_BASE_VLAN_FID_3_0_MASK) >> 12;
1578 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1579 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1581 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_BASE_VLAN,
1587 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1588 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_1);
1592 fid |= (ret & upper_mask) << 4;
1596 ret |= (*new >> 4) & upper_mask;
1598 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1,
1603 netdev_dbg(ds->ports[port], "FID %d (was %d)\n", *new, fid);
1612 static int _mv88e6xxx_port_fid_get(struct dsa_switch *ds, int port, u16 *fid)
1614 return _mv88e6xxx_port_fid(ds, port, NULL, fid);
1617 static int _mv88e6xxx_port_fid_set(struct dsa_switch *ds, int port, u16 fid)
1619 return _mv88e6xxx_port_fid(ds, port, &fid, NULL);
1622 static int _mv88e6xxx_fid_new(struct dsa_switch *ds, u16 *fid)
1624 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1625 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1626 struct mv88e6xxx_vtu_stu_entry vlan;
1629 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1631 /* Set every FID bit used by the (un)bridged ports */
1632 for (i = 0; i < ps->num_ports; ++i) {
1633 err = _mv88e6xxx_port_fid_get(ds, i, fid);
1637 set_bit(*fid, fid_bitmap);
1640 /* Set every FID bit used by the VLAN entries */
1641 err = _mv88e6xxx_vtu_vid_write(ds, GLOBAL_VTU_VID_MASK);
1646 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1653 set_bit(vlan.fid, fid_bitmap);
1654 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
1656 /* The reset value 0x000 is used to indicate that multiple address
1657 * databases are not needed. Return the next positive available.
1659 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1660 if (unlikely(*fid >= mv88e6xxx_num_databases(ds)))
1663 /* Clear the database */
1664 return _mv88e6xxx_atu_flush(ds, *fid, true);
1667 static int _mv88e6xxx_vtu_new(struct dsa_switch *ds, u16 vid,
1668 struct mv88e6xxx_vtu_stu_entry *entry)
1670 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1671 struct mv88e6xxx_vtu_stu_entry vlan = {
1677 err = _mv88e6xxx_fid_new(ds, &vlan.fid);
1681 /* exclude all ports except the CPU and DSA ports */
1682 for (i = 0; i < ps->num_ports; ++i)
1683 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
1684 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
1685 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1687 if (mv88e6xxx_6097_family(ds) || mv88e6xxx_6165_family(ds) ||
1688 mv88e6xxx_6351_family(ds) || mv88e6xxx_6352_family(ds)) {
1689 struct mv88e6xxx_vtu_stu_entry vstp;
1691 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
1692 * implemented, only one STU entry is needed to cover all VTU
1693 * entries. Thus, validate the SID 0.
1696 err = _mv88e6xxx_stu_getnext(ds, GLOBAL_VTU_SID_MASK, &vstp);
1700 if (vstp.sid != vlan.sid || !vstp.valid) {
1701 memset(&vstp, 0, sizeof(vstp));
1703 vstp.sid = vlan.sid;
1705 err = _mv88e6xxx_stu_loadpurge(ds, &vstp);
1715 static int _mv88e6xxx_vtu_get(struct dsa_switch *ds, u16 vid,
1716 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
1723 err = _mv88e6xxx_vtu_vid_write(ds, vid - 1);
1727 err = _mv88e6xxx_vtu_getnext(ds, entry);
1731 if (entry->vid != vid || !entry->valid) {
1734 /* -ENOENT would've been more appropriate, but switchdev expects
1735 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
1738 err = _mv88e6xxx_vtu_new(ds, vid, entry);
1744 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1745 u16 vid_begin, u16 vid_end)
1747 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1748 struct mv88e6xxx_vtu_stu_entry vlan;
1754 mutex_lock(&ps->smi_mutex);
1756 err = _mv88e6xxx_vtu_vid_write(ds, vid_begin - 1);
1761 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
1768 if (vlan.vid > vid_end)
1771 for (i = 0; i < ps->num_ports; ++i) {
1772 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1776 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1779 if (ps->ports[i].bridge_dev ==
1780 ps->ports[port].bridge_dev)
1781 break; /* same bridge, check next VLAN */
1783 netdev_warn(ds->ports[port],
1784 "hardware VLAN %d already used by %s\n",
1786 netdev_name(ps->ports[i].bridge_dev));
1790 } while (vlan.vid < vid_end);
1793 mutex_unlock(&ps->smi_mutex);
1798 static const char * const mv88e6xxx_port_8021q_mode_names[] = {
1799 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled",
1800 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback",
1801 [PORT_CONTROL_2_8021Q_CHECK] = "Check",
1802 [PORT_CONTROL_2_8021Q_SECURE] = "Secure",
1805 int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1806 bool vlan_filtering)
1808 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1809 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
1810 PORT_CONTROL_2_8021Q_DISABLED;
1813 mutex_lock(&ps->smi_mutex);
1815 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_CONTROL_2);
1819 old = ret & PORT_CONTROL_2_8021Q_MASK;
1822 ret &= ~PORT_CONTROL_2_8021Q_MASK;
1823 ret |= new & PORT_CONTROL_2_8021Q_MASK;
1825 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_2,
1830 netdev_dbg(ds->ports[port], "802.1Q Mode %s (was %s)\n",
1831 mv88e6xxx_port_8021q_mode_names[new],
1832 mv88e6xxx_port_8021q_mode_names[old]);
1837 mutex_unlock(&ps->smi_mutex);
1842 int mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1843 const struct switchdev_obj_port_vlan *vlan,
1844 struct switchdev_trans *trans)
1848 /* If the requested port doesn't belong to the same bridge as the VLAN
1849 * members, do not support it (yet) and fallback to software VLAN.
1851 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1856 /* We don't need any dynamic resource from the kernel (yet),
1857 * so skip the prepare phase.
1862 static int _mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, u16 vid,
1865 struct mv88e6xxx_vtu_stu_entry vlan;
1868 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, true);
1872 vlan.data[port] = untagged ?
1873 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
1874 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
1876 return _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1879 int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1880 const struct switchdev_obj_port_vlan *vlan,
1881 struct switchdev_trans *trans)
1883 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1884 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1885 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1889 mutex_lock(&ps->smi_mutex);
1891 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1892 err = _mv88e6xxx_port_vlan_add(ds, port, vid, untagged);
1897 /* no PVID with ranges, otherwise it's a bug */
1899 err = _mv88e6xxx_port_pvid_set(ds, port, vlan->vid_end);
1901 mutex_unlock(&ps->smi_mutex);
1906 static int _mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, u16 vid)
1908 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1909 struct mv88e6xxx_vtu_stu_entry vlan;
1912 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
1916 /* Tell switchdev if this VLAN is handled in software */
1917 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1920 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1922 /* keep the VLAN unless all ports are excluded */
1924 for (i = 0; i < ps->num_ports; ++i) {
1925 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
1928 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1934 err = _mv88e6xxx_vtu_loadpurge(ds, &vlan);
1938 return _mv88e6xxx_atu_remove(ds, vlan.fid, port, false);
1941 int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1942 const struct switchdev_obj_port_vlan *vlan)
1944 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
1948 mutex_lock(&ps->smi_mutex);
1950 err = _mv88e6xxx_port_pvid_get(ds, port, &pvid);
1954 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1955 err = _mv88e6xxx_port_vlan_del(ds, port, vid);
1960 err = _mv88e6xxx_port_pvid_set(ds, port, 0);
1967 mutex_unlock(&ps->smi_mutex);
1972 static int _mv88e6xxx_atu_mac_write(struct dsa_switch *ds,
1973 const unsigned char *addr)
1977 for (i = 0; i < 3; i++) {
1978 ret = _mv88e6xxx_reg_write(
1979 ds, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
1980 (addr[i * 2] << 8) | addr[i * 2 + 1]);
1988 static int _mv88e6xxx_atu_mac_read(struct dsa_switch *ds, unsigned char *addr)
1992 for (i = 0; i < 3; i++) {
1993 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL,
1994 GLOBAL_ATU_MAC_01 + i);
1997 addr[i * 2] = ret >> 8;
1998 addr[i * 2 + 1] = ret & 0xff;
2004 static int _mv88e6xxx_atu_load(struct dsa_switch *ds,
2005 struct mv88e6xxx_atu_entry *entry)
2009 ret = _mv88e6xxx_atu_wait(ds);
2013 ret = _mv88e6xxx_atu_mac_write(ds, entry->mac);
2017 ret = _mv88e6xxx_atu_data_write(ds, entry);
2021 return _mv88e6xxx_atu_cmd(ds, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2024 static int _mv88e6xxx_port_fdb_load(struct dsa_switch *ds, int port,
2025 const unsigned char *addr, u16 vid,
2028 struct mv88e6xxx_atu_entry entry = { 0 };
2029 struct mv88e6xxx_vtu_stu_entry vlan;
2032 /* Null VLAN ID corresponds to the port private database */
2034 err = _mv88e6xxx_port_fid_get(ds, port, &vlan.fid);
2036 err = _mv88e6xxx_vtu_get(ds, vid, &vlan, false);
2040 entry.fid = vlan.fid;
2041 entry.state = state;
2042 ether_addr_copy(entry.mac, addr);
2043 if (state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2044 entry.trunk = false;
2045 entry.portv_trunkid = BIT(port);
2048 return _mv88e6xxx_atu_load(ds, &entry);
2051 int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2052 const struct switchdev_obj_port_fdb *fdb,
2053 struct switchdev_trans *trans)
2055 /* We don't need any dynamic resource from the kernel (yet),
2056 * so skip the prepare phase.
2061 int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2062 const struct switchdev_obj_port_fdb *fdb,
2063 struct switchdev_trans *trans)
2065 int state = is_multicast_ether_addr(fdb->addr) ?
2066 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2067 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2068 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2071 mutex_lock(&ps->smi_mutex);
2072 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid, state);
2073 mutex_unlock(&ps->smi_mutex);
2078 int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2079 const struct switchdev_obj_port_fdb *fdb)
2081 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2084 mutex_lock(&ps->smi_mutex);
2085 ret = _mv88e6xxx_port_fdb_load(ds, port, fdb->addr, fdb->vid,
2086 GLOBAL_ATU_DATA_STATE_UNUSED);
2087 mutex_unlock(&ps->smi_mutex);
2092 static int _mv88e6xxx_atu_getnext(struct dsa_switch *ds, u16 fid,
2093 struct mv88e6xxx_atu_entry *entry)
2095 struct mv88e6xxx_atu_entry next = { 0 };
2100 ret = _mv88e6xxx_atu_wait(ds);
2104 ret = _mv88e6xxx_atu_cmd(ds, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2108 ret = _mv88e6xxx_atu_mac_read(ds, next.mac);
2112 ret = _mv88e6xxx_reg_read(ds, REG_GLOBAL, GLOBAL_ATU_DATA);
2116 next.state = ret & GLOBAL_ATU_DATA_STATE_MASK;
2117 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) {
2118 unsigned int mask, shift;
2120 if (ret & GLOBAL_ATU_DATA_TRUNK) {
2122 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK;
2123 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT;
2126 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK;
2127 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT;
2130 next.portv_trunkid = (ret & mask) >> shift;
2137 static int _mv88e6xxx_port_fdb_dump_one(struct dsa_switch *ds, u16 fid, u16 vid,
2139 struct switchdev_obj_port_fdb *fdb,
2140 int (*cb)(struct switchdev_obj *obj))
2142 struct mv88e6xxx_atu_entry addr = {
2143 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },
2147 err = _mv88e6xxx_atu_mac_write(ds, addr.mac);
2152 err = _mv88e6xxx_atu_getnext(ds, fid, &addr);
2156 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED)
2159 if (!addr.trunk && addr.portv_trunkid & BIT(port)) {
2160 bool is_static = addr.state ==
2161 (is_multicast_ether_addr(addr.mac) ?
2162 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2163 GLOBAL_ATU_DATA_STATE_UC_STATIC);
2166 ether_addr_copy(fdb->addr, addr.mac);
2167 fdb->ndm_state = is_static ? NUD_NOARP : NUD_REACHABLE;
2169 err = cb(&fdb->obj);
2173 } while (!is_broadcast_ether_addr(addr.mac));
2178 int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2179 struct switchdev_obj_port_fdb *fdb,
2180 int (*cb)(struct switchdev_obj *obj))
2182 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2183 struct mv88e6xxx_vtu_stu_entry vlan = {
2184 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2189 mutex_lock(&ps->smi_mutex);
2191 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2192 err = _mv88e6xxx_port_fid_get(ds, port, &fid);
2196 err = _mv88e6xxx_port_fdb_dump_one(ds, fid, 0, port, fdb, cb);
2200 /* Dump VLANs' Filtering Information Databases */
2201 err = _mv88e6xxx_vtu_vid_write(ds, vlan.vid);
2206 err = _mv88e6xxx_vtu_getnext(ds, &vlan);
2213 err = _mv88e6xxx_port_fdb_dump_one(ds, vlan.fid, vlan.vid, port,
2217 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2220 mutex_unlock(&ps->smi_mutex);
2225 int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2226 struct net_device *bridge)
2228 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2232 mutex_lock(&ps->smi_mutex);
2234 /* Get or create the bridge FID and assign it to the port */
2235 for (i = 0; i < ps->num_ports; ++i)
2236 if (ps->ports[i].bridge_dev == bridge)
2239 if (i < ps->num_ports)
2240 err = _mv88e6xxx_port_fid_get(ds, i, &fid);
2242 err = _mv88e6xxx_fid_new(ds, &fid);
2246 err = _mv88e6xxx_port_fid_set(ds, port, fid);
2250 /* Assign the bridge and remap each port's VLANTable */
2251 ps->ports[port].bridge_dev = bridge;
2253 for (i = 0; i < ps->num_ports; ++i) {
2254 if (ps->ports[i].bridge_dev == bridge) {
2255 err = _mv88e6xxx_port_based_vlan_map(ds, i);
2262 mutex_unlock(&ps->smi_mutex);
2267 void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2269 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2270 struct net_device *bridge = ps->ports[port].bridge_dev;
2274 mutex_lock(&ps->smi_mutex);
2276 /* Give the port a fresh Filtering Information Database */
2277 if (_mv88e6xxx_fid_new(ds, &fid) ||
2278 _mv88e6xxx_port_fid_set(ds, port, fid))
2279 netdev_warn(ds->ports[port], "failed to assign a new FID\n");
2281 /* Unassign the bridge and remap each port's VLANTable */
2282 ps->ports[port].bridge_dev = NULL;
2284 for (i = 0; i < ps->num_ports; ++i)
2285 if (i == port || ps->ports[i].bridge_dev == bridge)
2286 if (_mv88e6xxx_port_based_vlan_map(ds, i))
2287 netdev_warn(ds->ports[i], "failed to remap\n");
2289 mutex_unlock(&ps->smi_mutex);
2292 static void mv88e6xxx_bridge_work(struct work_struct *work)
2294 struct mv88e6xxx_priv_state *ps;
2295 struct dsa_switch *ds;
2298 ps = container_of(work, struct mv88e6xxx_priv_state, bridge_work);
2299 ds = ((struct dsa_switch *)ps) - 1;
2301 mutex_lock(&ps->smi_mutex);
2303 for (port = 0; port < ps->num_ports; ++port)
2304 if (test_and_clear_bit(port, ps->port_state_update_mask) &&
2305 _mv88e6xxx_port_state(ds, port, ps->ports[port].state))
2306 netdev_warn(ds->ports[port], "failed to update state to %s\n",
2307 mv88e6xxx_port_state_names[ps->ports[port].state]);
2309 mutex_unlock(&ps->smi_mutex);
2312 static int _mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2317 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2319 goto restore_page_0;
2321 ret = _mv88e6xxx_phy_write_indirect(ds, port, reg, val);
2323 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2328 static int _mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page,
2333 ret = _mv88e6xxx_phy_write_indirect(ds, port, 0x16, page);
2335 goto restore_page_0;
2337 ret = _mv88e6xxx_phy_read_indirect(ds, port, reg);
2339 _mv88e6xxx_phy_write_indirect(ds, port, 0x16, 0x0);
2344 static int mv88e6xxx_power_on_serdes(struct dsa_switch *ds)
2348 ret = _mv88e6xxx_phy_page_read(ds, REG_FIBER_SERDES, PAGE_FIBER_SERDES,
2353 if (ret & BMCR_PDOWN) {
2355 ret = _mv88e6xxx_phy_page_write(ds, REG_FIBER_SERDES,
2356 PAGE_FIBER_SERDES, MII_BMCR,
2363 static int mv88e6xxx_setup_port(struct dsa_switch *ds, int port)
2365 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2369 mutex_lock(&ps->smi_mutex);
2371 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2372 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2373 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2374 mv88e6xxx_6065_family(ds) || mv88e6xxx_6320_family(ds)) {
2375 /* MAC Forcing register: don't force link, speed,
2376 * duplex or flow control state to any particular
2377 * values on physical ports, but force the CPU port
2378 * and all DSA ports to their maximum bandwidth and
2381 reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL);
2382 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2383 reg &= ~PORT_PCS_CTRL_UNFORCED;
2384 reg |= PORT_PCS_CTRL_FORCE_LINK |
2385 PORT_PCS_CTRL_LINK_UP |
2386 PORT_PCS_CTRL_DUPLEX_FULL |
2387 PORT_PCS_CTRL_FORCE_DUPLEX;
2388 if (mv88e6xxx_6065_family(ds))
2389 reg |= PORT_PCS_CTRL_100;
2391 reg |= PORT_PCS_CTRL_1000;
2393 reg |= PORT_PCS_CTRL_UNFORCED;
2396 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2397 PORT_PCS_CTRL, reg);
2402 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2403 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2404 * tunneling, determine priority by looking at 802.1p and IP
2405 * priority fields (IP prio has precedence), and set STP state
2408 * If this is the CPU link, use DSA or EDSA tagging depending
2409 * on which tagging mode was configured.
2411 * If this is a link to another switch, use DSA tagging mode.
2413 * If this is the upstream port for this switch, enable
2414 * forwarding of unknown unicasts and multicasts.
2417 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2418 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2419 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2420 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds))
2421 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2422 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2423 PORT_CONTROL_STATE_FORWARDING;
2424 if (dsa_is_cpu_port(ds, port)) {
2425 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2426 reg |= PORT_CONTROL_DSA_TAG;
2427 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2428 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2429 mv88e6xxx_6320_family(ds)) {
2430 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2431 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA;
2433 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2434 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2435 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2438 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2439 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2440 mv88e6xxx_6095_family(ds) || mv88e6xxx_6065_family(ds) ||
2441 mv88e6xxx_6185_family(ds) || mv88e6xxx_6320_family(ds)) {
2442 if (ds->dst->tag_protocol == DSA_TAG_PROTO_EDSA)
2443 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2446 if (dsa_is_dsa_port(ds, port)) {
2447 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds))
2448 reg |= PORT_CONTROL_DSA_TAG;
2449 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2450 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2451 mv88e6xxx_6320_family(ds)) {
2452 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2455 if (port == dsa_upstream_port(ds))
2456 reg |= PORT_CONTROL_FORWARD_UNKNOWN |
2457 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2460 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2466 /* If this port is connected to a SerDes, make sure the SerDes is not
2469 if (mv88e6xxx_6352_family(ds)) {
2470 ret = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_STATUS);
2473 ret &= PORT_STATUS_CMODE_MASK;
2474 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2475 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2476 (ret == PORT_STATUS_CMODE_SGMII)) {
2477 ret = mv88e6xxx_power_on_serdes(ds);
2483 /* Port Control 2: don't force a good FCS, set the maximum frame size to
2484 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2485 * untagged frames on this port, do a destination address lookup on all
2486 * received packets as usual, disable ARP mirroring and don't send a
2487 * copy of all transmitted/received frames on this port to the CPU.
2490 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2491 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2492 mv88e6xxx_6095_family(ds) || mv88e6xxx_6320_family(ds))
2493 reg = PORT_CONTROL_2_MAP_DA;
2495 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2496 mv88e6xxx_6165_family(ds) || mv88e6xxx_6320_family(ds))
2497 reg |= PORT_CONTROL_2_JUMBO_10240;
2499 if (mv88e6xxx_6095_family(ds) || mv88e6xxx_6185_family(ds)) {
2500 /* Set the upstream port this port should use */
2501 reg |= dsa_upstream_port(ds);
2502 /* enable forwarding of unknown multicast addresses to
2505 if (port == dsa_upstream_port(ds))
2506 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN;
2509 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2512 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2513 PORT_CONTROL_2, reg);
2518 /* Port Association Vector: when learning source addresses
2519 * of packets, add the address to the address database using
2520 * a port bitmap that has only the bit for this port set and
2521 * the other bits clear.
2524 /* Disable learning for DSA and CPU ports */
2525 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2526 reg = PORT_ASSOC_VECTOR_LOCKED_PORT;
2528 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_ASSOC_VECTOR, reg);
2532 /* Egress rate control 2: disable egress rate control. */
2533 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_RATE_CONTROL_2,
2538 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2539 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2540 mv88e6xxx_6320_family(ds)) {
2541 /* Do not limit the period of time that this port can
2542 * be paused for by the remote end or the period of
2543 * time that this port can pause the remote end.
2545 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2546 PORT_PAUSE_CTRL, 0x0000);
2550 /* Port ATU control: disable limiting the number of
2551 * address database entries that this port is allowed
2554 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2555 PORT_ATU_CONTROL, 0x0000);
2556 /* Priority Override: disable DA, SA and VTU priority
2559 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2560 PORT_PRI_OVERRIDE, 0x0000);
2564 /* Port Ethertype: use the Ethertype DSA Ethertype
2567 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2568 PORT_ETH_TYPE, ETH_P_EDSA);
2571 /* Tag Remap: use an identity 802.1p prio -> switch
2574 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2575 PORT_TAG_REGMAP_0123, 0x3210);
2579 /* Tag Remap 2: use an identity 802.1p prio -> switch
2582 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2583 PORT_TAG_REGMAP_4567, 0x7654);
2588 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2589 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2590 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2591 mv88e6xxx_6320_family(ds)) {
2592 /* Rate Control: disable ingress rate limiting. */
2593 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port),
2594 PORT_RATE_CONTROL, 0x0001);
2599 /* Port Control 1: disable trunking, disable sending
2600 * learning messages to this port.
2602 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_CONTROL_1, 0x0000);
2606 /* Port based VLAN map: give each port its own address
2607 * database, and allow bidirectional communication between the
2608 * CPU and DSA port(s), and the other ports.
2610 ret = _mv88e6xxx_port_fid_set(ds, port, port + 1);
2614 ret = _mv88e6xxx_port_based_vlan_map(ds, port);
2618 /* Default VLAN ID and priority: don't set a default VLAN
2619 * ID, and set the default packet priority to zero.
2621 ret = _mv88e6xxx_reg_write(ds, REG_PORT(port), PORT_DEFAULT_VLAN,
2624 mutex_unlock(&ps->smi_mutex);
2628 int mv88e6xxx_setup_ports(struct dsa_switch *ds)
2630 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2634 for (i = 0; i < ps->num_ports; i++) {
2635 ret = mv88e6xxx_setup_port(ds, i);
2642 int mv88e6xxx_setup_common(struct dsa_switch *ds)
2644 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2646 mutex_init(&ps->smi_mutex);
2648 ps->id = REG_READ(REG_PORT(0), PORT_SWITCH_ID) & 0xfff0;
2650 INIT_WORK(&ps->bridge_work, mv88e6xxx_bridge_work);
2655 int mv88e6xxx_setup_global(struct dsa_switch *ds)
2657 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2661 /* Set the default address aging time to 5 minutes, and
2662 * enable address learn messages to be sent to all message
2665 REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL,
2666 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
2668 /* Configure the IP ToS mapping registers. */
2669 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
2670 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
2671 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
2672 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
2673 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
2674 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
2675 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
2676 REG_WRITE(REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
2678 /* Configure the IEEE 802.1p priority mapping register. */
2679 REG_WRITE(REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
2681 /* Send all frames with destination addresses matching
2682 * 01:80:c2:00:00:0x to the CPU port.
2684 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff);
2686 /* Ignore removed tag data on doubly tagged packets, disable
2687 * flow control messages, force flow control priority to the
2688 * highest, and send all special multicast frames to the CPU
2689 * port at the highest priority.
2691 REG_WRITE(REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
2692 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
2693 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
2695 /* Program the DSA routing table. */
2696 for (i = 0; i < 32; i++) {
2699 if (ds->pd->rtable &&
2700 i != ds->index && i < ds->dst->pd->nr_chips)
2701 nexthop = ds->pd->rtable[i] & 0x1f;
2703 REG_WRITE(REG_GLOBAL2, GLOBAL2_DEVICE_MAPPING,
2704 GLOBAL2_DEVICE_MAPPING_UPDATE |
2705 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) |
2709 /* Clear all trunk masks. */
2710 for (i = 0; i < 8; i++)
2711 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MASK,
2712 0x8000 | (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
2713 ((1 << ps->num_ports) - 1));
2715 /* Clear all trunk mappings. */
2716 for (i = 0; i < 16; i++)
2717 REG_WRITE(REG_GLOBAL2, GLOBAL2_TRUNK_MAPPING,
2718 GLOBAL2_TRUNK_MAPPING_UPDATE |
2719 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
2721 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2722 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2723 mv88e6xxx_6320_family(ds)) {
2724 /* Send all frames with destination addresses matching
2725 * 01:80:c2:00:00:2x to the CPU port.
2727 REG_WRITE(REG_GLOBAL2, GLOBAL2_MGMT_EN_2X, 0xffff);
2729 /* Initialise cross-chip port VLAN table to reset
2732 REG_WRITE(REG_GLOBAL2, GLOBAL2_PVT_ADDR, 0x9000);
2734 /* Clear the priority override table. */
2735 for (i = 0; i < 16; i++)
2736 REG_WRITE(REG_GLOBAL2, GLOBAL2_PRIO_OVERRIDE,
2740 if (mv88e6xxx_6352_family(ds) || mv88e6xxx_6351_family(ds) ||
2741 mv88e6xxx_6165_family(ds) || mv88e6xxx_6097_family(ds) ||
2742 mv88e6xxx_6185_family(ds) || mv88e6xxx_6095_family(ds) ||
2743 mv88e6xxx_6320_family(ds)) {
2744 /* Disable ingress rate limiting by resetting all
2745 * ingress rate limit registers to their initial
2748 for (i = 0; i < ps->num_ports; i++)
2749 REG_WRITE(REG_GLOBAL2, GLOBAL2_INGRESS_OP,
2753 /* Clear the statistics counters for all ports */
2754 REG_WRITE(REG_GLOBAL, GLOBAL_STATS_OP, GLOBAL_STATS_OP_FLUSH_ALL);
2756 /* Wait for the flush to complete. */
2757 mutex_lock(&ps->smi_mutex);
2758 ret = _mv88e6xxx_stats_wait(ds);
2762 /* Clear all ATU entries */
2763 ret = _mv88e6xxx_atu_flush(ds, 0, true);
2767 /* Clear all the VTU and STU entries */
2768 ret = _mv88e6xxx_vtu_stu_flush(ds);
2770 mutex_unlock(&ps->smi_mutex);
2775 int mv88e6xxx_switch_reset(struct dsa_switch *ds, bool ppu_active)
2777 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2778 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2779 struct gpio_desc *gpiod = ds->pd->reset;
2780 unsigned long timeout;
2784 /* Set all ports to the disabled state. */
2785 for (i = 0; i < ps->num_ports; i++) {
2786 ret = REG_READ(REG_PORT(i), PORT_CONTROL);
2787 REG_WRITE(REG_PORT(i), PORT_CONTROL, ret & 0xfffc);
2790 /* Wait for transmit queues to drain. */
2791 usleep_range(2000, 4000);
2793 /* If there is a gpio connected to the reset pin, toggle it */
2795 gpiod_set_value_cansleep(gpiod, 1);
2796 usleep_range(10000, 20000);
2797 gpiod_set_value_cansleep(gpiod, 0);
2798 usleep_range(10000, 20000);
2801 /* Reset the switch. Keep the PPU active if requested. The PPU
2802 * needs to be active to support indirect phy register access
2803 * through global registers 0x18 and 0x19.
2806 REG_WRITE(REG_GLOBAL, 0x04, 0xc000);
2808 REG_WRITE(REG_GLOBAL, 0x04, 0xc400);
2810 /* Wait up to one second for reset to complete. */
2811 timeout = jiffies + 1 * HZ;
2812 while (time_before(jiffies, timeout)) {
2813 ret = REG_READ(REG_GLOBAL, 0x00);
2814 if ((ret & is_reset) == is_reset)
2816 usleep_range(1000, 2000);
2818 if (time_after(jiffies, timeout))
2824 int mv88e6xxx_phy_page_read(struct dsa_switch *ds, int port, int page, int reg)
2826 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2829 mutex_lock(&ps->smi_mutex);
2830 ret = _mv88e6xxx_phy_page_read(ds, port, page, reg);
2831 mutex_unlock(&ps->smi_mutex);
2836 int mv88e6xxx_phy_page_write(struct dsa_switch *ds, int port, int page,
2839 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2842 mutex_lock(&ps->smi_mutex);
2843 ret = _mv88e6xxx_phy_page_write(ds, port, page, reg, val);
2844 mutex_unlock(&ps->smi_mutex);
2849 static int mv88e6xxx_port_to_phy_addr(struct dsa_switch *ds, int port)
2851 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2853 if (port >= 0 && port < ps->num_ports)
2859 mv88e6xxx_phy_read(struct dsa_switch *ds, int port, int regnum)
2861 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2862 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2868 mutex_lock(&ps->smi_mutex);
2869 ret = _mv88e6xxx_phy_read(ds, addr, regnum);
2870 mutex_unlock(&ps->smi_mutex);
2875 mv88e6xxx_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
2877 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2878 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2884 mutex_lock(&ps->smi_mutex);
2885 ret = _mv88e6xxx_phy_write(ds, addr, regnum, val);
2886 mutex_unlock(&ps->smi_mutex);
2891 mv88e6xxx_phy_read_indirect(struct dsa_switch *ds, int port, int regnum)
2893 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2894 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2900 mutex_lock(&ps->smi_mutex);
2901 ret = _mv88e6xxx_phy_read_indirect(ds, addr, regnum);
2902 mutex_unlock(&ps->smi_mutex);
2907 mv88e6xxx_phy_write_indirect(struct dsa_switch *ds, int port, int regnum,
2910 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2911 int addr = mv88e6xxx_port_to_phy_addr(ds, port);
2917 mutex_lock(&ps->smi_mutex);
2918 ret = _mv88e6xxx_phy_write_indirect(ds, addr, regnum, val);
2919 mutex_unlock(&ps->smi_mutex);
2923 #ifdef CONFIG_NET_DSA_HWMON
2925 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
2927 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds);
2933 mutex_lock(&ps->smi_mutex);
2935 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x6);
2939 /* Enable temperature sensor */
2940 ret = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2944 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret | (1 << 5));
2948 /* Wait for temperature to stabilize */
2949 usleep_range(10000, 12000);
2951 val = _mv88e6xxx_phy_read(ds, 0x0, 0x1a);
2957 /* Disable temperature sensor */
2958 ret = _mv88e6xxx_phy_write(ds, 0x0, 0x1a, ret & ~(1 << 5));
2962 *temp = ((val & 0x1f) - 5) * 5;
2965 _mv88e6xxx_phy_write(ds, 0x0, 0x16, 0x0);
2966 mutex_unlock(&ps->smi_mutex);
2970 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
2972 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2977 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 27);
2981 *temp = (ret & 0xff) - 25;
2986 int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
2988 if (mv88e6xxx_6320_family(ds) || mv88e6xxx_6352_family(ds))
2989 return mv88e63xx_get_temp(ds, temp);
2991 return mv88e61xx_get_temp(ds, temp);
2994 int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
2996 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
2999 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3004 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3008 *temp = (((ret >> 8) & 0x1f) * 5) - 25;
3013 int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3015 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3018 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3021 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3024 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f);
3025 return mv88e6xxx_phy_page_write(ds, phy, 6, 26,
3026 (ret & 0xe0ff) | (temp << 8));
3029 int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3031 int phy = mv88e6xxx_6320_family(ds) ? 3 : 0;
3034 if (!mv88e6xxx_6320_family(ds) && !mv88e6xxx_6352_family(ds))
3039 ret = mv88e6xxx_phy_page_read(ds, phy, 6, 26);
3043 *alarm = !!(ret & 0x40);
3047 #endif /* CONFIG_NET_DSA_HWMON */
3049 char *mv88e6xxx_lookup_name(struct device *host_dev, int sw_addr,
3050 const struct mv88e6xxx_switch_id *table,
3053 struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
3059 ret = __mv88e6xxx_reg_read(bus, sw_addr, REG_PORT(0), PORT_SWITCH_ID);
3063 /* Look up the exact switch ID */
3064 for (i = 0; i < num; ++i)
3065 if (table[i].id == ret)
3066 return table[i].name;
3068 /* Look up only the product number */
3069 for (i = 0; i < num; ++i) {
3070 if (table[i].id == (ret & PORT_SWITCH_ID_PROD_NUM_MASK)) {
3071 dev_warn(host_dev, "unknown revision %d, using base switch 0x%x\n",
3072 ret & PORT_SWITCH_ID_REV_MASK,
3073 ret & PORT_SWITCH_ID_PROD_NUM_MASK);
3074 return table[i].name;
3081 static int __init mv88e6xxx_init(void)
3083 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3084 register_switch_driver(&mv88e6131_switch_driver);
3086 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3087 register_switch_driver(&mv88e6123_switch_driver);
3089 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3090 register_switch_driver(&mv88e6352_switch_driver);
3092 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3093 register_switch_driver(&mv88e6171_switch_driver);
3097 module_init(mv88e6xxx_init);
3099 static void __exit mv88e6xxx_cleanup(void)
3101 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6171)
3102 unregister_switch_driver(&mv88e6171_switch_driver);
3104 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6352)
3105 unregister_switch_driver(&mv88e6352_switch_driver);
3107 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6123)
3108 unregister_switch_driver(&mv88e6123_switch_driver);
3110 #if IS_ENABLED(CONFIG_NET_DSA_MV88E6131)
3111 unregister_switch_driver(&mv88e6131_switch_driver);
3114 module_exit(mv88e6xxx_cleanup);
3116 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
3117 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
3118 MODULE_LICENSE("GPL");