1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * 82562G 10/100 Network Connection
31 * 82562G-2 10/100 Network Connection
32 * 82562GT 10/100 Network Connection
33 * 82562GT-2 10/100 Network Connection
34 * 82562V 10/100 Network Connection
35 * 82562V-2 10/100 Network Connection
36 * 82566DC-2 Gigabit Network Connection
37 * 82566DC Gigabit Network Connection
38 * 82566DM-2 Gigabit Network Connection
39 * 82566DM Gigabit Network Connection
40 * 82566MC Gigabit Network Connection
41 * 82566MM Gigabit Network Connection
42 * 82567LM Gigabit Network Connection
43 * 82567LF Gigabit Network Connection
44 * 82567V Gigabit Network Connection
45 * 82567LM-2 Gigabit Network Connection
46 * 82567LF-2 Gigabit Network Connection
47 * 82567V-2 Gigabit Network Connection
48 * 82567LF-3 Gigabit Network Connection
49 * 82567LM-3 Gigabit Network Connection
50 * 82567LM-4 Gigabit Network Connection
51 * 82577LM Gigabit Network Connection
52 * 82577LC Gigabit Network Connection
53 * 82578DM Gigabit Network Connection
54 * 82578DC Gigabit Network Connection
55 * 82579LM Gigabit Network Connection
56 * 82579V Gigabit Network Connection
61 #define ICH_FLASH_GFPREG 0x0000
62 #define ICH_FLASH_HSFSTS 0x0004
63 #define ICH_FLASH_HSFCTL 0x0006
64 #define ICH_FLASH_FADDR 0x0008
65 #define ICH_FLASH_FDATA0 0x0010
66 #define ICH_FLASH_PR0 0x0074
68 #define ICH_FLASH_READ_COMMAND_TIMEOUT 500
69 #define ICH_FLASH_WRITE_COMMAND_TIMEOUT 500
70 #define ICH_FLASH_ERASE_COMMAND_TIMEOUT 3000000
71 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF
72 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10
74 #define ICH_CYCLE_READ 0
75 #define ICH_CYCLE_WRITE 2
76 #define ICH_CYCLE_ERASE 3
78 #define FLASH_GFPREG_BASE_MASK 0x1FFF
79 #define FLASH_SECTOR_ADDR_SHIFT 12
81 #define ICH_FLASH_SEG_SIZE_256 256
82 #define ICH_FLASH_SEG_SIZE_4K 4096
83 #define ICH_FLASH_SEG_SIZE_8K 8192
84 #define ICH_FLASH_SEG_SIZE_64K 65536
87 #define E1000_ICH_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI Reset */
88 /* FW established a valid mode */
89 #define E1000_ICH_FWSM_FW_VALID 0x00008000
91 #define E1000_ICH_MNG_IAMT_MODE 0x2
93 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \
94 (ID_LED_DEF1_OFF2 << 8) | \
95 (ID_LED_DEF1_ON2 << 4) | \
98 #define E1000_ICH_NVM_SIG_WORD 0x13
99 #define E1000_ICH_NVM_SIG_MASK 0xC000
100 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0
101 #define E1000_ICH_NVM_SIG_VALUE 0x80
103 #define E1000_ICH8_LAN_INIT_TIMEOUT 1500
105 #define E1000_FEXTNVM_SW_CONFIG 1
106 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */
108 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7
109 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7
110 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3
112 #define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
114 #define E1000_ICH_RAR_ENTRIES 7
116 #define PHY_PAGE_SHIFT 5
117 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
118 ((reg) & MAX_PHY_REG_ADDRESS))
119 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
120 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
122 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002
123 #define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
124 #define IGP3_VR_CTRL_MODE_SHUTDOWN 0x0200
126 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
128 #define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
130 /* SMBus Address Phy Register */
131 #define HV_SMB_ADDR PHY_REG(768, 26)
132 #define HV_SMB_ADDR_MASK 0x007F
133 #define HV_SMB_ADDR_PEC_EN 0x0200
134 #define HV_SMB_ADDR_VALID 0x0080
136 /* PHY Power Management Control */
137 #define HV_PM_CTRL PHY_REG(770, 17)
139 /* PHY Low Power Idle Control */
140 #define I82579_LPI_CTRL PHY_REG(772, 20)
141 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000
144 #define I82579_EMI_ADDR 0x10
145 #define I82579_EMI_DATA 0x11
146 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */
148 /* Strapping Option Register - RO */
149 #define E1000_STRAP 0x0000C
150 #define E1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000
151 #define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
153 /* OEM Bits Phy Register */
154 #define HV_OEM_BITS PHY_REG(768, 25)
155 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
156 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */
157 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
159 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
160 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
162 /* KMRN Mode Control */
163 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16)
164 #define HV_KMRN_MDIO_SLOW 0x0400
166 /* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
167 /* Offset 04h HSFSTS */
168 union ich8_hws_flash_status {
170 u16 flcdone :1; /* bit 0 Flash Cycle Done */
171 u16 flcerr :1; /* bit 1 Flash Cycle Error */
172 u16 dael :1; /* bit 2 Direct Access error Log */
173 u16 berasesz :2; /* bit 4:3 Sector Erase Size */
174 u16 flcinprog :1; /* bit 5 flash cycle in Progress */
175 u16 reserved1 :2; /* bit 13:6 Reserved */
176 u16 reserved2 :6; /* bit 13:6 Reserved */
177 u16 fldesvalid :1; /* bit 14 Flash Descriptor Valid */
178 u16 flockdn :1; /* bit 15 Flash Config Lock-Down */
183 /* ICH GbE Flash Hardware Sequencing Flash control Register bit breakdown */
184 /* Offset 06h FLCTL */
185 union ich8_hws_flash_ctrl {
186 struct ich8_hsflctl {
187 u16 flcgo :1; /* 0 Flash Cycle Go */
188 u16 flcycle :2; /* 2:1 Flash Cycle */
189 u16 reserved :5; /* 7:3 Reserved */
190 u16 fldbcount :2; /* 9:8 Flash Data Byte Count */
191 u16 flockdn :6; /* 15:10 Reserved */
196 /* ICH Flash Region Access Permissions */
197 union ich8_hws_flash_regacc {
199 u32 grra :8; /* 0:7 GbE region Read Access */
200 u32 grwa :8; /* 8:15 GbE region Write Access */
201 u32 gmrag :8; /* 23:16 GbE Master Read Access Grant */
202 u32 gmwag :8; /* 31:24 GbE Master Write Access Grant */
207 /* ICH Flash Protected Region */
208 union ich8_flash_protected_range {
210 u32 base:13; /* 0:12 Protected Range Base */
211 u32 reserved1:2; /* 13:14 Reserved */
212 u32 rpe:1; /* 15 Read Protection Enable */
213 u32 limit:13; /* 16:28 Protected Range Limit */
214 u32 reserved2:2; /* 29:30 Reserved */
215 u32 wpe:1; /* 31 Write Protection Enable */
220 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw);
221 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw);
222 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw);
223 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank);
224 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
225 u32 offset, u8 byte);
226 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
228 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
230 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
232 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw);
233 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw);
234 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw);
235 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw);
236 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw);
237 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw);
238 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw);
239 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
240 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
241 static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
242 static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
243 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
244 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw);
245 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw);
246 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link);
247 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw);
248 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw);
249 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw);
250 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw);
251 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate);
253 static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
255 return readw(hw->flash_address + reg);
258 static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
260 return readl(hw->flash_address + reg);
263 static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
265 writew(val, hw->flash_address + reg);
268 static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
270 writel(val, hw->flash_address + reg);
273 #define er16flash(reg) __er16flash(hw, (reg))
274 #define er32flash(reg) __er32flash(hw, (reg))
275 #define ew16flash(reg,val) __ew16flash(hw, (reg), (val))
276 #define ew32flash(reg,val) __ew32flash(hw, (reg), (val))
278 static void e1000_toggle_lanphypc_value_ich8lan(struct e1000_hw *hw)
283 ctrl |= E1000_CTRL_LANPHYPC_OVERRIDE;
284 ctrl &= ~E1000_CTRL_LANPHYPC_VALUE;
287 ctrl &= ~E1000_CTRL_LANPHYPC_OVERRIDE;
292 * e1000_init_phy_params_pchlan - Initialize PHY function pointers
293 * @hw: pointer to the HW structure
295 * Initialize family-specific PHY parameters and function pointers.
297 static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
299 struct e1000_phy_info *phy = &hw->phy;
304 phy->reset_delay_us = 100;
306 phy->ops.set_page = e1000_set_page_igp;
307 phy->ops.read_reg = e1000_read_phy_reg_hv;
308 phy->ops.read_reg_locked = e1000_read_phy_reg_hv_locked;
309 phy->ops.read_reg_page = e1000_read_phy_reg_page_hv;
310 phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
311 phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
312 phy->ops.write_reg = e1000_write_phy_reg_hv;
313 phy->ops.write_reg_locked = e1000_write_phy_reg_hv_locked;
314 phy->ops.write_reg_page = e1000_write_phy_reg_page_hv;
315 phy->ops.power_up = e1000_power_up_phy_copper;
316 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
317 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
320 * The MAC-PHY interconnect may still be in SMBus mode
321 * after Sx->S0. If the manageability engine (ME) is
322 * disabled, then toggle the LANPHYPC Value bit to force
323 * the interconnect to PCIe mode.
326 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) && !e1000_check_reset_block(hw)) {
327 e1000_toggle_lanphypc_value_ich8lan(hw);
331 * Gate automatic PHY configuration by hardware on
334 if (hw->mac.type == e1000_pch2lan)
335 e1000_gate_hw_phy_config_ich8lan(hw, true);
339 * Reset the PHY before any access to it. Doing so, ensures that
340 * the PHY is in a known good state before we read/write PHY registers.
341 * The generic reset is sufficient here, because we haven't determined
344 ret_val = e1000e_phy_hw_reset_generic(hw);
348 /* Ungate automatic PHY configuration on non-managed 82579 */
349 if ((hw->mac.type == e1000_pch2lan) &&
350 !(fwsm & E1000_ICH_FWSM_FW_VALID)) {
351 usleep_range(10000, 20000);
352 e1000_gate_hw_phy_config_ich8lan(hw, false);
355 phy->id = e1000_phy_unknown;
356 switch (hw->mac.type) {
358 ret_val = e1000e_get_phy_id(hw);
361 if ((phy->id != 0) && (phy->id != PHY_REVISION_MASK))
366 * In case the PHY needs to be in mdio slow mode,
367 * set slow mode and try to get the PHY id again.
369 ret_val = e1000_set_mdio_slow_mode_hv(hw);
372 ret_val = e1000e_get_phy_id(hw);
377 phy->type = e1000e_get_phy_type_from_id(phy->id);
380 case e1000_phy_82577:
381 case e1000_phy_82579:
382 phy->ops.check_polarity = e1000_check_polarity_82577;
383 phy->ops.force_speed_duplex =
384 e1000_phy_force_speed_duplex_82577;
385 phy->ops.get_cable_length = e1000_get_cable_length_82577;
386 phy->ops.get_info = e1000_get_phy_info_82577;
387 phy->ops.commit = e1000e_phy_sw_reset;
389 case e1000_phy_82578:
390 phy->ops.check_polarity = e1000_check_polarity_m88;
391 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
392 phy->ops.get_cable_length = e1000e_get_cable_length_m88;
393 phy->ops.get_info = e1000e_get_phy_info_m88;
396 ret_val = -E1000_ERR_PHY;
405 * e1000_init_phy_params_ich8lan - Initialize PHY function pointers
406 * @hw: pointer to the HW structure
408 * Initialize family-specific PHY parameters and function pointers.
410 static s32 e1000_init_phy_params_ich8lan(struct e1000_hw *hw)
412 struct e1000_phy_info *phy = &hw->phy;
417 phy->reset_delay_us = 100;
419 phy->ops.power_up = e1000_power_up_phy_copper;
420 phy->ops.power_down = e1000_power_down_phy_copper_ich8lan;
423 * We may need to do this twice - once for IGP and if that fails,
424 * we'll set BM func pointers and try again
426 ret_val = e1000e_determine_phy_address(hw);
428 phy->ops.write_reg = e1000e_write_phy_reg_bm;
429 phy->ops.read_reg = e1000e_read_phy_reg_bm;
430 ret_val = e1000e_determine_phy_address(hw);
432 e_dbg("Cannot determine PHY addr. Erroring out\n");
438 while ((e1000_phy_unknown == e1000e_get_phy_type_from_id(phy->id)) &&
440 usleep_range(1000, 2000);
441 ret_val = e1000e_get_phy_id(hw);
448 case IGP03E1000_E_PHY_ID:
449 phy->type = e1000_phy_igp_3;
450 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
451 phy->ops.read_reg_locked = e1000e_read_phy_reg_igp_locked;
452 phy->ops.write_reg_locked = e1000e_write_phy_reg_igp_locked;
453 phy->ops.get_info = e1000e_get_phy_info_igp;
454 phy->ops.check_polarity = e1000_check_polarity_igp;
455 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_igp;
458 case IFE_PLUS_E_PHY_ID:
460 phy->type = e1000_phy_ife;
461 phy->autoneg_mask = E1000_ALL_NOT_GIG;
462 phy->ops.get_info = e1000_get_phy_info_ife;
463 phy->ops.check_polarity = e1000_check_polarity_ife;
464 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_ife;
466 case BME1000_E_PHY_ID:
467 phy->type = e1000_phy_bm;
468 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
469 phy->ops.read_reg = e1000e_read_phy_reg_bm;
470 phy->ops.write_reg = e1000e_write_phy_reg_bm;
471 phy->ops.commit = e1000e_phy_sw_reset;
472 phy->ops.get_info = e1000e_get_phy_info_m88;
473 phy->ops.check_polarity = e1000_check_polarity_m88;
474 phy->ops.force_speed_duplex = e1000e_phy_force_speed_duplex_m88;
477 return -E1000_ERR_PHY;
485 * e1000_init_nvm_params_ich8lan - Initialize NVM function pointers
486 * @hw: pointer to the HW structure
488 * Initialize family-specific NVM parameters and function
491 static s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw)
493 struct e1000_nvm_info *nvm = &hw->nvm;
494 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
495 u32 gfpreg, sector_base_addr, sector_end_addr;
498 /* Can't read flash registers if the register set isn't mapped. */
499 if (!hw->flash_address) {
500 e_dbg("ERROR: Flash registers not mapped\n");
501 return -E1000_ERR_CONFIG;
504 nvm->type = e1000_nvm_flash_sw;
506 gfpreg = er32flash(ICH_FLASH_GFPREG);
509 * sector_X_addr is a "sector"-aligned address (4096 bytes)
510 * Add 1 to sector_end_addr since this sector is included in
513 sector_base_addr = gfpreg & FLASH_GFPREG_BASE_MASK;
514 sector_end_addr = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK) + 1;
516 /* flash_base_addr is byte-aligned */
517 nvm->flash_base_addr = sector_base_addr << FLASH_SECTOR_ADDR_SHIFT;
520 * find total size of the NVM, then cut in half since the total
521 * size represents two separate NVM banks.
523 nvm->flash_bank_size = (sector_end_addr - sector_base_addr)
524 << FLASH_SECTOR_ADDR_SHIFT;
525 nvm->flash_bank_size /= 2;
526 /* Adjust to word count */
527 nvm->flash_bank_size /= sizeof(u16);
529 nvm->word_size = E1000_ICH8_SHADOW_RAM_WORDS;
531 /* Clear shadow ram */
532 for (i = 0; i < nvm->word_size; i++) {
533 dev_spec->shadow_ram[i].modified = false;
534 dev_spec->shadow_ram[i].value = 0xFFFF;
541 * e1000_init_mac_params_ich8lan - Initialize MAC function pointers
542 * @hw: pointer to the HW structure
544 * Initialize family-specific MAC parameters and function
547 static s32 e1000_init_mac_params_ich8lan(struct e1000_adapter *adapter)
549 struct e1000_hw *hw = &adapter->hw;
550 struct e1000_mac_info *mac = &hw->mac;
552 /* Set media type function pointer */
553 hw->phy.media_type = e1000_media_type_copper;
555 /* Set mta register count */
556 mac->mta_reg_count = 32;
557 /* Set rar entry count */
558 mac->rar_entry_count = E1000_ICH_RAR_ENTRIES;
559 if (mac->type == e1000_ich8lan)
560 mac->rar_entry_count--;
562 mac->has_fwsm = true;
563 /* ARC subsystem not supported */
564 mac->arc_subsystem_valid = false;
565 /* Adaptive IFS supported */
566 mac->adaptive_ifs = true;
573 /* check management mode */
574 mac->ops.check_mng_mode = e1000_check_mng_mode_ich8lan;
576 mac->ops.id_led_init = e1000e_id_led_init;
578 mac->ops.blink_led = e1000e_blink_led_generic;
580 mac->ops.setup_led = e1000e_setup_led_generic;
582 mac->ops.cleanup_led = e1000_cleanup_led_ich8lan;
583 /* turn on/off LED */
584 mac->ops.led_on = e1000_led_on_ich8lan;
585 mac->ops.led_off = e1000_led_off_ich8lan;
589 /* check management mode */
590 mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan;
592 mac->ops.id_led_init = e1000_id_led_init_pchlan;
594 mac->ops.setup_led = e1000_setup_led_pchlan;
596 mac->ops.cleanup_led = e1000_cleanup_led_pchlan;
597 /* turn on/off LED */
598 mac->ops.led_on = e1000_led_on_pchlan;
599 mac->ops.led_off = e1000_led_off_pchlan;
605 /* Enable PCS Lock-loss workaround for ICH8 */
606 if (mac->type == e1000_ich8lan)
607 e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
609 /* Gate automatic PHY configuration by hardware on managed 82579 */
610 if ((mac->type == e1000_pch2lan) &&
611 (er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
612 e1000_gate_hw_phy_config_ich8lan(hw, true);
618 * e1000_set_eee_pchlan - Enable/disable EEE support
619 * @hw: pointer to the HW structure
621 * Enable/disable EEE based on setting in dev_spec structure. The bits in
622 * the LPI Control register will remain set only if/when link is up.
624 static s32 e1000_set_eee_pchlan(struct e1000_hw *hw)
629 if (hw->phy.type != e1000_phy_82579)
632 ret_val = e1e_rphy(hw, I82579_LPI_CTRL, &phy_reg);
636 if (hw->dev_spec.ich8lan.eee_disable)
637 phy_reg &= ~I82579_LPI_CTRL_ENABLE_MASK;
639 phy_reg |= I82579_LPI_CTRL_ENABLE_MASK;
641 ret_val = e1e_wphy(hw, I82579_LPI_CTRL, phy_reg);
647 * e1000_check_for_copper_link_ich8lan - Check for link (Copper)
648 * @hw: pointer to the HW structure
650 * Checks to see of the link status of the hardware has changed. If a
651 * change in link status has been detected, then we read the PHY registers
652 * to get the current speed/duplex if link exists.
654 static s32 e1000_check_for_copper_link_ich8lan(struct e1000_hw *hw)
656 struct e1000_mac_info *mac = &hw->mac;
661 * We only want to go out to the PHY registers to see if Auto-Neg
662 * has completed and/or if our link status has changed. The
663 * get_link_status flag is set upon receiving a Link Status
664 * Change or Rx Sequence Error interrupt.
666 if (!mac->get_link_status) {
672 * First we want to see if the MII Status Register reports
673 * link. If so, then we want to get the current speed/duplex
676 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
680 if (hw->mac.type == e1000_pchlan) {
681 ret_val = e1000_k1_gig_workaround_hv(hw, link);
687 goto out; /* No link detected */
689 mac->get_link_status = false;
691 if (hw->phy.type == e1000_phy_82578) {
692 ret_val = e1000_link_stall_workaround_hv(hw);
697 if (hw->mac.type == e1000_pch2lan) {
698 ret_val = e1000_k1_workaround_lv(hw);
704 * Check if there was DownShift, must be checked
705 * immediately after link-up
707 e1000e_check_downshift(hw);
709 /* Enable/Disable EEE after link up */
710 ret_val = e1000_set_eee_pchlan(hw);
715 * If we are forcing speed/duplex, then we simply return since
716 * we have already determined whether we have link or not.
719 ret_val = -E1000_ERR_CONFIG;
724 * Auto-Neg is enabled. Auto Speed Detection takes care
725 * of MAC speed/duplex configuration. So we only need to
726 * configure Collision Distance in the MAC.
728 e1000e_config_collision_dist(hw);
731 * Configure Flow Control now that Auto-Neg has completed.
732 * First, we need to restore the desired flow control
733 * settings because we may have had to re-autoneg with a
734 * different link partner.
736 ret_val = e1000e_config_fc_after_link_up(hw);
738 e_dbg("Error configuring flow control\n");
744 static s32 e1000_get_variants_ich8lan(struct e1000_adapter *adapter)
746 struct e1000_hw *hw = &adapter->hw;
749 rc = e1000_init_mac_params_ich8lan(adapter);
753 rc = e1000_init_nvm_params_ich8lan(hw);
757 switch (hw->mac.type) {
761 rc = e1000_init_phy_params_ich8lan(hw);
765 rc = e1000_init_phy_params_pchlan(hw);
774 * Disable Jumbo Frame support on parts with Intel 10/100 PHY or
775 * on parts with MACsec enabled in NVM (reflected in CTRL_EXT).
777 if ((adapter->hw.phy.type == e1000_phy_ife) ||
778 ((adapter->hw.mac.type >= e1000_pch2lan) &&
779 (!(er32(CTRL_EXT) & E1000_CTRL_EXT_LSECCK)))) {
780 adapter->flags &= ~FLAG_HAS_JUMBO_FRAMES;
781 adapter->max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN;
783 hw->mac.ops.blink_led = NULL;
786 if ((adapter->hw.mac.type == e1000_ich8lan) &&
787 (adapter->hw.phy.type == e1000_phy_igp_3))
788 adapter->flags |= FLAG_LSC_GIG_SPEED_DROP;
790 /* Disable EEE by default until IEEE802.3az spec is finalized */
791 if (adapter->flags2 & FLAG2_HAS_EEE)
792 adapter->hw.dev_spec.ich8lan.eee_disable = true;
797 static DEFINE_MUTEX(nvm_mutex);
800 * e1000_acquire_nvm_ich8lan - Acquire NVM mutex
801 * @hw: pointer to the HW structure
803 * Acquires the mutex for performing NVM operations.
805 static s32 e1000_acquire_nvm_ich8lan(struct e1000_hw *hw)
807 mutex_lock(&nvm_mutex);
813 * e1000_release_nvm_ich8lan - Release NVM mutex
814 * @hw: pointer to the HW structure
816 * Releases the mutex used while performing NVM operations.
818 static void e1000_release_nvm_ich8lan(struct e1000_hw *hw)
820 mutex_unlock(&nvm_mutex);
823 static DEFINE_MUTEX(swflag_mutex);
826 * e1000_acquire_swflag_ich8lan - Acquire software control flag
827 * @hw: pointer to the HW structure
829 * Acquires the software control flag for performing PHY and select
832 static s32 e1000_acquire_swflag_ich8lan(struct e1000_hw *hw)
834 u32 extcnf_ctrl, timeout = PHY_CFG_TIMEOUT;
837 mutex_lock(&swflag_mutex);
840 extcnf_ctrl = er32(EXTCNF_CTRL);
841 if (!(extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG))
849 e_dbg("SW/FW/HW has locked the resource for too long.\n");
850 ret_val = -E1000_ERR_CONFIG;
854 timeout = SW_FLAG_TIMEOUT;
856 extcnf_ctrl |= E1000_EXTCNF_CTRL_SWFLAG;
857 ew32(EXTCNF_CTRL, extcnf_ctrl);
860 extcnf_ctrl = er32(EXTCNF_CTRL);
861 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
869 e_dbg("Failed to acquire the semaphore.\n");
870 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
871 ew32(EXTCNF_CTRL, extcnf_ctrl);
872 ret_val = -E1000_ERR_CONFIG;
878 mutex_unlock(&swflag_mutex);
884 * e1000_release_swflag_ich8lan - Release software control flag
885 * @hw: pointer to the HW structure
887 * Releases the software control flag for performing PHY and select
890 static void e1000_release_swflag_ich8lan(struct e1000_hw *hw)
894 extcnf_ctrl = er32(EXTCNF_CTRL);
896 if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG) {
897 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
898 ew32(EXTCNF_CTRL, extcnf_ctrl);
900 e_dbg("Semaphore unexpectedly released by sw/fw/hw\n");
903 mutex_unlock(&swflag_mutex);
907 * e1000_check_mng_mode_ich8lan - Checks management mode
908 * @hw: pointer to the HW structure
910 * This checks if the adapter has any manageability enabled.
911 * This is a function pointer entry point only called by read/write
912 * routines for the PHY and NVM parts.
914 static bool e1000_check_mng_mode_ich8lan(struct e1000_hw *hw)
919 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
920 ((fwsm & E1000_FWSM_MODE_MASK) ==
921 (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
925 * e1000_check_mng_mode_pchlan - Checks management mode
926 * @hw: pointer to the HW structure
928 * This checks if the adapter has iAMT enabled.
929 * This is a function pointer entry point only called by read/write
930 * routines for the PHY and NVM parts.
932 static bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw)
937 return (fwsm & E1000_ICH_FWSM_FW_VALID) &&
938 (fwsm & (E1000_ICH_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT));
942 * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked
943 * @hw: pointer to the HW structure
945 * Checks if firmware is blocking the reset of the PHY.
946 * This is a function pointer entry point only called by
949 static s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw)
955 return (fwsm & E1000_ICH_FWSM_RSPCIPHY) ? 0 : E1000_BLK_PHY_RESET;
959 * e1000_write_smbus_addr - Write SMBus address to PHY needed during Sx states
960 * @hw: pointer to the HW structure
962 * Assumes semaphore already acquired.
965 static s32 e1000_write_smbus_addr(struct e1000_hw *hw)
968 u32 strap = er32(STRAP);
971 strap &= E1000_STRAP_SMBUS_ADDRESS_MASK;
973 ret_val = e1000_read_phy_reg_hv_locked(hw, HV_SMB_ADDR, &phy_data);
977 phy_data &= ~HV_SMB_ADDR_MASK;
978 phy_data |= (strap >> E1000_STRAP_SMBUS_ADDRESS_SHIFT);
979 phy_data |= HV_SMB_ADDR_PEC_EN | HV_SMB_ADDR_VALID;
980 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_SMB_ADDR, phy_data);
987 * e1000_sw_lcd_config_ich8lan - SW-based LCD Configuration
988 * @hw: pointer to the HW structure
990 * SW should configure the LCD from the NVM extended configuration region
991 * as a workaround for certain parts.
993 static s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw)
995 struct e1000_phy_info *phy = &hw->phy;
996 u32 i, data, cnf_size, cnf_base_addr, sw_cfg_mask;
998 u16 word_addr, reg_data, reg_addr, phy_page = 0;
1001 * Initialize the PHY from the NVM on ICH platforms. This
1002 * is needed due to an issue where the NVM configuration is
1003 * not properly autoloaded after power transitions.
1004 * Therefore, after each PHY reset, we will load the
1005 * configuration data out of the NVM manually.
1007 switch (hw->mac.type) {
1009 if (phy->type != e1000_phy_igp_3)
1012 if ((hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_AMT) ||
1013 (hw->adapter->pdev->device == E1000_DEV_ID_ICH8_IGP_C)) {
1014 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
1020 sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
1026 ret_val = hw->phy.ops.acquire(hw);
1030 data = er32(FEXTNVM);
1031 if (!(data & sw_cfg_mask))
1035 * Make sure HW does not configure LCD from PHY
1036 * extended configuration before SW configuration
1038 data = er32(EXTCNF_CTRL);
1039 if (!(hw->mac.type == e1000_pch2lan)) {
1040 if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
1044 cnf_size = er32(EXTCNF_SIZE);
1045 cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
1046 cnf_size >>= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT;
1050 cnf_base_addr = data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK;
1051 cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
1053 if ((!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
1054 (hw->mac.type == e1000_pchlan)) ||
1055 (hw->mac.type == e1000_pch2lan)) {
1057 * HW configures the SMBus address and LEDs when the
1058 * OEM and LCD Write Enable bits are set in the NVM.
1059 * When both NVM bits are cleared, SW will configure
1062 ret_val = e1000_write_smbus_addr(hw);
1066 data = er32(LEDCTL);
1067 ret_val = e1000_write_phy_reg_hv_locked(hw, HV_LED_CONFIG,
1073 /* Configure LCD from extended configuration region. */
1075 /* cnf_base_addr is in DWORD */
1076 word_addr = (u16)(cnf_base_addr << 1);
1078 for (i = 0; i < cnf_size; i++) {
1079 ret_val = e1000_read_nvm(hw, (word_addr + i * 2), 1,
1084 ret_val = e1000_read_nvm(hw, (word_addr + i * 2 + 1),
1089 /* Save off the PHY page for future writes. */
1090 if (reg_addr == IGP01E1000_PHY_PAGE_SELECT) {
1091 phy_page = reg_data;
1095 reg_addr &= PHY_REG_MASK;
1096 reg_addr |= phy_page;
1098 ret_val = phy->ops.write_reg_locked(hw, (u32)reg_addr,
1105 hw->phy.ops.release(hw);
1110 * e1000_k1_gig_workaround_hv - K1 Si workaround
1111 * @hw: pointer to the HW structure
1112 * @link: link up bool flag
1114 * If K1 is enabled for 1Gbps, the MAC might stall when transitioning
1115 * from a lower speed. This workaround disables K1 whenever link is at 1Gig
1116 * If link is down, the function will restore the default K1 setting located
1119 static s32 e1000_k1_gig_workaround_hv(struct e1000_hw *hw, bool link)
1123 bool k1_enable = hw->dev_spec.ich8lan.nvm_k1_enabled;
1125 if (hw->mac.type != e1000_pchlan)
1128 /* Wrap the whole flow with the sw flag */
1129 ret_val = hw->phy.ops.acquire(hw);
1133 /* Disable K1 when link is 1Gbps, otherwise use the NVM setting */
1135 if (hw->phy.type == e1000_phy_82578) {
1136 ret_val = hw->phy.ops.read_reg_locked(hw, BM_CS_STATUS,
1141 status_reg &= BM_CS_STATUS_LINK_UP |
1142 BM_CS_STATUS_RESOLVED |
1143 BM_CS_STATUS_SPEED_MASK;
1145 if (status_reg == (BM_CS_STATUS_LINK_UP |
1146 BM_CS_STATUS_RESOLVED |
1147 BM_CS_STATUS_SPEED_1000))
1151 if (hw->phy.type == e1000_phy_82577) {
1152 ret_val = hw->phy.ops.read_reg_locked(hw, HV_M_STATUS,
1157 status_reg &= HV_M_STATUS_LINK_UP |
1158 HV_M_STATUS_AUTONEG_COMPLETE |
1159 HV_M_STATUS_SPEED_MASK;
1161 if (status_reg == (HV_M_STATUS_LINK_UP |
1162 HV_M_STATUS_AUTONEG_COMPLETE |
1163 HV_M_STATUS_SPEED_1000))
1167 /* Link stall fix for link up */
1168 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1174 /* Link stall fix for link down */
1175 ret_val = hw->phy.ops.write_reg_locked(hw, PHY_REG(770, 19),
1181 ret_val = e1000_configure_k1_ich8lan(hw, k1_enable);
1184 hw->phy.ops.release(hw);
1190 * e1000_configure_k1_ich8lan - Configure K1 power state
1191 * @hw: pointer to the HW structure
1192 * @enable: K1 state to configure
1194 * Configure the K1 power state based on the provided parameter.
1195 * Assumes semaphore already acquired.
1197 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1199 s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable)
1207 ret_val = e1000e_read_kmrn_reg_locked(hw,
1208 E1000_KMRNCTRLSTA_K1_CONFIG,
1214 kmrn_reg |= E1000_KMRNCTRLSTA_K1_ENABLE;
1216 kmrn_reg &= ~E1000_KMRNCTRLSTA_K1_ENABLE;
1218 ret_val = e1000e_write_kmrn_reg_locked(hw,
1219 E1000_KMRNCTRLSTA_K1_CONFIG,
1225 ctrl_ext = er32(CTRL_EXT);
1226 ctrl_reg = er32(CTRL);
1228 reg = ctrl_reg & ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1229 reg |= E1000_CTRL_FRCSPD;
1232 ew32(CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_SPD_BYPS);
1234 ew32(CTRL, ctrl_reg);
1235 ew32(CTRL_EXT, ctrl_ext);
1243 * e1000_oem_bits_config_ich8lan - SW-based LCD Configuration
1244 * @hw: pointer to the HW structure
1245 * @d0_state: boolean if entering d0 or d3 device state
1247 * SW will configure Gbe Disable and LPLU based on the NVM. The four bits are
1248 * collectively called OEM bits. The OEM Write Enable bit and SW Config bit
1249 * in NVM determines whether HW should configure LPLU and Gbe Disable.
1251 static s32 e1000_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1257 if ((hw->mac.type != e1000_pch2lan) && (hw->mac.type != e1000_pchlan))
1260 ret_val = hw->phy.ops.acquire(hw);
1264 if (!(hw->mac.type == e1000_pch2lan)) {
1265 mac_reg = er32(EXTCNF_CTRL);
1266 if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1270 mac_reg = er32(FEXTNVM);
1271 if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
1274 mac_reg = er32(PHY_CTRL);
1276 ret_val = hw->phy.ops.read_reg_locked(hw, HV_OEM_BITS, &oem_reg);
1280 oem_reg &= ~(HV_OEM_BITS_GBE_DIS | HV_OEM_BITS_LPLU);
1283 if (mac_reg & E1000_PHY_CTRL_GBE_DISABLE)
1284 oem_reg |= HV_OEM_BITS_GBE_DIS;
1286 if (mac_reg & E1000_PHY_CTRL_D0A_LPLU)
1287 oem_reg |= HV_OEM_BITS_LPLU;
1289 if (mac_reg & E1000_PHY_CTRL_NOND0A_GBE_DISABLE)
1290 oem_reg |= HV_OEM_BITS_GBE_DIS;
1292 if (mac_reg & E1000_PHY_CTRL_NOND0A_LPLU)
1293 oem_reg |= HV_OEM_BITS_LPLU;
1295 /* Restart auto-neg to activate the bits */
1296 if (!e1000_check_reset_block(hw))
1297 oem_reg |= HV_OEM_BITS_RESTART_AN;
1298 ret_val = hw->phy.ops.write_reg_locked(hw, HV_OEM_BITS, oem_reg);
1301 hw->phy.ops.release(hw);
1308 * e1000_set_mdio_slow_mode_hv - Set slow MDIO access mode
1309 * @hw: pointer to the HW structure
1311 static s32 e1000_set_mdio_slow_mode_hv(struct e1000_hw *hw)
1316 ret_val = e1e_rphy(hw, HV_KMRN_MODE_CTRL, &data);
1320 data |= HV_KMRN_MDIO_SLOW;
1322 ret_val = e1e_wphy(hw, HV_KMRN_MODE_CTRL, data);
1328 * e1000_hv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1329 * done after every PHY reset.
1331 static s32 e1000_hv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1336 if (hw->mac.type != e1000_pchlan)
1339 /* Set MDIO slow mode before any other MDIO access */
1340 if (hw->phy.type == e1000_phy_82577) {
1341 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1346 if (((hw->phy.type == e1000_phy_82577) &&
1347 ((hw->phy.revision == 1) || (hw->phy.revision == 2))) ||
1348 ((hw->phy.type == e1000_phy_82578) && (hw->phy.revision == 1))) {
1349 /* Disable generation of early preamble */
1350 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431);
1354 /* Preamble tuning for SSC */
1355 ret_val = e1e_wphy(hw, PHY_REG(770, 16), 0xA204);
1360 if (hw->phy.type == e1000_phy_82578) {
1362 * Return registers to default by doing a soft reset then
1363 * writing 0x3140 to the control register.
1365 if (hw->phy.revision < 2) {
1366 e1000e_phy_sw_reset(hw);
1367 ret_val = e1e_wphy(hw, PHY_CONTROL, 0x3140);
1372 ret_val = hw->phy.ops.acquire(hw);
1377 ret_val = e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, 0);
1378 hw->phy.ops.release(hw);
1383 * Configure the K1 Si workaround during phy reset assuming there is
1384 * link so that it disables K1 if link is in 1Gbps.
1386 ret_val = e1000_k1_gig_workaround_hv(hw, true);
1390 /* Workaround for link disconnects on a busy hub in half duplex */
1391 ret_val = hw->phy.ops.acquire(hw);
1394 ret_val = hw->phy.ops.read_reg_locked(hw, BM_PORT_GEN_CFG, &phy_data);
1397 ret_val = hw->phy.ops.write_reg_locked(hw, BM_PORT_GEN_CFG,
1400 hw->phy.ops.release(hw);
1406 * e1000_copy_rx_addrs_to_phy_ich8lan - Copy Rx addresses from MAC to PHY
1407 * @hw: pointer to the HW structure
1409 void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw)
1415 ret_val = hw->phy.ops.acquire(hw);
1418 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1422 /* Copy both RAL/H (rar_entry_count) and SHRAL/H (+4) to PHY */
1423 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1424 mac_reg = er32(RAL(i));
1425 hw->phy.ops.write_reg_page(hw, BM_RAR_L(i),
1426 (u16)(mac_reg & 0xFFFF));
1427 hw->phy.ops.write_reg_page(hw, BM_RAR_M(i),
1428 (u16)((mac_reg >> 16) & 0xFFFF));
1430 mac_reg = er32(RAH(i));
1431 hw->phy.ops.write_reg_page(hw, BM_RAR_H(i),
1432 (u16)(mac_reg & 0xFFFF));
1433 hw->phy.ops.write_reg_page(hw, BM_RAR_CTRL(i),
1434 (u16)((mac_reg & E1000_RAH_AV)
1438 e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
1441 hw->phy.ops.release(hw);
1445 * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation
1447 * @hw: pointer to the HW structure
1448 * @enable: flag to enable/disable workaround when enabling/disabling jumbos
1450 s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable)
1457 if (hw->mac.type != e1000_pch2lan)
1460 /* disable Rx path while enabling/disabling workaround */
1461 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg);
1462 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | (1 << 14));
1468 * Write Rx addresses (rar_entry_count for RAL/H, +4 for
1469 * SHRAL/H) and initial CRC values to the MAC
1471 for (i = 0; i < (hw->mac.rar_entry_count + 4); i++) {
1472 u8 mac_addr[ETH_ALEN] = {0};
1473 u32 addr_high, addr_low;
1475 addr_high = er32(RAH(i));
1476 if (!(addr_high & E1000_RAH_AV))
1478 addr_low = er32(RAL(i));
1479 mac_addr[0] = (addr_low & 0xFF);
1480 mac_addr[1] = ((addr_low >> 8) & 0xFF);
1481 mac_addr[2] = ((addr_low >> 16) & 0xFF);
1482 mac_addr[3] = ((addr_low >> 24) & 0xFF);
1483 mac_addr[4] = (addr_high & 0xFF);
1484 mac_addr[5] = ((addr_high >> 8) & 0xFF);
1486 ew32(PCH_RAICC(i), ~ether_crc_le(ETH_ALEN, mac_addr));
1489 /* Write Rx addresses to the PHY */
1490 e1000_copy_rx_addrs_to_phy_ich8lan(hw);
1492 /* Enable jumbo frame workaround in the MAC */
1493 mac_reg = er32(FFLT_DBG);
1494 mac_reg &= ~(1 << 14);
1495 mac_reg |= (7 << 15);
1496 ew32(FFLT_DBG, mac_reg);
1498 mac_reg = er32(RCTL);
1499 mac_reg |= E1000_RCTL_SECRC;
1500 ew32(RCTL, mac_reg);
1502 ret_val = e1000e_read_kmrn_reg(hw,
1503 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1507 ret_val = e1000e_write_kmrn_reg(hw,
1508 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1512 ret_val = e1000e_read_kmrn_reg(hw,
1513 E1000_KMRNCTRLSTA_HD_CTRL,
1517 data &= ~(0xF << 8);
1519 ret_val = e1000e_write_kmrn_reg(hw,
1520 E1000_KMRNCTRLSTA_HD_CTRL,
1525 /* Enable jumbo frame workaround in the PHY */
1526 e1e_rphy(hw, PHY_REG(769, 23), &data);
1527 data &= ~(0x7F << 5);
1528 data |= (0x37 << 5);
1529 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1532 e1e_rphy(hw, PHY_REG(769, 16), &data);
1534 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1537 e1e_rphy(hw, PHY_REG(776, 20), &data);
1538 data &= ~(0x3FF << 2);
1539 data |= (0x1A << 2);
1540 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1543 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0xFE00);
1546 e1e_rphy(hw, HV_PM_CTRL, &data);
1547 ret_val = e1e_wphy(hw, HV_PM_CTRL, data | (1 << 10));
1551 /* Write MAC register values back to h/w defaults */
1552 mac_reg = er32(FFLT_DBG);
1553 mac_reg &= ~(0xF << 14);
1554 ew32(FFLT_DBG, mac_reg);
1556 mac_reg = er32(RCTL);
1557 mac_reg &= ~E1000_RCTL_SECRC;
1558 ew32(RCTL, mac_reg);
1560 ret_val = e1000e_read_kmrn_reg(hw,
1561 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1565 ret_val = e1000e_write_kmrn_reg(hw,
1566 E1000_KMRNCTRLSTA_CTRL_OFFSET,
1570 ret_val = e1000e_read_kmrn_reg(hw,
1571 E1000_KMRNCTRLSTA_HD_CTRL,
1575 data &= ~(0xF << 8);
1577 ret_val = e1000e_write_kmrn_reg(hw,
1578 E1000_KMRNCTRLSTA_HD_CTRL,
1583 /* Write PHY register values back to h/w defaults */
1584 e1e_rphy(hw, PHY_REG(769, 23), &data);
1585 data &= ~(0x7F << 5);
1586 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data);
1589 e1e_rphy(hw, PHY_REG(769, 16), &data);
1591 ret_val = e1e_wphy(hw, PHY_REG(769, 16), data);
1594 e1e_rphy(hw, PHY_REG(776, 20), &data);
1595 data &= ~(0x3FF << 2);
1597 ret_val = e1e_wphy(hw, PHY_REG(776, 20), data);
1600 ret_val = e1e_wphy(hw, PHY_REG(776, 23), 0x7E00);
1603 e1e_rphy(hw, HV_PM_CTRL, &data);
1604 ret_val = e1e_wphy(hw, HV_PM_CTRL, data & ~(1 << 10));
1609 /* re-enable Rx path after enabling/disabling workaround */
1610 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg & ~(1 << 14));
1617 * e1000_lv_phy_workarounds_ich8lan - A series of Phy workarounds to be
1618 * done after every PHY reset.
1620 static s32 e1000_lv_phy_workarounds_ich8lan(struct e1000_hw *hw)
1624 if (hw->mac.type != e1000_pch2lan)
1627 /* Set MDIO slow mode before any other MDIO access */
1628 ret_val = e1000_set_mdio_slow_mode_hv(hw);
1635 * e1000_k1_gig_workaround_lv - K1 Si workaround
1636 * @hw: pointer to the HW structure
1638 * Workaround to set the K1 beacon duration for 82579 parts
1640 static s32 e1000_k1_workaround_lv(struct e1000_hw *hw)
1646 if (hw->mac.type != e1000_pch2lan)
1649 /* Set K1 beacon duration based on 1Gbps speed or otherwise */
1650 ret_val = e1e_rphy(hw, HV_M_STATUS, &status_reg);
1654 if ((status_reg & (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE))
1655 == (HV_M_STATUS_LINK_UP | HV_M_STATUS_AUTONEG_COMPLETE)) {
1656 mac_reg = er32(FEXTNVM4);
1657 mac_reg &= ~E1000_FEXTNVM4_BEACON_DURATION_MASK;
1659 if (status_reg & HV_M_STATUS_SPEED_1000)
1660 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_8USEC;
1662 mac_reg |= E1000_FEXTNVM4_BEACON_DURATION_16USEC;
1664 ew32(FEXTNVM4, mac_reg);
1672 * e1000_gate_hw_phy_config_ich8lan - disable PHY config via hardware
1673 * @hw: pointer to the HW structure
1674 * @gate: boolean set to true to gate, false to ungate
1676 * Gate/ungate the automatic PHY configuration via hardware; perform
1677 * the configuration via software instead.
1679 static void e1000_gate_hw_phy_config_ich8lan(struct e1000_hw *hw, bool gate)
1683 if (hw->mac.type != e1000_pch2lan)
1686 extcnf_ctrl = er32(EXTCNF_CTRL);
1689 extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1691 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_GATE_PHY_CFG;
1693 ew32(EXTCNF_CTRL, extcnf_ctrl);
1698 * e1000_lan_init_done_ich8lan - Check for PHY config completion
1699 * @hw: pointer to the HW structure
1701 * Check the appropriate indication the MAC has finished configuring the
1702 * PHY after a software reset.
1704 static void e1000_lan_init_done_ich8lan(struct e1000_hw *hw)
1706 u32 data, loop = E1000_ICH8_LAN_INIT_TIMEOUT;
1708 /* Wait for basic configuration completes before proceeding */
1710 data = er32(STATUS);
1711 data &= E1000_STATUS_LAN_INIT_DONE;
1713 } while ((!data) && --loop);
1716 * If basic configuration is incomplete before the above loop
1717 * count reaches 0, loading the configuration from NVM will
1718 * leave the PHY in a bad state possibly resulting in no link.
1721 e_dbg("LAN_INIT_DONE not set, increase timeout\n");
1723 /* Clear the Init Done bit for the next init event */
1724 data = er32(STATUS);
1725 data &= ~E1000_STATUS_LAN_INIT_DONE;
1730 * e1000_post_phy_reset_ich8lan - Perform steps required after a PHY reset
1731 * @hw: pointer to the HW structure
1733 static s32 e1000_post_phy_reset_ich8lan(struct e1000_hw *hw)
1738 if (e1000_check_reset_block(hw))
1741 /* Allow time for h/w to get to quiescent state after reset */
1742 usleep_range(10000, 20000);
1744 /* Perform any necessary post-reset workarounds */
1745 switch (hw->mac.type) {
1747 ret_val = e1000_hv_phy_workarounds_ich8lan(hw);
1752 ret_val = e1000_lv_phy_workarounds_ich8lan(hw);
1760 /* Clear the host wakeup bit after lcd reset */
1761 if (hw->mac.type >= e1000_pchlan) {
1762 e1e_rphy(hw, BM_PORT_GEN_CFG, ®);
1763 reg &= ~BM_WUC_HOST_WU_BIT;
1764 e1e_wphy(hw, BM_PORT_GEN_CFG, reg);
1767 /* Configure the LCD with the extended configuration region in NVM */
1768 ret_val = e1000_sw_lcd_config_ich8lan(hw);
1772 /* Configure the LCD with the OEM bits in NVM */
1773 ret_val = e1000_oem_bits_config_ich8lan(hw, true);
1775 if (hw->mac.type == e1000_pch2lan) {
1776 /* Ungate automatic PHY configuration on non-managed 82579 */
1777 if (!(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) {
1778 usleep_range(10000, 20000);
1779 e1000_gate_hw_phy_config_ich8lan(hw, false);
1782 /* Set EEE LPI Update Timer to 200usec */
1783 ret_val = hw->phy.ops.acquire(hw);
1786 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_ADDR,
1787 I82579_LPI_UPDATE_TIMER);
1790 ret_val = hw->phy.ops.write_reg_locked(hw, I82579_EMI_DATA,
1793 hw->phy.ops.release(hw);
1801 * e1000_phy_hw_reset_ich8lan - Performs a PHY reset
1802 * @hw: pointer to the HW structure
1805 * This is a function pointer entry point called by drivers
1806 * or other shared routines.
1808 static s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw)
1812 /* Gate automatic PHY configuration by hardware on non-managed 82579 */
1813 if ((hw->mac.type == e1000_pch2lan) &&
1814 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
1815 e1000_gate_hw_phy_config_ich8lan(hw, true);
1817 ret_val = e1000e_phy_hw_reset_generic(hw);
1821 ret_val = e1000_post_phy_reset_ich8lan(hw);
1828 * e1000_set_lplu_state_pchlan - Set Low Power Link Up state
1829 * @hw: pointer to the HW structure
1830 * @active: true to enable LPLU, false to disable
1832 * Sets the LPLU state according to the active flag. For PCH, if OEM write
1833 * bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
1834 * the phy speed. This function will manually set the LPLU bit and restart
1835 * auto-neg as hw would do. D3 and D0 LPLU will call the same function
1836 * since it configures the same bit.
1838 static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
1843 ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
1848 oem_reg |= HV_OEM_BITS_LPLU;
1850 oem_reg &= ~HV_OEM_BITS_LPLU;
1852 oem_reg |= HV_OEM_BITS_RESTART_AN;
1853 ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
1860 * e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
1861 * @hw: pointer to the HW structure
1862 * @active: true to enable LPLU, false to disable
1864 * Sets the LPLU D0 state according to the active flag. When
1865 * activating LPLU this function also disables smart speed
1866 * and vice versa. LPLU will not be activated unless the
1867 * device autonegotiation advertisement meets standards of
1868 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1869 * This is a function pointer entry point only called by
1870 * PHY setup routines.
1872 static s32 e1000_set_d0_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1874 struct e1000_phy_info *phy = &hw->phy;
1879 if (phy->type == e1000_phy_ife)
1882 phy_ctrl = er32(PHY_CTRL);
1885 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU;
1886 ew32(PHY_CTRL, phy_ctrl);
1888 if (phy->type != e1000_phy_igp_3)
1892 * Call gig speed drop workaround on LPLU before accessing
1895 if (hw->mac.type == e1000_ich8lan)
1896 e1000e_gig_downshift_workaround_ich8lan(hw);
1898 /* When LPLU is enabled, we should disable SmartSpeed */
1899 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1900 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1901 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1905 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
1906 ew32(PHY_CTRL, phy_ctrl);
1908 if (phy->type != e1000_phy_igp_3)
1912 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1913 * during Dx states where the power conservation is most
1914 * important. During driver activity we should enable
1915 * SmartSpeed, so performance is maintained.
1917 if (phy->smart_speed == e1000_smart_speed_on) {
1918 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1923 data |= IGP01E1000_PSCFR_SMART_SPEED;
1924 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1928 } else if (phy->smart_speed == e1000_smart_speed_off) {
1929 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1934 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1935 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1946 * e1000_set_d3_lplu_state_ich8lan - Set Low Power Linkup D3 state
1947 * @hw: pointer to the HW structure
1948 * @active: true to enable LPLU, false to disable
1950 * Sets the LPLU D3 state according to the active flag. When
1951 * activating LPLU this function also disables smart speed
1952 * and vice versa. LPLU will not be activated unless the
1953 * device autonegotiation advertisement meets standards of
1954 * either 10 or 10/100 or 10/100/1000 at all duplexes.
1955 * This is a function pointer entry point only called by
1956 * PHY setup routines.
1958 static s32 e1000_set_d3_lplu_state_ich8lan(struct e1000_hw *hw, bool active)
1960 struct e1000_phy_info *phy = &hw->phy;
1965 phy_ctrl = er32(PHY_CTRL);
1968 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
1969 ew32(PHY_CTRL, phy_ctrl);
1971 if (phy->type != e1000_phy_igp_3)
1975 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1976 * during Dx states where the power conservation is most
1977 * important. During driver activity we should enable
1978 * SmartSpeed, so performance is maintained.
1980 if (phy->smart_speed == e1000_smart_speed_on) {
1981 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1986 data |= IGP01E1000_PSCFR_SMART_SPEED;
1987 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1991 } else if (phy->smart_speed == e1000_smart_speed_off) {
1992 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1997 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1998 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
2003 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
2004 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
2005 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
2006 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU;
2007 ew32(PHY_CTRL, phy_ctrl);
2009 if (phy->type != e1000_phy_igp_3)
2013 * Call gig speed drop workaround on LPLU before accessing
2016 if (hw->mac.type == e1000_ich8lan)
2017 e1000e_gig_downshift_workaround_ich8lan(hw);
2019 /* When LPLU is enabled, we should disable SmartSpeed */
2020 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
2024 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
2025 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
2032 * e1000_valid_nvm_bank_detect_ich8lan - finds out the valid bank 0 or 1
2033 * @hw: pointer to the HW structure
2034 * @bank: pointer to the variable that returns the active bank
2036 * Reads signature byte from the NVM using the flash access registers.
2037 * Word 0x13 bits 15:14 = 10b indicate a valid signature for that bank.
2039 static s32 e1000_valid_nvm_bank_detect_ich8lan(struct e1000_hw *hw, u32 *bank)
2042 struct e1000_nvm_info *nvm = &hw->nvm;
2043 u32 bank1_offset = nvm->flash_bank_size * sizeof(u16);
2044 u32 act_offset = E1000_ICH_NVM_SIG_WORD * 2 + 1;
2048 switch (hw->mac.type) {
2052 if ((eecd & E1000_EECD_SEC1VAL_VALID_MASK) ==
2053 E1000_EECD_SEC1VAL_VALID_MASK) {
2054 if (eecd & E1000_EECD_SEC1VAL)
2061 e_dbg("Unable to determine valid NVM bank via EEC - "
2062 "reading flash signature\n");
2065 /* set bank to 0 in case flash read fails */
2069 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset,
2073 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2074 E1000_ICH_NVM_SIG_VALUE) {
2080 ret_val = e1000_read_flash_byte_ich8lan(hw, act_offset +
2085 if ((sig_byte & E1000_ICH_NVM_VALID_SIG_MASK) ==
2086 E1000_ICH_NVM_SIG_VALUE) {
2091 e_dbg("ERROR: No valid NVM bank present\n");
2092 return -E1000_ERR_NVM;
2099 * e1000_read_nvm_ich8lan - Read word(s) from the NVM
2100 * @hw: pointer to the HW structure
2101 * @offset: The offset (in bytes) of the word(s) to read.
2102 * @words: Size of data to read in words
2103 * @data: Pointer to the word(s) to read at offset.
2105 * Reads a word(s) from the NVM using the flash access registers.
2107 static s32 e1000_read_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2110 struct e1000_nvm_info *nvm = &hw->nvm;
2111 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2117 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2119 e_dbg("nvm parameter(s) out of bounds\n");
2120 ret_val = -E1000_ERR_NVM;
2124 nvm->ops.acquire(hw);
2126 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2128 e_dbg("Could not detect valid bank, assuming bank 0\n");
2132 act_offset = (bank) ? nvm->flash_bank_size : 0;
2133 act_offset += offset;
2136 for (i = 0; i < words; i++) {
2137 if ((dev_spec->shadow_ram) &&
2138 (dev_spec->shadow_ram[offset+i].modified)) {
2139 data[i] = dev_spec->shadow_ram[offset+i].value;
2141 ret_val = e1000_read_flash_word_ich8lan(hw,
2150 nvm->ops.release(hw);
2154 e_dbg("NVM read error: %d\n", ret_val);
2160 * e1000_flash_cycle_init_ich8lan - Initialize flash
2161 * @hw: pointer to the HW structure
2163 * This function does initial flash setup so that a new read/write/erase cycle
2166 static s32 e1000_flash_cycle_init_ich8lan(struct e1000_hw *hw)
2168 union ich8_hws_flash_status hsfsts;
2169 s32 ret_val = -E1000_ERR_NVM;
2171 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2173 /* Check if the flash descriptor is valid */
2174 if (hsfsts.hsf_status.fldesvalid == 0) {
2175 e_dbg("Flash descriptor invalid. "
2176 "SW Sequencing must be used.\n");
2177 return -E1000_ERR_NVM;
2180 /* Clear FCERR and DAEL in hw status by writing 1 */
2181 hsfsts.hsf_status.flcerr = 1;
2182 hsfsts.hsf_status.dael = 1;
2184 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2187 * Either we should have a hardware SPI cycle in progress
2188 * bit to check against, in order to start a new cycle or
2189 * FDONE bit should be changed in the hardware so that it
2190 * is 1 after hardware reset, which can then be used as an
2191 * indication whether a cycle is in progress or has been
2195 if (hsfsts.hsf_status.flcinprog == 0) {
2197 * There is no cycle running at present,
2198 * so we can start a cycle.
2199 * Begin by setting Flash Cycle Done.
2201 hsfsts.hsf_status.flcdone = 1;
2202 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2208 * Otherwise poll for sometime so the current
2209 * cycle has a chance to end before giving up.
2211 for (i = 0; i < ICH_FLASH_READ_COMMAND_TIMEOUT; i++) {
2212 hsfsts.regval = __er16flash(hw, ICH_FLASH_HSFSTS);
2213 if (hsfsts.hsf_status.flcinprog == 0) {
2221 * Successful in waiting for previous cycle to timeout,
2222 * now set the Flash Cycle Done.
2224 hsfsts.hsf_status.flcdone = 1;
2225 ew16flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2227 e_dbg("Flash controller busy, cannot get access\n");
2235 * e1000_flash_cycle_ich8lan - Starts flash cycle (read/write/erase)
2236 * @hw: pointer to the HW structure
2237 * @timeout: maximum time to wait for completion
2239 * This function starts a flash cycle and waits for its completion.
2241 static s32 e1000_flash_cycle_ich8lan(struct e1000_hw *hw, u32 timeout)
2243 union ich8_hws_flash_ctrl hsflctl;
2244 union ich8_hws_flash_status hsfsts;
2245 s32 ret_val = -E1000_ERR_NVM;
2248 /* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
2249 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2250 hsflctl.hsf_ctrl.flcgo = 1;
2251 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2253 /* wait till FDONE bit is set to 1 */
2255 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2256 if (hsfsts.hsf_status.flcdone == 1)
2259 } while (i++ < timeout);
2261 if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0)
2268 * e1000_read_flash_word_ich8lan - Read word from flash
2269 * @hw: pointer to the HW structure
2270 * @offset: offset to data location
2271 * @data: pointer to the location for storing the data
2273 * Reads the flash word at offset into data. Offset is converted
2274 * to bytes before read.
2276 static s32 e1000_read_flash_word_ich8lan(struct e1000_hw *hw, u32 offset,
2279 /* Must convert offset into bytes. */
2282 return e1000_read_flash_data_ich8lan(hw, offset, 2, data);
2286 * e1000_read_flash_byte_ich8lan - Read byte from flash
2287 * @hw: pointer to the HW structure
2288 * @offset: The offset of the byte to read.
2289 * @data: Pointer to a byte to store the value read.
2291 * Reads a single byte from the NVM using the flash access registers.
2293 static s32 e1000_read_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2299 ret_val = e1000_read_flash_data_ich8lan(hw, offset, 1, &word);
2309 * e1000_read_flash_data_ich8lan - Read byte or word from NVM
2310 * @hw: pointer to the HW structure
2311 * @offset: The offset (in bytes) of the byte or word to read.
2312 * @size: Size of data to read, 1=byte 2=word
2313 * @data: Pointer to the word to store the value read.
2315 * Reads a byte or word from the NVM using the flash access registers.
2317 static s32 e1000_read_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2320 union ich8_hws_flash_status hsfsts;
2321 union ich8_hws_flash_ctrl hsflctl;
2322 u32 flash_linear_addr;
2324 s32 ret_val = -E1000_ERR_NVM;
2327 if (size < 1 || size > 2 || offset > ICH_FLASH_LINEAR_ADDR_MASK)
2328 return -E1000_ERR_NVM;
2330 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2331 hw->nvm.flash_base_addr;
2336 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2340 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2341 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2342 hsflctl.hsf_ctrl.fldbcount = size - 1;
2343 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
2344 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2346 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2348 ret_val = e1000_flash_cycle_ich8lan(hw,
2349 ICH_FLASH_READ_COMMAND_TIMEOUT);
2352 * Check if FCERR is set to 1, if set to 1, clear it
2353 * and try the whole sequence a few more times, else
2354 * read in (shift in) the Flash Data0, the order is
2355 * least significant byte first msb to lsb
2358 flash_data = er32flash(ICH_FLASH_FDATA0);
2360 *data = (u8)(flash_data & 0x000000FF);
2362 *data = (u16)(flash_data & 0x0000FFFF);
2366 * If we've gotten here, then things are probably
2367 * completely hosed, but if the error condition is
2368 * detected, it won't hurt to give it another try...
2369 * ICH_FLASH_CYCLE_REPEAT_COUNT times.
2371 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2372 if (hsfsts.hsf_status.flcerr == 1) {
2373 /* Repeat for some time before giving up. */
2375 } else if (hsfsts.hsf_status.flcdone == 0) {
2376 e_dbg("Timeout error - flash cycle "
2377 "did not complete.\n");
2381 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2387 * e1000_write_nvm_ich8lan - Write word(s) to the NVM
2388 * @hw: pointer to the HW structure
2389 * @offset: The offset (in bytes) of the word(s) to write.
2390 * @words: Size of data to write in words
2391 * @data: Pointer to the word(s) to write at offset.
2393 * Writes a byte or word to the NVM using the flash access registers.
2395 static s32 e1000_write_nvm_ich8lan(struct e1000_hw *hw, u16 offset, u16 words,
2398 struct e1000_nvm_info *nvm = &hw->nvm;
2399 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2402 if ((offset >= nvm->word_size) || (words > nvm->word_size - offset) ||
2404 e_dbg("nvm parameter(s) out of bounds\n");
2405 return -E1000_ERR_NVM;
2408 nvm->ops.acquire(hw);
2410 for (i = 0; i < words; i++) {
2411 dev_spec->shadow_ram[offset+i].modified = true;
2412 dev_spec->shadow_ram[offset+i].value = data[i];
2415 nvm->ops.release(hw);
2421 * e1000_update_nvm_checksum_ich8lan - Update the checksum for NVM
2422 * @hw: pointer to the HW structure
2424 * The NVM checksum is updated by calling the generic update_nvm_checksum,
2425 * which writes the checksum to the shadow ram. The changes in the shadow
2426 * ram are then committed to the EEPROM by processing each bank at a time
2427 * checking for the modified bit and writing only the pending changes.
2428 * After a successful commit, the shadow ram is cleared and is ready for
2431 static s32 e1000_update_nvm_checksum_ich8lan(struct e1000_hw *hw)
2433 struct e1000_nvm_info *nvm = &hw->nvm;
2434 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
2435 u32 i, act_offset, new_bank_offset, old_bank_offset, bank;
2439 ret_val = e1000e_update_nvm_checksum_generic(hw);
2443 if (nvm->type != e1000_nvm_flash_sw)
2446 nvm->ops.acquire(hw);
2449 * We're writing to the opposite bank so if we're on bank 1,
2450 * write to bank 0 etc. We also need to erase the segment that
2451 * is going to be written
2453 ret_val = e1000_valid_nvm_bank_detect_ich8lan(hw, &bank);
2455 e_dbg("Could not detect valid bank, assuming bank 0\n");
2460 new_bank_offset = nvm->flash_bank_size;
2461 old_bank_offset = 0;
2462 ret_val = e1000_erase_flash_bank_ich8lan(hw, 1);
2466 old_bank_offset = nvm->flash_bank_size;
2467 new_bank_offset = 0;
2468 ret_val = e1000_erase_flash_bank_ich8lan(hw, 0);
2473 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2475 * Determine whether to write the value stored
2476 * in the other NVM bank or a modified value stored
2479 if (dev_spec->shadow_ram[i].modified) {
2480 data = dev_spec->shadow_ram[i].value;
2482 ret_val = e1000_read_flash_word_ich8lan(hw, i +
2490 * If the word is 0x13, then make sure the signature bits
2491 * (15:14) are 11b until the commit has completed.
2492 * This will allow us to write 10b which indicates the
2493 * signature is valid. We want to do this after the write
2494 * has completed so that we don't mark the segment valid
2495 * while the write is still in progress
2497 if (i == E1000_ICH_NVM_SIG_WORD)
2498 data |= E1000_ICH_NVM_SIG_MASK;
2500 /* Convert offset to bytes. */
2501 act_offset = (i + new_bank_offset) << 1;
2504 /* Write the bytes to the new bank. */
2505 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2512 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2520 * Don't bother writing the segment valid bits if sector
2521 * programming failed.
2524 /* Possibly read-only, see e1000e_write_protect_nvm_ich8lan() */
2525 e_dbg("Flash commit failed.\n");
2530 * Finally validate the new segment by setting bit 15:14
2531 * to 10b in word 0x13 , this can be done without an
2532 * erase as well since these bits are 11 to start with
2533 * and we need to change bit 14 to 0b
2535 act_offset = new_bank_offset + E1000_ICH_NVM_SIG_WORD;
2536 ret_val = e1000_read_flash_word_ich8lan(hw, act_offset, &data);
2541 ret_val = e1000_retry_write_flash_byte_ich8lan(hw,
2548 * And invalidate the previously valid segment by setting
2549 * its signature word (0x13) high_byte to 0b. This can be
2550 * done without an erase because flash erase sets all bits
2551 * to 1's. We can write 1's to 0's without an erase
2553 act_offset = (old_bank_offset + E1000_ICH_NVM_SIG_WORD) * 2 + 1;
2554 ret_val = e1000_retry_write_flash_byte_ich8lan(hw, act_offset, 0);
2558 /* Great! Everything worked, we can now clear the cached entries. */
2559 for (i = 0; i < E1000_ICH8_SHADOW_RAM_WORDS; i++) {
2560 dev_spec->shadow_ram[i].modified = false;
2561 dev_spec->shadow_ram[i].value = 0xFFFF;
2565 nvm->ops.release(hw);
2568 * Reload the EEPROM, or else modifications will not appear
2569 * until after the next adapter reset.
2572 e1000e_reload_nvm(hw);
2573 usleep_range(10000, 20000);
2578 e_dbg("NVM update error: %d\n", ret_val);
2584 * e1000_validate_nvm_checksum_ich8lan - Validate EEPROM checksum
2585 * @hw: pointer to the HW structure
2587 * Check to see if checksum needs to be fixed by reading bit 6 in word 0x19.
2588 * If the bit is 0, that the EEPROM had been modified, but the checksum was not
2589 * calculated, in which case we need to calculate the checksum and set bit 6.
2591 static s32 e1000_validate_nvm_checksum_ich8lan(struct e1000_hw *hw)
2597 * Read 0x19 and check bit 6. If this bit is 0, the checksum
2598 * needs to be fixed. This bit is an indication that the NVM
2599 * was prepared by OEM software and did not calculate the
2600 * checksum...a likely scenario.
2602 ret_val = e1000_read_nvm(hw, 0x19, 1, &data);
2606 if ((data & 0x40) == 0) {
2608 ret_val = e1000_write_nvm(hw, 0x19, 1, &data);
2611 ret_val = e1000e_update_nvm_checksum(hw);
2616 return e1000e_validate_nvm_checksum_generic(hw);
2620 * e1000e_write_protect_nvm_ich8lan - Make the NVM read-only
2621 * @hw: pointer to the HW structure
2623 * To prevent malicious write/erase of the NVM, set it to be read-only
2624 * so that the hardware ignores all write/erase cycles of the NVM via
2625 * the flash control registers. The shadow-ram copy of the NVM will
2626 * still be updated, however any updates to this copy will not stick
2627 * across driver reloads.
2629 void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw)
2631 struct e1000_nvm_info *nvm = &hw->nvm;
2632 union ich8_flash_protected_range pr0;
2633 union ich8_hws_flash_status hsfsts;
2636 nvm->ops.acquire(hw);
2638 gfpreg = er32flash(ICH_FLASH_GFPREG);
2640 /* Write-protect GbE Sector of NVM */
2641 pr0.regval = er32flash(ICH_FLASH_PR0);
2642 pr0.range.base = gfpreg & FLASH_GFPREG_BASE_MASK;
2643 pr0.range.limit = ((gfpreg >> 16) & FLASH_GFPREG_BASE_MASK);
2644 pr0.range.wpe = true;
2645 ew32flash(ICH_FLASH_PR0, pr0.regval);
2648 * Lock down a subset of GbE Flash Control Registers, e.g.
2649 * PR0 to prevent the write-protection from being lifted.
2650 * Once FLOCKDN is set, the registers protected by it cannot
2651 * be written until FLOCKDN is cleared by a hardware reset.
2653 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2654 hsfsts.hsf_status.flockdn = true;
2655 ew32flash(ICH_FLASH_HSFSTS, hsfsts.regval);
2657 nvm->ops.release(hw);
2661 * e1000_write_flash_data_ich8lan - Writes bytes to the NVM
2662 * @hw: pointer to the HW structure
2663 * @offset: The offset (in bytes) of the byte/word to read.
2664 * @size: Size of data to read, 1=byte 2=word
2665 * @data: The byte(s) to write to the NVM.
2667 * Writes one/two bytes to the NVM using the flash access registers.
2669 static s32 e1000_write_flash_data_ich8lan(struct e1000_hw *hw, u32 offset,
2672 union ich8_hws_flash_status hsfsts;
2673 union ich8_hws_flash_ctrl hsflctl;
2674 u32 flash_linear_addr;
2679 if (size < 1 || size > 2 || data > size * 0xff ||
2680 offset > ICH_FLASH_LINEAR_ADDR_MASK)
2681 return -E1000_ERR_NVM;
2683 flash_linear_addr = (ICH_FLASH_LINEAR_ADDR_MASK & offset) +
2684 hw->nvm.flash_base_addr;
2689 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2693 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2694 /* 0b/1b corresponds to 1 or 2 byte size, respectively. */
2695 hsflctl.hsf_ctrl.fldbcount = size -1;
2696 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
2697 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2699 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2702 flash_data = (u32)data & 0x00FF;
2704 flash_data = (u32)data;
2706 ew32flash(ICH_FLASH_FDATA0, flash_data);
2709 * check if FCERR is set to 1 , if set to 1, clear it
2710 * and try the whole sequence a few more times else done
2712 ret_val = e1000_flash_cycle_ich8lan(hw,
2713 ICH_FLASH_WRITE_COMMAND_TIMEOUT);
2718 * If we're here, then things are most likely
2719 * completely hosed, but if the error condition
2720 * is detected, it won't hurt to give it another
2721 * try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
2723 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2724 if (hsfsts.hsf_status.flcerr == 1)
2725 /* Repeat for some time before giving up. */
2727 if (hsfsts.hsf_status.flcdone == 0) {
2728 e_dbg("Timeout error - flash cycle "
2729 "did not complete.");
2732 } while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
2738 * e1000_write_flash_byte_ich8lan - Write a single byte to NVM
2739 * @hw: pointer to the HW structure
2740 * @offset: The index of the byte to read.
2741 * @data: The byte to write to the NVM.
2743 * Writes a single byte to the NVM using the flash access registers.
2745 static s32 e1000_write_flash_byte_ich8lan(struct e1000_hw *hw, u32 offset,
2748 u16 word = (u16)data;
2750 return e1000_write_flash_data_ich8lan(hw, offset, 1, word);
2754 * e1000_retry_write_flash_byte_ich8lan - Writes a single byte to NVM
2755 * @hw: pointer to the HW structure
2756 * @offset: The offset of the byte to write.
2757 * @byte: The byte to write to the NVM.
2759 * Writes a single byte to the NVM using the flash access registers.
2760 * Goes through a retry algorithm before giving up.
2762 static s32 e1000_retry_write_flash_byte_ich8lan(struct e1000_hw *hw,
2763 u32 offset, u8 byte)
2766 u16 program_retries;
2768 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2772 for (program_retries = 0; program_retries < 100; program_retries++) {
2773 e_dbg("Retrying Byte %2.2X at offset %u\n", byte, offset);
2775 ret_val = e1000_write_flash_byte_ich8lan(hw, offset, byte);
2779 if (program_retries == 100)
2780 return -E1000_ERR_NVM;
2786 * e1000_erase_flash_bank_ich8lan - Erase a bank (4k) from NVM
2787 * @hw: pointer to the HW structure
2788 * @bank: 0 for first bank, 1 for second bank, etc.
2790 * Erases the bank specified. Each bank is a 4k block. Banks are 0 based.
2791 * bank N is 4096 * N + flash_reg_addr.
2793 static s32 e1000_erase_flash_bank_ich8lan(struct e1000_hw *hw, u32 bank)
2795 struct e1000_nvm_info *nvm = &hw->nvm;
2796 union ich8_hws_flash_status hsfsts;
2797 union ich8_hws_flash_ctrl hsflctl;
2798 u32 flash_linear_addr;
2799 /* bank size is in 16bit words - adjust to bytes */
2800 u32 flash_bank_size = nvm->flash_bank_size * 2;
2803 s32 j, iteration, sector_size;
2805 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2808 * Determine HW Sector size: Read BERASE bits of hw flash status
2810 * 00: The Hw sector is 256 bytes, hence we need to erase 16
2811 * consecutive sectors. The start index for the nth Hw sector
2812 * can be calculated as = bank * 4096 + n * 256
2813 * 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
2814 * The start index for the nth Hw sector can be calculated
2816 * 10: The Hw sector is 8K bytes, nth sector = bank * 8192
2817 * (ich9 only, otherwise error condition)
2818 * 11: The Hw sector is 64K bytes, nth sector = bank * 65536
2820 switch (hsfsts.hsf_status.berasesz) {
2822 /* Hw sector size 256 */
2823 sector_size = ICH_FLASH_SEG_SIZE_256;
2824 iteration = flash_bank_size / ICH_FLASH_SEG_SIZE_256;
2827 sector_size = ICH_FLASH_SEG_SIZE_4K;
2831 sector_size = ICH_FLASH_SEG_SIZE_8K;
2835 sector_size = ICH_FLASH_SEG_SIZE_64K;
2839 return -E1000_ERR_NVM;
2842 /* Start with the base address, then add the sector offset. */
2843 flash_linear_addr = hw->nvm.flash_base_addr;
2844 flash_linear_addr += (bank) ? flash_bank_size : 0;
2846 for (j = 0; j < iteration ; j++) {
2849 ret_val = e1000_flash_cycle_init_ich8lan(hw);
2854 * Write a value 11 (block Erase) in Flash
2855 * Cycle field in hw flash control
2857 hsflctl.regval = er16flash(ICH_FLASH_HSFCTL);
2858 hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
2859 ew16flash(ICH_FLASH_HSFCTL, hsflctl.regval);
2862 * Write the last 24 bits of an index within the
2863 * block into Flash Linear address field in Flash
2866 flash_linear_addr += (j * sector_size);
2867 ew32flash(ICH_FLASH_FADDR, flash_linear_addr);
2869 ret_val = e1000_flash_cycle_ich8lan(hw,
2870 ICH_FLASH_ERASE_COMMAND_TIMEOUT);
2875 * Check if FCERR is set to 1. If 1,
2876 * clear it and try the whole sequence
2877 * a few more times else Done
2879 hsfsts.regval = er16flash(ICH_FLASH_HSFSTS);
2880 if (hsfsts.hsf_status.flcerr == 1)
2881 /* repeat for some time before giving up */
2883 else if (hsfsts.hsf_status.flcdone == 0)
2885 } while (++count < ICH_FLASH_CYCLE_REPEAT_COUNT);
2892 * e1000_valid_led_default_ich8lan - Set the default LED settings
2893 * @hw: pointer to the HW structure
2894 * @data: Pointer to the LED settings
2896 * Reads the LED default settings from the NVM to data. If the NVM LED
2897 * settings is all 0's or F's, set the LED default to a valid LED default
2900 static s32 e1000_valid_led_default_ich8lan(struct e1000_hw *hw, u16 *data)
2904 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
2906 e_dbg("NVM Read Error\n");
2910 if (*data == ID_LED_RESERVED_0000 ||
2911 *data == ID_LED_RESERVED_FFFF)
2912 *data = ID_LED_DEFAULT_ICH8LAN;
2918 * e1000_id_led_init_pchlan - store LED configurations
2919 * @hw: pointer to the HW structure
2921 * PCH does not control LEDs via the LEDCTL register, rather it uses
2922 * the PHY LED configuration register.
2924 * PCH also does not have an "always on" or "always off" mode which
2925 * complicates the ID feature. Instead of using the "on" mode to indicate
2926 * in ledctl_mode2 the LEDs to use for ID (see e1000e_id_led_init()),
2927 * use "link_up" mode. The LEDs will still ID on request if there is no
2928 * link based on logic in e1000_led_[on|off]_pchlan().
2930 static s32 e1000_id_led_init_pchlan(struct e1000_hw *hw)
2932 struct e1000_mac_info *mac = &hw->mac;
2934 const u32 ledctl_on = E1000_LEDCTL_MODE_LINK_UP;
2935 const u32 ledctl_off = E1000_LEDCTL_MODE_LINK_UP | E1000_PHY_LED0_IVRT;
2936 u16 data, i, temp, shift;
2938 /* Get default ID LED modes */
2939 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
2943 mac->ledctl_default = er32(LEDCTL);
2944 mac->ledctl_mode1 = mac->ledctl_default;
2945 mac->ledctl_mode2 = mac->ledctl_default;
2947 for (i = 0; i < 4; i++) {
2948 temp = (data >> (i << 2)) & E1000_LEDCTL_LED0_MODE_MASK;
2951 case ID_LED_ON1_DEF2:
2952 case ID_LED_ON1_ON2:
2953 case ID_LED_ON1_OFF2:
2954 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2955 mac->ledctl_mode1 |= (ledctl_on << shift);
2957 case ID_LED_OFF1_DEF2:
2958 case ID_LED_OFF1_ON2:
2959 case ID_LED_OFF1_OFF2:
2960 mac->ledctl_mode1 &= ~(E1000_PHY_LED0_MASK << shift);
2961 mac->ledctl_mode1 |= (ledctl_off << shift);
2968 case ID_LED_DEF1_ON2:
2969 case ID_LED_ON1_ON2:
2970 case ID_LED_OFF1_ON2:
2971 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2972 mac->ledctl_mode2 |= (ledctl_on << shift);
2974 case ID_LED_DEF1_OFF2:
2975 case ID_LED_ON1_OFF2:
2976 case ID_LED_OFF1_OFF2:
2977 mac->ledctl_mode2 &= ~(E1000_PHY_LED0_MASK << shift);
2978 mac->ledctl_mode2 |= (ledctl_off << shift);
2991 * e1000_get_bus_info_ich8lan - Get/Set the bus type and width
2992 * @hw: pointer to the HW structure
2994 * ICH8 use the PCI Express bus, but does not contain a PCI Express Capability
2995 * register, so the the bus width is hard coded.
2997 static s32 e1000_get_bus_info_ich8lan(struct e1000_hw *hw)
2999 struct e1000_bus_info *bus = &hw->bus;
3002 ret_val = e1000e_get_bus_info_pcie(hw);
3005 * ICH devices are "PCI Express"-ish. They have
3006 * a configuration space, but do not contain
3007 * PCI Express Capability registers, so bus width
3008 * must be hardcoded.
3010 if (bus->width == e1000_bus_width_unknown)
3011 bus->width = e1000_bus_width_pcie_x1;
3017 * e1000_reset_hw_ich8lan - Reset the hardware
3018 * @hw: pointer to the HW structure
3020 * Does a full reset of the hardware which includes a reset of the PHY and
3023 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw)
3025 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3031 * Prevent the PCI-E bus from sticking if there is no TLP connection
3032 * on the last TLP read/write transaction when MAC is reset.
3034 ret_val = e1000e_disable_pcie_master(hw);
3036 e_dbg("PCI-E Master disable polling has failed.\n");
3038 e_dbg("Masking off all interrupts\n");
3039 ew32(IMC, 0xffffffff);
3042 * Disable the Transmit and Receive units. Then delay to allow
3043 * any pending transactions to complete before we hit the MAC
3044 * with the global reset.
3047 ew32(TCTL, E1000_TCTL_PSP);
3050 usleep_range(10000, 20000);
3052 /* Workaround for ICH8 bit corruption issue in FIFO memory */
3053 if (hw->mac.type == e1000_ich8lan) {
3054 /* Set Tx and Rx buffer allocation to 8k apiece. */
3055 ew32(PBA, E1000_PBA_8K);
3056 /* Set Packet Buffer Size to 16k. */
3057 ew32(PBS, E1000_PBS_16K);
3060 if (hw->mac.type == e1000_pchlan) {
3061 /* Save the NVM K1 bit setting*/
3062 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, ®);
3066 if (reg & E1000_NVM_K1_ENABLE)
3067 dev_spec->nvm_k1_enabled = true;
3069 dev_spec->nvm_k1_enabled = false;
3074 if (!e1000_check_reset_block(hw)) {
3076 * Full-chip reset requires MAC and PHY reset at the same
3077 * time to make sure the interface between MAC and the
3078 * external PHY is reset.
3080 ctrl |= E1000_CTRL_PHY_RST;
3083 * Gate automatic PHY configuration by hardware on
3086 if ((hw->mac.type == e1000_pch2lan) &&
3087 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID))
3088 e1000_gate_hw_phy_config_ich8lan(hw, true);
3090 ret_val = e1000_acquire_swflag_ich8lan(hw);
3091 e_dbg("Issuing a global reset to ich8lan\n");
3092 ew32(CTRL, (ctrl | E1000_CTRL_RST));
3096 mutex_unlock(&swflag_mutex);
3098 if (ctrl & E1000_CTRL_PHY_RST) {
3099 ret_val = hw->phy.ops.get_cfg_done(hw);
3103 ret_val = e1000_post_phy_reset_ich8lan(hw);
3109 * For PCH, this write will make sure that any noise
3110 * will be detected as a CRC error and be dropped rather than show up
3111 * as a bad packet to the DMA engine.
3113 if (hw->mac.type == e1000_pchlan)
3114 ew32(CRC_OFFSET, 0x65656565);
3116 ew32(IMC, 0xffffffff);
3119 kab = er32(KABGTXD);
3120 kab |= E1000_KABGTXD_BGSQLBIAS;
3128 * e1000_init_hw_ich8lan - Initialize the hardware
3129 * @hw: pointer to the HW structure
3131 * Prepares the hardware for transmit and receive by doing the following:
3132 * - initialize hardware bits
3133 * - initialize LED identification
3134 * - setup receive address registers
3135 * - setup flow control
3136 * - setup transmit descriptors
3137 * - clear statistics
3139 static s32 e1000_init_hw_ich8lan(struct e1000_hw *hw)
3141 struct e1000_mac_info *mac = &hw->mac;
3142 u32 ctrl_ext, txdctl, snoop;
3146 e1000_initialize_hw_bits_ich8lan(hw);
3148 /* Initialize identification LED */
3149 ret_val = mac->ops.id_led_init(hw);
3151 e_dbg("Error initializing identification LED\n");
3152 /* This is not fatal and we should not stop init due to this */
3154 /* Setup the receive address. */
3155 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
3157 /* Zero out the Multicast HASH table */
3158 e_dbg("Zeroing the MTA\n");
3159 for (i = 0; i < mac->mta_reg_count; i++)
3160 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
3163 * The 82578 Rx buffer will stall if wakeup is enabled in host and
3164 * the ME. Disable wakeup by clearing the host wakeup bit.
3165 * Reset the phy after disabling host wakeup to reset the Rx buffer.
3167 if (hw->phy.type == e1000_phy_82578) {
3168 e1e_rphy(hw, BM_PORT_GEN_CFG, &i);
3169 i &= ~BM_WUC_HOST_WU_BIT;
3170 e1e_wphy(hw, BM_PORT_GEN_CFG, i);
3171 ret_val = e1000_phy_hw_reset_ich8lan(hw);
3176 /* Setup link and flow control */
3177 ret_val = e1000_setup_link_ich8lan(hw);
3179 /* Set the transmit descriptor write-back policy for both queues */
3180 txdctl = er32(TXDCTL(0));
3181 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3182 E1000_TXDCTL_FULL_TX_DESC_WB;
3183 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3184 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3185 ew32(TXDCTL(0), txdctl);
3186 txdctl = er32(TXDCTL(1));
3187 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
3188 E1000_TXDCTL_FULL_TX_DESC_WB;
3189 txdctl = (txdctl & ~E1000_TXDCTL_PTHRESH) |
3190 E1000_TXDCTL_MAX_TX_DESC_PREFETCH;
3191 ew32(TXDCTL(1), txdctl);
3194 * ICH8 has opposite polarity of no_snoop bits.
3195 * By default, we should use snoop behavior.
3197 if (mac->type == e1000_ich8lan)
3198 snoop = PCIE_ICH8_SNOOP_ALL;
3200 snoop = (u32) ~(PCIE_NO_SNOOP_ALL);
3201 e1000e_set_pcie_no_snoop(hw, snoop);
3203 ctrl_ext = er32(CTRL_EXT);
3204 ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
3205 ew32(CTRL_EXT, ctrl_ext);
3208 * Clear all of the statistics registers (clear on read). It is
3209 * important that we do this after we have tried to establish link
3210 * because the symbol error count will increment wildly if there
3213 e1000_clear_hw_cntrs_ich8lan(hw);
3218 * e1000_initialize_hw_bits_ich8lan - Initialize required hardware bits
3219 * @hw: pointer to the HW structure
3221 * Sets/Clears required hardware bits necessary for correctly setting up the
3222 * hardware for transmit and receive.
3224 static void e1000_initialize_hw_bits_ich8lan(struct e1000_hw *hw)
3228 /* Extended Device Control */
3229 reg = er32(CTRL_EXT);
3231 /* Enable PHY low-power state when MAC is at D3 w/o WoL */
3232 if (hw->mac.type >= e1000_pchlan)
3233 reg |= E1000_CTRL_EXT_PHYPDEN;
3234 ew32(CTRL_EXT, reg);
3236 /* Transmit Descriptor Control 0 */
3237 reg = er32(TXDCTL(0));
3239 ew32(TXDCTL(0), reg);
3241 /* Transmit Descriptor Control 1 */
3242 reg = er32(TXDCTL(1));
3244 ew32(TXDCTL(1), reg);
3246 /* Transmit Arbitration Control 0 */
3247 reg = er32(TARC(0));
3248 if (hw->mac.type == e1000_ich8lan)
3249 reg |= (1 << 28) | (1 << 29);
3250 reg |= (1 << 23) | (1 << 24) | (1 << 26) | (1 << 27);
3253 /* Transmit Arbitration Control 1 */
3254 reg = er32(TARC(1));
3255 if (er32(TCTL) & E1000_TCTL_MULR)
3259 reg |= (1 << 24) | (1 << 26) | (1 << 30);
3263 if (hw->mac.type == e1000_ich8lan) {
3270 * work-around descriptor data corruption issue during nfs v2 udp
3271 * traffic, just disable the nfs filtering capability
3274 reg |= (E1000_RFCTL_NFSW_DIS | E1000_RFCTL_NFSR_DIS);
3279 * e1000_setup_link_ich8lan - Setup flow control and link settings
3280 * @hw: pointer to the HW structure
3282 * Determines which flow control settings to use, then configures flow
3283 * control. Calls the appropriate media-specific link configuration
3284 * function. Assuming the adapter has a valid link partner, a valid link
3285 * should be established. Assumes the hardware has previously been reset
3286 * and the transmitter and receiver are not enabled.
3288 static s32 e1000_setup_link_ich8lan(struct e1000_hw *hw)
3292 if (e1000_check_reset_block(hw))
3296 * ICH parts do not have a word in the NVM to determine
3297 * the default flow control setting, so we explicitly
3300 if (hw->fc.requested_mode == e1000_fc_default) {
3301 /* Workaround h/w hang when Tx flow control enabled */
3302 if (hw->mac.type == e1000_pchlan)
3303 hw->fc.requested_mode = e1000_fc_rx_pause;
3305 hw->fc.requested_mode = e1000_fc_full;
3309 * Save off the requested flow control mode for use later. Depending
3310 * on the link partner's capabilities, we may or may not use this mode.
3312 hw->fc.current_mode = hw->fc.requested_mode;
3314 e_dbg("After fix-ups FlowControl is now = %x\n",
3315 hw->fc.current_mode);
3317 /* Continue to configure the copper link. */
3318 ret_val = e1000_setup_copper_link_ich8lan(hw);
3322 ew32(FCTTV, hw->fc.pause_time);
3323 if ((hw->phy.type == e1000_phy_82578) ||
3324 (hw->phy.type == e1000_phy_82579) ||
3325 (hw->phy.type == e1000_phy_82577)) {
3326 ew32(FCRTV_PCH, hw->fc.refresh_time);
3328 ret_val = e1e_wphy(hw, PHY_REG(BM_PORT_CTRL_PAGE, 27),
3334 return e1000e_set_fc_watermarks(hw);
3338 * e1000_setup_copper_link_ich8lan - Configure MAC/PHY interface
3339 * @hw: pointer to the HW structure
3341 * Configures the kumeran interface to the PHY to wait the appropriate time
3342 * when polling the PHY, then call the generic setup_copper_link to finish
3343 * configuring the copper link.
3345 static s32 e1000_setup_copper_link_ich8lan(struct e1000_hw *hw)
3352 ctrl |= E1000_CTRL_SLU;
3353 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
3357 * Set the mac to wait the maximum time between each iteration
3358 * and increase the max iterations when polling the phy;
3359 * this fixes erroneous timeouts at 10Mbps.
3361 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_TIMEOUTS, 0xFFFF);
3364 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3369 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
3374 switch (hw->phy.type) {
3375 case e1000_phy_igp_3:
3376 ret_val = e1000e_copper_link_setup_igp(hw);
3381 case e1000_phy_82578:
3382 ret_val = e1000e_copper_link_setup_m88(hw);
3386 case e1000_phy_82577:
3387 case e1000_phy_82579:
3388 ret_val = e1000_copper_link_setup_82577(hw);
3393 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, ®_data);
3397 reg_data &= ~IFE_PMC_AUTO_MDIX;
3399 switch (hw->phy.mdix) {
3401 reg_data &= ~IFE_PMC_FORCE_MDIX;
3404 reg_data |= IFE_PMC_FORCE_MDIX;
3408 reg_data |= IFE_PMC_AUTO_MDIX;
3411 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, reg_data);
3418 return e1000e_setup_copper_link(hw);
3422 * e1000_get_link_up_info_ich8lan - Get current link speed and duplex
3423 * @hw: pointer to the HW structure
3424 * @speed: pointer to store current link speed
3425 * @duplex: pointer to store the current link duplex
3427 * Calls the generic get_speed_and_duplex to retrieve the current link
3428 * information and then calls the Kumeran lock loss workaround for links at
3431 static s32 e1000_get_link_up_info_ich8lan(struct e1000_hw *hw, u16 *speed,
3436 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
3440 if ((hw->mac.type == e1000_ich8lan) &&
3441 (hw->phy.type == e1000_phy_igp_3) &&
3442 (*speed == SPEED_1000)) {
3443 ret_val = e1000_kmrn_lock_loss_workaround_ich8lan(hw);
3450 * e1000_kmrn_lock_loss_workaround_ich8lan - Kumeran workaround
3451 * @hw: pointer to the HW structure
3453 * Work-around for 82566 Kumeran PCS lock loss:
3454 * On link status change (i.e. PCI reset, speed change) and link is up and
3456 * 0) if workaround is optionally disabled do nothing
3457 * 1) wait 1ms for Kumeran link to come up
3458 * 2) check Kumeran Diagnostic register PCS lock loss bit
3459 * 3) if not set the link is locked (all is good), otherwise...
3461 * 5) repeat up to 10 times
3462 * Note: this is only called for IGP3 copper when speed is 1gb.
3464 static s32 e1000_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw)
3466 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3472 if (!dev_spec->kmrn_lock_loss_workaround_enabled)
3476 * Make sure link is up before proceeding. If not just return.
3477 * Attempting this while link is negotiating fouled up link
3480 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3484 for (i = 0; i < 10; i++) {
3485 /* read once to clear */
3486 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3489 /* and again to get new status */
3490 ret_val = e1e_rphy(hw, IGP3_KMRN_DIAG, &data);
3494 /* check for PCS lock */
3495 if (!(data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
3498 /* Issue PHY reset */
3499 e1000_phy_hw_reset(hw);
3502 /* Disable GigE link negotiation */
3503 phy_ctrl = er32(PHY_CTRL);
3504 phy_ctrl |= (E1000_PHY_CTRL_GBE_DISABLE |
3505 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3506 ew32(PHY_CTRL, phy_ctrl);
3509 * Call gig speed drop workaround on Gig disable before accessing
3512 e1000e_gig_downshift_workaround_ich8lan(hw);
3514 /* unable to acquire PCS lock */
3515 return -E1000_ERR_PHY;
3519 * e1000_set_kmrn_lock_loss_workaround_ich8lan - Set Kumeran workaround state
3520 * @hw: pointer to the HW structure
3521 * @state: boolean value used to set the current Kumeran workaround state
3523 * If ICH8, set the current Kumeran workaround state (enabled - true
3524 * /disabled - false).
3526 void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
3529 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan;
3531 if (hw->mac.type != e1000_ich8lan) {
3532 e_dbg("Workaround applies to ICH8 only.\n");
3536 dev_spec->kmrn_lock_loss_workaround_enabled = state;
3540 * e1000_ipg3_phy_powerdown_workaround_ich8lan - Power down workaround on D3
3541 * @hw: pointer to the HW structure
3543 * Workaround for 82566 power-down on D3 entry:
3544 * 1) disable gigabit link
3545 * 2) write VR power-down enable
3547 * Continue if successful, else issue LCD reset and repeat
3549 void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw)
3555 if (hw->phy.type != e1000_phy_igp_3)
3558 /* Try the workaround twice (if needed) */
3561 reg = er32(PHY_CTRL);
3562 reg |= (E1000_PHY_CTRL_GBE_DISABLE |
3563 E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
3564 ew32(PHY_CTRL, reg);
3567 * Call gig speed drop workaround on Gig disable before
3568 * accessing any PHY registers
3570 if (hw->mac.type == e1000_ich8lan)
3571 e1000e_gig_downshift_workaround_ich8lan(hw);
3573 /* Write VR power-down enable */
3574 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3575 data &= ~IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3576 e1e_wphy(hw, IGP3_VR_CTRL, data | IGP3_VR_CTRL_MODE_SHUTDOWN);
3578 /* Read it back and test */
3579 e1e_rphy(hw, IGP3_VR_CTRL, &data);
3580 data &= IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK;
3581 if ((data == IGP3_VR_CTRL_MODE_SHUTDOWN) || retry)
3584 /* Issue PHY reset and repeat at most one more time */
3586 ew32(CTRL, reg | E1000_CTRL_PHY_RST);
3592 * e1000e_gig_downshift_workaround_ich8lan - WoL from S5 stops working
3593 * @hw: pointer to the HW structure
3595 * Steps to take when dropping from 1Gb/s (eg. link cable removal (LSC),
3596 * LPLU, Gig disable, MDIC PHY reset):
3597 * 1) Set Kumeran Near-end loopback
3598 * 2) Clear Kumeran Near-end loopback
3599 * Should only be called for ICH8[m] devices with IGP_3 Phy.
3601 void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw)
3606 if ((hw->mac.type != e1000_ich8lan) ||
3607 (hw->phy.type != e1000_phy_igp_3))
3610 ret_val = e1000e_read_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3614 reg_data |= E1000_KMRNCTRLSTA_DIAG_NELPBK;
3615 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3619 reg_data &= ~E1000_KMRNCTRLSTA_DIAG_NELPBK;
3620 ret_val = e1000e_write_kmrn_reg(hw, E1000_KMRNCTRLSTA_DIAG_OFFSET,
3625 * e1000_suspend_workarounds_ich8lan - workarounds needed during S0->Sx
3626 * @hw: pointer to the HW structure
3628 * During S0 to Sx transition, it is possible the link remains at gig
3629 * instead of negotiating to a lower speed. Before going to Sx, set
3630 * 'LPLU Enabled' and 'Gig Disable' to force link speed negotiation
3631 * to a lower speed. For PCH and newer parts, the OEM bits PHY register
3632 * (LED, GbE disable and LPLU configurations) also needs to be written.
3634 void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw)
3639 phy_ctrl = er32(PHY_CTRL);
3640 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU | E1000_PHY_CTRL_GBE_DISABLE;
3641 ew32(PHY_CTRL, phy_ctrl);
3643 if (hw->mac.type >= e1000_pchlan) {
3644 e1000_oem_bits_config_ich8lan(hw, false);
3645 ret_val = hw->phy.ops.acquire(hw);
3648 e1000_write_smbus_addr(hw);
3649 hw->phy.ops.release(hw);
3654 * e1000_resume_workarounds_pchlan - workarounds needed during Sx->S0
3655 * @hw: pointer to the HW structure
3657 * During Sx to S0 transitions on non-managed devices or managed devices
3658 * on which PHY resets are not blocked, if the PHY registers cannot be
3659 * accessed properly by the s/w toggle the LANPHYPC value to power cycle
3662 void e1000_resume_workarounds_pchlan(struct e1000_hw *hw)
3666 if (hw->mac.type != e1000_pch2lan)
3670 if (!(fwsm & E1000_ICH_FWSM_FW_VALID) || !e1000_check_reset_block(hw)) {
3671 u16 phy_id1, phy_id2;
3674 ret_val = hw->phy.ops.acquire(hw);
3676 e_dbg("Failed to acquire PHY semaphore in resume\n");
3680 /* Test access to the PHY registers by reading the ID regs */
3681 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID1, &phy_id1);
3684 ret_val = hw->phy.ops.read_reg_locked(hw, PHY_ID2, &phy_id2);
3688 if (hw->phy.id == ((u32)(phy_id1 << 16) |
3689 (u32)(phy_id2 & PHY_REVISION_MASK)))
3692 e1000_toggle_lanphypc_value_ich8lan(hw);
3694 hw->phy.ops.release(hw);
3696 e1000_phy_hw_reset(hw);
3702 hw->phy.ops.release(hw);
3708 * e1000_cleanup_led_ich8lan - Restore the default LED operation
3709 * @hw: pointer to the HW structure
3711 * Return the LED back to the default configuration.
3713 static s32 e1000_cleanup_led_ich8lan(struct e1000_hw *hw)
3715 if (hw->phy.type == e1000_phy_ife)
3716 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
3718 ew32(LEDCTL, hw->mac.ledctl_default);
3723 * e1000_led_on_ich8lan - Turn LEDs on
3724 * @hw: pointer to the HW structure
3728 static s32 e1000_led_on_ich8lan(struct e1000_hw *hw)
3730 if (hw->phy.type == e1000_phy_ife)
3731 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3732 (IFE_PSCL_PROBE_MODE | IFE_PSCL_PROBE_LEDS_ON));
3734 ew32(LEDCTL, hw->mac.ledctl_mode2);
3739 * e1000_led_off_ich8lan - Turn LEDs off
3740 * @hw: pointer to the HW structure
3742 * Turn off the LEDs.
3744 static s32 e1000_led_off_ich8lan(struct e1000_hw *hw)
3746 if (hw->phy.type == e1000_phy_ife)
3747 return e1e_wphy(hw, IFE_PHY_SPECIAL_CONTROL_LED,
3748 (IFE_PSCL_PROBE_MODE |
3749 IFE_PSCL_PROBE_LEDS_OFF));
3751 ew32(LEDCTL, hw->mac.ledctl_mode1);
3756 * e1000_setup_led_pchlan - Configures SW controllable LED
3757 * @hw: pointer to the HW structure
3759 * This prepares the SW controllable LED for use.
3761 static s32 e1000_setup_led_pchlan(struct e1000_hw *hw)
3763 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_mode1);
3767 * e1000_cleanup_led_pchlan - Restore the default LED operation
3768 * @hw: pointer to the HW structure
3770 * Return the LED back to the default configuration.
3772 static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw)
3774 return e1e_wphy(hw, HV_LED_CONFIG, (u16)hw->mac.ledctl_default);
3778 * e1000_led_on_pchlan - Turn LEDs on
3779 * @hw: pointer to the HW structure
3783 static s32 e1000_led_on_pchlan(struct e1000_hw *hw)
3785 u16 data = (u16)hw->mac.ledctl_mode2;
3789 * If no link, then turn LED on by setting the invert bit
3790 * for each LED that's mode is "link_up" in ledctl_mode2.
3792 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3793 for (i = 0; i < 3; i++) {
3794 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3795 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3796 E1000_LEDCTL_MODE_LINK_UP)
3798 if (led & E1000_PHY_LED0_IVRT)
3799 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3801 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3805 return e1e_wphy(hw, HV_LED_CONFIG, data);
3809 * e1000_led_off_pchlan - Turn LEDs off
3810 * @hw: pointer to the HW structure
3812 * Turn off the LEDs.
3814 static s32 e1000_led_off_pchlan(struct e1000_hw *hw)
3816 u16 data = (u16)hw->mac.ledctl_mode1;
3820 * If no link, then turn LED off by clearing the invert bit
3821 * for each LED that's mode is "link_up" in ledctl_mode1.
3823 if (!(er32(STATUS) & E1000_STATUS_LU)) {
3824 for (i = 0; i < 3; i++) {
3825 led = (data >> (i * 5)) & E1000_PHY_LED0_MASK;
3826 if ((led & E1000_PHY_LED0_MODE_MASK) !=
3827 E1000_LEDCTL_MODE_LINK_UP)
3829 if (led & E1000_PHY_LED0_IVRT)
3830 data &= ~(E1000_PHY_LED0_IVRT << (i * 5));
3832 data |= (E1000_PHY_LED0_IVRT << (i * 5));
3836 return e1e_wphy(hw, HV_LED_CONFIG, data);
3840 * e1000_get_cfg_done_ich8lan - Read config done bit after Full or PHY reset
3841 * @hw: pointer to the HW structure
3843 * Read appropriate register for the config done bit for completion status
3844 * and configure the PHY through s/w for EEPROM-less parts.
3846 * NOTE: some silicon which is EEPROM-less will fail trying to read the
3847 * config done bit, so only an error is logged and continues. If we were
3848 * to return with error, EEPROM-less silicon would not be able to be reset
3851 static s32 e1000_get_cfg_done_ich8lan(struct e1000_hw *hw)
3857 e1000e_get_cfg_done(hw);
3859 /* Wait for indication from h/w that it has completed basic config */
3860 if (hw->mac.type >= e1000_ich10lan) {
3861 e1000_lan_init_done_ich8lan(hw);
3863 ret_val = e1000e_get_auto_rd_done(hw);
3866 * When auto config read does not complete, do not
3867 * return with an error. This can happen in situations
3868 * where there is no eeprom and prevents getting link.
3870 e_dbg("Auto Read Done did not complete\n");
3875 /* Clear PHY Reset Asserted bit */
3876 status = er32(STATUS);
3877 if (status & E1000_STATUS_PHYRA)
3878 ew32(STATUS, status & ~E1000_STATUS_PHYRA);
3880 e_dbg("PHY Reset Asserted not set - needs delay\n");
3882 /* If EEPROM is not marked present, init the IGP 3 PHY manually */
3883 if (hw->mac.type <= e1000_ich9lan) {
3884 if (((er32(EECD) & E1000_EECD_PRES) == 0) &&
3885 (hw->phy.type == e1000_phy_igp_3)) {
3886 e1000e_phy_init_script_igp3(hw);
3889 if (e1000_valid_nvm_bank_detect_ich8lan(hw, &bank)) {
3890 /* Maybe we should do a basic PHY config */
3891 e_dbg("EEPROM not present\n");
3892 ret_val = -E1000_ERR_CONFIG;
3900 * e1000_power_down_phy_copper_ich8lan - Remove link during PHY power down
3901 * @hw: pointer to the HW structure
3903 * In the case of a PHY power down to save power, or to turn off link during a
3904 * driver unload, or wake on lan is not enabled, remove the link.
3906 static void e1000_power_down_phy_copper_ich8lan(struct e1000_hw *hw)
3908 /* If the management interface is not enabled, then power down */
3909 if (!(hw->mac.ops.check_mng_mode(hw) ||
3910 hw->phy.ops.check_reset_block(hw)))
3911 e1000_power_down_phy_copper(hw);
3915 * e1000_clear_hw_cntrs_ich8lan - Clear statistical counters
3916 * @hw: pointer to the HW structure
3918 * Clears hardware counters specific to the silicon family and calls
3919 * clear_hw_cntrs_generic to clear all general purpose counters.
3921 static void e1000_clear_hw_cntrs_ich8lan(struct e1000_hw *hw)
3926 e1000e_clear_hw_cntrs_base(hw);
3942 /* Clear PHY statistics registers */
3943 if ((hw->phy.type == e1000_phy_82578) ||
3944 (hw->phy.type == e1000_phy_82579) ||
3945 (hw->phy.type == e1000_phy_82577)) {
3946 ret_val = hw->phy.ops.acquire(hw);
3949 ret_val = hw->phy.ops.set_page(hw,
3950 HV_STATS_PAGE << IGP_PAGE_SHIFT);
3953 hw->phy.ops.read_reg_page(hw, HV_SCC_UPPER, &phy_data);
3954 hw->phy.ops.read_reg_page(hw, HV_SCC_LOWER, &phy_data);
3955 hw->phy.ops.read_reg_page(hw, HV_ECOL_UPPER, &phy_data);
3956 hw->phy.ops.read_reg_page(hw, HV_ECOL_LOWER, &phy_data);
3957 hw->phy.ops.read_reg_page(hw, HV_MCC_UPPER, &phy_data);
3958 hw->phy.ops.read_reg_page(hw, HV_MCC_LOWER, &phy_data);
3959 hw->phy.ops.read_reg_page(hw, HV_LATECOL_UPPER, &phy_data);
3960 hw->phy.ops.read_reg_page(hw, HV_LATECOL_LOWER, &phy_data);
3961 hw->phy.ops.read_reg_page(hw, HV_COLC_UPPER, &phy_data);
3962 hw->phy.ops.read_reg_page(hw, HV_COLC_LOWER, &phy_data);
3963 hw->phy.ops.read_reg_page(hw, HV_DC_UPPER, &phy_data);
3964 hw->phy.ops.read_reg_page(hw, HV_DC_LOWER, &phy_data);
3965 hw->phy.ops.read_reg_page(hw, HV_TNCRS_UPPER, &phy_data);
3966 hw->phy.ops.read_reg_page(hw, HV_TNCRS_LOWER, &phy_data);
3968 hw->phy.ops.release(hw);
3972 static struct e1000_mac_operations ich8_mac_ops = {
3973 .id_led_init = e1000e_id_led_init,
3974 /* check_mng_mode dependent on mac type */
3975 .check_for_link = e1000_check_for_copper_link_ich8lan,
3976 /* cleanup_led dependent on mac type */
3977 .clear_hw_cntrs = e1000_clear_hw_cntrs_ich8lan,
3978 .get_bus_info = e1000_get_bus_info_ich8lan,
3979 .set_lan_id = e1000_set_lan_id_single_port,
3980 .get_link_up_info = e1000_get_link_up_info_ich8lan,
3981 /* led_on dependent on mac type */
3982 /* led_off dependent on mac type */
3983 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
3984 .reset_hw = e1000_reset_hw_ich8lan,
3985 .init_hw = e1000_init_hw_ich8lan,
3986 .setup_link = e1000_setup_link_ich8lan,
3987 .setup_physical_interface= e1000_setup_copper_link_ich8lan,
3988 /* id_led_init dependent on mac type */
3991 static struct e1000_phy_operations ich8_phy_ops = {
3992 .acquire = e1000_acquire_swflag_ich8lan,
3993 .check_reset_block = e1000_check_reset_block_ich8lan,
3995 .get_cfg_done = e1000_get_cfg_done_ich8lan,
3996 .get_cable_length = e1000e_get_cable_length_igp_2,
3997 .read_reg = e1000e_read_phy_reg_igp,
3998 .release = e1000_release_swflag_ich8lan,
3999 .reset = e1000_phy_hw_reset_ich8lan,
4000 .set_d0_lplu_state = e1000_set_d0_lplu_state_ich8lan,
4001 .set_d3_lplu_state = e1000_set_d3_lplu_state_ich8lan,
4002 .write_reg = e1000e_write_phy_reg_igp,
4005 static struct e1000_nvm_operations ich8_nvm_ops = {
4006 .acquire = e1000_acquire_nvm_ich8lan,
4007 .read = e1000_read_nvm_ich8lan,
4008 .release = e1000_release_nvm_ich8lan,
4009 .update = e1000_update_nvm_checksum_ich8lan,
4010 .valid_led_default = e1000_valid_led_default_ich8lan,
4011 .validate = e1000_validate_nvm_checksum_ich8lan,
4012 .write = e1000_write_nvm_ich8lan,
4015 struct e1000_info e1000_ich8_info = {
4016 .mac = e1000_ich8lan,
4017 .flags = FLAG_HAS_WOL
4019 | FLAG_RX_CSUM_ENABLED
4020 | FLAG_HAS_CTRLEXT_ON_LOAD
4025 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
4026 .get_variants = e1000_get_variants_ich8lan,
4027 .mac_ops = &ich8_mac_ops,
4028 .phy_ops = &ich8_phy_ops,
4029 .nvm_ops = &ich8_nvm_ops,
4032 struct e1000_info e1000_ich9_info = {
4033 .mac = e1000_ich9lan,
4034 .flags = FLAG_HAS_JUMBO_FRAMES
4037 | FLAG_RX_CSUM_ENABLED
4038 | FLAG_HAS_CTRLEXT_ON_LOAD
4044 .max_hw_frame_size = DEFAULT_JUMBO,
4045 .get_variants = e1000_get_variants_ich8lan,
4046 .mac_ops = &ich8_mac_ops,
4047 .phy_ops = &ich8_phy_ops,
4048 .nvm_ops = &ich8_nvm_ops,
4051 struct e1000_info e1000_ich10_info = {
4052 .mac = e1000_ich10lan,
4053 .flags = FLAG_HAS_JUMBO_FRAMES
4056 | FLAG_RX_CSUM_ENABLED
4057 | FLAG_HAS_CTRLEXT_ON_LOAD
4063 .max_hw_frame_size = DEFAULT_JUMBO,
4064 .get_variants = e1000_get_variants_ich8lan,
4065 .mac_ops = &ich8_mac_ops,
4066 .phy_ops = &ich8_phy_ops,
4067 .nvm_ops = &ich8_nvm_ops,
4070 struct e1000_info e1000_pch_info = {
4071 .mac = e1000_pchlan,
4072 .flags = FLAG_IS_ICH
4074 | FLAG_RX_CSUM_ENABLED
4075 | FLAG_HAS_CTRLEXT_ON_LOAD
4078 | FLAG_HAS_JUMBO_FRAMES
4079 | FLAG_DISABLE_FC_PAUSE_TIME /* errata */
4081 .flags2 = FLAG2_HAS_PHY_STATS,
4083 .max_hw_frame_size = 4096,
4084 .get_variants = e1000_get_variants_ich8lan,
4085 .mac_ops = &ich8_mac_ops,
4086 .phy_ops = &ich8_phy_ops,
4087 .nvm_ops = &ich8_nvm_ops,
4090 struct e1000_info e1000_pch2_info = {
4091 .mac = e1000_pch2lan,
4092 .flags = FLAG_IS_ICH
4094 | FLAG_RX_CSUM_ENABLED
4095 | FLAG_HAS_CTRLEXT_ON_LOAD
4098 | FLAG_HAS_JUMBO_FRAMES
4100 .flags2 = FLAG2_HAS_PHY_STATS
4103 .max_hw_frame_size = DEFAULT_JUMBO,
4104 .get_variants = e1000_get_variants_ich8lan,
4105 .mac_ops = &ich8_mac_ops,
4106 .phy_ops = &ich8_phy_ops,
4107 .nvm_ops = &ich8_nvm_ops,