1 /*******************************************************************************
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/delay.h>
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg);
38 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
39 u16 *data, bool read, bool page_set);
40 static u32 e1000_get_phy_addr_for_hv_page(u32 page);
41 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
42 u16 *data, bool read);
44 /* Cable length tables */
45 static const u16 e1000_m88_cable_length_table[] = {
46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
47 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
48 ARRAY_SIZE(e1000_m88_cable_length_table)
50 static const u16 e1000_igp_2_cable_length_table[] = {
51 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
52 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
53 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
54 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
55 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
56 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
57 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
59 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
60 ARRAY_SIZE(e1000_igp_2_cable_length_table)
62 #define BM_PHY_REG_PAGE(offset) \
63 ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
64 #define BM_PHY_REG_NUM(offset) \
65 ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
66 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
67 ~MAX_PHY_REG_ADDRESS)))
69 #define HV_INTC_FC_PAGE_START 768
70 #define I82578_ADDR_REG 29
71 #define I82577_ADDR_REG 16
72 #define I82577_CFG_REG 22
73 #define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15)
74 #define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */
75 #define I82577_CTRL_REG 23
77 /* 82577 specific PHY registers */
78 #define I82577_PHY_CTRL_2 18
79 #define I82577_PHY_STATUS_2 26
80 #define I82577_PHY_DIAG_STATUS 31
82 /* I82577 PHY Status 2 */
83 #define I82577_PHY_STATUS2_REV_POLARITY 0x0400
84 #define I82577_PHY_STATUS2_MDIX 0x0800
85 #define I82577_PHY_STATUS2_SPEED_MASK 0x0300
86 #define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
88 /* I82577 PHY Control 2 */
89 #define I82577_PHY_CTRL2_AUTO_MDIX 0x0400
90 #define I82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200
92 /* I82577 PHY Diagnostics Status */
93 #define I82577_DSTATUS_CABLE_LENGTH 0x03FC
94 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
96 /* BM PHY Copper Specific Control 1 */
97 #define BM_CS_CTRL1 16
99 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
100 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400
101 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004
104 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
105 * @hw: pointer to the HW structure
107 * Read the PHY management control register and check whether a PHY reset
108 * is blocked. If a reset is not blocked return 0, otherwise
109 * return E1000_BLK_PHY_RESET (12).
111 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
117 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
118 E1000_BLK_PHY_RESET : 0;
122 * e1000e_get_phy_id - Retrieve the PHY ID and revision
123 * @hw: pointer to the HW structure
125 * Reads the PHY registers and stores the PHY ID and possibly the PHY
126 * revision in the hardware structure.
128 s32 e1000e_get_phy_id(struct e1000_hw *hw)
130 struct e1000_phy_info *phy = &hw->phy;
135 if (!(phy->ops.read_reg))
138 while (retry_count < 2) {
139 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
143 phy->id = (u32)(phy_id << 16);
145 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
149 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
150 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
152 if (phy->id != 0 && phy->id != PHY_REVISION_MASK)
162 * e1000e_phy_reset_dsp - Reset PHY DSP
163 * @hw: pointer to the HW structure
165 * Reset the digital signal processor.
167 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
171 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
175 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
179 * e1000e_read_phy_reg_mdic - Read MDI control register
180 * @hw: pointer to the HW structure
181 * @offset: register offset to be read
182 * @data: pointer to the read data
184 * Reads the MDI control register in the PHY at offset and stores the
185 * information read to data.
187 s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
189 struct e1000_phy_info *phy = &hw->phy;
192 if (offset > MAX_PHY_REG_ADDRESS) {
193 e_dbg("PHY Address %d is out of range\n", offset);
194 return -E1000_ERR_PARAM;
198 * Set up Op-code, Phy Address, and register offset in the MDI
199 * Control register. The MAC will take care of interfacing with the
200 * PHY to retrieve the desired data.
202 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
203 (phy->addr << E1000_MDIC_PHY_SHIFT) |
204 (E1000_MDIC_OP_READ));
209 * Poll the ready bit to see if the MDI read completed
210 * Increasing the time out as testing showed failures with
213 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
216 if (mdic & E1000_MDIC_READY)
219 if (!(mdic & E1000_MDIC_READY)) {
220 e_dbg("MDI Read did not complete\n");
221 return -E1000_ERR_PHY;
223 if (mdic & E1000_MDIC_ERROR) {
224 e_dbg("MDI Error\n");
225 return -E1000_ERR_PHY;
230 * Allow some time after each MDIC transaction to avoid
231 * reading duplicate data in the next MDIC transaction.
233 if (hw->mac.type == e1000_pch2lan)
240 * e1000e_write_phy_reg_mdic - Write MDI control register
241 * @hw: pointer to the HW structure
242 * @offset: register offset to write to
243 * @data: data to write to register at offset
245 * Writes data to MDI control register in the PHY at offset.
247 s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
249 struct e1000_phy_info *phy = &hw->phy;
252 if (offset > MAX_PHY_REG_ADDRESS) {
253 e_dbg("PHY Address %d is out of range\n", offset);
254 return -E1000_ERR_PARAM;
258 * Set up Op-code, Phy Address, and register offset in the MDI
259 * Control register. The MAC will take care of interfacing with the
260 * PHY to retrieve the desired data.
262 mdic = (((u32)data) |
263 (offset << E1000_MDIC_REG_SHIFT) |
264 (phy->addr << E1000_MDIC_PHY_SHIFT) |
265 (E1000_MDIC_OP_WRITE));
270 * Poll the ready bit to see if the MDI read completed
271 * Increasing the time out as testing showed failures with
274 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
277 if (mdic & E1000_MDIC_READY)
280 if (!(mdic & E1000_MDIC_READY)) {
281 e_dbg("MDI Write did not complete\n");
282 return -E1000_ERR_PHY;
284 if (mdic & E1000_MDIC_ERROR) {
285 e_dbg("MDI Error\n");
286 return -E1000_ERR_PHY;
290 * Allow some time after each MDIC transaction to avoid
291 * reading duplicate data in the next MDIC transaction.
293 if (hw->mac.type == e1000_pch2lan)
300 * e1000e_read_phy_reg_m88 - Read m88 PHY register
301 * @hw: pointer to the HW structure
302 * @offset: register offset to be read
303 * @data: pointer to the read data
305 * Acquires semaphore, if necessary, then reads the PHY register at offset
306 * and storing the retrieved information in data. Release any acquired
307 * semaphores before exiting.
309 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
313 ret_val = hw->phy.ops.acquire(hw);
317 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
320 hw->phy.ops.release(hw);
326 * e1000e_write_phy_reg_m88 - Write m88 PHY register
327 * @hw: pointer to the HW structure
328 * @offset: register offset to write to
329 * @data: data to write at register offset
331 * Acquires semaphore, if necessary, then writes the data to PHY register
332 * at the offset. Release any acquired semaphores before exiting.
334 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
338 ret_val = hw->phy.ops.acquire(hw);
342 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
345 hw->phy.ops.release(hw);
351 * e1000_set_page_igp - Set page as on IGP-like PHY(s)
352 * @hw: pointer to the HW structure
353 * @page: page to set (shifted left when necessary)
355 * Sets PHY page required for PHY register access. Assumes semaphore is
356 * already acquired. Note, this function sets phy.addr to 1 so the caller
357 * must set it appropriately (if necessary) after this function returns.
359 s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page)
361 e_dbg("Setting page 0x%x\n", page);
365 return e1000e_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page);
369 * __e1000e_read_phy_reg_igp - Read igp PHY register
370 * @hw: pointer to the HW structure
371 * @offset: register offset to be read
372 * @data: pointer to the read data
373 * @locked: semaphore has already been acquired or not
375 * Acquires semaphore, if necessary, then reads the PHY register at offset
376 * and stores the retrieved information in data. Release any acquired
377 * semaphores before exiting.
379 static s32 __e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
385 if (!(hw->phy.ops.acquire))
388 ret_val = hw->phy.ops.acquire(hw);
393 if (offset > MAX_PHY_MULTI_PAGE_REG) {
394 ret_val = e1000e_write_phy_reg_mdic(hw,
395 IGP01E1000_PHY_PAGE_SELECT,
401 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
406 hw->phy.ops.release(hw);
412 * e1000e_read_phy_reg_igp - Read igp PHY register
413 * @hw: pointer to the HW structure
414 * @offset: register offset to be read
415 * @data: pointer to the read data
417 * Acquires semaphore then reads the PHY register at offset and stores the
418 * retrieved information in data.
419 * Release the acquired semaphore before exiting.
421 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
423 return __e1000e_read_phy_reg_igp(hw, offset, data, false);
427 * e1000e_read_phy_reg_igp_locked - Read igp PHY register
428 * @hw: pointer to the HW structure
429 * @offset: register offset to be read
430 * @data: pointer to the read data
432 * Reads the PHY register at offset and stores the retrieved information
433 * in data. Assumes semaphore already acquired.
435 s32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
437 return __e1000e_read_phy_reg_igp(hw, offset, data, true);
441 * e1000e_write_phy_reg_igp - Write igp PHY register
442 * @hw: pointer to the HW structure
443 * @offset: register offset to write to
444 * @data: data to write at register offset
445 * @locked: semaphore has already been acquired or not
447 * Acquires semaphore, if necessary, then writes the data to PHY register
448 * at the offset. Release any acquired semaphores before exiting.
450 static s32 __e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
456 if (!(hw->phy.ops.acquire))
459 ret_val = hw->phy.ops.acquire(hw);
464 if (offset > MAX_PHY_MULTI_PAGE_REG) {
465 ret_val = e1000e_write_phy_reg_mdic(hw,
466 IGP01E1000_PHY_PAGE_SELECT,
472 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
477 hw->phy.ops.release(hw);
484 * e1000e_write_phy_reg_igp - Write igp PHY register
485 * @hw: pointer to the HW structure
486 * @offset: register offset to write to
487 * @data: data to write at register offset
489 * Acquires semaphore then writes the data to PHY register
490 * at the offset. Release any acquired semaphores before exiting.
492 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
494 return __e1000e_write_phy_reg_igp(hw, offset, data, false);
498 * e1000e_write_phy_reg_igp_locked - Write igp PHY register
499 * @hw: pointer to the HW structure
500 * @offset: register offset to write to
501 * @data: data to write at register offset
503 * Writes the data to PHY register at the offset.
504 * Assumes semaphore already acquired.
506 s32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
508 return __e1000e_write_phy_reg_igp(hw, offset, data, true);
512 * __e1000_read_kmrn_reg - Read kumeran register
513 * @hw: pointer to the HW structure
514 * @offset: register offset to be read
515 * @data: pointer to the read data
516 * @locked: semaphore has already been acquired or not
518 * Acquires semaphore, if necessary. Then reads the PHY register at offset
519 * using the kumeran interface. The information retrieved is stored in data.
520 * Release any acquired semaphores before exiting.
522 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
529 if (!(hw->phy.ops.acquire))
532 ret_val = hw->phy.ops.acquire(hw);
537 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
538 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
539 ew32(KMRNCTRLSTA, kmrnctrlsta);
543 kmrnctrlsta = er32(KMRNCTRLSTA);
544 *data = (u16)kmrnctrlsta;
547 hw->phy.ops.release(hw);
554 * e1000e_read_kmrn_reg - Read kumeran register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to be read
557 * @data: pointer to the read data
559 * Acquires semaphore then reads the PHY register at offset using the
560 * kumeran interface. The information retrieved is stored in data.
561 * Release the acquired semaphore before exiting.
563 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
565 return __e1000_read_kmrn_reg(hw, offset, data, false);
569 * e1000e_read_kmrn_reg_locked - Read kumeran register
570 * @hw: pointer to the HW structure
571 * @offset: register offset to be read
572 * @data: pointer to the read data
574 * Reads the PHY register at offset using the kumeran interface. The
575 * information retrieved is stored in data.
576 * Assumes semaphore already acquired.
578 s32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
580 return __e1000_read_kmrn_reg(hw, offset, data, true);
584 * __e1000_write_kmrn_reg - Write kumeran register
585 * @hw: pointer to the HW structure
586 * @offset: register offset to write to
587 * @data: data to write at register offset
588 * @locked: semaphore has already been acquired or not
590 * Acquires semaphore, if necessary. Then write the data to PHY register
591 * at the offset using the kumeran interface. Release any acquired semaphores
594 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
601 if (!(hw->phy.ops.acquire))
604 ret_val = hw->phy.ops.acquire(hw);
609 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
610 E1000_KMRNCTRLSTA_OFFSET) | data;
611 ew32(KMRNCTRLSTA, kmrnctrlsta);
616 hw->phy.ops.release(hw);
623 * e1000e_write_kmrn_reg - Write kumeran register
624 * @hw: pointer to the HW structure
625 * @offset: register offset to write to
626 * @data: data to write at register offset
628 * Acquires semaphore then writes the data to the PHY register at the offset
629 * using the kumeran interface. Release the acquired semaphore before exiting.
631 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
633 return __e1000_write_kmrn_reg(hw, offset, data, false);
637 * e1000e_write_kmrn_reg_locked - Write kumeran register
638 * @hw: pointer to the HW structure
639 * @offset: register offset to write to
640 * @data: data to write at register offset
642 * Write the data to PHY register at the offset using the kumeran interface.
643 * Assumes semaphore already acquired.
645 s32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
647 return __e1000_write_kmrn_reg(hw, offset, data, true);
651 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
652 * @hw: pointer to the HW structure
654 * Sets up Carrier-sense on Transmit and downshift values.
656 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
661 /* Enable CRS on Tx. This must be set for half-duplex operation. */
662 ret_val = e1e_rphy(hw, I82577_CFG_REG, &phy_data);
666 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
668 /* Enable downshift */
669 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
671 ret_val = e1e_wphy(hw, I82577_CFG_REG, phy_data);
678 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
679 * @hw: pointer to the HW structure
681 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
682 * and downshift values are set also.
684 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
686 struct e1000_phy_info *phy = &hw->phy;
690 /* Enable CRS on Tx. This must be set for half-duplex operation. */
691 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
695 /* For BM PHY this bit is downshift enable */
696 if (phy->type != e1000_phy_bm)
697 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
701 * MDI/MDI-X = 0 (default)
702 * 0 - Auto for all speeds
705 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
707 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
711 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
714 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
717 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
721 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
727 * disable_polarity_correction = 0 (default)
728 * Automatic Correction for Reversed Cable Polarity
732 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
733 if (phy->disable_polarity_correction == 1)
734 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
736 /* Enable downshift on BM (disabled by default) */
737 if (phy->type == e1000_phy_bm)
738 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT;
740 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
744 if ((phy->type == e1000_phy_m88) &&
745 (phy->revision < E1000_REVISION_4) &&
746 (phy->id != BME1000_E_PHY_ID_R2)) {
748 * Force TX_CLK in the Extended PHY Specific Control Register
751 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
755 phy_data |= M88E1000_EPSCR_TX_CLK_25;
757 if ((phy->revision == 2) &&
758 (phy->id == M88E1111_I_PHY_ID)) {
759 /* 82573L PHY - set the downshift counter to 5x. */
760 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
761 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
763 /* Configure Master and Slave downshift values */
764 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
765 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
766 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
767 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
769 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
774 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) {
775 /* Set PHY page 0, register 29 to 0x0003 */
776 ret_val = e1e_wphy(hw, 29, 0x0003);
780 /* Set PHY page 0, register 30 to 0x0000 */
781 ret_val = e1e_wphy(hw, 30, 0x0000);
786 /* Commit the changes. */
787 ret_val = e1000e_commit_phy(hw);
789 e_dbg("Error committing the PHY changes\n");
793 if (phy->type == e1000_phy_82578) {
794 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
798 /* 82578 PHY - set the downshift count to 1x. */
799 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE;
800 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK;
801 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
810 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
811 * @hw: pointer to the HW structure
813 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
816 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
818 struct e1000_phy_info *phy = &hw->phy;
822 ret_val = e1000_phy_hw_reset(hw);
824 e_dbg("Error resetting the PHY.\n");
829 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
830 * timeout issues when LFS is enabled.
834 /* disable lplu d0 during driver init */
835 ret_val = e1000_set_d0_lplu_state(hw, false);
837 e_dbg("Error Disabling LPLU D0\n");
840 /* Configure mdi-mdix settings */
841 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
845 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
849 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
852 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
856 data |= IGP01E1000_PSCR_AUTO_MDIX;
859 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
863 /* set auto-master slave resolution settings */
864 if (hw->mac.autoneg) {
866 * when autonegotiation advertisement is only 1000Mbps then we
867 * should disable SmartSpeed and enable Auto MasterSlave
868 * resolution as hardware default.
870 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
871 /* Disable SmartSpeed */
872 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
877 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
878 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
883 /* Set auto Master/Slave resolution process */
884 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
888 data &= ~CR_1000T_MS_ENABLE;
889 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
894 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
898 /* load defaults for future use */
899 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
900 ((data & CR_1000T_MS_VALUE) ?
901 e1000_ms_force_master :
902 e1000_ms_force_slave) :
905 switch (phy->ms_type) {
906 case e1000_ms_force_master:
907 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
909 case e1000_ms_force_slave:
910 data |= CR_1000T_MS_ENABLE;
911 data &= ~(CR_1000T_MS_VALUE);
914 data &= ~CR_1000T_MS_ENABLE;
918 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
925 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
926 * @hw: pointer to the HW structure
928 * Reads the MII auto-neg advertisement register and/or the 1000T control
929 * register and if the PHY is already setup for auto-negotiation, then
930 * return successful. Otherwise, setup advertisement and flow control to
931 * the appropriate values for the wanted auto-negotiation.
933 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
935 struct e1000_phy_info *phy = &hw->phy;
937 u16 mii_autoneg_adv_reg;
938 u16 mii_1000t_ctrl_reg = 0;
940 phy->autoneg_advertised &= phy->autoneg_mask;
942 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
943 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
947 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
948 /* Read the MII 1000Base-T Control Register (Address 9). */
949 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
955 * Need to parse both autoneg_advertised and fc and set up
956 * the appropriate PHY registers. First we will parse for
957 * autoneg_advertised software override. Since we can advertise
958 * a plethora of combinations, we need to check each bit
963 * First we clear all the 10/100 mb speed bits in the Auto-Neg
964 * Advertisement Register (Address 4) and the 1000 mb speed bits in
965 * the 1000Base-T Control Register (Address 9).
967 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
968 NWAY_AR_100TX_HD_CAPS |
969 NWAY_AR_10T_FD_CAPS |
970 NWAY_AR_10T_HD_CAPS);
971 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
973 e_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
975 /* Do we want to advertise 10 Mb Half Duplex? */
976 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
977 e_dbg("Advertise 10mb Half duplex\n");
978 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
981 /* Do we want to advertise 10 Mb Full Duplex? */
982 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
983 e_dbg("Advertise 10mb Full duplex\n");
984 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
987 /* Do we want to advertise 100 Mb Half Duplex? */
988 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
989 e_dbg("Advertise 100mb Half duplex\n");
990 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
993 /* Do we want to advertise 100 Mb Full Duplex? */
994 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
995 e_dbg("Advertise 100mb Full duplex\n");
996 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
999 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1000 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1001 e_dbg("Advertise 1000mb Half duplex request denied!\n");
1003 /* Do we want to advertise 1000 Mb Full Duplex? */
1004 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1005 e_dbg("Advertise 1000mb Full duplex\n");
1006 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1010 * Check for a software override of the flow control settings, and
1011 * setup the PHY advertisement registers accordingly. If
1012 * auto-negotiation is enabled, then software will have to set the
1013 * "PAUSE" bits to the correct value in the Auto-Negotiation
1014 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1017 * The possible values of the "fc" parameter are:
1018 * 0: Flow control is completely disabled
1019 * 1: Rx flow control is enabled (we can receive pause frames
1020 * but not send pause frames).
1021 * 2: Tx flow control is enabled (we can send pause frames
1022 * but we do not support receiving pause frames).
1023 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1024 * other: No software override. The flow control configuration
1025 * in the EEPROM is used.
1027 switch (hw->fc.current_mode) {
1030 * Flow control (Rx & Tx) is completely disabled by a
1031 * software over-ride.
1033 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1035 case e1000_fc_rx_pause:
1037 * Rx Flow control is enabled, and Tx Flow control is
1038 * disabled, by a software over-ride.
1040 * Since there really isn't a way to advertise that we are
1041 * capable of Rx Pause ONLY, we will advertise that we
1042 * support both symmetric and asymmetric Rx PAUSE. Later
1043 * (in e1000e_config_fc_after_link_up) we will disable the
1044 * hw's ability to send PAUSE frames.
1046 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1048 case e1000_fc_tx_pause:
1050 * Tx Flow control is enabled, and Rx Flow control is
1051 * disabled, by a software over-ride.
1053 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1054 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1058 * Flow control (both Rx and Tx) is enabled by a software
1061 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1064 e_dbg("Flow control param set incorrectly\n");
1065 ret_val = -E1000_ERR_CONFIG;
1069 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1073 e_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1075 if (phy->autoneg_mask & ADVERTISE_1000_FULL)
1076 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
1082 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1083 * @hw: pointer to the HW structure
1085 * Performs initial bounds checking on autoneg advertisement parameter, then
1086 * configure to advertise the full capability. Setup the PHY to autoneg
1087 * and restart the negotiation process between the link partner. If
1088 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1090 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1092 struct e1000_phy_info *phy = &hw->phy;
1097 * Perform some bounds checking on the autoneg advertisement
1100 phy->autoneg_advertised &= phy->autoneg_mask;
1103 * If autoneg_advertised is zero, we assume it was not defaulted
1104 * by the calling code so we set to advertise full capability.
1106 if (phy->autoneg_advertised == 0)
1107 phy->autoneg_advertised = phy->autoneg_mask;
1109 e_dbg("Reconfiguring auto-neg advertisement params\n");
1110 ret_val = e1000_phy_setup_autoneg(hw);
1112 e_dbg("Error Setting up Auto-Negotiation\n");
1115 e_dbg("Restarting Auto-Neg\n");
1118 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1119 * the Auto Neg Restart bit in the PHY control register.
1121 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1125 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1126 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1131 * Does the user want to wait for Auto-Neg to complete here, or
1132 * check at a later time (for example, callback routine).
1134 if (phy->autoneg_wait_to_complete) {
1135 ret_val = e1000_wait_autoneg(hw);
1137 e_dbg("Error while waiting for "
1138 "autoneg to complete\n");
1143 hw->mac.get_link_status = 1;
1149 * e1000e_setup_copper_link - Configure copper link settings
1150 * @hw: pointer to the HW structure
1152 * Calls the appropriate function to configure the link for auto-neg or forced
1153 * speed and duplex. Then we check for link, once link is established calls
1154 * to configure collision distance and flow control are called. If link is
1155 * not established, we return -E1000_ERR_PHY (-2).
1157 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
1162 if (hw->mac.autoneg) {
1164 * Setup autoneg and flow control advertisement and perform
1167 ret_val = e1000_copper_link_autoneg(hw);
1172 * PHY will be set to 10H, 10F, 100H or 100F
1173 * depending on user settings.
1175 e_dbg("Forcing Speed and Duplex\n");
1176 ret_val = e1000_phy_force_speed_duplex(hw);
1178 e_dbg("Error Forcing Speed and Duplex\n");
1184 * Check link status. Wait up to 100 microseconds for link to become
1187 ret_val = e1000e_phy_has_link_generic(hw,
1188 COPPER_LINK_UP_LIMIT,
1195 e_dbg("Valid link established!!!\n");
1196 e1000e_config_collision_dist(hw);
1197 ret_val = e1000e_config_fc_after_link_up(hw);
1199 e_dbg("Unable to establish link!!!\n");
1206 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1207 * @hw: pointer to the HW structure
1209 * Calls the PHY setup function to force speed and duplex. Clears the
1210 * auto-crossover to force MDI manually. Waits for link and returns
1211 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1213 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1215 struct e1000_phy_info *phy = &hw->phy;
1220 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1224 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1226 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1231 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1232 * forced whenever speed and duplex are forced.
1234 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1238 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1239 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1241 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1245 e_dbg("IGP PSCR: %X\n", phy_data);
1249 if (phy->autoneg_wait_to_complete) {
1250 e_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1252 ret_val = e1000e_phy_has_link_generic(hw,
1260 e_dbg("Link taking longer than expected.\n");
1263 ret_val = e1000e_phy_has_link_generic(hw,
1275 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1276 * @hw: pointer to the HW structure
1278 * Calls the PHY setup function to force speed and duplex. Clears the
1279 * auto-crossover to force MDI manually. Resets the PHY to commit the
1280 * changes. If time expires while waiting for link up, we reset the DSP.
1281 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1282 * successful completion, else return corresponding error code.
1284 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1286 struct e1000_phy_info *phy = &hw->phy;
1292 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1293 * forced whenever speed and duplex are forced.
1295 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1299 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1300 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1304 e_dbg("M88E1000 PSCR: %X\n", phy_data);
1306 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
1310 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
1312 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
1316 /* Reset the phy to commit changes. */
1317 ret_val = e1000e_commit_phy(hw);
1321 if (phy->autoneg_wait_to_complete) {
1322 e_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1324 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1330 if (hw->phy.type != e1000_phy_m88) {
1331 e_dbg("Link taking longer than expected.\n");
1334 * We didn't get link.
1335 * Reset the DSP and cross our fingers.
1337 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT,
1341 ret_val = e1000e_phy_reset_dsp(hw);
1348 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1354 if (hw->phy.type != e1000_phy_m88)
1357 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1362 * Resetting the phy means we need to re-force TX_CLK in the
1363 * Extended PHY Specific Control Register to 25MHz clock from
1364 * the reset value of 2.5MHz.
1366 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1367 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1372 * In addition, we must re-enable CRS on Tx for both half and full
1375 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1379 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1380 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1386 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1387 * @hw: pointer to the HW structure
1389 * Forces the speed and duplex settings of the PHY.
1390 * This is a function pointer entry point only called by
1391 * PHY setup routines.
1393 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1395 struct e1000_phy_info *phy = &hw->phy;
1400 ret_val = e1e_rphy(hw, PHY_CONTROL, &data);
1404 e1000e_phy_force_speed_duplex_setup(hw, &data);
1406 ret_val = e1e_wphy(hw, PHY_CONTROL, data);
1410 /* Disable MDI-X support for 10/100 */
1411 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
1415 data &= ~IFE_PMC_AUTO_MDIX;
1416 data &= ~IFE_PMC_FORCE_MDIX;
1418 ret_val = e1e_wphy(hw, IFE_PHY_MDIX_CONTROL, data);
1422 e_dbg("IFE PMC: %X\n", data);
1426 if (phy->autoneg_wait_to_complete) {
1427 e_dbg("Waiting for forced speed/duplex link on IFE phy.\n");
1429 ret_val = e1000e_phy_has_link_generic(hw,
1437 e_dbg("Link taking longer than expected.\n");
1440 ret_val = e1000e_phy_has_link_generic(hw,
1453 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1454 * @hw: pointer to the HW structure
1455 * @phy_ctrl: pointer to current value of PHY_CONTROL
1457 * Forces speed and duplex on the PHY by doing the following: disable flow
1458 * control, force speed/duplex on the MAC, disable auto speed detection,
1459 * disable auto-negotiation, configure duplex, configure speed, configure
1460 * the collision distance, write configuration to CTRL register. The
1461 * caller must write to the PHY_CONTROL register for these settings to
1464 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1466 struct e1000_mac_info *mac = &hw->mac;
1469 /* Turn off flow control when forcing speed/duplex */
1470 hw->fc.current_mode = e1000_fc_none;
1472 /* Force speed/duplex on the mac */
1474 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1475 ctrl &= ~E1000_CTRL_SPD_SEL;
1477 /* Disable Auto Speed Detection */
1478 ctrl &= ~E1000_CTRL_ASDE;
1480 /* Disable autoneg on the phy */
1481 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1483 /* Forcing Full or Half Duplex? */
1484 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1485 ctrl &= ~E1000_CTRL_FD;
1486 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1487 e_dbg("Half Duplex\n");
1489 ctrl |= E1000_CTRL_FD;
1490 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1491 e_dbg("Full Duplex\n");
1494 /* Forcing 10mb or 100mb? */
1495 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1496 ctrl |= E1000_CTRL_SPD_100;
1497 *phy_ctrl |= MII_CR_SPEED_100;
1498 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1499 e_dbg("Forcing 100mb\n");
1501 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1502 *phy_ctrl |= MII_CR_SPEED_10;
1503 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1504 e_dbg("Forcing 10mb\n");
1507 e1000e_config_collision_dist(hw);
1513 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1514 * @hw: pointer to the HW structure
1515 * @active: boolean used to enable/disable lplu
1517 * Success returns 0, Failure returns 1
1519 * The low power link up (lplu) state is set to the power management level D3
1520 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1521 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1522 * is used during Dx states where the power conservation is most important.
1523 * During driver activity, SmartSpeed should be enabled so performance is
1526 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1528 struct e1000_phy_info *phy = &hw->phy;
1532 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1537 data &= ~IGP02E1000_PM_D3_LPLU;
1538 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1542 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1543 * during Dx states where the power conservation is most
1544 * important. During driver activity we should enable
1545 * SmartSpeed, so performance is maintained.
1547 if (phy->smart_speed == e1000_smart_speed_on) {
1548 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1553 data |= IGP01E1000_PSCFR_SMART_SPEED;
1554 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1558 } else if (phy->smart_speed == e1000_smart_speed_off) {
1559 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1564 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1565 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1570 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1571 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1572 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1573 data |= IGP02E1000_PM_D3_LPLU;
1574 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1578 /* When LPLU is enabled, we should disable SmartSpeed */
1579 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1583 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1584 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1591 * e1000e_check_downshift - Checks whether a downshift in speed occurred
1592 * @hw: pointer to the HW structure
1594 * Success returns 0, Failure returns 1
1596 * A downshift is detected by querying the PHY link health.
1598 s32 e1000e_check_downshift(struct e1000_hw *hw)
1600 struct e1000_phy_info *phy = &hw->phy;
1602 u16 phy_data, offset, mask;
1604 switch (phy->type) {
1606 case e1000_phy_gg82563:
1608 case e1000_phy_82578:
1609 offset = M88E1000_PHY_SPEC_STATUS;
1610 mask = M88E1000_PSSR_DOWNSHIFT;
1612 case e1000_phy_igp_2:
1613 case e1000_phy_igp_3:
1614 offset = IGP01E1000_PHY_LINK_HEALTH;
1615 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1618 /* speed downshift not supported */
1619 phy->speed_downgraded = false;
1623 ret_val = e1e_rphy(hw, offset, &phy_data);
1626 phy->speed_downgraded = (phy_data & mask);
1632 * e1000_check_polarity_m88 - Checks the polarity.
1633 * @hw: pointer to the HW structure
1635 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1637 * Polarity is determined based on the PHY specific status register.
1639 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1641 struct e1000_phy_info *phy = &hw->phy;
1645 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1648 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1649 ? e1000_rev_polarity_reversed
1650 : e1000_rev_polarity_normal;
1656 * e1000_check_polarity_igp - Checks the polarity.
1657 * @hw: pointer to the HW structure
1659 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1661 * Polarity is determined based on the PHY port status register, and the
1662 * current speed (since there is no polarity at 100Mbps).
1664 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1666 struct e1000_phy_info *phy = &hw->phy;
1668 u16 data, offset, mask;
1671 * Polarity is determined based on the speed of
1674 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1678 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1679 IGP01E1000_PSSR_SPEED_1000MBPS) {
1680 offset = IGP01E1000_PHY_PCS_INIT_REG;
1681 mask = IGP01E1000_PHY_POLARITY_MASK;
1684 * This really only applies to 10Mbps since
1685 * there is no polarity for 100Mbps (always 0).
1687 offset = IGP01E1000_PHY_PORT_STATUS;
1688 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1691 ret_val = e1e_rphy(hw, offset, &data);
1694 phy->cable_polarity = (data & mask)
1695 ? e1000_rev_polarity_reversed
1696 : e1000_rev_polarity_normal;
1702 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1703 * @hw: pointer to the HW structure
1705 * Polarity is determined on the polarity reversal feature being enabled.
1707 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1709 struct e1000_phy_info *phy = &hw->phy;
1711 u16 phy_data, offset, mask;
1714 * Polarity is determined based on the reversal feature being enabled.
1716 if (phy->polarity_correction) {
1717 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1718 mask = IFE_PESC_POLARITY_REVERSED;
1720 offset = IFE_PHY_SPECIAL_CONTROL;
1721 mask = IFE_PSC_FORCE_POLARITY;
1724 ret_val = e1e_rphy(hw, offset, &phy_data);
1727 phy->cable_polarity = (phy_data & mask)
1728 ? e1000_rev_polarity_reversed
1729 : e1000_rev_polarity_normal;
1735 * e1000_wait_autoneg - Wait for auto-neg completion
1736 * @hw: pointer to the HW structure
1738 * Waits for auto-negotiation to complete or for the auto-negotiation time
1739 * limit to expire, which ever happens first.
1741 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1746 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1747 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1748 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1751 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1754 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1760 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1767 * e1000e_phy_has_link_generic - Polls PHY for link
1768 * @hw: pointer to the HW structure
1769 * @iterations: number of times to poll for link
1770 * @usec_interval: delay between polling attempts
1771 * @success: pointer to whether polling was successful or not
1773 * Polls the PHY status register for link, 'iterations' number of times.
1775 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1776 u32 usec_interval, bool *success)
1781 for (i = 0; i < iterations; i++) {
1783 * Some PHYs require the PHY_STATUS register to be read
1784 * twice due to the link bit being sticky. No harm doing
1785 * it across the board.
1787 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1790 * If the first read fails, another entity may have
1791 * ownership of the resources, wait and try again to
1792 * see if they have relinquished the resources yet.
1794 udelay(usec_interval);
1795 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1798 if (phy_status & MII_SR_LINK_STATUS)
1800 if (usec_interval >= 1000)
1801 mdelay(usec_interval/1000);
1803 udelay(usec_interval);
1806 *success = (i < iterations);
1812 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1813 * @hw: pointer to the HW structure
1815 * Reads the PHY specific status register to retrieve the cable length
1816 * information. The cable length is determined by averaging the minimum and
1817 * maximum values to get the "average" cable length. The m88 PHY has four
1818 * possible cable length values, which are:
1819 * Register Value Cable Length
1823 * 3 110 - 140 meters
1826 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1828 struct e1000_phy_info *phy = &hw->phy;
1830 u16 phy_data, index;
1832 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1836 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1837 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1838 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1839 ret_val = -E1000_ERR_PHY;
1843 phy->min_cable_length = e1000_m88_cable_length_table[index];
1844 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1846 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1853 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1854 * @hw: pointer to the HW structure
1856 * The automatic gain control (agc) normalizes the amplitude of the
1857 * received signal, adjusting for the attenuation produced by the
1858 * cable. By reading the AGC registers, which represent the
1859 * combination of coarse and fine gain value, the value can be put
1860 * into a lookup table to obtain the approximate cable length
1863 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1865 struct e1000_phy_info *phy = &hw->phy;
1867 u16 phy_data, i, agc_value = 0;
1868 u16 cur_agc_index, max_agc_index = 0;
1869 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1870 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1871 IGP02E1000_PHY_AGC_A,
1872 IGP02E1000_PHY_AGC_B,
1873 IGP02E1000_PHY_AGC_C,
1874 IGP02E1000_PHY_AGC_D
1877 /* Read the AGC registers for all channels */
1878 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1879 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1884 * Getting bits 15:9, which represent the combination of
1885 * coarse and fine gain values. The result is a number
1886 * that can be put into the lookup table to obtain the
1887 * approximate cable length.
1889 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1890 IGP02E1000_AGC_LENGTH_MASK;
1892 /* Array index bound check. */
1893 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1894 (cur_agc_index == 0))
1895 return -E1000_ERR_PHY;
1897 /* Remove min & max AGC values from calculation. */
1898 if (e1000_igp_2_cable_length_table[min_agc_index] >
1899 e1000_igp_2_cable_length_table[cur_agc_index])
1900 min_agc_index = cur_agc_index;
1901 if (e1000_igp_2_cable_length_table[max_agc_index] <
1902 e1000_igp_2_cable_length_table[cur_agc_index])
1903 max_agc_index = cur_agc_index;
1905 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1908 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1909 e1000_igp_2_cable_length_table[max_agc_index]);
1910 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1912 /* Calculate cable length with the error range of +/- 10 meters. */
1913 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1914 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1915 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1917 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1923 * e1000e_get_phy_info_m88 - Retrieve PHY information
1924 * @hw: pointer to the HW structure
1926 * Valid for only copper links. Read the PHY status register (sticky read)
1927 * to verify that link is up. Read the PHY special control register to
1928 * determine the polarity and 10base-T extended distance. Read the PHY
1929 * special status register to determine MDI/MDIx and current speed. If
1930 * speed is 1000, then determine cable length, local and remote receiver.
1932 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1934 struct e1000_phy_info *phy = &hw->phy;
1939 if (phy->media_type != e1000_media_type_copper) {
1940 e_dbg("Phy info is only valid for copper media\n");
1941 return -E1000_ERR_CONFIG;
1944 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1949 e_dbg("Phy info is only valid if link is up\n");
1950 return -E1000_ERR_CONFIG;
1953 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1957 phy->polarity_correction = (phy_data &
1958 M88E1000_PSCR_POLARITY_REVERSAL);
1960 ret_val = e1000_check_polarity_m88(hw);
1964 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1968 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1970 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1971 ret_val = e1000_get_cable_length(hw);
1975 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1979 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1980 ? e1000_1000t_rx_status_ok
1981 : e1000_1000t_rx_status_not_ok;
1983 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1984 ? e1000_1000t_rx_status_ok
1985 : e1000_1000t_rx_status_not_ok;
1987 /* Set values to "undefined" */
1988 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1989 phy->local_rx = e1000_1000t_rx_status_undefined;
1990 phy->remote_rx = e1000_1000t_rx_status_undefined;
1997 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1998 * @hw: pointer to the HW structure
2000 * Read PHY status to determine if link is up. If link is up, then
2001 * set/determine 10base-T extended distance and polarity correction. Read
2002 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2003 * determine on the cable length, local and remote receiver.
2005 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
2007 struct e1000_phy_info *phy = &hw->phy;
2012 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2017 e_dbg("Phy info is only valid if link is up\n");
2018 return -E1000_ERR_CONFIG;
2021 phy->polarity_correction = true;
2023 ret_val = e1000_check_polarity_igp(hw);
2027 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2031 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
2033 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2034 IGP01E1000_PSSR_SPEED_1000MBPS) {
2035 ret_val = e1000_get_cable_length(hw);
2039 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
2043 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2044 ? e1000_1000t_rx_status_ok
2045 : e1000_1000t_rx_status_not_ok;
2047 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2048 ? e1000_1000t_rx_status_ok
2049 : e1000_1000t_rx_status_not_ok;
2051 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2052 phy->local_rx = e1000_1000t_rx_status_undefined;
2053 phy->remote_rx = e1000_1000t_rx_status_undefined;
2060 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2061 * @hw: pointer to the HW structure
2063 * Populates "phy" structure with various feature states.
2065 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2067 struct e1000_phy_info *phy = &hw->phy;
2072 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
2077 e_dbg("Phy info is only valid if link is up\n");
2078 ret_val = -E1000_ERR_CONFIG;
2082 ret_val = e1e_rphy(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2085 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2088 if (phy->polarity_correction) {
2089 ret_val = e1000_check_polarity_ife(hw);
2093 /* Polarity is forced */
2094 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2095 ? e1000_rev_polarity_reversed
2096 : e1000_rev_polarity_normal;
2099 ret_val = e1e_rphy(hw, IFE_PHY_MDIX_CONTROL, &data);
2103 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? true : false;
2105 /* The following parameters are undefined for 10/100 operation. */
2106 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2107 phy->local_rx = e1000_1000t_rx_status_undefined;
2108 phy->remote_rx = e1000_1000t_rx_status_undefined;
2115 * e1000e_phy_sw_reset - PHY software reset
2116 * @hw: pointer to the HW structure
2118 * Does a software reset of the PHY by reading the PHY control register and
2119 * setting/write the control register reset bit to the PHY.
2121 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
2126 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
2130 phy_ctrl |= MII_CR_RESET;
2131 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
2141 * e1000e_phy_hw_reset_generic - PHY hardware reset
2142 * @hw: pointer to the HW structure
2144 * Verify the reset block is not blocking us from resetting. Acquire
2145 * semaphore (if necessary) and read/set/write the device control reset
2146 * bit in the PHY. Wait the appropriate delay time for the device to
2147 * reset and release the semaphore (if necessary).
2149 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
2151 struct e1000_phy_info *phy = &hw->phy;
2155 ret_val = e1000_check_reset_block(hw);
2159 ret_val = phy->ops.acquire(hw);
2164 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
2167 udelay(phy->reset_delay_us);
2174 phy->ops.release(hw);
2176 return e1000_get_phy_cfg_done(hw);
2180 * e1000e_get_cfg_done - Generic configuration done
2181 * @hw: pointer to the HW structure
2183 * Generic function to wait 10 milli-seconds for configuration to complete
2184 * and return success.
2186 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
2193 * e1000e_phy_init_script_igp3 - Inits the IGP3 PHY
2194 * @hw: pointer to the HW structure
2196 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2198 s32 e1000e_phy_init_script_igp3(struct e1000_hw *hw)
2200 e_dbg("Running IGP 3 PHY init script\n");
2202 /* PHY init IGP 3 */
2203 /* Enable rise/fall, 10-mode work in class-A */
2204 e1e_wphy(hw, 0x2F5B, 0x9018);
2205 /* Remove all caps from Replica path filter */
2206 e1e_wphy(hw, 0x2F52, 0x0000);
2207 /* Bias trimming for ADC, AFE and Driver (Default) */
2208 e1e_wphy(hw, 0x2FB1, 0x8B24);
2209 /* Increase Hybrid poly bias */
2210 e1e_wphy(hw, 0x2FB2, 0xF8F0);
2211 /* Add 4% to Tx amplitude in Gig mode */
2212 e1e_wphy(hw, 0x2010, 0x10B0);
2213 /* Disable trimming (TTT) */
2214 e1e_wphy(hw, 0x2011, 0x0000);
2215 /* Poly DC correction to 94.6% + 2% for all channels */
2216 e1e_wphy(hw, 0x20DD, 0x249A);
2217 /* ABS DC correction to 95.9% */
2218 e1e_wphy(hw, 0x20DE, 0x00D3);
2219 /* BG temp curve trim */
2220 e1e_wphy(hw, 0x28B4, 0x04CE);
2221 /* Increasing ADC OPAMP stage 1 currents to max */
2222 e1e_wphy(hw, 0x2F70, 0x29E4);
2223 /* Force 1000 ( required for enabling PHY regs configuration) */
2224 e1e_wphy(hw, 0x0000, 0x0140);
2225 /* Set upd_freq to 6 */
2226 e1e_wphy(hw, 0x1F30, 0x1606);
2228 e1e_wphy(hw, 0x1F31, 0xB814);
2229 /* Disable adaptive fixed FFE (Default) */
2230 e1e_wphy(hw, 0x1F35, 0x002A);
2231 /* Enable FFE hysteresis */
2232 e1e_wphy(hw, 0x1F3E, 0x0067);
2233 /* Fixed FFE for short cable lengths */
2234 e1e_wphy(hw, 0x1F54, 0x0065);
2235 /* Fixed FFE for medium cable lengths */
2236 e1e_wphy(hw, 0x1F55, 0x002A);
2237 /* Fixed FFE for long cable lengths */
2238 e1e_wphy(hw, 0x1F56, 0x002A);
2239 /* Enable Adaptive Clip Threshold */
2240 e1e_wphy(hw, 0x1F72, 0x3FB0);
2241 /* AHT reset limit to 1 */
2242 e1e_wphy(hw, 0x1F76, 0xC0FF);
2243 /* Set AHT master delay to 127 msec */
2244 e1e_wphy(hw, 0x1F77, 0x1DEC);
2245 /* Set scan bits for AHT */
2246 e1e_wphy(hw, 0x1F78, 0xF9EF);
2247 /* Set AHT Preset bits */
2248 e1e_wphy(hw, 0x1F79, 0x0210);
2249 /* Change integ_factor of channel A to 3 */
2250 e1e_wphy(hw, 0x1895, 0x0003);
2251 /* Change prop_factor of channels BCD to 8 */
2252 e1e_wphy(hw, 0x1796, 0x0008);
2253 /* Change cg_icount + enable integbp for channels BCD */
2254 e1e_wphy(hw, 0x1798, 0xD008);
2256 * Change cg_icount + enable integbp + change prop_factor_master
2257 * to 8 for channel A
2259 e1e_wphy(hw, 0x1898, 0xD918);
2260 /* Disable AHT in Slave mode on channel A */
2261 e1e_wphy(hw, 0x187A, 0x0800);
2263 * Enable LPLU and disable AN to 1000 in non-D0a states,
2266 e1e_wphy(hw, 0x0019, 0x008D);
2267 /* Enable restart AN on an1000_dis change */
2268 e1e_wphy(hw, 0x001B, 0x2080);
2269 /* Enable wh_fifo read clock in 10/100 modes */
2270 e1e_wphy(hw, 0x0014, 0x0045);
2271 /* Restart AN, Speed selection is 1000 */
2272 e1e_wphy(hw, 0x0000, 0x1340);
2277 /* Internal function pointers */
2280 * e1000_get_phy_cfg_done - Generic PHY configuration done
2281 * @hw: pointer to the HW structure
2283 * Return success if silicon family did not implement a family specific
2284 * get_cfg_done function.
2286 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
2288 if (hw->phy.ops.get_cfg_done)
2289 return hw->phy.ops.get_cfg_done(hw);
2295 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
2296 * @hw: pointer to the HW structure
2298 * When the silicon family has not implemented a forced speed/duplex
2299 * function for the PHY, simply return 0.
2301 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2303 if (hw->phy.ops.force_speed_duplex)
2304 return hw->phy.ops.force_speed_duplex(hw);
2310 * e1000e_get_phy_type_from_id - Get PHY type from id
2311 * @phy_id: phy_id read from the phy
2313 * Returns the phy type from the id.
2315 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2317 enum e1000_phy_type phy_type = e1000_phy_unknown;
2320 case M88E1000_I_PHY_ID:
2321 case M88E1000_E_PHY_ID:
2322 case M88E1111_I_PHY_ID:
2323 case M88E1011_I_PHY_ID:
2324 phy_type = e1000_phy_m88;
2326 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2327 phy_type = e1000_phy_igp_2;
2329 case GG82563_E_PHY_ID:
2330 phy_type = e1000_phy_gg82563;
2332 case IGP03E1000_E_PHY_ID:
2333 phy_type = e1000_phy_igp_3;
2336 case IFE_PLUS_E_PHY_ID:
2337 case IFE_C_E_PHY_ID:
2338 phy_type = e1000_phy_ife;
2340 case BME1000_E_PHY_ID:
2341 case BME1000_E_PHY_ID_R2:
2342 phy_type = e1000_phy_bm;
2344 case I82578_E_PHY_ID:
2345 phy_type = e1000_phy_82578;
2347 case I82577_E_PHY_ID:
2348 phy_type = e1000_phy_82577;
2350 case I82579_E_PHY_ID:
2351 phy_type = e1000_phy_82579;
2354 phy_type = e1000_phy_unknown;
2361 * e1000e_determine_phy_address - Determines PHY address.
2362 * @hw: pointer to the HW structure
2364 * This uses a trial and error method to loop through possible PHY
2365 * addresses. It tests each by reading the PHY ID registers and
2366 * checking for a match.
2368 s32 e1000e_determine_phy_address(struct e1000_hw *hw)
2370 s32 ret_val = -E1000_ERR_PHY_TYPE;
2373 enum e1000_phy_type phy_type = e1000_phy_unknown;
2375 hw->phy.id = phy_type;
2377 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2378 hw->phy.addr = phy_addr;
2382 e1000e_get_phy_id(hw);
2383 phy_type = e1000e_get_phy_type_from_id(hw->phy.id);
2386 * If phy_type is valid, break - we found our
2389 if (phy_type != e1000_phy_unknown) {
2393 usleep_range(1000, 2000);
2403 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address
2404 * @page: page to access
2406 * Returns the phy address for the page requested.
2408 static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg)
2412 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31))
2419 * e1000e_write_phy_reg_bm - Write BM PHY register
2420 * @hw: pointer to the HW structure
2421 * @offset: register offset to write to
2422 * @data: data to write at register offset
2424 * Acquires semaphore, if necessary, then writes the data to PHY register
2425 * at the offset. Release any acquired semaphores before exiting.
2427 s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data)
2430 u32 page = offset >> IGP_PAGE_SHIFT;
2432 ret_val = hw->phy.ops.acquire(hw);
2436 /* Page 800 works differently than the rest so it has its own func */
2437 if (page == BM_WUC_PAGE) {
2438 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2443 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2445 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2446 u32 page_shift, page_select;
2449 * Page select is register 31 for phy address 1 and 22 for
2450 * phy address 2 and 3. Page select is shifted only for
2453 if (hw->phy.addr == 1) {
2454 page_shift = IGP_PAGE_SHIFT;
2455 page_select = IGP01E1000_PHY_PAGE_SELECT;
2458 page_select = BM_PHY_PAGE_SELECT;
2461 /* Page is shifted left, PHY expects (page x 32) */
2462 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2463 (page << page_shift));
2468 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2472 hw->phy.ops.release(hw);
2477 * e1000e_read_phy_reg_bm - Read BM PHY register
2478 * @hw: pointer to the HW structure
2479 * @offset: register offset to be read
2480 * @data: pointer to the read data
2482 * Acquires semaphore, if necessary, then reads the PHY register at offset
2483 * and storing the retrieved information in data. Release any acquired
2484 * semaphores before exiting.
2486 s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data)
2489 u32 page = offset >> IGP_PAGE_SHIFT;
2491 ret_val = hw->phy.ops.acquire(hw);
2495 /* Page 800 works differently than the rest so it has its own func */
2496 if (page == BM_WUC_PAGE) {
2497 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2502 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset);
2504 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2505 u32 page_shift, page_select;
2508 * Page select is register 31 for phy address 1 and 22 for
2509 * phy address 2 and 3. Page select is shifted only for
2512 if (hw->phy.addr == 1) {
2513 page_shift = IGP_PAGE_SHIFT;
2514 page_select = IGP01E1000_PHY_PAGE_SELECT;
2517 page_select = BM_PHY_PAGE_SELECT;
2520 /* Page is shifted left, PHY expects (page x 32) */
2521 ret_val = e1000e_write_phy_reg_mdic(hw, page_select,
2522 (page << page_shift));
2527 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2530 hw->phy.ops.release(hw);
2535 * e1000e_read_phy_reg_bm2 - Read BM PHY register
2536 * @hw: pointer to the HW structure
2537 * @offset: register offset to be read
2538 * @data: pointer to the read data
2540 * Acquires semaphore, if necessary, then reads the PHY register at offset
2541 * and storing the retrieved information in data. Release any acquired
2542 * semaphores before exiting.
2544 s32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data)
2547 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2549 ret_val = hw->phy.ops.acquire(hw);
2553 /* Page 800 works differently than the rest so it has its own func */
2554 if (page == BM_WUC_PAGE) {
2555 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2562 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2564 /* Page is shifted left, PHY expects (page x 32) */
2565 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2572 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2575 hw->phy.ops.release(hw);
2580 * e1000e_write_phy_reg_bm2 - Write BM PHY register
2581 * @hw: pointer to the HW structure
2582 * @offset: register offset to write to
2583 * @data: data to write at register offset
2585 * Acquires semaphore, if necessary, then writes the data to PHY register
2586 * at the offset. Release any acquired semaphores before exiting.
2588 s32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data)
2591 u16 page = (u16)(offset >> IGP_PAGE_SHIFT);
2593 ret_val = hw->phy.ops.acquire(hw);
2597 /* Page 800 works differently than the rest so it has its own func */
2598 if (page == BM_WUC_PAGE) {
2599 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
2606 if (offset > MAX_PHY_MULTI_PAGE_REG) {
2607 /* Page is shifted left, PHY expects (page x 32) */
2608 ret_val = e1000e_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT,
2615 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
2619 hw->phy.ops.release(hw);
2624 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers
2625 * @hw: pointer to the HW structure
2626 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG
2628 * Assumes semaphore already acquired and phy_reg points to a valid memory
2629 * address to store contents of the BM_WUC_ENABLE_REG register.
2631 s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2636 /* All page select, port ctrl and wakeup registers use phy address 1 */
2639 /* Select Port Control Registers page */
2640 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2642 e_dbg("Could not set Port Control page\n");
2646 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg);
2648 e_dbg("Could not read PHY register %d.%d\n",
2649 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2654 * Enable both PHY wakeup mode and Wakeup register page writes.
2655 * Prevent a power state change by disabling ME and Host PHY wakeup.
2658 temp |= BM_WUC_ENABLE_BIT;
2659 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT);
2661 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp);
2663 e_dbg("Could not write PHY register %d.%d\n",
2664 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2668 /* Select Host Wakeup Registers page */
2669 ret_val = e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT));
2671 /* caller now able to write registers on the Wakeup registers page */
2677 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs
2678 * @hw: pointer to the HW structure
2679 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG
2681 * Restore BM_WUC_ENABLE_REG to its original value.
2683 * Assumes semaphore already acquired and *phy_reg is the contents of the
2684 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by
2687 s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg)
2691 /* Select Port Control Registers page */
2692 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT));
2694 e_dbg("Could not set Port Control page\n");
2698 /* Restore 769.17 to its original value */
2699 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg);
2701 e_dbg("Could not restore PHY register %d.%d\n",
2702 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG);
2708 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register
2709 * @hw: pointer to the HW structure
2710 * @offset: register offset to be read or written
2711 * @data: pointer to the data to read or write
2712 * @read: determines if operation is read or write
2713 * @page_set: BM_WUC_PAGE already set and access enabled
2715 * Read the PHY register at offset and store the retrieved information in
2716 * data, or write data to PHY register at offset. Note the procedure to
2717 * access the PHY wakeup registers is different than reading the other PHY
2718 * registers. It works as such:
2719 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1
2720 * 2) Set page to 800 for host (801 if we were manageability)
2721 * 3) Write the address using the address opcode (0x11)
2722 * 4) Read or write the data using the data opcode (0x12)
2723 * 5) Restore 769.17.2 to its original value
2725 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and
2726 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm().
2728 * Assumes semaphore is already acquired. When page_set==true, assumes
2729 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack
2730 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()).
2732 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
2733 u16 *data, bool read, bool page_set)
2736 u16 reg = BM_PHY_REG_NUM(offset);
2737 u16 page = BM_PHY_REG_PAGE(offset);
2740 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */
2741 if ((hw->mac.type == e1000_pchlan) &&
2742 (!(er32(PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE)))
2743 e_dbg("Attempting to access page %d while gig enabled.\n",
2747 /* Enable access to PHY wakeup registers */
2748 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2750 e_dbg("Could not enable PHY wakeup reg access\n");
2755 e_dbg("Accessing PHY page %d reg 0x%x\n", page, reg);
2757 /* Write the Wakeup register page offset value using opcode 0x11 */
2758 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg);
2760 e_dbg("Could not write address opcode to page %d\n", page);
2765 /* Read the Wakeup register page value using opcode 0x12 */
2766 ret_val = e1000e_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2769 /* Write the Wakeup register page value using opcode 0x12 */
2770 ret_val = e1000e_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE,
2775 e_dbg("Could not access PHY reg %d.%d\n", page, reg);
2780 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg);
2787 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2788 * @hw: pointer to the HW structure
2790 * In the case of a PHY power down to save power, or to turn off link during a
2791 * driver unload, or wake on lan is not enabled, restore the link to previous
2794 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2798 /* The PHY will retain its settings across a power down/up cycle */
2799 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2800 mii_reg &= ~MII_CR_POWER_DOWN;
2801 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2805 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2806 * @hw: pointer to the HW structure
2808 * In the case of a PHY power down to save power, or to turn off link during a
2809 * driver unload, or wake on lan is not enabled, restore the link to previous
2812 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2816 /* The PHY will retain its settings across a power down/up cycle */
2817 e1e_rphy(hw, PHY_CONTROL, &mii_reg);
2818 mii_reg |= MII_CR_POWER_DOWN;
2819 e1e_wphy(hw, PHY_CONTROL, mii_reg);
2820 usleep_range(1000, 2000);
2824 * e1000e_commit_phy - Soft PHY reset
2825 * @hw: pointer to the HW structure
2827 * Performs a soft PHY reset on those that apply. This is a function pointer
2828 * entry point called by drivers.
2830 s32 e1000e_commit_phy(struct e1000_hw *hw)
2832 if (hw->phy.ops.commit)
2833 return hw->phy.ops.commit(hw);
2839 * e1000_set_d0_lplu_state - Sets low power link up state for D0
2840 * @hw: pointer to the HW structure
2841 * @active: boolean used to enable/disable lplu
2843 * Success returns 0, Failure returns 1
2845 * The low power link up (lplu) state is set to the power management level D0
2846 * and SmartSpeed is disabled when active is true, else clear lplu for D0
2847 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
2848 * is used during Dx states where the power conservation is most important.
2849 * During driver activity, SmartSpeed should be enabled so performance is
2850 * maintained. This is a function pointer entry point called by drivers.
2852 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
2854 if (hw->phy.ops.set_d0_lplu_state)
2855 return hw->phy.ops.set_d0_lplu_state(hw, active);
2861 * __e1000_read_phy_reg_hv - Read HV PHY register
2862 * @hw: pointer to the HW structure
2863 * @offset: register offset to be read
2864 * @data: pointer to the read data
2865 * @locked: semaphore has already been acquired or not
2867 * Acquires semaphore, if necessary, then reads the PHY register at offset
2868 * and stores the retrieved information in data. Release any acquired
2869 * semaphore before exiting.
2871 static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data,
2872 bool locked, bool page_set)
2875 u16 page = BM_PHY_REG_PAGE(offset);
2876 u16 reg = BM_PHY_REG_NUM(offset);
2877 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2880 ret_val = hw->phy.ops.acquire(hw);
2885 /* Page 800 works differently than the rest so it has its own func */
2886 if (page == BM_WUC_PAGE) {
2887 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data,
2892 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
2893 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
2899 if (page == HV_INTC_FC_PAGE_START)
2902 if (reg > MAX_PHY_MULTI_PAGE_REG) {
2903 /* Page is shifted left, PHY expects (page x 32) */
2904 ret_val = e1000_set_page_igp(hw,
2905 (page << IGP_PAGE_SHIFT));
2907 hw->phy.addr = phy_addr;
2914 e_dbg("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
2915 page << IGP_PAGE_SHIFT, reg);
2917 ret_val = e1000e_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
2921 hw->phy.ops.release(hw);
2927 * e1000_read_phy_reg_hv - Read HV PHY register
2928 * @hw: pointer to the HW structure
2929 * @offset: register offset to be read
2930 * @data: pointer to the read data
2932 * Acquires semaphore then reads the PHY register at offset and stores
2933 * the retrieved information in data. Release the acquired semaphore
2936 s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2938 return __e1000_read_phy_reg_hv(hw, offset, data, false, false);
2942 * e1000_read_phy_reg_hv_locked - Read HV PHY register
2943 * @hw: pointer to the HW structure
2944 * @offset: register offset to be read
2945 * @data: pointer to the read data
2947 * Reads the PHY register at offset and stores the retrieved information
2948 * in data. Assumes semaphore already acquired.
2950 s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data)
2952 return __e1000_read_phy_reg_hv(hw, offset, data, true, false);
2956 * e1000_read_phy_reg_page_hv - Read HV PHY register
2957 * @hw: pointer to the HW structure
2958 * @offset: register offset to write to
2959 * @data: data to write at register offset
2961 * Reads the PHY register at offset and stores the retrieved information
2962 * in data. Assumes semaphore already acquired and page already set.
2964 s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data)
2966 return __e1000_read_phy_reg_hv(hw, offset, data, true, true);
2970 * __e1000_write_phy_reg_hv - Write HV PHY register
2971 * @hw: pointer to the HW structure
2972 * @offset: register offset to write to
2973 * @data: data to write at register offset
2974 * @locked: semaphore has already been acquired or not
2976 * Acquires semaphore, if necessary, then writes the data to PHY register
2977 * at the offset. Release any acquired semaphores before exiting.
2979 static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data,
2980 bool locked, bool page_set)
2983 u16 page = BM_PHY_REG_PAGE(offset);
2984 u16 reg = BM_PHY_REG_NUM(offset);
2985 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page);
2988 ret_val = hw->phy.ops.acquire(hw);
2993 /* Page 800 works differently than the rest so it has its own func */
2994 if (page == BM_WUC_PAGE) {
2995 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data,
3000 if (page > 0 && page < HV_INTC_FC_PAGE_START) {
3001 ret_val = e1000_access_phy_debug_regs_hv(hw, offset,
3007 if (page == HV_INTC_FC_PAGE_START)
3011 * Workaround MDIO accesses being disabled after entering IEEE
3012 * Power Down (when bit 11 of the PHY Control register is set)
3014 if ((hw->phy.type == e1000_phy_82578) &&
3015 (hw->phy.revision >= 1) &&
3016 (hw->phy.addr == 2) &&
3017 ((MAX_PHY_REG_ADDRESS & reg) == 0) && (data & (1 << 11))) {
3019 ret_val = e1000_access_phy_debug_regs_hv(hw,
3026 if (reg > MAX_PHY_MULTI_PAGE_REG) {
3027 /* Page is shifted left, PHY expects (page x 32) */
3028 ret_val = e1000_set_page_igp(hw,
3029 (page << IGP_PAGE_SHIFT));
3031 hw->phy.addr = phy_addr;
3038 e_dbg("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page,
3039 page << IGP_PAGE_SHIFT, reg);
3041 ret_val = e1000e_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg,
3046 hw->phy.ops.release(hw);
3052 * e1000_write_phy_reg_hv - Write HV PHY register
3053 * @hw: pointer to the HW structure
3054 * @offset: register offset to write to
3055 * @data: data to write at register offset
3057 * Acquires semaphore then writes the data to PHY register at the offset.
3058 * Release the acquired semaphores before exiting.
3060 s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data)
3062 return __e1000_write_phy_reg_hv(hw, offset, data, false, false);
3066 * e1000_write_phy_reg_hv_locked - Write HV PHY register
3067 * @hw: pointer to the HW structure
3068 * @offset: register offset to write to
3069 * @data: data to write at register offset
3071 * Writes the data to PHY register at the offset. Assumes semaphore
3074 s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data)
3076 return __e1000_write_phy_reg_hv(hw, offset, data, true, false);
3080 * e1000_write_phy_reg_page_hv - Write HV PHY register
3081 * @hw: pointer to the HW structure
3082 * @offset: register offset to write to
3083 * @data: data to write at register offset
3085 * Writes the data to PHY register at the offset. Assumes semaphore
3086 * already acquired and page already set.
3088 s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data)
3090 return __e1000_write_phy_reg_hv(hw, offset, data, true, true);
3094 * e1000_get_phy_addr_for_hv_page - Get PHY address based on page
3095 * @page: page to be accessed
3097 static u32 e1000_get_phy_addr_for_hv_page(u32 page)
3101 if (page >= HV_INTC_FC_PAGE_START)
3108 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers
3109 * @hw: pointer to the HW structure
3110 * @offset: register offset to be read or written
3111 * @data: pointer to the data to be read or written
3112 * @read: determines if operation is read or write
3114 * Reads the PHY register at offset and stores the retreived information
3115 * in data. Assumes semaphore already acquired. Note that the procedure
3116 * to access these regs uses the address port and data port to read/write.
3117 * These accesses done with PHY address 2 and without using pages.
3119 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
3120 u16 *data, bool read)
3126 /* This takes care of the difference with desktop vs mobile phy */
3127 addr_reg = (hw->phy.type == e1000_phy_82578) ?
3128 I82578_ADDR_REG : I82577_ADDR_REG;
3129 data_reg = addr_reg + 1;
3131 /* All operations in this function are phy address 2 */
3134 /* masking with 0x3F to remove the page from offset */
3135 ret_val = e1000e_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F);
3137 e_dbg("Could not write the Address Offset port register\n");
3141 /* Read or write the data value next */
3143 ret_val = e1000e_read_phy_reg_mdic(hw, data_reg, data);
3145 ret_val = e1000e_write_phy_reg_mdic(hw, data_reg, *data);
3148 e_dbg("Could not access the Data port register\n");
3157 * e1000_link_stall_workaround_hv - Si workaround
3158 * @hw: pointer to the HW structure
3160 * This function works around a Si bug where the link partner can get
3161 * a link up indication before the PHY does. If small packets are sent
3162 * by the link partner they can be placed in the packet buffer without
3163 * being properly accounted for by the PHY and will stall preventing
3164 * further packets from being received. The workaround is to clear the
3165 * packet buffer after the PHY detects link up.
3167 s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw)
3172 if (hw->phy.type != e1000_phy_82578)
3175 /* Do not apply workaround if in PHY loopback bit 14 set */
3176 e1e_rphy(hw, PHY_CONTROL, &data);
3177 if (data & PHY_CONTROL_LB)
3180 /* check if link is up and at 1Gbps */
3181 ret_val = e1e_rphy(hw, BM_CS_STATUS, &data);
3185 data &= BM_CS_STATUS_LINK_UP |
3186 BM_CS_STATUS_RESOLVED |
3187 BM_CS_STATUS_SPEED_MASK;
3189 if (data != (BM_CS_STATUS_LINK_UP |
3190 BM_CS_STATUS_RESOLVED |
3191 BM_CS_STATUS_SPEED_1000))
3196 /* flush the packets in the fifo buffer */
3197 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC |
3198 HV_MUX_DATA_CTRL_FORCE_SPEED);
3202 ret_val = e1e_wphy(hw, HV_MUX_DATA_CTRL, HV_MUX_DATA_CTRL_GEN_TO_MAC);
3209 * e1000_check_polarity_82577 - Checks the polarity.
3210 * @hw: pointer to the HW structure
3212 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
3214 * Polarity is determined based on the PHY specific status register.
3216 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
3218 struct e1000_phy_info *phy = &hw->phy;
3222 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3225 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
3226 ? e1000_rev_polarity_reversed
3227 : e1000_rev_polarity_normal;
3233 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
3234 * @hw: pointer to the HW structure
3236 * Calls the PHY setup function to force speed and duplex.
3238 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
3240 struct e1000_phy_info *phy = &hw->phy;
3245 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
3249 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
3251 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
3257 if (phy->autoneg_wait_to_complete) {
3258 e_dbg("Waiting for forced speed/duplex link on 82577 phy\n");
3260 ret_val = e1000e_phy_has_link_generic(hw,
3268 e_dbg("Link taking longer than expected.\n");
3271 ret_val = e1000e_phy_has_link_generic(hw,
3284 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
3285 * @hw: pointer to the HW structure
3287 * Read PHY status to determine if link is up. If link is up, then
3288 * set/determine 10base-T extended distance and polarity correction. Read
3289 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
3290 * determine on the cable length, local and remote receiver.
3292 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
3294 struct e1000_phy_info *phy = &hw->phy;
3299 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
3304 e_dbg("Phy info is only valid if link is up\n");
3305 ret_val = -E1000_ERR_CONFIG;
3309 phy->polarity_correction = true;
3311 ret_val = e1000_check_polarity_82577(hw);
3315 ret_val = e1e_rphy(hw, I82577_PHY_STATUS_2, &data);
3319 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? true : false;
3321 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
3322 I82577_PHY_STATUS2_SPEED_1000MBPS) {
3323 ret_val = hw->phy.ops.get_cable_length(hw);
3327 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
3331 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
3332 ? e1000_1000t_rx_status_ok
3333 : e1000_1000t_rx_status_not_ok;
3335 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
3336 ? e1000_1000t_rx_status_ok
3337 : e1000_1000t_rx_status_not_ok;
3339 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
3340 phy->local_rx = e1000_1000t_rx_status_undefined;
3341 phy->remote_rx = e1000_1000t_rx_status_undefined;
3349 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
3350 * @hw: pointer to the HW structure
3352 * Reads the diagnostic status register and verifies result is valid before
3353 * placing it in the phy_cable_length field.
3355 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
3357 struct e1000_phy_info *phy = &hw->phy;
3359 u16 phy_data, length;
3361 ret_val = e1e_rphy(hw, I82577_PHY_DIAG_STATUS, &phy_data);
3365 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
3366 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
3368 if (length == E1000_CABLE_LENGTH_UNDEFINED)
3369 ret_val = -E1000_ERR_PHY;
3371 phy->cable_length = length;