3 * Alchemy Au1x00 ethernet driver
5 * Copyright 2001-2003, 2006 MontaVista Software Inc.
6 * Copyright 2002 TimeSys Corp.
7 * Added ethtool/mii-tool support,
8 * Copyright 2004 Matt Porter <mporter@kernel.crashing.org>
9 * Update: 2004 Bjoern Riemer, riemer@fokus.fraunhofer.de
10 * or riemer@riemer-nt.de: fixed the link beat detection with
11 * ioctls (SIOCGMIIPHY)
12 * Copyright 2006 Herbert Valerio Riedel <hvr@gnu.org>
13 * converted to use linux-2.6.x's PHY framework
15 * Author: MontaVista Software, Inc.
16 * ppopov@mvista.com or source@mvista.com
18 * ########################################################################
20 * This program is free software; you can distribute it and/or modify it
21 * under the terms of the GNU General Public License (Version 2) as
22 * published by the Free Software Foundation.
24 * This program is distributed in the hope it will be useful, but WITHOUT
25 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, see <http://www.gnu.org/licenses/>.
32 * ########################################################################
36 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
38 #include <linux/capability.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/module.h>
41 #include <linux/kernel.h>
42 #include <linux/string.h>
43 #include <linux/timer.h>
44 #include <linux/errno.h>
46 #include <linux/ioport.h>
47 #include <linux/bitops.h>
48 #include <linux/slab.h>
49 #include <linux/interrupt.h>
50 #include <linux/netdevice.h>
51 #include <linux/etherdevice.h>
52 #include <linux/ethtool.h>
53 #include <linux/mii.h>
54 #include <linux/skbuff.h>
55 #include <linux/delay.h>
56 #include <linux/crc32.h>
57 #include <linux/phy.h>
58 #include <linux/platform_device.h>
59 #include <linux/cpu.h>
62 #include <asm/mipsregs.h>
64 #include <asm/processor.h>
67 #include <au1xxx_eth.h>
70 #include "au1000_eth.h"
72 #ifdef AU1000_ETH_DEBUG
73 static int au1000_debug = 5;
75 static int au1000_debug = 3;
78 #define AU1000_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
82 #define DRV_NAME "au1000_eth"
83 #define DRV_VERSION "1.7"
84 #define DRV_AUTHOR "Pete Popov <ppopov@embeddedalley.com>"
85 #define DRV_DESC "Au1xxx on-chip Ethernet driver"
87 MODULE_AUTHOR(DRV_AUTHOR);
88 MODULE_DESCRIPTION(DRV_DESC);
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_VERSION);
92 /* AU1000 MAC registers and bits */
93 #define MAC_CONTROL 0x0
94 # define MAC_RX_ENABLE (1 << 2)
95 # define MAC_TX_ENABLE (1 << 3)
96 # define MAC_DEF_CHECK (1 << 5)
97 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
98 # define MAC_AUTO_PAD (1 << 8)
99 # define MAC_DISABLE_RETRY (1 << 10)
100 # define MAC_DISABLE_BCAST (1 << 11)
101 # define MAC_LATE_COL (1 << 12)
102 # define MAC_HASH_MODE (1 << 13)
103 # define MAC_HASH_ONLY (1 << 15)
104 # define MAC_PASS_ALL (1 << 16)
105 # define MAC_INVERSE_FILTER (1 << 17)
106 # define MAC_PROMISCUOUS (1 << 18)
107 # define MAC_PASS_ALL_MULTI (1 << 19)
108 # define MAC_FULL_DUPLEX (1 << 20)
109 # define MAC_NORMAL_MODE 0
110 # define MAC_INT_LOOPBACK (1 << 21)
111 # define MAC_EXT_LOOPBACK (1 << 22)
112 # define MAC_DISABLE_RX_OWN (1 << 23)
113 # define MAC_BIG_ENDIAN (1 << 30)
114 # define MAC_RX_ALL (1 << 31)
115 #define MAC_ADDRESS_HIGH 0x4
116 #define MAC_ADDRESS_LOW 0x8
117 #define MAC_MCAST_HIGH 0xC
118 #define MAC_MCAST_LOW 0x10
119 #define MAC_MII_CNTRL 0x14
120 # define MAC_MII_BUSY (1 << 0)
121 # define MAC_MII_READ 0
122 # define MAC_MII_WRITE (1 << 1)
123 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
124 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
125 #define MAC_MII_DATA 0x18
126 #define MAC_FLOW_CNTRL 0x1C
127 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
128 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
129 # define MAC_PASS_CONTROL (1 << 2)
130 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
131 #define MAC_VLAN1_TAG 0x20
132 #define MAC_VLAN2_TAG 0x24
134 /* Ethernet Controller Enable */
135 # define MAC_EN_CLOCK_ENABLE (1 << 0)
136 # define MAC_EN_RESET0 (1 << 1)
137 # define MAC_EN_TOSS (0 << 2)
138 # define MAC_EN_CACHEABLE (1 << 3)
139 # define MAC_EN_RESET1 (1 << 4)
140 # define MAC_EN_RESET2 (1 << 5)
141 # define MAC_DMA_RESET (1 << 6)
143 /* Ethernet Controller DMA Channels */
144 /* offsets from MAC_TX_RING_ADDR address */
145 #define MAC_TX_BUFF0_STATUS 0x0
146 # define TX_FRAME_ABORTED (1 << 0)
147 # define TX_JAB_TIMEOUT (1 << 1)
148 # define TX_NO_CARRIER (1 << 2)
149 # define TX_LOSS_CARRIER (1 << 3)
150 # define TX_EXC_DEF (1 << 4)
151 # define TX_LATE_COLL_ABORT (1 << 5)
152 # define TX_EXC_COLL (1 << 6)
153 # define TX_UNDERRUN (1 << 7)
154 # define TX_DEFERRED (1 << 8)
155 # define TX_LATE_COLL (1 << 9)
156 # define TX_COLL_CNT_MASK (0xF << 10)
157 # define TX_PKT_RETRY (1 << 31)
158 #define MAC_TX_BUFF0_ADDR 0x4
159 # define TX_DMA_ENABLE (1 << 0)
160 # define TX_T_DONE (1 << 1)
161 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
162 #define MAC_TX_BUFF0_LEN 0x8
163 #define MAC_TX_BUFF1_STATUS 0x10
164 #define MAC_TX_BUFF1_ADDR 0x14
165 #define MAC_TX_BUFF1_LEN 0x18
166 #define MAC_TX_BUFF2_STATUS 0x20
167 #define MAC_TX_BUFF2_ADDR 0x24
168 #define MAC_TX_BUFF2_LEN 0x28
169 #define MAC_TX_BUFF3_STATUS 0x30
170 #define MAC_TX_BUFF3_ADDR 0x34
171 #define MAC_TX_BUFF3_LEN 0x38
173 /* offsets from MAC_RX_RING_ADDR */
174 #define MAC_RX_BUFF0_STATUS 0x0
175 # define RX_FRAME_LEN_MASK 0x3fff
176 # define RX_WDOG_TIMER (1 << 14)
177 # define RX_RUNT (1 << 15)
178 # define RX_OVERLEN (1 << 16)
179 # define RX_COLL (1 << 17)
180 # define RX_ETHER (1 << 18)
181 # define RX_MII_ERROR (1 << 19)
182 # define RX_DRIBBLING (1 << 20)
183 # define RX_CRC_ERROR (1 << 21)
184 # define RX_VLAN1 (1 << 22)
185 # define RX_VLAN2 (1 << 23)
186 # define RX_LEN_ERROR (1 << 24)
187 # define RX_CNTRL_FRAME (1 << 25)
188 # define RX_U_CNTRL_FRAME (1 << 26)
189 # define RX_MCAST_FRAME (1 << 27)
190 # define RX_BCAST_FRAME (1 << 28)
191 # define RX_FILTER_FAIL (1 << 29)
192 # define RX_PACKET_FILTER (1 << 30)
193 # define RX_MISSED_FRAME (1 << 31)
195 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
196 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
197 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
198 #define MAC_RX_BUFF0_ADDR 0x4
199 # define RX_DMA_ENABLE (1 << 0)
200 # define RX_T_DONE (1 << 1)
201 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
202 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
203 #define MAC_RX_BUFF1_STATUS 0x10
204 #define MAC_RX_BUFF1_ADDR 0x14
205 #define MAC_RX_BUFF2_STATUS 0x20
206 #define MAC_RX_BUFF2_ADDR 0x24
207 #define MAC_RX_BUFF3_STATUS 0x30
208 #define MAC_RX_BUFF3_ADDR 0x34
211 * Theory of operation
213 * The Au1000 MACs use a simple rx and tx descriptor ring scheme.
214 * There are four receive and four transmit descriptors. These
215 * descriptors are not in memory; rather, they are just a set of
216 * hardware registers.
218 * Since the Au1000 has a coherent data cache, the receive and
219 * transmit buffers are allocated from the KSEG0 segment. The
220 * hardware registers, however, are still mapped at KSEG1 to
221 * make sure there's no out-of-order writes, and that all writes
222 * complete immediately.
226 * board-specific configurations
228 * PHY detection algorithm
230 * If phy_static_config is undefined, the PHY setup is
233 * mii_probe() first searches the current MAC's MII bus for a PHY,
234 * selecting the first (or last, if phy_search_highest_addr is
235 * defined) PHY address not already claimed by another netdev.
237 * If nothing was found that way when searching for the 2nd ethernet
238 * controller's PHY and phy1_search_mac0 is defined, then
239 * the first MII bus is searched as well for an unclaimed PHY; this is
240 * needed in case of a dual-PHY accessible only through the MAC0's MII
243 * Finally, if no PHY is found, then the corresponding ethernet
244 * controller is not registered to the network subsystem.
247 /* autodetection defaults: phy1_search_mac0 */
251 * most boards PHY setup should be detectable properly with the
252 * autodetection algorithm in mii_probe(), but in some cases (e.g. if
253 * you have a switch attached, or want to use the PHY's interrupt
254 * notification capabilities) you can provide a static PHY
257 * IRQs may only be set, if a PHY address was configured
258 * If a PHY address is given, also a bus id is required to be set
260 * ps: make sure the used irqs are configured properly in the board
264 static void au1000_enable_mac(struct net_device *dev, int force_reset)
267 struct au1000_private *aup = netdev_priv(dev);
269 spin_lock_irqsave(&aup->lock, flags);
271 if (force_reset || (!aup->mac_enabled)) {
272 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
273 wmb(); /* drain writebuffer */
275 writel((MAC_EN_RESET0 | MAC_EN_RESET1 | MAC_EN_RESET2
276 | MAC_EN_CLOCK_ENABLE), aup->enable);
277 wmb(); /* drain writebuffer */
280 aup->mac_enabled = 1;
283 spin_unlock_irqrestore(&aup->lock, flags);
289 static int au1000_mdio_read(struct net_device *dev, int phy_addr, int reg)
291 struct au1000_private *aup = netdev_priv(dev);
292 u32 *const mii_control_reg = &aup->mac->mii_control;
293 u32 *const mii_data_reg = &aup->mac->mii_data;
297 while (readl(mii_control_reg) & MAC_MII_BUSY) {
299 if (--timedout == 0) {
300 netdev_err(dev, "read_MII busy timeout!!\n");
305 mii_control = MAC_SET_MII_SELECT_REG(reg) |
306 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_READ;
308 writel(mii_control, mii_control_reg);
311 while (readl(mii_control_reg) & MAC_MII_BUSY) {
313 if (--timedout == 0) {
314 netdev_err(dev, "mdio_read busy timeout!!\n");
318 return readl(mii_data_reg);
321 static void au1000_mdio_write(struct net_device *dev, int phy_addr,
324 struct au1000_private *aup = netdev_priv(dev);
325 u32 *const mii_control_reg = &aup->mac->mii_control;
326 u32 *const mii_data_reg = &aup->mac->mii_data;
330 while (readl(mii_control_reg) & MAC_MII_BUSY) {
332 if (--timedout == 0) {
333 netdev_err(dev, "mdio_write busy timeout!!\n");
338 mii_control = MAC_SET_MII_SELECT_REG(reg) |
339 MAC_SET_MII_SELECT_PHY(phy_addr) | MAC_MII_WRITE;
341 writel(value, mii_data_reg);
342 writel(mii_control, mii_control_reg);
345 static int au1000_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
347 /* WARNING: bus->phy_map[phy_addr].attached_dev == dev does
348 * _NOT_ hold (e.g. when PHY is accessed through other MAC's MII bus)
350 struct net_device *const dev = bus->priv;
352 /* make sure the MAC associated with this
355 au1000_enable_mac(dev, 0);
357 return au1000_mdio_read(dev, phy_addr, regnum);
360 static int au1000_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
363 struct net_device *const dev = bus->priv;
365 /* make sure the MAC associated with this
368 au1000_enable_mac(dev, 0);
370 au1000_mdio_write(dev, phy_addr, regnum, value);
374 static int au1000_mdiobus_reset(struct mii_bus *bus)
376 struct net_device *const dev = bus->priv;
378 /* make sure the MAC associated with this
381 au1000_enable_mac(dev, 0);
386 static void au1000_hard_stop(struct net_device *dev)
388 struct au1000_private *aup = netdev_priv(dev);
391 netif_dbg(aup, drv, dev, "hard stop\n");
393 reg = readl(&aup->mac->control);
394 reg &= ~(MAC_RX_ENABLE | MAC_TX_ENABLE);
395 writel(reg, &aup->mac->control);
396 wmb(); /* drain writebuffer */
400 static void au1000_enable_rx_tx(struct net_device *dev)
402 struct au1000_private *aup = netdev_priv(dev);
405 netif_dbg(aup, hw, dev, "enable_rx_tx\n");
407 reg = readl(&aup->mac->control);
408 reg |= (MAC_RX_ENABLE | MAC_TX_ENABLE);
409 writel(reg, &aup->mac->control);
410 wmb(); /* drain writebuffer */
415 au1000_adjust_link(struct net_device *dev)
417 struct au1000_private *aup = netdev_priv(dev);
418 struct phy_device *phydev = aup->phy_dev;
422 int status_change = 0;
424 BUG_ON(!aup->phy_dev);
426 spin_lock_irqsave(&aup->lock, flags);
428 if (phydev->link && (aup->old_speed != phydev->speed)) {
431 switch (phydev->speed) {
436 netdev_warn(dev, "Speed (%d) is not 10/100 ???\n",
441 aup->old_speed = phydev->speed;
446 if (phydev->link && (aup->old_duplex != phydev->duplex)) {
447 /* duplex mode changed */
449 /* switching duplex mode requires to disable rx and tx! */
450 au1000_hard_stop(dev);
452 reg = readl(&aup->mac->control);
453 if (DUPLEX_FULL == phydev->duplex) {
454 reg |= MAC_FULL_DUPLEX;
455 reg &= ~MAC_DISABLE_RX_OWN;
457 reg &= ~MAC_FULL_DUPLEX;
458 reg |= MAC_DISABLE_RX_OWN;
460 writel(reg, &aup->mac->control);
461 wmb(); /* drain writebuffer */
464 au1000_enable_rx_tx(dev);
465 aup->old_duplex = phydev->duplex;
470 if (phydev->link != aup->old_link) {
471 /* link state changed */
476 aup->old_duplex = -1;
479 aup->old_link = phydev->link;
483 spin_unlock_irqrestore(&aup->lock, flags);
487 netdev_info(dev, "link up (%d/%s)\n",
489 DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
491 netdev_info(dev, "link down\n");
495 static int au1000_mii_probe(struct net_device *dev)
497 struct au1000_private *const aup = netdev_priv(dev);
498 struct phy_device *phydev = NULL;
501 if (aup->phy_static_config) {
502 BUG_ON(aup->mac_id < 0 || aup->mac_id > 1);
505 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
507 netdev_info(dev, "using PHY-less setup\n");
511 /* find the first (lowest address) PHY
512 * on the current MAC's MII bus
514 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
515 if (mdiobus_get_phy(aup->mii_bus, aup->phy_addr)) {
516 phydev = mdiobus_get_phy(aup->mii_bus, aup->phy_addr);
517 if (!aup->phy_search_highest_addr)
518 /* break out with first one found */
522 if (aup->phy1_search_mac0) {
523 /* try harder to find a PHY */
524 if (!phydev && (aup->mac_id == 1)) {
525 /* no PHY found, maybe we have a dual PHY? */
526 dev_info(&dev->dev, ": no PHY found on MAC1, "
527 "let's see if it's attached to MAC0...\n");
529 /* find the first (lowest address) non-attached
530 * PHY on the MAC0 MII bus
532 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
533 struct phy_device *const tmp_phydev =
534 mdiobus_get_phy(aup->mii_bus,
537 if (aup->mac_id == 1)
544 /* already claimed by MAC0 */
545 if (tmp_phydev->attached_dev)
549 break; /* found it */
555 netdev_err(dev, "no PHY found\n");
559 /* now we are supposed to have a proper phydev, to attach to... */
560 BUG_ON(phydev->attached_dev);
562 phydev = phy_connect(dev, phydev_name(phydev),
563 &au1000_adjust_link, PHY_INTERFACE_MODE_MII);
565 if (IS_ERR(phydev)) {
566 netdev_err(dev, "Could not attach to PHY\n");
567 return PTR_ERR(phydev);
570 /* mask with MAC supported features */
571 phydev->supported &= (SUPPORTED_10baseT_Half
572 | SUPPORTED_10baseT_Full
573 | SUPPORTED_100baseT_Half
574 | SUPPORTED_100baseT_Full
576 /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
580 phydev->advertising = phydev->supported;
584 aup->old_duplex = -1;
585 aup->phy_dev = phydev;
587 phy_attached_info(phydev);
594 * Buffer allocation/deallocation routines. The buffer descriptor returned
595 * has the virtual and dma address of a buffer suitable for
596 * both, receive and transmit operations.
598 static struct db_dest *au1000_GetFreeDB(struct au1000_private *aup)
604 aup->pDBfree = pDB->pnext;
609 void au1000_ReleaseDB(struct au1000_private *aup, struct db_dest *pDB)
611 struct db_dest *pDBfree = aup->pDBfree;
613 pDBfree->pnext = pDB;
617 static void au1000_reset_mac_unlocked(struct net_device *dev)
619 struct au1000_private *const aup = netdev_priv(dev);
622 au1000_hard_stop(dev);
624 writel(MAC_EN_CLOCK_ENABLE, aup->enable);
625 wmb(); /* drain writebuffer */
627 writel(0, aup->enable);
628 wmb(); /* drain writebuffer */
632 for (i = 0; i < NUM_RX_DMA; i++) {
633 /* reset control bits */
634 aup->rx_dma_ring[i]->buff_stat &= ~0xf;
636 for (i = 0; i < NUM_TX_DMA; i++) {
637 /* reset control bits */
638 aup->tx_dma_ring[i]->buff_stat &= ~0xf;
641 aup->mac_enabled = 0;
645 static void au1000_reset_mac(struct net_device *dev)
647 struct au1000_private *const aup = netdev_priv(dev);
650 netif_dbg(aup, hw, dev, "reset mac, aup %x\n",
653 spin_lock_irqsave(&aup->lock, flags);
655 au1000_reset_mac_unlocked(dev);
657 spin_unlock_irqrestore(&aup->lock, flags);
661 * Setup the receive and transmit "rings". These pointers are the addresses
662 * of the rx and tx MAC DMA registers so they are fixed by the hardware --
663 * these are not descriptors sitting in memory.
666 au1000_setup_hw_rings(struct au1000_private *aup, void __iomem *tx_base)
670 for (i = 0; i < NUM_RX_DMA; i++) {
671 aup->rx_dma_ring[i] = (struct rx_dma *)
672 (tx_base + 0x100 + sizeof(struct rx_dma) * i);
674 for (i = 0; i < NUM_TX_DMA; i++) {
675 aup->tx_dma_ring[i] = (struct tx_dma *)
676 (tx_base + sizeof(struct tx_dma) * i);
684 static int au1000_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
686 struct au1000_private *aup = netdev_priv(dev);
689 return phy_ethtool_gset(aup->phy_dev, cmd);
694 static int au1000_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
696 struct au1000_private *aup = netdev_priv(dev);
698 if (!capable(CAP_NET_ADMIN))
702 return phy_ethtool_sset(aup->phy_dev, cmd);
708 au1000_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
710 struct au1000_private *aup = netdev_priv(dev);
712 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
713 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
714 snprintf(info->bus_info, sizeof(info->bus_info), "%s %d", DRV_NAME,
718 static void au1000_set_msglevel(struct net_device *dev, u32 value)
720 struct au1000_private *aup = netdev_priv(dev);
721 aup->msg_enable = value;
724 static u32 au1000_get_msglevel(struct net_device *dev)
726 struct au1000_private *aup = netdev_priv(dev);
727 return aup->msg_enable;
730 static const struct ethtool_ops au1000_ethtool_ops = {
731 .get_settings = au1000_get_settings,
732 .set_settings = au1000_set_settings,
733 .get_drvinfo = au1000_get_drvinfo,
734 .get_link = ethtool_op_get_link,
735 .get_msglevel = au1000_get_msglevel,
736 .set_msglevel = au1000_set_msglevel,
741 * Initialize the interface.
743 * When the device powers up, the clocks are disabled and the
744 * mac is in reset state. When the interface is closed, we
745 * do the same -- reset the device and disable the clocks to
746 * conserve power. Thus, whenever au1000_init() is called,
747 * the device should already be in reset state.
749 static int au1000_init(struct net_device *dev)
751 struct au1000_private *aup = netdev_priv(dev);
756 netif_dbg(aup, hw, dev, "au1000_init\n");
758 /* bring the device out of reset */
759 au1000_enable_mac(dev, 1);
761 spin_lock_irqsave(&aup->lock, flags);
763 writel(0, &aup->mac->control);
764 aup->tx_head = (aup->tx_dma_ring[0]->buff_stat & 0xC) >> 2;
765 aup->tx_tail = aup->tx_head;
766 aup->rx_head = (aup->rx_dma_ring[0]->buff_stat & 0xC) >> 2;
768 writel(dev->dev_addr[5]<<8 | dev->dev_addr[4],
769 &aup->mac->mac_addr_high);
770 writel(dev->dev_addr[3]<<24 | dev->dev_addr[2]<<16 |
771 dev->dev_addr[1]<<8 | dev->dev_addr[0],
772 &aup->mac->mac_addr_low);
775 for (i = 0; i < NUM_RX_DMA; i++)
776 aup->rx_dma_ring[i]->buff_stat |= RX_DMA_ENABLE;
778 wmb(); /* drain writebuffer */
780 control = MAC_RX_ENABLE | MAC_TX_ENABLE;
781 #ifndef CONFIG_CPU_LITTLE_ENDIAN
782 control |= MAC_BIG_ENDIAN;
785 if (aup->phy_dev->link && (DUPLEX_FULL == aup->phy_dev->duplex))
786 control |= MAC_FULL_DUPLEX;
788 control |= MAC_DISABLE_RX_OWN;
789 } else { /* PHY-less op, assume full-duplex */
790 control |= MAC_FULL_DUPLEX;
793 writel(control, &aup->mac->control);
794 writel(0x8100, &aup->mac->vlan1_tag); /* activate vlan support */
795 wmb(); /* drain writebuffer */
797 spin_unlock_irqrestore(&aup->lock, flags);
801 static inline void au1000_update_rx_stats(struct net_device *dev, u32 status)
803 struct net_device_stats *ps = &dev->stats;
806 if (status & RX_MCAST_FRAME)
809 if (status & RX_ERROR) {
811 if (status & RX_MISSED_FRAME)
812 ps->rx_missed_errors++;
813 if (status & (RX_OVERLEN | RX_RUNT | RX_LEN_ERROR))
814 ps->rx_length_errors++;
815 if (status & RX_CRC_ERROR)
817 if (status & RX_COLL)
820 ps->rx_bytes += status & RX_FRAME_LEN_MASK;
825 * Au1000 receive routine.
827 static int au1000_rx(struct net_device *dev)
829 struct au1000_private *aup = netdev_priv(dev);
832 u32 buff_stat, status;
836 netif_dbg(aup, rx_status, dev, "au1000_rx head %d\n", aup->rx_head);
838 prxd = aup->rx_dma_ring[aup->rx_head];
839 buff_stat = prxd->buff_stat;
840 while (buff_stat & RX_T_DONE) {
841 status = prxd->status;
842 pDB = aup->rx_db_inuse[aup->rx_head];
843 au1000_update_rx_stats(dev, status);
844 if (!(status & RX_ERROR)) {
847 frmlen = (status & RX_FRAME_LEN_MASK);
848 frmlen -= 4; /* Remove FCS */
849 skb = netdev_alloc_skb(dev, frmlen + 2);
851 dev->stats.rx_dropped++;
854 skb_reserve(skb, 2); /* 16 byte IP header align */
855 skb_copy_to_linear_data(skb,
856 (unsigned char *)pDB->vaddr, frmlen);
857 skb_put(skb, frmlen);
858 skb->protocol = eth_type_trans(skb, dev);
859 netif_rx(skb); /* pass the packet to upper layers */
861 if (au1000_debug > 4) {
862 pr_err("rx_error(s):");
863 if (status & RX_MISSED_FRAME)
865 if (status & RX_WDOG_TIMER)
867 if (status & RX_RUNT)
869 if (status & RX_OVERLEN)
871 if (status & RX_COLL)
873 if (status & RX_MII_ERROR)
874 pr_cont(" mii error");
875 if (status & RX_CRC_ERROR)
876 pr_cont(" crc error");
877 if (status & RX_LEN_ERROR)
878 pr_cont(" len error");
879 if (status & RX_U_CNTRL_FRAME)
880 pr_cont(" u control frame");
884 prxd->buff_stat = (u32)(pDB->dma_addr | RX_DMA_ENABLE);
885 aup->rx_head = (aup->rx_head + 1) & (NUM_RX_DMA - 1);
886 wmb(); /* drain writebuffer */
888 /* next descriptor */
889 prxd = aup->rx_dma_ring[aup->rx_head];
890 buff_stat = prxd->buff_stat;
895 static void au1000_update_tx_stats(struct net_device *dev, u32 status)
897 struct au1000_private *aup = netdev_priv(dev);
898 struct net_device_stats *ps = &dev->stats;
900 if (status & TX_FRAME_ABORTED) {
901 if (!aup->phy_dev || (DUPLEX_FULL == aup->phy_dev->duplex)) {
902 if (status & (TX_JAB_TIMEOUT | TX_UNDERRUN)) {
903 /* any other tx errors are only valid
904 * in half duplex mode
907 ps->tx_aborted_errors++;
911 ps->tx_aborted_errors++;
912 if (status & (TX_NO_CARRIER | TX_LOSS_CARRIER))
913 ps->tx_carrier_errors++;
919 * Called from the interrupt service routine to acknowledge
920 * the TX DONE bits. This is a must if the irq is setup as
923 static void au1000_tx_ack(struct net_device *dev)
925 struct au1000_private *aup = netdev_priv(dev);
928 ptxd = aup->tx_dma_ring[aup->tx_tail];
930 while (ptxd->buff_stat & TX_T_DONE) {
931 au1000_update_tx_stats(dev, ptxd->status);
932 ptxd->buff_stat &= ~TX_T_DONE;
934 wmb(); /* drain writebuffer */
936 aup->tx_tail = (aup->tx_tail + 1) & (NUM_TX_DMA - 1);
937 ptxd = aup->tx_dma_ring[aup->tx_tail];
941 netif_wake_queue(dev);
947 * Au1000 interrupt service routine.
949 static irqreturn_t au1000_interrupt(int irq, void *dev_id)
951 struct net_device *dev = dev_id;
953 /* Handle RX interrupts first to minimize chance of overrun */
957 return IRQ_RETVAL(1);
960 static int au1000_open(struct net_device *dev)
963 struct au1000_private *aup = netdev_priv(dev);
965 netif_dbg(aup, drv, dev, "open: dev=%p\n", dev);
967 retval = request_irq(dev->irq, au1000_interrupt, 0,
970 netdev_err(dev, "unable to get IRQ %d\n", dev->irq);
974 retval = au1000_init(dev);
976 netdev_err(dev, "error in au1000_init\n");
977 free_irq(dev->irq, dev);
982 /* cause the PHY state machine to schedule a link state check */
983 aup->phy_dev->state = PHY_CHANGELINK;
984 phy_start(aup->phy_dev);
987 netif_start_queue(dev);
989 netif_dbg(aup, drv, dev, "open: Initialization done.\n");
994 static int au1000_close(struct net_device *dev)
997 struct au1000_private *const aup = netdev_priv(dev);
999 netif_dbg(aup, drv, dev, "close: dev=%p\n", dev);
1002 phy_stop(aup->phy_dev);
1004 spin_lock_irqsave(&aup->lock, flags);
1006 au1000_reset_mac_unlocked(dev);
1008 /* stop the device */
1009 netif_stop_queue(dev);
1011 /* disable the interrupt */
1012 free_irq(dev->irq, dev);
1013 spin_unlock_irqrestore(&aup->lock, flags);
1019 * Au1000 transmit routine.
1021 static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev)
1023 struct au1000_private *aup = netdev_priv(dev);
1024 struct net_device_stats *ps = &dev->stats;
1025 struct tx_dma *ptxd;
1027 struct db_dest *pDB;
1030 netif_dbg(aup, tx_queued, dev, "tx: aup %x len=%d, data=%p, head %d\n",
1031 (unsigned)aup, skb->len,
1032 skb->data, aup->tx_head);
1034 ptxd = aup->tx_dma_ring[aup->tx_head];
1035 buff_stat = ptxd->buff_stat;
1036 if (buff_stat & TX_DMA_ENABLE) {
1037 /* We've wrapped around and the transmitter is still busy */
1038 netif_stop_queue(dev);
1040 return NETDEV_TX_BUSY;
1041 } else if (buff_stat & TX_T_DONE) {
1042 au1000_update_tx_stats(dev, ptxd->status);
1048 netif_wake_queue(dev);
1051 pDB = aup->tx_db_inuse[aup->tx_head];
1052 skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len);
1053 if (skb->len < ETH_ZLEN) {
1054 for (i = skb->len; i < ETH_ZLEN; i++)
1055 ((char *)pDB->vaddr)[i] = 0;
1057 ptxd->len = ETH_ZLEN;
1059 ptxd->len = skb->len;
1062 ps->tx_bytes += ptxd->len;
1064 ptxd->buff_stat = pDB->dma_addr | TX_DMA_ENABLE;
1065 wmb(); /* drain writebuffer */
1067 aup->tx_head = (aup->tx_head + 1) & (NUM_TX_DMA - 1);
1068 return NETDEV_TX_OK;
1072 * The Tx ring has been full longer than the watchdog timeout
1073 * value. The transmitter must be hung?
1075 static void au1000_tx_timeout(struct net_device *dev)
1077 netdev_err(dev, "au1000_tx_timeout: dev=%p\n", dev);
1078 au1000_reset_mac(dev);
1080 dev->trans_start = jiffies; /* prevent tx timeout */
1081 netif_wake_queue(dev);
1084 static void au1000_multicast_list(struct net_device *dev)
1086 struct au1000_private *aup = netdev_priv(dev);
1089 netif_dbg(aup, drv, dev, "%s: flags=%x\n", __func__, dev->flags);
1090 reg = readl(&aup->mac->control);
1091 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1092 reg |= MAC_PROMISCUOUS;
1093 } else if ((dev->flags & IFF_ALLMULTI) ||
1094 netdev_mc_count(dev) > MULTICAST_FILTER_LIMIT) {
1095 reg |= MAC_PASS_ALL_MULTI;
1096 reg &= ~MAC_PROMISCUOUS;
1097 netdev_info(dev, "Pass all multicast\n");
1099 struct netdev_hw_addr *ha;
1100 u32 mc_filter[2]; /* Multicast hash filter */
1102 mc_filter[1] = mc_filter[0] = 0;
1103 netdev_for_each_mc_addr(ha, dev)
1104 set_bit(ether_crc(ETH_ALEN, ha->addr)>>26,
1106 writel(mc_filter[1], &aup->mac->multi_hash_high);
1107 writel(mc_filter[0], &aup->mac->multi_hash_low);
1108 reg &= ~MAC_PROMISCUOUS;
1109 reg |= MAC_HASH_MODE;
1111 writel(reg, &aup->mac->control);
1114 static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1116 struct au1000_private *aup = netdev_priv(dev);
1118 if (!netif_running(dev))
1122 return -EINVAL; /* PHY not controllable */
1124 return phy_mii_ioctl(aup->phy_dev, rq, cmd);
1127 static const struct net_device_ops au1000_netdev_ops = {
1128 .ndo_open = au1000_open,
1129 .ndo_stop = au1000_close,
1130 .ndo_start_xmit = au1000_tx,
1131 .ndo_set_rx_mode = au1000_multicast_list,
1132 .ndo_do_ioctl = au1000_ioctl,
1133 .ndo_tx_timeout = au1000_tx_timeout,
1134 .ndo_set_mac_address = eth_mac_addr,
1135 .ndo_validate_addr = eth_validate_addr,
1136 .ndo_change_mtu = eth_change_mtu,
1139 static int au1000_probe(struct platform_device *pdev)
1141 struct au1000_private *aup = NULL;
1142 struct au1000_eth_platform_data *pd;
1143 struct net_device *dev = NULL;
1144 struct db_dest *pDB, *pDBfree;
1145 int irq, i, err = 0;
1146 struct resource *base, *macen, *macdma;
1148 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1150 dev_err(&pdev->dev, "failed to retrieve base register\n");
1155 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1157 dev_err(&pdev->dev, "failed to retrieve MAC Enable register\n");
1162 irq = platform_get_irq(pdev, 0);
1164 dev_err(&pdev->dev, "failed to retrieve IRQ\n");
1169 macdma = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1171 dev_err(&pdev->dev, "failed to retrieve MACDMA registers\n");
1176 if (!request_mem_region(base->start, resource_size(base),
1178 dev_err(&pdev->dev, "failed to request memory region for base registers\n");
1183 if (!request_mem_region(macen->start, resource_size(macen),
1185 dev_err(&pdev->dev, "failed to request memory region for MAC enable register\n");
1190 if (!request_mem_region(macdma->start, resource_size(macdma),
1192 dev_err(&pdev->dev, "failed to request MACDMA memory region\n");
1197 dev = alloc_etherdev(sizeof(struct au1000_private));
1203 SET_NETDEV_DEV(dev, &pdev->dev);
1204 platform_set_drvdata(pdev, dev);
1205 aup = netdev_priv(dev);
1207 spin_lock_init(&aup->lock);
1208 aup->msg_enable = (au1000_debug < 4 ?
1209 AU1000_DEF_MSG_ENABLE : au1000_debug);
1211 /* Allocate the data buffers
1212 * Snooping works fine with eth on all au1xxx
1214 aup->vaddr = (u32)dma_alloc_noncoherent(NULL, MAX_BUF_SIZE *
1215 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1218 dev_err(&pdev->dev, "failed to allocate data buffers\n");
1223 /* aup->mac is the base address of the MAC's registers */
1224 aup->mac = (struct mac_reg *)
1225 ioremap_nocache(base->start, resource_size(base));
1227 dev_err(&pdev->dev, "failed to ioremap MAC registers\n");
1232 /* Setup some variables for quick register address access */
1233 aup->enable = (u32 *)ioremap_nocache(macen->start,
1234 resource_size(macen));
1236 dev_err(&pdev->dev, "failed to ioremap MAC enable register\n");
1240 aup->mac_id = pdev->id;
1242 aup->macdma = ioremap_nocache(macdma->start, resource_size(macdma));
1244 dev_err(&pdev->dev, "failed to ioremap MACDMA registers\n");
1249 au1000_setup_hw_rings(aup, aup->macdma);
1251 writel(0, aup->enable);
1252 aup->mac_enabled = 0;
1254 pd = dev_get_platdata(&pdev->dev);
1256 dev_info(&pdev->dev, "no platform_data passed,"
1257 " PHY search on MAC0\n");
1258 aup->phy1_search_mac0 = 1;
1260 if (is_valid_ether_addr(pd->mac)) {
1261 memcpy(dev->dev_addr, pd->mac, ETH_ALEN);
1263 /* Set a random MAC since no valid provided by platform_data. */
1264 eth_hw_addr_random(dev);
1267 aup->phy_static_config = pd->phy_static_config;
1268 aup->phy_search_highest_addr = pd->phy_search_highest_addr;
1269 aup->phy1_search_mac0 = pd->phy1_search_mac0;
1270 aup->phy_addr = pd->phy_addr;
1271 aup->phy_busid = pd->phy_busid;
1272 aup->phy_irq = pd->phy_irq;
1275 if (aup->phy_busid && aup->phy_busid > 0) {
1276 dev_err(&pdev->dev, "MAC0-associated PHY attached 2nd MACs MII bus not supported yet\n");
1278 goto err_mdiobus_alloc;
1281 aup->mii_bus = mdiobus_alloc();
1282 if (aup->mii_bus == NULL) {
1283 dev_err(&pdev->dev, "failed to allocate mdiobus structure\n");
1285 goto err_mdiobus_alloc;
1288 aup->mii_bus->priv = dev;
1289 aup->mii_bus->read = au1000_mdiobus_read;
1290 aup->mii_bus->write = au1000_mdiobus_write;
1291 aup->mii_bus->reset = au1000_mdiobus_reset;
1292 aup->mii_bus->name = "au1000_eth_mii";
1293 snprintf(aup->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1294 pdev->name, aup->mac_id);
1296 /* if known, set corresponding PHY IRQs */
1297 if (aup->phy_static_config)
1298 if (aup->phy_irq && aup->phy_busid == aup->mac_id)
1299 aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq;
1301 err = mdiobus_register(aup->mii_bus);
1303 dev_err(&pdev->dev, "failed to register MDIO bus\n");
1304 goto err_mdiobus_reg;
1307 err = au1000_mii_probe(dev);
1312 /* setup the data buffer descriptors and attach a buffer to each one */
1314 for (i = 0; i < (NUM_TX_BUFFS+NUM_RX_BUFFS); i++) {
1315 pDB->pnext = pDBfree;
1317 pDB->vaddr = (u32 *)((unsigned)aup->vaddr + MAX_BUF_SIZE*i);
1318 pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr);
1321 aup->pDBfree = pDBfree;
1324 for (i = 0; i < NUM_RX_DMA; i++) {
1325 pDB = au1000_GetFreeDB(aup);
1329 aup->rx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1330 aup->rx_db_inuse[i] = pDB;
1334 for (i = 0; i < NUM_TX_DMA; i++) {
1335 pDB = au1000_GetFreeDB(aup);
1339 aup->tx_dma_ring[i]->buff_stat = (unsigned)pDB->dma_addr;
1340 aup->tx_dma_ring[i]->len = 0;
1341 aup->tx_db_inuse[i] = pDB;
1344 dev->base_addr = base->start;
1346 dev->netdev_ops = &au1000_netdev_ops;
1347 dev->ethtool_ops = &au1000_ethtool_ops;
1348 dev->watchdog_timeo = ETH_TX_TIMEOUT;
1351 * The boot code uses the ethernet controller, so reset it to start
1352 * fresh. au1000_init() expects that the device is in reset state.
1354 au1000_reset_mac(dev);
1356 err = register_netdev(dev);
1358 netdev_err(dev, "Cannot register net device, aborting.\n");
1362 netdev_info(dev, "Au1xx0 Ethernet found at 0x%lx, irq %d\n",
1363 (unsigned long)base->start, irq);
1365 pr_info_once("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR);
1370 if (aup->mii_bus != NULL)
1371 mdiobus_unregister(aup->mii_bus);
1373 /* here we should have a valid dev plus aup-> register addresses
1374 * so we can reset the mac properly.
1376 au1000_reset_mac(dev);
1378 for (i = 0; i < NUM_RX_DMA; i++) {
1379 if (aup->rx_db_inuse[i])
1380 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1382 for (i = 0; i < NUM_TX_DMA; i++) {
1383 if (aup->tx_db_inuse[i])
1384 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1387 mdiobus_free(aup->mii_bus);
1389 iounmap(aup->macdma);
1391 iounmap(aup->enable);
1395 dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS),
1396 (void *)aup->vaddr, aup->dma_addr);
1400 release_mem_region(macdma->start, resource_size(macdma));
1402 release_mem_region(macen->start, resource_size(macen));
1404 release_mem_region(base->start, resource_size(base));
1409 static int au1000_remove(struct platform_device *pdev)
1411 struct net_device *dev = platform_get_drvdata(pdev);
1412 struct au1000_private *aup = netdev_priv(dev);
1414 struct resource *base, *macen;
1416 unregister_netdev(dev);
1417 mdiobus_unregister(aup->mii_bus);
1418 mdiobus_free(aup->mii_bus);
1420 for (i = 0; i < NUM_RX_DMA; i++)
1421 if (aup->rx_db_inuse[i])
1422 au1000_ReleaseDB(aup, aup->rx_db_inuse[i]);
1424 for (i = 0; i < NUM_TX_DMA; i++)
1425 if (aup->tx_db_inuse[i])
1426 au1000_ReleaseDB(aup, aup->tx_db_inuse[i]);
1428 dma_free_noncoherent(NULL, MAX_BUF_SIZE *
1429 (NUM_TX_BUFFS + NUM_RX_BUFFS),
1430 (void *)aup->vaddr, aup->dma_addr);
1432 iounmap(aup->macdma);
1434 iounmap(aup->enable);
1436 base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1437 release_mem_region(base->start, resource_size(base));
1439 base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1440 release_mem_region(base->start, resource_size(base));
1442 macen = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1443 release_mem_region(macen->start, resource_size(macen));
1450 static struct platform_driver au1000_eth_driver = {
1451 .probe = au1000_probe,
1452 .remove = au1000_remove,
1454 .name = "au1000-eth",
1458 module_platform_driver(au1000_eth_driver);
1460 MODULE_ALIAS("platform:au1000-eth");