1 /* Applied Micro X-Gene SoC Ethernet Classifier structures
3 * Copyright (c) 2016, Applied Micro Circuits Corporation
4 * Authors: Khuong Dinh <kdinh@apm.com>
5 * Tanmay Inamdar <tinamdar@apm.com>
6 * Iyappan Subramanian <isubramanian@apm.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "xgene_enet_main.h"
24 /* interfaces to convert structures to HW recognized bit formats */
25 static void xgene_cle_sband_to_hw(u8 frag, enum xgene_cle_prot_version ver,
26 enum xgene_cle_prot_type type, u32 len,
29 *reg = SET_VAL(SB_IPFRAG, frag) |
30 SET_VAL(SB_IPPROT, type) |
31 SET_VAL(SB_IPVER, ver) |
32 SET_VAL(SB_HDRLEN, len);
35 static void xgene_cle_idt_to_hw(u32 dstqid, u32 fpsel,
36 u32 nfpsel, u32 *idt_reg)
38 *idt_reg = SET_VAL(IDT_DSTQID, dstqid) |
39 SET_VAL(IDT_FPSEL, fpsel) |
40 SET_VAL(IDT_NFPSEL, nfpsel);
43 static void xgene_cle_dbptr_to_hw(struct xgene_enet_pdata *pdata,
44 struct xgene_cle_dbptr *dbptr, u32 *buf)
46 buf[0] = SET_VAL(CLE_DROP, dbptr->drop);
47 buf[4] = SET_VAL(CLE_FPSEL, dbptr->fpsel) |
48 SET_VAL(CLE_DSTQIDL, dbptr->dstqid);
50 buf[5] = SET_VAL(CLE_DSTQIDH, (u32)dbptr->dstqid >> CLE_DSTQIDL_LEN) |
51 SET_VAL(CLE_PRIORITY, dbptr->cle_priority);
54 static void xgene_cle_kn_to_hw(struct xgene_cle_ptree_kn *kn, u32 *buf)
59 buf[j++] = SET_VAL(CLE_TYPE, kn->node_type);
60 for (i = 0; i < kn->num_keys; i++) {
61 struct xgene_cle_ptree_key *key = &kn->key[i];
64 buf[j] = SET_VAL(CLE_KN_PRIO, key->priority) |
65 SET_VAL(CLE_KN_RPTR, key->result_pointer);
67 data = SET_VAL(CLE_KN_PRIO, key->priority) |
68 SET_VAL(CLE_KN_RPTR, key->result_pointer);
69 buf[j++] |= (data << 16);
74 static void xgene_cle_dn_to_hw(struct xgene_cle_ptree_ewdn *dn,
77 struct xgene_cle_ptree_branch *br;
81 buf[j++] = SET_VAL(CLE_DN_TYPE, dn->node_type) |
82 SET_VAL(CLE_DN_LASTN, dn->last_node) |
83 SET_VAL(CLE_DN_HLS, dn->hdr_len_store) |
84 SET_VAL(CLE_DN_EXT, dn->hdr_extn) |
85 SET_VAL(CLE_DN_BSTOR, dn->byte_store) |
86 SET_VAL(CLE_DN_SBSTOR, dn->search_byte_store) |
87 SET_VAL(CLE_DN_RPTR, dn->result_pointer);
89 for (i = 0; i < dn->num_branches; i++) {
91 npp = br->next_packet_pointer;
93 if ((br->jump_rel == JMP_ABS) && (npp < CLE_PKTRAM_SIZE))
96 buf[j++] = SET_VAL(CLE_BR_VALID, br->valid) |
97 SET_VAL(CLE_BR_NPPTR, npp) |
98 SET_VAL(CLE_BR_JB, br->jump_bw) |
99 SET_VAL(CLE_BR_JR, br->jump_rel) |
100 SET_VAL(CLE_BR_OP, br->operation) |
101 SET_VAL(CLE_BR_NNODE, br->next_node) |
102 SET_VAL(CLE_BR_NBR, br->next_branch);
104 buf[j++] = SET_VAL(CLE_BR_DATA, br->data) |
105 SET_VAL(CLE_BR_MASK, br->mask);
109 static int xgene_cle_poll_cmd_done(void __iomem *base,
110 enum xgene_cle_cmd_type cmd)
112 u32 status, loop = 10;
116 status = ioread32(base + INDCMD_STATUS);
121 usleep_range(1000, 2000);
127 static int xgene_cle_dram_wr(struct xgene_enet_cle *cle, u32 *data, u8 nregs,
128 u32 index, enum xgene_cle_dram_type type,
129 enum xgene_cle_cmd_type cmd)
131 enum xgene_cle_parser parser = cle->active_parser;
132 void __iomem *base = cle->base;
137 /* PTREE_RAM onwards, DRAM regions are common for all parsers */
138 nparsers = (type >= PTREE_RAM) ? 1 : cle->parsers;
140 for (i = 0; i < nparsers; i++) {
142 if ((type < PTREE_RAM) && (parser != PARSER_ALL))
145 ind_addr = XGENE_CLE_DRAM(type + (port * 4)) | index;
146 iowrite32(ind_addr, base + INDADDR);
147 for (j = 0; j < nregs; j++)
148 iowrite32(data[j], base + DATA_RAM0 + (j * 4));
149 iowrite32(cmd, base + INDCMD);
151 ret = xgene_cle_poll_cmd_done(base, cmd);
159 static void xgene_cle_enable_ptree(struct xgene_enet_pdata *pdata,
160 struct xgene_enet_cle *cle)
162 struct xgene_cle_ptree *ptree = &cle->ptree;
163 void __iomem *addr, *base = cle->base;
164 u32 offset = CLE_PORT_OFFSET;
167 /* 1G port has to advance 4 bytes and 10G has to advance 8 bytes */
168 ptree->start_pkt += cle->jump_bytes;
169 for (i = 0; i < cle->parsers; i++) {
170 if (cle->active_parser != PARSER_ALL)
171 addr = base + cle->active_parser * offset;
173 addr = base + (i * offset);
175 iowrite32(ptree->start_node & 0x3fff, addr + SNPTR0);
176 iowrite32(ptree->start_pkt & 0x1ff, addr + SPPTR0);
180 static int xgene_cle_setup_dbptr(struct xgene_enet_pdata *pdata,
181 struct xgene_enet_cle *cle)
183 struct xgene_cle_ptree *ptree = &cle->ptree;
184 u32 buf[CLE_DRAM_REGS];
188 memset(buf, 0, sizeof(buf));
189 for (i = 0; i < ptree->num_dbptr; i++) {
190 xgene_cle_dbptr_to_hw(pdata, &ptree->dbptr[i], buf);
191 ret = xgene_cle_dram_wr(cle, buf, 6, i + ptree->start_dbptr,
200 static int xgene_cle_setup_node(struct xgene_enet_pdata *pdata,
201 struct xgene_enet_cle *cle)
203 struct xgene_cle_ptree *ptree = &cle->ptree;
204 struct xgene_cle_ptree_ewdn *dn = ptree->dn;
205 struct xgene_cle_ptree_kn *kn = ptree->kn;
206 u32 buf[CLE_DRAM_REGS];
209 memset(buf, 0, sizeof(buf));
210 for (i = 0; i < ptree->num_dn; i++) {
211 xgene_cle_dn_to_hw(&dn[i], buf, cle->jump_bytes);
212 ret = xgene_cle_dram_wr(cle, buf, 17, i + ptree->start_node,
213 PTREE_RAM, CLE_CMD_WR);
218 /* continue node index for key node */
219 memset(buf, 0, sizeof(buf));
220 for (j = i; j < (ptree->num_kn + ptree->num_dn); j++) {
221 xgene_cle_kn_to_hw(&kn[j - ptree->num_dn], buf);
222 ret = xgene_cle_dram_wr(cle, buf, 17, j + ptree->start_node,
223 PTREE_RAM, CLE_CMD_WR);
231 static int xgene_cle_setup_ptree(struct xgene_enet_pdata *pdata,
232 struct xgene_enet_cle *cle)
236 ret = xgene_cle_setup_node(pdata, cle);
240 ret = xgene_cle_setup_dbptr(pdata, cle);
244 xgene_cle_enable_ptree(pdata, cle);
249 static void xgene_cle_setup_def_dbptr(struct xgene_enet_pdata *pdata,
250 struct xgene_enet_cle *enet_cle,
251 struct xgene_cle_dbptr *dbptr,
252 u32 index, u8 priority)
254 void __iomem *base = enet_cle->base;
255 void __iomem *base_addr;
256 u32 buf[CLE_DRAM_REGS];
260 memset(buf, 0, sizeof(buf));
261 xgene_cle_dbptr_to_hw(pdata, dbptr, buf);
263 for (i = 0; i < enet_cle->parsers; i++) {
264 if (enet_cle->active_parser != PARSER_ALL) {
265 offset = enet_cle->active_parser *
268 offset = i * CLE_PORT_OFFSET;
271 base_addr = base + DFCLSRESDB00 + offset;
272 for (j = 0; j < 6; j++)
273 iowrite32(buf[j], base_addr + (j * 4));
275 def_cls = ((priority & 0x7) << 10) | (index & 0x3ff);
276 iowrite32(def_cls, base + DFCLSRESDBPTR0 + offset);
280 static int xgene_cle_set_rss_sband(struct xgene_enet_cle *cle)
282 u32 idx = CLE_PKTRAM_SIZE / sizeof(u32);
283 u32 mac_hdr_len = ETH_HLEN;
289 /* Sideband: IPV4/TCP packets */
290 hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
291 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_TCP, hdr_len, ®);
294 /* Sideband: IPv4/UDP packets */
295 hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
296 xgene_cle_sband_to_hw(1, XGENE_CLE_IPV4, XGENE_CLE_UDP, hdr_len, ®);
297 sband |= (reg << 16);
299 ret = xgene_cle_dram_wr(cle, &sband, 1, idx, PKT_RAM, CLE_CMD_WR);
303 /* Sideband: IPv4/RAW packets */
304 hdr_len = (mac_hdr_len << 5) | ipv4_ihl;
305 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_OTHER,
309 /* Sideband: Ethernet II/RAW packets */
310 hdr_len = (mac_hdr_len << 5);
311 xgene_cle_sband_to_hw(0, XGENE_CLE_IPV4, XGENE_CLE_OTHER,
313 sband |= (reg << 16);
315 ret = xgene_cle_dram_wr(cle, &sband, 1, idx + 1, PKT_RAM, CLE_CMD_WR);
322 static int xgene_cle_set_rss_skeys(struct xgene_enet_cle *cle)
324 u32 secret_key_ipv4[4]; /* 16 Bytes*/
327 get_random_bytes(secret_key_ipv4, 16);
328 ret = xgene_cle_dram_wr(cle, secret_key_ipv4, 4, 0,
329 RSS_IPV4_HASH_SKEY, CLE_CMD_WR);
333 static int xgene_cle_set_rss_idt(struct xgene_enet_pdata *pdata)
335 u32 fpsel, dstqid, nfpsel, idt_reg, idx;
339 for (i = 0; i < XGENE_CLE_IDT_ENTRIES; i++) {
340 idx = i % pdata->rxq_cnt;
341 pool_id = pdata->rx_ring[idx]->buf_pool->id;
342 fpsel = xgene_enet_ring_bufnum(pool_id) - 0x20;
343 dstqid = xgene_enet_dst_ring_num(pdata->rx_ring[idx]);
347 xgene_cle_idt_to_hw(dstqid, fpsel, nfpsel, &idt_reg);
348 ret = xgene_cle_dram_wr(&pdata->cle, &idt_reg, 1, i,
349 RSS_IDT, CLE_CMD_WR);
354 ret = xgene_cle_set_rss_skeys(&pdata->cle);
361 static int xgene_cle_setup_rss(struct xgene_enet_pdata *pdata)
363 struct xgene_enet_cle *cle = &pdata->cle;
364 void __iomem *base = cle->base;
368 offset = CLE_PORT_OFFSET;
369 for (i = 0; i < cle->parsers; i++) {
370 if (cle->active_parser != PARSER_ALL)
371 offset = cle->active_parser * CLE_PORT_OFFSET;
373 offset = i * CLE_PORT_OFFSET;
376 val = (RSS_IPV4_12B << 1) | 0x1;
377 writel(val, base + RSS_CTRL0 + offset);
380 /* setup sideband data */
381 ret = xgene_cle_set_rss_sband(cle);
385 /* setup indirection table */
386 ret = xgene_cle_set_rss_idt(pdata);
393 static int xgene_enet_cle_init(struct xgene_enet_pdata *pdata)
395 struct xgene_enet_cle *enet_cle = &pdata->cle;
396 struct xgene_cle_dbptr dbptr[DB_MAX_PTRS];
397 struct xgene_cle_ptree_branch *br;
398 u32 def_qid, def_fpsel, pool_id;
399 struct xgene_cle_ptree *ptree;
400 struct xgene_cle_ptree_kn kn;
402 struct xgene_cle_ptree_ewdn ptree_dn[] = {
409 .byte_store = NO_BYTE,
410 .search_byte_store = NO_BYTE,
411 .result_pointer = DB_RES_DROP,
417 .next_packet_pointer = 22,
421 .next_node = PKT_PROT_NODE,
428 .next_packet_pointer = 262,
432 .next_node = LAST_NODE,
445 .byte_store = NO_BYTE,
446 .search_byte_store = NO_BYTE,
447 .result_pointer = DB_RES_DROP,
453 .next_packet_pointer = 26,
457 .next_node = RSS_IPV4_TCP_NODE,
465 .next_packet_pointer = 26,
469 .next_node = RSS_IPV4_UDP_NODE,
476 .next_packet_pointer = 260,
480 .next_node = LAST_NODE,
488 /* RSS_IPV4_TCP_NODE */
493 .byte_store = NO_BYTE,
494 .search_byte_store = BOTH_BYTES,
495 .result_pointer = DB_RES_DROP,
501 .next_packet_pointer = 28,
505 .next_node = RSS_IPV4_TCP_NODE,
513 .next_packet_pointer = 30,
517 .next_node = RSS_IPV4_TCP_NODE,
525 .next_packet_pointer = 32,
529 .next_node = RSS_IPV4_TCP_NODE,
537 .next_packet_pointer = 34,
541 .next_node = RSS_IPV4_TCP_NODE,
549 .next_packet_pointer = 36,
553 .next_node = RSS_IPV4_TCP_NODE,
561 .next_packet_pointer = 256,
565 .next_node = LAST_NODE,
573 /* RSS_IPV4_UDP_NODE */
578 .byte_store = NO_BYTE,
579 .search_byte_store = BOTH_BYTES,
580 .result_pointer = DB_RES_DROP,
586 .next_packet_pointer = 28,
590 .next_node = RSS_IPV4_UDP_NODE,
598 .next_packet_pointer = 30,
602 .next_node = RSS_IPV4_UDP_NODE,
610 .next_packet_pointer = 32,
614 .next_node = RSS_IPV4_UDP_NODE,
622 .next_packet_pointer = 34,
626 .next_node = RSS_IPV4_UDP_NODE,
634 .next_packet_pointer = 36,
638 .next_node = RSS_IPV4_UDP_NODE,
646 .next_packet_pointer = 258,
650 .next_node = LAST_NODE,
663 .byte_store = NO_BYTE,
664 .search_byte_store = NO_BYTE,
665 .result_pointer = DB_RES_DROP,
670 .next_packet_pointer = 0,
674 .next_node = MAX_NODES,
683 ptree = &enet_cle->ptree;
684 ptree->start_pkt = 12; /* Ethertype */
685 if (pdata->phy_mode == PHY_INTERFACE_MODE_XGMII) {
686 ret = xgene_cle_setup_rss(pdata);
688 netdev_err(pdata->ndev, "RSS initialization failed\n");
692 br = &ptree_dn[PKT_PROT_NODE].branch[0];
694 br->next_packet_pointer = 260;
695 br->next_node = LAST_NODE;
700 def_qid = xgene_enet_dst_ring_num(pdata->rx_ring[0]);
701 pool_id = pdata->rx_ring[0]->buf_pool->id;
702 def_fpsel = xgene_enet_ring_bufnum(pool_id) - 0x20;
704 memset(dbptr, 0, sizeof(struct xgene_cle_dbptr) * DB_MAX_PTRS);
705 dbptr[DB_RES_ACCEPT].fpsel = def_fpsel;
706 dbptr[DB_RES_ACCEPT].dstqid = def_qid;
707 dbptr[DB_RES_ACCEPT].cle_priority = 1;
709 dbptr[DB_RES_DEF].fpsel = def_fpsel;
710 dbptr[DB_RES_DEF].dstqid = def_qid;
711 dbptr[DB_RES_DEF].cle_priority = 7;
712 xgene_cle_setup_def_dbptr(pdata, enet_cle, &dbptr[DB_RES_DEF],
715 dbptr[DB_RES_DROP].drop = 1;
717 memset(&kn, 0, sizeof(kn));
720 kn.key[0].priority = 0;
721 kn.key[0].result_pointer = DB_RES_ACCEPT;
723 ptree->dn = ptree_dn;
725 ptree->dbptr = dbptr;
726 ptree->num_dn = MAX_NODES;
728 ptree->num_dbptr = DB_MAX_PTRS;
730 return xgene_cle_setup_ptree(pdata, enet_cle);
733 const struct xgene_cle_ops xgene_cle3in_ops = {
734 .cle_init = xgene_enet_cle_init,