drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 575 {
 576         struct bcm_enet_priv *priv;
 577         struct bcm_enet_desc *desc;
 578         u32 len_stat;
 579         int ret;
 580
 581         priv = netdev_priv(dev);
 582
 583         /* lock against tx reclaim */
 584         spin_lock(&priv->tx_lock);
 585
 586         /* make sure  the tx hw queue  is not full,  should not happen
 587          * since we stop queue before it's the case */
 588         if (unlikely(!priv->tx_desc_count)) {
 589                 netif_stop_queue(dev);
 590                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 591                         "available?\n");
 592                 ret = NETDEV_TX_BUSY;
 593                 goto out_unlock;
 594         }
 595
 596         /* pad small packets sent on a switch device */
 597         if (priv->enet_is_sw && skb->len < 64) {
 598                 int needed = 64 - skb->len;
 599                 char *data;
 600
 601                 if (unlikely(skb_tailroom(skb) < needed)) {
 602                         struct sk_buff *nskb;
 603
 604                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 605                         if (!nskb) {
 606                                 ret = NETDEV_TX_BUSY;
 607                                 goto out_unlock;
 608                         }
 609                         dev_kfree_skb(skb);
 610                         skb = nskb;
 611                 }
 612                 data = skb_put(skb, needed);
 613                 memset(data, 0, needed);
 614         }
 615
 616         /* point to the next available desc */
 617         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 618         priv->tx_skb[priv->tx_curr_desc] = skb;
 619
 620         /* fill descriptor */
 621         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 622                                        DMA_TO_DEVICE);
 623
 624         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 625         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 626                 DMADESC_APPEND_CRC |
 627                 DMADESC_OWNER_MASK;
 628
 629         priv->tx_curr_desc++;
 630         if (priv->tx_curr_desc == priv->tx_ring_size) {
 631                 priv->tx_curr_desc = 0;
 632                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 633         }
 634         priv->tx_desc_count--;
 635
 636         /* dma might be already polling, make sure we update desc
 637          * fields in correct order */
 638         wmb();
 639         desc->len_stat = len_stat;
 640         wmb();
 641
 642         /* kick tx dma */
 643         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 644                                  ENETDMAC_CHANCFG, priv->tx_chan);
 645
 646         /* stop queue if no more desc available */
 647         if (!priv->tx_desc_count)
 648                 netif_stop_queue(dev);
 649
 650         dev->stats.tx_bytes += skb->len;
 651         dev->stats.tx_packets++;
 652         ret = NETDEV_TX_OK;
 653
 654 out_unlock:
 655         spin_unlock(&priv->tx_lock);
 656         return ret;
 657 }
 658
 659 /*
 660  * Change the interface's mac address.
 661  */
 662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 663 {
 664         struct bcm_enet_priv *priv;
 665         struct sockaddr *addr = p;
 666         u32 val;
 667
 668         priv = netdev_priv(dev);
 669         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 670
 671         /* use perfect match register 0 to store my mac address */
 672         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 673                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 674         enet_writel(priv, val, ENET_PML_REG(0));
 675
 676         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 677         val |= ENET_PMH_DATAVALID_MASK;
 678         enet_writel(priv, val, ENET_PMH_REG(0));
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * Change rx mode (promiscuous/allmulti) and update multicast list
 685  */
 686 static void bcm_enet_set_multicast_list(struct net_device *dev)
 687 {
 688         struct bcm_enet_priv *priv;
 689         struct netdev_hw_addr *ha;
 690         u32 val;
 691         int i;
 692
 693         priv = netdev_priv(dev);
 694
 695         val = enet_readl(priv, ENET_RXCFG_REG);
 696
 697         if (dev->flags & IFF_PROMISC)
 698                 val |= ENET_RXCFG_PROMISC_MASK;
 699         else
 700                 val &= ~ENET_RXCFG_PROMISC_MASK;
 701
 702         /* only 3 perfect match registers left, first one is used for
 703          * own mac address */
 704         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 705                 val |= ENET_RXCFG_ALLMCAST_MASK;
 706         else
 707                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 708
 709         /* no need to set perfect match registers if we catch all
 710          * multicast */
 711         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 712                 enet_writel(priv, val, ENET_RXCFG_REG);
 713                 return;
 714         }
 715
 716         i = 0;
 717         netdev_for_each_mc_addr(ha, dev) {
 718                 u8 *dmi_addr;
 719                 u32 tmp;
 720
 721                 if (i == 3)
 722                         break;
 723                 /* update perfect match registers */
 724                 dmi_addr = ha->addr;
 725                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 726                         (dmi_addr[4] << 8) | dmi_addr[5];
 727                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 728
 729                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 730                 tmp |= ENET_PMH_DATAVALID_MASK;
 731                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 732         }
 733
 734         for (; i < 3; i++) {
 735                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 736                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 737         }
 738
 739         enet_writel(priv, val, ENET_RXCFG_REG);
 740 }
 741
 742 /*
 743  * set mac duplex parameters
 744  */
 745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 746 {
 747         u32 val;
 748
 749         val = enet_readl(priv, ENET_TXCTL_REG);
 750         if (fullduplex)
 751                 val |= ENET_TXCTL_FD_MASK;
 752         else
 753                 val &= ~ENET_TXCTL_FD_MASK;
 754         enet_writel(priv, val, ENET_TXCTL_REG);
 755 }
 756
 757 /*
 758  * set mac flow control parameters
 759  */
 760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 761 {
 762         u32 val;
 763
 764         /* rx flow control (pause frame handling) */
 765         val = enet_readl(priv, ENET_RXCFG_REG);
 766         if (rx_en)
 767                 val |= ENET_RXCFG_ENFLOW_MASK;
 768         else
 769                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 770         enet_writel(priv, val, ENET_RXCFG_REG);
 771
 772         if (!priv->dma_has_sram)
 773                 return;
 774
 775         /* tx flow control (pause frame generation) */
 776         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 777         if (tx_en)
 778                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 779         else
 780                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 781         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 782 }
 783
 784 /*
 785  * link changed callback (from phylib)
 786  */
 787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 788 {
 789         struct bcm_enet_priv *priv;
 790         struct phy_device *phydev;
 791         int status_changed;
 792
 793         priv = netdev_priv(dev);
 794         phydev = dev->phydev;
 795         status_changed = 0;
 796
 797         if (priv->old_link != phydev->link) {
 798                 status_changed = 1;
 799                 priv->old_link = phydev->link;
 800         }
 801
 802         /* reflect duplex change in mac configuration */
 803         if (phydev->link && phydev->duplex != priv->old_duplex) {
 804                 bcm_enet_set_duplex(priv,
 805                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 806                 status_changed = 1;
 807                 priv->old_duplex = phydev->duplex;
 808         }
 809
 810         /* enable flow control if remote advertise it (trust phylib to
 811          * check that duplex is full */
 812         if (phydev->link && phydev->pause != priv->old_pause) {
 813                 int rx_pause_en, tx_pause_en;
 814
 815                 if (phydev->pause) {
 816                         /* pause was advertised by lpa and us */
 817                         rx_pause_en = 1;
 818                         tx_pause_en = 1;
 819                 } else if (!priv->pause_auto) {
 820                         /* pause setting overrided by user */
 821                         rx_pause_en = priv->pause_rx;
 822                         tx_pause_en = priv->pause_tx;
 823                 } else {
 824                         rx_pause_en = 0;
 825                         tx_pause_en = 0;
 826                 }
 827
 828                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 829                 status_changed = 1;
 830                 priv->old_pause = phydev->pause;
 831         }
 832
 833         if (status_changed) {
 834                 pr_info("%s: link %s", dev->name, phydev->link ?
 835                         "UP" : "DOWN");
 836                 if (phydev->link)
 837                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 838                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 839                                phydev->pause == 1 ? "rx&tx" : "off");
 840
 841                 pr_cont("\n");
 842         }
 843 }
 844
 845 /*
 846  * link changed callback (if phylib is not used)
 847  */
 848 static void bcm_enet_adjust_link(struct net_device *dev)
 849 {
 850         struct bcm_enet_priv *priv;
 851
 852         priv = netdev_priv(dev);
 853         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 854         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 855         netif_carrier_on(dev);
 856
 857         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 858                 dev->name,
 859                 priv->force_speed_100 ? 100 : 10,
 860                 priv->force_duplex_full ? "full" : "half",
 861                 priv->pause_rx ? "rx" : "off",
 862                 priv->pause_tx ? "tx" : "off");
 863 }
 864
 865 /*
 866  * open callback, allocate dma rings & buffers and start rx operation
 867  */
 868 static int bcm_enet_open(struct net_device *dev)
 869 {
 870         struct bcm_enet_priv *priv;
 871         struct sockaddr addr;
 872         struct device *kdev;
 873         struct phy_device *phydev;
 874         int i, ret;
 875         unsigned int size;
 876         char phy_id[MII_BUS_ID_SIZE + 3];
 877         void *p;
 878         u32 val;
 879
 880         priv = netdev_priv(dev);
 881         kdev = &priv->pdev->dev;
 882
 883         if (priv->has_phy) {
 884                 /* connect to PHY */
 885                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 886                          priv->mii_bus->id, priv->phy_id);
 887
 888                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 889                                      PHY_INTERFACE_MODE_MII);
 890
 891                 if (IS_ERR(phydev)) {
 892                         dev_err(kdev, "could not attach to PHY\n");
 893                         return PTR_ERR(phydev);
 894                 }
 895
 896                 /* mask with MAC supported features */
 897                 phydev->supported &= (SUPPORTED_10baseT_Half |
 898                                       SUPPORTED_10baseT_Full |
 899                                       SUPPORTED_100baseT_Half |
 900                                       SUPPORTED_100baseT_Full |
 901                                       SUPPORTED_Autoneg |
 902                                       SUPPORTED_Pause |
 903                                       SUPPORTED_MII);
 904                 phydev->advertising = phydev->supported;
 905
 906                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 907                         phydev->advertising |= SUPPORTED_Pause;
 908                 else
 909                         phydev->advertising &= ~SUPPORTED_Pause;
 910
 911                 phy_attached_info(phydev);
 912
 913                 priv->old_link = 0;
 914                 priv->old_duplex = -1;
 915                 priv->old_pause = -1;
 916         }
 917
 918         /* mask all interrupts and request them */
 919         enet_writel(priv, 0, ENET_IRMASK_REG);
 920         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 921         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 922
 923         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 924         if (ret)
 925                 goto out_phy_disconnect;
 926
 927         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 928                           dev->name, dev);
 929         if (ret)
 930                 goto out_freeirq;
 931
 932         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 933                           0, dev->name, dev);
 934         if (ret)
 935                 goto out_freeirq_rx;
 936
 937         /* initialize perfect match registers */
 938         for (i = 0; i < 4; i++) {
 939                 enet_writel(priv, 0, ENET_PML_REG(i));
 940                 enet_writel(priv, 0, ENET_PMH_REG(i));
 941         }
 942
 943         /* write device mac address */
 944         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 945         bcm_enet_set_mac_address(dev, &addr);
 946
 947         /* allocate rx dma ring */
 948         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 949         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 950         if (!p) {
 951                 ret = -ENOMEM;
 952                 goto out_freeirq_tx;
 953         }
 954
 955         priv->rx_desc_alloc_size = size;
 956         priv->rx_desc_cpu = p;
 957
 958         /* allocate tx dma ring */
 959         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 960         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 961         if (!p) {
 962                 ret = -ENOMEM;
 963                 goto out_free_rx_ring;
 964         }
 965
 966         priv->tx_desc_alloc_size = size;
 967         priv->tx_desc_cpu = p;
 968
 969         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 970                                GFP_KERNEL);
 971         if (!priv->tx_skb) {
 972                 ret = -ENOMEM;
 973                 goto out_free_tx_ring;
 974         }
 975
 976         priv->tx_desc_count = priv->tx_ring_size;
 977         priv->tx_dirty_desc = 0;
 978         priv->tx_curr_desc = 0;
 979         spin_lock_init(&priv->tx_lock);
 980
 981         /* init & fill rx ring with skbs */
 982         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 983                                GFP_KERNEL);
 984         if (!priv->rx_skb) {
 985                 ret = -ENOMEM;
 986                 goto out_free_tx_skb;
 987         }
 988
 989         priv->rx_desc_count = 0;
 990         priv->rx_dirty_desc = 0;
 991         priv->rx_curr_desc = 0;
 992
 993         /* initialize flow control buffer allocation */
 994         if (priv->dma_has_sram)
 995                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 996                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 997         else
 998                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 999                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1000
1001         if (bcm_enet_refill_rx(dev)) {
1002                 dev_err(kdev, "cannot allocate rx skb queue\n");
1003                 ret = -ENOMEM;
1004                 goto out;
1005         }
1006
1007         /* write rx & tx ring addresses */
1008         if (priv->dma_has_sram) {
1009                 enet_dmas_writel(priv, priv->rx_desc_dma,
1010                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1011                 enet_dmas_writel(priv, priv->tx_desc_dma,
1012                          ENETDMAS_RSTART_REG, priv->tx_chan);
1013         } else {
1014                 enet_dmac_writel(priv, priv->rx_desc_dma,
1015                                 ENETDMAC_RSTART, priv->rx_chan);
1016                 enet_dmac_writel(priv, priv->tx_desc_dma,
1017                                 ENETDMAC_RSTART, priv->tx_chan);
1018         }
1019
1020         /* clear remaining state ram for rx & tx channel */
1021         if (priv->dma_has_sram) {
1022                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1028         } else {
1029                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1030                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1031         }
1032
1033         /* set max rx/tx length */
1034         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1035         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1036
1037         /* set dma maximum burst len */
1038         enet_dmac_writel(priv, priv->dma_maxburst,
1039                          ENETDMAC_MAXBURST, priv->rx_chan);
1040         enet_dmac_writel(priv, priv->dma_maxburst,
1041                          ENETDMAC_MAXBURST, priv->tx_chan);
1042
1043         /* set correct transmit fifo watermark */
1044         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1045
1046         /* set flow control low/high threshold to 1/3 / 2/3 */
1047         if (priv->dma_has_sram) {
1048                 val = priv->rx_ring_size / 3;
1049                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1050                 val = (priv->rx_ring_size * 2) / 3;
1051                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1052         } else {
1053                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1054                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1055                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1056         }
1057
1058         /* all set, enable mac and interrupts, start dma engine and
1059          * kick rx dma channel */
1060         wmb();
1061         val = enet_readl(priv, ENET_CTL_REG);
1062         val |= ENET_CTL_ENABLE_MASK;
1063         enet_writel(priv, val, ENET_CTL_REG);
1064         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1065         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1066                          ENETDMAC_CHANCFG, priv->rx_chan);
1067
1068         /* watch "mib counters about to overflow" interrupt */
1069         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1070         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1071
1072         /* watch "packet transferred" interrupt in rx and tx */
1073         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1074                          ENETDMAC_IR, priv->rx_chan);
1075         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1076                          ENETDMAC_IR, priv->tx_chan);
1077
1078         /* make sure we enable napi before rx interrupt  */
1079         napi_enable(&priv->napi);
1080
1081         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1082                          ENETDMAC_IRMASK, priv->rx_chan);
1083         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1084                          ENETDMAC_IRMASK, priv->tx_chan);
1085
1086         if (priv->has_phy)
1087                 phy_start(phydev);
1088         else
1089                 bcm_enet_adjust_link(dev);
1090
1091         netif_start_queue(dev);
1092         return 0;
1093
1094 out:
1095         for (i = 0; i < priv->rx_ring_size; i++) {
1096                 struct bcm_enet_desc *desc;
1097
1098                 if (!priv->rx_skb[i])
1099                         continue;
1100
1101                 desc = &priv->rx_desc_cpu[i];
1102                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1103                                  DMA_FROM_DEVICE);
1104                 kfree_skb(priv->rx_skb[i]);
1105         }
1106         kfree(priv->rx_skb);
1107
1108 out_free_tx_skb:
1109         kfree(priv->tx_skb);
1110
1111 out_free_tx_ring:
1112         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1113                           priv->tx_desc_cpu, priv->tx_desc_dma);
1114
1115 out_free_rx_ring:
1116         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1117                           priv->rx_desc_cpu, priv->rx_desc_dma);
1118
1119 out_freeirq_tx:
1120         free_irq(priv->irq_tx, dev);
1121
1122 out_freeirq_rx:
1123         free_irq(priv->irq_rx, dev);
1124
1125 out_freeirq:
1126         free_irq(dev->irq, dev);
1127
1128 out_phy_disconnect:
1129         phy_disconnect(phydev);
1130
1131         return ret;
1132 }
1133
1134 /*
1135  * disable mac
1136  */
1137 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1138 {
1139         int limit;
1140         u32 val;
1141
1142         val = enet_readl(priv, ENET_CTL_REG);
1143         val |= ENET_CTL_DISABLE_MASK;
1144         enet_writel(priv, val, ENET_CTL_REG);
1145
1146         limit = 1000;
1147         do {
1148                 u32 val;
1149
1150                 val = enet_readl(priv, ENET_CTL_REG);
1151                 if (!(val & ENET_CTL_DISABLE_MASK))
1152                         break;
1153                 udelay(1);
1154         } while (limit--);
1155 }
1156
1157 /*
1158  * disable dma in given channel
1159  */
1160 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1161 {
1162         int limit;
1163
1164         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1165
1166         limit = 1000;
1167         do {
1168                 u32 val;
1169
1170                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1171                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1172                         break;
1173                 udelay(1);
1174         } while (limit--);
1175 }
1176
1177 /*
1178  * stop callback
1179  */
1180 static int bcm_enet_stop(struct net_device *dev)
1181 {
1182         struct bcm_enet_priv *priv;
1183         struct device *kdev;
1184         int i;
1185
1186         priv = netdev_priv(dev);
1187         kdev = &priv->pdev->dev;
1188
1189         netif_stop_queue(dev);
1190         napi_disable(&priv->napi);
1191         if (priv->has_phy)
1192                 phy_stop(dev->phydev);
1193         del_timer_sync(&priv->rx_timeout);
1194
1195         /* mask all interrupts */
1196         enet_writel(priv, 0, ENET_IRMASK_REG);
1197         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1199
1200         /* make sure no mib update is scheduled */
1201         cancel_work_sync(&priv->mib_update_task);
1202
1203         /* disable dma & mac */
1204         bcm_enet_disable_dma(priv, priv->tx_chan);
1205         bcm_enet_disable_dma(priv, priv->rx_chan);
1206         bcm_enet_disable_mac(priv);
1207
1208         /* force reclaim of all tx buffers */
1209         bcm_enet_tx_reclaim(dev, 1);
1210
1211         /* free the rx skb ring */
1212         for (i = 0; i < priv->rx_ring_size; i++) {
1213                 struct bcm_enet_desc *desc;
1214
1215                 if (!priv->rx_skb[i])
1216                         continue;
1217
1218                 desc = &priv->rx_desc_cpu[i];
1219                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1220                                  DMA_FROM_DEVICE);
1221                 kfree_skb(priv->rx_skb[i]);
1222         }
1223
1224         /* free remaining allocated memory */
1225         kfree(priv->rx_skb);
1226         kfree(priv->tx_skb);
1227         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1228                           priv->rx_desc_cpu, priv->rx_desc_dma);
1229         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1230                           priv->tx_desc_cpu, priv->tx_desc_dma);
1231         free_irq(priv->irq_tx, dev);
1232         free_irq(priv->irq_rx, dev);
1233         free_irq(dev->irq, dev);
1234
1235         /* release phy */
1236         if (priv->has_phy)
1237                 phy_disconnect(dev->phydev);
1238
1239         return 0;
1240 }
1241
1242 /*
1243  * ethtool callbacks
1244  */
1245 struct bcm_enet_stats {
1246         char stat_string[ETH_GSTRING_LEN];
1247         int sizeof_stat;
1248         int stat_offset;
1249         int mib_reg;
1250 };
1251
1252 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1253                      offsetof(struct bcm_enet_priv, m)
1254 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1255                      offsetof(struct net_device_stats, m)
1256
1257 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1258         { "rx_packets", DEV_STAT(rx_packets), -1 },
1259         { "tx_packets", DEV_STAT(tx_packets), -1 },
1260         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1261         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1262         { "rx_errors", DEV_STAT(rx_errors), -1 },
1263         { "tx_errors", DEV_STAT(tx_errors), -1 },
1264         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1265         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1266
1267         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1268         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1269         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1270         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1271         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1272         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1273         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1274         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1275         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1276         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1277         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1278         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1279         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1280         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1281         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1282         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1283         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1284         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1285         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1286         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1287         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1288
1289         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1290         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1291         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1292         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1293         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1294         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1295         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1296         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1297         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1298         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1299         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1300         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1301         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1302         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1303         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1304         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1305         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1306         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1307         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1308         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1309         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1310         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1311
1312 };
1313
1314 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1315
1316 static const u32 unused_mib_regs[] = {
1317         ETH_MIB_TX_ALL_OCTETS,
1318         ETH_MIB_TX_ALL_PKTS,
1319         ETH_MIB_RX_ALL_OCTETS,
1320         ETH_MIB_RX_ALL_PKTS,
1321 };
1322
1323
1324 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1325                                  struct ethtool_drvinfo *drvinfo)
1326 {
1327         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1328         strlcpy(drvinfo->version, bcm_enet_driver_version,
1329                 sizeof(drvinfo->version));
1330         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1331         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1332 }
1333
1334 static int bcm_enet_get_sset_count(struct net_device *netdev,
1335                                         int string_set)
1336 {
1337         switch (string_set) {
1338         case ETH_SS_STATS:
1339                 return BCM_ENET_STATS_LEN;
1340         default:
1341                 return -EINVAL;
1342         }
1343 }
1344
1345 static void bcm_enet_get_strings(struct net_device *netdev,
1346                                  u32 stringset, u8 *data)
1347 {
1348         int i;
1349
1350         switch (stringset) {
1351         case ETH_SS_STATS:
1352                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1353                         memcpy(data + i * ETH_GSTRING_LEN,
1354                                bcm_enet_gstrings_stats[i].stat_string,
1355                                ETH_GSTRING_LEN);
1356                 }
1357                 break;
1358         }
1359 }
1360
1361 static void update_mib_counters(struct bcm_enet_priv *priv)
1362 {
1363         int i;
1364
1365         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1366                 const struct bcm_enet_stats *s;
1367                 u32 val;
1368                 char *p;
1369
1370                 s = &bcm_enet_gstrings_stats[i];
1371                 if (s->mib_reg == -1)
1372                         continue;
1373
1374                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1375                 p = (char *)priv + s->stat_offset;
1376
1377                 if (s->sizeof_stat == sizeof(u64))
1378                         *(u64 *)p += val;
1379                 else
1380                         *(u32 *)p += val;
1381         }
1382
1383         /* also empty unused mib counters to make sure mib counter
1384          * overflow interrupt is cleared */
1385         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1386                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1387 }
1388
1389 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1390 {
1391         struct bcm_enet_priv *priv;
1392
1393         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1394         mutex_lock(&priv->mib_update_lock);
1395         update_mib_counters(priv);
1396         mutex_unlock(&priv->mib_update_lock);
1397
1398         /* reenable mib interrupt */
1399         if (netif_running(priv->net_dev))
1400                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1401 }
1402
1403 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1404                                        struct ethtool_stats *stats,
1405                                        u64 *data)
1406 {
1407         struct bcm_enet_priv *priv;
1408         int i;
1409
1410         priv = netdev_priv(netdev);
1411
1412         mutex_lock(&priv->mib_update_lock);
1413         update_mib_counters(priv);
1414
1415         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1416                 const struct bcm_enet_stats *s;
1417                 char *p;
1418
1419                 s = &bcm_enet_gstrings_stats[i];
1420                 if (s->mib_reg == -1)
1421                         p = (char *)&netdev->stats;
1422                 else
1423                         p = (char *)priv;
1424                 p += s->stat_offset;
1425                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1426                         *(u64 *)p : *(u32 *)p;
1427         }
1428         mutex_unlock(&priv->mib_update_lock);
1429 }
1430
1431 static int bcm_enet_nway_reset(struct net_device *dev)
1432 {
1433         struct bcm_enet_priv *priv;
1434
1435         priv = netdev_priv(dev);
1436         if (priv->has_phy) {
1437                 if (!dev->phydev)
1438                         return -ENODEV;
1439                 return genphy_restart_aneg(dev->phydev);
1440         }
1441
1442         return -EOPNOTSUPP;
1443 }
1444
1445 static int bcm_enet_get_settings(struct net_device *dev,
1446                                  struct ethtool_cmd *cmd)
1447 {
1448         struct bcm_enet_priv *priv;
1449
1450         priv = netdev_priv(dev);
1451
1452         cmd->maxrxpkt = 0;
1453         cmd->maxtxpkt = 0;
1454
1455         if (priv->has_phy) {
1456                 if (!dev->phydev)
1457                         return -ENODEV;
1458                 return phy_ethtool_gset(dev->phydev, cmd);
1459         } else {
1460                 cmd->autoneg = 0;
1461                 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1462                                             ? SPEED_100 : SPEED_10));
1463                 cmd->duplex = (priv->force_duplex_full) ?
1464                         DUPLEX_FULL : DUPLEX_HALF;
1465                 cmd->supported = ADVERTISED_10baseT_Half  |
1466                         ADVERTISED_10baseT_Full |
1467                         ADVERTISED_100baseT_Half |
1468                         ADVERTISED_100baseT_Full;
1469                 cmd->advertising = 0;
1470                 cmd->port = PORT_MII;
1471                 cmd->transceiver = XCVR_EXTERNAL;
1472         }
1473         return 0;
1474 }
1475
1476 static int bcm_enet_set_settings(struct net_device *dev,
1477                                  struct ethtool_cmd *cmd)
1478 {
1479         struct bcm_enet_priv *priv;
1480
1481         priv = netdev_priv(dev);
1482         if (priv->has_phy) {
1483                 if (!dev->phydev)
1484                         return -ENODEV;
1485                 return phy_ethtool_sset(dev->phydev, cmd);
1486         } else {
1487
1488                 if (cmd->autoneg ||
1489                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1490                     cmd->port != PORT_MII)
1491                         return -EINVAL;
1492
1493                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1494                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1495
1496                 if (netif_running(dev))
1497                         bcm_enet_adjust_link(dev);
1498                 return 0;
1499         }
1500 }
1501
1502 static void bcm_enet_get_ringparam(struct net_device *dev,
1503                                    struct ethtool_ringparam *ering)
1504 {
1505         struct bcm_enet_priv *priv;
1506
1507         priv = netdev_priv(dev);
1508
1509         /* rx/tx ring is actually only limited by memory */
1510         ering->rx_max_pending = 8192;
1511         ering->tx_max_pending = 8192;
1512         ering->rx_pending = priv->rx_ring_size;
1513         ering->tx_pending = priv->tx_ring_size;
1514 }
1515
1516 static int bcm_enet_set_ringparam(struct net_device *dev,
1517                                   struct ethtool_ringparam *ering)
1518 {
1519         struct bcm_enet_priv *priv;
1520         int was_running;
1521
1522         priv = netdev_priv(dev);
1523
1524         was_running = 0;
1525         if (netif_running(dev)) {
1526                 bcm_enet_stop(dev);
1527                 was_running = 1;
1528         }
1529
1530         priv->rx_ring_size = ering->rx_pending;
1531         priv->tx_ring_size = ering->tx_pending;
1532
1533         if (was_running) {
1534                 int err;
1535
1536                 err = bcm_enet_open(dev);
1537                 if (err)
1538                         dev_close(dev);
1539                 else
1540                         bcm_enet_set_multicast_list(dev);
1541         }
1542         return 0;
1543 }
1544
1545 static void bcm_enet_get_pauseparam(struct net_device *dev,
1546                                     struct ethtool_pauseparam *ecmd)
1547 {
1548         struct bcm_enet_priv *priv;
1549
1550         priv = netdev_priv(dev);
1551         ecmd->autoneg = priv->pause_auto;
1552         ecmd->rx_pause = priv->pause_rx;
1553         ecmd->tx_pause = priv->pause_tx;
1554 }
1555
1556 static int bcm_enet_set_pauseparam(struct net_device *dev,
1557                                    struct ethtool_pauseparam *ecmd)
1558 {
1559         struct bcm_enet_priv *priv;
1560
1561         priv = netdev_priv(dev);
1562
1563         if (priv->has_phy) {
1564                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1565                         /* asymetric pause mode not supported,
1566                          * actually possible but integrated PHY has RO
1567                          * asym_pause bit */
1568                         return -EINVAL;
1569                 }
1570         } else {
1571                 /* no pause autoneg on direct mii connection */
1572                 if (ecmd->autoneg)
1573                         return -EINVAL;
1574         }
1575
1576         priv->pause_auto = ecmd->autoneg;
1577         priv->pause_rx = ecmd->rx_pause;
1578         priv->pause_tx = ecmd->tx_pause;
1579
1580         return 0;
1581 }
1582
1583 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1584         .get_strings            = bcm_enet_get_strings,
1585         .get_sset_count         = bcm_enet_get_sset_count,
1586         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1587         .nway_reset             = bcm_enet_nway_reset,
1588         .get_settings           = bcm_enet_get_settings,
1589         .set_settings           = bcm_enet_set_settings,
1590         .get_drvinfo            = bcm_enet_get_drvinfo,
1591         .get_link               = ethtool_op_get_link,
1592         .get_ringparam          = bcm_enet_get_ringparam,
1593         .set_ringparam          = bcm_enet_set_ringparam,
1594         .get_pauseparam         = bcm_enet_get_pauseparam,
1595         .set_pauseparam         = bcm_enet_set_pauseparam,
1596 };
1597
1598 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1599 {
1600         struct bcm_enet_priv *priv;
1601
1602         priv = netdev_priv(dev);
1603         if (priv->has_phy) {
1604                 if (!dev->phydev)
1605                         return -ENODEV;
1606                 return phy_mii_ioctl(dev->phydev, rq, cmd);
1607         } else {
1608                 struct mii_if_info mii;
1609
1610                 mii.dev = dev;
1611                 mii.mdio_read = bcm_enet_mdio_read_mii;
1612                 mii.mdio_write = bcm_enet_mdio_write_mii;
1613                 mii.phy_id = 0;
1614                 mii.phy_id_mask = 0x3f;
1615                 mii.reg_num_mask = 0x1f;
1616                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1617         }
1618 }
1619
1620 /*
1621  * calculate actual hardware mtu
1622  */
1623 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1624 {
1625         int actual_mtu;
1626
1627         actual_mtu = mtu;
1628
1629         /* add ethernet header + vlan tag size */
1630         actual_mtu += VLAN_ETH_HLEN;
1631
1632         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1633                 return -EINVAL;
1634
1635         /*
1636          * setup maximum size before we get overflow mark in
1637          * descriptor, note that this will not prevent reception of
1638          * big frames, they will be split into multiple buffers
1639          * anyway
1640          */
1641         priv->hw_mtu = actual_mtu;
1642
1643         /*
1644          * align rx buffer size to dma burst len, account FCS since
1645          * it's appended
1646          */
1647         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1648                                   priv->dma_maxburst * 4);
1649         return 0;
1650 }
1651
1652 /*
1653  * adjust mtu, can't be called while device is running
1654  */
1655 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1656 {
1657         int ret;
1658
1659         if (netif_running(dev))
1660                 return -EBUSY;
1661
1662         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1663         if (ret)
1664                 return ret;
1665         dev->mtu = new_mtu;
1666         return 0;
1667 }
1668
1669 /*
1670  * preinit hardware to allow mii operation while device is down
1671  */
1672 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1673 {
1674         u32 val;
1675         int limit;
1676
1677         /* make sure mac is disabled */
1678         bcm_enet_disable_mac(priv);
1679
1680         /* soft reset mac */
1681         val = ENET_CTL_SRESET_MASK;
1682         enet_writel(priv, val, ENET_CTL_REG);
1683         wmb();
1684
1685         limit = 1000;
1686         do {
1687                 val = enet_readl(priv, ENET_CTL_REG);
1688                 if (!(val & ENET_CTL_SRESET_MASK))
1689                         break;
1690                 udelay(1);
1691         } while (limit--);
1692
1693         /* select correct mii interface */
1694         val = enet_readl(priv, ENET_CTL_REG);
1695         if (priv->use_external_mii)
1696                 val |= ENET_CTL_EPHYSEL_MASK;
1697         else
1698                 val &= ~ENET_CTL_EPHYSEL_MASK;
1699         enet_writel(priv, val, ENET_CTL_REG);
1700
1701         /* turn on mdc clock */
1702         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1703                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1704
1705         /* set mib counters to self-clear when read */
1706         val = enet_readl(priv, ENET_MIBCTL_REG);
1707         val |= ENET_MIBCTL_RDCLEAR_MASK;
1708         enet_writel(priv, val, ENET_MIBCTL_REG);
1709 }
1710
1711 static const struct net_device_ops bcm_enet_ops = {
1712         .ndo_open               = bcm_enet_open,
1713         .ndo_stop               = bcm_enet_stop,
1714         .ndo_start_xmit         = bcm_enet_start_xmit,
1715         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1716         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1717         .ndo_do_ioctl           = bcm_enet_ioctl,
1718         .ndo_change_mtu         = bcm_enet_change_mtu,
1719 };
1720
1721 /*
1722  * allocate netdevice, request register memory and register device.
1723  */
1724 static int bcm_enet_probe(struct platform_device *pdev)
1725 {
1726         struct bcm_enet_priv *priv;
1727         struct net_device *dev;
1728         struct bcm63xx_enet_platform_data *pd;
1729         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1730         struct mii_bus *bus;
1731         const char *clk_name;
1732         int i, ret;
1733
1734         /* stop if shared driver failed, assume driver->probe will be
1735          * called in the same order we register devices (correct ?) */
1736         if (!bcm_enet_shared_base[0])
1737                 return -ENODEV;
1738
1739         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1740         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1741         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1742         if (!res_irq || !res_irq_rx || !res_irq_tx)
1743                 return -ENODEV;
1744
1745         ret = 0;
1746         dev = alloc_etherdev(sizeof(*priv));
1747         if (!dev)
1748                 return -ENOMEM;
1749         priv = netdev_priv(dev);
1750
1751         priv->enet_is_sw = false;
1752         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1753
1754         ret = compute_hw_mtu(priv, dev->mtu);
1755         if (ret)
1756                 goto out;
1757
1758         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1759         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1760         if (IS_ERR(priv->base)) {
1761                 ret = PTR_ERR(priv->base);
1762                 goto out;
1763         }
1764
1765         dev->irq = priv->irq = res_irq->start;
1766         priv->irq_rx = res_irq_rx->start;
1767         priv->irq_tx = res_irq_tx->start;
1768         priv->mac_id = pdev->id;
1769
1770         /* get rx & tx dma channel id for this mac */
1771         if (priv->mac_id == 0) {
1772                 priv->rx_chan = 0;
1773                 priv->tx_chan = 1;
1774                 clk_name = "enet0";
1775         } else {
1776                 priv->rx_chan = 2;
1777                 priv->tx_chan = 3;
1778                 clk_name = "enet1";
1779         }
1780
1781         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1782         if (IS_ERR(priv->mac_clk)) {
1783                 ret = PTR_ERR(priv->mac_clk);
1784                 goto out;
1785         }
1786         clk_prepare_enable(priv->mac_clk);
1787
1788         /* initialize default and fetch platform data */
1789         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1790         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1791
1792         pd = dev_get_platdata(&pdev->dev);
1793         if (pd) {
1794                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1795                 priv->has_phy = pd->has_phy;
1796                 priv->phy_id = pd->phy_id;
1797                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1798                 priv->phy_interrupt = pd->phy_interrupt;
1799                 priv->use_external_mii = !pd->use_internal_phy;
1800                 priv->pause_auto = pd->pause_auto;
1801                 priv->pause_rx = pd->pause_rx;
1802                 priv->pause_tx = pd->pause_tx;
1803                 priv->force_duplex_full = pd->force_duplex_full;
1804                 priv->force_speed_100 = pd->force_speed_100;
1805                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1806                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1807                 priv->dma_chan_width = pd->dma_chan_width;
1808                 priv->dma_has_sram = pd->dma_has_sram;
1809                 priv->dma_desc_shift = pd->dma_desc_shift;
1810         }
1811
1812         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1813                 /* using internal PHY, enable clock */
1814                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1815                 if (IS_ERR(priv->phy_clk)) {
1816                         ret = PTR_ERR(priv->phy_clk);
1817                         priv->phy_clk = NULL;
1818                         goto out_put_clk_mac;
1819                 }
1820                 clk_prepare_enable(priv->phy_clk);
1821         }
1822
1823         /* do minimal hardware init to be able to probe mii bus */
1824         bcm_enet_hw_preinit(priv);
1825
1826         /* MII bus registration */
1827         if (priv->has_phy) {
1828
1829                 priv->mii_bus = mdiobus_alloc();
1830                 if (!priv->mii_bus) {
1831                         ret = -ENOMEM;
1832                         goto out_uninit_hw;
1833                 }
1834
1835                 bus = priv->mii_bus;
1836                 bus->name = "bcm63xx_enet MII bus";
1837                 bus->parent = &pdev->dev;
1838                 bus->priv = priv;
1839                 bus->read = bcm_enet_mdio_read_phylib;
1840                 bus->write = bcm_enet_mdio_write_phylib;
1841                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1842
1843                 /* only probe bus where we think the PHY is, because
1844                  * the mdio read operation return 0 instead of 0xffff
1845                  * if a slave is not present on hw */
1846                 bus->phy_mask = ~(1 << priv->phy_id);
1847
1848                 if (priv->has_phy_interrupt)
1849                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1850
1851                 ret = mdiobus_register(bus);
1852                 if (ret) {
1853                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1854                         goto out_free_mdio;
1855                 }
1856         } else {
1857
1858                 /* run platform code to initialize PHY device */
1859                 if (pd && pd->mii_config &&
1860                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1861                                    bcm_enet_mdio_write_mii)) {
1862                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1863                         goto out_uninit_hw;
1864                 }
1865         }
1866
1867         spin_lock_init(&priv->rx_lock);
1868
1869         /* init rx timeout (used for oom) */
1870         init_timer(&priv->rx_timeout);
1871         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1872         priv->rx_timeout.data = (unsigned long)dev;
1873
1874         /* init the mib update lock&work */
1875         mutex_init(&priv->mib_update_lock);
1876         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1877
1878         /* zero mib counters */
1879         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1880                 enet_writel(priv, 0, ENET_MIB_REG(i));
1881
1882         /* register netdevice */
1883         dev->netdev_ops = &bcm_enet_ops;
1884         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1885
1886         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1887         SET_NETDEV_DEV(dev, &pdev->dev);
1888
1889         ret = register_netdev(dev);
1890         if (ret)
1891                 goto out_unregister_mdio;
1892
1893         netif_carrier_off(dev);
1894         platform_set_drvdata(pdev, dev);
1895         priv->pdev = pdev;
1896         priv->net_dev = dev;
1897
1898         return 0;
1899
1900 out_unregister_mdio:
1901         if (priv->mii_bus)
1902                 mdiobus_unregister(priv->mii_bus);
1903
1904 out_free_mdio:
1905         if (priv->mii_bus)
1906                 mdiobus_free(priv->mii_bus);
1907
1908 out_uninit_hw:
1909         /* turn off mdc clock */
1910         enet_writel(priv, 0, ENET_MIISC_REG);
1911         if (priv->phy_clk) {
1912                 clk_disable_unprepare(priv->phy_clk);
1913                 clk_put(priv->phy_clk);
1914         }
1915
1916 out_put_clk_mac:
1917         clk_disable_unprepare(priv->mac_clk);
1918         clk_put(priv->mac_clk);
1919 out:
1920         free_netdev(dev);
1921         return ret;
1922 }
1923
1924
1925 /*
1926  * exit func, stops hardware and unregisters netdevice
1927  */
1928 static int bcm_enet_remove(struct platform_device *pdev)
1929 {
1930         struct bcm_enet_priv *priv;
1931         struct net_device *dev;
1932
1933         /* stop netdevice */
1934         dev = platform_get_drvdata(pdev);
1935         priv = netdev_priv(dev);
1936         unregister_netdev(dev);
1937
1938         /* turn off mdc clock */
1939         enet_writel(priv, 0, ENET_MIISC_REG);
1940
1941         if (priv->has_phy) {
1942                 mdiobus_unregister(priv->mii_bus);
1943                 mdiobus_free(priv->mii_bus);
1944         } else {
1945                 struct bcm63xx_enet_platform_data *pd;
1946
1947                 pd = dev_get_platdata(&pdev->dev);
1948                 if (pd && pd->mii_config)
1949                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1950                                        bcm_enet_mdio_write_mii);
1951         }
1952
1953         /* disable hw block clocks */
1954         if (priv->phy_clk) {
1955                 clk_disable_unprepare(priv->phy_clk);
1956                 clk_put(priv->phy_clk);
1957         }
1958         clk_disable_unprepare(priv->mac_clk);
1959         clk_put(priv->mac_clk);
1960
1961         free_netdev(dev);
1962         return 0;
1963 }
1964
1965 struct platform_driver bcm63xx_enet_driver = {
1966         .probe  = bcm_enet_probe,
1967         .remove = bcm_enet_remove,
1968         .driver = {
1969                 .name   = "bcm63xx_enet",
1970                 .owner  = THIS_MODULE,
1971         },
1972 };
1973
1974 /*
1975  * switch mii access callbacks
1976  */
1977 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1978                                 int ext, int phy_id, int location)
1979 {
1980         u32 reg;
1981         int ret;
1982
1983         spin_lock_bh(&priv->enetsw_mdio_lock);
1984         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1985
1986         reg = ENETSW_MDIOC_RD_MASK |
1987                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1988                 (location << ENETSW_MDIOC_REG_SHIFT);
1989
1990         if (ext)
1991                 reg |= ENETSW_MDIOC_EXT_MASK;
1992
1993         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1994         udelay(50);
1995         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1996         spin_unlock_bh(&priv->enetsw_mdio_lock);
1997         return ret;
1998 }
1999
2000 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2001                                  int ext, int phy_id, int location,
2002                                  uint16_t data)
2003 {
2004         u32 reg;
2005
2006         spin_lock_bh(&priv->enetsw_mdio_lock);
2007         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2008
2009         reg = ENETSW_MDIOC_WR_MASK |
2010                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2011                 (location << ENETSW_MDIOC_REG_SHIFT);
2012
2013         if (ext)
2014                 reg |= ENETSW_MDIOC_EXT_MASK;
2015
2016         reg |= data;
2017
2018         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2019         udelay(50);
2020         spin_unlock_bh(&priv->enetsw_mdio_lock);
2021 }
2022
2023 static inline int bcm_enet_port_is_rgmii(int portid)
2024 {
2025         return portid >= ENETSW_RGMII_PORT0;
2026 }
2027
2028 /*
2029  * enet sw PHY polling
2030  */
2031 static void swphy_poll_timer(unsigned long data)
2032 {
2033         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2034         unsigned int i;
2035
2036         for (i = 0; i < priv->num_ports; i++) {
2037                 struct bcm63xx_enetsw_port *port;
2038                 int val, j, up, advertise, lpa, speed, duplex, media;
2039                 int external_phy = bcm_enet_port_is_rgmii(i);
2040                 u8 override;
2041
2042                 port = &priv->used_ports[i];
2043                 if (!port->used)
2044                         continue;
2045
2046                 if (port->bypass_link)
2047                         continue;
2048
2049                 /* dummy read to clear */
2050                 for (j = 0; j < 2; j++)
2051                         val = bcmenet_sw_mdio_read(priv, external_phy,
2052                                                    port->phy_id, MII_BMSR);
2053
2054                 if (val == 0xffff)
2055                         continue;
2056
2057                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2058                 if (!(up ^ priv->sw_port_link[i]))
2059                         continue;
2060
2061                 priv->sw_port_link[i] = up;
2062
2063                 /* link changed */
2064                 if (!up) {
2065                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2066                                  port->name);
2067                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2068                                       ENETSW_PORTOV_REG(i));
2069                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2070                                       ENETSW_PTCTRL_TXDIS_MASK,
2071                                       ENETSW_PTCTRL_REG(i));
2072                         continue;
2073                 }
2074
2075                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2076                                                  port->phy_id, MII_ADVERTISE);
2077
2078                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2079                                            MII_LPA);
2080
2081                 /* figure out media and duplex from advertise and LPA values */
2082                 media = mii_nway_result(lpa & advertise);
2083                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2084
2085                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2086                         speed = 100;
2087                 else
2088                         speed = 10;
2089
2090                 if (val & BMSR_ESTATEN) {
2091                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2092                                                 port->phy_id, MII_CTRL1000);
2093
2094                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2095                                                 port->phy_id, MII_STAT1000);
2096
2097                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2098                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2099                                 speed = 1000;
2100                                 duplex = (lpa & LPA_1000FULL);
2101                         }
2102                 }
2103
2104                 dev_info(&priv->pdev->dev,
2105                          "link UP on %s, %dMbps, %s-duplex\n",
2106                          port->name, speed, duplex ? "full" : "half");
2107
2108                 override = ENETSW_PORTOV_ENABLE_MASK |
2109                         ENETSW_PORTOV_LINKUP_MASK;
2110
2111                 if (speed == 1000)
2112                         override |= ENETSW_IMPOV_1000_MASK;
2113                 else if (speed == 100)
2114                         override |= ENETSW_IMPOV_100_MASK;
2115                 if (duplex)
2116                         override |= ENETSW_IMPOV_FDX_MASK;
2117
2118                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2119                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2120         }
2121
2122         priv->swphy_poll.expires = jiffies + HZ;
2123         add_timer(&priv->swphy_poll);
2124 }
2125
2126 /*
2127  * open callback, allocate dma rings & buffers and start rx operation
2128  */
2129 static int bcm_enetsw_open(struct net_device *dev)
2130 {
2131         struct bcm_enet_priv *priv;
2132         struct device *kdev;
2133         int i, ret;
2134         unsigned int size;
2135         void *p;
2136         u32 val;
2137
2138         priv = netdev_priv(dev);
2139         kdev = &priv->pdev->dev;
2140
2141         /* mask all interrupts and request them */
2142         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2143         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2144
2145         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2146                           0, dev->name, dev);
2147         if (ret)
2148                 goto out_freeirq;
2149
2150         if (priv->irq_tx != -1) {
2151                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2152                                   0, dev->name, dev);
2153                 if (ret)
2154                         goto out_freeirq_rx;
2155         }
2156
2157         /* allocate rx dma ring */
2158         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2159         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2160         if (!p) {
2161                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2162                 ret = -ENOMEM;
2163                 goto out_freeirq_tx;
2164         }
2165
2166         memset(p, 0, size);
2167         priv->rx_desc_alloc_size = size;
2168         priv->rx_desc_cpu = p;
2169
2170         /* allocate tx dma ring */
2171         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2172         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2173         if (!p) {
2174                 dev_err(kdev, "cannot allocate tx ring\n");
2175                 ret = -ENOMEM;
2176                 goto out_free_rx_ring;
2177         }
2178
2179         memset(p, 0, size);
2180         priv->tx_desc_alloc_size = size;
2181         priv->tx_desc_cpu = p;
2182
2183         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2184                                GFP_KERNEL);
2185         if (!priv->tx_skb) {
2186                 dev_err(kdev, "cannot allocate rx skb queue\n");
2187                 ret = -ENOMEM;
2188                 goto out_free_tx_ring;
2189         }
2190
2191         priv->tx_desc_count = priv->tx_ring_size;
2192         priv->tx_dirty_desc = 0;
2193         priv->tx_curr_desc = 0;
2194         spin_lock_init(&priv->tx_lock);
2195
2196         /* init & fill rx ring with skbs */
2197         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2198                                GFP_KERNEL);
2199         if (!priv->rx_skb) {
2200                 dev_err(kdev, "cannot allocate rx skb queue\n");
2201                 ret = -ENOMEM;
2202                 goto out_free_tx_skb;
2203         }
2204
2205         priv->rx_desc_count = 0;
2206         priv->rx_dirty_desc = 0;
2207         priv->rx_curr_desc = 0;
2208
2209         /* disable all ports */
2210         for (i = 0; i < priv->num_ports; i++) {
2211                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2212                               ENETSW_PORTOV_REG(i));
2213                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2214                               ENETSW_PTCTRL_TXDIS_MASK,
2215                               ENETSW_PTCTRL_REG(i));
2216
2217                 priv->sw_port_link[i] = 0;
2218         }
2219
2220         /* reset mib */
2221         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2222         val |= ENETSW_GMCR_RST_MIB_MASK;
2223         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2224         mdelay(1);
2225         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2226         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2227         mdelay(1);
2228
2229         /* force CPU port state */
2230         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2231         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2232         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2233
2234         /* enable switch forward engine */
2235         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2236         val |= ENETSW_SWMODE_FWD_EN_MASK;
2237         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2238
2239         /* enable jumbo on all ports */
2240         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2241         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2242
2243         /* initialize flow control buffer allocation */
2244         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2245                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2246
2247         if (bcm_enet_refill_rx(dev)) {
2248                 dev_err(kdev, "cannot allocate rx skb queue\n");
2249                 ret = -ENOMEM;
2250                 goto out;
2251         }
2252
2253         /* write rx & tx ring addresses */
2254         enet_dmas_writel(priv, priv->rx_desc_dma,
2255                          ENETDMAS_RSTART_REG, priv->rx_chan);
2256         enet_dmas_writel(priv, priv->tx_desc_dma,
2257                          ENETDMAS_RSTART_REG, priv->tx_chan);
2258
2259         /* clear remaining state ram for rx & tx channel */
2260         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2261         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2262         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2263         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2264         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2265         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2266
2267         /* set dma maximum burst len */
2268         enet_dmac_writel(priv, priv->dma_maxburst,
2269                          ENETDMAC_MAXBURST, priv->rx_chan);
2270         enet_dmac_writel(priv, priv->dma_maxburst,
2271                          ENETDMAC_MAXBURST, priv->tx_chan);
2272
2273         /* set flow control low/high threshold to 1/3 / 2/3 */
2274         val = priv->rx_ring_size / 3;
2275         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2276         val = (priv->rx_ring_size * 2) / 3;
2277         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2278
2279         /* all set, enable mac and interrupts, start dma engine and
2280          * kick rx dma channel
2281          */
2282         wmb();
2283         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2284         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2285                          ENETDMAC_CHANCFG, priv->rx_chan);
2286
2287         /* watch "packet transferred" interrupt in rx and tx */
2288         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2289                          ENETDMAC_IR, priv->rx_chan);
2290         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2291                          ENETDMAC_IR, priv->tx_chan);
2292
2293         /* make sure we enable napi before rx interrupt  */
2294         napi_enable(&priv->napi);
2295
2296         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2297                          ENETDMAC_IRMASK, priv->rx_chan);
2298         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2299                          ENETDMAC_IRMASK, priv->tx_chan);
2300
2301         netif_carrier_on(dev);
2302         netif_start_queue(dev);
2303
2304         /* apply override config for bypass_link ports here. */
2305         for (i = 0; i < priv->num_ports; i++) {
2306                 struct bcm63xx_enetsw_port *port;
2307                 u8 override;
2308                 port = &priv->used_ports[i];
2309                 if (!port->used)
2310                         continue;
2311
2312                 if (!port->bypass_link)
2313                         continue;
2314
2315                 override = ENETSW_PORTOV_ENABLE_MASK |
2316                         ENETSW_PORTOV_LINKUP_MASK;
2317
2318                 switch (port->force_speed) {
2319                 case 1000:
2320                         override |= ENETSW_IMPOV_1000_MASK;
2321                         break;
2322                 case 100:
2323                         override |= ENETSW_IMPOV_100_MASK;
2324                         break;
2325                 case 10:
2326                         break;
2327                 default:
2328                         pr_warn("invalid forced speed on port %s: assume 10\n",
2329                                port->name);
2330                         break;
2331                 }
2332
2333                 if (port->force_duplex_full)
2334                         override |= ENETSW_IMPOV_FDX_MASK;
2335
2336
2337                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2338                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2339         }
2340
2341         /* start phy polling timer */
2342         init_timer(&priv->swphy_poll);
2343         priv->swphy_poll.function = swphy_poll_timer;
2344         priv->swphy_poll.data = (unsigned long)priv;
2345         priv->swphy_poll.expires = jiffies;
2346         add_timer(&priv->swphy_poll);
2347         return 0;
2348
2349 out:
2350         for (i = 0; i < priv->rx_ring_size; i++) {
2351                 struct bcm_enet_desc *desc;
2352
2353                 if (!priv->rx_skb[i])
2354                         continue;
2355
2356                 desc = &priv->rx_desc_cpu[i];
2357                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2358                                  DMA_FROM_DEVICE);
2359                 kfree_skb(priv->rx_skb[i]);
2360         }
2361         kfree(priv->rx_skb);
2362
2363 out_free_tx_skb:
2364         kfree(priv->tx_skb);
2365
2366 out_free_tx_ring:
2367         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2368                           priv->tx_desc_cpu, priv->tx_desc_dma);
2369
2370 out_free_rx_ring:
2371         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2372                           priv->rx_desc_cpu, priv->rx_desc_dma);
2373
2374 out_freeirq_tx:
2375         if (priv->irq_tx != -1)
2376                 free_irq(priv->irq_tx, dev);
2377
2378 out_freeirq_rx:
2379         free_irq(priv->irq_rx, dev);
2380
2381 out_freeirq:
2382         return ret;
2383 }
2384
2385 /* stop callback */
2386 static int bcm_enetsw_stop(struct net_device *dev)
2387 {
2388         struct bcm_enet_priv *priv;
2389         struct device *kdev;
2390         int i;
2391
2392         priv = netdev_priv(dev);
2393         kdev = &priv->pdev->dev;
2394
2395         del_timer_sync(&priv->swphy_poll);
2396         netif_stop_queue(dev);
2397         napi_disable(&priv->napi);
2398         del_timer_sync(&priv->rx_timeout);
2399
2400         /* mask all interrupts */
2401         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2402         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2403
2404         /* disable dma & mac */
2405         bcm_enet_disable_dma(priv, priv->tx_chan);
2406         bcm_enet_disable_dma(priv, priv->rx_chan);
2407
2408         /* force reclaim of all tx buffers */
2409         bcm_enet_tx_reclaim(dev, 1);
2410
2411         /* free the rx skb ring */
2412         for (i = 0; i < priv->rx_ring_size; i++) {
2413                 struct bcm_enet_desc *desc;
2414
2415                 if (!priv->rx_skb[i])
2416                         continue;
2417
2418                 desc = &priv->rx_desc_cpu[i];
2419                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2420                                  DMA_FROM_DEVICE);
2421                 kfree_skb(priv->rx_skb[i]);
2422         }
2423
2424         /* free remaining allocated memory */
2425         kfree(priv->rx_skb);
2426         kfree(priv->tx_skb);
2427         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2428                           priv->rx_desc_cpu, priv->rx_desc_dma);
2429         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2430                           priv->tx_desc_cpu, priv->tx_desc_dma);
2431         if (priv->irq_tx != -1)
2432                 free_irq(priv->irq_tx, dev);
2433         free_irq(priv->irq_rx, dev);
2434
2435         return 0;
2436 }
2437
2438 /* try to sort out phy external status by walking the used_port field
2439  * in the bcm_enet_priv structure. in case the phy address is not
2440  * assigned to any physical port on the switch, assume it is external
2441  * (and yell at the user).
2442  */
2443 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2444 {
2445         int i;
2446
2447         for (i = 0; i < priv->num_ports; ++i) {
2448                 if (!priv->used_ports[i].used)
2449                         continue;
2450                 if (priv->used_ports[i].phy_id == phy_id)
2451                         return bcm_enet_port_is_rgmii(i);
2452         }
2453
2454         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2455                     phy_id);
2456         return 1;
2457 }
2458
2459 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2460  * external/internal status of the given phy_id first.
2461  */
2462 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2463                                     int location)
2464 {
2465         struct bcm_enet_priv *priv;
2466
2467         priv = netdev_priv(dev);
2468         return bcmenet_sw_mdio_read(priv,
2469                                     bcm_enetsw_phy_is_external(priv, phy_id),
2470                                     phy_id, location);
2471 }
2472
2473 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2474  * external/internal status of the given phy_id first.
2475  */
2476 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2477                                       int location,
2478                                       int val)
2479 {
2480         struct bcm_enet_priv *priv;
2481
2482         priv = netdev_priv(dev);
2483         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2484                               phy_id, location, val);
2485 }
2486
2487 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2488 {
2489         struct mii_if_info mii;
2490
2491         mii.dev = dev;
2492         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2493         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2494         mii.phy_id = 0;
2495         mii.phy_id_mask = 0x3f;
2496         mii.reg_num_mask = 0x1f;
2497         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2498
2499 }
2500
2501 static const struct net_device_ops bcm_enetsw_ops = {
2502         .ndo_open               = bcm_enetsw_open,
2503         .ndo_stop               = bcm_enetsw_stop,
2504         .ndo_start_xmit         = bcm_enet_start_xmit,
2505         .ndo_change_mtu         = bcm_enet_change_mtu,
2506         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2507 };
2508
2509
2510 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2511         { "rx_packets", DEV_STAT(rx_packets), -1 },
2512         { "tx_packets", DEV_STAT(tx_packets), -1 },
2513         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2514         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2515         { "rx_errors", DEV_STAT(rx_errors), -1 },
2516         { "tx_errors", DEV_STAT(tx_errors), -1 },
2517         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2518         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2519
2520         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2521         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2522         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2523         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2524         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2525         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2526         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2527         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2528         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2529         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2530           ETHSW_MIB_RX_1024_1522 },
2531         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2532           ETHSW_MIB_RX_1523_2047 },
2533         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2534           ETHSW_MIB_RX_2048_4095 },
2535         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2536           ETHSW_MIB_RX_4096_8191 },
2537         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2538           ETHSW_MIB_RX_8192_9728 },
2539         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2540         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2541         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2542         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2543         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2544
2545         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2546         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2547         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2548         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2549         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2550         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2551
2552 };
2553
2554 #define BCM_ENETSW_STATS_LEN    \
2555         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2556
2557 static void bcm_enetsw_get_strings(struct net_device *netdev,
2558                                    u32 stringset, u8 *data)
2559 {
2560         int i;
2561
2562         switch (stringset) {
2563         case ETH_SS_STATS:
2564                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2565                         memcpy(data + i * ETH_GSTRING_LEN,
2566                                bcm_enetsw_gstrings_stats[i].stat_string,
2567                                ETH_GSTRING_LEN);
2568                 }
2569                 break;
2570         }
2571 }
2572
2573 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2574                                      int string_set)
2575 {
2576         switch (string_set) {
2577         case ETH_SS_STATS:
2578                 return BCM_ENETSW_STATS_LEN;
2579         default:
2580                 return -EINVAL;
2581         }
2582 }
2583
2584 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2585                                    struct ethtool_drvinfo *drvinfo)
2586 {
2587         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2588         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2589         strncpy(drvinfo->fw_version, "N/A", 32);
2590         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2591 }
2592
2593 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2594                                          struct ethtool_stats *stats,
2595                                          u64 *data)
2596 {
2597         struct bcm_enet_priv *priv;
2598         int i;
2599
2600         priv = netdev_priv(netdev);
2601
2602         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2603                 const struct bcm_enet_stats *s;
2604                 u32 lo, hi;
2605                 char *p;
2606                 int reg;
2607
2608                 s = &bcm_enetsw_gstrings_stats[i];
2609
2610                 reg = s->mib_reg;
2611                 if (reg == -1)
2612                         continue;
2613
2614                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2615                 p = (char *)priv + s->stat_offset;
2616
2617                 if (s->sizeof_stat == sizeof(u64)) {
2618                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2619                         *(u64 *)p = ((u64)hi << 32 | lo);
2620                 } else {
2621                         *(u32 *)p = lo;
2622                 }
2623         }
2624
2625         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2626                 const struct bcm_enet_stats *s;
2627                 char *p;
2628
2629                 s = &bcm_enetsw_gstrings_stats[i];
2630
2631                 if (s->mib_reg == -1)
2632                         p = (char *)&netdev->stats + s->stat_offset;
2633                 else
2634                         p = (char *)priv + s->stat_offset;
2635
2636                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2637                         *(u64 *)p : *(u32 *)p;
2638         }
2639 }
2640
2641 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2642                                      struct ethtool_ringparam *ering)
2643 {
2644         struct bcm_enet_priv *priv;
2645
2646         priv = netdev_priv(dev);
2647
2648         /* rx/tx ring is actually only limited by memory */
2649         ering->rx_max_pending = 8192;
2650         ering->tx_max_pending = 8192;
2651         ering->rx_mini_max_pending = 0;
2652         ering->rx_jumbo_max_pending = 0;
2653         ering->rx_pending = priv->rx_ring_size;
2654         ering->tx_pending = priv->tx_ring_size;
2655 }
2656
2657 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2658                                     struct ethtool_ringparam *ering)
2659 {
2660         struct bcm_enet_priv *priv;
2661         int was_running;
2662
2663         priv = netdev_priv(dev);
2664
2665         was_running = 0;
2666         if (netif_running(dev)) {
2667                 bcm_enetsw_stop(dev);
2668                 was_running = 1;
2669         }
2670
2671         priv->rx_ring_size = ering->rx_pending;
2672         priv->tx_ring_size = ering->tx_pending;
2673
2674         if (was_running) {
2675                 int err;
2676
2677                 err = bcm_enetsw_open(dev);
2678                 if (err)
2679                         dev_close(dev);
2680         }
2681         return 0;
2682 }
2683
2684 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2685         .get_strings            = bcm_enetsw_get_strings,
2686         .get_sset_count         = bcm_enetsw_get_sset_count,
2687         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2688         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2689         .get_ringparam          = bcm_enetsw_get_ringparam,
2690         .set_ringparam          = bcm_enetsw_set_ringparam,
2691 };
2692
2693 /* allocate netdevice, request register memory and register device. */
2694 static int bcm_enetsw_probe(struct platform_device *pdev)
2695 {
2696         struct bcm_enet_priv *priv;
2697         struct net_device *dev;
2698         struct bcm63xx_enetsw_platform_data *pd;
2699         struct resource *res_mem;
2700         int ret, irq_rx, irq_tx;
2701
2702         /* stop if shared driver failed, assume driver->probe will be
2703          * called in the same order we register devices (correct ?)
2704          */
2705         if (!bcm_enet_shared_base[0])
2706                 return -ENODEV;
2707
2708         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2709         irq_rx = platform_get_irq(pdev, 0);
2710         irq_tx = platform_get_irq(pdev, 1);
2711         if (!res_mem || irq_rx < 0)
2712                 return -ENODEV;
2713
2714         ret = 0;
2715         dev = alloc_etherdev(sizeof(*priv));
2716         if (!dev)
2717                 return -ENOMEM;
2718         priv = netdev_priv(dev);
2719         memset(priv, 0, sizeof(*priv));
2720
2721         /* initialize default and fetch platform data */
2722         priv->enet_is_sw = true;
2723         priv->irq_rx = irq_rx;
2724         priv->irq_tx = irq_tx;
2725         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2726         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2727         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2728
2729         pd = dev_get_platdata(&pdev->dev);
2730         if (pd) {
2731                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2732                 memcpy(priv->used_ports, pd->used_ports,
2733                        sizeof(pd->used_ports));
2734                 priv->num_ports = pd->num_ports;
2735                 priv->dma_has_sram = pd->dma_has_sram;
2736                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2737                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2738                 priv->dma_chan_width = pd->dma_chan_width;
2739         }
2740
2741         ret = compute_hw_mtu(priv, dev->mtu);
2742         if (ret)
2743                 goto out;
2744
2745         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2746                                 "bcm63xx_enetsw")) {
2747                 ret = -EBUSY;
2748                 goto out;
2749         }
2750
2751         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2752         if (priv->base == NULL) {
2753                 ret = -ENOMEM;
2754                 goto out_release_mem;
2755         }
2756
2757         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2758         if (IS_ERR(priv->mac_clk)) {
2759                 ret = PTR_ERR(priv->mac_clk);
2760                 goto out_unmap;
2761         }
2762         clk_enable(priv->mac_clk);
2763
2764         priv->rx_chan = 0;
2765         priv->tx_chan = 1;
2766         spin_lock_init(&priv->rx_lock);
2767
2768         /* init rx timeout (used for oom) */
2769         init_timer(&priv->rx_timeout);
2770         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2771         priv->rx_timeout.data = (unsigned long)dev;
2772
2773         /* register netdevice */
2774         dev->netdev_ops = &bcm_enetsw_ops;
2775         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2776         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2777         SET_NETDEV_DEV(dev, &pdev->dev);
2778
2779         spin_lock_init(&priv->enetsw_mdio_lock);
2780
2781         ret = register_netdev(dev);
2782         if (ret)
2783                 goto out_put_clk;
2784
2785         netif_carrier_off(dev);
2786         platform_set_drvdata(pdev, dev);
2787         priv->pdev = pdev;
2788         priv->net_dev = dev;
2789
2790         return 0;
2791
2792 out_put_clk:
2793         clk_put(priv->mac_clk);
2794
2795 out_unmap:
2796         iounmap(priv->base);
2797
2798 out_release_mem:
2799         release_mem_region(res_mem->start, resource_size(res_mem));
2800 out:
2801         free_netdev(dev);
2802         return ret;
2803 }
2804
2805
2806 /* exit func, stops hardware and unregisters netdevice */
2807 static int bcm_enetsw_remove(struct platform_device *pdev)
2808 {
2809         struct bcm_enet_priv *priv;
2810         struct net_device *dev;
2811         struct resource *res;
2812
2813         /* stop netdevice */
2814         dev = platform_get_drvdata(pdev);
2815         priv = netdev_priv(dev);
2816         unregister_netdev(dev);
2817
2818         /* release device resources */
2819         iounmap(priv->base);
2820         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2821         release_mem_region(res->start, resource_size(res));
2822
2823         free_netdev(dev);
2824         return 0;
2825 }
2826
2827 struct platform_driver bcm63xx_enetsw_driver = {
2828         .probe  = bcm_enetsw_probe,
2829         .remove = bcm_enetsw_remove,
2830         .driver = {
2831                 .name   = "bcm63xx_enetsw",
2832                 .owner  = THIS_MODULE,
2833         },
2834 };
2835
2836 /* reserve & remap memory space shared between all macs */
2837 static int bcm_enet_shared_probe(struct platform_device *pdev)
2838 {
2839         struct resource *res;
2840         void __iomem *p[3];
2841         unsigned int i;
2842
2843         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2844
2845         for (i = 0; i < 3; i++) {
2846                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2847                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2848                 if (IS_ERR(p[i]))
2849                         return PTR_ERR(p[i]);
2850         }
2851
2852         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2853
2854         return 0;
2855 }
2856
2857 static int bcm_enet_shared_remove(struct platform_device *pdev)
2858 {
2859         return 0;
2860 }
2861
2862 /* this "shared" driver is needed because both macs share a single
2863  * address space
2864  */
2865 struct platform_driver bcm63xx_enet_shared_driver = {
2866         .probe  = bcm_enet_shared_probe,
2867         .remove = bcm_enet_shared_remove,
2868         .driver = {
2869                 .name   = "bcm63xx_enet_shared",
2870                 .owner  = THIS_MODULE,
2871         },
2872 };
2873
2874 static struct platform_driver * const drivers[] = {
2875         &bcm63xx_enet_shared_driver,
2876         &bcm63xx_enet_driver,
2877         &bcm63xx_enetsw_driver,
2878 };
2879
2880 /* entry point */
2881 static int __init bcm_enet_init(void)
2882 {
2883         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2884 }
2885
2886 static void __exit bcm_enet_exit(void)
2887 {
2888         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2889 }
2890
2891
2892 module_init(bcm_enet_init);
2893 module_exit(bcm_enet_exit);
2894
2895 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2896 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2897 MODULE_LICENSE("GPL");