drivers/net/ethernet/broadcom/bcm63xx_enet.c

   1 /*
   2  * Driver for BCM963xx builtin Ethernet mac
   3  *
   4  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/module.h>
  23 #include <linux/clk.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/crc32.h>
  29 #include <linux/err.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/if_vlan.h>
  33
  34 #include <bcm63xx_dev_enet.h>
  35 #include "bcm63xx_enet.h"
  36
  37 static char bcm_enet_driver_name[] = "bcm63xx_enet";
  38 static char bcm_enet_driver_version[] = "1.0";
  39
  40 static int copybreak __read_mostly = 128;
  41 module_param(copybreak, int, 0);
  42 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
  43
  44 /* io registers memory shared between all devices */
  45 static void __iomem *bcm_enet_shared_base[3];
  46
  47 /*
  48  * io helpers to access mac registers
  49  */
  50 static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
  51 {
  52         return bcm_readl(priv->base + off);
  53 }
  54
  55 static inline void enet_writel(struct bcm_enet_priv *priv,
  56                                u32 val, u32 off)
  57 {
  58         bcm_writel(val, priv->base + off);
  59 }
  60
  61 /*
  62  * io helpers to access switch registers
  63  */
  64 static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
  65 {
  66         return bcm_readl(priv->base + off);
  67 }
  68
  69 static inline void enetsw_writel(struct bcm_enet_priv *priv,
  70                                  u32 val, u32 off)
  71 {
  72         bcm_writel(val, priv->base + off);
  73 }
  74
  75 static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
  76 {
  77         return bcm_readw(priv->base + off);
  78 }
  79
  80 static inline void enetsw_writew(struct bcm_enet_priv *priv,
  81                                  u16 val, u32 off)
  82 {
  83         bcm_writew(val, priv->base + off);
  84 }
  85
  86 static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
  87 {
  88         return bcm_readb(priv->base + off);
  89 }
  90
  91 static inline void enetsw_writeb(struct bcm_enet_priv *priv,
  92                                  u8 val, u32 off)
  93 {
  94         bcm_writeb(val, priv->base + off);
  95 }
  96
  97
  98 /* io helpers to access shared registers */
  99 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
 100 {
 101         return bcm_readl(bcm_enet_shared_base[0] + off);
 102 }
 103
 104 static inline void enet_dma_writel(struct bcm_enet_priv *priv,
 105                                        u32 val, u32 off)
 106 {
 107         bcm_writel(val, bcm_enet_shared_base[0] + off);
 108 }
 109
 110 static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 111 {
 112         return bcm_readl(bcm_enet_shared_base[1] +
 113                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 114 }
 115
 116 static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
 117                                        u32 val, u32 off, int chan)
 118 {
 119         bcm_writel(val, bcm_enet_shared_base[1] +
 120                 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
 121 }
 122
 123 static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
 124 {
 125         return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 126 }
 127
 128 static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
 129                                        u32 val, u32 off, int chan)
 130 {
 131         bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
 132 }
 133
 134 /*
 135  * write given data into mii register and wait for transfer to end
 136  * with timeout (average measured transfer time is 25us)
 137  */
 138 static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
 139 {
 140         int limit;
 141
 142         /* make sure mii interrupt status is cleared */
 143         enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
 144
 145         enet_writel(priv, data, ENET_MIIDATA_REG);
 146         wmb();
 147
 148         /* busy wait on mii interrupt bit, with timeout */
 149         limit = 1000;
 150         do {
 151                 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
 152                         break;
 153                 udelay(1);
 154         } while (limit-- > 0);
 155
 156         return (limit < 0) ? 1 : 0;
 157 }
 158
 159 /*
 160  * MII internal read callback
 161  */
 162 static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
 163                               int regnum)
 164 {
 165         u32 tmp, val;
 166
 167         tmp = regnum << ENET_MIIDATA_REG_SHIFT;
 168         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 169         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 170         tmp |= ENET_MIIDATA_OP_READ_MASK;
 171
 172         if (do_mdio_op(priv, tmp))
 173                 return -1;
 174
 175         val = enet_readl(priv, ENET_MIIDATA_REG);
 176         val &= 0xffff;
 177         return val;
 178 }
 179
 180 /*
 181  * MII internal write callback
 182  */
 183 static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
 184                                int regnum, u16 value)
 185 {
 186         u32 tmp;
 187
 188         tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
 189         tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
 190         tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
 191         tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
 192         tmp |= ENET_MIIDATA_OP_WRITE_MASK;
 193
 194         (void)do_mdio_op(priv, tmp);
 195         return 0;
 196 }
 197
 198 /*
 199  * MII read callback from phylib
 200  */
 201 static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
 202                                      int regnum)
 203 {
 204         return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
 205 }
 206
 207 /*
 208  * MII write callback from phylib
 209  */
 210 static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
 211                                       int regnum, u16 value)
 212 {
 213         return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
 214 }
 215
 216 /*
 217  * MII read callback from mii core
 218  */
 219 static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
 220                                   int regnum)
 221 {
 222         return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
 223 }
 224
 225 /*
 226  * MII write callback from mii core
 227  */
 228 static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
 229                                     int regnum, int value)
 230 {
 231         bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
 232 }
 233
 234 /*
 235  * refill rx queue
 236  */
 237 static int bcm_enet_refill_rx(struct net_device *dev)
 238 {
 239         struct bcm_enet_priv *priv;
 240
 241         priv = netdev_priv(dev);
 242
 243         while (priv->rx_desc_count < priv->rx_ring_size) {
 244                 struct bcm_enet_desc *desc;
 245                 struct sk_buff *skb;
 246                 dma_addr_t p;
 247                 int desc_idx;
 248                 u32 len_stat;
 249
 250                 desc_idx = priv->rx_dirty_desc;
 251                 desc = &priv->rx_desc_cpu[desc_idx];
 252
 253                 if (!priv->rx_skb[desc_idx]) {
 254                         skb = netdev_alloc_skb(dev, priv->rx_skb_size);
 255                         if (!skb)
 256                                 break;
 257                         priv->rx_skb[desc_idx] = skb;
 258                         p = dma_map_single(&priv->pdev->dev, skb->data,
 259                                            priv->rx_skb_size,
 260                                            DMA_FROM_DEVICE);
 261                         desc->address = p;
 262                 }
 263
 264                 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
 265                 len_stat |= DMADESC_OWNER_MASK;
 266                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 267                         len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 268                         priv->rx_dirty_desc = 0;
 269                 } else {
 270                         priv->rx_dirty_desc++;
 271                 }
 272                 wmb();
 273                 desc->len_stat = len_stat;
 274
 275                 priv->rx_desc_count++;
 276
 277                 /* tell dma engine we allocated one buffer */
 278                 if (priv->dma_has_sram)
 279                         enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
 280                 else
 281                         enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
 282         }
 283
 284         /* If rx ring is still empty, set a timer to try allocating
 285          * again at a later time. */
 286         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 287                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 288                 priv->rx_timeout.expires = jiffies + HZ;
 289                 add_timer(&priv->rx_timeout);
 290         }
 291
 292         return 0;
 293 }
 294
 295 /*
 296  * timer callback to defer refill rx queue in case we're OOM
 297  */
 298 static void bcm_enet_refill_rx_timer(unsigned long data)
 299 {
 300         struct net_device *dev;
 301         struct bcm_enet_priv *priv;
 302
 303         dev = (struct net_device *)data;
 304         priv = netdev_priv(dev);
 305
 306         spin_lock(&priv->rx_lock);
 307         bcm_enet_refill_rx((struct net_device *)data);
 308         spin_unlock(&priv->rx_lock);
 309 }
 310
 311 /*
 312  * extract packet from rx queue
 313  */
 314 static int bcm_enet_receive_queue(struct net_device *dev, int budget)
 315 {
 316         struct bcm_enet_priv *priv;
 317         struct device *kdev;
 318         int processed;
 319
 320         priv = netdev_priv(dev);
 321         kdev = &priv->pdev->dev;
 322         processed = 0;
 323
 324         /* don't scan ring further than number of refilled
 325          * descriptor */
 326         if (budget > priv->rx_desc_count)
 327                 budget = priv->rx_desc_count;
 328
 329         do {
 330                 struct bcm_enet_desc *desc;
 331                 struct sk_buff *skb;
 332                 int desc_idx;
 333                 u32 len_stat;
 334                 unsigned int len;
 335
 336                 desc_idx = priv->rx_curr_desc;
 337                 desc = &priv->rx_desc_cpu[desc_idx];
 338
 339                 /* make sure we actually read the descriptor status at
 340                  * each loop */
 341                 rmb();
 342
 343                 len_stat = desc->len_stat;
 344
 345                 /* break if dma ownership belongs to hw */
 346                 if (len_stat & DMADESC_OWNER_MASK)
 347                         break;
 348
 349                 processed++;
 350                 priv->rx_curr_desc++;
 351                 if (priv->rx_curr_desc == priv->rx_ring_size)
 352                         priv->rx_curr_desc = 0;
 353                 priv->rx_desc_count--;
 354
 355                 /* if the packet does not have start of packet _and_
 356                  * end of packet flag set, then just recycle it */
 357                 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
 358                         (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
 359                         dev->stats.rx_dropped++;
 360                         continue;
 361                 }
 362
 363                 /* recycle packet if it's marked as bad */
 364                 if (!priv->enet_is_sw &&
 365                     unlikely(len_stat & DMADESC_ERR_MASK)) {
 366                         dev->stats.rx_errors++;
 367
 368                         if (len_stat & DMADESC_OVSIZE_MASK)
 369                                 dev->stats.rx_length_errors++;
 370                         if (len_stat & DMADESC_CRC_MASK)
 371                                 dev->stats.rx_crc_errors++;
 372                         if (len_stat & DMADESC_UNDER_MASK)
 373                                 dev->stats.rx_frame_errors++;
 374                         if (len_stat & DMADESC_OV_MASK)
 375                                 dev->stats.rx_fifo_errors++;
 376                         continue;
 377                 }
 378
 379                 /* valid packet */
 380                 skb = priv->rx_skb[desc_idx];
 381                 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
 382                 /* don't include FCS */
 383                 len -= 4;
 384
 385                 if (len < copybreak) {
 386                         struct sk_buff *nskb;
 387
 388                         nskb = napi_alloc_skb(&priv->napi, len);
 389                         if (!nskb) {
 390                                 /* forget packet, just rearm desc */
 391                                 dev->stats.rx_dropped++;
 392                                 continue;
 393                         }
 394
 395                         dma_sync_single_for_cpu(kdev, desc->address,
 396                                                 len, DMA_FROM_DEVICE);
 397                         memcpy(nskb->data, skb->data, len);
 398                         dma_sync_single_for_device(kdev, desc->address,
 399                                                    len, DMA_FROM_DEVICE);
 400                         skb = nskb;
 401                 } else {
 402                         dma_unmap_single(&priv->pdev->dev, desc->address,
 403                                          priv->rx_skb_size, DMA_FROM_DEVICE);
 404                         priv->rx_skb[desc_idx] = NULL;
 405                 }
 406
 407                 skb_put(skb, len);
 408                 skb->protocol = eth_type_trans(skb, dev);
 409                 dev->stats.rx_packets++;
 410                 dev->stats.rx_bytes += len;
 411                 netif_receive_skb(skb);
 412
 413         } while (--budget > 0);
 414
 415         if (processed || !priv->rx_desc_count) {
 416                 bcm_enet_refill_rx(dev);
 417
 418                 /* kick rx dma */
 419                 enet_dmac_writel(priv, priv->dma_chan_en_mask,
 420                                          ENETDMAC_CHANCFG, priv->rx_chan);
 421         }
 422
 423         return processed;
 424 }
 425
 426
 427 /*
 428  * try to or force reclaim of transmitted buffers
 429  */
 430 static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
 431 {
 432         struct bcm_enet_priv *priv;
 433         int released;
 434
 435         priv = netdev_priv(dev);
 436         released = 0;
 437
 438         while (priv->tx_desc_count < priv->tx_ring_size) {
 439                 struct bcm_enet_desc *desc;
 440                 struct sk_buff *skb;
 441
 442                 /* We run in a bh and fight against start_xmit, which
 443                  * is called with bh disabled  */
 444                 spin_lock(&priv->tx_lock);
 445
 446                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 447
 448                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 449                         spin_unlock(&priv->tx_lock);
 450                         break;
 451                 }
 452
 453                 /* ensure other field of the descriptor were not read
 454                  * before we checked ownership */
 455                 rmb();
 456
 457                 skb = priv->tx_skb[priv->tx_dirty_desc];
 458                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 459                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 460                                  DMA_TO_DEVICE);
 461
 462                 priv->tx_dirty_desc++;
 463                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 464                         priv->tx_dirty_desc = 0;
 465                 priv->tx_desc_count++;
 466
 467                 spin_unlock(&priv->tx_lock);
 468
 469                 if (desc->len_stat & DMADESC_UNDER_MASK)
 470                         dev->stats.tx_errors++;
 471
 472                 dev_kfree_skb(skb);
 473                 released++;
 474         }
 475
 476         if (netif_queue_stopped(dev) && released)
 477                 netif_wake_queue(dev);
 478
 479         return released;
 480 }
 481
 482 /*
 483  * poll func, called by network core
 484  */
 485 static int bcm_enet_poll(struct napi_struct *napi, int budget)
 486 {
 487         struct bcm_enet_priv *priv;
 488         struct net_device *dev;
 489         int rx_work_done;
 490
 491         priv = container_of(napi, struct bcm_enet_priv, napi);
 492         dev = priv->net_dev;
 493
 494         /* ack interrupts */
 495         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 496                          ENETDMAC_IR, priv->rx_chan);
 497         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 498                          ENETDMAC_IR, priv->tx_chan);
 499
 500         /* reclaim sent skb */
 501         bcm_enet_tx_reclaim(dev, 0);
 502
 503         spin_lock(&priv->rx_lock);
 504         rx_work_done = bcm_enet_receive_queue(dev, budget);
 505         spin_unlock(&priv->rx_lock);
 506
 507         if (rx_work_done >= budget) {
 508                 /* rx queue is not yet empty/clean */
 509                 return rx_work_done;
 510         }
 511
 512         /* no more packet in rx/tx queue, remove device from poll
 513          * queue */
 514         napi_complete(napi);
 515
 516         /* restore rx/tx interrupt */
 517         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 518                          ENETDMAC_IRMASK, priv->rx_chan);
 519         enet_dmac_writel(priv, priv->dma_chan_int_mask,
 520                          ENETDMAC_IRMASK, priv->tx_chan);
 521
 522         return rx_work_done;
 523 }
 524
 525 /*
 526  * mac interrupt handler
 527  */
 528 static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
 529 {
 530         struct net_device *dev;
 531         struct bcm_enet_priv *priv;
 532         u32 stat;
 533
 534         dev = dev_id;
 535         priv = netdev_priv(dev);
 536
 537         stat = enet_readl(priv, ENET_IR_REG);
 538         if (!(stat & ENET_IR_MIB))
 539                 return IRQ_NONE;
 540
 541         /* clear & mask interrupt */
 542         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
 543         enet_writel(priv, 0, ENET_IRMASK_REG);
 544
 545         /* read mib registers in workqueue */
 546         schedule_work(&priv->mib_update_task);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 /*
 552  * rx/tx dma interrupt handler
 553  */
 554 static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
 555 {
 556         struct net_device *dev;
 557         struct bcm_enet_priv *priv;
 558
 559         dev = dev_id;
 560         priv = netdev_priv(dev);
 561
 562         /* mask rx/tx interrupts */
 563         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 564         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 565
 566         napi_schedule(&priv->napi);
 567
 568         return IRQ_HANDLED;
 569 }
 570
 571 /*
 572  * tx request callback
 573  */
 574 static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 575 {
 576         struct bcm_enet_priv *priv;
 577         struct bcm_enet_desc *desc;
 578         u32 len_stat;
 579         int ret;
 580
 581         priv = netdev_priv(dev);
 582
 583         /* lock against tx reclaim */
 584         spin_lock(&priv->tx_lock);
 585
 586         /* make sure  the tx hw queue  is not full,  should not happen
 587          * since we stop queue before it's the case */
 588         if (unlikely(!priv->tx_desc_count)) {
 589                 netif_stop_queue(dev);
 590                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 591                         "available?\n");
 592                 ret = NETDEV_TX_BUSY;
 593                 goto out_unlock;
 594         }
 595
 596         /* pad small packets sent on a switch device */
 597         if (priv->enet_is_sw && skb->len < 64) {
 598                 int needed = 64 - skb->len;
 599                 char *data;
 600
 601                 if (unlikely(skb_tailroom(skb) < needed)) {
 602                         struct sk_buff *nskb;
 603
 604                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 605                         if (!nskb) {
 606                                 ret = NETDEV_TX_BUSY;
 607                                 goto out_unlock;
 608                         }
 609                         dev_kfree_skb(skb);
 610                         skb = nskb;
 611                 }
 612                 data = skb_put(skb, needed);
 613                 memset(data, 0, needed);
 614         }
 615
 616         /* point to the next available desc */
 617         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 618         priv->tx_skb[priv->tx_curr_desc] = skb;
 619
 620         /* fill descriptor */
 621         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 622                                        DMA_TO_DEVICE);
 623
 624         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 625         len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
 626                 DMADESC_APPEND_CRC |
 627                 DMADESC_OWNER_MASK;
 628
 629         priv->tx_curr_desc++;
 630         if (priv->tx_curr_desc == priv->tx_ring_size) {
 631                 priv->tx_curr_desc = 0;
 632                 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
 633         }
 634         priv->tx_desc_count--;
 635
 636         /* dma might be already polling, make sure we update desc
 637          * fields in correct order */
 638         wmb();
 639         desc->len_stat = len_stat;
 640         wmb();
 641
 642         /* kick tx dma */
 643         enet_dmac_writel(priv, priv->dma_chan_en_mask,
 644                                  ENETDMAC_CHANCFG, priv->tx_chan);
 645
 646         /* stop queue if no more desc available */
 647         if (!priv->tx_desc_count)
 648                 netif_stop_queue(dev);
 649
 650         dev->stats.tx_bytes += skb->len;
 651         dev->stats.tx_packets++;
 652         ret = NETDEV_TX_OK;
 653
 654 out_unlock:
 655         spin_unlock(&priv->tx_lock);
 656         return ret;
 657 }
 658
 659 /*
 660  * Change the interface's mac address.
 661  */
 662 static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
 663 {
 664         struct bcm_enet_priv *priv;
 665         struct sockaddr *addr = p;
 666         u32 val;
 667
 668         priv = netdev_priv(dev);
 669         memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 670
 671         /* use perfect match register 0 to store my mac address */
 672         val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
 673                 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
 674         enet_writel(priv, val, ENET_PML_REG(0));
 675
 676         val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
 677         val |= ENET_PMH_DATAVALID_MASK;
 678         enet_writel(priv, val, ENET_PMH_REG(0));
 679
 680         return 0;
 681 }
 682
 683 /*
 684  * Change rx mode (promiscuous/allmulti) and update multicast list
 685  */
 686 static void bcm_enet_set_multicast_list(struct net_device *dev)
 687 {
 688         struct bcm_enet_priv *priv;
 689         struct netdev_hw_addr *ha;
 690         u32 val;
 691         int i;
 692
 693         priv = netdev_priv(dev);
 694
 695         val = enet_readl(priv, ENET_RXCFG_REG);
 696
 697         if (dev->flags & IFF_PROMISC)
 698                 val |= ENET_RXCFG_PROMISC_MASK;
 699         else
 700                 val &= ~ENET_RXCFG_PROMISC_MASK;
 701
 702         /* only 3 perfect match registers left, first one is used for
 703          * own mac address */
 704         if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
 705                 val |= ENET_RXCFG_ALLMCAST_MASK;
 706         else
 707                 val &= ~ENET_RXCFG_ALLMCAST_MASK;
 708
 709         /* no need to set perfect match registers if we catch all
 710          * multicast */
 711         if (val & ENET_RXCFG_ALLMCAST_MASK) {
 712                 enet_writel(priv, val, ENET_RXCFG_REG);
 713                 return;
 714         }
 715
 716         i = 0;
 717         netdev_for_each_mc_addr(ha, dev) {
 718                 u8 *dmi_addr;
 719                 u32 tmp;
 720
 721                 if (i == 3)
 722                         break;
 723                 /* update perfect match registers */
 724                 dmi_addr = ha->addr;
 725                 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
 726                         (dmi_addr[4] << 8) | dmi_addr[5];
 727                 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
 728
 729                 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
 730                 tmp |= ENET_PMH_DATAVALID_MASK;
 731                 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
 732         }
 733
 734         for (; i < 3; i++) {
 735                 enet_writel(priv, 0, ENET_PML_REG(i + 1));
 736                 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
 737         }
 738
 739         enet_writel(priv, val, ENET_RXCFG_REG);
 740 }
 741
 742 /*
 743  * set mac duplex parameters
 744  */
 745 static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
 746 {
 747         u32 val;
 748
 749         val = enet_readl(priv, ENET_TXCTL_REG);
 750         if (fullduplex)
 751                 val |= ENET_TXCTL_FD_MASK;
 752         else
 753                 val &= ~ENET_TXCTL_FD_MASK;
 754         enet_writel(priv, val, ENET_TXCTL_REG);
 755 }
 756
 757 /*
 758  * set mac flow control parameters
 759  */
 760 static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
 761 {
 762         u32 val;
 763
 764         /* rx flow control (pause frame handling) */
 765         val = enet_readl(priv, ENET_RXCFG_REG);
 766         if (rx_en)
 767                 val |= ENET_RXCFG_ENFLOW_MASK;
 768         else
 769                 val &= ~ENET_RXCFG_ENFLOW_MASK;
 770         enet_writel(priv, val, ENET_RXCFG_REG);
 771
 772         if (!priv->dma_has_sram)
 773                 return;
 774
 775         /* tx flow control (pause frame generation) */
 776         val = enet_dma_readl(priv, ENETDMA_CFG_REG);
 777         if (tx_en)
 778                 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 779         else
 780                 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
 781         enet_dma_writel(priv, val, ENETDMA_CFG_REG);
 782 }
 783
 784 /*
 785  * link changed callback (from phylib)
 786  */
 787 static void bcm_enet_adjust_phy_link(struct net_device *dev)
 788 {
 789         struct bcm_enet_priv *priv;
 790         struct phy_device *phydev;
 791         int status_changed;
 792
 793         priv = netdev_priv(dev);
 794         phydev = priv->phydev;
 795         status_changed = 0;
 796
 797         if (priv->old_link != phydev->link) {
 798                 status_changed = 1;
 799                 priv->old_link = phydev->link;
 800         }
 801
 802         /* reflect duplex change in mac configuration */
 803         if (phydev->link && phydev->duplex != priv->old_duplex) {
 804                 bcm_enet_set_duplex(priv,
 805                                     (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
 806                 status_changed = 1;
 807                 priv->old_duplex = phydev->duplex;
 808         }
 809
 810         /* enable flow control if remote advertise it (trust phylib to
 811          * check that duplex is full */
 812         if (phydev->link && phydev->pause != priv->old_pause) {
 813                 int rx_pause_en, tx_pause_en;
 814
 815                 if (phydev->pause) {
 816                         /* pause was advertised by lpa and us */
 817                         rx_pause_en = 1;
 818                         tx_pause_en = 1;
 819                 } else if (!priv->pause_auto) {
 820                         /* pause setting overrided by user */
 821                         rx_pause_en = priv->pause_rx;
 822                         tx_pause_en = priv->pause_tx;
 823                 } else {
 824                         rx_pause_en = 0;
 825                         tx_pause_en = 0;
 826                 }
 827
 828                 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
 829                 status_changed = 1;
 830                 priv->old_pause = phydev->pause;
 831         }
 832
 833         if (status_changed) {
 834                 pr_info("%s: link %s", dev->name, phydev->link ?
 835                         "UP" : "DOWN");
 836                 if (phydev->link)
 837                         pr_cont(" - %d/%s - flow control %s", phydev->speed,
 838                                DUPLEX_FULL == phydev->duplex ? "full" : "half",
 839                                phydev->pause == 1 ? "rx&tx" : "off");
 840
 841                 pr_cont("\n");
 842         }
 843 }
 844
 845 /*
 846  * link changed callback (if phylib is not used)
 847  */
 848 static void bcm_enet_adjust_link(struct net_device *dev)
 849 {
 850         struct bcm_enet_priv *priv;
 851
 852         priv = netdev_priv(dev);
 853         bcm_enet_set_duplex(priv, priv->force_duplex_full);
 854         bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
 855         netif_carrier_on(dev);
 856
 857         pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
 858                 dev->name,
 859                 priv->force_speed_100 ? 100 : 10,
 860                 priv->force_duplex_full ? "full" : "half",
 861                 priv->pause_rx ? "rx" : "off",
 862                 priv->pause_tx ? "tx" : "off");
 863 }
 864
 865 /*
 866  * open callback, allocate dma rings & buffers and start rx operation
 867  */
 868 static int bcm_enet_open(struct net_device *dev)
 869 {
 870         struct bcm_enet_priv *priv;
 871         struct sockaddr addr;
 872         struct device *kdev;
 873         struct phy_device *phydev;
 874         int i, ret;
 875         unsigned int size;
 876         char phy_id[MII_BUS_ID_SIZE + 3];
 877         void *p;
 878         u32 val;
 879
 880         priv = netdev_priv(dev);
 881         kdev = &priv->pdev->dev;
 882
 883         if (priv->has_phy) {
 884                 /* connect to PHY */
 885                 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
 886                          priv->mii_bus->id, priv->phy_id);
 887
 888                 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
 889                                      PHY_INTERFACE_MODE_MII);
 890
 891                 if (IS_ERR(phydev)) {
 892                         dev_err(kdev, "could not attach to PHY\n");
 893                         return PTR_ERR(phydev);
 894                 }
 895
 896                 /* mask with MAC supported features */
 897                 phydev->supported &= (SUPPORTED_10baseT_Half |
 898                                       SUPPORTED_10baseT_Full |
 899                                       SUPPORTED_100baseT_Half |
 900                                       SUPPORTED_100baseT_Full |
 901                                       SUPPORTED_Autoneg |
 902                                       SUPPORTED_Pause |
 903                                       SUPPORTED_MII);
 904                 phydev->advertising = phydev->supported;
 905
 906                 if (priv->pause_auto && priv->pause_rx && priv->pause_tx)
 907                         phydev->advertising |= SUPPORTED_Pause;
 908                 else
 909                         phydev->advertising &= ~SUPPORTED_Pause;
 910
 911                 phy_attached_info(phydev);
 912
 913                 priv->old_link = 0;
 914                 priv->old_duplex = -1;
 915                 priv->old_pause = -1;
 916                 priv->phydev = phydev;
 917         }
 918
 919         /* mask all interrupts and request them */
 920         enet_writel(priv, 0, ENET_IRMASK_REG);
 921         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
 922         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
 923
 924         ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
 925         if (ret)
 926                 goto out_phy_disconnect;
 927
 928         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
 929                           dev->name, dev);
 930         if (ret)
 931                 goto out_freeirq;
 932
 933         ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
 934                           0, dev->name, dev);
 935         if (ret)
 936                 goto out_freeirq_rx;
 937
 938         /* initialize perfect match registers */
 939         for (i = 0; i < 4; i++) {
 940                 enet_writel(priv, 0, ENET_PML_REG(i));
 941                 enet_writel(priv, 0, ENET_PMH_REG(i));
 942         }
 943
 944         /* write device mac address */
 945         memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
 946         bcm_enet_set_mac_address(dev, &addr);
 947
 948         /* allocate rx dma ring */
 949         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
 950         p = dma_zalloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 951         if (!p) {
 952                 ret = -ENOMEM;
 953                 goto out_freeirq_tx;
 954         }
 955
 956         priv->rx_desc_alloc_size = size;
 957         priv->rx_desc_cpu = p;
 958
 959         /* allocate tx dma ring */
 960         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
 961         p = dma_zalloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 962         if (!p) {
 963                 ret = -ENOMEM;
 964                 goto out_free_rx_ring;
 965         }
 966
 967         priv->tx_desc_alloc_size = size;
 968         priv->tx_desc_cpu = p;
 969
 970         priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
 971                                GFP_KERNEL);
 972         if (!priv->tx_skb) {
 973                 ret = -ENOMEM;
 974                 goto out_free_tx_ring;
 975         }
 976
 977         priv->tx_desc_count = priv->tx_ring_size;
 978         priv->tx_dirty_desc = 0;
 979         priv->tx_curr_desc = 0;
 980         spin_lock_init(&priv->tx_lock);
 981
 982         /* init & fill rx ring with skbs */
 983         priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
 984                                GFP_KERNEL);
 985         if (!priv->rx_skb) {
 986                 ret = -ENOMEM;
 987                 goto out_free_tx_skb;
 988         }
 989
 990         priv->rx_desc_count = 0;
 991         priv->rx_dirty_desc = 0;
 992         priv->rx_curr_desc = 0;
 993
 994         /* initialize flow control buffer allocation */
 995         if (priv->dma_has_sram)
 996                 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
 997                                 ENETDMA_BUFALLOC_REG(priv->rx_chan));
 998         else
 999                 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
1000                                 ENETDMAC_BUFALLOC, priv->rx_chan);
1001
1002         if (bcm_enet_refill_rx(dev)) {
1003                 dev_err(kdev, "cannot allocate rx skb queue\n");
1004                 ret = -ENOMEM;
1005                 goto out;
1006         }
1007
1008         /* write rx & tx ring addresses */
1009         if (priv->dma_has_sram) {
1010                 enet_dmas_writel(priv, priv->rx_desc_dma,
1011                                  ENETDMAS_RSTART_REG, priv->rx_chan);
1012                 enet_dmas_writel(priv, priv->tx_desc_dma,
1013                          ENETDMAS_RSTART_REG, priv->tx_chan);
1014         } else {
1015                 enet_dmac_writel(priv, priv->rx_desc_dma,
1016                                 ENETDMAC_RSTART, priv->rx_chan);
1017                 enet_dmac_writel(priv, priv->tx_desc_dma,
1018                                 ENETDMAC_RSTART, priv->tx_chan);
1019         }
1020
1021         /* clear remaining state ram for rx & tx channel */
1022         if (priv->dma_has_sram) {
1023                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1024                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1025                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1026                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1027                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1028                 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1029         } else {
1030                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1031                 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1032         }
1033
1034         /* set max rx/tx length */
1035         enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1036         enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1037
1038         /* set dma maximum burst len */
1039         enet_dmac_writel(priv, priv->dma_maxburst,
1040                          ENETDMAC_MAXBURST, priv->rx_chan);
1041         enet_dmac_writel(priv, priv->dma_maxburst,
1042                          ENETDMAC_MAXBURST, priv->tx_chan);
1043
1044         /* set correct transmit fifo watermark */
1045         enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1046
1047         /* set flow control low/high threshold to 1/3 / 2/3 */
1048         if (priv->dma_has_sram) {
1049                 val = priv->rx_ring_size / 3;
1050                 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1051                 val = (priv->rx_ring_size * 2) / 3;
1052                 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1053         } else {
1054                 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1055                 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1056                 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1057         }
1058
1059         /* all set, enable mac and interrupts, start dma engine and
1060          * kick rx dma channel */
1061         wmb();
1062         val = enet_readl(priv, ENET_CTL_REG);
1063         val |= ENET_CTL_ENABLE_MASK;
1064         enet_writel(priv, val, ENET_CTL_REG);
1065         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1066         enet_dmac_writel(priv, priv->dma_chan_en_mask,
1067                          ENETDMAC_CHANCFG, priv->rx_chan);
1068
1069         /* watch "mib counters about to overflow" interrupt */
1070         enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1071         enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1072
1073         /* watch "packet transferred" interrupt in rx and tx */
1074         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1075                          ENETDMAC_IR, priv->rx_chan);
1076         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1077                          ENETDMAC_IR, priv->tx_chan);
1078
1079         /* make sure we enable napi before rx interrupt  */
1080         napi_enable(&priv->napi);
1081
1082         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1083                          ENETDMAC_IRMASK, priv->rx_chan);
1084         enet_dmac_writel(priv, priv->dma_chan_int_mask,
1085                          ENETDMAC_IRMASK, priv->tx_chan);
1086
1087         if (priv->has_phy)
1088                 phy_start(priv->phydev);
1089         else
1090                 bcm_enet_adjust_link(dev);
1091
1092         netif_start_queue(dev);
1093         return 0;
1094
1095 out:
1096         for (i = 0; i < priv->rx_ring_size; i++) {
1097                 struct bcm_enet_desc *desc;
1098
1099                 if (!priv->rx_skb[i])
1100                         continue;
1101
1102                 desc = &priv->rx_desc_cpu[i];
1103                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1104                                  DMA_FROM_DEVICE);
1105                 kfree_skb(priv->rx_skb[i]);
1106         }
1107         kfree(priv->rx_skb);
1108
1109 out_free_tx_skb:
1110         kfree(priv->tx_skb);
1111
1112 out_free_tx_ring:
1113         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1114                           priv->tx_desc_cpu, priv->tx_desc_dma);
1115
1116 out_free_rx_ring:
1117         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1118                           priv->rx_desc_cpu, priv->rx_desc_dma);
1119
1120 out_freeirq_tx:
1121         free_irq(priv->irq_tx, dev);
1122
1123 out_freeirq_rx:
1124         free_irq(priv->irq_rx, dev);
1125
1126 out_freeirq:
1127         free_irq(dev->irq, dev);
1128
1129 out_phy_disconnect:
1130         phy_disconnect(priv->phydev);
1131
1132         return ret;
1133 }
1134
1135 /*
1136  * disable mac
1137  */
1138 static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1139 {
1140         int limit;
1141         u32 val;
1142
1143         val = enet_readl(priv, ENET_CTL_REG);
1144         val |= ENET_CTL_DISABLE_MASK;
1145         enet_writel(priv, val, ENET_CTL_REG);
1146
1147         limit = 1000;
1148         do {
1149                 u32 val;
1150
1151                 val = enet_readl(priv, ENET_CTL_REG);
1152                 if (!(val & ENET_CTL_DISABLE_MASK))
1153                         break;
1154                 udelay(1);
1155         } while (limit--);
1156 }
1157
1158 /*
1159  * disable dma in given channel
1160  */
1161 static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1162 {
1163         int limit;
1164
1165         enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1166
1167         limit = 1000;
1168         do {
1169                 u32 val;
1170
1171                 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1172                 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1173                         break;
1174                 udelay(1);
1175         } while (limit--);
1176 }
1177
1178 /*
1179  * stop callback
1180  */
1181 static int bcm_enet_stop(struct net_device *dev)
1182 {
1183         struct bcm_enet_priv *priv;
1184         struct device *kdev;
1185         int i;
1186
1187         priv = netdev_priv(dev);
1188         kdev = &priv->pdev->dev;
1189
1190         netif_stop_queue(dev);
1191         napi_disable(&priv->napi);
1192         if (priv->has_phy)
1193                 phy_stop(priv->phydev);
1194         del_timer_sync(&priv->rx_timeout);
1195
1196         /* mask all interrupts */
1197         enet_writel(priv, 0, ENET_IRMASK_REG);
1198         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1199         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1200
1201         /* make sure no mib update is scheduled */
1202         cancel_work_sync(&priv->mib_update_task);
1203
1204         /* disable dma & mac */
1205         bcm_enet_disable_dma(priv, priv->tx_chan);
1206         bcm_enet_disable_dma(priv, priv->rx_chan);
1207         bcm_enet_disable_mac(priv);
1208
1209         /* force reclaim of all tx buffers */
1210         bcm_enet_tx_reclaim(dev, 1);
1211
1212         /* free the rx skb ring */
1213         for (i = 0; i < priv->rx_ring_size; i++) {
1214                 struct bcm_enet_desc *desc;
1215
1216                 if (!priv->rx_skb[i])
1217                         continue;
1218
1219                 desc = &priv->rx_desc_cpu[i];
1220                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1221                                  DMA_FROM_DEVICE);
1222                 kfree_skb(priv->rx_skb[i]);
1223         }
1224
1225         /* free remaining allocated memory */
1226         kfree(priv->rx_skb);
1227         kfree(priv->tx_skb);
1228         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1229                           priv->rx_desc_cpu, priv->rx_desc_dma);
1230         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1231                           priv->tx_desc_cpu, priv->tx_desc_dma);
1232         free_irq(priv->irq_tx, dev);
1233         free_irq(priv->irq_rx, dev);
1234         free_irq(dev->irq, dev);
1235
1236         /* release phy */
1237         if (priv->has_phy) {
1238                 phy_disconnect(priv->phydev);
1239                 priv->phydev = NULL;
1240         }
1241
1242         return 0;
1243 }
1244
1245 /*
1246  * ethtool callbacks
1247  */
1248 struct bcm_enet_stats {
1249         char stat_string[ETH_GSTRING_LEN];
1250         int sizeof_stat;
1251         int stat_offset;
1252         int mib_reg;
1253 };
1254
1255 #define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m),             \
1256                      offsetof(struct bcm_enet_priv, m)
1257 #define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m),          \
1258                      offsetof(struct net_device_stats, m)
1259
1260 static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1261         { "rx_packets", DEV_STAT(rx_packets), -1 },
1262         { "tx_packets", DEV_STAT(tx_packets), -1 },
1263         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1264         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1265         { "rx_errors", DEV_STAT(rx_errors), -1 },
1266         { "tx_errors", DEV_STAT(tx_errors), -1 },
1267         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1268         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1269
1270         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1271         { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1272         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1273         { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1274         { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1275         { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1276         { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1277         { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1278         { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1279         { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1280         { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1281         { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1282         { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1283         { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1284         { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1285         { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1286         { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1287         { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1288         { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1289         { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1290         { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1291
1292         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1293         { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1294         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1295         { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1296         { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1297         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1298         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1299         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1300         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1301         { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1302         { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1303         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1304         { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1305         { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1306         { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1307         { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1308         { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1309         { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1310         { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1311         { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1312         { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1313         { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1314
1315 };
1316
1317 #define BCM_ENET_STATS_LEN      ARRAY_SIZE(bcm_enet_gstrings_stats)
1318
1319 static const u32 unused_mib_regs[] = {
1320         ETH_MIB_TX_ALL_OCTETS,
1321         ETH_MIB_TX_ALL_PKTS,
1322         ETH_MIB_RX_ALL_OCTETS,
1323         ETH_MIB_RX_ALL_PKTS,
1324 };
1325
1326
1327 static void bcm_enet_get_drvinfo(struct net_device *netdev,
1328                                  struct ethtool_drvinfo *drvinfo)
1329 {
1330         strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1331         strlcpy(drvinfo->version, bcm_enet_driver_version,
1332                 sizeof(drvinfo->version));
1333         strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1334         strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1335 }
1336
1337 static int bcm_enet_get_sset_count(struct net_device *netdev,
1338                                         int string_set)
1339 {
1340         switch (string_set) {
1341         case ETH_SS_STATS:
1342                 return BCM_ENET_STATS_LEN;
1343         default:
1344                 return -EINVAL;
1345         }
1346 }
1347
1348 static void bcm_enet_get_strings(struct net_device *netdev,
1349                                  u32 stringset, u8 *data)
1350 {
1351         int i;
1352
1353         switch (stringset) {
1354         case ETH_SS_STATS:
1355                 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1356                         memcpy(data + i * ETH_GSTRING_LEN,
1357                                bcm_enet_gstrings_stats[i].stat_string,
1358                                ETH_GSTRING_LEN);
1359                 }
1360                 break;
1361         }
1362 }
1363
1364 static void update_mib_counters(struct bcm_enet_priv *priv)
1365 {
1366         int i;
1367
1368         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1369                 const struct bcm_enet_stats *s;
1370                 u32 val;
1371                 char *p;
1372
1373                 s = &bcm_enet_gstrings_stats[i];
1374                 if (s->mib_reg == -1)
1375                         continue;
1376
1377                 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1378                 p = (char *)priv + s->stat_offset;
1379
1380                 if (s->sizeof_stat == sizeof(u64))
1381                         *(u64 *)p += val;
1382                 else
1383                         *(u32 *)p += val;
1384         }
1385
1386         /* also empty unused mib counters to make sure mib counter
1387          * overflow interrupt is cleared */
1388         for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1389                 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1390 }
1391
1392 static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1393 {
1394         struct bcm_enet_priv *priv;
1395
1396         priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1397         mutex_lock(&priv->mib_update_lock);
1398         update_mib_counters(priv);
1399         mutex_unlock(&priv->mib_update_lock);
1400
1401         /* reenable mib interrupt */
1402         if (netif_running(priv->net_dev))
1403                 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1404 }
1405
1406 static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1407                                        struct ethtool_stats *stats,
1408                                        u64 *data)
1409 {
1410         struct bcm_enet_priv *priv;
1411         int i;
1412
1413         priv = netdev_priv(netdev);
1414
1415         mutex_lock(&priv->mib_update_lock);
1416         update_mib_counters(priv);
1417
1418         for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1419                 const struct bcm_enet_stats *s;
1420                 char *p;
1421
1422                 s = &bcm_enet_gstrings_stats[i];
1423                 if (s->mib_reg == -1)
1424                         p = (char *)&netdev->stats;
1425                 else
1426                         p = (char *)priv;
1427                 p += s->stat_offset;
1428                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1429                         *(u64 *)p : *(u32 *)p;
1430         }
1431         mutex_unlock(&priv->mib_update_lock);
1432 }
1433
1434 static int bcm_enet_nway_reset(struct net_device *dev)
1435 {
1436         struct bcm_enet_priv *priv;
1437
1438         priv = netdev_priv(dev);
1439         if (priv->has_phy) {
1440                 if (!priv->phydev)
1441                         return -ENODEV;
1442                 return genphy_restart_aneg(priv->phydev);
1443         }
1444
1445         return -EOPNOTSUPP;
1446 }
1447
1448 static int bcm_enet_get_settings(struct net_device *dev,
1449                                  struct ethtool_cmd *cmd)
1450 {
1451         struct bcm_enet_priv *priv;
1452
1453         priv = netdev_priv(dev);
1454
1455         cmd->maxrxpkt = 0;
1456         cmd->maxtxpkt = 0;
1457
1458         if (priv->has_phy) {
1459                 if (!priv->phydev)
1460                         return -ENODEV;
1461                 return phy_ethtool_gset(priv->phydev, cmd);
1462         } else {
1463                 cmd->autoneg = 0;
1464                 ethtool_cmd_speed_set(cmd, ((priv->force_speed_100)
1465                                             ? SPEED_100 : SPEED_10));
1466                 cmd->duplex = (priv->force_duplex_full) ?
1467                         DUPLEX_FULL : DUPLEX_HALF;
1468                 cmd->supported = ADVERTISED_10baseT_Half  |
1469                         ADVERTISED_10baseT_Full |
1470                         ADVERTISED_100baseT_Half |
1471                         ADVERTISED_100baseT_Full;
1472                 cmd->advertising = 0;
1473                 cmd->port = PORT_MII;
1474                 cmd->transceiver = XCVR_EXTERNAL;
1475         }
1476         return 0;
1477 }
1478
1479 static int bcm_enet_set_settings(struct net_device *dev,
1480                                  struct ethtool_cmd *cmd)
1481 {
1482         struct bcm_enet_priv *priv;
1483
1484         priv = netdev_priv(dev);
1485         if (priv->has_phy) {
1486                 if (!priv->phydev)
1487                         return -ENODEV;
1488                 return phy_ethtool_sset(priv->phydev, cmd);
1489         } else {
1490
1491                 if (cmd->autoneg ||
1492                     (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) ||
1493                     cmd->port != PORT_MII)
1494                         return -EINVAL;
1495
1496                 priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0;
1497                 priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0;
1498
1499                 if (netif_running(dev))
1500                         bcm_enet_adjust_link(dev);
1501                 return 0;
1502         }
1503 }
1504
1505 static void bcm_enet_get_ringparam(struct net_device *dev,
1506                                    struct ethtool_ringparam *ering)
1507 {
1508         struct bcm_enet_priv *priv;
1509
1510         priv = netdev_priv(dev);
1511
1512         /* rx/tx ring is actually only limited by memory */
1513         ering->rx_max_pending = 8192;
1514         ering->tx_max_pending = 8192;
1515         ering->rx_pending = priv->rx_ring_size;
1516         ering->tx_pending = priv->tx_ring_size;
1517 }
1518
1519 static int bcm_enet_set_ringparam(struct net_device *dev,
1520                                   struct ethtool_ringparam *ering)
1521 {
1522         struct bcm_enet_priv *priv;
1523         int was_running;
1524
1525         priv = netdev_priv(dev);
1526
1527         was_running = 0;
1528         if (netif_running(dev)) {
1529                 bcm_enet_stop(dev);
1530                 was_running = 1;
1531         }
1532
1533         priv->rx_ring_size = ering->rx_pending;
1534         priv->tx_ring_size = ering->tx_pending;
1535
1536         if (was_running) {
1537                 int err;
1538
1539                 err = bcm_enet_open(dev);
1540                 if (err)
1541                         dev_close(dev);
1542                 else
1543                         bcm_enet_set_multicast_list(dev);
1544         }
1545         return 0;
1546 }
1547
1548 static void bcm_enet_get_pauseparam(struct net_device *dev,
1549                                     struct ethtool_pauseparam *ecmd)
1550 {
1551         struct bcm_enet_priv *priv;
1552
1553         priv = netdev_priv(dev);
1554         ecmd->autoneg = priv->pause_auto;
1555         ecmd->rx_pause = priv->pause_rx;
1556         ecmd->tx_pause = priv->pause_tx;
1557 }
1558
1559 static int bcm_enet_set_pauseparam(struct net_device *dev,
1560                                    struct ethtool_pauseparam *ecmd)
1561 {
1562         struct bcm_enet_priv *priv;
1563
1564         priv = netdev_priv(dev);
1565
1566         if (priv->has_phy) {
1567                 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1568                         /* asymetric pause mode not supported,
1569                          * actually possible but integrated PHY has RO
1570                          * asym_pause bit */
1571                         return -EINVAL;
1572                 }
1573         } else {
1574                 /* no pause autoneg on direct mii connection */
1575                 if (ecmd->autoneg)
1576                         return -EINVAL;
1577         }
1578
1579         priv->pause_auto = ecmd->autoneg;
1580         priv->pause_rx = ecmd->rx_pause;
1581         priv->pause_tx = ecmd->tx_pause;
1582
1583         return 0;
1584 }
1585
1586 static const struct ethtool_ops bcm_enet_ethtool_ops = {
1587         .get_strings            = bcm_enet_get_strings,
1588         .get_sset_count         = bcm_enet_get_sset_count,
1589         .get_ethtool_stats      = bcm_enet_get_ethtool_stats,
1590         .nway_reset             = bcm_enet_nway_reset,
1591         .get_settings           = bcm_enet_get_settings,
1592         .set_settings           = bcm_enet_set_settings,
1593         .get_drvinfo            = bcm_enet_get_drvinfo,
1594         .get_link               = ethtool_op_get_link,
1595         .get_ringparam          = bcm_enet_get_ringparam,
1596         .set_ringparam          = bcm_enet_set_ringparam,
1597         .get_pauseparam         = bcm_enet_get_pauseparam,
1598         .set_pauseparam         = bcm_enet_set_pauseparam,
1599 };
1600
1601 static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1602 {
1603         struct bcm_enet_priv *priv;
1604
1605         priv = netdev_priv(dev);
1606         if (priv->has_phy) {
1607                 if (!priv->phydev)
1608                         return -ENODEV;
1609                 return phy_mii_ioctl(priv->phydev, rq, cmd);
1610         } else {
1611                 struct mii_if_info mii;
1612
1613                 mii.dev = dev;
1614                 mii.mdio_read = bcm_enet_mdio_read_mii;
1615                 mii.mdio_write = bcm_enet_mdio_write_mii;
1616                 mii.phy_id = 0;
1617                 mii.phy_id_mask = 0x3f;
1618                 mii.reg_num_mask = 0x1f;
1619                 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1620         }
1621 }
1622
1623 /*
1624  * calculate actual hardware mtu
1625  */
1626 static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu)
1627 {
1628         int actual_mtu;
1629
1630         actual_mtu = mtu;
1631
1632         /* add ethernet header + vlan tag size */
1633         actual_mtu += VLAN_ETH_HLEN;
1634
1635         if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU)
1636                 return -EINVAL;
1637
1638         /*
1639          * setup maximum size before we get overflow mark in
1640          * descriptor, note that this will not prevent reception of
1641          * big frames, they will be split into multiple buffers
1642          * anyway
1643          */
1644         priv->hw_mtu = actual_mtu;
1645
1646         /*
1647          * align rx buffer size to dma burst len, account FCS since
1648          * it's appended
1649          */
1650         priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1651                                   priv->dma_maxburst * 4);
1652         return 0;
1653 }
1654
1655 /*
1656  * adjust mtu, can't be called while device is running
1657  */
1658 static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1659 {
1660         int ret;
1661
1662         if (netif_running(dev))
1663                 return -EBUSY;
1664
1665         ret = compute_hw_mtu(netdev_priv(dev), new_mtu);
1666         if (ret)
1667                 return ret;
1668         dev->mtu = new_mtu;
1669         return 0;
1670 }
1671
1672 /*
1673  * preinit hardware to allow mii operation while device is down
1674  */
1675 static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1676 {
1677         u32 val;
1678         int limit;
1679
1680         /* make sure mac is disabled */
1681         bcm_enet_disable_mac(priv);
1682
1683         /* soft reset mac */
1684         val = ENET_CTL_SRESET_MASK;
1685         enet_writel(priv, val, ENET_CTL_REG);
1686         wmb();
1687
1688         limit = 1000;
1689         do {
1690                 val = enet_readl(priv, ENET_CTL_REG);
1691                 if (!(val & ENET_CTL_SRESET_MASK))
1692                         break;
1693                 udelay(1);
1694         } while (limit--);
1695
1696         /* select correct mii interface */
1697         val = enet_readl(priv, ENET_CTL_REG);
1698         if (priv->use_external_mii)
1699                 val |= ENET_CTL_EPHYSEL_MASK;
1700         else
1701                 val &= ~ENET_CTL_EPHYSEL_MASK;
1702         enet_writel(priv, val, ENET_CTL_REG);
1703
1704         /* turn on mdc clock */
1705         enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1706                     ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1707
1708         /* set mib counters to self-clear when read */
1709         val = enet_readl(priv, ENET_MIBCTL_REG);
1710         val |= ENET_MIBCTL_RDCLEAR_MASK;
1711         enet_writel(priv, val, ENET_MIBCTL_REG);
1712 }
1713
1714 static const struct net_device_ops bcm_enet_ops = {
1715         .ndo_open               = bcm_enet_open,
1716         .ndo_stop               = bcm_enet_stop,
1717         .ndo_start_xmit         = bcm_enet_start_xmit,
1718         .ndo_set_mac_address    = bcm_enet_set_mac_address,
1719         .ndo_set_rx_mode        = bcm_enet_set_multicast_list,
1720         .ndo_do_ioctl           = bcm_enet_ioctl,
1721         .ndo_change_mtu         = bcm_enet_change_mtu,
1722 };
1723
1724 /*
1725  * allocate netdevice, request register memory and register device.
1726  */
1727 static int bcm_enet_probe(struct platform_device *pdev)
1728 {
1729         struct bcm_enet_priv *priv;
1730         struct net_device *dev;
1731         struct bcm63xx_enet_platform_data *pd;
1732         struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1733         struct mii_bus *bus;
1734         const char *clk_name;
1735         int i, ret;
1736
1737         /* stop if shared driver failed, assume driver->probe will be
1738          * called in the same order we register devices (correct ?) */
1739         if (!bcm_enet_shared_base[0])
1740                 return -ENODEV;
1741
1742         res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1743         res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1744         res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1745         if (!res_irq || !res_irq_rx || !res_irq_tx)
1746                 return -ENODEV;
1747
1748         ret = 0;
1749         dev = alloc_etherdev(sizeof(*priv));
1750         if (!dev)
1751                 return -ENOMEM;
1752         priv = netdev_priv(dev);
1753
1754         priv->enet_is_sw = false;
1755         priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1756
1757         ret = compute_hw_mtu(priv, dev->mtu);
1758         if (ret)
1759                 goto out;
1760
1761         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1762         priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1763         if (IS_ERR(priv->base)) {
1764                 ret = PTR_ERR(priv->base);
1765                 goto out;
1766         }
1767
1768         dev->irq = priv->irq = res_irq->start;
1769         priv->irq_rx = res_irq_rx->start;
1770         priv->irq_tx = res_irq_tx->start;
1771         priv->mac_id = pdev->id;
1772
1773         /* get rx & tx dma channel id for this mac */
1774         if (priv->mac_id == 0) {
1775                 priv->rx_chan = 0;
1776                 priv->tx_chan = 1;
1777                 clk_name = "enet0";
1778         } else {
1779                 priv->rx_chan = 2;
1780                 priv->tx_chan = 3;
1781                 clk_name = "enet1";
1782         }
1783
1784         priv->mac_clk = clk_get(&pdev->dev, clk_name);
1785         if (IS_ERR(priv->mac_clk)) {
1786                 ret = PTR_ERR(priv->mac_clk);
1787                 goto out;
1788         }
1789         clk_prepare_enable(priv->mac_clk);
1790
1791         /* initialize default and fetch platform data */
1792         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1793         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1794
1795         pd = dev_get_platdata(&pdev->dev);
1796         if (pd) {
1797                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1798                 priv->has_phy = pd->has_phy;
1799                 priv->phy_id = pd->phy_id;
1800                 priv->has_phy_interrupt = pd->has_phy_interrupt;
1801                 priv->phy_interrupt = pd->phy_interrupt;
1802                 priv->use_external_mii = !pd->use_internal_phy;
1803                 priv->pause_auto = pd->pause_auto;
1804                 priv->pause_rx = pd->pause_rx;
1805                 priv->pause_tx = pd->pause_tx;
1806                 priv->force_duplex_full = pd->force_duplex_full;
1807                 priv->force_speed_100 = pd->force_speed_100;
1808                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1809                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1810                 priv->dma_chan_width = pd->dma_chan_width;
1811                 priv->dma_has_sram = pd->dma_has_sram;
1812                 priv->dma_desc_shift = pd->dma_desc_shift;
1813         }
1814
1815         if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) {
1816                 /* using internal PHY, enable clock */
1817                 priv->phy_clk = clk_get(&pdev->dev, "ephy");
1818                 if (IS_ERR(priv->phy_clk)) {
1819                         ret = PTR_ERR(priv->phy_clk);
1820                         priv->phy_clk = NULL;
1821                         goto out_put_clk_mac;
1822                 }
1823                 clk_prepare_enable(priv->phy_clk);
1824         }
1825
1826         /* do minimal hardware init to be able to probe mii bus */
1827         bcm_enet_hw_preinit(priv);
1828
1829         /* MII bus registration */
1830         if (priv->has_phy) {
1831
1832                 priv->mii_bus = mdiobus_alloc();
1833                 if (!priv->mii_bus) {
1834                         ret = -ENOMEM;
1835                         goto out_uninit_hw;
1836                 }
1837
1838                 bus = priv->mii_bus;
1839                 bus->name = "bcm63xx_enet MII bus";
1840                 bus->parent = &pdev->dev;
1841                 bus->priv = priv;
1842                 bus->read = bcm_enet_mdio_read_phylib;
1843                 bus->write = bcm_enet_mdio_write_phylib;
1844                 sprintf(bus->id, "%s-%d", pdev->name, priv->mac_id);
1845
1846                 /* only probe bus where we think the PHY is, because
1847                  * the mdio read operation return 0 instead of 0xffff
1848                  * if a slave is not present on hw */
1849                 bus->phy_mask = ~(1 << priv->phy_id);
1850
1851                 if (priv->has_phy_interrupt)
1852                         bus->irq[priv->phy_id] = priv->phy_interrupt;
1853
1854                 ret = mdiobus_register(bus);
1855                 if (ret) {
1856                         dev_err(&pdev->dev, "unable to register mdio bus\n");
1857                         goto out_free_mdio;
1858                 }
1859         } else {
1860
1861                 /* run platform code to initialize PHY device */
1862                 if (pd->mii_config &&
1863                     pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1864                                    bcm_enet_mdio_write_mii)) {
1865                         dev_err(&pdev->dev, "unable to configure mdio bus\n");
1866                         goto out_uninit_hw;
1867                 }
1868         }
1869
1870         spin_lock_init(&priv->rx_lock);
1871
1872         /* init rx timeout (used for oom) */
1873         init_timer(&priv->rx_timeout);
1874         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1875         priv->rx_timeout.data = (unsigned long)dev;
1876
1877         /* init the mib update lock&work */
1878         mutex_init(&priv->mib_update_lock);
1879         INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1880
1881         /* zero mib counters */
1882         for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1883                 enet_writel(priv, 0, ENET_MIB_REG(i));
1884
1885         /* register netdevice */
1886         dev->netdev_ops = &bcm_enet_ops;
1887         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1888
1889         dev->ethtool_ops = &bcm_enet_ethtool_ops;
1890         SET_NETDEV_DEV(dev, &pdev->dev);
1891
1892         ret = register_netdev(dev);
1893         if (ret)
1894                 goto out_unregister_mdio;
1895
1896         netif_carrier_off(dev);
1897         platform_set_drvdata(pdev, dev);
1898         priv->pdev = pdev;
1899         priv->net_dev = dev;
1900
1901         return 0;
1902
1903 out_unregister_mdio:
1904         if (priv->mii_bus)
1905                 mdiobus_unregister(priv->mii_bus);
1906
1907 out_free_mdio:
1908         if (priv->mii_bus)
1909                 mdiobus_free(priv->mii_bus);
1910
1911 out_uninit_hw:
1912         /* turn off mdc clock */
1913         enet_writel(priv, 0, ENET_MIISC_REG);
1914         if (priv->phy_clk) {
1915                 clk_disable_unprepare(priv->phy_clk);
1916                 clk_put(priv->phy_clk);
1917         }
1918
1919 out_put_clk_mac:
1920         clk_disable_unprepare(priv->mac_clk);
1921         clk_put(priv->mac_clk);
1922 out:
1923         free_netdev(dev);
1924         return ret;
1925 }
1926
1927
1928 /*
1929  * exit func, stops hardware and unregisters netdevice
1930  */
1931 static int bcm_enet_remove(struct platform_device *pdev)
1932 {
1933         struct bcm_enet_priv *priv;
1934         struct net_device *dev;
1935
1936         /* stop netdevice */
1937         dev = platform_get_drvdata(pdev);
1938         priv = netdev_priv(dev);
1939         unregister_netdev(dev);
1940
1941         /* turn off mdc clock */
1942         enet_writel(priv, 0, ENET_MIISC_REG);
1943
1944         if (priv->has_phy) {
1945                 mdiobus_unregister(priv->mii_bus);
1946                 mdiobus_free(priv->mii_bus);
1947         } else {
1948                 struct bcm63xx_enet_platform_data *pd;
1949
1950                 pd = dev_get_platdata(&pdev->dev);
1951                 if (pd && pd->mii_config)
1952                         pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1953                                        bcm_enet_mdio_write_mii);
1954         }
1955
1956         /* disable hw block clocks */
1957         if (priv->phy_clk) {
1958                 clk_disable_unprepare(priv->phy_clk);
1959                 clk_put(priv->phy_clk);
1960         }
1961         clk_disable_unprepare(priv->mac_clk);
1962         clk_put(priv->mac_clk);
1963
1964         free_netdev(dev);
1965         return 0;
1966 }
1967
1968 struct platform_driver bcm63xx_enet_driver = {
1969         .probe  = bcm_enet_probe,
1970         .remove = bcm_enet_remove,
1971         .driver = {
1972                 .name   = "bcm63xx_enet",
1973                 .owner  = THIS_MODULE,
1974         },
1975 };
1976
1977 /*
1978  * switch mii access callbacks
1979  */
1980 static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1981                                 int ext, int phy_id, int location)
1982 {
1983         u32 reg;
1984         int ret;
1985
1986         spin_lock_bh(&priv->enetsw_mdio_lock);
1987         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1988
1989         reg = ENETSW_MDIOC_RD_MASK |
1990                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1991                 (location << ENETSW_MDIOC_REG_SHIFT);
1992
1993         if (ext)
1994                 reg |= ENETSW_MDIOC_EXT_MASK;
1995
1996         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1997         udelay(50);
1998         ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1999         spin_unlock_bh(&priv->enetsw_mdio_lock);
2000         return ret;
2001 }
2002
2003 static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
2004                                  int ext, int phy_id, int location,
2005                                  uint16_t data)
2006 {
2007         u32 reg;
2008
2009         spin_lock_bh(&priv->enetsw_mdio_lock);
2010         enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
2011
2012         reg = ENETSW_MDIOC_WR_MASK |
2013                 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
2014                 (location << ENETSW_MDIOC_REG_SHIFT);
2015
2016         if (ext)
2017                 reg |= ENETSW_MDIOC_EXT_MASK;
2018
2019         reg |= data;
2020
2021         enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
2022         udelay(50);
2023         spin_unlock_bh(&priv->enetsw_mdio_lock);
2024 }
2025
2026 static inline int bcm_enet_port_is_rgmii(int portid)
2027 {
2028         return portid >= ENETSW_RGMII_PORT0;
2029 }
2030
2031 /*
2032  * enet sw PHY polling
2033  */
2034 static void swphy_poll_timer(unsigned long data)
2035 {
2036         struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
2037         unsigned int i;
2038
2039         for (i = 0; i < priv->num_ports; i++) {
2040                 struct bcm63xx_enetsw_port *port;
2041                 int val, j, up, advertise, lpa, speed, duplex, media;
2042                 int external_phy = bcm_enet_port_is_rgmii(i);
2043                 u8 override;
2044
2045                 port = &priv->used_ports[i];
2046                 if (!port->used)
2047                         continue;
2048
2049                 if (port->bypass_link)
2050                         continue;
2051
2052                 /* dummy read to clear */
2053                 for (j = 0; j < 2; j++)
2054                         val = bcmenet_sw_mdio_read(priv, external_phy,
2055                                                    port->phy_id, MII_BMSR);
2056
2057                 if (val == 0xffff)
2058                         continue;
2059
2060                 up = (val & BMSR_LSTATUS) ? 1 : 0;
2061                 if (!(up ^ priv->sw_port_link[i]))
2062                         continue;
2063
2064                 priv->sw_port_link[i] = up;
2065
2066                 /* link changed */
2067                 if (!up) {
2068                         dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2069                                  port->name);
2070                         enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2071                                       ENETSW_PORTOV_REG(i));
2072                         enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2073                                       ENETSW_PTCTRL_TXDIS_MASK,
2074                                       ENETSW_PTCTRL_REG(i));
2075                         continue;
2076                 }
2077
2078                 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2079                                                  port->phy_id, MII_ADVERTISE);
2080
2081                 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2082                                            MII_LPA);
2083
2084                 /* figure out media and duplex from advertise and LPA values */
2085                 media = mii_nway_result(lpa & advertise);
2086                 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2087
2088                 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2089                         speed = 100;
2090                 else
2091                         speed = 10;
2092
2093                 if (val & BMSR_ESTATEN) {
2094                         advertise = bcmenet_sw_mdio_read(priv, external_phy,
2095                                                 port->phy_id, MII_CTRL1000);
2096
2097                         lpa = bcmenet_sw_mdio_read(priv, external_phy,
2098                                                 port->phy_id, MII_STAT1000);
2099
2100                         if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2101                                         && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2102                                 speed = 1000;
2103                                 duplex = (lpa & LPA_1000FULL);
2104                         }
2105                 }
2106
2107                 dev_info(&priv->pdev->dev,
2108                          "link UP on %s, %dMbps, %s-duplex\n",
2109                          port->name, speed, duplex ? "full" : "half");
2110
2111                 override = ENETSW_PORTOV_ENABLE_MASK |
2112                         ENETSW_PORTOV_LINKUP_MASK;
2113
2114                 if (speed == 1000)
2115                         override |= ENETSW_IMPOV_1000_MASK;
2116                 else if (speed == 100)
2117                         override |= ENETSW_IMPOV_100_MASK;
2118                 if (duplex)
2119                         override |= ENETSW_IMPOV_FDX_MASK;
2120
2121                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2122                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2123         }
2124
2125         priv->swphy_poll.expires = jiffies + HZ;
2126         add_timer(&priv->swphy_poll);
2127 }
2128
2129 /*
2130  * open callback, allocate dma rings & buffers and start rx operation
2131  */
2132 static int bcm_enetsw_open(struct net_device *dev)
2133 {
2134         struct bcm_enet_priv *priv;
2135         struct device *kdev;
2136         int i, ret;
2137         unsigned int size;
2138         void *p;
2139         u32 val;
2140
2141         priv = netdev_priv(dev);
2142         kdev = &priv->pdev->dev;
2143
2144         /* mask all interrupts and request them */
2145         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2146         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2147
2148         ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2149                           0, dev->name, dev);
2150         if (ret)
2151                 goto out_freeirq;
2152
2153         if (priv->irq_tx != -1) {
2154                 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2155                                   0, dev->name, dev);
2156                 if (ret)
2157                         goto out_freeirq_rx;
2158         }
2159
2160         /* allocate rx dma ring */
2161         size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2162         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2163         if (!p) {
2164                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2165                 ret = -ENOMEM;
2166                 goto out_freeirq_tx;
2167         }
2168
2169         memset(p, 0, size);
2170         priv->rx_desc_alloc_size = size;
2171         priv->rx_desc_cpu = p;
2172
2173         /* allocate tx dma ring */
2174         size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2175         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2176         if (!p) {
2177                 dev_err(kdev, "cannot allocate tx ring\n");
2178                 ret = -ENOMEM;
2179                 goto out_free_rx_ring;
2180         }
2181
2182         memset(p, 0, size);
2183         priv->tx_desc_alloc_size = size;
2184         priv->tx_desc_cpu = p;
2185
2186         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
2187                                GFP_KERNEL);
2188         if (!priv->tx_skb) {
2189                 dev_err(kdev, "cannot allocate rx skb queue\n");
2190                 ret = -ENOMEM;
2191                 goto out_free_tx_ring;
2192         }
2193
2194         priv->tx_desc_count = priv->tx_ring_size;
2195         priv->tx_dirty_desc = 0;
2196         priv->tx_curr_desc = 0;
2197         spin_lock_init(&priv->tx_lock);
2198
2199         /* init & fill rx ring with skbs */
2200         priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
2201                                GFP_KERNEL);
2202         if (!priv->rx_skb) {
2203                 dev_err(kdev, "cannot allocate rx skb queue\n");
2204                 ret = -ENOMEM;
2205                 goto out_free_tx_skb;
2206         }
2207
2208         priv->rx_desc_count = 0;
2209         priv->rx_dirty_desc = 0;
2210         priv->rx_curr_desc = 0;
2211
2212         /* disable all ports */
2213         for (i = 0; i < priv->num_ports; i++) {
2214                 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2215                               ENETSW_PORTOV_REG(i));
2216                 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2217                               ENETSW_PTCTRL_TXDIS_MASK,
2218                               ENETSW_PTCTRL_REG(i));
2219
2220                 priv->sw_port_link[i] = 0;
2221         }
2222
2223         /* reset mib */
2224         val = enetsw_readb(priv, ENETSW_GMCR_REG);
2225         val |= ENETSW_GMCR_RST_MIB_MASK;
2226         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2227         mdelay(1);
2228         val &= ~ENETSW_GMCR_RST_MIB_MASK;
2229         enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2230         mdelay(1);
2231
2232         /* force CPU port state */
2233         val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2234         val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2235         enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2236
2237         /* enable switch forward engine */
2238         val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2239         val |= ENETSW_SWMODE_FWD_EN_MASK;
2240         enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2241
2242         /* enable jumbo on all ports */
2243         enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2244         enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2245
2246         /* initialize flow control buffer allocation */
2247         enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2248                         ENETDMA_BUFALLOC_REG(priv->rx_chan));
2249
2250         if (bcm_enet_refill_rx(dev)) {
2251                 dev_err(kdev, "cannot allocate rx skb queue\n");
2252                 ret = -ENOMEM;
2253                 goto out;
2254         }
2255
2256         /* write rx & tx ring addresses */
2257         enet_dmas_writel(priv, priv->rx_desc_dma,
2258                          ENETDMAS_RSTART_REG, priv->rx_chan);
2259         enet_dmas_writel(priv, priv->tx_desc_dma,
2260                          ENETDMAS_RSTART_REG, priv->tx_chan);
2261
2262         /* clear remaining state ram for rx & tx channel */
2263         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2264         enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2265         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2266         enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2267         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2268         enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2269
2270         /* set dma maximum burst len */
2271         enet_dmac_writel(priv, priv->dma_maxburst,
2272                          ENETDMAC_MAXBURST, priv->rx_chan);
2273         enet_dmac_writel(priv, priv->dma_maxburst,
2274                          ENETDMAC_MAXBURST, priv->tx_chan);
2275
2276         /* set flow control low/high threshold to 1/3 / 2/3 */
2277         val = priv->rx_ring_size / 3;
2278         enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2279         val = (priv->rx_ring_size * 2) / 3;
2280         enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2281
2282         /* all set, enable mac and interrupts, start dma engine and
2283          * kick rx dma channel
2284          */
2285         wmb();
2286         enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2287         enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2288                          ENETDMAC_CHANCFG, priv->rx_chan);
2289
2290         /* watch "packet transferred" interrupt in rx and tx */
2291         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2292                          ENETDMAC_IR, priv->rx_chan);
2293         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2294                          ENETDMAC_IR, priv->tx_chan);
2295
2296         /* make sure we enable napi before rx interrupt  */
2297         napi_enable(&priv->napi);
2298
2299         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2300                          ENETDMAC_IRMASK, priv->rx_chan);
2301         enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2302                          ENETDMAC_IRMASK, priv->tx_chan);
2303
2304         netif_carrier_on(dev);
2305         netif_start_queue(dev);
2306
2307         /* apply override config for bypass_link ports here. */
2308         for (i = 0; i < priv->num_ports; i++) {
2309                 struct bcm63xx_enetsw_port *port;
2310                 u8 override;
2311                 port = &priv->used_ports[i];
2312                 if (!port->used)
2313                         continue;
2314
2315                 if (!port->bypass_link)
2316                         continue;
2317
2318                 override = ENETSW_PORTOV_ENABLE_MASK |
2319                         ENETSW_PORTOV_LINKUP_MASK;
2320
2321                 switch (port->force_speed) {
2322                 case 1000:
2323                         override |= ENETSW_IMPOV_1000_MASK;
2324                         break;
2325                 case 100:
2326                         override |= ENETSW_IMPOV_100_MASK;
2327                         break;
2328                 case 10:
2329                         break;
2330                 default:
2331                         pr_warn("invalid forced speed on port %s: assume 10\n",
2332                                port->name);
2333                         break;
2334                 }
2335
2336                 if (port->force_duplex_full)
2337                         override |= ENETSW_IMPOV_FDX_MASK;
2338
2339
2340                 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2341                 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2342         }
2343
2344         /* start phy polling timer */
2345         init_timer(&priv->swphy_poll);
2346         priv->swphy_poll.function = swphy_poll_timer;
2347         priv->swphy_poll.data = (unsigned long)priv;
2348         priv->swphy_poll.expires = jiffies;
2349         add_timer(&priv->swphy_poll);
2350         return 0;
2351
2352 out:
2353         for (i = 0; i < priv->rx_ring_size; i++) {
2354                 struct bcm_enet_desc *desc;
2355
2356                 if (!priv->rx_skb[i])
2357                         continue;
2358
2359                 desc = &priv->rx_desc_cpu[i];
2360                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2361                                  DMA_FROM_DEVICE);
2362                 kfree_skb(priv->rx_skb[i]);
2363         }
2364         kfree(priv->rx_skb);
2365
2366 out_free_tx_skb:
2367         kfree(priv->tx_skb);
2368
2369 out_free_tx_ring:
2370         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2371                           priv->tx_desc_cpu, priv->tx_desc_dma);
2372
2373 out_free_rx_ring:
2374         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2375                           priv->rx_desc_cpu, priv->rx_desc_dma);
2376
2377 out_freeirq_tx:
2378         if (priv->irq_tx != -1)
2379                 free_irq(priv->irq_tx, dev);
2380
2381 out_freeirq_rx:
2382         free_irq(priv->irq_rx, dev);
2383
2384 out_freeirq:
2385         return ret;
2386 }
2387
2388 /* stop callback */
2389 static int bcm_enetsw_stop(struct net_device *dev)
2390 {
2391         struct bcm_enet_priv *priv;
2392         struct device *kdev;
2393         int i;
2394
2395         priv = netdev_priv(dev);
2396         kdev = &priv->pdev->dev;
2397
2398         del_timer_sync(&priv->swphy_poll);
2399         netif_stop_queue(dev);
2400         napi_disable(&priv->napi);
2401         del_timer_sync(&priv->rx_timeout);
2402
2403         /* mask all interrupts */
2404         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2405         enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2406
2407         /* disable dma & mac */
2408         bcm_enet_disable_dma(priv, priv->tx_chan);
2409         bcm_enet_disable_dma(priv, priv->rx_chan);
2410
2411         /* force reclaim of all tx buffers */
2412         bcm_enet_tx_reclaim(dev, 1);
2413
2414         /* free the rx skb ring */
2415         for (i = 0; i < priv->rx_ring_size; i++) {
2416                 struct bcm_enet_desc *desc;
2417
2418                 if (!priv->rx_skb[i])
2419                         continue;
2420
2421                 desc = &priv->rx_desc_cpu[i];
2422                 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2423                                  DMA_FROM_DEVICE);
2424                 kfree_skb(priv->rx_skb[i]);
2425         }
2426
2427         /* free remaining allocated memory */
2428         kfree(priv->rx_skb);
2429         kfree(priv->tx_skb);
2430         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2431                           priv->rx_desc_cpu, priv->rx_desc_dma);
2432         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2433                           priv->tx_desc_cpu, priv->tx_desc_dma);
2434         if (priv->irq_tx != -1)
2435                 free_irq(priv->irq_tx, dev);
2436         free_irq(priv->irq_rx, dev);
2437
2438         return 0;
2439 }
2440
2441 /* try to sort out phy external status by walking the used_port field
2442  * in the bcm_enet_priv structure. in case the phy address is not
2443  * assigned to any physical port on the switch, assume it is external
2444  * (and yell at the user).
2445  */
2446 static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2447 {
2448         int i;
2449
2450         for (i = 0; i < priv->num_ports; ++i) {
2451                 if (!priv->used_ports[i].used)
2452                         continue;
2453                 if (priv->used_ports[i].phy_id == phy_id)
2454                         return bcm_enet_port_is_rgmii(i);
2455         }
2456
2457         printk_once(KERN_WARNING  "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2458                     phy_id);
2459         return 1;
2460 }
2461
2462 /* can't use bcmenet_sw_mdio_read directly as we need to sort out
2463  * external/internal status of the given phy_id first.
2464  */
2465 static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2466                                     int location)
2467 {
2468         struct bcm_enet_priv *priv;
2469
2470         priv = netdev_priv(dev);
2471         return bcmenet_sw_mdio_read(priv,
2472                                     bcm_enetsw_phy_is_external(priv, phy_id),
2473                                     phy_id, location);
2474 }
2475
2476 /* can't use bcmenet_sw_mdio_write directly as we need to sort out
2477  * external/internal status of the given phy_id first.
2478  */
2479 static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2480                                       int location,
2481                                       int val)
2482 {
2483         struct bcm_enet_priv *priv;
2484
2485         priv = netdev_priv(dev);
2486         bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2487                               phy_id, location, val);
2488 }
2489
2490 static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2491 {
2492         struct mii_if_info mii;
2493
2494         mii.dev = dev;
2495         mii.mdio_read = bcm_enetsw_mii_mdio_read;
2496         mii.mdio_write = bcm_enetsw_mii_mdio_write;
2497         mii.phy_id = 0;
2498         mii.phy_id_mask = 0x3f;
2499         mii.reg_num_mask = 0x1f;
2500         return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2501
2502 }
2503
2504 static const struct net_device_ops bcm_enetsw_ops = {
2505         .ndo_open               = bcm_enetsw_open,
2506         .ndo_stop               = bcm_enetsw_stop,
2507         .ndo_start_xmit         = bcm_enet_start_xmit,
2508         .ndo_change_mtu         = bcm_enet_change_mtu,
2509         .ndo_do_ioctl           = bcm_enetsw_ioctl,
2510 };
2511
2512
2513 static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2514         { "rx_packets", DEV_STAT(rx_packets), -1 },
2515         { "tx_packets", DEV_STAT(tx_packets), -1 },
2516         { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2517         { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2518         { "rx_errors", DEV_STAT(rx_errors), -1 },
2519         { "tx_errors", DEV_STAT(tx_errors), -1 },
2520         { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2521         { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2522
2523         { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2524         { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2525         { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2526         { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2527         { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2528         { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2529         { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2530         { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2531         { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2532         { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2533           ETHSW_MIB_RX_1024_1522 },
2534         { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2535           ETHSW_MIB_RX_1523_2047 },
2536         { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2537           ETHSW_MIB_RX_2048_4095 },
2538         { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2539           ETHSW_MIB_RX_4096_8191 },
2540         { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2541           ETHSW_MIB_RX_8192_9728 },
2542         { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2543         { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2544         { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2545         { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2546         { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2547
2548         { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2549         { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2550         { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2551         { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2552         { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2553         { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2554
2555 };
2556
2557 #define BCM_ENETSW_STATS_LEN    \
2558         (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2559
2560 static void bcm_enetsw_get_strings(struct net_device *netdev,
2561                                    u32 stringset, u8 *data)
2562 {
2563         int i;
2564
2565         switch (stringset) {
2566         case ETH_SS_STATS:
2567                 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2568                         memcpy(data + i * ETH_GSTRING_LEN,
2569                                bcm_enetsw_gstrings_stats[i].stat_string,
2570                                ETH_GSTRING_LEN);
2571                 }
2572                 break;
2573         }
2574 }
2575
2576 static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2577                                      int string_set)
2578 {
2579         switch (string_set) {
2580         case ETH_SS_STATS:
2581                 return BCM_ENETSW_STATS_LEN;
2582         default:
2583                 return -EINVAL;
2584         }
2585 }
2586
2587 static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2588                                    struct ethtool_drvinfo *drvinfo)
2589 {
2590         strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2591         strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2592         strncpy(drvinfo->fw_version, "N/A", 32);
2593         strncpy(drvinfo->bus_info, "bcm63xx", 32);
2594 }
2595
2596 static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2597                                          struct ethtool_stats *stats,
2598                                          u64 *data)
2599 {
2600         struct bcm_enet_priv *priv;
2601         int i;
2602
2603         priv = netdev_priv(netdev);
2604
2605         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2606                 const struct bcm_enet_stats *s;
2607                 u32 lo, hi;
2608                 char *p;
2609                 int reg;
2610
2611                 s = &bcm_enetsw_gstrings_stats[i];
2612
2613                 reg = s->mib_reg;
2614                 if (reg == -1)
2615                         continue;
2616
2617                 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2618                 p = (char *)priv + s->stat_offset;
2619
2620                 if (s->sizeof_stat == sizeof(u64)) {
2621                         hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2622                         *(u64 *)p = ((u64)hi << 32 | lo);
2623                 } else {
2624                         *(u32 *)p = lo;
2625                 }
2626         }
2627
2628         for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2629                 const struct bcm_enet_stats *s;
2630                 char *p;
2631
2632                 s = &bcm_enetsw_gstrings_stats[i];
2633
2634                 if (s->mib_reg == -1)
2635                         p = (char *)&netdev->stats + s->stat_offset;
2636                 else
2637                         p = (char *)priv + s->stat_offset;
2638
2639                 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2640                         *(u64 *)p : *(u32 *)p;
2641         }
2642 }
2643
2644 static void bcm_enetsw_get_ringparam(struct net_device *dev,
2645                                      struct ethtool_ringparam *ering)
2646 {
2647         struct bcm_enet_priv *priv;
2648
2649         priv = netdev_priv(dev);
2650
2651         /* rx/tx ring is actually only limited by memory */
2652         ering->rx_max_pending = 8192;
2653         ering->tx_max_pending = 8192;
2654         ering->rx_mini_max_pending = 0;
2655         ering->rx_jumbo_max_pending = 0;
2656         ering->rx_pending = priv->rx_ring_size;
2657         ering->tx_pending = priv->tx_ring_size;
2658 }
2659
2660 static int bcm_enetsw_set_ringparam(struct net_device *dev,
2661                                     struct ethtool_ringparam *ering)
2662 {
2663         struct bcm_enet_priv *priv;
2664         int was_running;
2665
2666         priv = netdev_priv(dev);
2667
2668         was_running = 0;
2669         if (netif_running(dev)) {
2670                 bcm_enetsw_stop(dev);
2671                 was_running = 1;
2672         }
2673
2674         priv->rx_ring_size = ering->rx_pending;
2675         priv->tx_ring_size = ering->tx_pending;
2676
2677         if (was_running) {
2678                 int err;
2679
2680                 err = bcm_enetsw_open(dev);
2681                 if (err)
2682                         dev_close(dev);
2683         }
2684         return 0;
2685 }
2686
2687 static struct ethtool_ops bcm_enetsw_ethtool_ops = {
2688         .get_strings            = bcm_enetsw_get_strings,
2689         .get_sset_count         = bcm_enetsw_get_sset_count,
2690         .get_ethtool_stats      = bcm_enetsw_get_ethtool_stats,
2691         .get_drvinfo            = bcm_enetsw_get_drvinfo,
2692         .get_ringparam          = bcm_enetsw_get_ringparam,
2693         .set_ringparam          = bcm_enetsw_set_ringparam,
2694 };
2695
2696 /* allocate netdevice, request register memory and register device. */
2697 static int bcm_enetsw_probe(struct platform_device *pdev)
2698 {
2699         struct bcm_enet_priv *priv;
2700         struct net_device *dev;
2701         struct bcm63xx_enetsw_platform_data *pd;
2702         struct resource *res_mem;
2703         int ret, irq_rx, irq_tx;
2704
2705         /* stop if shared driver failed, assume driver->probe will be
2706          * called in the same order we register devices (correct ?)
2707          */
2708         if (!bcm_enet_shared_base[0])
2709                 return -ENODEV;
2710
2711         res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2712         irq_rx = platform_get_irq(pdev, 0);
2713         irq_tx = platform_get_irq(pdev, 1);
2714         if (!res_mem || irq_rx < 0)
2715                 return -ENODEV;
2716
2717         ret = 0;
2718         dev = alloc_etherdev(sizeof(*priv));
2719         if (!dev)
2720                 return -ENOMEM;
2721         priv = netdev_priv(dev);
2722         memset(priv, 0, sizeof(*priv));
2723
2724         /* initialize default and fetch platform data */
2725         priv->enet_is_sw = true;
2726         priv->irq_rx = irq_rx;
2727         priv->irq_tx = irq_tx;
2728         priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2729         priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2730         priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2731
2732         pd = dev_get_platdata(&pdev->dev);
2733         if (pd) {
2734                 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2735                 memcpy(priv->used_ports, pd->used_ports,
2736                        sizeof(pd->used_ports));
2737                 priv->num_ports = pd->num_ports;
2738                 priv->dma_has_sram = pd->dma_has_sram;
2739                 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2740                 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2741                 priv->dma_chan_width = pd->dma_chan_width;
2742         }
2743
2744         ret = compute_hw_mtu(priv, dev->mtu);
2745         if (ret)
2746                 goto out;
2747
2748         if (!request_mem_region(res_mem->start, resource_size(res_mem),
2749                                 "bcm63xx_enetsw")) {
2750                 ret = -EBUSY;
2751                 goto out;
2752         }
2753
2754         priv->base = ioremap(res_mem->start, resource_size(res_mem));
2755         if (priv->base == NULL) {
2756                 ret = -ENOMEM;
2757                 goto out_release_mem;
2758         }
2759
2760         priv->mac_clk = clk_get(&pdev->dev, "enetsw");
2761         if (IS_ERR(priv->mac_clk)) {
2762                 ret = PTR_ERR(priv->mac_clk);
2763                 goto out_unmap;
2764         }
2765         clk_enable(priv->mac_clk);
2766
2767         priv->rx_chan = 0;
2768         priv->tx_chan = 1;
2769         spin_lock_init(&priv->rx_lock);
2770
2771         /* init rx timeout (used for oom) */
2772         init_timer(&priv->rx_timeout);
2773         priv->rx_timeout.function = bcm_enet_refill_rx_timer;
2774         priv->rx_timeout.data = (unsigned long)dev;
2775
2776         /* register netdevice */
2777         dev->netdev_ops = &bcm_enetsw_ops;
2778         netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2779         dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2780         SET_NETDEV_DEV(dev, &pdev->dev);
2781
2782         spin_lock_init(&priv->enetsw_mdio_lock);
2783
2784         ret = register_netdev(dev);
2785         if (ret)
2786                 goto out_put_clk;
2787
2788         netif_carrier_off(dev);
2789         platform_set_drvdata(pdev, dev);
2790         priv->pdev = pdev;
2791         priv->net_dev = dev;
2792
2793         return 0;
2794
2795 out_put_clk:
2796         clk_put(priv->mac_clk);
2797
2798 out_unmap:
2799         iounmap(priv->base);
2800
2801 out_release_mem:
2802         release_mem_region(res_mem->start, resource_size(res_mem));
2803 out:
2804         free_netdev(dev);
2805         return ret;
2806 }
2807
2808
2809 /* exit func, stops hardware and unregisters netdevice */
2810 static int bcm_enetsw_remove(struct platform_device *pdev)
2811 {
2812         struct bcm_enet_priv *priv;
2813         struct net_device *dev;
2814         struct resource *res;
2815
2816         /* stop netdevice */
2817         dev = platform_get_drvdata(pdev);
2818         priv = netdev_priv(dev);
2819         unregister_netdev(dev);
2820
2821         /* release device resources */
2822         iounmap(priv->base);
2823         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2824         release_mem_region(res->start, resource_size(res));
2825
2826         free_netdev(dev);
2827         return 0;
2828 }
2829
2830 struct platform_driver bcm63xx_enetsw_driver = {
2831         .probe  = bcm_enetsw_probe,
2832         .remove = bcm_enetsw_remove,
2833         .driver = {
2834                 .name   = "bcm63xx_enetsw",
2835                 .owner  = THIS_MODULE,
2836         },
2837 };
2838
2839 /* reserve & remap memory space shared between all macs */
2840 static int bcm_enet_shared_probe(struct platform_device *pdev)
2841 {
2842         struct resource *res;
2843         void __iomem *p[3];
2844         unsigned int i;
2845
2846         memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2847
2848         for (i = 0; i < 3; i++) {
2849                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2850                 p[i] = devm_ioremap_resource(&pdev->dev, res);
2851                 if (IS_ERR(p[i]))
2852                         return PTR_ERR(p[i]);
2853         }
2854
2855         memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2856
2857         return 0;
2858 }
2859
2860 static int bcm_enet_shared_remove(struct platform_device *pdev)
2861 {
2862         return 0;
2863 }
2864
2865 /* this "shared" driver is needed because both macs share a single
2866  * address space
2867  */
2868 struct platform_driver bcm63xx_enet_shared_driver = {
2869         .probe  = bcm_enet_shared_probe,
2870         .remove = bcm_enet_shared_remove,
2871         .driver = {
2872                 .name   = "bcm63xx_enet_shared",
2873                 .owner  = THIS_MODULE,
2874         },
2875 };
2876
2877 static struct platform_driver * const drivers[] = {
2878         &bcm63xx_enet_shared_driver,
2879         &bcm63xx_enet_driver,
2880         &bcm63xx_enetsw_driver,
2881 };
2882
2883 /* entry point */
2884 static int __init bcm_enet_init(void)
2885 {
2886         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2887 }
2888
2889 static void __exit bcm_enet_exit(void)
2890 {
2891         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2892 }
2893
2894
2895 module_init(bcm_enet_init);
2896 module_exit(bcm_enet_exit);
2897
2898 MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2899 MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2900 MODULE_LICENSE("GPL");