1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
82 static char version[] __devinitdata =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
99 module_param(num_queues, int, 0);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
128 struct workqueue_struct *bnx2x_wq;
130 enum bnx2x_board_type {
149 /* indexed by board_type, above */
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
220 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
221 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
222 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
223 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
224 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
225 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
226 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
227 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
228 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
229 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
230 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
231 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
250 u32 addr, dma_addr_t mapping)
252 REG_WR(bp, addr, U64_LO(mapping));
253 REG_WR(bp, addr + 4, U64_HI(mapping));
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257 dma_addr_t mapping, u16 abs_fid)
259 u32 addr = XSEM_REG_FAST_MEMORY +
260 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
262 __storm_memset_dma_mapping(bp, addr, mapping);
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
270 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
272 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
274 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
281 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
283 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
285 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
287 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
291 static void storm_memset_eq_data(struct bnx2x *bp,
292 struct event_ring_data *eq_data,
295 size_t size = sizeof(struct event_ring_data);
297 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
299 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
305 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
306 REG_WR16(bp, addr, eq_prod);
310 * locking is done by mcp
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
314 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
317 PCICFG_VENDOR_ID_OFFSET);
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
327 PCICFG_VENDOR_ID_OFFSET);
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
345 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
349 REG_WR(bp, dmae_reg_go_c[idx], 1);
352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
354 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
360 return opcode & ~DMAE_CMD_SRC_RESET;
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364 bool with_comp, u8 comp_type)
368 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369 (dst_type << DMAE_COMMAND_DST_SHIFT));
371 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
373 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
375 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
376 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
379 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
381 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
384 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389 struct dmae_command *dmae,
390 u8 src_type, u8 dst_type)
392 memset(dmae, 0, sizeof(struct dmae_command));
395 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396 true, DMAE_COMP_PCI);
398 /* fill in the completion parameters */
399 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401 dmae->comp_val = DMAE_COMP_VAL;
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406 struct dmae_command *dmae)
408 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
413 * Lock the dmae channel. Disable BHs to prevent a dead-lock
414 * as long as this code is called both from syscall context and
415 * from ndo_set_rx_mode() flow that may be called from BH.
417 spin_lock_bh(&bp->dmae_lock);
419 /* reset completion */
422 /* post the command on the channel used for initializations */
423 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
425 /* wait for completion */
427 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
430 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
431 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
432 BNX2X_ERR("DMAE timeout!\n");
439 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440 BNX2X_ERR("DMAE PCI error!\n");
445 spin_unlock_bh(&bp->dmae_lock);
449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
452 struct dmae_command dmae;
454 if (!bp->dmae_ready) {
455 u32 *data = bnx2x_sp(bp, wb_data[0]);
458 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
460 bnx2x_init_str_wr(bp, dst_addr, data, len32);
464 /* set opcode and fixed command fields */
465 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
467 /* fill in addresses and len */
468 dmae.src_addr_lo = U64_LO(dma_addr);
469 dmae.src_addr_hi = U64_HI(dma_addr);
470 dmae.dst_addr_lo = dst_addr >> 2;
471 dmae.dst_addr_hi = 0;
474 /* issue the command and wait for completion */
475 bnx2x_issue_dmae_with_comp(bp, &dmae);
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
480 struct dmae_command dmae;
482 if (!bp->dmae_ready) {
483 u32 *data = bnx2x_sp(bp, wb_data[0]);
487 for (i = 0; i < len32; i++)
488 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
490 for (i = 0; i < len32; i++)
491 data[i] = REG_RD(bp, src_addr + i*4);
496 /* set opcode and fixed command fields */
497 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
499 /* fill in addresses and len */
500 dmae.src_addr_lo = src_addr >> 2;
501 dmae.src_addr_hi = 0;
502 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
513 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
516 while (len > dmae_wr_max) {
517 bnx2x_write_dmae(bp, phys_addr + offset,
518 addr + offset, dmae_wr_max);
519 offset += dmae_wr_max * 4;
523 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
526 static int bnx2x_mc_assert(struct bnx2x *bp)
530 u32 row0, row1, row2, row3;
533 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
534 XSTORM_ASSERT_LIST_INDEX_OFFSET);
536 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
538 /* print the asserts */
539 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
541 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
542 XSTORM_ASSERT_LIST_OFFSET(i));
543 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
544 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
545 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
547 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
550 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552 i, row3, row2, row1, row0);
560 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
561 TSTORM_ASSERT_LIST_INDEX_OFFSET);
563 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
565 /* print the asserts */
566 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
568 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
569 TSTORM_ASSERT_LIST_OFFSET(i));
570 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
571 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
572 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
574 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
577 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i, row3, row2, row1, row0);
587 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
588 CSTORM_ASSERT_LIST_INDEX_OFFSET);
590 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
592 /* print the asserts */
593 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
595 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
596 CSTORM_ASSERT_LIST_OFFSET(i));
597 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
598 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
599 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
601 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
604 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606 i, row3, row2, row1, row0);
614 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
615 USTORM_ASSERT_LIST_INDEX_OFFSET);
617 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
619 /* print the asserts */
620 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
622 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
623 USTORM_ASSERT_LIST_OFFSET(i));
624 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
625 USTORM_ASSERT_LIST_OFFSET(i) + 4);
626 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_OFFSET(i) + 8);
628 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629 USTORM_ASSERT_LIST_OFFSET(i) + 12);
631 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633 i, row3, row2, row1, row0);
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
649 u32 trace_shmem_base;
651 BNX2X_ERR("NO MCP - can not dump\n");
654 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655 (bp->common.bc_ver & 0xff0000) >> 16,
656 (bp->common.bc_ver & 0xff00) >> 8,
657 (bp->common.bc_ver & 0xff));
659 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
660 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
661 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
663 if (BP_PATH(bp) == 0)
664 trace_shmem_base = bp->common.shmem_base;
666 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667 addr = trace_shmem_base - 0x800;
669 /* validate TRCB signature */
670 mark = REG_RD(bp, addr);
671 if (mark != MFW_TRACE_SIGNATURE) {
672 BNX2X_ERR("Trace buffer signature is missing.");
676 /* read cyclic buffer pointer */
678 mark = REG_RD(bp, addr);
679 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
680 + ((mark + 0x3) & ~0x3) - 0x08000000;
681 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
684 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685 for (word = 0; word < 8; word++)
686 data[word] = htonl(REG_RD(bp, offset + 4*word));
688 pr_cont("%s", (char *)data);
690 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691 for (word = 0; word < 8; word++)
692 data[word] = htonl(REG_RD(bp, offset + 4*word));
694 pr_cont("%s", (char *)data);
696 printk("%s" "end of fw dump\n", lvl);
699 static void bnx2x_fw_dump(struct bnx2x *bp)
701 bnx2x_fw_dump_lvl(bp, KERN_ERR);
704 void bnx2x_panic_dump(struct bnx2x *bp)
708 struct hc_sp_status_block_data sp_sb_data;
709 int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711 u16 start = 0, end = 0;
715 bp->stats_state = STATS_STATE_DISABLED;
716 bp->eth_stats.unrecoverable_error++;
717 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
719 BNX2X_ERR("begin crash dump -----------------\n");
723 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724 bp->def_idx, bp->def_att_idx, bp->attn_state,
725 bp->spq_prod_idx, bp->stats_counter);
726 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727 bp->def_status_blk->atten_status_block.attn_bits,
728 bp->def_status_blk->atten_status_block.attn_bits_ack,
729 bp->def_status_blk->atten_status_block.status_block_id,
730 bp->def_status_blk->atten_status_block.attn_bits_index);
732 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
734 bp->def_status_blk->sp_sb.index_values[i],
735 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
737 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
739 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
742 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743 sp_sb_data.igu_sb_id,
744 sp_sb_data.igu_seg_id,
745 sp_sb_data.p_func.pf_id,
746 sp_sb_data.p_func.vnic_id,
747 sp_sb_data.p_func.vf_id,
748 sp_sb_data.p_func.vf_valid,
752 for_each_eth_queue(bp, i) {
753 struct bnx2x_fastpath *fp = &bp->fp[i];
755 struct hc_status_block_data_e2 sb_data_e2;
756 struct hc_status_block_data_e1x sb_data_e1x;
757 struct hc_status_block_sm *hc_sm_p =
759 sb_data_e1x.common.state_machine :
760 sb_data_e2.common.state_machine;
761 struct hc_index_data *hc_index_p =
763 sb_data_e1x.index_data :
764 sb_data_e2.index_data;
767 struct bnx2x_fp_txdata txdata;
770 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771 i, fp->rx_bd_prod, fp->rx_bd_cons,
773 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775 fp->rx_sge_prod, fp->last_max_sge,
776 le16_to_cpu(fp->fp_hc_idx));
779 for_each_cos_in_tx_queue(fp, cos)
781 txdata = *fp->txdata_ptr[cos];
782 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783 i, txdata.tx_pkt_prod,
784 txdata.tx_pkt_cons, txdata.tx_bd_prod,
786 le16_to_cpu(*txdata.tx_cons_sb));
789 loop = CHIP_IS_E1x(bp) ?
790 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
798 BNX2X_ERR(" run indexes (");
799 for (j = 0; j < HC_SB_MAX_SM; j++)
801 fp->sb_running_index[j],
802 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
804 BNX2X_ERR(" indexes (");
805 for (j = 0; j < loop; j++)
807 fp->sb_index_values[j],
808 (j == loop - 1) ? ")" : " ");
810 data_size = CHIP_IS_E1x(bp) ?
811 sizeof(struct hc_status_block_data_e1x) :
812 sizeof(struct hc_status_block_data_e2);
813 data_size /= sizeof(u32);
814 sb_data_p = CHIP_IS_E1x(bp) ?
815 (u32 *)&sb_data_e1x :
817 /* copy sb data in here */
818 for (j = 0; j < data_size; j++)
819 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
820 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
823 if (!CHIP_IS_E1x(bp)) {
824 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
825 sb_data_e2.common.p_func.pf_id,
826 sb_data_e2.common.p_func.vf_id,
827 sb_data_e2.common.p_func.vf_valid,
828 sb_data_e2.common.p_func.vnic_id,
829 sb_data_e2.common.same_igu_sb_1b,
830 sb_data_e2.common.state);
832 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
833 sb_data_e1x.common.p_func.pf_id,
834 sb_data_e1x.common.p_func.vf_id,
835 sb_data_e1x.common.p_func.vf_valid,
836 sb_data_e1x.common.p_func.vnic_id,
837 sb_data_e1x.common.same_igu_sb_1b,
838 sb_data_e1x.common.state);
842 for (j = 0; j < HC_SB_MAX_SM; j++) {
843 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
844 j, hc_sm_p[j].__flags,
845 hc_sm_p[j].igu_sb_id,
846 hc_sm_p[j].igu_seg_id,
847 hc_sm_p[j].time_to_expire,
848 hc_sm_p[j].timer_value);
852 for (j = 0; j < loop; j++) {
853 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
855 hc_index_p[j].timeout);
859 #ifdef BNX2X_STOP_ON_ERROR
862 for_each_rx_queue(bp, i) {
863 struct bnx2x_fastpath *fp = &bp->fp[i];
865 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
866 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
867 for (j = start; j != end; j = RX_BD(j + 1)) {
868 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
869 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
871 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
872 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
875 start = RX_SGE(fp->rx_sge_prod);
876 end = RX_SGE(fp->last_max_sge);
877 for (j = start; j != end; j = RX_SGE(j + 1)) {
878 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
879 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
881 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
882 i, j, rx_sge[1], rx_sge[0], sw_page->page);
885 start = RCQ_BD(fp->rx_comp_cons - 10);
886 end = RCQ_BD(fp->rx_comp_cons + 503);
887 for (j = start; j != end; j = RCQ_BD(j + 1)) {
888 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
890 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
891 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
896 for_each_tx_queue(bp, i) {
897 struct bnx2x_fastpath *fp = &bp->fp[i];
898 for_each_cos_in_tx_queue(fp, cos) {
899 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
901 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
902 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
903 for (j = start; j != end; j = TX_BD(j + 1)) {
904 struct sw_tx_bd *sw_bd =
905 &txdata->tx_buf_ring[j];
907 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
908 i, cos, j, sw_bd->skb,
912 start = TX_BD(txdata->tx_bd_cons - 10);
913 end = TX_BD(txdata->tx_bd_cons + 254);
914 for (j = start; j != end; j = TX_BD(j + 1)) {
915 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
917 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
918 i, cos, j, tx_bd[0], tx_bd[1],
926 BNX2X_ERR("end crash dump -----------------\n");
932 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
935 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
936 #define FLR_WAIT_INTERVAL 50 /* usec */
937 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
939 struct pbf_pN_buf_regs {
946 struct pbf_pN_cmd_regs {
952 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
953 struct pbf_pN_buf_regs *regs,
956 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
957 u32 cur_cnt = poll_count;
959 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
960 crd = crd_start = REG_RD(bp, regs->crd);
961 init_crd = REG_RD(bp, regs->init_crd);
963 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
964 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
965 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
967 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
968 (init_crd - crd_start))) {
970 udelay(FLR_WAIT_INTERVAL);
971 crd = REG_RD(bp, regs->crd);
972 crd_freed = REG_RD(bp, regs->crd_freed);
974 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
976 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
978 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
979 regs->pN, crd_freed);
983 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
984 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
987 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
988 struct pbf_pN_cmd_regs *regs,
991 u32 occup, to_free, freed, freed_start;
992 u32 cur_cnt = poll_count;
994 occup = to_free = REG_RD(bp, regs->lines_occup);
995 freed = freed_start = REG_RD(bp, regs->lines_freed);
997 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
998 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1000 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1002 udelay(FLR_WAIT_INTERVAL);
1003 occup = REG_RD(bp, regs->lines_occup);
1004 freed = REG_RD(bp, regs->lines_freed);
1006 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1008 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1010 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1015 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1016 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1019 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1020 u32 expected, u32 poll_count)
1022 u32 cur_cnt = poll_count;
1025 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1026 udelay(FLR_WAIT_INTERVAL);
1031 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1032 char *msg, u32 poll_cnt)
1034 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1036 BNX2X_ERR("%s usage count=%d\n", msg, val);
1042 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1044 /* adjust polling timeout */
1045 if (CHIP_REV_IS_EMUL(bp))
1046 return FLR_POLL_CNT * 2000;
1048 if (CHIP_REV_IS_FPGA(bp))
1049 return FLR_POLL_CNT * 120;
1051 return FLR_POLL_CNT;
1054 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1056 struct pbf_pN_cmd_regs cmd_regs[] = {
1057 {0, (CHIP_IS_E3B0(bp)) ?
1058 PBF_REG_TQ_OCCUPANCY_Q0 :
1059 PBF_REG_P0_TQ_OCCUPANCY,
1060 (CHIP_IS_E3B0(bp)) ?
1061 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1062 PBF_REG_P0_TQ_LINES_FREED_CNT},
1063 {1, (CHIP_IS_E3B0(bp)) ?
1064 PBF_REG_TQ_OCCUPANCY_Q1 :
1065 PBF_REG_P1_TQ_OCCUPANCY,
1066 (CHIP_IS_E3B0(bp)) ?
1067 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1068 PBF_REG_P1_TQ_LINES_FREED_CNT},
1069 {4, (CHIP_IS_E3B0(bp)) ?
1070 PBF_REG_TQ_OCCUPANCY_LB_Q :
1071 PBF_REG_P4_TQ_OCCUPANCY,
1072 (CHIP_IS_E3B0(bp)) ?
1073 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1074 PBF_REG_P4_TQ_LINES_FREED_CNT}
1077 struct pbf_pN_buf_regs buf_regs[] = {
1078 {0, (CHIP_IS_E3B0(bp)) ?
1079 PBF_REG_INIT_CRD_Q0 :
1080 PBF_REG_P0_INIT_CRD ,
1081 (CHIP_IS_E3B0(bp)) ?
1084 (CHIP_IS_E3B0(bp)) ?
1085 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1086 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1087 {1, (CHIP_IS_E3B0(bp)) ?
1088 PBF_REG_INIT_CRD_Q1 :
1089 PBF_REG_P1_INIT_CRD,
1090 (CHIP_IS_E3B0(bp)) ?
1093 (CHIP_IS_E3B0(bp)) ?
1094 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1095 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1096 {4, (CHIP_IS_E3B0(bp)) ?
1097 PBF_REG_INIT_CRD_LB_Q :
1098 PBF_REG_P4_INIT_CRD,
1099 (CHIP_IS_E3B0(bp)) ?
1100 PBF_REG_CREDIT_LB_Q :
1102 (CHIP_IS_E3B0(bp)) ?
1103 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1104 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1109 /* Verify the command queues are flushed P0, P1, P4 */
1110 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1111 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1114 /* Verify the transmission buffers are flushed P0, P1, P4 */
1115 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1116 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1119 #define OP_GEN_PARAM(param) \
1120 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1122 #define OP_GEN_TYPE(type) \
1123 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1125 #define OP_GEN_AGG_VECT(index) \
1126 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1129 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1132 struct sdm_op_gen op_gen = {0};
1134 u32 comp_addr = BAR_CSTRORM_INTMEM +
1135 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1138 if (REG_RD(bp, comp_addr)) {
1139 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1143 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1144 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1145 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1146 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1148 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1149 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1151 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1152 BNX2X_ERR("FW final cleanup did not succeed\n");
1153 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1154 (REG_RD(bp, comp_addr)));
1157 /* Zero completion for nxt FLR */
1158 REG_WR(bp, comp_addr, 0);
1163 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1168 pos = pci_pcie_cap(dev);
1172 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1173 return status & PCI_EXP_DEVSTA_TRPND;
1176 /* PF FLR specific routines
1178 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1181 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1182 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1183 CFC_REG_NUM_LCIDS_INSIDE_PF,
1184 "CFC PF usage counter timed out",
1189 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1190 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1191 DORQ_REG_PF_USAGE_CNT,
1192 "DQ PF usage counter timed out",
1196 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1197 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1198 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1199 "QM PF usage counter timed out",
1203 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1204 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1205 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1206 "Timers VNIC usage counter timed out",
1209 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1210 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1211 "Timers NUM_SCANS usage counter timed out",
1215 /* Wait DMAE PF usage counter to zero */
1216 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1217 dmae_reg_go_c[INIT_DMAE_C(bp)],
1218 "DMAE dommand register timed out",
1225 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1229 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1230 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1232 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1233 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1235 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1236 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1238 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1239 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1241 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1242 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1244 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1245 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1247 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1248 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1250 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1251 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1255 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1257 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1259 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1261 /* Re-enable PF target read access */
1262 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1264 /* Poll HW usage counters */
1265 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1266 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1269 /* Zero the igu 'trailing edge' and 'leading edge' */
1271 /* Send the FW cleanup command */
1272 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1277 /* Verify TX hw is flushed */
1278 bnx2x_tx_hw_flushed(bp, poll_cnt);
1280 /* Wait 100ms (not adjusted according to platform) */
1283 /* Verify no pending pci transactions */
1284 if (bnx2x_is_pcie_pending(bp->pdev))
1285 BNX2X_ERR("PCIE Transactions still pending\n");
1288 bnx2x_hw_enable_status(bp);
1291 * Master enable - Due to WB DMAE writes performed before this
1292 * register is re-initialized as part of the regular function init
1294 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1299 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1301 int port = BP_PORT(bp);
1302 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1303 u32 val = REG_RD(bp, addr);
1304 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1305 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1306 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1309 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1310 HC_CONFIG_0_REG_INT_LINE_EN_0);
1311 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1312 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1314 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1316 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1317 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1318 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1319 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1321 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1322 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1323 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1324 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1326 if (!CHIP_IS_E1(bp)) {
1328 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1330 REG_WR(bp, addr, val);
1332 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1337 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1340 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1341 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1343 REG_WR(bp, addr, val);
1345 * Ensure that HC_CONFIG is written before leading/trailing edge config
1350 if (!CHIP_IS_E1(bp)) {
1351 /* init leading/trailing edge */
1353 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1355 /* enable nig and gpio3 attention */
1360 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1361 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1364 /* Make sure that interrupts are indeed enabled from here on */
1368 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1371 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1372 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1373 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1375 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1378 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1379 IGU_PF_CONF_SINGLE_ISR_EN);
1380 val |= (IGU_PF_CONF_FUNC_EN |
1381 IGU_PF_CONF_MSI_MSIX_EN |
1382 IGU_PF_CONF_ATTN_BIT_EN);
1385 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1387 val &= ~IGU_PF_CONF_INT_LINE_EN;
1388 val |= (IGU_PF_CONF_FUNC_EN |
1389 IGU_PF_CONF_MSI_MSIX_EN |
1390 IGU_PF_CONF_ATTN_BIT_EN |
1391 IGU_PF_CONF_SINGLE_ISR_EN);
1393 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1394 val |= (IGU_PF_CONF_FUNC_EN |
1395 IGU_PF_CONF_INT_LINE_EN |
1396 IGU_PF_CONF_ATTN_BIT_EN |
1397 IGU_PF_CONF_SINGLE_ISR_EN);
1400 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1401 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1403 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1405 if (val & IGU_PF_CONF_INT_LINE_EN)
1406 pci_intx(bp->pdev, true);
1410 /* init leading/trailing edge */
1412 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1414 /* enable nig and gpio3 attention */
1419 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1420 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1422 /* Make sure that interrupts are indeed enabled from here on */
1426 void bnx2x_int_enable(struct bnx2x *bp)
1428 if (bp->common.int_block == INT_BLOCK_HC)
1429 bnx2x_hc_int_enable(bp);
1431 bnx2x_igu_int_enable(bp);
1434 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1436 int port = BP_PORT(bp);
1437 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1438 u32 val = REG_RD(bp, addr);
1441 * in E1 we must use only PCI configuration space to disable
1442 * MSI/MSIX capablility
1443 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1445 if (CHIP_IS_E1(bp)) {
1446 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1447 * Use mask register to prevent from HC sending interrupts
1448 * after we exit the function
1450 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1452 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1453 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1454 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1456 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1457 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1458 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1459 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1461 DP(NETIF_MSG_IFDOWN,
1462 "write %x to HC %d (addr 0x%x)\n",
1465 /* flush all outstanding writes */
1468 REG_WR(bp, addr, val);
1469 if (REG_RD(bp, addr) != val)
1470 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1473 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1475 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1477 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1478 IGU_PF_CONF_INT_LINE_EN |
1479 IGU_PF_CONF_ATTN_BIT_EN);
1481 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1483 /* flush all outstanding writes */
1486 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1487 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1488 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1491 void bnx2x_int_disable(struct bnx2x *bp)
1493 if (bp->common.int_block == INT_BLOCK_HC)
1494 bnx2x_hc_int_disable(bp);
1496 bnx2x_igu_int_disable(bp);
1499 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1501 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1505 /* prevent the HW from sending interrupts */
1506 bnx2x_int_disable(bp);
1508 /* make sure all ISRs are done */
1510 synchronize_irq(bp->msix_table[0].vector);
1515 for_each_eth_queue(bp, i)
1516 synchronize_irq(bp->msix_table[offset++].vector);
1518 synchronize_irq(bp->pdev->irq);
1520 /* make sure sp_task is not running */
1521 cancel_delayed_work(&bp->sp_task);
1522 cancel_delayed_work(&bp->period_task);
1523 flush_workqueue(bnx2x_wq);
1529 * General service functions
1532 /* Return true if succeeded to acquire the lock */
1533 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1536 u32 resource_bit = (1 << resource);
1537 int func = BP_FUNC(bp);
1538 u32 hw_lock_control_reg;
1540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1541 "Trying to take a lock on resource %d\n", resource);
1543 /* Validating that the resource is within range */
1544 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1547 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1552 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1554 hw_lock_control_reg =
1555 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1557 /* Try to acquire the lock */
1558 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1559 lock_status = REG_RD(bp, hw_lock_control_reg);
1560 if (lock_status & resource_bit)
1563 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1564 "Failed to get a lock on resource %d\n", resource);
1569 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1571 * @bp: driver handle
1573 * Returns the recovery leader resource id according to the engine this function
1574 * belongs to. Currently only only 2 engines is supported.
1576 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1579 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1581 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1585 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1587 * @bp: driver handle
1589 * Tries to aquire a leader lock for current engine.
1591 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1593 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1597 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1600 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1602 struct bnx2x *bp = fp->bp;
1603 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1604 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1605 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1606 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1609 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1610 fp->index, cid, command, bp->state,
1611 rr_cqe->ramrod_cqe.ramrod_type);
1614 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1615 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1616 drv_cmd = BNX2X_Q_CMD_UPDATE;
1619 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1620 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1621 drv_cmd = BNX2X_Q_CMD_SETUP;
1624 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1625 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1626 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1629 case (RAMROD_CMD_ID_ETH_HALT):
1630 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1631 drv_cmd = BNX2X_Q_CMD_HALT;
1634 case (RAMROD_CMD_ID_ETH_TERMINATE):
1635 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1636 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1639 case (RAMROD_CMD_ID_ETH_EMPTY):
1640 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1641 drv_cmd = BNX2X_Q_CMD_EMPTY;
1645 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1646 command, fp->index);
1650 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1651 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1652 /* q_obj->complete_cmd() failure means that this was
1653 * an unexpected completion.
1655 * In this case we don't want to increase the bp->spq_left
1656 * because apparently we haven't sent this command the first
1659 #ifdef BNX2X_STOP_ON_ERROR
1665 smp_mb__before_atomic_inc();
1666 atomic_inc(&bp->cq_spq_left);
1667 /* push the change in bp->spq_left and towards the memory */
1668 smp_mb__after_atomic_inc();
1670 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1672 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1673 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1674 /* if Q update ramrod is completed for last Q in AFEX vif set
1675 * flow, then ACK MCP at the end
1677 * mark pending ACK to MCP bit.
1678 * prevent case that both bits are cleared.
1679 * At the end of load/unload driver checks that
1680 * sp_state is cleaerd, and this order prevents
1683 smp_mb__before_clear_bit();
1684 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1686 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1687 smp_mb__after_clear_bit();
1689 /* schedule workqueue to send ack to MCP */
1690 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1696 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1697 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1699 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1701 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1705 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1707 struct bnx2x *bp = netdev_priv(dev_instance);
1708 u16 status = bnx2x_ack_int(bp);
1713 /* Return here if interrupt is shared and it's not for us */
1714 if (unlikely(status == 0)) {
1715 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1718 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1720 #ifdef BNX2X_STOP_ON_ERROR
1721 if (unlikely(bp->panic))
1725 for_each_eth_queue(bp, i) {
1726 struct bnx2x_fastpath *fp = &bp->fp[i];
1728 mask = 0x2 << (fp->index + CNIC_PRESENT);
1729 if (status & mask) {
1730 /* Handle Rx or Tx according to SB id */
1731 prefetch(fp->rx_cons_sb);
1732 for_each_cos_in_tx_queue(fp, cos)
1733 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1734 prefetch(&fp->sb_running_index[SM_RX_ID]);
1735 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1742 if (status & (mask | 0x1)) {
1743 struct cnic_ops *c_ops = NULL;
1745 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1747 c_ops = rcu_dereference(bp->cnic_ops);
1749 c_ops->cnic_handler(bp->cnic_data, NULL);
1757 if (unlikely(status & 0x1)) {
1758 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1765 if (unlikely(status))
1766 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1775 * General service functions
1778 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1781 u32 resource_bit = (1 << resource);
1782 int func = BP_FUNC(bp);
1783 u32 hw_lock_control_reg;
1786 /* Validating that the resource is within range */
1787 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1788 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1789 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1794 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1796 hw_lock_control_reg =
1797 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1800 /* Validating that the resource is not already taken */
1801 lock_status = REG_RD(bp, hw_lock_control_reg);
1802 if (lock_status & resource_bit) {
1803 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1804 lock_status, resource_bit);
1808 /* Try for 5 second every 5ms */
1809 for (cnt = 0; cnt < 1000; cnt++) {
1810 /* Try to acquire the lock */
1811 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit)
1818 BNX2X_ERR("Timeout\n");
1822 int bnx2x_release_leader_lock(struct bnx2x *bp)
1824 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1827 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1830 u32 resource_bit = (1 << resource);
1831 int func = BP_FUNC(bp);
1832 u32 hw_lock_control_reg;
1834 /* Validating that the resource is within range */
1835 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1836 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1837 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1844 hw_lock_control_reg =
1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1848 /* Validating that the resource is currently taken */
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (!(lock_status & resource_bit)) {
1851 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1852 lock_status, resource_bit);
1856 REG_WR(bp, hw_lock_control_reg, resource_bit);
1861 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1863 /* The GPIO should be swapped if swap register is set and active */
1864 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1865 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1866 int gpio_shift = gpio_num +
1867 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1868 u32 gpio_mask = (1 << gpio_shift);
1872 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1873 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1877 /* read GPIO value */
1878 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1880 /* get the requested pin value */
1881 if ((gpio_reg & gpio_mask) == gpio_mask)
1886 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1891 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1893 /* The GPIO should be swapped if swap register is set and active */
1894 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1895 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1896 int gpio_shift = gpio_num +
1897 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1898 u32 gpio_mask = (1 << gpio_shift);
1901 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1902 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1907 /* read GPIO and mask except the float bits */
1908 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1911 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1913 "Set GPIO %d (shift %d) -> output low\n",
1914 gpio_num, gpio_shift);
1915 /* clear FLOAT and set CLR */
1916 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1917 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1920 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1922 "Set GPIO %d (shift %d) -> output high\n",
1923 gpio_num, gpio_shift);
1924 /* clear FLOAT and set SET */
1925 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1926 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1929 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1931 "Set GPIO %d (shift %d) -> input\n",
1932 gpio_num, gpio_shift);
1934 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1941 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1942 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1947 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1952 /* Any port swapping should be handled by caller. */
1954 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1955 /* read GPIO and mask except the float bits */
1956 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1957 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1959 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1963 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1965 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1968 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1969 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1971 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1974 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1975 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1977 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1981 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1987 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1994 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1996 /* The GPIO should be swapped if swap register is set and active */
1997 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1998 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1999 int gpio_shift = gpio_num +
2000 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2001 u32 gpio_mask = (1 << gpio_shift);
2004 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2005 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2009 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2011 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2014 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2016 "Clear GPIO INT %d (shift %d) -> output low\n",
2017 gpio_num, gpio_shift);
2018 /* clear SET and set CLR */
2019 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2020 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2023 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2025 "Set GPIO INT %d (shift %d) -> output high\n",
2026 gpio_num, gpio_shift);
2027 /* clear CLR and set SET */
2028 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2029 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2036 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2042 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2044 u32 spio_mask = (1 << spio_num);
2047 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2048 (spio_num > MISC_REGISTERS_SPIO_7)) {
2049 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2053 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2054 /* read SPIO and mask except the float bits */
2055 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2058 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2060 /* clear FLOAT and set CLR */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2065 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2067 /* clear FLOAT and set SET */
2068 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2069 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2072 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2073 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2075 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2082 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2088 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2090 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2091 switch (bp->link_vars.ieee_fc &
2092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2093 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2094 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2098 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2099 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2103 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2104 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2108 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2114 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2116 if (!BP_NOMCP(bp)) {
2118 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2119 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2121 * Initialize link parameters structure variables
2122 * It is recommended to turn off RX FC for jumbo frames
2123 * for better performance
2125 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2126 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2128 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2130 bnx2x_acquire_phy_lock(bp);
2132 if (load_mode == LOAD_DIAG) {
2133 struct link_params *lp = &bp->link_params;
2134 lp->loopback_mode = LOOPBACK_XGXS;
2135 /* do PHY loopback at 10G speed, if possible */
2136 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2137 if (lp->speed_cap_mask[cfx_idx] &
2138 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2139 lp->req_line_speed[cfx_idx] =
2142 lp->req_line_speed[cfx_idx] =
2147 if (load_mode == LOAD_LOOPBACK_EXT) {
2148 struct link_params *lp = &bp->link_params;
2149 lp->loopback_mode = LOOPBACK_EXT;
2152 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2154 bnx2x_release_phy_lock(bp);
2156 bnx2x_calc_fc_adv(bp);
2158 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2159 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2160 bnx2x_link_report(bp);
2162 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2163 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2166 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2170 void bnx2x_link_set(struct bnx2x *bp)
2172 if (!BP_NOMCP(bp)) {
2173 bnx2x_acquire_phy_lock(bp);
2174 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2175 bnx2x_release_phy_lock(bp);
2177 bnx2x_calc_fc_adv(bp);
2179 BNX2X_ERR("Bootcode is missing - can not set link\n");
2182 static void bnx2x__link_reset(struct bnx2x *bp)
2184 if (!BP_NOMCP(bp)) {
2185 bnx2x_acquire_phy_lock(bp);
2186 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2187 bnx2x_release_phy_lock(bp);
2189 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2192 void bnx2x_force_link_reset(struct bnx2x *bp)
2194 bnx2x_acquire_phy_lock(bp);
2195 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2196 bnx2x_release_phy_lock(bp);
2199 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2203 if (!BP_NOMCP(bp)) {
2204 bnx2x_acquire_phy_lock(bp);
2205 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2207 bnx2x_release_phy_lock(bp);
2209 BNX2X_ERR("Bootcode is missing - can not test link\n");
2215 /* Calculates the sum of vn_min_rates.
2216 It's needed for further normalizing of the min_rates.
2218 sum of vn_min_rates.
2220 0 - if all the min_rates are 0.
2221 In the later case fainess algorithm should be deactivated.
2222 If not all min_rates are zero then those that are zeroes will be set to 1.
2224 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2225 struct cmng_init_input *input)
2230 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2231 u32 vn_cfg = bp->mf_config[vn];
2232 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2233 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2235 /* Skip hidden vns */
2236 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2238 /* If min rate is zero - set it to 1 */
2239 else if (!vn_min_rate)
2240 vn_min_rate = DEF_MIN_RATE;
2244 input->vnic_min_rate[vn] = vn_min_rate;
2247 /* if ETS or all min rates are zeros - disable fairness */
2248 if (BNX2X_IS_ETS_ENABLED(bp)) {
2249 input->flags.cmng_enables &=
2250 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2251 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2252 } else if (all_zero) {
2253 input->flags.cmng_enables &=
2254 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2256 "All MIN values are zeroes fairness will be disabled\n");
2258 input->flags.cmng_enables |=
2259 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2262 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2263 struct cmng_init_input *input)
2266 u32 vn_cfg = bp->mf_config[vn];
2268 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2271 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2274 /* maxCfg in percents of linkspeed */
2275 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2276 } else /* SD modes */
2277 /* maxCfg is absolute in 100Mb units */
2278 vn_max_rate = maxCfg * 100;
2281 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2283 input->vnic_max_rate[vn] = vn_max_rate;
2287 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2289 if (CHIP_REV_IS_SLOW(bp))
2290 return CMNG_FNS_NONE;
2292 return CMNG_FNS_MINMAX;
2294 return CMNG_FNS_NONE;
2297 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2299 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2302 return; /* what should be the default bvalue in this case */
2304 /* For 2 port configuration the absolute function number formula
2306 * abs_func = 2 * vn + BP_PORT + BP_PATH
2308 * and there are 4 functions per port
2310 * For 4 port configuration it is
2311 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2313 * and there are 2 functions per port
2315 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2316 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2318 if (func >= E1H_FUNC_MAX)
2322 MF_CFG_RD(bp, func_mf_config[func].config);
2324 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2325 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2326 bp->flags |= MF_FUNC_DIS;
2328 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2329 bp->flags &= ~MF_FUNC_DIS;
2333 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2335 struct cmng_init_input input;
2336 memset(&input, 0, sizeof(struct cmng_init_input));
2338 input.port_rate = bp->link_vars.line_speed;
2340 if (cmng_type == CMNG_FNS_MINMAX) {
2343 /* read mf conf from shmem */
2345 bnx2x_read_mf_cfg(bp);
2347 /* vn_weight_sum and enable fairness if not 0 */
2348 bnx2x_calc_vn_min(bp, &input);
2350 /* calculate and set min-max rate for each vn */
2352 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2353 bnx2x_calc_vn_max(bp, vn, &input);
2355 /* always enable rate shaping and fairness */
2356 input.flags.cmng_enables |=
2357 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2359 bnx2x_init_cmng(&input, &bp->cmng);
2363 /* rate shaping and fairness are disabled */
2365 "rate shaping and fairness are disabled\n");
2368 static void storm_memset_cmng(struct bnx2x *bp,
2369 struct cmng_init *cmng,
2373 size_t size = sizeof(struct cmng_struct_per_port);
2375 u32 addr = BAR_XSTRORM_INTMEM +
2376 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2378 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2380 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2381 int func = func_by_vn(bp, vn);
2383 addr = BAR_XSTRORM_INTMEM +
2384 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2385 size = sizeof(struct rate_shaping_vars_per_vn);
2386 __storm_memset_struct(bp, addr, size,
2387 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2389 addr = BAR_XSTRORM_INTMEM +
2390 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2391 size = sizeof(struct fairness_vars_per_vn);
2392 __storm_memset_struct(bp, addr, size,
2393 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2397 /* This function is called upon link interrupt */
2398 static void bnx2x_link_attn(struct bnx2x *bp)
2400 /* Make sure that we are synced with the current statistics */
2401 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2403 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2405 if (bp->link_vars.link_up) {
2407 /* dropless flow control */
2408 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2409 int port = BP_PORT(bp);
2410 u32 pause_enabled = 0;
2412 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2415 REG_WR(bp, BAR_USTRORM_INTMEM +
2416 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2420 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2421 struct host_port_stats *pstats;
2423 pstats = bnx2x_sp(bp, port_stats);
2424 /* reset old mac stats */
2425 memset(&(pstats->mac_stx[0]), 0,
2426 sizeof(struct mac_stx));
2428 if (bp->state == BNX2X_STATE_OPEN)
2429 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2432 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2433 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2435 if (cmng_fns != CMNG_FNS_NONE) {
2436 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2437 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2439 /* rate shaping and fairness are disabled */
2441 "single function mode without fairness\n");
2444 __bnx2x_link_report(bp);
2447 bnx2x_link_sync_notify(bp);
2450 void bnx2x__link_status_update(struct bnx2x *bp)
2452 if (bp->state != BNX2X_STATE_OPEN)
2455 /* read updated dcb configuration */
2456 bnx2x_dcbx_pmf_update(bp);
2458 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2460 if (bp->link_vars.link_up)
2461 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2463 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2465 /* indicate link status */
2466 bnx2x_link_report(bp);
2469 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2470 u16 vlan_val, u8 allowed_prio)
2472 struct bnx2x_func_state_params func_params = {0};
2473 struct bnx2x_func_afex_update_params *f_update_params =
2474 &func_params.params.afex_update;
2476 func_params.f_obj = &bp->func_obj;
2477 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2479 /* no need to wait for RAMROD completion, so don't
2480 * set RAMROD_COMP_WAIT flag
2483 f_update_params->vif_id = vifid;
2484 f_update_params->afex_default_vlan = vlan_val;
2485 f_update_params->allowed_priorities = allowed_prio;
2487 /* if ramrod can not be sent, response to MCP immediately */
2488 if (bnx2x_func_state_change(bp, &func_params) < 0)
2489 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2494 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2495 u16 vif_index, u8 func_bit_map)
2497 struct bnx2x_func_state_params func_params = {0};
2498 struct bnx2x_func_afex_viflists_params *update_params =
2499 &func_params.params.afex_viflists;
2503 /* validate only LIST_SET and LIST_GET are received from switch */
2504 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2505 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2508 func_params.f_obj = &bp->func_obj;
2509 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2511 /* set parameters according to cmd_type */
2512 update_params->afex_vif_list_command = cmd_type;
2513 update_params->vif_list_index = cpu_to_le16(vif_index);
2514 update_params->func_bit_map =
2515 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2516 update_params->func_to_clear = 0;
2518 (cmd_type == VIF_LIST_RULE_GET) ?
2519 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2520 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2522 /* if ramrod can not be sent, respond to MCP immediately for
2523 * SET and GET requests (other are not triggered from MCP)
2525 rc = bnx2x_func_state_change(bp, &func_params);
2527 bnx2x_fw_command(bp, drv_msg_code, 0);
2532 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2534 struct afex_stats afex_stats;
2535 u32 func = BP_ABS_FUNC(bp);
2542 u32 addr_to_write, vifid, addrs, stats_type, i;
2544 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2545 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2547 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2548 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2551 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2552 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2553 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2555 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2557 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2561 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2562 addr_to_write = SHMEM2_RD(bp,
2563 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2564 stats_type = SHMEM2_RD(bp,
2565 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2568 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2571 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2573 /* write response to scratchpad, for MCP */
2574 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2575 REG_WR(bp, addr_to_write + i*sizeof(u32),
2576 *(((u32 *)(&afex_stats))+i));
2578 /* send ack message to MCP */
2579 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2582 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2583 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2584 bp->mf_config[BP_VN(bp)] = mf_config;
2586 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2589 /* if VIF_SET is "enabled" */
2590 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2591 /* set rate limit directly to internal RAM */
2592 struct cmng_init_input cmng_input;
2593 struct rate_shaping_vars_per_vn m_rs_vn;
2594 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2595 u32 addr = BAR_XSTRORM_INTMEM +
2596 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2598 bp->mf_config[BP_VN(bp)] = mf_config;
2600 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2601 m_rs_vn.vn_counter.rate =
2602 cmng_input.vnic_max_rate[BP_VN(bp)];
2603 m_rs_vn.vn_counter.quota =
2604 (m_rs_vn.vn_counter.rate *
2605 RS_PERIODIC_TIMEOUT_USEC) / 8;
2607 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2609 /* read relevant values from mf_cfg struct in shmem */
2611 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2612 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2613 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2615 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2616 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2617 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2618 vlan_prio = (mf_config &
2619 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2620 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2621 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2624 func_mf_config[func].afex_config) &
2625 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2626 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2629 func_mf_config[func].afex_config) &
2630 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2631 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2633 /* send ramrod to FW, return in case of failure */
2634 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2638 bp->afex_def_vlan_tag = vlan_val;
2639 bp->afex_vlan_mode = vlan_mode;
2641 /* notify link down because BP->flags is disabled */
2642 bnx2x_link_report(bp);
2644 /* send INVALID VIF ramrod to FW */
2645 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2647 /* Reset the default afex VLAN */
2648 bp->afex_def_vlan_tag = -1;
2653 static void bnx2x_pmf_update(struct bnx2x *bp)
2655 int port = BP_PORT(bp);
2659 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2662 * We need the mb() to ensure the ordering between the writing to
2663 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2667 /* queue a periodic task */
2668 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2670 bnx2x_dcbx_pmf_update(bp);
2672 /* enable nig attention */
2673 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2674 if (bp->common.int_block == INT_BLOCK_HC) {
2675 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2676 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2677 } else if (!CHIP_IS_E1x(bp)) {
2678 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2679 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2682 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2690 * General service functions
2693 /* send the MCP a request, block until there is a reply */
2694 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2696 int mb_idx = BP_FW_MB_IDX(bp);
2700 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2702 mutex_lock(&bp->fw_mb_mutex);
2704 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2705 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2707 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2708 (command | seq), param);
2711 /* let the FW do it's magic ... */
2714 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2716 /* Give the FW up to 5 second (500*10ms) */
2717 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2719 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2720 cnt*delay, rc, seq);
2722 /* is this a reply to our command? */
2723 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2724 rc &= FW_MSG_CODE_MASK;
2727 BNX2X_ERR("FW failed to respond!\n");
2731 mutex_unlock(&bp->fw_mb_mutex);
2737 static void storm_memset_func_cfg(struct bnx2x *bp,
2738 struct tstorm_eth_function_common_config *tcfg,
2741 size_t size = sizeof(struct tstorm_eth_function_common_config);
2743 u32 addr = BAR_TSTRORM_INTMEM +
2744 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2746 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2749 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2751 if (CHIP_IS_E1x(bp)) {
2752 struct tstorm_eth_function_common_config tcfg = {0};
2754 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2757 /* Enable the function in the FW */
2758 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2759 storm_memset_func_en(bp, p->func_id, 1);
2762 if (p->func_flgs & FUNC_FLG_SPQ) {
2763 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2764 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2765 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2770 * bnx2x_get_tx_only_flags - Return common flags
2774 * @zero_stats TRUE if statistics zeroing is needed
2776 * Return the flags that are common for the Tx-only and not normal connections.
2778 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2779 struct bnx2x_fastpath *fp,
2782 unsigned long flags = 0;
2784 /* PF driver will always initialize the Queue to an ACTIVE state */
2785 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2787 /* tx only connections collect statistics (on the same index as the
2788 * parent connection). The statistics are zeroed when the parent
2789 * connection is initialized.
2792 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2794 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2800 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2801 struct bnx2x_fastpath *fp,
2804 unsigned long flags = 0;
2806 /* calculate other queue flags */
2808 __set_bit(BNX2X_Q_FLG_OV, &flags);
2810 if (IS_FCOE_FP(fp)) {
2811 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2812 /* For FCoE - force usage of default priority (for afex) */
2813 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2816 if (!fp->disable_tpa) {
2817 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2818 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2819 if (fp->mode == TPA_MODE_GRO)
2820 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2824 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2825 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2828 /* Always set HW VLAN stripping */
2829 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2831 /* configure silent vlan removal */
2833 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2836 return flags | bnx2x_get_common_flags(bp, fp, true);
2839 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2840 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2843 gen_init->stat_id = bnx2x_stats_id(fp);
2844 gen_init->spcl_id = fp->cl_id;
2846 /* Always use mini-jumbo MTU for FCoE L2 ring */
2848 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2850 gen_init->mtu = bp->dev->mtu;
2852 gen_init->cos = cos;
2855 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2856 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2857 struct bnx2x_rxq_setup_params *rxq_init)
2861 u16 tpa_agg_size = 0;
2863 if (!fp->disable_tpa) {
2864 pause->sge_th_lo = SGE_TH_LO(bp);
2865 pause->sge_th_hi = SGE_TH_HI(bp);
2867 /* validate SGE ring has enough to cross high threshold */
2868 WARN_ON(bp->dropless_fc &&
2869 pause->sge_th_hi + FW_PREFETCH_CNT >
2870 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2872 tpa_agg_size = min_t(u32,
2873 (min_t(u32, 8, MAX_SKB_FRAGS) *
2874 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2875 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2877 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2878 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2879 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2883 /* pause - not for e1 */
2884 if (!CHIP_IS_E1(bp)) {
2885 pause->bd_th_lo = BD_TH_LO(bp);
2886 pause->bd_th_hi = BD_TH_HI(bp);
2888 pause->rcq_th_lo = RCQ_TH_LO(bp);
2889 pause->rcq_th_hi = RCQ_TH_HI(bp);
2891 * validate that rings have enough entries to cross
2894 WARN_ON(bp->dropless_fc &&
2895 pause->bd_th_hi + FW_PREFETCH_CNT >
2897 WARN_ON(bp->dropless_fc &&
2898 pause->rcq_th_hi + FW_PREFETCH_CNT >
2899 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2905 rxq_init->dscr_map = fp->rx_desc_mapping;
2906 rxq_init->sge_map = fp->rx_sge_mapping;
2907 rxq_init->rcq_map = fp->rx_comp_mapping;
2908 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2910 /* This should be a maximum number of data bytes that may be
2911 * placed on the BD (not including paddings).
2913 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2914 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2916 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2917 rxq_init->tpa_agg_sz = tpa_agg_size;
2918 rxq_init->sge_buf_sz = sge_sz;
2919 rxq_init->max_sges_pkt = max_sge;
2920 rxq_init->rss_engine_id = BP_FUNC(bp);
2921 rxq_init->mcast_engine_id = BP_FUNC(bp);
2923 /* Maximum number or simultaneous TPA aggregation for this Queue.
2925 * For PF Clients it should be the maximum avaliable number.
2926 * VF driver(s) may want to define it to a smaller value.
2928 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2930 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2931 rxq_init->fw_sb_id = fp->fw_sb_id;
2934 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2936 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2937 /* configure silent vlan removal
2938 * if multi function mode is afex, then mask default vlan
2940 if (IS_MF_AFEX(bp)) {
2941 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2942 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2946 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2947 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2950 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2951 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2952 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2953 txq_init->fw_sb_id = fp->fw_sb_id;
2956 * set the tss leading client id for TX classfication ==
2957 * leading RSS client id
2959 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2961 if (IS_FCOE_FP(fp)) {
2962 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2963 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2967 static void bnx2x_pf_init(struct bnx2x *bp)
2969 struct bnx2x_func_init_params func_init = {0};
2970 struct event_ring_data eq_data = { {0} };
2973 if (!CHIP_IS_E1x(bp)) {
2974 /* reset IGU PF statistics: MSIX + ATTN */
2976 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2977 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2978 (CHIP_MODE_IS_4_PORT(bp) ?
2979 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2981 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2982 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2983 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2984 (CHIP_MODE_IS_4_PORT(bp) ?
2985 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2988 /* function setup flags */
2989 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2991 /* This flag is relevant for E1x only.
2992 * E2 doesn't have a TPA configuration in a function level.
2994 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2996 func_init.func_flgs = flags;
2997 func_init.pf_id = BP_FUNC(bp);
2998 func_init.func_id = BP_FUNC(bp);
2999 func_init.spq_map = bp->spq_mapping;
3000 func_init.spq_prod = bp->spq_prod_idx;
3002 bnx2x_func_init(bp, &func_init);
3004 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3007 * Congestion management values depend on the link rate
3008 * There is no active link so initial link rate is set to 10 Gbps.
3009 * When the link comes up The congestion management values are
3010 * re-calculated according to the actual link rate.
3012 bp->link_vars.line_speed = SPEED_10000;
3013 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3015 /* Only the PMF sets the HW */
3017 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3019 /* init Event Queue */
3020 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3021 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3022 eq_data.producer = bp->eq_prod;
3023 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3024 eq_data.sb_id = DEF_SB_ID;
3025 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3029 static void bnx2x_e1h_disable(struct bnx2x *bp)
3031 int port = BP_PORT(bp);
3033 bnx2x_tx_disable(bp);
3035 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3038 static void bnx2x_e1h_enable(struct bnx2x *bp)
3040 int port = BP_PORT(bp);
3042 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3044 /* Tx queue should be only reenabled */
3045 netif_tx_wake_all_queues(bp->dev);
3048 * Should not call netif_carrier_on since it will be called if the link
3049 * is up when checking for link state
3053 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3055 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3057 struct eth_stats_info *ether_stat =
3058 &bp->slowpath->drv_info_to_mcp.ether_stat;
3060 /* leave last char as NULL */
3061 memcpy(ether_stat->version, DRV_MODULE_VERSION,
3062 ETH_STAT_INFO_VERSION_LEN - 1);
3064 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3065 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3066 ether_stat->mac_local);
3068 ether_stat->mtu_size = bp->dev->mtu;
3070 if (bp->dev->features & NETIF_F_RXCSUM)
3071 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3072 if (bp->dev->features & NETIF_F_TSO)
3073 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3074 ether_stat->feature_flags |= bp->common.boot_mode;
3076 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3078 ether_stat->txq_size = bp->tx_ring_size;
3079 ether_stat->rxq_size = bp->rx_ring_size;
3082 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3085 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3086 struct fcoe_stats_info *fcoe_stat =
3087 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3089 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3090 bp->fip_mac, ETH_ALEN);
3092 fcoe_stat->qos_priority =
3093 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3095 /* insert FCoE stats from ramrod response */
3097 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3098 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3099 tstorm_queue_statistics;
3101 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3102 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3103 xstorm_queue_statistics;
3105 struct fcoe_statistics_params *fw_fcoe_stat =
3106 &bp->fw_stats_data->fcoe;
3108 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3109 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3111 ADD_64(fcoe_stat->rx_bytes_hi,
3112 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3113 fcoe_stat->rx_bytes_lo,
3114 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3116 ADD_64(fcoe_stat->rx_bytes_hi,
3117 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3118 fcoe_stat->rx_bytes_lo,
3119 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3121 ADD_64(fcoe_stat->rx_bytes_hi,
3122 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3123 fcoe_stat->rx_bytes_lo,
3124 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3126 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3129 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3132 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3133 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3135 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3136 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3138 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3139 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3141 ADD_64(fcoe_stat->tx_bytes_hi,
3142 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3143 fcoe_stat->tx_bytes_lo,
3144 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3146 ADD_64(fcoe_stat->tx_bytes_hi,
3147 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3148 fcoe_stat->tx_bytes_lo,
3149 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3151 ADD_64(fcoe_stat->tx_bytes_hi,
3152 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3153 fcoe_stat->tx_bytes_lo,
3154 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3156 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3159 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160 fcoe_q_xstorm_stats->ucast_pkts_sent);
3162 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3163 fcoe_q_xstorm_stats->bcast_pkts_sent);
3165 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3166 fcoe_q_xstorm_stats->mcast_pkts_sent);
3169 /* ask L5 driver to add data to the struct */
3170 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3174 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3177 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3178 struct iscsi_stats_info *iscsi_stat =
3179 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3181 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3182 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3184 iscsi_stat->qos_priority =
3185 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3187 /* ask L5 driver to add data to the struct */
3188 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3192 /* called due to MCP event (on pmf):
3193 * reread new bandwidth configuration
3195 * notify others function about the change
3197 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3199 if (bp->link_vars.link_up) {
3200 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3201 bnx2x_link_sync_notify(bp);
3203 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3206 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3208 bnx2x_config_mf_bw(bp);
3209 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3212 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3214 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3215 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3218 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3220 enum drv_info_opcode op_code;
3221 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3223 /* if drv_info version supported by MFW doesn't match - send NACK */
3224 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3225 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3229 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3230 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3232 memset(&bp->slowpath->drv_info_to_mcp, 0,
3233 sizeof(union drv_info_to_mcp));
3236 case ETH_STATS_OPCODE:
3237 bnx2x_drv_info_ether_stat(bp);
3239 case FCOE_STATS_OPCODE:
3240 bnx2x_drv_info_fcoe_stat(bp);
3242 case ISCSI_STATS_OPCODE:
3243 bnx2x_drv_info_iscsi_stat(bp);
3246 /* if op code isn't supported - send NACK */
3247 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3251 /* if we got drv_info attn from MFW then these fields are defined in
3254 SHMEM2_WR(bp, drv_info_host_addr_lo,
3255 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3256 SHMEM2_WR(bp, drv_info_host_addr_hi,
3257 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3259 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3262 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3264 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3266 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3269 * This is the only place besides the function initialization
3270 * where the bp->flags can change so it is done without any
3273 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3274 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3275 bp->flags |= MF_FUNC_DIS;
3277 bnx2x_e1h_disable(bp);
3279 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3280 bp->flags &= ~MF_FUNC_DIS;
3282 bnx2x_e1h_enable(bp);
3284 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3286 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3287 bnx2x_config_mf_bw(bp);
3288 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3291 /* Report results to MCP */
3293 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3295 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3298 /* must be called under the spq lock */
3299 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3301 struct eth_spe *next_spe = bp->spq_prod_bd;
3303 if (bp->spq_prod_bd == bp->spq_last_bd) {
3304 bp->spq_prod_bd = bp->spq;
3305 bp->spq_prod_idx = 0;
3306 DP(BNX2X_MSG_SP, "end of spq\n");
3314 /* must be called under the spq lock */
3315 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3317 int func = BP_FUNC(bp);
3320 * Make sure that BD data is updated before writing the producer:
3321 * BD data is written to the memory, the producer is read from the
3322 * memory, thus we need a full memory barrier to ensure the ordering.
3326 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3332 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3334 * @cmd: command to check
3335 * @cmd_type: command type
3337 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3339 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3340 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3341 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3342 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3343 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3344 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3345 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3354 * bnx2x_sp_post - place a single command on an SP ring
3356 * @bp: driver handle
3357 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3358 * @cid: SW CID the command is related to
3359 * @data_hi: command private data address (high 32 bits)
3360 * @data_lo: command private data address (low 32 bits)
3361 * @cmd_type: command type (e.g. NONE, ETH)
3363 * SP data is handled as if it's always an address pair, thus data fields are
3364 * not swapped to little endian in upper functions. Instead this function swaps
3365 * data as if it's two u32 fields.
3367 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3368 u32 data_hi, u32 data_lo, int cmd_type)
3370 struct eth_spe *spe;
3372 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3374 #ifdef BNX2X_STOP_ON_ERROR
3375 if (unlikely(bp->panic)) {
3376 BNX2X_ERR("Can't post SP when there is panic\n");
3381 spin_lock_bh(&bp->spq_lock);
3384 if (!atomic_read(&bp->eq_spq_left)) {
3385 BNX2X_ERR("BUG! EQ ring full!\n");
3386 spin_unlock_bh(&bp->spq_lock);
3390 } else if (!atomic_read(&bp->cq_spq_left)) {
3391 BNX2X_ERR("BUG! SPQ ring full!\n");
3392 spin_unlock_bh(&bp->spq_lock);
3397 spe = bnx2x_sp_get_next(bp);
3399 /* CID needs port number to be encoded int it */
3400 spe->hdr.conn_and_cmd_data =
3401 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3404 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3406 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3407 SPE_HDR_FUNCTION_ID);
3409 spe->hdr.type = cpu_to_le16(type);
3411 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3412 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3415 * It's ok if the actual decrement is issued towards the memory
3416 * somewhere between the spin_lock and spin_unlock. Thus no
3417 * more explict memory barrier is needed.
3420 atomic_dec(&bp->eq_spq_left);
3422 atomic_dec(&bp->cq_spq_left);
3426 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3427 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3428 (u32)(U64_LO(bp->spq_mapping) +
3429 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3430 HW_CID(bp, cid), data_hi, data_lo, type,
3431 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3433 bnx2x_sp_prod_update(bp);
3434 spin_unlock_bh(&bp->spq_lock);
3438 /* acquire split MCP access lock register */
3439 static int bnx2x_acquire_alr(struct bnx2x *bp)
3445 for (j = 0; j < 1000; j++) {
3447 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3448 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3449 if (val & (1L << 31))
3454 if (!(val & (1L << 31))) {
3455 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3462 /* release split MCP access lock register */
3463 static void bnx2x_release_alr(struct bnx2x *bp)
3465 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3468 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3469 #define BNX2X_DEF_SB_IDX 0x0002
3471 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3473 struct host_sp_status_block *def_sb = bp->def_status_blk;
3476 barrier(); /* status block is written to by the chip */
3477 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3478 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3479 rc |= BNX2X_DEF_SB_ATT_IDX;
3482 if (bp->def_idx != def_sb->sp_sb.running_index) {
3483 bp->def_idx = def_sb->sp_sb.running_index;
3484 rc |= BNX2X_DEF_SB_IDX;
3487 /* Do not reorder: indecies reading should complete before handling */
3493 * slow path service functions
3496 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3498 int port = BP_PORT(bp);
3499 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3500 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3501 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3502 NIG_REG_MASK_INTERRUPT_PORT0;
3507 if (bp->attn_state & asserted)
3508 BNX2X_ERR("IGU ERROR\n");
3510 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3511 aeu_mask = REG_RD(bp, aeu_addr);
3513 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3514 aeu_mask, asserted);
3515 aeu_mask &= ~(asserted & 0x3ff);
3516 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3518 REG_WR(bp, aeu_addr, aeu_mask);
3519 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3521 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3522 bp->attn_state |= asserted;
3523 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3525 if (asserted & ATTN_HARD_WIRED_MASK) {
3526 if (asserted & ATTN_NIG_FOR_FUNC) {
3528 bnx2x_acquire_phy_lock(bp);
3530 /* save nig interrupt mask */
3531 nig_mask = REG_RD(bp, nig_int_mask_addr);
3533 /* If nig_mask is not set, no need to call the update
3537 REG_WR(bp, nig_int_mask_addr, 0);
3539 bnx2x_link_attn(bp);
3542 /* handle unicore attn? */
3544 if (asserted & ATTN_SW_TIMER_4_FUNC)
3545 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3547 if (asserted & GPIO_2_FUNC)
3548 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3550 if (asserted & GPIO_3_FUNC)
3551 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3553 if (asserted & GPIO_4_FUNC)
3554 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3557 if (asserted & ATTN_GENERAL_ATTN_1) {
3558 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3559 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3561 if (asserted & ATTN_GENERAL_ATTN_2) {
3562 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3563 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3565 if (asserted & ATTN_GENERAL_ATTN_3) {
3566 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3567 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3570 if (asserted & ATTN_GENERAL_ATTN_4) {
3571 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3572 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3574 if (asserted & ATTN_GENERAL_ATTN_5) {
3575 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3576 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3578 if (asserted & ATTN_GENERAL_ATTN_6) {
3579 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3580 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3584 } /* if hardwired */
3586 if (bp->common.int_block == INT_BLOCK_HC)
3587 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3588 COMMAND_REG_ATTN_BITS_SET);
3590 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3592 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3593 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3594 REG_WR(bp, reg_addr, asserted);
3596 /* now set back the mask */
3597 if (asserted & ATTN_NIG_FOR_FUNC) {
3598 REG_WR(bp, nig_int_mask_addr, nig_mask);
3599 bnx2x_release_phy_lock(bp);
3603 static void bnx2x_fan_failure(struct bnx2x *bp)
3605 int port = BP_PORT(bp);
3607 /* mark the failure */
3610 dev_info.port_hw_config[port].external_phy_config);
3612 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3613 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3614 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3617 /* log the failure */
3618 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3619 "Please contact OEM Support for assistance\n");
3622 * Scheudle device reset (unload)
3623 * This is due to some boards consuming sufficient power when driver is
3624 * up to overheat if fan fails.
3626 smp_mb__before_clear_bit();
3627 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3628 smp_mb__after_clear_bit();
3629 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3633 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3635 int port = BP_PORT(bp);
3639 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3640 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3642 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3644 val = REG_RD(bp, reg_offset);
3645 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3646 REG_WR(bp, reg_offset, val);
3648 BNX2X_ERR("SPIO5 hw attention\n");
3650 /* Fan failure attention */
3651 bnx2x_hw_reset_phy(&bp->link_params);
3652 bnx2x_fan_failure(bp);
3655 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3656 bnx2x_acquire_phy_lock(bp);
3657 bnx2x_handle_module_detect_int(&bp->link_params);
3658 bnx2x_release_phy_lock(bp);
3661 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3663 val = REG_RD(bp, reg_offset);
3664 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3665 REG_WR(bp, reg_offset, val);
3667 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3668 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3673 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3677 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3679 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3680 BNX2X_ERR("DB hw attention 0x%x\n", val);
3681 /* DORQ discard attention */
3683 BNX2X_ERR("FATAL error from DORQ\n");
3686 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3688 int port = BP_PORT(bp);
3691 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3692 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3694 val = REG_RD(bp, reg_offset);
3695 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3696 REG_WR(bp, reg_offset, val);
3698 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3699 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3704 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3708 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3710 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3711 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3712 /* CFC error attention */
3714 BNX2X_ERR("FATAL error from CFC\n");
3717 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3718 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3719 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3720 /* RQ_USDMDP_FIFO_OVERFLOW */
3722 BNX2X_ERR("FATAL error from PXP\n");
3724 if (!CHIP_IS_E1x(bp)) {
3725 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3726 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3730 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3732 int port = BP_PORT(bp);
3735 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3736 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3738 val = REG_RD(bp, reg_offset);
3739 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3740 REG_WR(bp, reg_offset, val);
3742 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3743 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3748 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3752 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3754 if (attn & BNX2X_PMF_LINK_ASSERT) {
3755 int func = BP_FUNC(bp);
3757 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3758 bnx2x_read_mf_cfg(bp);
3759 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3760 func_mf_config[BP_ABS_FUNC(bp)].config);
3762 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3763 if (val & DRV_STATUS_DCC_EVENT_MASK)
3765 (val & DRV_STATUS_DCC_EVENT_MASK));
3767 if (val & DRV_STATUS_SET_MF_BW)
3768 bnx2x_set_mf_bw(bp);
3770 if (val & DRV_STATUS_DRV_INFO_REQ)
3771 bnx2x_handle_drv_info_req(bp);
3772 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3773 bnx2x_pmf_update(bp);
3776 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3777 bp->dcbx_enabled > 0)
3778 /* start dcbx state machine */
3779 bnx2x_dcbx_set_params(bp,
3780 BNX2X_DCBX_STATE_NEG_RECEIVED);
3781 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3782 bnx2x_handle_afex_cmd(bp,
3783 val & DRV_STATUS_AFEX_EVENT_MASK);
3784 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3785 bnx2x_handle_eee_event(bp);
3786 if (bp->link_vars.periodic_flags &
3787 PERIODIC_FLAGS_LINK_EVENT) {
3788 /* sync with link */
3789 bnx2x_acquire_phy_lock(bp);
3790 bp->link_vars.periodic_flags &=
3791 ~PERIODIC_FLAGS_LINK_EVENT;
3792 bnx2x_release_phy_lock(bp);
3794 bnx2x_link_sync_notify(bp);
3795 bnx2x_link_report(bp);
3797 /* Always call it here: bnx2x_link_report() will
3798 * prevent the link indication duplication.
3800 bnx2x__link_status_update(bp);
3801 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3803 BNX2X_ERR("MC assert!\n");
3804 bnx2x_mc_assert(bp);
3805 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3806 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3807 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3811 } else if (attn & BNX2X_MCP_ASSERT) {
3813 BNX2X_ERR("MCP assert!\n");
3814 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3818 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3821 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3822 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3823 if (attn & BNX2X_GRC_TIMEOUT) {
3824 val = CHIP_IS_E1(bp) ? 0 :
3825 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3826 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3828 if (attn & BNX2X_GRC_RSV) {
3829 val = CHIP_IS_E1(bp) ? 0 :
3830 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3831 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3833 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3839 * 0-7 - Engine0 load counter.
3840 * 8-15 - Engine1 load counter.
3841 * 16 - Engine0 RESET_IN_PROGRESS bit.
3842 * 17 - Engine1 RESET_IN_PROGRESS bit.
3843 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3845 * 19 - Engine1 ONE_IS_LOADED.
3846 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3847 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3848 * just the one belonging to its engine).
3851 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3853 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3854 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3855 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3856 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3857 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3858 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3859 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3862 * Set the GLOBAL_RESET bit.
3864 * Should be run under rtnl lock
3866 void bnx2x_set_reset_global(struct bnx2x *bp)
3869 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3870 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3871 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3872 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3876 * Clear the GLOBAL_RESET bit.
3878 * Should be run under rtnl lock
3880 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3883 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3884 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3885 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3886 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3890 * Checks the GLOBAL_RESET bit.
3892 * should be run under rtnl lock
3894 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3896 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3898 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3899 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3903 * Clear RESET_IN_PROGRESS bit for the current engine.
3905 * Should be run under rtnl lock
3907 static void bnx2x_set_reset_done(struct bnx2x *bp)
3910 u32 bit = BP_PATH(bp) ?
3911 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3912 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3913 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3917 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3919 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3923 * Set RESET_IN_PROGRESS for the current engine.
3925 * should be run under rtnl lock
3927 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3930 u32 bit = BP_PATH(bp) ?
3931 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3932 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3933 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3937 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3938 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3942 * Checks the RESET_IN_PROGRESS bit for the given engine.
3943 * should be run under rtnl lock
3945 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3947 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3949 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3951 /* return false if bit is set */
3952 return (val & bit) ? false : true;
3956 * set pf load for the current pf.
3958 * should be run under rtnl lock
3960 void bnx2x_set_pf_load(struct bnx2x *bp)
3963 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3964 BNX2X_PATH0_LOAD_CNT_MASK;
3965 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3966 BNX2X_PATH0_LOAD_CNT_SHIFT;
3968 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3969 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3971 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3973 /* get the current counter value */
3974 val1 = (val & mask) >> shift;
3976 /* set bit of that PF */
3977 val1 |= (1 << bp->pf_num);
3979 /* clear the old value */
3982 /* set the new one */
3983 val |= ((val1 << shift) & mask);
3985 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3986 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3990 * bnx2x_clear_pf_load - clear pf load mark
3992 * @bp: driver handle
3994 * Should be run under rtnl lock.
3995 * Decrements the load counter for the current engine. Returns
3996 * whether other functions are still loaded
3998 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4001 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4002 BNX2X_PATH0_LOAD_CNT_MASK;
4003 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4004 BNX2X_PATH0_LOAD_CNT_SHIFT;
4006 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4007 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4008 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4010 /* get the current counter value */
4011 val1 = (val & mask) >> shift;
4013 /* clear bit of that PF */
4014 val1 &= ~(1 << bp->pf_num);
4016 /* clear the old value */
4019 /* set the new one */
4020 val |= ((val1 << shift) & mask);
4022 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4023 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4028 * Read the load status for the current engine.
4030 * should be run under rtnl lock
4032 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4034 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4035 BNX2X_PATH0_LOAD_CNT_MASK);
4036 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4037 BNX2X_PATH0_LOAD_CNT_SHIFT);
4038 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4040 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4042 val = (val & mask) >> shift;
4044 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4050 static void _print_next_block(int idx, const char *blk)
4052 pr_cont("%s%s", idx ? ", " : "", blk);
4055 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4060 for (i = 0; sig; i++) {
4061 cur_bit = ((u32)0x1 << i);
4062 if (sig & cur_bit) {
4064 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4066 _print_next_block(par_num++, "BRB");
4068 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4070 _print_next_block(par_num++, "PARSER");
4072 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4074 _print_next_block(par_num++, "TSDM");
4076 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4078 _print_next_block(par_num++,
4081 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4083 _print_next_block(par_num++, "TCM");
4085 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4087 _print_next_block(par_num++, "TSEMI");
4089 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4091 _print_next_block(par_num++, "XPB");
4103 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4104 bool *global, bool print)
4108 for (i = 0; sig; i++) {
4109 cur_bit = ((u32)0x1 << i);
4110 if (sig & cur_bit) {
4112 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4114 _print_next_block(par_num++, "PBF");
4116 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4118 _print_next_block(par_num++, "QM");
4120 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4122 _print_next_block(par_num++, "TM");
4124 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4126 _print_next_block(par_num++, "XSDM");
4128 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4130 _print_next_block(par_num++, "XCM");
4132 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4134 _print_next_block(par_num++, "XSEMI");
4136 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4138 _print_next_block(par_num++,
4141 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4143 _print_next_block(par_num++, "NIG");
4145 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4147 _print_next_block(par_num++,
4151 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4153 _print_next_block(par_num++, "DEBUG");
4155 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4157 _print_next_block(par_num++, "USDM");
4159 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4161 _print_next_block(par_num++, "UCM");
4163 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4165 _print_next_block(par_num++, "USEMI");
4167 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4169 _print_next_block(par_num++, "UPB");
4171 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4173 _print_next_block(par_num++, "CSDM");
4175 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4177 _print_next_block(par_num++, "CCM");
4189 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4194 for (i = 0; sig; i++) {
4195 cur_bit = ((u32)0x1 << i);
4196 if (sig & cur_bit) {
4198 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4200 _print_next_block(par_num++, "CSEMI");
4202 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4204 _print_next_block(par_num++, "PXP");
4206 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4208 _print_next_block(par_num++,
4209 "PXPPCICLOCKCLIENT");
4211 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4213 _print_next_block(par_num++, "CFC");
4215 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4217 _print_next_block(par_num++, "CDU");
4219 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4221 _print_next_block(par_num++, "DMAE");
4223 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4225 _print_next_block(par_num++, "IGU");
4227 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4229 _print_next_block(par_num++, "MISC");
4241 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4242 bool *global, bool print)
4246 for (i = 0; sig; i++) {
4247 cur_bit = ((u32)0x1 << i);
4248 if (sig & cur_bit) {
4250 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4252 _print_next_block(par_num++, "MCP ROM");
4255 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4257 _print_next_block(par_num++,
4261 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4263 _print_next_block(par_num++,
4267 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4269 _print_next_block(par_num++,
4283 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4288 for (i = 0; sig; i++) {
4289 cur_bit = ((u32)0x1 << i);
4290 if (sig & cur_bit) {
4292 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4294 _print_next_block(par_num++, "PGLUE_B");
4296 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4298 _print_next_block(par_num++, "ATC");
4310 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4313 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4314 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4315 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4316 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4317 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4319 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4320 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4321 sig[0] & HW_PRTY_ASSERT_SET_0,
4322 sig[1] & HW_PRTY_ASSERT_SET_1,
4323 sig[2] & HW_PRTY_ASSERT_SET_2,
4324 sig[3] & HW_PRTY_ASSERT_SET_3,
4325 sig[4] & HW_PRTY_ASSERT_SET_4);
4328 "Parity errors detected in blocks: ");
4329 par_num = bnx2x_check_blocks_with_parity0(
4330 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4331 par_num = bnx2x_check_blocks_with_parity1(
4332 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4333 par_num = bnx2x_check_blocks_with_parity2(
4334 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4335 par_num = bnx2x_check_blocks_with_parity3(
4336 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4337 par_num = bnx2x_check_blocks_with_parity4(
4338 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4349 * bnx2x_chk_parity_attn - checks for parity attentions.
4351 * @bp: driver handle
4352 * @global: true if there was a global attention
4353 * @print: show parity attention in syslog
4355 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4357 struct attn_route attn = { {0} };
4358 int port = BP_PORT(bp);
4360 attn.sig[0] = REG_RD(bp,
4361 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4363 attn.sig[1] = REG_RD(bp,
4364 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4366 attn.sig[2] = REG_RD(bp,
4367 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4369 attn.sig[3] = REG_RD(bp,
4370 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4373 if (!CHIP_IS_E1x(bp))
4374 attn.sig[4] = REG_RD(bp,
4375 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4378 return bnx2x_parity_attn(bp, global, print, attn.sig);
4382 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4385 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4387 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4388 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4389 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4390 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4391 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4392 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4393 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4394 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4395 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4396 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4398 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4399 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4401 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4402 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4403 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4404 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4405 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4406 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4407 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4408 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4410 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4411 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4412 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4413 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4414 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4415 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4416 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4417 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4418 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4419 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4420 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4421 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4422 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4423 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4424 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4427 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4428 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4429 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4430 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4431 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4436 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4438 struct attn_route attn, *group_mask;
4439 int port = BP_PORT(bp);
4444 bool global = false;
4446 /* need to take HW lock because MCP or other port might also
4447 try to handle this event */
4448 bnx2x_acquire_alr(bp);
4450 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4451 #ifndef BNX2X_STOP_ON_ERROR
4452 bp->recovery_state = BNX2X_RECOVERY_INIT;
4453 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4454 /* Disable HW interrupts */
4455 bnx2x_int_disable(bp);
4456 /* In case of parity errors don't handle attentions so that
4457 * other function would "see" parity errors.
4462 bnx2x_release_alr(bp);
4466 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4467 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4468 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4469 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4470 if (!CHIP_IS_E1x(bp))
4472 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4476 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4477 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4479 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4480 if (deasserted & (1 << index)) {
4481 group_mask = &bp->attn_group[index];
4483 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4485 group_mask->sig[0], group_mask->sig[1],
4486 group_mask->sig[2], group_mask->sig[3],
4487 group_mask->sig[4]);
4489 bnx2x_attn_int_deasserted4(bp,
4490 attn.sig[4] & group_mask->sig[4]);
4491 bnx2x_attn_int_deasserted3(bp,
4492 attn.sig[3] & group_mask->sig[3]);
4493 bnx2x_attn_int_deasserted1(bp,
4494 attn.sig[1] & group_mask->sig[1]);
4495 bnx2x_attn_int_deasserted2(bp,
4496 attn.sig[2] & group_mask->sig[2]);
4497 bnx2x_attn_int_deasserted0(bp,
4498 attn.sig[0] & group_mask->sig[0]);
4502 bnx2x_release_alr(bp);
4504 if (bp->common.int_block == INT_BLOCK_HC)
4505 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4506 COMMAND_REG_ATTN_BITS_CLR);
4508 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4511 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4512 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4513 REG_WR(bp, reg_addr, val);
4515 if (~bp->attn_state & deasserted)
4516 BNX2X_ERR("IGU ERROR\n");
4518 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4519 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4521 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4522 aeu_mask = REG_RD(bp, reg_addr);
4524 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4525 aeu_mask, deasserted);
4526 aeu_mask |= (deasserted & 0x3ff);
4527 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4529 REG_WR(bp, reg_addr, aeu_mask);
4530 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4532 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4533 bp->attn_state &= ~deasserted;
4534 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4537 static void bnx2x_attn_int(struct bnx2x *bp)
4539 /* read local copy of bits */
4540 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4542 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4544 u32 attn_state = bp->attn_state;
4546 /* look for changed bits */
4547 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4548 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4551 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4552 attn_bits, attn_ack, asserted, deasserted);
4554 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4555 BNX2X_ERR("BAD attention state\n");
4557 /* handle bits that were raised */
4559 bnx2x_attn_int_asserted(bp, asserted);
4562 bnx2x_attn_int_deasserted(bp, deasserted);
4565 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4566 u16 index, u8 op, u8 update)
4568 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4570 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4574 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4576 /* No memory barriers */
4577 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4578 mmiowb(); /* keep prod updates ordered */
4582 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4583 union event_ring_elem *elem)
4585 u8 err = elem->message.error;
4587 if (!bp->cnic_eth_dev.starting_cid ||
4588 (cid < bp->cnic_eth_dev.starting_cid &&
4589 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4592 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4594 if (unlikely(err)) {
4596 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4598 bnx2x_panic_dump(bp);
4600 bnx2x_cnic_cfc_comp(bp, cid, err);
4605 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4607 struct bnx2x_mcast_ramrod_params rparam;
4610 memset(&rparam, 0, sizeof(rparam));
4612 rparam.mcast_obj = &bp->mcast_obj;
4614 netif_addr_lock_bh(bp->dev);
4616 /* Clear pending state for the last command */
4617 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4619 /* If there are pending mcast commands - send them */
4620 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4621 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4623 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4627 netif_addr_unlock_bh(bp->dev);
4630 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4631 union event_ring_elem *elem)
4633 unsigned long ramrod_flags = 0;
4635 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4636 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4638 /* Always push next commands out, don't wait here */
4639 __set_bit(RAMROD_CONT, &ramrod_flags);
4641 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4642 case BNX2X_FILTER_MAC_PENDING:
4643 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4645 if (cid == BNX2X_ISCSI_ETH_CID(bp))
4646 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4649 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4652 case BNX2X_FILTER_MCAST_PENDING:
4653 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4654 /* This is only relevant for 57710 where multicast MACs are
4655 * configured as unicast MACs using the same ramrod.
4657 bnx2x_handle_mcast_eqe(bp);
4660 BNX2X_ERR("Unsupported classification command: %d\n",
4661 elem->message.data.eth_event.echo);
4665 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4668 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4670 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4675 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4678 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4680 netif_addr_lock_bh(bp->dev);
4682 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4684 /* Send rx_mode command again if was requested */
4685 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4686 bnx2x_set_storm_rx_mode(bp);
4688 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4690 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4691 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4693 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4696 netif_addr_unlock_bh(bp->dev);
4699 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4700 union event_ring_elem *elem)
4702 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4704 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4705 elem->message.data.vif_list_event.func_bit_map);
4706 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4707 elem->message.data.vif_list_event.func_bit_map);
4708 } else if (elem->message.data.vif_list_event.echo ==
4709 VIF_LIST_RULE_SET) {
4710 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4711 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4715 /* called with rtnl_lock */
4716 static void bnx2x_after_function_update(struct bnx2x *bp)
4719 struct bnx2x_fastpath *fp;
4720 struct bnx2x_queue_state_params queue_params = {NULL};
4721 struct bnx2x_queue_update_params *q_update_params =
4722 &queue_params.params.update;
4724 /* Send Q update command with afex vlan removal values for all Qs */
4725 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4727 /* set silent vlan removal values according to vlan mode */
4728 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4729 &q_update_params->update_flags);
4730 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4731 &q_update_params->update_flags);
4732 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4734 /* in access mode mark mask and value are 0 to strip all vlans */
4735 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4736 q_update_params->silent_removal_value = 0;
4737 q_update_params->silent_removal_mask = 0;
4739 q_update_params->silent_removal_value =
4740 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4741 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4744 for_each_eth_queue(bp, q) {
4745 /* Set the appropriate Queue object */
4747 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4749 /* send the ramrod */
4750 rc = bnx2x_queue_state_change(bp, &queue_params);
4752 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4758 fp = &bp->fp[FCOE_IDX(bp)];
4759 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4761 /* clear pending completion bit */
4762 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4764 /* mark latest Q bit */
4765 smp_mb__before_clear_bit();
4766 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4767 smp_mb__after_clear_bit();
4769 /* send Q update ramrod for FCoE Q */
4770 rc = bnx2x_queue_state_change(bp, &queue_params);
4772 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4775 /* If no FCoE ring - ACK MCP now */
4776 bnx2x_link_report(bp);
4777 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4780 /* If no FCoE ring - ACK MCP now */
4781 bnx2x_link_report(bp);
4782 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4783 #endif /* BCM_CNIC */
4786 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4787 struct bnx2x *bp, u32 cid)
4789 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4791 if (cid == BNX2X_FCOE_ETH_CID(bp))
4792 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4795 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4798 static void bnx2x_eq_int(struct bnx2x *bp)
4800 u16 hw_cons, sw_cons, sw_prod;
4801 union event_ring_elem *elem;
4805 struct bnx2x_queue_sp_obj *q_obj;
4806 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4807 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4809 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4811 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4812 * when we get the the next-page we nned to adjust so the loop
4813 * condition below will be met. The next element is the size of a
4814 * regular element and hence incrementing by 1
4816 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4819 /* This function may never run in parallel with itself for a
4820 * specific bp, thus there is no need in "paired" read memory
4823 sw_cons = bp->eq_cons;
4824 sw_prod = bp->eq_prod;
4826 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4827 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4829 for (; sw_cons != hw_cons;
4830 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4833 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4835 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4836 opcode = elem->message.opcode;
4839 /* handle eq element */
4841 case EVENT_RING_OPCODE_STAT_QUERY:
4842 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4843 "got statistics comp event %d\n",
4845 /* nothing to do with stats comp */
4848 case EVENT_RING_OPCODE_CFC_DEL:
4849 /* handle according to cid range */
4851 * we may want to verify here that the bp state is
4855 "got delete ramrod for MULTI[%d]\n", cid);
4857 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4860 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4862 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4869 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4870 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4871 if (f_obj->complete_cmd(bp, f_obj,
4872 BNX2X_F_CMD_TX_STOP))
4874 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4877 case EVENT_RING_OPCODE_START_TRAFFIC:
4878 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4879 if (f_obj->complete_cmd(bp, f_obj,
4880 BNX2X_F_CMD_TX_START))
4882 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4884 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4885 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4886 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4887 f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4889 /* We will perform the Queues update from sp_rtnl task
4890 * as all Queue SP operations should run under
4893 smp_mb__before_clear_bit();
4894 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4895 &bp->sp_rtnl_state);
4896 smp_mb__after_clear_bit();
4898 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4901 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4902 f_obj->complete_cmd(bp, f_obj,
4903 BNX2X_F_CMD_AFEX_VIFLISTS);
4904 bnx2x_after_afex_vif_lists(bp, elem);
4906 case EVENT_RING_OPCODE_FUNCTION_START:
4907 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4908 "got FUNC_START ramrod\n");
4909 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4914 case EVENT_RING_OPCODE_FUNCTION_STOP:
4915 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4916 "got FUNC_STOP ramrod\n");
4917 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4923 switch (opcode | bp->state) {
4924 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4926 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4927 BNX2X_STATE_OPENING_WAIT4_PORT):
4928 cid = elem->message.data.eth_event.echo &
4930 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4932 rss_raw->clear_pending(rss_raw);
4935 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4936 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4937 case (EVENT_RING_OPCODE_SET_MAC |
4938 BNX2X_STATE_CLOSING_WAIT4_HALT):
4939 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4941 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4943 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4944 BNX2X_STATE_CLOSING_WAIT4_HALT):
4945 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4946 bnx2x_handle_classification_eqe(bp, elem);
4949 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4951 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4953 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4954 BNX2X_STATE_CLOSING_WAIT4_HALT):
4955 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4956 bnx2x_handle_mcast_eqe(bp);
4959 case (EVENT_RING_OPCODE_FILTERS_RULES |
4961 case (EVENT_RING_OPCODE_FILTERS_RULES |
4963 case (EVENT_RING_OPCODE_FILTERS_RULES |
4964 BNX2X_STATE_CLOSING_WAIT4_HALT):
4965 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4966 bnx2x_handle_rx_mode_eqe(bp);
4969 /* unknown event log error and continue */
4970 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4971 elem->message.opcode, bp->state);
4977 smp_mb__before_atomic_inc();
4978 atomic_add(spqe_cnt, &bp->eq_spq_left);
4980 bp->eq_cons = sw_cons;
4981 bp->eq_prod = sw_prod;
4982 /* Make sure that above mem writes were issued towards the memory */
4985 /* update producer */
4986 bnx2x_update_eq_prod(bp, bp->eq_prod);
4989 static void bnx2x_sp_task(struct work_struct *work)
4991 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4994 status = bnx2x_update_dsb_idx(bp);
4995 /* if (status == 0) */
4996 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4998 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
5001 if (status & BNX2X_DEF_SB_ATT_IDX) {
5003 status &= ~BNX2X_DEF_SB_ATT_IDX;
5006 /* SP events: STAT_QUERY and others */
5007 if (status & BNX2X_DEF_SB_IDX) {
5009 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5011 if ((!NO_FCOE(bp)) &&
5012 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5014 * Prevent local bottom-halves from running as
5015 * we are going to change the local NAPI list.
5018 napi_schedule(&bnx2x_fcoe(bp, napi));
5022 /* Handle EQ completions */
5025 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5026 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5028 status &= ~BNX2X_DEF_SB_IDX;
5031 if (unlikely(status))
5032 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5035 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5036 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5038 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5039 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5041 bnx2x_link_report(bp);
5042 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5046 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5048 struct net_device *dev = dev_instance;
5049 struct bnx2x *bp = netdev_priv(dev);
5051 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5052 IGU_INT_DISABLE, 0);
5054 #ifdef BNX2X_STOP_ON_ERROR
5055 if (unlikely(bp->panic))
5061 struct cnic_ops *c_ops;
5064 c_ops = rcu_dereference(bp->cnic_ops);
5066 c_ops->cnic_handler(bp->cnic_data, NULL);
5070 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5075 /* end of slow path */
5078 void bnx2x_drv_pulse(struct bnx2x *bp)
5080 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5081 bp->fw_drv_pulse_wr_seq);
5085 static void bnx2x_timer(unsigned long data)
5087 struct bnx2x *bp = (struct bnx2x *) data;
5089 if (!netif_running(bp->dev))
5092 if (!BP_NOMCP(bp)) {
5093 int mb_idx = BP_FW_MB_IDX(bp);
5097 ++bp->fw_drv_pulse_wr_seq;
5098 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5099 /* TBD - add SYSTEM_TIME */
5100 drv_pulse = bp->fw_drv_pulse_wr_seq;
5101 bnx2x_drv_pulse(bp);
5103 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5104 MCP_PULSE_SEQ_MASK);
5105 /* The delta between driver pulse and mcp response
5106 * should be 1 (before mcp response) or 0 (after mcp response)
5108 if ((drv_pulse != mcp_pulse) &&
5109 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5110 /* someone lost a heartbeat... */
5111 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5112 drv_pulse, mcp_pulse);
5116 if (bp->state == BNX2X_STATE_OPEN)
5117 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5119 mod_timer(&bp->timer, jiffies + bp->current_interval);
5122 /* end of Statistics */
5127 * nic init service functions
5130 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5133 if (!(len%4) && !(addr%4))
5134 for (i = 0; i < len; i += 4)
5135 REG_WR(bp, addr + i, fill);
5137 for (i = 0; i < len; i++)
5138 REG_WR8(bp, addr + i, fill);
5142 /* helper: writes FP SP data to FW - data_size in dwords */
5143 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5149 for (index = 0; index < data_size; index++)
5150 REG_WR(bp, BAR_CSTRORM_INTMEM +
5151 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5153 *(sb_data_p + index));
5156 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5160 struct hc_status_block_data_e2 sb_data_e2;
5161 struct hc_status_block_data_e1x sb_data_e1x;
5163 /* disable the function first */
5164 if (!CHIP_IS_E1x(bp)) {
5165 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5166 sb_data_e2.common.state = SB_DISABLED;
5167 sb_data_e2.common.p_func.vf_valid = false;
5168 sb_data_p = (u32 *)&sb_data_e2;
5169 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5171 memset(&sb_data_e1x, 0,
5172 sizeof(struct hc_status_block_data_e1x));
5173 sb_data_e1x.common.state = SB_DISABLED;
5174 sb_data_e1x.common.p_func.vf_valid = false;
5175 sb_data_p = (u32 *)&sb_data_e1x;
5176 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5178 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5180 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5181 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5182 CSTORM_STATUS_BLOCK_SIZE);
5183 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5184 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5185 CSTORM_SYNC_BLOCK_SIZE);
5188 /* helper: writes SP SB data to FW */
5189 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5190 struct hc_sp_status_block_data *sp_sb_data)
5192 int func = BP_FUNC(bp);
5194 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5195 REG_WR(bp, BAR_CSTRORM_INTMEM +
5196 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5198 *((u32 *)sp_sb_data + i));
5201 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5203 int func = BP_FUNC(bp);
5204 struct hc_sp_status_block_data sp_sb_data;
5205 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5207 sp_sb_data.state = SB_DISABLED;
5208 sp_sb_data.p_func.vf_valid = false;
5210 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5212 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5213 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5214 CSTORM_SP_STATUS_BLOCK_SIZE);
5215 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5216 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5217 CSTORM_SP_SYNC_BLOCK_SIZE);
5222 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5223 int igu_sb_id, int igu_seg_id)
5225 hc_sm->igu_sb_id = igu_sb_id;
5226 hc_sm->igu_seg_id = igu_seg_id;
5227 hc_sm->timer_value = 0xFF;
5228 hc_sm->time_to_expire = 0xFFFFFFFF;
5232 /* allocates state machine ids. */
5233 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5235 /* zero out state machine indices */
5237 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5240 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5241 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5242 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5243 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5247 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5248 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5251 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5252 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5253 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5254 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5255 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5256 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5257 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5258 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5261 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5262 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5266 struct hc_status_block_data_e2 sb_data_e2;
5267 struct hc_status_block_data_e1x sb_data_e1x;
5268 struct hc_status_block_sm *hc_sm_p;
5272 if (CHIP_INT_MODE_IS_BC(bp))
5273 igu_seg_id = HC_SEG_ACCESS_NORM;
5275 igu_seg_id = IGU_SEG_ACCESS_NORM;
5277 bnx2x_zero_fp_sb(bp, fw_sb_id);
5279 if (!CHIP_IS_E1x(bp)) {
5280 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5281 sb_data_e2.common.state = SB_ENABLED;
5282 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5283 sb_data_e2.common.p_func.vf_id = vfid;
5284 sb_data_e2.common.p_func.vf_valid = vf_valid;
5285 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5286 sb_data_e2.common.same_igu_sb_1b = true;
5287 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5288 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5289 hc_sm_p = sb_data_e2.common.state_machine;
5290 sb_data_p = (u32 *)&sb_data_e2;
5291 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5292 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5294 memset(&sb_data_e1x, 0,
5295 sizeof(struct hc_status_block_data_e1x));
5296 sb_data_e1x.common.state = SB_ENABLED;
5297 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5298 sb_data_e1x.common.p_func.vf_id = 0xff;
5299 sb_data_e1x.common.p_func.vf_valid = false;
5300 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5301 sb_data_e1x.common.same_igu_sb_1b = true;
5302 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5303 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5304 hc_sm_p = sb_data_e1x.common.state_machine;
5305 sb_data_p = (u32 *)&sb_data_e1x;
5306 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5307 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5310 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5311 igu_sb_id, igu_seg_id);
5312 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5313 igu_sb_id, igu_seg_id);
5315 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5317 /* write indecies to HW */
5318 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5321 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5322 u16 tx_usec, u16 rx_usec)
5324 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5326 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5327 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5329 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5330 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5332 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5333 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5337 static void bnx2x_init_def_sb(struct bnx2x *bp)
5339 struct host_sp_status_block *def_sb = bp->def_status_blk;
5340 dma_addr_t mapping = bp->def_status_blk_mapping;
5341 int igu_sp_sb_index;
5343 int port = BP_PORT(bp);
5344 int func = BP_FUNC(bp);
5345 int reg_offset, reg_offset_en5;
5348 struct hc_sp_status_block_data sp_sb_data;
5349 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5351 if (CHIP_INT_MODE_IS_BC(bp)) {
5352 igu_sp_sb_index = DEF_SB_IGU_ID;
5353 igu_seg_id = HC_SEG_ACCESS_DEF;
5355 igu_sp_sb_index = bp->igu_dsb_id;
5356 igu_seg_id = IGU_SEG_ACCESS_DEF;
5360 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5361 atten_status_block);
5362 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5366 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5367 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5368 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5369 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5370 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5372 /* take care of sig[0]..sig[4] */
5373 for (sindex = 0; sindex < 4; sindex++)
5374 bp->attn_group[index].sig[sindex] =
5375 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5377 if (!CHIP_IS_E1x(bp))
5379 * enable5 is separate from the rest of the registers,
5380 * and therefore the address skip is 4
5381 * and not 16 between the different groups
5383 bp->attn_group[index].sig[4] = REG_RD(bp,
5384 reg_offset_en5 + 0x4*index);
5386 bp->attn_group[index].sig[4] = 0;
5389 if (bp->common.int_block == INT_BLOCK_HC) {
5390 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5391 HC_REG_ATTN_MSG0_ADDR_L);
5393 REG_WR(bp, reg_offset, U64_LO(section));
5394 REG_WR(bp, reg_offset + 4, U64_HI(section));
5395 } else if (!CHIP_IS_E1x(bp)) {
5396 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5397 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5400 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5403 bnx2x_zero_sp_sb(bp);
5405 sp_sb_data.state = SB_ENABLED;
5406 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5407 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5408 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5409 sp_sb_data.igu_seg_id = igu_seg_id;
5410 sp_sb_data.p_func.pf_id = func;
5411 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5412 sp_sb_data.p_func.vf_id = 0xff;
5414 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5416 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5419 void bnx2x_update_coalesce(struct bnx2x *bp)
5423 for_each_eth_queue(bp, i)
5424 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5425 bp->tx_ticks, bp->rx_ticks);
5428 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5430 spin_lock_init(&bp->spq_lock);
5431 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5433 bp->spq_prod_idx = 0;
5434 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5435 bp->spq_prod_bd = bp->spq;
5436 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5439 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5442 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5443 union event_ring_elem *elem =
5444 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5446 elem->next_page.addr.hi =
5447 cpu_to_le32(U64_HI(bp->eq_mapping +
5448 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5449 elem->next_page.addr.lo =
5450 cpu_to_le32(U64_LO(bp->eq_mapping +
5451 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5454 bp->eq_prod = NUM_EQ_DESC;
5455 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5456 /* we want a warning message before it gets rought... */
5457 atomic_set(&bp->eq_spq_left,
5458 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5462 /* called with netif_addr_lock_bh() */
5463 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5464 unsigned long rx_mode_flags,
5465 unsigned long rx_accept_flags,
5466 unsigned long tx_accept_flags,
5467 unsigned long ramrod_flags)
5469 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5472 memset(&ramrod_param, 0, sizeof(ramrod_param));
5474 /* Prepare ramrod parameters */
5475 ramrod_param.cid = 0;
5476 ramrod_param.cl_id = cl_id;
5477 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5478 ramrod_param.func_id = BP_FUNC(bp);
5480 ramrod_param.pstate = &bp->sp_state;
5481 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5483 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5484 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5486 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5488 ramrod_param.ramrod_flags = ramrod_flags;
5489 ramrod_param.rx_mode_flags = rx_mode_flags;
5491 ramrod_param.rx_accept_flags = rx_accept_flags;
5492 ramrod_param.tx_accept_flags = tx_accept_flags;
5494 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5496 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5501 /* called with netif_addr_lock_bh() */
5502 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5504 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5505 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5510 /* Configure rx_mode of FCoE Queue */
5511 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5514 switch (bp->rx_mode) {
5515 case BNX2X_RX_MODE_NONE:
5517 * 'drop all' supersedes any accept flags that may have been
5518 * passed to the function.
5521 case BNX2X_RX_MODE_NORMAL:
5522 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5523 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5524 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5526 /* internal switching mode */
5527 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5528 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5529 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5532 case BNX2X_RX_MODE_ALLMULTI:
5533 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5534 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5535 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5537 /* internal switching mode */
5538 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5539 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5540 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5543 case BNX2X_RX_MODE_PROMISC:
5544 /* According to deffinition of SI mode, iface in promisc mode
5545 * should receive matched and unmatched (in resolution of port)
5548 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5549 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5550 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5551 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5553 /* internal switching mode */
5554 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5555 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5558 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5560 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5564 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5568 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5569 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5570 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5573 __set_bit(RAMROD_RX, &ramrod_flags);
5574 __set_bit(RAMROD_TX, &ramrod_flags);
5576 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5577 tx_accept_flags, ramrod_flags);
5580 static void bnx2x_init_internal_common(struct bnx2x *bp)
5586 * In switch independent mode, the TSTORM needs to accept
5587 * packets that failed classification, since approximate match
5588 * mac addresses aren't written to NIG LLH
5590 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5591 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5592 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5593 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5594 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5596 /* Zero this manually as its initialization is
5597 currently missing in the initTool */
5598 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5599 REG_WR(bp, BAR_USTRORM_INTMEM +
5600 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5601 if (!CHIP_IS_E1x(bp)) {
5602 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5603 CHIP_INT_MODE_IS_BC(bp) ?
5604 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5608 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5610 switch (load_code) {
5611 case FW_MSG_CODE_DRV_LOAD_COMMON:
5612 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5613 bnx2x_init_internal_common(bp);
5616 case FW_MSG_CODE_DRV_LOAD_PORT:
5620 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5621 /* internal memory per function is
5622 initialized inside bnx2x_pf_init */
5626 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5631 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5633 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5636 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5638 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5641 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5643 if (CHIP_IS_E1x(fp->bp))
5644 return BP_L_ID(fp->bp) + fp->index;
5645 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5646 return bnx2x_fp_igu_sb_id(fp);
5649 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5651 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5653 unsigned long q_type = 0;
5654 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5655 fp->rx_queue = fp_idx;
5657 fp->cl_id = bnx2x_fp_cl_id(fp);
5658 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5659 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5660 /* qZone id equals to FW (per path) client id */
5661 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5664 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5666 /* Setup SB indicies */
5667 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5669 /* Configure Queue State object */
5670 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5671 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5673 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5676 for_each_cos_in_tx_queue(fp, cos) {
5677 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5678 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5679 FP_COS_TO_TXQ(fp, cos, bp),
5680 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5681 cids[cos] = fp->txdata_ptr[cos]->cid;
5684 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5685 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5686 bnx2x_sp_mapping(bp, q_rdata), q_type);
5689 * Configure classification DBs: Always enable Tx switching
5691 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5693 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5694 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5696 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5697 fp->fw_sb_id, fp->igu_sb_id);
5699 bnx2x_update_fpsb_idx(fp);
5702 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5706 for (i = 1; i <= NUM_TX_RINGS; i++) {
5707 struct eth_tx_next_bd *tx_next_bd =
5708 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5710 tx_next_bd->addr_hi =
5711 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5712 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5713 tx_next_bd->addr_lo =
5714 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5715 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5718 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5719 txdata->tx_db.data.zero_fill1 = 0;
5720 txdata->tx_db.data.prod = 0;
5722 txdata->tx_pkt_prod = 0;
5723 txdata->tx_pkt_cons = 0;
5724 txdata->tx_bd_prod = 0;
5725 txdata->tx_bd_cons = 0;
5729 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5734 for_each_tx_queue(bp, i)
5735 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5736 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5739 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5743 for_each_eth_queue(bp, i)
5744 bnx2x_init_eth_fp(bp, i);
5747 bnx2x_init_fcoe_fp(bp);
5749 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5750 BNX2X_VF_ID_INVALID, false,
5751 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5755 /* Initialize MOD_ABS interrupts */
5756 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5757 bp->common.shmem_base, bp->common.shmem2_base,
5759 /* ensure status block indices were read */
5762 bnx2x_init_def_sb(bp);
5763 bnx2x_update_dsb_idx(bp);
5764 bnx2x_init_rx_rings(bp);
5765 bnx2x_init_tx_rings(bp);
5766 bnx2x_init_sp_ring(bp);
5767 bnx2x_init_eq_ring(bp);
5768 bnx2x_init_internal(bp, load_code);
5770 bnx2x_stats_init(bp);
5772 /* flush all before enabling interrupts */
5776 bnx2x_int_enable(bp);
5778 /* Check for SPIO5 */
5779 bnx2x_attn_int_deasserted0(bp,
5780 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5781 AEU_INPUTS_ATTN_BITS_SPIO5);
5784 /* end of nic init */
5787 * gzip service functions
5790 static int bnx2x_gunzip_init(struct bnx2x *bp)
5792 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5793 &bp->gunzip_mapping, GFP_KERNEL);
5794 if (bp->gunzip_buf == NULL)
5797 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5798 if (bp->strm == NULL)
5801 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5802 if (bp->strm->workspace == NULL)
5812 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5813 bp->gunzip_mapping);
5814 bp->gunzip_buf = NULL;
5817 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5821 static void bnx2x_gunzip_end(struct bnx2x *bp)
5824 vfree(bp->strm->workspace);
5829 if (bp->gunzip_buf) {
5830 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5831 bp->gunzip_mapping);
5832 bp->gunzip_buf = NULL;
5836 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5840 /* check gzip header */
5841 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5842 BNX2X_ERR("Bad gzip header\n");
5850 if (zbuf[3] & FNAME)
5851 while ((zbuf[n++] != 0) && (n < len));
5853 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5854 bp->strm->avail_in = len - n;
5855 bp->strm->next_out = bp->gunzip_buf;
5856 bp->strm->avail_out = FW_BUF_SIZE;
5858 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5862 rc = zlib_inflate(bp->strm, Z_FINISH);
5863 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5864 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5867 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5868 if (bp->gunzip_outlen & 0x3)
5870 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5872 bp->gunzip_outlen >>= 2;
5874 zlib_inflateEnd(bp->strm);
5876 if (rc == Z_STREAM_END)
5882 /* nic load/unload */
5885 * General service functions
5888 /* send a NIG loopback debug packet */
5889 static void bnx2x_lb_pckt(struct bnx2x *bp)
5893 /* Ethernet source and destination addresses */
5894 wb_write[0] = 0x55555555;
5895 wb_write[1] = 0x55555555;
5896 wb_write[2] = 0x20; /* SOP */
5897 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5899 /* NON-IP protocol */
5900 wb_write[0] = 0x09000000;
5901 wb_write[1] = 0x55555555;
5902 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5903 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5906 /* some of the internal memories
5907 * are not directly readable from the driver
5908 * to test them we send debug packets
5910 static int bnx2x_int_mem_test(struct bnx2x *bp)
5916 if (CHIP_REV_IS_FPGA(bp))
5918 else if (CHIP_REV_IS_EMUL(bp))
5923 /* Disable inputs of parser neighbor blocks */
5924 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5925 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5926 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5927 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5929 /* Write 0 to parser credits for CFC search request */
5930 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5932 /* send Ethernet packet */
5935 /* TODO do i reset NIG statistic? */
5936 /* Wait until NIG register shows 1 packet of size 0x10 */
5937 count = 1000 * factor;
5940 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5941 val = *bnx2x_sp(bp, wb_data[0]);
5949 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5953 /* Wait until PRS register shows 1 packet */
5954 count = 1000 * factor;
5956 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5964 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5968 /* Reset and init BRB, PRS */
5969 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5971 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5973 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5974 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5976 DP(NETIF_MSG_HW, "part2\n");
5978 /* Disable inputs of parser neighbor blocks */
5979 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5980 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5981 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5982 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5984 /* Write 0 to parser credits for CFC search request */
5985 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5987 /* send 10 Ethernet packets */
5988 for (i = 0; i < 10; i++)
5991 /* Wait until NIG register shows 10 + 1
5992 packets of size 11*0x10 = 0xb0 */
5993 count = 1000 * factor;
5996 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5997 val = *bnx2x_sp(bp, wb_data[0]);
6005 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6009 /* Wait until PRS register shows 2 packets */
6010 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6012 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6014 /* Write 1 to parser credits for CFC search request */
6015 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6017 /* Wait until PRS register shows 3 packets */
6018 msleep(10 * factor);
6019 /* Wait until NIG register shows 1 packet of size 0x10 */
6020 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6022 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6024 /* clear NIG EOP FIFO */
6025 for (i = 0; i < 11; i++)
6026 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6027 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6029 BNX2X_ERR("clear of NIG failed\n");
6033 /* Reset and init BRB, PRS, NIG */
6034 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6036 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6038 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6039 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6042 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6045 /* Enable inputs of parser neighbor blocks */
6046 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6047 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6048 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6049 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6051 DP(NETIF_MSG_HW, "done\n");
6056 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6058 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6059 if (!CHIP_IS_E1x(bp))
6060 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6062 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6063 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6064 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6066 * mask read length error interrupts in brb for parser
6067 * (parsing unit and 'checksum and crc' unit)
6068 * these errors are legal (PU reads fixed length and CAC can cause
6069 * read length error on truncated packets)
6071 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6072 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6073 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6074 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6075 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6076 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6077 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6078 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6079 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6080 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6081 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6082 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6083 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6084 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6085 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6086 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6087 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6088 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6089 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6091 if (CHIP_REV_IS_FPGA(bp))
6092 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6093 else if (!CHIP_IS_E1x(bp))
6094 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6095 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6096 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6097 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6098 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6099 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6101 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6102 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6103 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6104 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6105 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6107 if (!CHIP_IS_E1x(bp))
6108 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6109 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6111 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6112 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6113 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6114 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6117 static void bnx2x_reset_common(struct bnx2x *bp)
6122 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6125 if (CHIP_IS_E3(bp)) {
6126 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6127 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6130 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6133 static void bnx2x_setup_dmae(struct bnx2x *bp)
6136 spin_lock_init(&bp->dmae_lock);
6139 static void bnx2x_init_pxp(struct bnx2x *bp)
6142 int r_order, w_order;
6144 pci_read_config_word(bp->pdev,
6145 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
6146 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6147 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6149 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6151 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6155 bnx2x_init_pxp_arb(bp, r_order, w_order);
6158 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6168 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6169 SHARED_HW_CFG_FAN_FAILURE_MASK;
6171 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6175 * The fan failure mechanism is usually related to the PHY type since
6176 * the power consumption of the board is affected by the PHY. Currently,
6177 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6179 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6180 for (port = PORT_0; port < PORT_MAX; port++) {
6182 bnx2x_fan_failure_det_req(
6184 bp->common.shmem_base,
6185 bp->common.shmem2_base,
6189 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6191 if (is_required == 0)
6194 /* Fan failure is indicated by SPIO 5 */
6195 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6196 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6198 /* set to active low mode */
6199 val = REG_RD(bp, MISC_REG_SPIO_INT);
6200 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6201 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6202 REG_WR(bp, MISC_REG_SPIO_INT, val);
6204 /* enable interrupt to signal the IGU */
6205 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6206 val |= (1 << MISC_REGISTERS_SPIO_5);
6207 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6210 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6216 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6219 switch (BP_ABS_FUNC(bp)) {
6221 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6224 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6227 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6230 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6233 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6236 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6239 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6242 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6248 REG_WR(bp, offset, pretend_func_num);
6250 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6253 void bnx2x_pf_disable(struct bnx2x *bp)
6255 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6256 val &= ~IGU_PF_CONF_FUNC_EN;
6258 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6259 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6260 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6263 static void bnx2x__common_init_phy(struct bnx2x *bp)
6265 u32 shmem_base[2], shmem2_base[2];
6266 shmem_base[0] = bp->common.shmem_base;
6267 shmem2_base[0] = bp->common.shmem2_base;
6268 if (!CHIP_IS_E1x(bp)) {
6270 SHMEM2_RD(bp, other_shmem_base_addr);
6272 SHMEM2_RD(bp, other_shmem2_base_addr);
6274 bnx2x_acquire_phy_lock(bp);
6275 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6276 bp->common.chip_id);
6277 bnx2x_release_phy_lock(bp);
6281 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6283 * @bp: driver handle
6285 static int bnx2x_init_hw_common(struct bnx2x *bp)
6289 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6292 * take the UNDI lock to protect undi_unload flow from accessing
6293 * registers while we're resetting the chip
6295 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6297 bnx2x_reset_common(bp);
6298 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6301 if (CHIP_IS_E3(bp)) {
6302 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6303 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6305 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6307 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6309 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6311 if (!CHIP_IS_E1x(bp)) {
6315 * 4-port mode or 2-port mode we need to turn of master-enable
6316 * for everyone, after that, turn it back on for self.
6317 * so, we disregard multi-function or not, and always disable
6318 * for all functions on the given path, this means 0,2,4,6 for
6319 * path 0 and 1,3,5,7 for path 1
6321 for (abs_func_id = BP_PATH(bp);
6322 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6323 if (abs_func_id == BP_ABS_FUNC(bp)) {
6325 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6330 bnx2x_pretend_func(bp, abs_func_id);
6331 /* clear pf enable */
6332 bnx2x_pf_disable(bp);
6333 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6337 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6338 if (CHIP_IS_E1(bp)) {
6339 /* enable HW interrupt from PXP on USDM overflow
6340 bit 16 on INT_MASK_0 */
6341 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6344 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6348 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6349 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6350 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6351 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6352 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6353 /* make sure this value is 0 */
6354 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6356 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6357 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6358 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6359 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6360 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6363 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6365 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6366 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6368 /* let the HW do it's magic ... */
6370 /* finish PXP init */
6371 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6373 BNX2X_ERR("PXP2 CFG failed\n");
6376 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6378 BNX2X_ERR("PXP2 RD_INIT failed\n");
6382 /* Timers bug workaround E2 only. We need to set the entire ILT to
6383 * have entries with value "0" and valid bit on.
6384 * This needs to be done by the first PF that is loaded in a path
6385 * (i.e. common phase)
6387 if (!CHIP_IS_E1x(bp)) {
6388 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6389 * (i.e. vnic3) to start even if it is marked as "scan-off".
6390 * This occurs when a different function (func2,3) is being marked
6391 * as "scan-off". Real-life scenario for example: if a driver is being
6392 * load-unloaded while func6,7 are down. This will cause the timer to access
6393 * the ilt, translate to a logical address and send a request to read/write.
6394 * Since the ilt for the function that is down is not valid, this will cause
6395 * a translation error which is unrecoverable.
6396 * The Workaround is intended to make sure that when this happens nothing fatal
6397 * will occur. The workaround:
6398 * 1. First PF driver which loads on a path will:
6399 * a. After taking the chip out of reset, by using pretend,
6400 * it will write "0" to the following registers of
6402 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6403 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6404 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6405 * And for itself it will write '1' to
6406 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6407 * dmae-operations (writing to pram for example.)
6408 * note: can be done for only function 6,7 but cleaner this
6410 * b. Write zero+valid to the entire ILT.
6411 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6412 * VNIC3 (of that port). The range allocated will be the
6413 * entire ILT. This is needed to prevent ILT range error.
6414 * 2. Any PF driver load flow:
6415 * a. ILT update with the physical addresses of the allocated
6417 * b. Wait 20msec. - note that this timeout is needed to make
6418 * sure there are no requests in one of the PXP internal
6419 * queues with "old" ILT addresses.
6420 * c. PF enable in the PGLC.
6421 * d. Clear the was_error of the PF in the PGLC. (could have
6422 * occured while driver was down)
6423 * e. PF enable in the CFC (WEAK + STRONG)
6424 * f. Timers scan enable
6425 * 3. PF driver unload flow:
6426 * a. Clear the Timers scan_en.
6427 * b. Polling for scan_on=0 for that PF.
6428 * c. Clear the PF enable bit in the PXP.
6429 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6430 * e. Write zero+valid to all ILT entries (The valid bit must
6432 * f. If this is VNIC 3 of a port then also init
6433 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6434 * to the last enrty in the ILT.
6437 * Currently the PF error in the PGLC is non recoverable.
6438 * In the future the there will be a recovery routine for this error.
6439 * Currently attention is masked.
6440 * Having an MCP lock on the load/unload process does not guarantee that
6441 * there is no Timer disable during Func6/7 enable. This is because the
6442 * Timers scan is currently being cleared by the MCP on FLR.
6443 * Step 2.d can be done only for PF6/7 and the driver can also check if
6444 * there is error before clearing it. But the flow above is simpler and
6446 * All ILT entries are written by zero+valid and not just PF6/7
6447 * ILT entries since in the future the ILT entries allocation for
6448 * PF-s might be dynamic.
6450 struct ilt_client_info ilt_cli;
6451 struct bnx2x_ilt ilt;
6452 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6453 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6455 /* initialize dummy TM client */
6457 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6458 ilt_cli.client_num = ILT_CLIENT_TM;
6460 /* Step 1: set zeroes to all ilt page entries with valid bit on
6461 * Step 2: set the timers first/last ilt entry to point
6462 * to the entire range to prevent ILT range error for 3rd/4th
6463 * vnic (this code assumes existance of the vnic)
6465 * both steps performed by call to bnx2x_ilt_client_init_op()
6466 * with dummy TM client
6468 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6469 * and his brother are split registers
6471 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6472 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6473 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6475 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6476 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6477 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6481 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6482 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6484 if (!CHIP_IS_E1x(bp)) {
6485 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6486 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6487 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6489 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6491 /* let the HW do it's magic ... */
6494 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6495 } while (factor-- && (val != 1));
6498 BNX2X_ERR("ATC_INIT failed\n");
6503 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6505 /* clean the DMAE memory */
6507 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6509 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6511 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6513 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6515 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6517 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6518 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6519 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6520 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6522 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6525 /* QM queues pointers table */
6526 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6528 /* soft reset pulse */
6529 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6530 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6533 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6536 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6537 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6538 if (!CHIP_REV_IS_SLOW(bp))
6539 /* enable hw interrupt from doorbell Q */
6540 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6542 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6544 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6545 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6547 if (!CHIP_IS_E1(bp))
6548 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6550 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6551 if (IS_MF_AFEX(bp)) {
6552 /* configure that VNTag and VLAN headers must be
6553 * received in afex mode
6555 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6556 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6557 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6558 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6559 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6561 /* Bit-map indicating which L2 hdrs may appear
6562 * after the basic Ethernet header
6564 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6565 bp->path_has_ovlan ? 7 : 6);
6569 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6570 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6571 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6572 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6574 if (!CHIP_IS_E1x(bp)) {
6575 /* reset VFC memories */
6576 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6577 VFC_MEMORIES_RST_REG_CAM_RST |
6578 VFC_MEMORIES_RST_REG_RAM_RST);
6579 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6580 VFC_MEMORIES_RST_REG_CAM_RST |
6581 VFC_MEMORIES_RST_REG_RAM_RST);
6586 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6587 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6588 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6589 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6592 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6594 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6597 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6598 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6599 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6601 if (!CHIP_IS_E1x(bp)) {
6602 if (IS_MF_AFEX(bp)) {
6603 /* configure that VNTag and VLAN headers must be
6606 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6607 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6608 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6609 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6610 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6612 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6613 bp->path_has_ovlan ? 7 : 6);
6617 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6619 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6622 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6623 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6624 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6625 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6626 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6627 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6628 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6629 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6630 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6631 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6633 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6635 if (sizeof(union cdu_context) != 1024)
6636 /* we currently assume that a context is 1024 bytes */
6637 dev_alert(&bp->pdev->dev,
6638 "please adjust the size of cdu_context(%ld)\n",
6639 (long)sizeof(union cdu_context));
6641 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6642 val = (4 << 24) + (0 << 12) + 1024;
6643 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6645 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6646 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6647 /* enable context validation interrupt from CFC */
6648 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6650 /* set the thresholds to prevent CFC/CDU race */
6651 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6653 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6655 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6656 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6658 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6659 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6661 /* Reset PCIE errors for debug */
6662 REG_WR(bp, 0x2814, 0xffffffff);
6663 REG_WR(bp, 0x3820, 0xffffffff);
6665 if (!CHIP_IS_E1x(bp)) {
6666 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6667 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6668 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6669 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6670 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6671 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6672 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6673 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6674 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6675 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6676 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6679 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6680 if (!CHIP_IS_E1(bp)) {
6681 /* in E3 this done in per-port section */
6682 if (!CHIP_IS_E3(bp))
6683 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6685 if (CHIP_IS_E1H(bp))
6686 /* not applicable for E2 (and above ...) */
6687 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6689 if (CHIP_REV_IS_SLOW(bp))
6692 /* finish CFC init */
6693 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6695 BNX2X_ERR("CFC LL_INIT failed\n");
6698 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6700 BNX2X_ERR("CFC AC_INIT failed\n");
6703 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6705 BNX2X_ERR("CFC CAM_INIT failed\n");
6708 REG_WR(bp, CFC_REG_DEBUG0, 0);
6710 if (CHIP_IS_E1(bp)) {
6711 /* read NIG statistic
6712 to see if this is our first up since powerup */
6713 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6714 val = *bnx2x_sp(bp, wb_data[0]);
6716 /* do internal memory self test */
6717 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6718 BNX2X_ERR("internal mem self test failed\n");
6723 bnx2x_setup_fan_failure_detection(bp);
6725 /* clear PXP2 attentions */
6726 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6728 bnx2x_enable_blocks_attention(bp);
6729 bnx2x_enable_blocks_parity(bp);
6731 if (!BP_NOMCP(bp)) {
6732 if (CHIP_IS_E1x(bp))
6733 bnx2x__common_init_phy(bp);
6735 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6741 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6743 * @bp: driver handle
6745 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6747 int rc = bnx2x_init_hw_common(bp);
6752 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6754 bnx2x__common_init_phy(bp);
6759 static int bnx2x_init_hw_port(struct bnx2x *bp)
6761 int port = BP_PORT(bp);
6762 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6767 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6769 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6771 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6772 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6773 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6775 /* Timers bug workaround: disables the pf_master bit in pglue at
6776 * common phase, we need to enable it here before any dmae access are
6777 * attempted. Therefore we manually added the enable-master to the
6778 * port phase (it also happens in the function phase)
6780 if (!CHIP_IS_E1x(bp))
6781 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6783 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6784 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6785 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6786 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6788 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6789 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6790 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6791 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6793 /* QM cid (connection) count */
6794 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6797 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6798 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6799 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6802 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6804 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6805 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6808 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6809 else if (bp->dev->mtu > 4096) {
6810 if (bp->flags & ONE_PORT_FLAG)
6814 /* (24*1024 + val*4)/256 */
6815 low = 96 + (val/64) +
6816 ((val % 64) ? 1 : 0);
6819 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6820 high = low + 56; /* 14*1024/256 */
6821 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6822 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6825 if (CHIP_MODE_IS_4_PORT(bp))
6826 REG_WR(bp, (BP_PORT(bp) ?
6827 BRB1_REG_MAC_GUARANTIED_1 :
6828 BRB1_REG_MAC_GUARANTIED_0), 40);
6831 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6832 if (CHIP_IS_E3B0(bp)) {
6833 if (IS_MF_AFEX(bp)) {
6834 /* configure headers for AFEX mode */
6835 REG_WR(bp, BP_PORT(bp) ?
6836 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6837 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6838 REG_WR(bp, BP_PORT(bp) ?
6839 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6840 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6841 REG_WR(bp, BP_PORT(bp) ?
6842 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6843 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6845 /* Ovlan exists only if we are in multi-function +
6846 * switch-dependent mode, in switch-independent there
6847 * is no ovlan headers
6849 REG_WR(bp, BP_PORT(bp) ?
6850 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6851 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6852 (bp->path_has_ovlan ? 7 : 6));
6856 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6857 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6858 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6859 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6861 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6862 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6863 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6864 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6866 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6867 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6869 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6871 if (CHIP_IS_E1x(bp)) {
6872 /* configure PBF to work without PAUSE mtu 9000 */
6873 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6875 /* update threshold */
6876 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6877 /* update init credit */
6878 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6881 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6883 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6887 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6889 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6890 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6892 if (CHIP_IS_E1(bp)) {
6893 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6894 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6896 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6898 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6900 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6901 /* init aeu_mask_attn_func_0/1:
6902 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6903 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6904 * bits 4-7 are used for "per vn group attention" */
6905 val = IS_MF(bp) ? 0xF7 : 0x7;
6906 /* Enable DCBX attention for all but E1 */
6907 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6908 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6910 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6912 if (!CHIP_IS_E1x(bp)) {
6913 /* Bit-map indicating which L2 hdrs may appear after the
6914 * basic Ethernet header
6917 REG_WR(bp, BP_PORT(bp) ?
6918 NIG_REG_P1_HDRS_AFTER_BASIC :
6919 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6921 REG_WR(bp, BP_PORT(bp) ?
6922 NIG_REG_P1_HDRS_AFTER_BASIC :
6923 NIG_REG_P0_HDRS_AFTER_BASIC,
6924 IS_MF_SD(bp) ? 7 : 6);
6927 REG_WR(bp, BP_PORT(bp) ?
6928 NIG_REG_LLH1_MF_MODE :
6929 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6931 if (!CHIP_IS_E3(bp))
6932 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6934 if (!CHIP_IS_E1(bp)) {
6935 /* 0x2 disable mf_ov, 0x1 enable */
6936 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6937 (IS_MF_SD(bp) ? 0x1 : 0x2));
6939 if (!CHIP_IS_E1x(bp)) {
6941 switch (bp->mf_mode) {
6942 case MULTI_FUNCTION_SD:
6945 case MULTI_FUNCTION_SI:
6946 case MULTI_FUNCTION_AFEX:
6951 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6952 NIG_REG_LLH0_CLS_TYPE), val);
6955 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6956 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6957 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6962 /* If SPIO5 is set to generate interrupts, enable it for this port */
6963 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6964 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6965 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6966 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6967 val = REG_RD(bp, reg_addr);
6968 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6969 REG_WR(bp, reg_addr, val);
6975 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6981 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6983 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6985 wb_write[0] = ONCHIP_ADDR1(addr);
6986 wb_write[1] = ONCHIP_ADDR2(addr);
6987 REG_WR_DMAE(bp, reg, wb_write, 2);
6990 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6991 u8 idu_sb_id, bool is_Pf)
6993 u32 data, ctl, cnt = 100;
6994 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6995 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6996 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
6997 u32 sb_bit = 1 << (idu_sb_id%32);
6998 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
6999 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7001 /* Not supported in BC mode */
7002 if (CHIP_INT_MODE_IS_BC(bp))
7005 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7006 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7007 IGU_REGULAR_CLEANUP_SET |
7008 IGU_REGULAR_BCLEANUP;
7010 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7011 func_encode << IGU_CTRL_REG_FID_SHIFT |
7012 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7014 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7015 data, igu_addr_data);
7016 REG_WR(bp, igu_addr_data, data);
7019 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7021 REG_WR(bp, igu_addr_ctl, ctl);
7025 /* wait for clean up to finish */
7026 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7030 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7032 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7033 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7037 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7039 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7042 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7044 u32 i, base = FUNC_ILT_BASE(func);
7045 for (i = base; i < base + ILT_PER_FUNC; i++)
7046 bnx2x_ilt_wr(bp, i, 0);
7049 static int bnx2x_init_hw_func(struct bnx2x *bp)
7051 int port = BP_PORT(bp);
7052 int func = BP_FUNC(bp);
7053 int init_phase = PHASE_PF0 + func;
7054 struct bnx2x_ilt *ilt = BP_ILT(bp);
7057 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7058 int i, main_mem_width, rc;
7060 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7062 /* FLR cleanup - hmmm */
7063 if (!CHIP_IS_E1x(bp)) {
7064 rc = bnx2x_pf_flr_clnup(bp);
7069 /* set MSI reconfigure capability */
7070 if (bp->common.int_block == INT_BLOCK_HC) {
7071 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7072 val = REG_RD(bp, addr);
7073 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7074 REG_WR(bp, addr, val);
7077 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7078 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7081 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7083 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7084 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7085 ilt->lines[cdu_ilt_start + i].page_mapping =
7086 bp->context[i].cxt_mapping;
7087 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7089 bnx2x_ilt_init_op(bp, INITOP_SET);
7092 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7094 /* T1 hash bits value determines the T1 number of entries */
7095 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7100 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7101 #endif /* BCM_CNIC */
7103 if (!CHIP_IS_E1x(bp)) {
7104 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7106 /* Turn on a single ISR mode in IGU if driver is going to use
7109 if (!(bp->flags & USING_MSIX_FLAG))
7110 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7112 * Timers workaround bug: function init part.
7113 * Need to wait 20msec after initializing ILT,
7114 * needed to make sure there are no requests in
7115 * one of the PXP internal queues with "old" ILT addresses
7119 * Master enable - Due to WB DMAE writes performed before this
7120 * register is re-initialized as part of the regular function
7123 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7124 /* Enable the function in IGU */
7125 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7130 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7132 if (!CHIP_IS_E1x(bp))
7133 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7135 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7136 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7137 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7138 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7139 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7140 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7141 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7142 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7143 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7144 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7145 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7146 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7147 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7149 if (!CHIP_IS_E1x(bp))
7150 REG_WR(bp, QM_REG_PF_EN, 1);
7152 if (!CHIP_IS_E1x(bp)) {
7153 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7154 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7155 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7156 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7158 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7160 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7161 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7162 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7163 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7164 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7165 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7166 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7167 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7168 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7169 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7170 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7171 if (!CHIP_IS_E1x(bp))
7172 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7174 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7176 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7178 if (!CHIP_IS_E1x(bp))
7179 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7182 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7183 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7186 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7188 /* HC init per function */
7189 if (bp->common.int_block == INT_BLOCK_HC) {
7190 if (CHIP_IS_E1H(bp)) {
7191 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7193 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7194 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7196 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7199 int num_segs, sb_idx, prod_offset;
7201 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7203 if (!CHIP_IS_E1x(bp)) {
7204 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7205 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7208 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7210 if (!CHIP_IS_E1x(bp)) {
7214 * E2 mode: address 0-135 match to the mapping memory;
7215 * 136 - PF0 default prod; 137 - PF1 default prod;
7216 * 138 - PF2 default prod; 139 - PF3 default prod;
7217 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7218 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7221 * E1.5 mode - In backward compatible mode;
7222 * for non default SB; each even line in the memory
7223 * holds the U producer and each odd line hold
7224 * the C producer. The first 128 producers are for
7225 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7226 * producers are for the DSB for each PF.
7227 * Each PF has five segments: (the order inside each
7228 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7229 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7230 * 144-147 attn prods;
7232 /* non-default-status-blocks */
7233 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7234 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7235 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7236 prod_offset = (bp->igu_base_sb + sb_idx) *
7239 for (i = 0; i < num_segs; i++) {
7240 addr = IGU_REG_PROD_CONS_MEMORY +
7241 (prod_offset + i) * 4;
7242 REG_WR(bp, addr, 0);
7244 /* send consumer update with value 0 */
7245 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7246 USTORM_ID, 0, IGU_INT_NOP, 1);
7247 bnx2x_igu_clear_sb(bp,
7248 bp->igu_base_sb + sb_idx);
7251 /* default-status-blocks */
7252 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7253 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7255 if (CHIP_MODE_IS_4_PORT(bp))
7256 dsb_idx = BP_FUNC(bp);
7258 dsb_idx = BP_VN(bp);
7260 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7261 IGU_BC_BASE_DSB_PROD + dsb_idx :
7262 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7265 * igu prods come in chunks of E1HVN_MAX (4) -
7266 * does not matters what is the current chip mode
7268 for (i = 0; i < (num_segs * E1HVN_MAX);
7270 addr = IGU_REG_PROD_CONS_MEMORY +
7271 (prod_offset + i)*4;
7272 REG_WR(bp, addr, 0);
7274 /* send consumer update with 0 */
7275 if (CHIP_INT_MODE_IS_BC(bp)) {
7276 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7277 USTORM_ID, 0, IGU_INT_NOP, 1);
7278 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7279 CSTORM_ID, 0, IGU_INT_NOP, 1);
7280 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7281 XSTORM_ID, 0, IGU_INT_NOP, 1);
7282 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7283 TSTORM_ID, 0, IGU_INT_NOP, 1);
7284 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7285 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7287 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7288 USTORM_ID, 0, IGU_INT_NOP, 1);
7289 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7290 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7292 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7294 /* !!! these should become driver const once
7295 rf-tool supports split-68 const */
7296 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7297 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7298 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7299 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7300 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7301 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7305 /* Reset PCIE errors for debug */
7306 REG_WR(bp, 0x2114, 0xffffffff);
7307 REG_WR(bp, 0x2120, 0xffffffff);
7309 if (CHIP_IS_E1x(bp)) {
7310 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7311 main_mem_base = HC_REG_MAIN_MEMORY +
7312 BP_PORT(bp) * (main_mem_size * 4);
7313 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7316 val = REG_RD(bp, main_mem_prty_clr);
7319 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7322 /* Clear "false" parity errors in MSI-X table */
7323 for (i = main_mem_base;
7324 i < main_mem_base + main_mem_size * 4;
7325 i += main_mem_width) {
7326 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7327 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7328 i, main_mem_width / 4);
7330 /* Clear HC parity attention */
7331 REG_RD(bp, main_mem_prty_clr);
7334 #ifdef BNX2X_STOP_ON_ERROR
7335 /* Enable STORMs SP logging */
7336 REG_WR8(bp, BAR_USTRORM_INTMEM +
7337 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7338 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7339 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7340 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7341 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7342 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7343 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7346 bnx2x_phy_probe(&bp->link_params);
7352 void bnx2x_free_mem(struct bnx2x *bp)
7357 bnx2x_free_fp_mem(bp);
7358 /* end of fastpath */
7360 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7361 sizeof(struct host_sp_status_block));
7363 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7364 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7366 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7367 sizeof(struct bnx2x_slowpath));
7369 for (i = 0; i < L2_ILT_LINES(bp); i++)
7370 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7371 bp->context[i].size);
7372 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7374 BNX2X_FREE(bp->ilt->lines);
7377 if (!CHIP_IS_E1x(bp))
7378 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7379 sizeof(struct host_hc_status_block_e2));
7381 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7382 sizeof(struct host_hc_status_block_e1x));
7384 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7387 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7389 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7390 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7393 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7396 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7398 /* number of queues for statistics is number of eth queues + FCoE */
7399 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7401 /* Total number of FW statistics requests =
7402 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7405 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7408 /* Request is built from stats_query_header and an array of
7409 * stats_query_cmd_group each of which contains
7410 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7411 * configured in the stats_query_header.
7413 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7414 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7416 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7417 num_groups * sizeof(struct stats_query_cmd_group);
7419 /* Data for statistics requests + stats_conter
7421 * stats_counter holds per-STORM counters that are incremented
7422 * when STORM has finished with the current request.
7424 * memory for FCoE offloaded statistics are counted anyway,
7425 * even if they will not be sent.
7427 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7428 sizeof(struct per_pf_stats) +
7429 sizeof(struct fcoe_statistics_params) +
7430 sizeof(struct per_queue_stats) * num_queue_stats +
7431 sizeof(struct stats_counter);
7433 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7434 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7437 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7438 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7440 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7441 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7443 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7444 bp->fw_stats_req_sz;
7448 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7449 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7450 BNX2X_ERR("Can't allocate memory\n");
7455 int bnx2x_alloc_mem(struct bnx2x *bp)
7457 int i, allocated, context_size;
7460 if (!CHIP_IS_E1x(bp))
7461 /* size = the status block + ramrod buffers */
7462 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7463 sizeof(struct host_hc_status_block_e2));
7465 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7466 sizeof(struct host_hc_status_block_e1x));
7468 /* allocate searcher T2 table */
7469 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7473 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7474 sizeof(struct host_sp_status_block));
7476 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7477 sizeof(struct bnx2x_slowpath));
7480 /* write address to which L5 should insert its values */
7481 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7484 /* Allocated memory for FW statistics */
7485 if (bnx2x_alloc_fw_stats_mem(bp))
7488 /* Allocate memory for CDU context:
7489 * This memory is allocated separately and not in the generic ILT
7490 * functions because CDU differs in few aspects:
7491 * 1. There are multiple entities allocating memory for context -
7492 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7493 * its own ILT lines.
7494 * 2. Since CDU page-size is not a single 4KB page (which is the case
7495 * for the other ILT clients), to be efficient we want to support
7496 * allocation of sub-page-size in the last entry.
7497 * 3. Context pointers are used by the driver to pass to FW / update
7498 * the context (for the other ILT clients the pointers are used just to
7499 * free the memory during unload).
7501 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7503 for (i = 0, allocated = 0; allocated < context_size; i++) {
7504 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7505 (context_size - allocated));
7506 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7507 &bp->context[i].cxt_mapping,
7508 bp->context[i].size);
7509 allocated += bp->context[i].size;
7511 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7513 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7516 /* Slow path ring */
7517 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7520 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7521 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7525 /* need to be done at the end, since it's self adjusting to amount
7526 * of memory available for RSS queues
7528 if (bnx2x_alloc_fp_mem(bp))
7534 BNX2X_ERR("Can't allocate memory\n");
7539 * Init service functions
7542 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7543 struct bnx2x_vlan_mac_obj *obj, bool set,
7544 int mac_type, unsigned long *ramrod_flags)
7547 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7549 memset(&ramrod_param, 0, sizeof(ramrod_param));
7551 /* Fill general parameters */
7552 ramrod_param.vlan_mac_obj = obj;
7553 ramrod_param.ramrod_flags = *ramrod_flags;
7555 /* Fill a user request section if needed */
7556 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7557 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7559 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7561 /* Set the command: ADD or DEL */
7563 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7565 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7568 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7570 if (rc == -EEXIST) {
7571 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7572 /* do not treat adding same MAC as error */
7575 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7580 int bnx2x_del_all_macs(struct bnx2x *bp,
7581 struct bnx2x_vlan_mac_obj *mac_obj,
7582 int mac_type, bool wait_for_comp)
7585 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7587 /* Wait for completion of requested */
7589 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7591 /* Set the mac type of addresses we want to clear */
7592 __set_bit(mac_type, &vlan_mac_flags);
7594 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7596 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7601 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7603 unsigned long ramrod_flags = 0;
7606 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7607 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7608 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7609 "Ignoring Zero MAC for STORAGE SD mode\n");
7614 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7616 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7617 /* Eth MAC is set on RSS leading client (fp[0]) */
7618 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7619 set, BNX2X_ETH_MAC, &ramrod_flags);
7622 int bnx2x_setup_leading(struct bnx2x *bp)
7624 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7628 * bnx2x_set_int_mode - configure interrupt mode
7630 * @bp: driver handle
7632 * In case of MSI-X it will also try to enable MSI-X.
7634 void bnx2x_set_int_mode(struct bnx2x *bp)
7638 bnx2x_enable_msi(bp);
7639 /* falling through... */
7641 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7642 BNX2X_DEV_INFO("set number of queues to 1\n");
7645 /* if we can't use MSI-X we only need one fp,
7646 * so try to enable MSI-X with the requested number of fp's
7647 * and fallback to MSI or legacy INTx with one fp
7649 if (bnx2x_enable_msix(bp) ||
7650 bp->flags & USING_SINGLE_MSIX_FLAG) {
7651 /* failed to enable multiple MSI-X */
7652 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7653 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7655 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7657 /* Try to enable MSI */
7658 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7659 !(bp->flags & DISABLE_MSI_FLAG))
7660 bnx2x_enable_msi(bp);
7666 /* must be called prioir to any HW initializations */
7667 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7669 return L2_ILT_LINES(bp);
7672 void bnx2x_ilt_set_info(struct bnx2x *bp)
7674 struct ilt_client_info *ilt_client;
7675 struct bnx2x_ilt *ilt = BP_ILT(bp);
7678 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7679 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7682 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7683 ilt_client->client_num = ILT_CLIENT_CDU;
7684 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7685 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7686 ilt_client->start = line;
7687 line += bnx2x_cid_ilt_lines(bp);
7689 line += CNIC_ILT_LINES;
7691 ilt_client->end = line - 1;
7693 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7696 ilt_client->page_size,
7698 ilog2(ilt_client->page_size >> 12));
7701 if (QM_INIT(bp->qm_cid_count)) {
7702 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7703 ilt_client->client_num = ILT_CLIENT_QM;
7704 ilt_client->page_size = QM_ILT_PAGE_SZ;
7705 ilt_client->flags = 0;
7706 ilt_client->start = line;
7708 /* 4 bytes for each cid */
7709 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7712 ilt_client->end = line - 1;
7715 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7718 ilt_client->page_size,
7720 ilog2(ilt_client->page_size >> 12));
7724 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7726 ilt_client->client_num = ILT_CLIENT_SRC;
7727 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7728 ilt_client->flags = 0;
7729 ilt_client->start = line;
7730 line += SRC_ILT_LINES;
7731 ilt_client->end = line - 1;
7734 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7737 ilt_client->page_size,
7739 ilog2(ilt_client->page_size >> 12));
7742 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7746 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7748 ilt_client->client_num = ILT_CLIENT_TM;
7749 ilt_client->page_size = TM_ILT_PAGE_SZ;
7750 ilt_client->flags = 0;
7751 ilt_client->start = line;
7752 line += TM_ILT_LINES;
7753 ilt_client->end = line - 1;
7756 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7759 ilt_client->page_size,
7761 ilog2(ilt_client->page_size >> 12));
7764 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7766 BUG_ON(line > ILT_MAX_LINES);
7770 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7772 * @bp: driver handle
7773 * @fp: pointer to fastpath
7774 * @init_params: pointer to parameters structure
7776 * parameters configured:
7777 * - HC configuration
7778 * - Queue's CDU context
7780 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7781 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7785 int cxt_index, cxt_offset;
7787 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7788 if (!IS_FCOE_FP(fp)) {
7789 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7790 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7792 /* If HC is supporterd, enable host coalescing in the transition
7795 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7796 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7799 init_params->rx.hc_rate = bp->rx_ticks ?
7800 (1000000 / bp->rx_ticks) : 0;
7801 init_params->tx.hc_rate = bp->tx_ticks ?
7802 (1000000 / bp->tx_ticks) : 0;
7805 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7809 * CQ index among the SB indices: FCoE clients uses the default
7810 * SB, therefore it's different.
7812 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7813 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7816 /* set maximum number of COSs supported by this queue */
7817 init_params->max_cos = fp->max_cos;
7819 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7820 fp->index, init_params->max_cos);
7822 /* set the context pointers queue object */
7823 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7824 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7825 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7827 init_params->cxts[cos] =
7828 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7832 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7833 struct bnx2x_queue_state_params *q_params,
7834 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7835 int tx_index, bool leading)
7837 memset(tx_only_params, 0, sizeof(*tx_only_params));
7839 /* Set the command */
7840 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7842 /* Set tx-only QUEUE flags: don't zero statistics */
7843 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7845 /* choose the index of the cid to send the slow path on */
7846 tx_only_params->cid_index = tx_index;
7848 /* Set general TX_ONLY_SETUP parameters */
7849 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7851 /* Set Tx TX_ONLY_SETUP parameters */
7852 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7855 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7856 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7857 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7858 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7860 /* send the ramrod */
7861 return bnx2x_queue_state_change(bp, q_params);
7866 * bnx2x_setup_queue - setup queue
7868 * @bp: driver handle
7869 * @fp: pointer to fastpath
7870 * @leading: is leading
7872 * This function performs 2 steps in a Queue state machine
7873 * actually: 1) RESET->INIT 2) INIT->SETUP
7876 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7879 struct bnx2x_queue_state_params q_params = {NULL};
7880 struct bnx2x_queue_setup_params *setup_params =
7881 &q_params.params.setup;
7882 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7883 &q_params.params.tx_only;
7887 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7889 /* reset IGU state skip FCoE L2 queue */
7890 if (!IS_FCOE_FP(fp))
7891 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7894 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7895 /* We want to wait for completion in this context */
7896 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7898 /* Prepare the INIT parameters */
7899 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7901 /* Set the command */
7902 q_params.cmd = BNX2X_Q_CMD_INIT;
7904 /* Change the state to INIT */
7905 rc = bnx2x_queue_state_change(bp, &q_params);
7907 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7911 DP(NETIF_MSG_IFUP, "init complete\n");
7914 /* Now move the Queue to the SETUP state... */
7915 memset(setup_params, 0, sizeof(*setup_params));
7917 /* Set QUEUE flags */
7918 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7920 /* Set general SETUP parameters */
7921 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7922 FIRST_TX_COS_INDEX);
7924 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7925 &setup_params->rxq_params);
7927 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7928 FIRST_TX_COS_INDEX);
7930 /* Set the command */
7931 q_params.cmd = BNX2X_Q_CMD_SETUP;
7933 /* Change the state to SETUP */
7934 rc = bnx2x_queue_state_change(bp, &q_params);
7936 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7940 /* loop through the relevant tx-only indices */
7941 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7942 tx_index < fp->max_cos;
7945 /* prepare and send tx-only ramrod*/
7946 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7947 tx_only_params, tx_index, leading);
7949 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7950 fp->index, tx_index);
7958 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7960 struct bnx2x_fastpath *fp = &bp->fp[index];
7961 struct bnx2x_fp_txdata *txdata;
7962 struct bnx2x_queue_state_params q_params = {NULL};
7965 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7967 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7968 /* We want to wait for completion in this context */
7969 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7972 /* close tx-only connections */
7973 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7974 tx_index < fp->max_cos;
7977 /* ascertain this is a normal queue*/
7978 txdata = fp->txdata_ptr[tx_index];
7980 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7983 /* send halt terminate on tx-only connection */
7984 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7985 memset(&q_params.params.terminate, 0,
7986 sizeof(q_params.params.terminate));
7987 q_params.params.terminate.cid_index = tx_index;
7989 rc = bnx2x_queue_state_change(bp, &q_params);
7993 /* send halt terminate on tx-only connection */
7994 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7995 memset(&q_params.params.cfc_del, 0,
7996 sizeof(q_params.params.cfc_del));
7997 q_params.params.cfc_del.cid_index = tx_index;
7998 rc = bnx2x_queue_state_change(bp, &q_params);
8002 /* Stop the primary connection: */
8003 /* ...halt the connection */
8004 q_params.cmd = BNX2X_Q_CMD_HALT;
8005 rc = bnx2x_queue_state_change(bp, &q_params);
8009 /* ...terminate the connection */
8010 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8011 memset(&q_params.params.terminate, 0,
8012 sizeof(q_params.params.terminate));
8013 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8014 rc = bnx2x_queue_state_change(bp, &q_params);
8017 /* ...delete cfc entry */
8018 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8019 memset(&q_params.params.cfc_del, 0,
8020 sizeof(q_params.params.cfc_del));
8021 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8022 return bnx2x_queue_state_change(bp, &q_params);
8026 static void bnx2x_reset_func(struct bnx2x *bp)
8028 int port = BP_PORT(bp);
8029 int func = BP_FUNC(bp);
8032 /* Disable the function in the FW */
8033 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8034 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8035 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8036 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8039 for_each_eth_queue(bp, i) {
8040 struct bnx2x_fastpath *fp = &bp->fp[i];
8041 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8042 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8048 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8049 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8053 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8054 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8057 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8058 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8062 if (bp->common.int_block == INT_BLOCK_HC) {
8063 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8064 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8066 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8067 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8071 /* Disable Timer scan */
8072 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8074 * Wait for at least 10ms and up to 2 second for the timers scan to
8077 for (i = 0; i < 200; i++) {
8079 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8084 bnx2x_clear_func_ilt(bp, func);
8086 /* Timers workaround bug for E2: if this is vnic-3,
8087 * we need to set the entire ilt range for this timers.
8089 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8090 struct ilt_client_info ilt_cli;
8091 /* use dummy TM client */
8092 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8094 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8095 ilt_cli.client_num = ILT_CLIENT_TM;
8097 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8100 /* this assumes that reset_port() called before reset_func()*/
8101 if (!CHIP_IS_E1x(bp))
8102 bnx2x_pf_disable(bp);
8107 static void bnx2x_reset_port(struct bnx2x *bp)
8109 int port = BP_PORT(bp);
8112 /* Reset physical Link */
8113 bnx2x__link_reset(bp);
8115 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8117 /* Do not rcv packets to BRB */
8118 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8119 /* Do not direct rcv packets that are not for MCP to the BRB */
8120 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8121 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8124 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8127 /* Check for BRB port occupancy */
8128 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8130 DP(NETIF_MSG_IFDOWN,
8131 "BRB1 is not empty %d blocks are occupied\n", val);
8133 /* TODO: Close Doorbell port? */
8136 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8138 struct bnx2x_func_state_params func_params = {NULL};
8140 /* Prepare parameters for function state transitions */
8141 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8143 func_params.f_obj = &bp->func_obj;
8144 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8146 func_params.params.hw_init.load_phase = load_code;
8148 return bnx2x_func_state_change(bp, &func_params);
8151 static int bnx2x_func_stop(struct bnx2x *bp)
8153 struct bnx2x_func_state_params func_params = {NULL};
8156 /* Prepare parameters for function state transitions */
8157 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8158 func_params.f_obj = &bp->func_obj;
8159 func_params.cmd = BNX2X_F_CMD_STOP;
8162 * Try to stop the function the 'good way'. If fails (in case
8163 * of a parity error during bnx2x_chip_cleanup()) and we are
8164 * not in a debug mode, perform a state transaction in order to
8165 * enable further HW_RESET transaction.
8167 rc = bnx2x_func_state_change(bp, &func_params);
8169 #ifdef BNX2X_STOP_ON_ERROR
8172 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8173 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8174 return bnx2x_func_state_change(bp, &func_params);
8182 * bnx2x_send_unload_req - request unload mode from the MCP.
8184 * @bp: driver handle
8185 * @unload_mode: requested function's unload mode
8187 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8189 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8192 int port = BP_PORT(bp);
8194 /* Select the UNLOAD request mode */
8195 if (unload_mode == UNLOAD_NORMAL)
8196 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8198 else if (bp->flags & NO_WOL_FLAG)
8199 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8202 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8203 u8 *mac_addr = bp->dev->dev_addr;
8207 /* The mac address is written to entries 1-4 to
8208 * preserve entry 0 which is used by the PMF
8210 u8 entry = (BP_VN(bp) + 1)*8;
8212 val = (mac_addr[0] << 8) | mac_addr[1];
8213 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8215 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8216 (mac_addr[4] << 8) | mac_addr[5];
8217 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8219 /* Enable the PME and clear the status */
8220 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8221 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8222 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8224 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8227 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8229 /* Send the request to the MCP */
8231 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8233 int path = BP_PATH(bp);
8235 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8236 path, load_count[path][0], load_count[path][1],
8237 load_count[path][2]);
8238 load_count[path][0]--;
8239 load_count[path][1 + port]--;
8240 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8241 path, load_count[path][0], load_count[path][1],
8242 load_count[path][2]);
8243 if (load_count[path][0] == 0)
8244 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8245 else if (load_count[path][1 + port] == 0)
8246 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8248 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8255 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8257 * @bp: driver handle
8258 * @keep_link: true iff link should be kept up
8260 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8262 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8264 /* Report UNLOAD_DONE to MCP */
8266 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8269 static int bnx2x_func_wait_started(struct bnx2x *bp)
8272 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8278 * (assumption: No Attention from MCP at this stage)
8279 * PMF probably in the middle of TXdisable/enable transaction
8280 * 1. Sync IRS for default SB
8281 * 2. Sync SP queue - this guarantes us that attention handling started
8282 * 3. Wait, that TXdisable/enable transaction completes
8284 * 1+2 guranty that if DCBx attention was scheduled it already changed
8285 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8286 * received complettion for the transaction the state is TX_STOPPED.
8287 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8291 /* make sure default SB ISR is done */
8293 synchronize_irq(bp->msix_table[0].vector);
8295 synchronize_irq(bp->pdev->irq);
8297 flush_workqueue(bnx2x_wq);
8299 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8300 BNX2X_F_STATE_STARTED && tout--)
8303 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8304 BNX2X_F_STATE_STARTED) {
8305 #ifdef BNX2X_STOP_ON_ERROR
8306 BNX2X_ERR("Wrong function state\n");
8310 * Failed to complete the transaction in a "good way"
8311 * Force both transactions with CLR bit
8313 struct bnx2x_func_state_params func_params = {NULL};
8315 DP(NETIF_MSG_IFDOWN,
8316 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8318 func_params.f_obj = &bp->func_obj;
8319 __set_bit(RAMROD_DRV_CLR_ONLY,
8320 &func_params.ramrod_flags);
8322 /* STARTED-->TX_ST0PPED */
8323 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8324 bnx2x_func_state_change(bp, &func_params);
8326 /* TX_ST0PPED-->STARTED */
8327 func_params.cmd = BNX2X_F_CMD_TX_START;
8328 return bnx2x_func_state_change(bp, &func_params);
8335 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8337 int port = BP_PORT(bp);
8340 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8343 /* Wait until tx fastpath tasks complete */
8344 for_each_tx_queue(bp, i) {
8345 struct bnx2x_fastpath *fp = &bp->fp[i];
8347 for_each_cos_in_tx_queue(fp, cos)
8348 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8349 #ifdef BNX2X_STOP_ON_ERROR
8355 /* Give HW time to discard old tx messages */
8356 usleep_range(1000, 1000);
8358 /* Clean all ETH MACs */
8359 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8362 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8364 /* Clean up UC list */
8365 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8368 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8372 if (!CHIP_IS_E1(bp))
8373 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8375 /* Set "drop all" (stop Rx).
8376 * We need to take a netif_addr_lock() here in order to prevent
8377 * a race between the completion code and this code.
8379 netif_addr_lock_bh(bp->dev);
8380 /* Schedule the rx_mode command */
8381 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8382 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8384 bnx2x_set_storm_rx_mode(bp);
8386 /* Cleanup multicast configuration */
8387 rparam.mcast_obj = &bp->mcast_obj;
8388 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8390 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8392 netif_addr_unlock_bh(bp->dev);
8397 * Send the UNLOAD_REQUEST to the MCP. This will return if
8398 * this function should perform FUNC, PORT or COMMON HW
8401 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8404 * (assumption: No Attention from MCP at this stage)
8405 * PMF probably in the middle of TXdisable/enable transaction
8407 rc = bnx2x_func_wait_started(bp);
8409 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8410 #ifdef BNX2X_STOP_ON_ERROR
8415 /* Close multi and leading connections
8416 * Completions for ramrods are collected in a synchronous way
8418 for_each_queue(bp, i)
8419 if (bnx2x_stop_queue(bp, i))
8420 #ifdef BNX2X_STOP_ON_ERROR
8425 /* If SP settings didn't get completed so far - something
8426 * very wrong has happen.
8428 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8429 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8431 #ifndef BNX2X_STOP_ON_ERROR
8434 rc = bnx2x_func_stop(bp);
8436 BNX2X_ERR("Function stop failed!\n");
8437 #ifdef BNX2X_STOP_ON_ERROR
8442 /* Disable HW interrupts, NAPI */
8443 bnx2x_netif_stop(bp, 1);
8444 /* Delete all NAPI objects */
8445 bnx2x_del_all_napi(bp);
8450 /* Reset the chip */
8451 rc = bnx2x_reset_hw(bp, reset_code);
8453 BNX2X_ERR("HW_RESET failed\n");
8456 /* Report UNLOAD_DONE to MCP */
8457 bnx2x_send_unload_done(bp, keep_link);
8460 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8464 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8466 if (CHIP_IS_E1(bp)) {
8467 int port = BP_PORT(bp);
8468 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8469 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8471 val = REG_RD(bp, addr);
8473 REG_WR(bp, addr, val);
8475 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8476 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8477 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8478 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8482 /* Close gates #2, #3 and #4: */
8483 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8487 /* Gates #2 and #4a are closed/opened for "not E1" only */
8488 if (!CHIP_IS_E1(bp)) {
8490 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8492 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8496 if (CHIP_IS_E1x(bp)) {
8497 /* Prevent interrupts from HC on both ports */
8498 val = REG_RD(bp, HC_REG_CONFIG_1);
8499 REG_WR(bp, HC_REG_CONFIG_1,
8500 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8501 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8503 val = REG_RD(bp, HC_REG_CONFIG_0);
8504 REG_WR(bp, HC_REG_CONFIG_0,
8505 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8506 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8508 /* Prevent incomming interrupts in IGU */
8509 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8511 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8513 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8514 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8517 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8518 close ? "closing" : "opening");
8522 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8524 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8526 /* Do some magic... */
8527 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8528 *magic_val = val & SHARED_MF_CLP_MAGIC;
8529 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8533 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8535 * @bp: driver handle
8536 * @magic_val: old value of the `magic' bit.
8538 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8540 /* Restore the `magic' bit value... */
8541 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8542 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8543 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8547 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8549 * @bp: driver handle
8550 * @magic_val: old value of 'magic' bit.
8552 * Takes care of CLP configurations.
8554 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8557 u32 validity_offset;
8559 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8561 /* Set `magic' bit in order to save MF config */
8562 if (!CHIP_IS_E1(bp))
8563 bnx2x_clp_reset_prep(bp, magic_val);
8565 /* Get shmem offset */
8566 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8567 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8569 /* Clear validity map flags */
8571 REG_WR(bp, shmem + validity_offset, 0);
8574 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8575 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8578 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8580 * @bp: driver handle
8582 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8584 /* special handling for emulation and FPGA,
8585 wait 10 times longer */
8586 if (CHIP_REV_IS_SLOW(bp))
8587 msleep(MCP_ONE_TIMEOUT*10);
8589 msleep(MCP_ONE_TIMEOUT);
8593 * initializes bp->common.shmem_base and waits for validity signature to appear
8595 static int bnx2x_init_shmem(struct bnx2x *bp)
8601 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8602 if (bp->common.shmem_base) {
8603 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8604 if (val & SHR_MEM_VALIDITY_MB)
8608 bnx2x_mcp_wait_one(bp);
8610 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8612 BNX2X_ERR("BAD MCP validity signature\n");
8617 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8619 int rc = bnx2x_init_shmem(bp);
8621 /* Restore the `magic' bit value */
8622 if (!CHIP_IS_E1(bp))
8623 bnx2x_clp_reset_done(bp, magic_val);
8628 static void bnx2x_pxp_prep(struct bnx2x *bp)
8630 if (!CHIP_IS_E1(bp)) {
8631 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8632 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8638 * Reset the whole chip except for:
8640 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8643 * - MISC (including AEU)
8647 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8649 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8650 u32 global_bits2, stay_reset2;
8653 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8654 * (per chip) blocks.
8657 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8658 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8660 /* Don't reset the following blocks */
8662 MISC_REGISTERS_RESET_REG_1_RST_HC |
8663 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8664 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8667 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8668 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8669 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8670 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8671 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8672 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8673 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8674 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8675 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8676 MISC_REGISTERS_RESET_REG_2_PGLC;
8679 * Keep the following blocks in reset:
8680 * - all xxMACs are handled by the bnx2x_link code.
8683 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8684 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8685 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8686 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8687 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8688 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8689 MISC_REGISTERS_RESET_REG_2_XMAC |
8690 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8692 /* Full reset masks according to the chip */
8693 reset_mask1 = 0xffffffff;
8696 reset_mask2 = 0xffff;
8697 else if (CHIP_IS_E1H(bp))
8698 reset_mask2 = 0x1ffff;
8699 else if (CHIP_IS_E2(bp))
8700 reset_mask2 = 0xfffff;
8701 else /* CHIP_IS_E3 */
8702 reset_mask2 = 0x3ffffff;
8704 /* Don't reset global blocks unless we need to */
8706 reset_mask2 &= ~global_bits2;
8709 * In case of attention in the QM, we need to reset PXP
8710 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8711 * because otherwise QM reset would release 'close the gates' shortly
8712 * before resetting the PXP, then the PSWRQ would send a write
8713 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8714 * read the payload data from PSWWR, but PSWWR would not
8715 * respond. The write queue in PGLUE would stuck, dmae commands
8716 * would not return. Therefore it's important to reset the second
8717 * reset register (containing the
8718 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8719 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8722 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8723 reset_mask2 & (~not_reset_mask2));
8725 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8726 reset_mask1 & (~not_reset_mask1));
8731 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8732 reset_mask2 & (~stay_reset2));
8737 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8742 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8743 * It should get cleared in no more than 1s.
8745 * @bp: driver handle
8747 * It should get cleared in no more than 1s. Returns 0 if
8748 * pending writes bit gets cleared.
8750 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8756 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8761 usleep_range(1000, 1000);
8762 } while (cnt-- > 0);
8765 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8773 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8777 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8780 /* Empty the Tetris buffer, wait for 1s */
8782 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8783 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8784 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8785 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8786 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8787 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8788 ((port_is_idle_0 & 0x1) == 0x1) &&
8789 ((port_is_idle_1 & 0x1) == 0x1) &&
8790 (pgl_exp_rom2 == 0xffffffff))
8792 usleep_range(1000, 1000);
8793 } while (cnt-- > 0);
8796 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8797 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8798 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8805 /* Close gates #2, #3 and #4 */
8806 bnx2x_set_234_gates(bp, true);
8808 /* Poll for IGU VQs for 57712 and newer chips */
8809 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8813 /* TBD: Indicate that "process kill" is in progress to MCP */
8815 /* Clear "unprepared" bit */
8816 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8819 /* Make sure all is written to the chip before the reset */
8822 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8823 * PSWHST, GRC and PSWRD Tetris buffer.
8825 usleep_range(1000, 1000);
8827 /* Prepare to chip reset: */
8830 bnx2x_reset_mcp_prep(bp, &val);
8836 /* reset the chip */
8837 bnx2x_process_kill_chip_reset(bp, global);
8840 /* Recover after reset: */
8842 if (global && bnx2x_reset_mcp_comp(bp, val))
8845 /* TBD: Add resetting the NO_MCP mode DB here */
8850 /* Open the gates #2, #3 and #4 */
8851 bnx2x_set_234_gates(bp, false);
8853 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8854 * reset state, re-enable attentions. */
8859 int bnx2x_leader_reset(struct bnx2x *bp)
8862 bool global = bnx2x_reset_is_global(bp);
8865 /* if not going to reset MCP - load "fake" driver to reset HW while
8866 * driver is owner of the HW
8868 if (!global && !BP_NOMCP(bp)) {
8869 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
8870 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
8872 BNX2X_ERR("MCP response failure, aborting\n");
8874 goto exit_leader_reset;
8876 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8877 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8878 BNX2X_ERR("MCP unexpected resp, aborting\n");
8880 goto exit_leader_reset2;
8882 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8884 BNX2X_ERR("MCP response failure, aborting\n");
8886 goto exit_leader_reset2;
8890 /* Try to recover after the failure */
8891 if (bnx2x_process_kill(bp, global)) {
8892 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8895 goto exit_leader_reset2;
8899 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8902 bnx2x_set_reset_done(bp);
8904 bnx2x_clear_reset_global(bp);
8907 /* unload "fake driver" if it was loaded */
8908 if (!global && !BP_NOMCP(bp)) {
8909 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8910 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8914 bnx2x_release_leader_lock(bp);
8919 static void bnx2x_recovery_failed(struct bnx2x *bp)
8921 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8923 /* Disconnect this device */
8924 netif_device_detach(bp->dev);
8927 * Block ifup for all function on this engine until "process kill"
8930 bnx2x_set_reset_in_progress(bp);
8932 /* Shut down the power */
8933 bnx2x_set_power_state(bp, PCI_D3hot);
8935 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8941 * Assumption: runs under rtnl lock. This together with the fact
8942 * that it's called only from bnx2x_sp_rtnl() ensure that it
8943 * will never be called when netif_running(bp->dev) is false.
8945 static void bnx2x_parity_recover(struct bnx2x *bp)
8947 bool global = false;
8948 u32 error_recovered, error_unrecovered;
8951 DP(NETIF_MSG_HW, "Handling parity\n");
8953 switch (bp->recovery_state) {
8954 case BNX2X_RECOVERY_INIT:
8955 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8956 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8957 WARN_ON(!is_parity);
8959 /* Try to get a LEADER_LOCK HW lock */
8960 if (bnx2x_trylock_leader_lock(bp)) {
8961 bnx2x_set_reset_in_progress(bp);
8963 * Check if there is a global attention and if
8964 * there was a global attention, set the global
8969 bnx2x_set_reset_global(bp);
8974 /* Stop the driver */
8975 /* If interface has been removed - break */
8976 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
8979 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8981 /* Ensure "is_leader", MCP command sequence and
8982 * "recovery_state" update values are seen on other
8988 case BNX2X_RECOVERY_WAIT:
8989 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8990 if (bp->is_leader) {
8991 int other_engine = BP_PATH(bp) ? 0 : 1;
8992 bool other_load_status =
8993 bnx2x_get_load_status(bp, other_engine);
8995 bnx2x_get_load_status(bp, BP_PATH(bp));
8996 global = bnx2x_reset_is_global(bp);
8999 * In case of a parity in a global block, let
9000 * the first leader that performs a
9001 * leader_reset() reset the global blocks in
9002 * order to clear global attentions. Otherwise
9003 * the the gates will remain closed for that
9007 (global && other_load_status)) {
9008 /* Wait until all other functions get
9011 schedule_delayed_work(&bp->sp_rtnl_task,
9015 /* If all other functions got down -
9016 * try to bring the chip back to
9017 * normal. In any case it's an exit
9018 * point for a leader.
9020 if (bnx2x_leader_reset(bp)) {
9021 bnx2x_recovery_failed(bp);
9025 /* If we are here, means that the
9026 * leader has succeeded and doesn't
9027 * want to be a leader any more. Try
9028 * to continue as a none-leader.
9032 } else { /* non-leader */
9033 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9034 /* Try to get a LEADER_LOCK HW lock as
9035 * long as a former leader may have
9036 * been unloaded by the user or
9037 * released a leadership by another
9040 if (bnx2x_trylock_leader_lock(bp)) {
9041 /* I'm a leader now! Restart a
9048 schedule_delayed_work(&bp->sp_rtnl_task,
9054 * If there was a global attention, wait
9055 * for it to be cleared.
9057 if (bnx2x_reset_is_global(bp)) {
9058 schedule_delayed_work(
9065 bp->eth_stats.recoverable_error;
9067 bp->eth_stats.unrecoverable_error;
9068 bp->recovery_state =
9069 BNX2X_RECOVERY_NIC_LOADING;
9070 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9071 error_unrecovered++;
9073 "Recovery failed. Power cycle needed\n");
9074 /* Disconnect this device */
9075 netif_device_detach(bp->dev);
9076 /* Shut down the power */
9077 bnx2x_set_power_state(
9081 bp->recovery_state =
9082 BNX2X_RECOVERY_DONE;
9086 bp->eth_stats.recoverable_error =
9088 bp->eth_stats.unrecoverable_error =
9100 static int bnx2x_close(struct net_device *dev);
9102 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9103 * scheduled on a general queue in order to prevent a dead lock.
9105 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9107 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9111 if (!netif_running(bp->dev))
9114 /* if stop on error is defined no recovery flows should be executed */
9115 #ifdef BNX2X_STOP_ON_ERROR
9116 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9117 "you will need to reboot when done\n");
9118 goto sp_rtnl_not_reset;
9121 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9123 * Clear all pending SP commands as we are going to reset the
9126 bp->sp_rtnl_state = 0;
9129 bnx2x_parity_recover(bp);
9134 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9136 * Clear all pending SP commands as we are going to reset the
9139 bp->sp_rtnl_state = 0;
9142 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9143 bnx2x_nic_load(bp, LOAD_NORMAL);
9147 #ifdef BNX2X_STOP_ON_ERROR
9150 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9151 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9152 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9153 bnx2x_after_function_update(bp);
9155 * in case of fan failure we need to reset id if the "stop on error"
9156 * debug flag is set, since we trying to prevent permanent overheating
9159 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9160 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9161 netif_device_detach(bp->dev);
9162 bnx2x_close(bp->dev);
9169 /* end of nic load/unload */
9171 static void bnx2x_period_task(struct work_struct *work)
9173 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9175 if (!netif_running(bp->dev))
9176 goto period_task_exit;
9178 if (CHIP_REV_IS_SLOW(bp)) {
9179 BNX2X_ERR("period task called on emulation, ignoring\n");
9180 goto period_task_exit;
9183 bnx2x_acquire_phy_lock(bp);
9185 * The barrier is needed to ensure the ordering between the writing to
9186 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9191 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9193 /* Re-queue task in 1 sec */
9194 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9197 bnx2x_release_phy_lock(bp);
9203 * Init service functions
9206 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9208 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9209 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9210 return base + (BP_ABS_FUNC(bp)) * stride;
9213 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9215 u32 reg = bnx2x_get_pretend_reg(bp);
9217 /* Flush all outstanding writes */
9220 /* Pretend to be function 0 */
9222 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9224 /* From now we are in the "like-E1" mode */
9225 bnx2x_int_disable(bp);
9227 /* Flush all outstanding writes */
9230 /* Restore the original function */
9231 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9235 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9238 bnx2x_int_disable(bp);
9240 bnx2x_undi_int_disable_e1h(bp);
9243 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9245 u32 val, base_addr, offset, mask, reset_reg;
9246 bool mac_stopped = false;
9247 u8 port = BP_PORT(bp);
9249 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9251 if (!CHIP_IS_E3(bp)) {
9252 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9253 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9254 if ((mask & reset_reg) && val) {
9256 BNX2X_DEV_INFO("Disable bmac Rx\n");
9257 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9258 : NIG_REG_INGRESS_BMAC0_MEM;
9259 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9260 : BIGMAC_REGISTER_BMAC_CONTROL;
9263 * use rd/wr since we cannot use dmae. This is safe
9264 * since MCP won't access the bus due to the request
9265 * to unload, and no function on the path can be
9266 * loaded at this time.
9268 wb_data[0] = REG_RD(bp, base_addr + offset);
9269 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9270 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9271 REG_WR(bp, base_addr + offset, wb_data[0]);
9272 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9275 BNX2X_DEV_INFO("Disable emac Rx\n");
9276 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9280 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9281 BNX2X_DEV_INFO("Disable xmac Rx\n");
9282 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9283 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9284 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9286 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9288 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9291 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9292 if (mask & reset_reg) {
9293 BNX2X_DEV_INFO("Disable umac Rx\n");
9294 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9295 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9305 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9306 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9307 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9308 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9310 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9314 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9316 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9317 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9319 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9320 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9322 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9326 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9328 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9329 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9331 BNX2X_ERR("MCP response failure, aborting\n");
9338 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9340 struct bnx2x_prev_path_list *tmp_list;
9343 if (down_trylock(&bnx2x_prev_sem))
9346 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9347 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9348 bp->pdev->bus->number == tmp_list->bus &&
9349 BP_PATH(bp) == tmp_list->path) {
9351 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9357 up(&bnx2x_prev_sem);
9362 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9364 struct bnx2x_prev_path_list *tmp_list;
9367 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9369 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9373 tmp_list->bus = bp->pdev->bus->number;
9374 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9375 tmp_list->path = BP_PATH(bp);
9377 rc = down_interruptible(&bnx2x_prev_sem);
9379 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9382 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9384 list_add(&tmp_list->list, &bnx2x_prev_list);
9385 up(&bnx2x_prev_sem);
9391 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9395 struct pci_dev *dev = bp->pdev;
9398 if (CHIP_IS_E1x(bp)) {
9399 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9403 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9404 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9405 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9410 pos = pci_pcie_cap(dev);
9414 /* Wait for Transaction Pending bit clean */
9415 for (i = 0; i < 4; i++) {
9417 msleep((1 << (i - 1)) * 100);
9419 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9420 if (!(status & PCI_EXP_DEVSTA_TRPND))
9425 "transaction is not cleared; proceeding with reset anyway\n");
9429 BNX2X_DEV_INFO("Initiating FLR\n");
9430 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9435 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9439 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9441 /* Test if previous unload process was already finished for this path */
9442 if (bnx2x_prev_is_path_marked(bp))
9443 return bnx2x_prev_mcp_done(bp);
9445 /* If function has FLR capabilities, and existing FW version matches
9446 * the one required, then FLR will be sufficient to clean any residue
9447 * left by previous driver
9449 rc = bnx2x_test_firmware_version(bp, false);
9452 /* fw version is good */
9453 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9454 rc = bnx2x_do_flr(bp);
9458 /* FLR was performed */
9459 BNX2X_DEV_INFO("FLR successful\n");
9463 BNX2X_DEV_INFO("Could not FLR\n");
9465 /* Close the MCP request, return failure*/
9466 rc = bnx2x_prev_mcp_done(bp);
9468 rc = BNX2X_PREV_WAIT_NEEDED;
9473 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9475 u32 reset_reg, tmp_reg = 0, rc;
9476 /* It is possible a previous function received 'common' answer,
9477 * but hasn't loaded yet, therefore creating a scenario of
9478 * multiple functions receiving 'common' on the same path.
9480 BNX2X_DEV_INFO("Common unload Flow\n");
9482 if (bnx2x_prev_is_path_marked(bp))
9483 return bnx2x_prev_mcp_done(bp);
9485 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9487 /* Reset should be performed after BRB is emptied */
9488 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9489 u32 timer_count = 1000;
9490 bool prev_undi = false;
9492 /* Close the MAC Rx to prevent BRB from filling up */
9493 bnx2x_prev_unload_close_mac(bp);
9495 /* Check if the UNDI driver was previously loaded
9496 * UNDI driver initializes CID offset for normal bell to 0x7
9498 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9499 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9500 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9501 if (tmp_reg == 0x7) {
9502 BNX2X_DEV_INFO("UNDI previously loaded\n");
9504 /* clear the UNDI indication */
9505 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9508 /* wait until BRB is empty */
9509 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9510 while (timer_count) {
9511 u32 prev_brb = tmp_reg;
9513 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9517 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9519 /* reset timer as long as BRB actually gets emptied */
9520 if (prev_brb > tmp_reg)
9525 /* If UNDI resides in memory, manually increment it */
9527 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9533 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9537 /* No packets are in the pipeline, path is ready for reset */
9538 bnx2x_reset_common(bp);
9540 rc = bnx2x_prev_mark_path(bp);
9542 bnx2x_prev_mcp_done(bp);
9546 return bnx2x_prev_mcp_done(bp);
9549 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9550 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9551 * the addresses of the transaction, resulting in was-error bit set in the pci
9552 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9553 * to clear the interrupt which detected this from the pglueb and the was done
9556 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9558 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9559 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9560 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9561 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9565 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9567 int time_counter = 10;
9568 u32 rc, fw, hw_lock_reg, hw_lock_val;
9569 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9571 /* clear hw from errors which may have resulted from an interrupted
9574 bnx2x_prev_interrupted_dmae(bp);
9576 /* Release previously held locks */
9577 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9578 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9579 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9581 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9583 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9584 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9585 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9586 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9589 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9590 REG_WR(bp, hw_lock_reg, 0xffffffff);
9592 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9594 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9595 BNX2X_DEV_INFO("Release previously held alr\n");
9596 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9601 /* Lock MCP using an unload request */
9602 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9604 BNX2X_ERR("MCP response failure, aborting\n");
9609 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9610 rc = bnx2x_prev_unload_common(bp);
9614 /* non-common reply from MCP night require looping */
9615 rc = bnx2x_prev_unload_uncommon(bp);
9616 if (rc != BNX2X_PREV_WAIT_NEEDED)
9620 } while (--time_counter);
9622 if (!time_counter || rc) {
9623 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9627 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9632 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9634 u32 val, val2, val3, val4, id, boot_mode;
9637 /* Get the chip revision id and number. */
9638 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9639 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9640 id = ((val & 0xffff) << 16);
9641 val = REG_RD(bp, MISC_REG_CHIP_REV);
9642 id |= ((val & 0xf) << 12);
9643 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9644 id |= ((val & 0xff) << 4);
9645 val = REG_RD(bp, MISC_REG_BOND_ID);
9647 bp->common.chip_id = id;
9649 /* force 57811 according to MISC register */
9650 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9651 if (CHIP_IS_57810(bp))
9652 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9653 (bp->common.chip_id & 0x0000FFFF);
9654 else if (CHIP_IS_57810_MF(bp))
9655 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9656 (bp->common.chip_id & 0x0000FFFF);
9657 bp->common.chip_id |= 0x1;
9660 /* Set doorbell size */
9661 bp->db_size = (1 << BNX2X_DB_SHIFT);
9663 if (!CHIP_IS_E1x(bp)) {
9664 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9666 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9668 val = (val >> 1) & 1;
9669 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9671 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9674 if (CHIP_MODE_IS_4_PORT(bp))
9675 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9677 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9679 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9680 bp->pfid = bp->pf_num; /* 0..7 */
9683 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9685 bp->link_params.chip_id = bp->common.chip_id;
9686 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9688 val = (REG_RD(bp, 0x2874) & 0x55);
9689 if ((bp->common.chip_id & 0x1) ||
9690 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9691 bp->flags |= ONE_PORT_FLAG;
9692 BNX2X_DEV_INFO("single port device\n");
9695 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9696 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9697 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9698 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9699 bp->common.flash_size, bp->common.flash_size);
9701 bnx2x_init_shmem(bp);
9705 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9706 MISC_REG_GENERIC_CR_1 :
9707 MISC_REG_GENERIC_CR_0));
9709 bp->link_params.shmem_base = bp->common.shmem_base;
9710 bp->link_params.shmem2_base = bp->common.shmem2_base;
9711 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9712 bp->common.shmem_base, bp->common.shmem2_base);
9714 if (!bp->common.shmem_base) {
9715 BNX2X_DEV_INFO("MCP not active\n");
9716 bp->flags |= NO_MCP_FLAG;
9720 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9721 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9723 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9724 SHARED_HW_CFG_LED_MODE_MASK) >>
9725 SHARED_HW_CFG_LED_MODE_SHIFT);
9727 bp->link_params.feature_config_flags = 0;
9728 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9729 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9730 bp->link_params.feature_config_flags |=
9731 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9733 bp->link_params.feature_config_flags &=
9734 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9736 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9737 bp->common.bc_ver = val;
9738 BNX2X_DEV_INFO("bc_ver %X\n", val);
9739 if (val < BNX2X_BC_VER) {
9740 /* for now only warn
9741 * later we might need to enforce this */
9742 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9745 bp->link_params.feature_config_flags |=
9746 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9747 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9749 bp->link_params.feature_config_flags |=
9750 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9751 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9752 bp->link_params.feature_config_flags |=
9753 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9754 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9755 bp->link_params.feature_config_flags |=
9756 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9757 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9758 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9759 BC_SUPPORTS_PFC_STATS : 0;
9761 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9762 BC_SUPPORTS_FCOE_FEATURES : 0;
9764 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9765 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9766 boot_mode = SHMEM_RD(bp,
9767 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9768 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9769 switch (boot_mode) {
9770 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9771 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9773 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9774 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9776 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9777 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9779 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9780 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9784 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9785 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9787 BNX2X_DEV_INFO("%sWoL capable\n",
9788 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9790 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9791 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9792 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9793 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9795 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9796 val, val2, val3, val4);
9799 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9800 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9802 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9804 int pfid = BP_FUNC(bp);
9807 u8 fid, igu_sb_cnt = 0;
9809 bp->igu_base_sb = 0xff;
9810 if (CHIP_INT_MODE_IS_BC(bp)) {
9812 igu_sb_cnt = bp->igu_sb_cnt;
9813 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9816 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9817 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9822 /* IGU in normal mode - read CAM */
9823 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9825 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9826 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9829 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9830 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9832 if (IGU_VEC(val) == 0)
9833 /* default status block */
9834 bp->igu_dsb_id = igu_sb_id;
9836 if (bp->igu_base_sb == 0xff)
9837 bp->igu_base_sb = igu_sb_id;
9843 #ifdef CONFIG_PCI_MSI
9844 /* Due to new PF resource allocation by MFW T7.4 and above, it's
9845 * optional that number of CAM entries will not be equal to the value
9846 * advertised in PCI.
9847 * Driver should use the minimal value of both as the actual status
9850 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
9853 if (igu_sb_cnt == 0)
9854 BNX2X_ERR("CAM configuration error\n");
9857 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9860 int cfg_size = 0, idx, port = BP_PORT(bp);
9862 /* Aggregation of supported attributes of all external phys */
9863 bp->port.supported[0] = 0;
9864 bp->port.supported[1] = 0;
9865 switch (bp->link_params.num_phys) {
9867 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9871 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9875 if (bp->link_params.multi_phy_config &
9876 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9877 bp->port.supported[1] =
9878 bp->link_params.phy[EXT_PHY1].supported;
9879 bp->port.supported[0] =
9880 bp->link_params.phy[EXT_PHY2].supported;
9882 bp->port.supported[0] =
9883 bp->link_params.phy[EXT_PHY1].supported;
9884 bp->port.supported[1] =
9885 bp->link_params.phy[EXT_PHY2].supported;
9891 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9892 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9894 dev_info.port_hw_config[port].external_phy_config),
9896 dev_info.port_hw_config[port].external_phy_config2));
9901 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9903 switch (switch_cfg) {
9905 bp->port.phy_addr = REG_RD(
9906 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9908 case SWITCH_CFG_10G:
9909 bp->port.phy_addr = REG_RD(
9910 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9913 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9914 bp->port.link_config[0]);
9918 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9919 /* mask what we support according to speed_cap_mask per configuration */
9920 for (idx = 0; idx < cfg_size; idx++) {
9921 if (!(bp->link_params.speed_cap_mask[idx] &
9922 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9923 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9925 if (!(bp->link_params.speed_cap_mask[idx] &
9926 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9927 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9929 if (!(bp->link_params.speed_cap_mask[idx] &
9930 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9931 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9933 if (!(bp->link_params.speed_cap_mask[idx] &
9934 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9935 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9937 if (!(bp->link_params.speed_cap_mask[idx] &
9938 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9939 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9940 SUPPORTED_1000baseT_Full);
9942 if (!(bp->link_params.speed_cap_mask[idx] &
9943 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9944 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9946 if (!(bp->link_params.speed_cap_mask[idx] &
9947 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9948 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9952 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9953 bp->port.supported[1]);
9956 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9958 u32 link_config, idx, cfg_size = 0;
9959 bp->port.advertising[0] = 0;
9960 bp->port.advertising[1] = 0;
9961 switch (bp->link_params.num_phys) {
9970 for (idx = 0; idx < cfg_size; idx++) {
9971 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9972 link_config = bp->port.link_config[idx];
9973 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9974 case PORT_FEATURE_LINK_SPEED_AUTO:
9975 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9976 bp->link_params.req_line_speed[idx] =
9978 bp->port.advertising[idx] |=
9979 bp->port.supported[idx];
9980 if (bp->link_params.phy[EXT_PHY1].type ==
9981 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9982 bp->port.advertising[idx] |=
9983 (SUPPORTED_100baseT_Half |
9984 SUPPORTED_100baseT_Full);
9986 /* force 10G, no AN */
9987 bp->link_params.req_line_speed[idx] =
9989 bp->port.advertising[idx] |=
9990 (ADVERTISED_10000baseT_Full |
9996 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9997 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9998 bp->link_params.req_line_speed[idx] =
10000 bp->port.advertising[idx] |=
10001 (ADVERTISED_10baseT_Full |
10004 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10006 bp->link_params.speed_cap_mask[idx]);
10011 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10012 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10013 bp->link_params.req_line_speed[idx] =
10015 bp->link_params.req_duplex[idx] =
10017 bp->port.advertising[idx] |=
10018 (ADVERTISED_10baseT_Half |
10021 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10023 bp->link_params.speed_cap_mask[idx]);
10028 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10029 if (bp->port.supported[idx] &
10030 SUPPORTED_100baseT_Full) {
10031 bp->link_params.req_line_speed[idx] =
10033 bp->port.advertising[idx] |=
10034 (ADVERTISED_100baseT_Full |
10037 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10039 bp->link_params.speed_cap_mask[idx]);
10044 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10045 if (bp->port.supported[idx] &
10046 SUPPORTED_100baseT_Half) {
10047 bp->link_params.req_line_speed[idx] =
10049 bp->link_params.req_duplex[idx] =
10051 bp->port.advertising[idx] |=
10052 (ADVERTISED_100baseT_Half |
10055 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10057 bp->link_params.speed_cap_mask[idx]);
10062 case PORT_FEATURE_LINK_SPEED_1G:
10063 if (bp->port.supported[idx] &
10064 SUPPORTED_1000baseT_Full) {
10065 bp->link_params.req_line_speed[idx] =
10067 bp->port.advertising[idx] |=
10068 (ADVERTISED_1000baseT_Full |
10071 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10073 bp->link_params.speed_cap_mask[idx]);
10078 case PORT_FEATURE_LINK_SPEED_2_5G:
10079 if (bp->port.supported[idx] &
10080 SUPPORTED_2500baseX_Full) {
10081 bp->link_params.req_line_speed[idx] =
10083 bp->port.advertising[idx] |=
10084 (ADVERTISED_2500baseX_Full |
10087 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10089 bp->link_params.speed_cap_mask[idx]);
10094 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10095 if (bp->port.supported[idx] &
10096 SUPPORTED_10000baseT_Full) {
10097 bp->link_params.req_line_speed[idx] =
10099 bp->port.advertising[idx] |=
10100 (ADVERTISED_10000baseT_Full |
10103 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10105 bp->link_params.speed_cap_mask[idx]);
10109 case PORT_FEATURE_LINK_SPEED_20G:
10110 bp->link_params.req_line_speed[idx] = SPEED_20000;
10114 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10116 bp->link_params.req_line_speed[idx] =
10118 bp->port.advertising[idx] =
10119 bp->port.supported[idx];
10123 bp->link_params.req_flow_ctrl[idx] = (link_config &
10124 PORT_FEATURE_FLOW_CONTROL_MASK);
10125 if ((bp->link_params.req_flow_ctrl[idx] ==
10126 BNX2X_FLOW_CTRL_AUTO) &&
10127 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10128 bp->link_params.req_flow_ctrl[idx] =
10129 BNX2X_FLOW_CTRL_NONE;
10132 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10133 bp->link_params.req_line_speed[idx],
10134 bp->link_params.req_duplex[idx],
10135 bp->link_params.req_flow_ctrl[idx],
10136 bp->port.advertising[idx]);
10140 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10142 mac_hi = cpu_to_be16(mac_hi);
10143 mac_lo = cpu_to_be32(mac_lo);
10144 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10145 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10148 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10150 int port = BP_PORT(bp);
10152 u32 ext_phy_type, ext_phy_config, eee_mode;
10154 bp->link_params.bp = bp;
10155 bp->link_params.port = port;
10157 bp->link_params.lane_config =
10158 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10160 bp->link_params.speed_cap_mask[0] =
10162 dev_info.port_hw_config[port].speed_capability_mask);
10163 bp->link_params.speed_cap_mask[1] =
10165 dev_info.port_hw_config[port].speed_capability_mask2);
10166 bp->port.link_config[0] =
10167 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10169 bp->port.link_config[1] =
10170 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10172 bp->link_params.multi_phy_config =
10173 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10174 /* If the device is capable of WoL, set the default state according
10177 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10178 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10179 (config & PORT_FEATURE_WOL_ENABLED));
10181 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10182 bp->link_params.lane_config,
10183 bp->link_params.speed_cap_mask[0],
10184 bp->port.link_config[0]);
10186 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10187 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10188 bnx2x_phy_probe(&bp->link_params);
10189 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10191 bnx2x_link_settings_requested(bp);
10194 * If connected directly, work with the internal PHY, otherwise, work
10195 * with the external PHY
10199 dev_info.port_hw_config[port].external_phy_config);
10200 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10201 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10202 bp->mdio.prtad = bp->port.phy_addr;
10204 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10205 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10207 XGXS_EXT_PHY_ADDR(ext_phy_config);
10210 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10211 * In MF mode, it is set to cover self test cases
10214 bp->port.need_hw_lock = 1;
10216 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10217 bp->common.shmem_base,
10218 bp->common.shmem2_base);
10220 /* Configure link feature according to nvram value */
10221 eee_mode = (((SHMEM_RD(bp, dev_info.
10222 port_feature_config[port].eee_power_mode)) &
10223 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10224 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10225 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10226 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10227 EEE_MODE_ENABLE_LPI |
10228 EEE_MODE_OUTPUT_TIME;
10230 bp->link_params.eee_mode = 0;
10234 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10236 u32 no_flags = NO_ISCSI_FLAG;
10238 int port = BP_PORT(bp);
10240 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10241 drv_lic_key[port].max_iscsi_conn);
10243 /* Get the number of maximum allowed iSCSI connections */
10244 bp->cnic_eth_dev.max_iscsi_conn =
10245 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10246 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10248 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10249 bp->cnic_eth_dev.max_iscsi_conn);
10252 * If maximum allowed number of connections is zero -
10253 * disable the feature.
10255 if (!bp->cnic_eth_dev.max_iscsi_conn)
10256 bp->flags |= no_flags;
10258 bp->flags |= no_flags;
10263 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10266 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10267 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10268 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10269 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10272 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10273 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10274 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10275 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10278 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10281 int port = BP_PORT(bp);
10282 int func = BP_ABS_FUNC(bp);
10284 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10285 drv_lic_key[port].max_fcoe_conn);
10287 /* Get the number of maximum allowed FCoE connections */
10288 bp->cnic_eth_dev.max_fcoe_conn =
10289 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10290 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10292 /* Read the WWN: */
10295 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10297 dev_info.port_hw_config[port].
10298 fcoe_wwn_port_name_upper);
10299 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10301 dev_info.port_hw_config[port].
10302 fcoe_wwn_port_name_lower);
10305 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10307 dev_info.port_hw_config[port].
10308 fcoe_wwn_node_name_upper);
10309 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10311 dev_info.port_hw_config[port].
10312 fcoe_wwn_node_name_lower);
10313 } else if (!IS_MF_SD(bp)) {
10315 * Read the WWN info only if the FCoE feature is enabled for
10318 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10319 bnx2x_get_ext_wwn_info(bp, func);
10321 } else if (IS_MF_FCOE_SD(bp))
10322 bnx2x_get_ext_wwn_info(bp, func);
10324 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10327 * If maximum allowed number of connections is zero -
10328 * disable the feature.
10330 if (!bp->cnic_eth_dev.max_fcoe_conn)
10331 bp->flags |= NO_FCOE_FLAG;
10333 bp->flags |= NO_FCOE_FLAG;
10337 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10340 * iSCSI may be dynamically disabled but reading
10341 * info here we will decrease memory usage by driver
10342 * if the feature is disabled for good
10344 bnx2x_get_iscsi_info(bp);
10345 bnx2x_get_fcoe_info(bp);
10348 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10351 int func = BP_ABS_FUNC(bp);
10352 int port = BP_PORT(bp);
10354 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10355 u8 *fip_mac = bp->fip_mac;
10358 /* Zero primary MAC configuration */
10359 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10361 if (BP_NOMCP(bp)) {
10362 BNX2X_ERROR("warning: random MAC workaround active\n");
10363 eth_hw_addr_random(bp->dev);
10364 } else if (IS_MF(bp)) {
10365 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10366 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10367 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10368 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10369 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10373 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10374 * FCoE MAC then the appropriate feature should be disabled.
10376 * In non SD mode features configuration comes from
10377 * struct func_ext_config.
10379 if (!IS_MF_SD(bp)) {
10380 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10381 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10382 val2 = MF_CFG_RD(bp, func_ext_config[func].
10383 iscsi_mac_addr_upper);
10384 val = MF_CFG_RD(bp, func_ext_config[func].
10385 iscsi_mac_addr_lower);
10386 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10387 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10390 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10392 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10393 val2 = MF_CFG_RD(bp, func_ext_config[func].
10394 fcoe_mac_addr_upper);
10395 val = MF_CFG_RD(bp, func_ext_config[func].
10396 fcoe_mac_addr_lower);
10397 bnx2x_set_mac_buf(fip_mac, val, val2);
10398 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10402 bp->flags |= NO_FCOE_FLAG;
10404 bp->mf_ext_config = cfg;
10406 } else { /* SD MODE */
10407 if (IS_MF_STORAGE_SD(bp)) {
10408 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10409 /* use primary mac as iscsi mac */
10410 memcpy(iscsi_mac, bp->dev->dev_addr,
10413 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10414 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10416 } else { /* FCoE */
10417 memcpy(fip_mac, bp->dev->dev_addr,
10419 BNX2X_DEV_INFO("SD FCoE MODE\n");
10420 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10423 /* Zero primary MAC configuration */
10424 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10428 if (IS_MF_FCOE_AFEX(bp))
10429 /* use FIP MAC as primary MAC */
10430 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10434 /* in SF read MACs from port configuration */
10435 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10436 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10437 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10440 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10442 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10444 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10446 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10447 fcoe_fip_mac_upper);
10448 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10449 fcoe_fip_mac_lower);
10450 bnx2x_set_mac_buf(fip_mac, val, val2);
10454 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10455 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10458 /* Disable iSCSI if MAC configuration is
10461 if (!is_valid_ether_addr(iscsi_mac)) {
10462 bp->flags |= NO_ISCSI_FLAG;
10463 memset(iscsi_mac, 0, ETH_ALEN);
10466 /* Disable FCoE if MAC configuration is
10469 if (!is_valid_ether_addr(fip_mac)) {
10470 bp->flags |= NO_FCOE_FLAG;
10471 memset(bp->fip_mac, 0, ETH_ALEN);
10475 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10476 dev_err(&bp->pdev->dev,
10477 "bad Ethernet MAC address configuration: %pM\n"
10478 "change it manually before bringing up the appropriate network interface\n",
10479 bp->dev->dev_addr);
10484 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10486 int /*abs*/func = BP_ABS_FUNC(bp);
10491 bnx2x_get_common_hwinfo(bp);
10494 * initialize IGU parameters
10496 if (CHIP_IS_E1x(bp)) {
10497 bp->common.int_block = INT_BLOCK_HC;
10499 bp->igu_dsb_id = DEF_SB_IGU_ID;
10500 bp->igu_base_sb = 0;
10502 bp->common.int_block = INT_BLOCK_IGU;
10504 /* do not allow device reset during IGU info preocessing */
10505 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10507 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10509 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10512 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10514 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10515 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10516 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10518 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10520 usleep_range(1000, 1000);
10523 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10524 dev_err(&bp->pdev->dev,
10525 "FORCING Normal Mode failed!!!\n");
10530 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10531 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10532 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10534 BNX2X_DEV_INFO("IGU Normal Mode\n");
10536 bnx2x_get_igu_cam_info(bp);
10538 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10542 * set base FW non-default (fast path) status block id, this value is
10543 * used to initialize the fw_sb_id saved on the fp/queue structure to
10544 * determine the id used by the FW.
10546 if (CHIP_IS_E1x(bp))
10547 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10549 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10550 * the same queue are indicated on the same IGU SB). So we prefer
10551 * FW and IGU SBs to be the same value.
10553 bp->base_fw_ndsb = bp->igu_base_sb;
10555 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10556 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10557 bp->igu_sb_cnt, bp->base_fw_ndsb);
10560 * Initialize MF configuration
10567 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10568 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10569 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10570 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10572 if (SHMEM2_HAS(bp, mf_cfg_addr))
10573 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10575 bp->common.mf_cfg_base = bp->common.shmem_base +
10576 offsetof(struct shmem_region, func_mb) +
10577 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10579 * get mf configuration:
10580 * 1. existence of MF configuration
10581 * 2. MAC address must be legal (check only upper bytes)
10582 * for Switch-Independent mode;
10583 * OVLAN must be legal for Switch-Dependent mode
10584 * 3. SF_MODE configures specific MF mode
10586 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10587 /* get mf configuration */
10589 dev_info.shared_feature_config.config);
10590 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10593 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10594 val = MF_CFG_RD(bp, func_mf_config[func].
10596 /* check for legal mac (upper bytes)*/
10597 if (val != 0xffff) {
10598 bp->mf_mode = MULTI_FUNCTION_SI;
10599 bp->mf_config[vn] = MF_CFG_RD(bp,
10600 func_mf_config[func].config);
10602 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10604 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10605 if ((!CHIP_IS_E1x(bp)) &&
10606 (MF_CFG_RD(bp, func_mf_config[func].
10607 mac_upper) != 0xffff) &&
10609 afex_driver_support))) {
10610 bp->mf_mode = MULTI_FUNCTION_AFEX;
10611 bp->mf_config[vn] = MF_CFG_RD(bp,
10612 func_mf_config[func].config);
10614 BNX2X_DEV_INFO("can not configure afex mode\n");
10617 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10618 /* get OV configuration */
10619 val = MF_CFG_RD(bp,
10620 func_mf_config[FUNC_0].e1hov_tag);
10621 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10623 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10624 bp->mf_mode = MULTI_FUNCTION_SD;
10625 bp->mf_config[vn] = MF_CFG_RD(bp,
10626 func_mf_config[func].config);
10628 BNX2X_DEV_INFO("illegal OV for SD\n");
10631 /* Unknown configuration: reset mf_config */
10632 bp->mf_config[vn] = 0;
10633 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10637 BNX2X_DEV_INFO("%s function mode\n",
10638 IS_MF(bp) ? "multi" : "single");
10640 switch (bp->mf_mode) {
10641 case MULTI_FUNCTION_SD:
10642 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10643 FUNC_MF_CFG_E1HOV_TAG_MASK;
10644 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10646 bp->path_has_ovlan = true;
10648 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10649 func, bp->mf_ov, bp->mf_ov);
10651 dev_err(&bp->pdev->dev,
10652 "No valid MF OV for func %d, aborting\n",
10657 case MULTI_FUNCTION_AFEX:
10658 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10660 case MULTI_FUNCTION_SI:
10661 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10666 dev_err(&bp->pdev->dev,
10667 "VN %d is in a single function mode, aborting\n",
10674 /* check if other port on the path needs ovlan:
10675 * Since MF configuration is shared between ports
10676 * Possible mixed modes are only
10677 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10679 if (CHIP_MODE_IS_4_PORT(bp) &&
10680 !bp->path_has_ovlan &&
10682 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10683 u8 other_port = !BP_PORT(bp);
10684 u8 other_func = BP_PATH(bp) + 2*other_port;
10685 val = MF_CFG_RD(bp,
10686 func_mf_config[other_func].e1hov_tag);
10687 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10688 bp->path_has_ovlan = true;
10692 /* adjust igu_sb_cnt to MF for E1x */
10693 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10694 bp->igu_sb_cnt /= E1HVN_MAX;
10697 bnx2x_get_port_hwinfo(bp);
10699 /* Get MAC addresses */
10700 bnx2x_get_mac_hwinfo(bp);
10702 bnx2x_get_cnic_info(bp);
10707 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10709 int cnt, i, block_end, rodi;
10710 char vpd_start[BNX2X_VPD_LEN+1];
10711 char str_id_reg[VENDOR_ID_LEN+1];
10712 char str_id_cap[VENDOR_ID_LEN+1];
10714 char *vpd_extended_data = NULL;
10717 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10718 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10720 if (cnt < BNX2X_VPD_LEN)
10721 goto out_not_found;
10723 /* VPD RO tag should be first tag after identifier string, hence
10724 * we should be able to find it in first BNX2X_VPD_LEN chars
10726 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10727 PCI_VPD_LRDT_RO_DATA);
10729 goto out_not_found;
10731 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10732 pci_vpd_lrdt_size(&vpd_start[i]);
10734 i += PCI_VPD_LRDT_TAG_SIZE;
10736 if (block_end > BNX2X_VPD_LEN) {
10737 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10738 if (vpd_extended_data == NULL)
10739 goto out_not_found;
10741 /* read rest of vpd image into vpd_extended_data */
10742 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10743 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10744 block_end - BNX2X_VPD_LEN,
10745 vpd_extended_data + BNX2X_VPD_LEN);
10746 if (cnt < (block_end - BNX2X_VPD_LEN))
10747 goto out_not_found;
10748 vpd_data = vpd_extended_data;
10750 vpd_data = vpd_start;
10752 /* now vpd_data holds full vpd content in both cases */
10754 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10755 PCI_VPD_RO_KEYWORD_MFR_ID);
10757 goto out_not_found;
10759 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10761 if (len != VENDOR_ID_LEN)
10762 goto out_not_found;
10764 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10766 /* vendor specific info */
10767 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10768 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10769 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10770 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10772 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10773 PCI_VPD_RO_KEYWORD_VENDOR0);
10775 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10777 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10779 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10780 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10781 bp->fw_ver[len] = ' ';
10784 kfree(vpd_extended_data);
10788 kfree(vpd_extended_data);
10792 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10796 if (CHIP_REV_IS_FPGA(bp))
10797 SET_FLAGS(flags, MODE_FPGA);
10798 else if (CHIP_REV_IS_EMUL(bp))
10799 SET_FLAGS(flags, MODE_EMUL);
10801 SET_FLAGS(flags, MODE_ASIC);
10803 if (CHIP_MODE_IS_4_PORT(bp))
10804 SET_FLAGS(flags, MODE_PORT4);
10806 SET_FLAGS(flags, MODE_PORT2);
10808 if (CHIP_IS_E2(bp))
10809 SET_FLAGS(flags, MODE_E2);
10810 else if (CHIP_IS_E3(bp)) {
10811 SET_FLAGS(flags, MODE_E3);
10812 if (CHIP_REV(bp) == CHIP_REV_Ax)
10813 SET_FLAGS(flags, MODE_E3_A0);
10814 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10815 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10819 SET_FLAGS(flags, MODE_MF);
10820 switch (bp->mf_mode) {
10821 case MULTI_FUNCTION_SD:
10822 SET_FLAGS(flags, MODE_MF_SD);
10824 case MULTI_FUNCTION_SI:
10825 SET_FLAGS(flags, MODE_MF_SI);
10827 case MULTI_FUNCTION_AFEX:
10828 SET_FLAGS(flags, MODE_MF_AFEX);
10832 SET_FLAGS(flags, MODE_SF);
10834 #if defined(__LITTLE_ENDIAN)
10835 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10836 #else /*(__BIG_ENDIAN)*/
10837 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10839 INIT_MODE_FLAGS(bp) = flags;
10842 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10847 mutex_init(&bp->port.phy_mutex);
10848 mutex_init(&bp->fw_mb_mutex);
10849 spin_lock_init(&bp->stats_lock);
10851 mutex_init(&bp->cnic_mutex);
10854 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10855 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10856 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10857 rc = bnx2x_get_hwinfo(bp);
10861 bnx2x_set_modes_bitmap(bp);
10863 rc = bnx2x_alloc_mem_bp(bp);
10867 bnx2x_read_fwinfo(bp);
10869 func = BP_FUNC(bp);
10871 /* need to reset chip if undi was active */
10872 if (!BP_NOMCP(bp)) {
10875 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10876 DRV_MSG_SEQ_NUMBER_MASK;
10877 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10879 bnx2x_prev_unload(bp);
10883 if (CHIP_REV_IS_FPGA(bp))
10884 dev_err(&bp->pdev->dev, "FPGA detected\n");
10886 if (BP_NOMCP(bp) && (func == 0))
10887 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10889 bp->disable_tpa = disable_tpa;
10892 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10895 /* Set TPA flags */
10896 if (bp->disable_tpa) {
10897 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10898 bp->dev->features &= ~NETIF_F_LRO;
10900 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10901 bp->dev->features |= NETIF_F_LRO;
10904 if (CHIP_IS_E1(bp))
10905 bp->dropless_fc = 0;
10907 bp->dropless_fc = dropless_fc;
10911 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10913 /* make sure that the numbers are in the right granularity */
10914 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10915 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10917 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10919 init_timer(&bp->timer);
10920 bp->timer.expires = jiffies + bp->current_interval;
10921 bp->timer.data = (unsigned long) bp;
10922 bp->timer.function = bnx2x_timer;
10924 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10925 bnx2x_dcbx_init_params(bp);
10928 if (CHIP_IS_E1x(bp))
10929 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10931 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10934 /* multiple tx priority */
10935 if (CHIP_IS_E1x(bp))
10936 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10937 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10938 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10939 if (CHIP_IS_E3B0(bp))
10940 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10946 /****************************************************************************
10947 * General service functions
10948 ****************************************************************************/
10951 * net_device service functions
10954 /* called with rtnl_lock */
10955 static int bnx2x_open(struct net_device *dev)
10957 struct bnx2x *bp = netdev_priv(dev);
10958 bool global = false;
10959 int other_engine = BP_PATH(bp) ? 0 : 1;
10960 bool other_load_status, load_status;
10962 bp->stats_init = true;
10964 netif_carrier_off(dev);
10966 bnx2x_set_power_state(bp, PCI_D0);
10968 other_load_status = bnx2x_get_load_status(bp, other_engine);
10969 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10972 * If parity had happen during the unload, then attentions
10973 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10974 * want the first function loaded on the current engine to
10975 * complete the recovery.
10977 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10978 bnx2x_chk_parity_attn(bp, &global, true))
10981 * If there are attentions and they are in a global
10982 * blocks, set the GLOBAL_RESET bit regardless whether
10983 * it will be this function that will complete the
10987 bnx2x_set_reset_global(bp);
10990 * Only the first function on the current engine should
10991 * try to recover in open. In case of attentions in
10992 * global blocks only the first in the chip should try
10995 if ((!load_status &&
10996 (!global || !other_load_status)) &&
10997 bnx2x_trylock_leader_lock(bp) &&
10998 !bnx2x_leader_reset(bp)) {
10999 netdev_info(bp->dev, "Recovered in open\n");
11003 /* recovery has failed... */
11004 bnx2x_set_power_state(bp, PCI_D3hot);
11005 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11007 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11008 "If you still see this message after a few retries then power cycle is required.\n");
11013 bp->recovery_state = BNX2X_RECOVERY_DONE;
11014 return bnx2x_nic_load(bp, LOAD_OPEN);
11017 /* called with rtnl_lock */
11018 static int bnx2x_close(struct net_device *dev)
11020 struct bnx2x *bp = netdev_priv(dev);
11022 /* Unload the driver, release IRQs */
11023 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11026 bnx2x_set_power_state(bp, PCI_D3hot);
11031 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11032 struct bnx2x_mcast_ramrod_params *p)
11034 int mc_count = netdev_mc_count(bp->dev);
11035 struct bnx2x_mcast_list_elem *mc_mac =
11036 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11037 struct netdev_hw_addr *ha;
11042 INIT_LIST_HEAD(&p->mcast_list);
11044 netdev_for_each_mc_addr(ha, bp->dev) {
11045 mc_mac->mac = bnx2x_mc_addr(ha);
11046 list_add_tail(&mc_mac->link, &p->mcast_list);
11050 p->mcast_list_len = mc_count;
11055 static void bnx2x_free_mcast_macs_list(
11056 struct bnx2x_mcast_ramrod_params *p)
11058 struct bnx2x_mcast_list_elem *mc_mac =
11059 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11067 * bnx2x_set_uc_list - configure a new unicast MACs list.
11069 * @bp: driver handle
11071 * We will use zero (0) as a MAC type for these MACs.
11073 static int bnx2x_set_uc_list(struct bnx2x *bp)
11076 struct net_device *dev = bp->dev;
11077 struct netdev_hw_addr *ha;
11078 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11079 unsigned long ramrod_flags = 0;
11081 /* First schedule a cleanup up of old configuration */
11082 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11084 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11088 netdev_for_each_uc_addr(ha, dev) {
11089 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11090 BNX2X_UC_LIST_MAC, &ramrod_flags);
11091 if (rc == -EEXIST) {
11093 "Failed to schedule ADD operations: %d\n", rc);
11094 /* do not treat adding same MAC as error */
11097 } else if (rc < 0) {
11099 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11105 /* Execute the pending commands */
11106 __set_bit(RAMROD_CONT, &ramrod_flags);
11107 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11108 BNX2X_UC_LIST_MAC, &ramrod_flags);
11111 static int bnx2x_set_mc_list(struct bnx2x *bp)
11113 struct net_device *dev = bp->dev;
11114 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11117 rparam.mcast_obj = &bp->mcast_obj;
11119 /* first, clear all configured multicast MACs */
11120 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11122 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11126 /* then, configure a new MACs list */
11127 if (netdev_mc_count(dev)) {
11128 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11130 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11135 /* Now add the new MACs */
11136 rc = bnx2x_config_mcast(bp, &rparam,
11137 BNX2X_MCAST_CMD_ADD);
11139 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11142 bnx2x_free_mcast_macs_list(&rparam);
11149 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11150 void bnx2x_set_rx_mode(struct net_device *dev)
11152 struct bnx2x *bp = netdev_priv(dev);
11153 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11155 if (bp->state != BNX2X_STATE_OPEN) {
11156 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11160 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11162 if (dev->flags & IFF_PROMISC)
11163 rx_mode = BNX2X_RX_MODE_PROMISC;
11164 else if ((dev->flags & IFF_ALLMULTI) ||
11165 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11167 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11169 /* some multicasts */
11170 if (bnx2x_set_mc_list(bp) < 0)
11171 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11173 if (bnx2x_set_uc_list(bp) < 0)
11174 rx_mode = BNX2X_RX_MODE_PROMISC;
11177 bp->rx_mode = rx_mode;
11179 /* handle ISCSI SD mode */
11180 if (IS_MF_ISCSI_SD(bp))
11181 bp->rx_mode = BNX2X_RX_MODE_NONE;
11184 /* Schedule the rx_mode command */
11185 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11186 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11190 bnx2x_set_storm_rx_mode(bp);
11193 /* called with rtnl_lock */
11194 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11195 int devad, u16 addr)
11197 struct bnx2x *bp = netdev_priv(netdev);
11201 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11202 prtad, devad, addr);
11204 /* The HW expects different devad if CL22 is used */
11205 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11207 bnx2x_acquire_phy_lock(bp);
11208 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11209 bnx2x_release_phy_lock(bp);
11210 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11217 /* called with rtnl_lock */
11218 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11219 u16 addr, u16 value)
11221 struct bnx2x *bp = netdev_priv(netdev);
11225 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11226 prtad, devad, addr, value);
11228 /* The HW expects different devad if CL22 is used */
11229 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11231 bnx2x_acquire_phy_lock(bp);
11232 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11233 bnx2x_release_phy_lock(bp);
11237 /* called with rtnl_lock */
11238 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11240 struct bnx2x *bp = netdev_priv(dev);
11241 struct mii_ioctl_data *mdio = if_mii(ifr);
11243 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11244 mdio->phy_id, mdio->reg_num, mdio->val_in);
11246 if (!netif_running(dev))
11249 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11252 #ifdef CONFIG_NET_POLL_CONTROLLER
11253 static void poll_bnx2x(struct net_device *dev)
11255 struct bnx2x *bp = netdev_priv(dev);
11258 for_each_eth_queue(bp, i) {
11259 struct bnx2x_fastpath *fp = &bp->fp[i];
11260 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11265 static int bnx2x_validate_addr(struct net_device *dev)
11267 struct bnx2x *bp = netdev_priv(dev);
11269 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11270 BNX2X_ERR("Non-valid Ethernet address\n");
11271 return -EADDRNOTAVAIL;
11276 static const struct net_device_ops bnx2x_netdev_ops = {
11277 .ndo_open = bnx2x_open,
11278 .ndo_stop = bnx2x_close,
11279 .ndo_start_xmit = bnx2x_start_xmit,
11280 .ndo_select_queue = bnx2x_select_queue,
11281 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11282 .ndo_set_mac_address = bnx2x_change_mac_addr,
11283 .ndo_validate_addr = bnx2x_validate_addr,
11284 .ndo_do_ioctl = bnx2x_ioctl,
11285 .ndo_change_mtu = bnx2x_change_mtu,
11286 .ndo_fix_features = bnx2x_fix_features,
11287 .ndo_set_features = bnx2x_set_features,
11288 .ndo_tx_timeout = bnx2x_tx_timeout,
11289 #ifdef CONFIG_NET_POLL_CONTROLLER
11290 .ndo_poll_controller = poll_bnx2x,
11292 .ndo_setup_tc = bnx2x_setup_tc,
11294 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11295 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11299 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11301 struct device *dev = &bp->pdev->dev;
11303 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11304 bp->flags |= USING_DAC_FLAG;
11305 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11306 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11309 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11310 dev_err(dev, "System does not support DMA, aborting\n");
11317 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11318 struct net_device *dev,
11319 unsigned long board_type)
11324 bool chip_is_e1x = (board_type == BCM57710 ||
11325 board_type == BCM57711 ||
11326 board_type == BCM57711E);
11328 SET_NETDEV_DEV(dev, &pdev->dev);
11329 bp = netdev_priv(dev);
11335 rc = pci_enable_device(pdev);
11337 dev_err(&bp->pdev->dev,
11338 "Cannot enable PCI device, aborting\n");
11342 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11343 dev_err(&bp->pdev->dev,
11344 "Cannot find PCI device base address, aborting\n");
11346 goto err_out_disable;
11349 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11350 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11351 " base address, aborting\n");
11353 goto err_out_disable;
11356 if (atomic_read(&pdev->enable_cnt) == 1) {
11357 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11359 dev_err(&bp->pdev->dev,
11360 "Cannot obtain PCI resources, aborting\n");
11361 goto err_out_disable;
11364 pci_set_master(pdev);
11365 pci_save_state(pdev);
11368 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11369 if (bp->pm_cap == 0) {
11370 dev_err(&bp->pdev->dev,
11371 "Cannot find power management capability, aborting\n");
11373 goto err_out_release;
11376 if (!pci_is_pcie(pdev)) {
11377 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11379 goto err_out_release;
11382 rc = bnx2x_set_coherency_mask(bp);
11384 goto err_out_release;
11386 dev->mem_start = pci_resource_start(pdev, 0);
11387 dev->base_addr = dev->mem_start;
11388 dev->mem_end = pci_resource_end(pdev, 0);
11390 dev->irq = pdev->irq;
11392 bp->regview = pci_ioremap_bar(pdev, 0);
11393 if (!bp->regview) {
11394 dev_err(&bp->pdev->dev,
11395 "Cannot map register space, aborting\n");
11397 goto err_out_release;
11400 /* In E1/E1H use pci device function given by kernel.
11401 * In E2/E3 read physical function from ME register since these chips
11402 * support Physical Device Assignment where kernel BDF maybe arbitrary
11403 * (depending on hypervisor).
11406 bp->pf_num = PCI_FUNC(pdev->devfn);
11407 else {/* chip is E2/3*/
11408 pci_read_config_dword(bp->pdev,
11409 PCICFG_ME_REGISTER, &pci_cfg_dword);
11410 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11411 ME_REG_ABS_PF_NUM_SHIFT);
11413 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11415 bnx2x_set_power_state(bp, PCI_D0);
11417 /* clean indirect addresses */
11418 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11419 PCICFG_VENDOR_ID_OFFSET);
11421 * Clean the following indirect addresses for all functions since it
11422 * is not used by the driver.
11424 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11425 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11426 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11427 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11430 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11431 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11432 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11433 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11437 * Enable internal target-read (in case we are probed after PF FLR).
11438 * Must be done prior to any BAR read access. Only for 57712 and up
11441 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11443 dev->watchdog_timeo = TX_TIMEOUT;
11445 dev->netdev_ops = &bnx2x_netdev_ops;
11446 bnx2x_set_ethtool_ops(dev);
11448 dev->priv_flags |= IFF_UNICAST_FLT;
11450 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11451 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11452 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11453 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11455 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11456 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11458 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11459 if (bp->flags & USING_DAC_FLAG)
11460 dev->features |= NETIF_F_HIGHDMA;
11462 /* Add Loopback capability to the device */
11463 dev->hw_features |= NETIF_F_LOOPBACK;
11466 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11469 /* get_port_hwinfo() will set prtad and mmds properly */
11470 bp->mdio.prtad = MDIO_PRTAD_NONE;
11472 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11473 bp->mdio.dev = dev;
11474 bp->mdio.mdio_read = bnx2x_mdio_read;
11475 bp->mdio.mdio_write = bnx2x_mdio_write;
11480 if (atomic_read(&pdev->enable_cnt) == 1)
11481 pci_release_regions(pdev);
11484 pci_disable_device(pdev);
11485 pci_set_drvdata(pdev, NULL);
11491 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11492 int *width, int *speed)
11494 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11496 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11498 /* return value of 1=2.5GHz 2=5GHz */
11499 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11502 static int bnx2x_check_firmware(struct bnx2x *bp)
11504 const struct firmware *firmware = bp->firmware;
11505 struct bnx2x_fw_file_hdr *fw_hdr;
11506 struct bnx2x_fw_file_section *sections;
11507 u32 offset, len, num_ops;
11512 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11513 BNX2X_ERR("Wrong FW size\n");
11517 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11518 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11520 /* Make sure none of the offsets and sizes make us read beyond
11521 * the end of the firmware data */
11522 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11523 offset = be32_to_cpu(sections[i].offset);
11524 len = be32_to_cpu(sections[i].len);
11525 if (offset + len > firmware->size) {
11526 BNX2X_ERR("Section %d length is out of bounds\n", i);
11531 /* Likewise for the init_ops offsets */
11532 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11533 ops_offsets = (u16 *)(firmware->data + offset);
11534 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11536 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11537 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11538 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11543 /* Check FW version */
11544 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11545 fw_ver = firmware->data + offset;
11546 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11547 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11548 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11549 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11550 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11551 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11552 BCM_5710_FW_MAJOR_VERSION,
11553 BCM_5710_FW_MINOR_VERSION,
11554 BCM_5710_FW_REVISION_VERSION,
11555 BCM_5710_FW_ENGINEERING_VERSION);
11562 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11564 const __be32 *source = (const __be32 *)_source;
11565 u32 *target = (u32 *)_target;
11568 for (i = 0; i < n/4; i++)
11569 target[i] = be32_to_cpu(source[i]);
11573 Ops array is stored in the following format:
11574 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11576 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11578 const __be32 *source = (const __be32 *)_source;
11579 struct raw_op *target = (struct raw_op *)_target;
11582 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11583 tmp = be32_to_cpu(source[j]);
11584 target[i].op = (tmp >> 24) & 0xff;
11585 target[i].offset = tmp & 0xffffff;
11586 target[i].raw_data = be32_to_cpu(source[j + 1]);
11590 /* IRO array is stored in the following format:
11591 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11593 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11595 const __be32 *source = (const __be32 *)_source;
11596 struct iro *target = (struct iro *)_target;
11599 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11600 target[i].base = be32_to_cpu(source[j]);
11602 tmp = be32_to_cpu(source[j]);
11603 target[i].m1 = (tmp >> 16) & 0xffff;
11604 target[i].m2 = tmp & 0xffff;
11606 tmp = be32_to_cpu(source[j]);
11607 target[i].m3 = (tmp >> 16) & 0xffff;
11608 target[i].size = tmp & 0xffff;
11613 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11615 const __be16 *source = (const __be16 *)_source;
11616 u16 *target = (u16 *)_target;
11619 for (i = 0; i < n/2; i++)
11620 target[i] = be16_to_cpu(source[i]);
11623 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11625 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11626 bp->arr = kmalloc(len, GFP_KERNEL); \
11629 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11630 (u8 *)bp->arr, len); \
11633 static int bnx2x_init_firmware(struct bnx2x *bp)
11635 const char *fw_file_name;
11636 struct bnx2x_fw_file_hdr *fw_hdr;
11642 if (CHIP_IS_E1(bp))
11643 fw_file_name = FW_FILE_NAME_E1;
11644 else if (CHIP_IS_E1H(bp))
11645 fw_file_name = FW_FILE_NAME_E1H;
11646 else if (!CHIP_IS_E1x(bp))
11647 fw_file_name = FW_FILE_NAME_E2;
11649 BNX2X_ERR("Unsupported chip revision\n");
11652 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11654 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11656 BNX2X_ERR("Can't load firmware file %s\n",
11658 goto request_firmware_exit;
11661 rc = bnx2x_check_firmware(bp);
11663 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11664 goto request_firmware_exit;
11667 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11669 /* Initialize the pointers to the init arrays */
11671 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11674 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11677 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11680 /* STORMs firmware */
11681 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11682 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11683 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11684 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11685 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11686 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11687 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11688 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11689 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11690 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11691 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11692 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11693 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11694 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11695 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11696 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11698 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11703 kfree(bp->init_ops_offsets);
11704 init_offsets_alloc_err:
11705 kfree(bp->init_ops);
11706 init_ops_alloc_err:
11707 kfree(bp->init_data);
11708 request_firmware_exit:
11709 release_firmware(bp->firmware);
11710 bp->firmware = NULL;
11715 static void bnx2x_release_firmware(struct bnx2x *bp)
11717 kfree(bp->init_ops_offsets);
11718 kfree(bp->init_ops);
11719 kfree(bp->init_data);
11720 release_firmware(bp->firmware);
11721 bp->firmware = NULL;
11725 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11726 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11727 .init_hw_cmn = bnx2x_init_hw_common,
11728 .init_hw_port = bnx2x_init_hw_port,
11729 .init_hw_func = bnx2x_init_hw_func,
11731 .reset_hw_cmn = bnx2x_reset_common,
11732 .reset_hw_port = bnx2x_reset_port,
11733 .reset_hw_func = bnx2x_reset_func,
11735 .gunzip_init = bnx2x_gunzip_init,
11736 .gunzip_end = bnx2x_gunzip_end,
11738 .init_fw = bnx2x_init_firmware,
11739 .release_fw = bnx2x_release_firmware,
11742 void bnx2x__init_func_obj(struct bnx2x *bp)
11744 /* Prepare DMAE related driver resources */
11745 bnx2x_setup_dmae(bp);
11747 bnx2x_init_func_obj(bp, &bp->func_obj,
11748 bnx2x_sp(bp, func_rdata),
11749 bnx2x_sp_mapping(bp, func_rdata),
11750 bnx2x_sp(bp, func_afex_rdata),
11751 bnx2x_sp_mapping(bp, func_afex_rdata),
11752 &bnx2x_func_sp_drv);
11755 /* must be called after sriov-enable */
11756 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11758 int cid_count = BNX2X_L2_MAX_CID(bp);
11761 cid_count += CNIC_CID_MAX;
11763 return roundup(cid_count, QM_CID_ROUND);
11767 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11772 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11777 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11780 * If MSI-X is not supported - return number of SBs needed to support
11781 * one fast path queue: one FP queue + SB for CNIC
11784 return 1 + CNIC_PRESENT;
11787 * The value in the PCI configuration space is the index of the last
11788 * entry, namely one less than the actual size of the table, which is
11789 * exactly what we want to return from this function: number of all SBs
11790 * without the default SB.
11792 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11793 return control & PCI_MSIX_FLAGS_QSIZE;
11796 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11797 const struct pci_device_id *ent)
11799 struct net_device *dev = NULL;
11801 int pcie_width, pcie_speed;
11802 int rc, max_non_def_sbs;
11803 int rx_count, tx_count, rss_count, doorbell_size;
11805 * An estimated maximum supported CoS number according to the chip
11807 * We will try to roughly estimate the maximum number of CoSes this chip
11808 * may support in order to minimize the memory allocated for Tx
11809 * netdev_queue's. This number will be accurately calculated during the
11810 * initialization of bp->max_cos based on the chip versions AND chip
11811 * revision in the bnx2x_init_bp().
11813 u8 max_cos_est = 0;
11815 switch (ent->driver_data) {
11819 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11824 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11832 case BCM57840_4_10:
11833 case BCM57840_2_20:
11838 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11842 pr_err("Unknown board_type (%ld), aborting\n",
11847 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11849 WARN_ON(!max_non_def_sbs);
11851 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11852 rss_count = max_non_def_sbs - CNIC_PRESENT;
11854 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11855 rx_count = rss_count + FCOE_PRESENT;
11858 * Maximum number of netdev Tx queues:
11859 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11861 tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11863 /* dev zeroed in init_etherdev */
11864 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11868 bp = netdev_priv(dev);
11870 bp->igu_sb_cnt = max_non_def_sbs;
11871 bp->msg_enable = debug;
11872 pci_set_drvdata(pdev, dev);
11874 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11880 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11882 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11883 tx_count, rx_count);
11885 rc = bnx2x_init_bp(bp);
11887 goto init_one_exit;
11890 * Map doorbels here as we need the real value of bp->max_cos which
11891 * is initialized in bnx2x_init_bp().
11893 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11894 if (doorbell_size > pci_resource_len(pdev, 2)) {
11895 dev_err(&bp->pdev->dev,
11896 "Cannot map doorbells, bar size too small, aborting\n");
11898 goto init_one_exit;
11900 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11902 if (!bp->doorbells) {
11903 dev_err(&bp->pdev->dev,
11904 "Cannot map doorbell space, aborting\n");
11906 goto init_one_exit;
11909 /* calc qm_cid_count */
11910 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11913 /* disable FCOE L2 queue for E1x */
11914 if (CHIP_IS_E1x(bp))
11915 bp->flags |= NO_FCOE_FLAG;
11920 /* Set bp->num_queues for MSI-X mode*/
11921 bnx2x_set_num_queues(bp);
11923 /* Configure interrupt mode: try to enable MSI-X/MSI if
11926 bnx2x_set_int_mode(bp);
11928 rc = register_netdev(dev);
11930 dev_err(&pdev->dev, "Cannot register net device\n");
11931 goto init_one_exit;
11935 if (!NO_FCOE(bp)) {
11936 /* Add storage MAC address */
11938 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11943 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11946 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11947 board_info[ent->driver_data].name,
11948 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11950 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11951 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11952 "5GHz (Gen2)" : "2.5GHz",
11953 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11959 iounmap(bp->regview);
11962 iounmap(bp->doorbells);
11966 if (atomic_read(&pdev->enable_cnt) == 1)
11967 pci_release_regions(pdev);
11969 pci_disable_device(pdev);
11970 pci_set_drvdata(pdev, NULL);
11975 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11977 struct net_device *dev = pci_get_drvdata(pdev);
11981 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11984 bp = netdev_priv(dev);
11987 /* Delete storage MAC address */
11988 if (!NO_FCOE(bp)) {
11990 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11996 /* Delete app tlvs from dcbnl */
11997 bnx2x_dcbnl_update_applist(bp, true);
12000 unregister_netdev(dev);
12002 /* Power on: we can't let PCI layer write to us while we are in D3 */
12003 bnx2x_set_power_state(bp, PCI_D0);
12005 /* Disable MSI/MSI-X */
12006 bnx2x_disable_msi(bp);
12009 bnx2x_set_power_state(bp, PCI_D3hot);
12011 /* Make sure RESET task is not scheduled before continuing */
12012 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12015 iounmap(bp->regview);
12018 iounmap(bp->doorbells);
12020 bnx2x_release_firmware(bp);
12022 bnx2x_free_mem_bp(bp);
12026 if (atomic_read(&pdev->enable_cnt) == 1)
12027 pci_release_regions(pdev);
12029 pci_disable_device(pdev);
12030 pci_set_drvdata(pdev, NULL);
12033 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12037 bp->state = BNX2X_STATE_ERROR;
12039 bp->rx_mode = BNX2X_RX_MODE_NONE;
12042 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12045 bnx2x_tx_disable(bp);
12047 bnx2x_netif_stop(bp, 0);
12048 /* Delete all NAPI objects */
12049 bnx2x_del_all_napi(bp);
12051 del_timer_sync(&bp->timer);
12053 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12056 bnx2x_free_irq(bp);
12058 /* Free SKBs, SGEs, TPA pool and driver internals */
12059 bnx2x_free_skbs(bp);
12061 for_each_rx_queue(bp, i)
12062 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12064 bnx2x_free_mem(bp);
12066 bp->state = BNX2X_STATE_CLOSED;
12068 netif_carrier_off(bp->dev);
12073 static void bnx2x_eeh_recover(struct bnx2x *bp)
12077 mutex_init(&bp->port.phy_mutex);
12080 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12081 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12082 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12083 BNX2X_ERR("BAD MCP validity signature\n");
12087 * bnx2x_io_error_detected - called when PCI error is detected
12088 * @pdev: Pointer to PCI device
12089 * @state: The current pci connection state
12091 * This function is called after a PCI bus error affecting
12092 * this device has been detected.
12094 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12095 pci_channel_state_t state)
12097 struct net_device *dev = pci_get_drvdata(pdev);
12098 struct bnx2x *bp = netdev_priv(dev);
12102 netif_device_detach(dev);
12104 if (state == pci_channel_io_perm_failure) {
12106 return PCI_ERS_RESULT_DISCONNECT;
12109 if (netif_running(dev))
12110 bnx2x_eeh_nic_unload(bp);
12112 pci_disable_device(pdev);
12116 /* Request a slot reset */
12117 return PCI_ERS_RESULT_NEED_RESET;
12121 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12122 * @pdev: Pointer to PCI device
12124 * Restart the card from scratch, as if from a cold-boot.
12126 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12128 struct net_device *dev = pci_get_drvdata(pdev);
12129 struct bnx2x *bp = netdev_priv(dev);
12133 if (pci_enable_device(pdev)) {
12134 dev_err(&pdev->dev,
12135 "Cannot re-enable PCI device after reset\n");
12137 return PCI_ERS_RESULT_DISCONNECT;
12140 pci_set_master(pdev);
12141 pci_restore_state(pdev);
12143 if (netif_running(dev))
12144 bnx2x_set_power_state(bp, PCI_D0);
12148 return PCI_ERS_RESULT_RECOVERED;
12152 * bnx2x_io_resume - called when traffic can start flowing again
12153 * @pdev: Pointer to PCI device
12155 * This callback is called when the error recovery driver tells us that
12156 * its OK to resume normal operation.
12158 static void bnx2x_io_resume(struct pci_dev *pdev)
12160 struct net_device *dev = pci_get_drvdata(pdev);
12161 struct bnx2x *bp = netdev_priv(dev);
12163 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12164 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12170 bnx2x_eeh_recover(bp);
12172 if (netif_running(dev))
12173 bnx2x_nic_load(bp, LOAD_NORMAL);
12175 netif_device_attach(dev);
12180 static struct pci_error_handlers bnx2x_err_handler = {
12181 .error_detected = bnx2x_io_error_detected,
12182 .slot_reset = bnx2x_io_slot_reset,
12183 .resume = bnx2x_io_resume,
12186 static struct pci_driver bnx2x_pci_driver = {
12187 .name = DRV_MODULE_NAME,
12188 .id_table = bnx2x_pci_tbl,
12189 .probe = bnx2x_init_one,
12190 .remove = __devexit_p(bnx2x_remove_one),
12191 .suspend = bnx2x_suspend,
12192 .resume = bnx2x_resume,
12193 .err_handler = &bnx2x_err_handler,
12196 static int __init bnx2x_init(void)
12200 pr_info("%s", version);
12202 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12203 if (bnx2x_wq == NULL) {
12204 pr_err("Cannot create workqueue\n");
12208 ret = pci_register_driver(&bnx2x_pci_driver);
12210 pr_err("Cannot register driver\n");
12211 destroy_workqueue(bnx2x_wq);
12216 static void __exit bnx2x_cleanup(void)
12218 struct list_head *pos, *q;
12219 pci_unregister_driver(&bnx2x_pci_driver);
12221 destroy_workqueue(bnx2x_wq);
12223 /* Free globablly allocated resources */
12224 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12225 struct bnx2x_prev_path_list *tmp =
12226 list_entry(pos, struct bnx2x_prev_path_list, list);
12232 void bnx2x_notify_link_changed(struct bnx2x *bp)
12234 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12237 module_init(bnx2x_init);
12238 module_exit(bnx2x_cleanup);
12242 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12244 * @bp: driver handle
12245 * @set: set or clear the CAM entry
12247 * This function will wait until the ramdord completion returns.
12248 * Return 0 if success, -ENODEV if ramrod doesn't return.
12250 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12252 unsigned long ramrod_flags = 0;
12254 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12255 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12256 &bp->iscsi_l2_mac_obj, true,
12257 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12260 /* count denotes the number of new completions we have seen */
12261 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12263 struct eth_spe *spe;
12264 int cxt_index, cxt_offset;
12266 #ifdef BNX2X_STOP_ON_ERROR
12267 if (unlikely(bp->panic))
12271 spin_lock_bh(&bp->spq_lock);
12272 BUG_ON(bp->cnic_spq_pending < count);
12273 bp->cnic_spq_pending -= count;
12276 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12277 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12278 & SPE_HDR_CONN_TYPE) >>
12279 SPE_HDR_CONN_TYPE_SHIFT;
12280 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12281 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12283 /* Set validation for iSCSI L2 client before sending SETUP
12286 if (type == ETH_CONNECTION_TYPE) {
12287 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12288 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12290 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12291 (cxt_index * ILT_PAGE_CIDS);
12292 bnx2x_set_ctx_validation(bp,
12293 &bp->context[cxt_index].
12294 vcxt[cxt_offset].eth,
12295 BNX2X_ISCSI_ETH_CID(bp));
12300 * There may be not more than 8 L2, not more than 8 L5 SPEs
12301 * and in the air. We also check that number of outstanding
12302 * COMMON ramrods is not more than the EQ and SPQ can
12305 if (type == ETH_CONNECTION_TYPE) {
12306 if (!atomic_read(&bp->cq_spq_left))
12309 atomic_dec(&bp->cq_spq_left);
12310 } else if (type == NONE_CONNECTION_TYPE) {
12311 if (!atomic_read(&bp->eq_spq_left))
12314 atomic_dec(&bp->eq_spq_left);
12315 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12316 (type == FCOE_CONNECTION_TYPE)) {
12317 if (bp->cnic_spq_pending >=
12318 bp->cnic_eth_dev.max_kwqe_pending)
12321 bp->cnic_spq_pending++;
12323 BNX2X_ERR("Unknown SPE type: %d\n", type);
12328 spe = bnx2x_sp_get_next(bp);
12329 *spe = *bp->cnic_kwq_cons;
12331 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12332 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12334 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12335 bp->cnic_kwq_cons = bp->cnic_kwq;
12337 bp->cnic_kwq_cons++;
12339 bnx2x_sp_prod_update(bp);
12340 spin_unlock_bh(&bp->spq_lock);
12343 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12344 struct kwqe_16 *kwqes[], u32 count)
12346 struct bnx2x *bp = netdev_priv(dev);
12349 #ifdef BNX2X_STOP_ON_ERROR
12350 if (unlikely(bp->panic)) {
12351 BNX2X_ERR("Can't post to SP queue while panic\n");
12356 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12357 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12358 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12362 spin_lock_bh(&bp->spq_lock);
12364 for (i = 0; i < count; i++) {
12365 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12367 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12370 *bp->cnic_kwq_prod = *spe;
12372 bp->cnic_kwq_pending++;
12374 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12375 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12376 spe->data.update_data_addr.hi,
12377 spe->data.update_data_addr.lo,
12378 bp->cnic_kwq_pending);
12380 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12381 bp->cnic_kwq_prod = bp->cnic_kwq;
12383 bp->cnic_kwq_prod++;
12386 spin_unlock_bh(&bp->spq_lock);
12388 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12389 bnx2x_cnic_sp_post(bp, 0);
12394 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12396 struct cnic_ops *c_ops;
12399 mutex_lock(&bp->cnic_mutex);
12400 c_ops = rcu_dereference_protected(bp->cnic_ops,
12401 lockdep_is_held(&bp->cnic_mutex));
12403 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12404 mutex_unlock(&bp->cnic_mutex);
12409 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12411 struct cnic_ops *c_ops;
12415 c_ops = rcu_dereference(bp->cnic_ops);
12417 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12424 * for commands that have no data
12426 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12428 struct cnic_ctl_info ctl = {0};
12432 return bnx2x_cnic_ctl_send(bp, &ctl);
12435 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12437 struct cnic_ctl_info ctl = {0};
12439 /* first we tell CNIC and only then we count this as a completion */
12440 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12441 ctl.data.comp.cid = cid;
12442 ctl.data.comp.error = err;
12444 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12445 bnx2x_cnic_sp_post(bp, 0);
12449 /* Called with netif_addr_lock_bh() taken.
12450 * Sets an rx_mode config for an iSCSI ETH client.
12452 * Completion should be checked outside.
12454 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12456 unsigned long accept_flags = 0, ramrod_flags = 0;
12457 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12458 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12461 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12462 * because it's the only way for UIO Queue to accept
12463 * multicasts (in non-promiscuous mode only one Queue per
12464 * function will receive multicast packets (leading in our
12467 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12468 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12469 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12470 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12472 /* Clear STOP_PENDING bit if START is requested */
12473 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12475 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12477 /* Clear START_PENDING bit if STOP is requested */
12478 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12480 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12481 set_bit(sched_state, &bp->sp_state);
12483 __set_bit(RAMROD_RX, &ramrod_flags);
12484 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12490 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12492 struct bnx2x *bp = netdev_priv(dev);
12495 switch (ctl->cmd) {
12496 case DRV_CTL_CTXTBL_WR_CMD: {
12497 u32 index = ctl->data.io.offset;
12498 dma_addr_t addr = ctl->data.io.dma_addr;
12500 bnx2x_ilt_wr(bp, index, addr);
12504 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12505 int count = ctl->data.credit.credit_count;
12507 bnx2x_cnic_sp_post(bp, count);
12511 /* rtnl_lock is held. */
12512 case DRV_CTL_START_L2_CMD: {
12513 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12514 unsigned long sp_bits = 0;
12516 /* Configure the iSCSI classification object */
12517 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12518 cp->iscsi_l2_client_id,
12519 cp->iscsi_l2_cid, BP_FUNC(bp),
12520 bnx2x_sp(bp, mac_rdata),
12521 bnx2x_sp_mapping(bp, mac_rdata),
12522 BNX2X_FILTER_MAC_PENDING,
12523 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12526 /* Set iSCSI MAC address */
12527 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12534 /* Start accepting on iSCSI L2 ring */
12536 netif_addr_lock_bh(dev);
12537 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12538 netif_addr_unlock_bh(dev);
12540 /* bits to wait on */
12541 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12542 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12544 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12545 BNX2X_ERR("rx_mode completion timed out!\n");
12550 /* rtnl_lock is held. */
12551 case DRV_CTL_STOP_L2_CMD: {
12552 unsigned long sp_bits = 0;
12554 /* Stop accepting on iSCSI L2 ring */
12555 netif_addr_lock_bh(dev);
12556 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12557 netif_addr_unlock_bh(dev);
12559 /* bits to wait on */
12560 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12561 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12563 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12564 BNX2X_ERR("rx_mode completion timed out!\n");
12569 /* Unset iSCSI L2 MAC */
12570 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12571 BNX2X_ISCSI_ETH_MAC, true);
12574 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12575 int count = ctl->data.credit.credit_count;
12577 smp_mb__before_atomic_inc();
12578 atomic_add(count, &bp->cq_spq_left);
12579 smp_mb__after_atomic_inc();
12582 case DRV_CTL_ULP_REGISTER_CMD: {
12583 int ulp_type = ctl->data.register_data.ulp_type;
12585 if (CHIP_IS_E3(bp)) {
12586 int idx = BP_FW_MB_IDX(bp);
12587 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12588 int path = BP_PATH(bp);
12589 int port = BP_PORT(bp);
12591 u32 scratch_offset;
12594 /* first write capability to shmem2 */
12595 if (ulp_type == CNIC_ULP_ISCSI)
12596 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12597 else if (ulp_type == CNIC_ULP_FCOE)
12598 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12599 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12601 if ((ulp_type != CNIC_ULP_FCOE) ||
12602 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12603 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12606 /* if reached here - should write fcoe capabilities */
12607 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12608 if (!scratch_offset)
12610 scratch_offset += offsetof(struct glob_ncsi_oem_data,
12611 fcoe_features[path][port]);
12612 host_addr = (u32 *) &(ctl->data.register_data.
12614 for (i = 0; i < sizeof(struct fcoe_capabilities);
12616 REG_WR(bp, scratch_offset + i,
12617 *(host_addr + i/4));
12622 case DRV_CTL_ULP_UNREGISTER_CMD: {
12623 int ulp_type = ctl->data.ulp_type;
12625 if (CHIP_IS_E3(bp)) {
12626 int idx = BP_FW_MB_IDX(bp);
12629 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12630 if (ulp_type == CNIC_ULP_ISCSI)
12631 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12632 else if (ulp_type == CNIC_ULP_FCOE)
12633 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12634 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12640 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12647 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12649 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12651 if (bp->flags & USING_MSIX_FLAG) {
12652 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12653 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12654 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12656 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12657 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12659 if (!CHIP_IS_E1x(bp))
12660 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12662 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12664 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12665 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12666 cp->irq_arr[1].status_blk = bp->def_status_blk;
12667 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12668 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12673 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12675 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12678 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12679 bnx2x_cid_ilt_lines(bp);
12680 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12681 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12682 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12684 if (NO_ISCSI_OOO(bp))
12685 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12688 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12691 struct bnx2x *bp = netdev_priv(dev);
12692 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12695 BNX2X_ERR("NULL ops received\n");
12699 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12703 bp->cnic_kwq_cons = bp->cnic_kwq;
12704 bp->cnic_kwq_prod = bp->cnic_kwq;
12705 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12707 bp->cnic_spq_pending = 0;
12708 bp->cnic_kwq_pending = 0;
12710 bp->cnic_data = data;
12713 cp->drv_state |= CNIC_DRV_STATE_REGD;
12714 cp->iro_arr = bp->iro_arr;
12716 bnx2x_setup_cnic_irq_info(bp);
12718 rcu_assign_pointer(bp->cnic_ops, ops);
12723 static int bnx2x_unregister_cnic(struct net_device *dev)
12725 struct bnx2x *bp = netdev_priv(dev);
12726 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12728 mutex_lock(&bp->cnic_mutex);
12730 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12731 mutex_unlock(&bp->cnic_mutex);
12733 kfree(bp->cnic_kwq);
12734 bp->cnic_kwq = NULL;
12739 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12741 struct bnx2x *bp = netdev_priv(dev);
12742 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12744 /* If both iSCSI and FCoE are disabled - return NULL in
12745 * order to indicate CNIC that it should not try to work
12746 * with this device.
12748 if (NO_ISCSI(bp) && NO_FCOE(bp))
12751 cp->drv_owner = THIS_MODULE;
12752 cp->chip_id = CHIP_ID(bp);
12753 cp->pdev = bp->pdev;
12754 cp->io_base = bp->regview;
12755 cp->io_base2 = bp->doorbells;
12756 cp->max_kwqe_pending = 8;
12757 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12758 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12759 bnx2x_cid_ilt_lines(bp);
12760 cp->ctx_tbl_len = CNIC_ILT_LINES;
12761 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12762 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12763 cp->drv_ctl = bnx2x_drv_ctl;
12764 cp->drv_register_cnic = bnx2x_register_cnic;
12765 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12766 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12767 cp->iscsi_l2_client_id =
12768 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12769 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12771 if (NO_ISCSI_OOO(bp))
12772 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12775 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12778 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12781 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12783 cp->ctx_tbl_offset,
12788 EXPORT_SYMBOL(bnx2x_cnic_probe);
12790 #endif /* BCM_CNIC */