drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c

   1 /* bnx2x_main.c: Broadcom Everest network driver.
   2  *
   3  * Copyright (c) 2007-2013 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
  10  * Written by: Eliezer Tamir
  11  * Based on code from Michael Chan's bnx2 driver
  12  * UDP CSUM errata workaround by Arik Gendelman
  13  * Slowpath and fastpath rework by Vladislav Zolotarov
  14  * Statistics and Link management by Yitchak Gertner
  15  *
  16  */
  17
  18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/device.h>  /* for dev_info() */
  24 #include <linux/timer.h>
  25 #include <linux/errno.h>
  26 #include <linux/ioport.h>
  27 #include <linux/slab.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/pci.h>
  30 #include <linux/aer.h>
  31 #include <linux/init.h>
  32 #include <linux/netdevice.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/bitops.h>
  37 #include <linux/irq.h>
  38 #include <linux/delay.h>
  39 #include <asm/byteorder.h>
  40 #include <linux/time.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/mii.h>
  43 #include <linux/if_vlan.h>
  44 #include <net/ip.h>
  45 #include <net/ipv6.h>
  46 #include <net/tcp.h>
  47 #include <net/checksum.h>
  48 #include <net/ip6_checksum.h>
  49 #include <linux/workqueue.h>
  50 #include <linux/crc32.h>
  51 #include <linux/crc32c.h>
  52 #include <linux/prefetch.h>
  53 #include <linux/zlib.h>
  54 #include <linux/io.h>
  55 #include <linux/semaphore.h>
  56 #include <linux/stringify.h>
  57 #include <linux/vmalloc.h>
  58
  59 #include "bnx2x.h"
  60 #include "bnx2x_init.h"
  61 #include "bnx2x_init_ops.h"
  62 #include "bnx2x_cmn.h"
  63 #include "bnx2x_vfpf.h"
  64 #include "bnx2x_dcb.h"
  65 #include "bnx2x_sp.h"
  66 #include <linux/firmware.h>
  67 #include "bnx2x_fw_file_hdr.h"
  68 /* FW files */
  69 #define FW_FILE_VERSION                                 \
  70         __stringify(BCM_5710_FW_MAJOR_VERSION) "."      \
  71         __stringify(BCM_5710_FW_MINOR_VERSION) "."      \
  72         __stringify(BCM_5710_FW_REVISION_VERSION) "."   \
  73         __stringify(BCM_5710_FW_ENGINEERING_VERSION)
  74 #define FW_FILE_NAME_E1         "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
  75 #define FW_FILE_NAME_E1H        "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
  76 #define FW_FILE_NAME_E2         "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
  77
  78 /* Time in jiffies before concluding the transmitter is hung */
  79 #define TX_TIMEOUT              (5*HZ)
  80
  81 static char version[] =
  82         "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
  83         DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  84
  85 MODULE_AUTHOR("Eliezer Tamir");
  86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
  87                    "BCM57710/57711/57711E/"
  88                    "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
  89                    "57840/57840_MF Driver");
  90 MODULE_LICENSE("GPL");
  91 MODULE_VERSION(DRV_MODULE_VERSION);
  92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
  93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
  94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
  95
  96 int bnx2x_num_queues;
  97 module_param_named(num_queues, bnx2x_num_queues, int, S_IRUGO);
  98 MODULE_PARM_DESC(num_queues,
  99                  " Set number of queues (default is as a number of CPUs)");
 100
 101 static int disable_tpa;
 102 module_param(disable_tpa, int, S_IRUGO);
 103 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
 104
 105 static int int_mode;
 106 module_param(int_mode, int, S_IRUGO);
 107 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
 108                                 "(1 INT#x; 2 MSI)");
 109
 110 static int dropless_fc;
 111 module_param(dropless_fc, int, S_IRUGO);
 112 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
 113
 114 static int mrrs = -1;
 115 module_param(mrrs, int, S_IRUGO);
 116 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
 117
 118 static int debug;
 119 module_param(debug, int, S_IRUGO);
 120 MODULE_PARM_DESC(debug, " Default debug msglevel");
 121
 122 static struct workqueue_struct *bnx2x_wq;
 123 struct workqueue_struct *bnx2x_iov_wq;
 124
 125 struct bnx2x_mac_vals {
 126         u32 xmac_addr;
 127         u32 xmac_val;
 128         u32 emac_addr;
 129         u32 emac_val;
 130         u32 umac_addr;
 131         u32 umac_val;
 132         u32 bmac_addr;
 133         u32 bmac_val[2];
 134 };
 135
 136 enum bnx2x_board_type {
 137         BCM57710 = 0,
 138         BCM57711,
 139         BCM57711E,
 140         BCM57712,
 141         BCM57712_MF,
 142         BCM57712_VF,
 143         BCM57800,
 144         BCM57800_MF,
 145         BCM57800_VF,
 146         BCM57810,
 147         BCM57810_MF,
 148         BCM57810_VF,
 149         BCM57840_4_10,
 150         BCM57840_2_20,
 151         BCM57840_MF,
 152         BCM57840_VF,
 153         BCM57811,
 154         BCM57811_MF,
 155         BCM57840_O,
 156         BCM57840_MFO,
 157         BCM57811_VF
 158 };
 159
 160 /* indexed by board_type, above */
 161 static struct {
 162         char *name;
 163 } board_info[] = {
 164         [BCM57710]      = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
 165         [BCM57711]      = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
 166         [BCM57711E]     = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
 167         [BCM57712]      = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
 168         [BCM57712_MF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
 169         [BCM57712_VF]   = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
 170         [BCM57800]      = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
 171         [BCM57800_MF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
 172         [BCM57800_VF]   = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
 173         [BCM57810]      = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
 174         [BCM57810_MF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
 175         [BCM57810_VF]   = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
 176         [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
 177         [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
 178         [BCM57840_MF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 179         [BCM57840_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
 180         [BCM57811]      = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
 181         [BCM57811_MF]   = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
 182         [BCM57840_O]    = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
 183         [BCM57840_MFO]  = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
 184         [BCM57811_VF]   = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
 185 };
 186
 187 #ifndef PCI_DEVICE_ID_NX2_57710
 188 #define PCI_DEVICE_ID_NX2_57710         CHIP_NUM_57710
 189 #endif
 190 #ifndef PCI_DEVICE_ID_NX2_57711
 191 #define PCI_DEVICE_ID_NX2_57711         CHIP_NUM_57711
 192 #endif
 193 #ifndef PCI_DEVICE_ID_NX2_57711E
 194 #define PCI_DEVICE_ID_NX2_57711E        CHIP_NUM_57711E
 195 #endif
 196 #ifndef PCI_DEVICE_ID_NX2_57712
 197 #define PCI_DEVICE_ID_NX2_57712         CHIP_NUM_57712
 198 #endif
 199 #ifndef PCI_DEVICE_ID_NX2_57712_MF
 200 #define PCI_DEVICE_ID_NX2_57712_MF      CHIP_NUM_57712_MF
 201 #endif
 202 #ifndef PCI_DEVICE_ID_NX2_57712_VF
 203 #define PCI_DEVICE_ID_NX2_57712_VF      CHIP_NUM_57712_VF
 204 #endif
 205 #ifndef PCI_DEVICE_ID_NX2_57800
 206 #define PCI_DEVICE_ID_NX2_57800         CHIP_NUM_57800
 207 #endif
 208 #ifndef PCI_DEVICE_ID_NX2_57800_MF
 209 #define PCI_DEVICE_ID_NX2_57800_MF      CHIP_NUM_57800_MF
 210 #endif
 211 #ifndef PCI_DEVICE_ID_NX2_57800_VF
 212 #define PCI_DEVICE_ID_NX2_57800_VF      CHIP_NUM_57800_VF
 213 #endif
 214 #ifndef PCI_DEVICE_ID_NX2_57810
 215 #define PCI_DEVICE_ID_NX2_57810         CHIP_NUM_57810
 216 #endif
 217 #ifndef PCI_DEVICE_ID_NX2_57810_MF
 218 #define PCI_DEVICE_ID_NX2_57810_MF      CHIP_NUM_57810_MF
 219 #endif
 220 #ifndef PCI_DEVICE_ID_NX2_57840_O
 221 #define PCI_DEVICE_ID_NX2_57840_O       CHIP_NUM_57840_OBSOLETE
 222 #endif
 223 #ifndef PCI_DEVICE_ID_NX2_57810_VF
 224 #define PCI_DEVICE_ID_NX2_57810_VF      CHIP_NUM_57810_VF
 225 #endif
 226 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
 227 #define PCI_DEVICE_ID_NX2_57840_4_10    CHIP_NUM_57840_4_10
 228 #endif
 229 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
 230 #define PCI_DEVICE_ID_NX2_57840_2_20    CHIP_NUM_57840_2_20
 231 #endif
 232 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
 233 #define PCI_DEVICE_ID_NX2_57840_MFO     CHIP_NUM_57840_MF_OBSOLETE
 234 #endif
 235 #ifndef PCI_DEVICE_ID_NX2_57840_MF
 236 #define PCI_DEVICE_ID_NX2_57840_MF      CHIP_NUM_57840_MF
 237 #endif
 238 #ifndef PCI_DEVICE_ID_NX2_57840_VF
 239 #define PCI_DEVICE_ID_NX2_57840_VF      CHIP_NUM_57840_VF
 240 #endif
 241 #ifndef PCI_DEVICE_ID_NX2_57811
 242 #define PCI_DEVICE_ID_NX2_57811         CHIP_NUM_57811
 243 #endif
 244 #ifndef PCI_DEVICE_ID_NX2_57811_MF
 245 #define PCI_DEVICE_ID_NX2_57811_MF      CHIP_NUM_57811_MF
 246 #endif
 247 #ifndef PCI_DEVICE_ID_NX2_57811_VF
 248 #define PCI_DEVICE_ID_NX2_57811_VF      CHIP_NUM_57811_VF
 249 #endif
 250
 251 static const struct pci_device_id bnx2x_pci_tbl[] = {
 252         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
 253         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
 254         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
 255         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
 256         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
 257         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
 258         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
 259         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
 260         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
 261         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
 262         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
 263         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
 264         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
 265         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
 266         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
 267         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
 268         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
 269         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
 270         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
 271         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
 272         { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
 273         { 0 }
 274 };
 275
 276 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
 277
 278 /* Global resources for unloading a previously loaded device */
 279 #define BNX2X_PREV_WAIT_NEEDED 1
 280 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
 281 static LIST_HEAD(bnx2x_prev_list);
 282
 283 /* Forward declaration */
 284 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
 285 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp);
 286 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 287
 288 /****************************************************************************
 289 * General service functions
 290 ****************************************************************************/
 291
 292 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
 293
 294 static void __storm_memset_dma_mapping(struct bnx2x *bp,
 295                                        u32 addr, dma_addr_t mapping)
 296 {
 297         REG_WR(bp,  addr, U64_LO(mapping));
 298         REG_WR(bp,  addr + 4, U64_HI(mapping));
 299 }
 300
 301 static void storm_memset_spq_addr(struct bnx2x *bp,
 302                                   dma_addr_t mapping, u16 abs_fid)
 303 {
 304         u32 addr = XSEM_REG_FAST_MEMORY +
 305                         XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
 306
 307         __storm_memset_dma_mapping(bp, addr, mapping);
 308 }
 309
 310 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
 311                                   u16 pf_id)
 312 {
 313         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
 314                 pf_id);
 315         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
 316                 pf_id);
 317         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
 318                 pf_id);
 319         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
 320                 pf_id);
 321 }
 322
 323 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
 324                                  u8 enable)
 325 {
 326         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
 327                 enable);
 328         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
 329                 enable);
 330         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
 331                 enable);
 332         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
 333                 enable);
 334 }
 335
 336 static void storm_memset_eq_data(struct bnx2x *bp,
 337                                  struct event_ring_data *eq_data,
 338                                 u16 pfid)
 339 {
 340         size_t size = sizeof(struct event_ring_data);
 341
 342         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
 343
 344         __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
 345 }
 346
 347 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
 348                                  u16 pfid)
 349 {
 350         u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
 351         REG_WR16(bp, addr, eq_prod);
 352 }
 353
 354 /* used only at init
 355  * locking is done by mcp
 356  */
 357 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
 358 {
 359         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 360         pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
 361         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 362                                PCICFG_VENDOR_ID_OFFSET);
 363 }
 364
 365 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
 366 {
 367         u32 val;
 368
 369         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
 370         pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
 371         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
 372                                PCICFG_VENDOR_ID_OFFSET);
 373
 374         return val;
 375 }
 376
 377 #define DMAE_DP_SRC_GRC         "grc src_addr [%08x]"
 378 #define DMAE_DP_SRC_PCI         "pci src_addr [%x:%08x]"
 379 #define DMAE_DP_DST_GRC         "grc dst_addr [%08x]"
 380 #define DMAE_DP_DST_PCI         "pci dst_addr [%x:%08x]"
 381 #define DMAE_DP_DST_NONE        "dst_addr [none]"
 382
 383 static void bnx2x_dp_dmae(struct bnx2x *bp,
 384                           struct dmae_command *dmae, int msglvl)
 385 {
 386         u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
 387         int i;
 388
 389         switch (dmae->opcode & DMAE_COMMAND_DST) {
 390         case DMAE_CMD_DST_PCI:
 391                 if (src_type == DMAE_CMD_SRC_PCI)
 392                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 393                            "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
 394                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 395                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 396                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 397                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 398                            dmae->comp_val);
 399                 else
 400                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 401                            "src [%08x], len [%d*4], dst [%x:%08x]\n"
 402                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 403                            dmae->opcode, dmae->src_addr_lo >> 2,
 404                            dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
 405                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 406                            dmae->comp_val);
 407                 break;
 408         case DMAE_CMD_DST_GRC:
 409                 if (src_type == DMAE_CMD_SRC_PCI)
 410                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 411                            "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
 412                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 413                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 414                            dmae->len, dmae->dst_addr_lo >> 2,
 415                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 416                            dmae->comp_val);
 417                 else
 418                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 419                            "src [%08x], len [%d*4], dst [%08x]\n"
 420                            "comp_addr [%x:%08x], comp_val 0x%08x\n",
 421                            dmae->opcode, dmae->src_addr_lo >> 2,
 422                            dmae->len, dmae->dst_addr_lo >> 2,
 423                            dmae->comp_addr_hi, dmae->comp_addr_lo,
 424                            dmae->comp_val);
 425                 break;
 426         default:
 427                 if (src_type == DMAE_CMD_SRC_PCI)
 428                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 429                            "src_addr [%x:%08x]  len [%d * 4]  dst_addr [none]\n"
 430                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 431                            dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
 432                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 433                            dmae->comp_val);
 434                 else
 435                         DP(msglvl, "DMAE: opcode 0x%08x\n"
 436                            "src_addr [%08x]  len [%d * 4]  dst_addr [none]\n"
 437                            "comp_addr [%x:%08x]  comp_val 0x%08x\n",
 438                            dmae->opcode, dmae->src_addr_lo >> 2,
 439                            dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
 440                            dmae->comp_val);
 441                 break;
 442         }
 443
 444         for (i = 0; i < (sizeof(struct dmae_command)/4); i++)
 445                 DP(msglvl, "DMAE RAW [%02d]: 0x%08x\n",
 446                    i, *(((u32 *)dmae) + i));
 447 }
 448
 449 /* copy command into DMAE command memory and set DMAE command go */
 450 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
 451 {
 452         u32 cmd_offset;
 453         int i;
 454
 455         cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
 456         for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
 457                 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
 458         }
 459         REG_WR(bp, dmae_reg_go_c[idx], 1);
 460 }
 461
 462 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
 463 {
 464         return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
 465                            DMAE_CMD_C_ENABLE);
 466 }
 467
 468 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
 469 {
 470         return opcode & ~DMAE_CMD_SRC_RESET;
 471 }
 472
 473 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
 474                              bool with_comp, u8 comp_type)
 475 {
 476         u32 opcode = 0;
 477
 478         opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
 479                    (dst_type << DMAE_COMMAND_DST_SHIFT));
 480
 481         opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
 482
 483         opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
 484         opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
 485                    (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
 486         opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
 487
 488 #ifdef __BIG_ENDIAN
 489         opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
 490 #else
 491         opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
 492 #endif
 493         if (with_comp)
 494                 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
 495         return opcode;
 496 }
 497
 498 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
 499                                       struct dmae_command *dmae,
 500                                       u8 src_type, u8 dst_type)
 501 {
 502         memset(dmae, 0, sizeof(struct dmae_command));
 503
 504         /* set the opcode */
 505         dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
 506                                          true, DMAE_COMP_PCI);
 507
 508         /* fill in the completion parameters */
 509         dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
 510         dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
 511         dmae->comp_val = DMAE_COMP_VAL;
 512 }
 513
 514 /* issue a dmae command over the init-channel and wait for completion */
 515 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
 516                                u32 *comp)
 517 {
 518         int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
 519         int rc = 0;
 520
 521         bnx2x_dp_dmae(bp, dmae, BNX2X_MSG_DMAE);
 522
 523         /* Lock the dmae channel. Disable BHs to prevent a dead-lock
 524          * as long as this code is called both from syscall context and
 525          * from ndo_set_rx_mode() flow that may be called from BH.
 526          */
 527
 528         spin_lock_bh(&bp->dmae_lock);
 529
 530         /* reset completion */
 531         *comp = 0;
 532
 533         /* post the command on the channel used for initializations */
 534         bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
 535
 536         /* wait for completion */
 537         udelay(5);
 538         while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
 539
 540                 if (!cnt ||
 541                     (bp->recovery_state != BNX2X_RECOVERY_DONE &&
 542                      bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
 543                         BNX2X_ERR("DMAE timeout!\n");
 544                         rc = DMAE_TIMEOUT;
 545                         goto unlock;
 546                 }
 547                 cnt--;
 548                 udelay(50);
 549         }
 550         if (*comp & DMAE_PCI_ERR_FLAG) {
 551                 BNX2X_ERR("DMAE PCI error!\n");
 552                 rc = DMAE_PCI_ERROR;
 553         }
 554
 555 unlock:
 556
 557         spin_unlock_bh(&bp->dmae_lock);
 558
 559         return rc;
 560 }
 561
 562 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
 563                       u32 len32)
 564 {
 565         int rc;
 566         struct dmae_command dmae;
 567
 568         if (!bp->dmae_ready) {
 569                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 570
 571                 if (CHIP_IS_E1(bp))
 572                         bnx2x_init_ind_wr(bp, dst_addr, data, len32);
 573                 else
 574                         bnx2x_init_str_wr(bp, dst_addr, data, len32);
 575                 return;
 576         }
 577
 578         /* set opcode and fixed command fields */
 579         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
 580
 581         /* fill in addresses and len */
 582         dmae.src_addr_lo = U64_LO(dma_addr);
 583         dmae.src_addr_hi = U64_HI(dma_addr);
 584         dmae.dst_addr_lo = dst_addr >> 2;
 585         dmae.dst_addr_hi = 0;
 586         dmae.len = len32;
 587
 588         /* issue the command and wait for completion */
 589         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 590         if (rc) {
 591                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 592 #ifdef BNX2X_STOP_ON_ERROR
 593                 bnx2x_panic();
 594 #endif
 595         }
 596 }
 597
 598 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
 599 {
 600         int rc;
 601         struct dmae_command dmae;
 602
 603         if (!bp->dmae_ready) {
 604                 u32 *data = bnx2x_sp(bp, wb_data[0]);
 605                 int i;
 606
 607                 if (CHIP_IS_E1(bp))
 608                         for (i = 0; i < len32; i++)
 609                                 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
 610                 else
 611                         for (i = 0; i < len32; i++)
 612                                 data[i] = REG_RD(bp, src_addr + i*4);
 613
 614                 return;
 615         }
 616
 617         /* set opcode and fixed command fields */
 618         bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
 619
 620         /* fill in addresses and len */
 621         dmae.src_addr_lo = src_addr >> 2;
 622         dmae.src_addr_hi = 0;
 623         dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
 624         dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
 625         dmae.len = len32;
 626
 627         /* issue the command and wait for completion */
 628         rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
 629         if (rc) {
 630                 BNX2X_ERR("DMAE returned failure %d\n", rc);
 631 #ifdef BNX2X_STOP_ON_ERROR
 632                 bnx2x_panic();
 633 #endif
 634         }
 635 }
 636
 637 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
 638                                       u32 addr, u32 len)
 639 {
 640         int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
 641         int offset = 0;
 642
 643         while (len > dmae_wr_max) {
 644                 bnx2x_write_dmae(bp, phys_addr + offset,
 645                                  addr + offset, dmae_wr_max);
 646                 offset += dmae_wr_max * 4;
 647                 len -= dmae_wr_max;
 648         }
 649
 650         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 651 }
 652
 653 enum storms {
 654            XSTORM,
 655            TSTORM,
 656            CSTORM,
 657            USTORM,
 658            MAX_STORMS
 659 };
 660
 661 #define STORMS_NUM 4
 662 #define REGS_IN_ENTRY 4
 663
 664 static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
 665                                               enum storms storm,
 666                                               int entry)
 667 {
 668         switch (storm) {
 669         case XSTORM:
 670                 return XSTORM_ASSERT_LIST_OFFSET(entry);
 671         case TSTORM:
 672                 return TSTORM_ASSERT_LIST_OFFSET(entry);
 673         case CSTORM:
 674                 return CSTORM_ASSERT_LIST_OFFSET(entry);
 675         case USTORM:
 676                 return USTORM_ASSERT_LIST_OFFSET(entry);
 677         case MAX_STORMS:
 678         default:
 679                 BNX2X_ERR("unknown storm\n");
 680         }
 681         return -EINVAL;
 682 }
 683
 684 static int bnx2x_mc_assert(struct bnx2x *bp)
 685 {
 686         char last_idx;
 687         int i, j, rc = 0;
 688         enum storms storm;
 689         u32 regs[REGS_IN_ENTRY];
 690         u32 bar_storm_intmem[STORMS_NUM] = {
 691                 BAR_XSTRORM_INTMEM,
 692                 BAR_TSTRORM_INTMEM,
 693                 BAR_CSTRORM_INTMEM,
 694                 BAR_USTRORM_INTMEM
 695         };
 696         u32 storm_assert_list_index[STORMS_NUM] = {
 697                 XSTORM_ASSERT_LIST_INDEX_OFFSET,
 698                 TSTORM_ASSERT_LIST_INDEX_OFFSET,
 699                 CSTORM_ASSERT_LIST_INDEX_OFFSET,
 700                 USTORM_ASSERT_LIST_INDEX_OFFSET
 701         };
 702         char *storms_string[STORMS_NUM] = {
 703                 "XSTORM",
 704                 "TSTORM",
 705                 "CSTORM",
 706                 "USTORM"
 707         };
 708
 709         for (storm = XSTORM; storm < MAX_STORMS; storm++) {
 710                 last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
 711                                    storm_assert_list_index[storm]);
 712                 if (last_idx)
 713                         BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
 714                                   storms_string[storm], last_idx);
 715
 716                 /* print the asserts */
 717                 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
 718                         /* read a single assert entry */
 719                         for (j = 0; j < REGS_IN_ENTRY; j++)
 720                                 regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
 721                                           bnx2x_get_assert_list_entry(bp,
 722                                                                       storm,
 723                                                                       i) +
 724                                           sizeof(u32) * j);
 725
 726                         /* log entry if it contains a valid assert */
 727                         if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
 728                                 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
 729                                           storms_string[storm], i, regs[3],
 730                                           regs[2], regs[1], regs[0]);
 731                                 rc++;
 732                         } else {
 733                                 break;
 734                         }
 735                 }
 736         }
 737
 738         BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
 739                   CHIP_IS_E1(bp) ? "everest1" :
 740                   CHIP_IS_E1H(bp) ? "everest1h" :
 741                   CHIP_IS_E2(bp) ? "everest2" : "everest3",
 742                   BCM_5710_FW_MAJOR_VERSION,
 743                   BCM_5710_FW_MINOR_VERSION,
 744                   BCM_5710_FW_REVISION_VERSION);
 745
 746         return rc;
 747 }
 748
 749 #define MCPR_TRACE_BUFFER_SIZE  (0x800)
 750 #define SCRATCH_BUFFER_SIZE(bp) \
 751         (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
 752
 753 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
 754 {
 755         u32 addr, val;
 756         u32 mark, offset;
 757         __be32 data[9];
 758         int word;
 759         u32 trace_shmem_base;
 760         if (BP_NOMCP(bp)) {
 761                 BNX2X_ERR("NO MCP - can not dump\n");
 762                 return;
 763         }
 764         netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
 765                 (bp->common.bc_ver & 0xff0000) >> 16,
 766                 (bp->common.bc_ver & 0xff00) >> 8,
 767                 (bp->common.bc_ver & 0xff));
 768
 769         val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
 770         if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
 771                 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
 772
 773         if (BP_PATH(bp) == 0)
 774                 trace_shmem_base = bp->common.shmem_base;
 775         else
 776                 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
 777
 778         /* sanity */
 779         if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
 780             trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
 781                                 SCRATCH_BUFFER_SIZE(bp)) {
 782                 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
 783                           trace_shmem_base);
 784                 return;
 785         }
 786
 787         addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
 788
 789         /* validate TRCB signature */
 790         mark = REG_RD(bp, addr);
 791         if (mark != MFW_TRACE_SIGNATURE) {
 792                 BNX2X_ERR("Trace buffer signature is missing.");
 793                 return ;
 794         }
 795
 796         /* read cyclic buffer pointer */
 797         addr += 4;
 798         mark = REG_RD(bp, addr);
 799         mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
 800         if (mark >= trace_shmem_base || mark < addr + 4) {
 801                 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
 802                 return;
 803         }
 804         printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
 805
 806         printk("%s", lvl);
 807
 808         /* dump buffer after the mark */
 809         for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
 810                 for (word = 0; word < 8; word++)
 811                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 812                 data[8] = 0x0;
 813                 pr_cont("%s", (char *)data);
 814         }
 815
 816         /* dump buffer before the mark */
 817         for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
 818                 for (word = 0; word < 8; word++)
 819                         data[word] = htonl(REG_RD(bp, offset + 4*word));
 820                 data[8] = 0x0;
 821                 pr_cont("%s", (char *)data);
 822         }
 823         printk("%s" "end of fw dump\n", lvl);
 824 }
 825
 826 static void bnx2x_fw_dump(struct bnx2x *bp)
 827 {
 828         bnx2x_fw_dump_lvl(bp, KERN_ERR);
 829 }
 830
 831 static void bnx2x_hc_int_disable(struct bnx2x *bp)
 832 {
 833         int port = BP_PORT(bp);
 834         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
 835         u32 val = REG_RD(bp, addr);
 836
 837         /* in E1 we must use only PCI configuration space to disable
 838          * MSI/MSIX capability
 839          * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
 840          */
 841         if (CHIP_IS_E1(bp)) {
 842                 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
 843                  * Use mask register to prevent from HC sending interrupts
 844                  * after we exit the function
 845                  */
 846                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
 847
 848                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 849                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 850                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 851         } else
 852                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
 853                          HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
 854                          HC_CONFIG_0_REG_INT_LINE_EN_0 |
 855                          HC_CONFIG_0_REG_ATTN_BIT_EN_0);
 856
 857         DP(NETIF_MSG_IFDOWN,
 858            "write %x to HC %d (addr 0x%x)\n",
 859            val, port, addr);
 860
 861         /* flush all outstanding writes */
 862         mmiowb();
 863
 864         REG_WR(bp, addr, val);
 865         if (REG_RD(bp, addr) != val)
 866                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 867 }
 868
 869 static void bnx2x_igu_int_disable(struct bnx2x *bp)
 870 {
 871         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
 872
 873         val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
 874                  IGU_PF_CONF_INT_LINE_EN |
 875                  IGU_PF_CONF_ATTN_BIT_EN);
 876
 877         DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
 878
 879         /* flush all outstanding writes */
 880         mmiowb();
 881
 882         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
 883         if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
 884                 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
 885 }
 886
 887 static void bnx2x_int_disable(struct bnx2x *bp)
 888 {
 889         if (bp->common.int_block == INT_BLOCK_HC)
 890                 bnx2x_hc_int_disable(bp);
 891         else
 892                 bnx2x_igu_int_disable(bp);
 893 }
 894
 895 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
 896 {
 897         int i;
 898         u16 j;
 899         struct hc_sp_status_block_data sp_sb_data;
 900         int func = BP_FUNC(bp);
 901 #ifdef BNX2X_STOP_ON_ERROR
 902         u16 start = 0, end = 0;
 903         u8 cos;
 904 #endif
 905         if (IS_PF(bp) && disable_int)
 906                 bnx2x_int_disable(bp);
 907
 908         bp->stats_state = STATS_STATE_DISABLED;
 909         bp->eth_stats.unrecoverable_error++;
 910         DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
 911
 912         BNX2X_ERR("begin crash dump -----------------\n");
 913
 914         /* Indices */
 915         /* Common */
 916         if (IS_PF(bp)) {
 917                 struct host_sp_status_block *def_sb = bp->def_status_blk;
 918                 int data_size, cstorm_offset;
 919
 920                 BNX2X_ERR("def_idx(0x%x)  def_att_idx(0x%x)  attn_state(0x%x)  spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
 921                           bp->def_idx, bp->def_att_idx, bp->attn_state,
 922                           bp->spq_prod_idx, bp->stats_counter);
 923                 BNX2X_ERR("DSB: attn bits(0x%x)  ack(0x%x)  id(0x%x)  idx(0x%x)\n",
 924                           def_sb->atten_status_block.attn_bits,
 925                           def_sb->atten_status_block.attn_bits_ack,
 926                           def_sb->atten_status_block.status_block_id,
 927                           def_sb->atten_status_block.attn_bits_index);
 928                 BNX2X_ERR("     def (");
 929                 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
 930                         pr_cont("0x%x%s",
 931                                 def_sb->sp_sb.index_values[i],
 932                                 (i == HC_SP_SB_MAX_INDICES - 1) ? ")  " : " ");
 933
 934                 data_size = sizeof(struct hc_sp_status_block_data) /
 935                             sizeof(u32);
 936                 cstorm_offset = CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func);
 937                 for (i = 0; i < data_size; i++)
 938                         *((u32 *)&sp_sb_data + i) =
 939                                 REG_RD(bp, BAR_CSTRORM_INTMEM + cstorm_offset +
 940                                            i * sizeof(u32));
 941
 942                 pr_cont("igu_sb_id(0x%x)  igu_seg_id(0x%x) pf_id(0x%x)  vnic_id(0x%x)  vf_id(0x%x)  vf_valid (0x%x) state(0x%x)\n",
 943                         sp_sb_data.igu_sb_id,
 944                         sp_sb_data.igu_seg_id,
 945                         sp_sb_data.p_func.pf_id,
 946                         sp_sb_data.p_func.vnic_id,
 947                         sp_sb_data.p_func.vf_id,
 948                         sp_sb_data.p_func.vf_valid,
 949                         sp_sb_data.state);
 950         }
 951
 952         for_each_eth_queue(bp, i) {
 953                 struct bnx2x_fastpath *fp = &bp->fp[i];
 954                 int loop;
 955                 struct hc_status_block_data_e2 sb_data_e2;
 956                 struct hc_status_block_data_e1x sb_data_e1x;
 957                 struct hc_status_block_sm  *hc_sm_p =
 958                         CHIP_IS_E1x(bp) ?
 959                         sb_data_e1x.common.state_machine :
 960                         sb_data_e2.common.state_machine;
 961                 struct hc_index_data *hc_index_p =
 962                         CHIP_IS_E1x(bp) ?
 963                         sb_data_e1x.index_data :
 964                         sb_data_e2.index_data;
 965                 u8 data_size, cos;
 966                 u32 *sb_data_p;
 967                 struct bnx2x_fp_txdata txdata;
 968
 969                 if (!bp->fp)
 970                         break;
 971
 972                 if (!fp->rx_cons_sb)
 973                         continue;
 974
 975                 /* Rx */
 976                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
 977                           i, fp->rx_bd_prod, fp->rx_bd_cons,
 978                           fp->rx_comp_prod,
 979                           fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
 980                 BNX2X_ERR("     rx_sge_prod(0x%x)  last_max_sge(0x%x)  fp_hc_idx(0x%x)\n",
 981                           fp->rx_sge_prod, fp->last_max_sge,
 982                           le16_to_cpu(fp->fp_hc_idx));
 983
 984                 /* Tx */
 985                 for_each_cos_in_tx_queue(fp, cos)
 986                 {
 987                         if (!fp->txdata_ptr)
 988                                 break;
 989
 990                         txdata = *fp->txdata_ptr[cos];
 991
 992                         if (!txdata.tx_cons_sb)
 993                                 continue;
 994
 995                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
 996                                   i, txdata.tx_pkt_prod,
 997                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
 998                                   txdata.tx_bd_cons,
 999                                   le16_to_cpu(*txdata.tx_cons_sb));
1000                 }
1001
1002                 loop = CHIP_IS_E1x(bp) ?
1003                         HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
1004
1005                 /* host sb data */
1006
1007                 if (IS_FCOE_FP(fp))
1008                         continue;
1009
1010                 BNX2X_ERR("     run indexes (");
1011                 for (j = 0; j < HC_SB_MAX_SM; j++)
1012                         pr_cont("0x%x%s",
1013                                fp->sb_running_index[j],
1014                                (j == HC_SB_MAX_SM - 1) ? ")" : " ");
1015
1016                 BNX2X_ERR("     indexes (");
1017                 for (j = 0; j < loop; j++)
1018                         pr_cont("0x%x%s",
1019                                fp->sb_index_values[j],
1020                                (j == loop - 1) ? ")" : " ");
1021
1022                 /* VF cannot access FW refelection for status block */
1023                 if (IS_VF(bp))
1024                         continue;
1025
1026                 /* fw sb data */
1027                 data_size = CHIP_IS_E1x(bp) ?
1028                         sizeof(struct hc_status_block_data_e1x) :
1029                         sizeof(struct hc_status_block_data_e2);
1030                 data_size /= sizeof(u32);
1031                 sb_data_p = CHIP_IS_E1x(bp) ?
1032                         (u32 *)&sb_data_e1x :
1033                         (u32 *)&sb_data_e2;
1034                 /* copy sb data in here */
1035                 for (j = 0; j < data_size; j++)
1036                         *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
1037                                 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
1038                                 j * sizeof(u32));
1039
1040                 if (!CHIP_IS_E1x(bp)) {
1041                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1042                                 sb_data_e2.common.p_func.pf_id,
1043                                 sb_data_e2.common.p_func.vf_id,
1044                                 sb_data_e2.common.p_func.vf_valid,
1045                                 sb_data_e2.common.p_func.vnic_id,
1046                                 sb_data_e2.common.same_igu_sb_1b,
1047                                 sb_data_e2.common.state);
1048                 } else {
1049                         pr_cont("pf_id(0x%x)  vf_id(0x%x)  vf_valid(0x%x) vnic_id(0x%x)  same_igu_sb_1b(0x%x) state(0x%x)\n",
1050                                 sb_data_e1x.common.p_func.pf_id,
1051                                 sb_data_e1x.common.p_func.vf_id,
1052                                 sb_data_e1x.common.p_func.vf_valid,
1053                                 sb_data_e1x.common.p_func.vnic_id,
1054                                 sb_data_e1x.common.same_igu_sb_1b,
1055                                 sb_data_e1x.common.state);
1056                 }
1057
1058                 /* SB_SMs data */
1059                 for (j = 0; j < HC_SB_MAX_SM; j++) {
1060                         pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x)  igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1061                                 j, hc_sm_p[j].__flags,
1062                                 hc_sm_p[j].igu_sb_id,
1063                                 hc_sm_p[j].igu_seg_id,
1064                                 hc_sm_p[j].time_to_expire,
1065                                 hc_sm_p[j].timer_value);
1066                 }
1067
1068                 /* Indices data */
1069                 for (j = 0; j < loop; j++) {
1070                         pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1071                                hc_index_p[j].flags,
1072                                hc_index_p[j].timeout);
1073                 }
1074         }
1075
1076 #ifdef BNX2X_STOP_ON_ERROR
1077         if (IS_PF(bp)) {
1078                 /* event queue */
1079                 BNX2X_ERR("eq cons %x prod %x\n", bp->eq_cons, bp->eq_prod);
1080                 for (i = 0; i < NUM_EQ_DESC; i++) {
1081                         u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1082
1083                         BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1084                                   i, bp->eq_ring[i].message.opcode,
1085                                   bp->eq_ring[i].message.error);
1086                         BNX2X_ERR("data: %x %x %x\n",
1087                                   data[0], data[1], data[2]);
1088                 }
1089         }
1090
1091         /* Rings */
1092         /* Rx */
1093         for_each_valid_rx_queue(bp, i) {
1094                 struct bnx2x_fastpath *fp = &bp->fp[i];
1095
1096                 if (!bp->fp)
1097                         break;
1098
1099                 if (!fp->rx_cons_sb)
1100                         continue;
1101
1102                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1103                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1104                 for (j = start; j != end; j = RX_BD(j + 1)) {
1105                         u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1106                         struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1107
1108                         BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x]  sw_bd=[%p]\n",
1109                                   i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1110                 }
1111
1112                 start = RX_SGE(fp->rx_sge_prod);
1113                 end = RX_SGE(fp->last_max_sge);
1114                 for (j = start; j != end; j = RX_SGE(j + 1)) {
1115                         u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1116                         struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1117
1118                         BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x]  sw_page=[%p]\n",
1119                                   i, j, rx_sge[1], rx_sge[0], sw_page->page);
1120                 }
1121
1122                 start = RCQ_BD(fp->rx_comp_cons - 10);
1123                 end = RCQ_BD(fp->rx_comp_cons + 503);
1124                 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1125                         u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1126
1127                         BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1128                                   i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1129                 }
1130         }
1131
1132         /* Tx */
1133         for_each_valid_tx_queue(bp, i) {
1134                 struct bnx2x_fastpath *fp = &bp->fp[i];
1135
1136                 if (!bp->fp)
1137                         break;
1138
1139                 for_each_cos_in_tx_queue(fp, cos) {
1140                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1141
1142                         if (!fp->txdata_ptr)
1143                                 break;
1144
1145                         if (!txdata.tx_cons_sb)
1146                                 continue;
1147
1148                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1149                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1150                         for (j = start; j != end; j = TX_BD(j + 1)) {
1151                                 struct sw_tx_bd *sw_bd =
1152                                         &txdata->tx_buf_ring[j];
1153
1154                                 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1155                                           i, cos, j, sw_bd->skb,
1156                                           sw_bd->first_bd);
1157                         }
1158
1159                         start = TX_BD(txdata->tx_bd_cons - 10);
1160                         end = TX_BD(txdata->tx_bd_cons + 254);
1161                         for (j = start; j != end; j = TX_BD(j + 1)) {
1162                                 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1163
1164                                 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1165                                           i, cos, j, tx_bd[0], tx_bd[1],
1166                                           tx_bd[2], tx_bd[3]);
1167                         }
1168                 }
1169         }
1170 #endif
1171         if (IS_PF(bp)) {
1172                 bnx2x_fw_dump(bp);
1173                 bnx2x_mc_assert(bp);
1174         }
1175         BNX2X_ERR("end crash dump -----------------\n");
1176 }
1177
1178 /*
1179  * FLR Support for E2
1180  *
1181  * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1182  * initialization.
1183  */
1184 #define FLR_WAIT_USEC           10000   /* 10 milliseconds */
1185 #define FLR_WAIT_INTERVAL       50      /* usec */
1186 #define FLR_POLL_CNT            (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1187
1188 struct pbf_pN_buf_regs {
1189         int pN;
1190         u32 init_crd;
1191         u32 crd;
1192         u32 crd_freed;
1193 };
1194
1195 struct pbf_pN_cmd_regs {
1196         int pN;
1197         u32 lines_occup;
1198         u32 lines_freed;
1199 };
1200
1201 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1202                                      struct pbf_pN_buf_regs *regs,
1203                                      u32 poll_count)
1204 {
1205         u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1206         u32 cur_cnt = poll_count;
1207
1208         crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1209         crd = crd_start = REG_RD(bp, regs->crd);
1210         init_crd = REG_RD(bp, regs->init_crd);
1211
1212         DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1213         DP(BNX2X_MSG_SP, "CREDIT[%d]      : s:%x\n", regs->pN, crd);
1214         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1215
1216         while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1217                (init_crd - crd_start))) {
1218                 if (cur_cnt--) {
1219                         udelay(FLR_WAIT_INTERVAL);
1220                         crd = REG_RD(bp, regs->crd);
1221                         crd_freed = REG_RD(bp, regs->crd_freed);
1222                 } else {
1223                         DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1224                            regs->pN);
1225                         DP(BNX2X_MSG_SP, "CREDIT[%d]      : c:%x\n",
1226                            regs->pN, crd);
1227                         DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1228                            regs->pN, crd_freed);
1229                         break;
1230                 }
1231         }
1232         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1233            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1234 }
1235
1236 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1237                                      struct pbf_pN_cmd_regs *regs,
1238                                      u32 poll_count)
1239 {
1240         u32 occup, to_free, freed, freed_start;
1241         u32 cur_cnt = poll_count;
1242
1243         occup = to_free = REG_RD(bp, regs->lines_occup);
1244         freed = freed_start = REG_RD(bp, regs->lines_freed);
1245
1246         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n", regs->pN, occup);
1247         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1248
1249         while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1250                 if (cur_cnt--) {
1251                         udelay(FLR_WAIT_INTERVAL);
1252                         occup = REG_RD(bp, regs->lines_occup);
1253                         freed = REG_RD(bp, regs->lines_freed);
1254                 } else {
1255                         DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1256                            regs->pN);
1257                         DP(BNX2X_MSG_SP, "OCCUPANCY[%d]   : s:%x\n",
1258                            regs->pN, occup);
1259                         DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1260                            regs->pN, freed);
1261                         break;
1262                 }
1263         }
1264         DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1265            poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1266 }
1267
1268 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1269                                     u32 expected, u32 poll_count)
1270 {
1271         u32 cur_cnt = poll_count;
1272         u32 val;
1273
1274         while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1275                 udelay(FLR_WAIT_INTERVAL);
1276
1277         return val;
1278 }
1279
1280 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1281                                     char *msg, u32 poll_cnt)
1282 {
1283         u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1284         if (val != 0) {
1285                 BNX2X_ERR("%s usage count=%d\n", msg, val);
1286                 return 1;
1287         }
1288         return 0;
1289 }
1290
1291 /* Common routines with VF FLR cleanup */
1292 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1293 {
1294         /* adjust polling timeout */
1295         if (CHIP_REV_IS_EMUL(bp))
1296                 return FLR_POLL_CNT * 2000;
1297
1298         if (CHIP_REV_IS_FPGA(bp))
1299                 return FLR_POLL_CNT * 120;
1300
1301         return FLR_POLL_CNT;
1302 }
1303
1304 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1305 {
1306         struct pbf_pN_cmd_regs cmd_regs[] = {
1307                 {0, (CHIP_IS_E3B0(bp)) ?
1308                         PBF_REG_TQ_OCCUPANCY_Q0 :
1309                         PBF_REG_P0_TQ_OCCUPANCY,
1310                     (CHIP_IS_E3B0(bp)) ?
1311                         PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1312                         PBF_REG_P0_TQ_LINES_FREED_CNT},
1313                 {1, (CHIP_IS_E3B0(bp)) ?
1314                         PBF_REG_TQ_OCCUPANCY_Q1 :
1315                         PBF_REG_P1_TQ_OCCUPANCY,
1316                     (CHIP_IS_E3B0(bp)) ?
1317                         PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1318                         PBF_REG_P1_TQ_LINES_FREED_CNT},
1319                 {4, (CHIP_IS_E3B0(bp)) ?
1320                         PBF_REG_TQ_OCCUPANCY_LB_Q :
1321                         PBF_REG_P4_TQ_OCCUPANCY,
1322                     (CHIP_IS_E3B0(bp)) ?
1323                         PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1324                         PBF_REG_P4_TQ_LINES_FREED_CNT}
1325         };
1326
1327         struct pbf_pN_buf_regs buf_regs[] = {
1328                 {0, (CHIP_IS_E3B0(bp)) ?
1329                         PBF_REG_INIT_CRD_Q0 :
1330                         PBF_REG_P0_INIT_CRD ,
1331                     (CHIP_IS_E3B0(bp)) ?
1332                         PBF_REG_CREDIT_Q0 :
1333                         PBF_REG_P0_CREDIT,
1334                     (CHIP_IS_E3B0(bp)) ?
1335                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1336                         PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1337                 {1, (CHIP_IS_E3B0(bp)) ?
1338                         PBF_REG_INIT_CRD_Q1 :
1339                         PBF_REG_P1_INIT_CRD,
1340                     (CHIP_IS_E3B0(bp)) ?
1341                         PBF_REG_CREDIT_Q1 :
1342                         PBF_REG_P1_CREDIT,
1343                     (CHIP_IS_E3B0(bp)) ?
1344                         PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1345                         PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1346                 {4, (CHIP_IS_E3B0(bp)) ?
1347                         PBF_REG_INIT_CRD_LB_Q :
1348                         PBF_REG_P4_INIT_CRD,
1349                     (CHIP_IS_E3B0(bp)) ?
1350                         PBF_REG_CREDIT_LB_Q :
1351                         PBF_REG_P4_CREDIT,
1352                     (CHIP_IS_E3B0(bp)) ?
1353                         PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1354                         PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1355         };
1356
1357         int i;
1358
1359         /* Verify the command queues are flushed P0, P1, P4 */
1360         for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1361                 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1362
1363         /* Verify the transmission buffers are flushed P0, P1, P4 */
1364         for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1365                 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1366 }
1367
1368 #define OP_GEN_PARAM(param) \
1369         (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1370
1371 #define OP_GEN_TYPE(type) \
1372         (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1373
1374 #define OP_GEN_AGG_VECT(index) \
1375         (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1376
1377 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1378 {
1379         u32 op_gen_command = 0;
1380         u32 comp_addr = BAR_CSTRORM_INTMEM +
1381                         CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1382         int ret = 0;
1383
1384         if (REG_RD(bp, comp_addr)) {
1385                 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1386                 return 1;
1387         }
1388
1389         op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1390         op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1391         op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1392         op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1393
1394         DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1395         REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1396
1397         if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1398                 BNX2X_ERR("FW final cleanup did not succeed\n");
1399                 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1400                    (REG_RD(bp, comp_addr)));
1401                 bnx2x_panic();
1402                 return 1;
1403         }
1404         /* Zero completion for next FLR */
1405         REG_WR(bp, comp_addr, 0);
1406
1407         return ret;
1408 }
1409
1410 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1411 {
1412         u16 status;
1413
1414         pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1415         return status & PCI_EXP_DEVSTA_TRPND;
1416 }
1417
1418 /* PF FLR specific routines
1419 */
1420 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1421 {
1422         /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1423         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1424                         CFC_REG_NUM_LCIDS_INSIDE_PF,
1425                         "CFC PF usage counter timed out",
1426                         poll_cnt))
1427                 return 1;
1428
1429         /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1430         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1431                         DORQ_REG_PF_USAGE_CNT,
1432                         "DQ PF usage counter timed out",
1433                         poll_cnt))
1434                 return 1;
1435
1436         /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1437         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1438                         QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1439                         "QM PF usage counter timed out",
1440                         poll_cnt))
1441                 return 1;
1442
1443         /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1444         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1445                         TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1446                         "Timers VNIC usage counter timed out",
1447                         poll_cnt))
1448                 return 1;
1449         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1450                         TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1451                         "Timers NUM_SCANS usage counter timed out",
1452                         poll_cnt))
1453                 return 1;
1454
1455         /* Wait DMAE PF usage counter to zero */
1456         if (bnx2x_flr_clnup_poll_hw_counter(bp,
1457                         dmae_reg_go_c[INIT_DMAE_C(bp)],
1458                         "DMAE command register timed out",
1459                         poll_cnt))
1460                 return 1;
1461
1462         return 0;
1463 }
1464
1465 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1466 {
1467         u32 val;
1468
1469         val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1470         DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1471
1472         val = REG_RD(bp, PBF_REG_DISABLE_PF);
1473         DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1474
1475         val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1476         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1477
1478         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1479         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1480
1481         val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1482         DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1483
1484         val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1485         DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1486
1487         val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1488         DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1489
1490         val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1491         DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1492            val);
1493 }
1494
1495 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1496 {
1497         u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1498
1499         DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1500
1501         /* Re-enable PF target read access */
1502         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1503
1504         /* Poll HW usage counters */
1505         DP(BNX2X_MSG_SP, "Polling usage counters\n");
1506         if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1507                 return -EBUSY;
1508
1509         /* Zero the igu 'trailing edge' and 'leading edge' */
1510
1511         /* Send the FW cleanup command */
1512         if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1513                 return -EBUSY;
1514
1515         /* ATC cleanup */
1516
1517         /* Verify TX hw is flushed */
1518         bnx2x_tx_hw_flushed(bp, poll_cnt);
1519
1520         /* Wait 100ms (not adjusted according to platform) */
1521         msleep(100);
1522
1523         /* Verify no pending pci transactions */
1524         if (bnx2x_is_pcie_pending(bp->pdev))
1525                 BNX2X_ERR("PCIE Transactions still pending\n");
1526
1527         /* Debug */
1528         bnx2x_hw_enable_status(bp);
1529
1530         /*
1531          * Master enable - Due to WB DMAE writes performed before this
1532          * register is re-initialized as part of the regular function init
1533          */
1534         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1535
1536         return 0;
1537 }
1538
1539 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1540 {
1541         int port = BP_PORT(bp);
1542         u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1543         u32 val = REG_RD(bp, addr);
1544         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1545         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1546         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1547
1548         if (msix) {
1549                 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1550                          HC_CONFIG_0_REG_INT_LINE_EN_0);
1551                 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1552                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1553                 if (single_msix)
1554                         val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1555         } else if (msi) {
1556                 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1557                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1558                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1559                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1560         } else {
1561                 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1562                         HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1563                         HC_CONFIG_0_REG_INT_LINE_EN_0 |
1564                         HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1565
1566                 if (!CHIP_IS_E1(bp)) {
1567                         DP(NETIF_MSG_IFUP,
1568                            "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1569
1570                         REG_WR(bp, addr, val);
1571
1572                         val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1573                 }
1574         }
1575
1576         if (CHIP_IS_E1(bp))
1577                 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1578
1579         DP(NETIF_MSG_IFUP,
1580            "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1581            (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1582
1583         REG_WR(bp, addr, val);
1584         /*
1585          * Ensure that HC_CONFIG is written before leading/trailing edge config
1586          */
1587         mmiowb();
1588         barrier();
1589
1590         if (!CHIP_IS_E1(bp)) {
1591                 /* init leading/trailing edge */
1592                 if (IS_MF(bp)) {
1593                         val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1594                         if (bp->port.pmf)
1595                                 /* enable nig and gpio3 attention */
1596                                 val |= 0x1100;
1597                 } else
1598                         val = 0xffff;
1599
1600                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1601                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1602         }
1603
1604         /* Make sure that interrupts are indeed enabled from here on */
1605         mmiowb();
1606 }
1607
1608 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1609 {
1610         u32 val;
1611         bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1612         bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1613         bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1614
1615         val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1616
1617         if (msix) {
1618                 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1619                          IGU_PF_CONF_SINGLE_ISR_EN);
1620                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1621                         IGU_PF_CONF_ATTN_BIT_EN);
1622
1623                 if (single_msix)
1624                         val |= IGU_PF_CONF_SINGLE_ISR_EN;
1625         } else if (msi) {
1626                 val &= ~IGU_PF_CONF_INT_LINE_EN;
1627                 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1628                         IGU_PF_CONF_ATTN_BIT_EN |
1629                         IGU_PF_CONF_SINGLE_ISR_EN);
1630         } else {
1631                 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1632                 val |= (IGU_PF_CONF_INT_LINE_EN |
1633                         IGU_PF_CONF_ATTN_BIT_EN |
1634                         IGU_PF_CONF_SINGLE_ISR_EN);
1635         }
1636
1637         /* Clean previous status - need to configure igu prior to ack*/
1638         if ((!msix) || single_msix) {
1639                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1640                 bnx2x_ack_int(bp);
1641         }
1642
1643         val |= IGU_PF_CONF_FUNC_EN;
1644
1645         DP(NETIF_MSG_IFUP, "write 0x%x to IGU  mode %s\n",
1646            val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1647
1648         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1649
1650         if (val & IGU_PF_CONF_INT_LINE_EN)
1651                 pci_intx(bp->pdev, true);
1652
1653         barrier();
1654
1655         /* init leading/trailing edge */
1656         if (IS_MF(bp)) {
1657                 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1658                 if (bp->port.pmf)
1659                         /* enable nig and gpio3 attention */
1660                         val |= 0x1100;
1661         } else
1662                 val = 0xffff;
1663
1664         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1665         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1666
1667         /* Make sure that interrupts are indeed enabled from here on */
1668         mmiowb();
1669 }
1670
1671 void bnx2x_int_enable(struct bnx2x *bp)
1672 {
1673         if (bp->common.int_block == INT_BLOCK_HC)
1674                 bnx2x_hc_int_enable(bp);
1675         else
1676                 bnx2x_igu_int_enable(bp);
1677 }
1678
1679 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1680 {
1681         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1682         int i, offset;
1683
1684         if (disable_hw)
1685                 /* prevent the HW from sending interrupts */
1686                 bnx2x_int_disable(bp);
1687
1688         /* make sure all ISRs are done */
1689         if (msix) {
1690                 synchronize_irq(bp->msix_table[0].vector);
1691                 offset = 1;
1692                 if (CNIC_SUPPORT(bp))
1693                         offset++;
1694                 for_each_eth_queue(bp, i)
1695                         synchronize_irq(bp->msix_table[offset++].vector);
1696         } else
1697                 synchronize_irq(bp->pdev->irq);
1698
1699         /* make sure sp_task is not running */
1700         cancel_delayed_work(&bp->sp_task);
1701         cancel_delayed_work(&bp->period_task);
1702         flush_workqueue(bnx2x_wq);
1703 }
1704
1705 /* fast path */
1706
1707 /*
1708  * General service functions
1709  */
1710
1711 /* Return true if succeeded to acquire the lock */
1712 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1713 {
1714         u32 lock_status;
1715         u32 resource_bit = (1 << resource);
1716         int func = BP_FUNC(bp);
1717         u32 hw_lock_control_reg;
1718
1719         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1720            "Trying to take a lock on resource %d\n", resource);
1721
1722         /* Validating that the resource is within range */
1723         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1724                 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1725                    "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1726                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1727                 return false;
1728         }
1729
1730         if (func <= 5)
1731                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1732         else
1733                 hw_lock_control_reg =
1734                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1735
1736         /* Try to acquire the lock */
1737         REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1738         lock_status = REG_RD(bp, hw_lock_control_reg);
1739         if (lock_status & resource_bit)
1740                 return true;
1741
1742         DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1743            "Failed to get a lock on resource %d\n", resource);
1744         return false;
1745 }
1746
1747 /**
1748  * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1749  *
1750  * @bp: driver handle
1751  *
1752  * Returns the recovery leader resource id according to the engine this function
1753  * belongs to. Currently only only 2 engines is supported.
1754  */
1755 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1756 {
1757         if (BP_PATH(bp))
1758                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1759         else
1760                 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1761 }
1762
1763 /**
1764  * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1765  *
1766  * @bp: driver handle
1767  *
1768  * Tries to acquire a leader lock for current engine.
1769  */
1770 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1771 {
1772         return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1773 }
1774
1775 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1776
1777 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1778 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1779 {
1780         /* Set the interrupt occurred bit for the sp-task to recognize it
1781          * must ack the interrupt and transition according to the IGU
1782          * state machine.
1783          */
1784         atomic_set(&bp->interrupt_occurred, 1);
1785
1786         /* The sp_task must execute only after this bit
1787          * is set, otherwise we will get out of sync and miss all
1788          * further interrupts. Hence, the barrier.
1789          */
1790         smp_wmb();
1791
1792         /* schedule sp_task to workqueue */
1793         return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1794 }
1795
1796 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1797 {
1798         struct bnx2x *bp = fp->bp;
1799         int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1800         int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1801         enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1802         struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1803
1804         DP(BNX2X_MSG_SP,
1805            "fp %d  cid %d  got ramrod #%d  state is %x  type is %d\n",
1806            fp->index, cid, command, bp->state,
1807            rr_cqe->ramrod_cqe.ramrod_type);
1808
1809         /* If cid is within VF range, replace the slowpath object with the
1810          * one corresponding to this VF
1811          */
1812         if (cid >= BNX2X_FIRST_VF_CID  &&
1813             cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1814                 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1815
1816         switch (command) {
1817         case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1818                 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1819                 drv_cmd = BNX2X_Q_CMD_UPDATE;
1820                 break;
1821
1822         case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1823                 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1824                 drv_cmd = BNX2X_Q_CMD_SETUP;
1825                 break;
1826
1827         case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1828                 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1829                 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1830                 break;
1831
1832         case (RAMROD_CMD_ID_ETH_HALT):
1833                 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1834                 drv_cmd = BNX2X_Q_CMD_HALT;
1835                 break;
1836
1837         case (RAMROD_CMD_ID_ETH_TERMINATE):
1838                 DP(BNX2X_MSG_SP, "got MULTI[%d] terminate ramrod\n", cid);
1839                 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1840                 break;
1841
1842         case (RAMROD_CMD_ID_ETH_EMPTY):
1843                 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1844                 drv_cmd = BNX2X_Q_CMD_EMPTY;
1845                 break;
1846
1847         case (RAMROD_CMD_ID_ETH_TPA_UPDATE):
1848                 DP(BNX2X_MSG_SP, "got tpa update ramrod CID=%d\n", cid);
1849                 drv_cmd = BNX2X_Q_CMD_UPDATE_TPA;
1850                 break;
1851
1852         default:
1853                 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1854                           command, fp->index);
1855                 return;
1856         }
1857
1858         if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1859             q_obj->complete_cmd(bp, q_obj, drv_cmd))
1860                 /* q_obj->complete_cmd() failure means that this was
1861                  * an unexpected completion.
1862                  *
1863                  * In this case we don't want to increase the bp->spq_left
1864                  * because apparently we haven't sent this command the first
1865                  * place.
1866                  */
1867 #ifdef BNX2X_STOP_ON_ERROR
1868                 bnx2x_panic();
1869 #else
1870                 return;
1871 #endif
1872
1873         smp_mb__before_atomic();
1874         atomic_inc(&bp->cq_spq_left);
1875         /* push the change in bp->spq_left and towards the memory */
1876         smp_mb__after_atomic();
1877
1878         DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1879
1880         if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1881             (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1882                 /* if Q update ramrod is completed for last Q in AFEX vif set
1883                  * flow, then ACK MCP at the end
1884                  *
1885                  * mark pending ACK to MCP bit.
1886                  * prevent case that both bits are cleared.
1887                  * At the end of load/unload driver checks that
1888                  * sp_state is cleared, and this order prevents
1889                  * races
1890                  */
1891                 smp_mb__before_atomic();
1892                 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1893                 wmb();
1894                 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1895                 smp_mb__after_atomic();
1896
1897                 /* schedule the sp task as mcp ack is required */
1898                 bnx2x_schedule_sp_task(bp);
1899         }
1900
1901         return;
1902 }
1903
1904 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1905 {
1906         struct bnx2x *bp = netdev_priv(dev_instance);
1907         u16 status = bnx2x_ack_int(bp);
1908         u16 mask;
1909         int i;
1910         u8 cos;
1911
1912         /* Return here if interrupt is shared and it's not for us */
1913         if (unlikely(status == 0)) {
1914                 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1915                 return IRQ_NONE;
1916         }
1917         DP(NETIF_MSG_INTR, "got an interrupt  status 0x%x\n", status);
1918
1919 #ifdef BNX2X_STOP_ON_ERROR
1920         if (unlikely(bp->panic))
1921                 return IRQ_HANDLED;
1922 #endif
1923
1924         for_each_eth_queue(bp, i) {
1925                 struct bnx2x_fastpath *fp = &bp->fp[i];
1926
1927                 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1928                 if (status & mask) {
1929                         /* Handle Rx or Tx according to SB id */
1930                         for_each_cos_in_tx_queue(fp, cos)
1931                                 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1932                         prefetch(&fp->sb_running_index[SM_RX_ID]);
1933                         napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1934                         status &= ~mask;
1935                 }
1936         }
1937
1938         if (CNIC_SUPPORT(bp)) {
1939                 mask = 0x2;
1940                 if (status & (mask | 0x1)) {
1941                         struct cnic_ops *c_ops = NULL;
1942
1943                         rcu_read_lock();
1944                         c_ops = rcu_dereference(bp->cnic_ops);
1945                         if (c_ops && (bp->cnic_eth_dev.drv_state &
1946                                       CNIC_DRV_STATE_HANDLES_IRQ))
1947                                 c_ops->cnic_handler(bp->cnic_data, NULL);
1948                         rcu_read_unlock();
1949
1950                         status &= ~mask;
1951                 }
1952         }
1953
1954         if (unlikely(status & 0x1)) {
1955
1956                 /* schedule sp task to perform default status block work, ack
1957                  * attentions and enable interrupts.
1958                  */
1959                 bnx2x_schedule_sp_task(bp);
1960
1961                 status &= ~0x1;
1962                 if (!status)
1963                         return IRQ_HANDLED;
1964         }
1965
1966         if (unlikely(status))
1967                 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1968                    status);
1969
1970         return IRQ_HANDLED;
1971 }
1972
1973 /* Link */
1974
1975 /*
1976  * General service functions
1977  */
1978
1979 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1980 {
1981         u32 lock_status;
1982         u32 resource_bit = (1 << resource);
1983         int func = BP_FUNC(bp);
1984         u32 hw_lock_control_reg;
1985         int cnt;
1986
1987         /* Validating that the resource is within range */
1988         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1989                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1990                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
1991                 return -EINVAL;
1992         }
1993
1994         if (func <= 5) {
1995                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1996         } else {
1997                 hw_lock_control_reg =
1998                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1999         }
2000
2001         /* Validating that the resource is not already taken */
2002         lock_status = REG_RD(bp, hw_lock_control_reg);
2003         if (lock_status & resource_bit) {
2004                 BNX2X_ERR("lock_status 0x%x  resource_bit 0x%x\n",
2005                    lock_status, resource_bit);
2006                 return -EEXIST;
2007         }
2008
2009         /* Try for 5 second every 5ms */
2010         for (cnt = 0; cnt < 1000; cnt++) {
2011                 /* Try to acquire the lock */
2012                 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
2013                 lock_status = REG_RD(bp, hw_lock_control_reg);
2014                 if (lock_status & resource_bit)
2015                         return 0;
2016
2017                 usleep_range(5000, 10000);
2018         }
2019         BNX2X_ERR("Timeout\n");
2020         return -EAGAIN;
2021 }
2022
2023 int bnx2x_release_leader_lock(struct bnx2x *bp)
2024 {
2025         return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
2026 }
2027
2028 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
2029 {
2030         u32 lock_status;
2031         u32 resource_bit = (1 << resource);
2032         int func = BP_FUNC(bp);
2033         u32 hw_lock_control_reg;
2034
2035         /* Validating that the resource is within range */
2036         if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
2037                 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2038                    resource, HW_LOCK_MAX_RESOURCE_VALUE);
2039                 return -EINVAL;
2040         }
2041
2042         if (func <= 5) {
2043                 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
2044         } else {
2045                 hw_lock_control_reg =
2046                                 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
2047         }
2048
2049         /* Validating that the resource is currently taken */
2050         lock_status = REG_RD(bp, hw_lock_control_reg);
2051         if (!(lock_status & resource_bit)) {
2052                 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2053                           lock_status, resource_bit);
2054                 return -EFAULT;
2055         }
2056
2057         REG_WR(bp, hw_lock_control_reg, resource_bit);
2058         return 0;
2059 }
2060
2061 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
2062 {
2063         /* The GPIO should be swapped if swap register is set and active */
2064         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2065                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2066         int gpio_shift = gpio_num +
2067                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2068         u32 gpio_mask = (1 << gpio_shift);
2069         u32 gpio_reg;
2070         int value;
2071
2072         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2073                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2074                 return -EINVAL;
2075         }
2076
2077         /* read GPIO value */
2078         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2079
2080         /* get the requested pin value */
2081         if ((gpio_reg & gpio_mask) == gpio_mask)
2082                 value = 1;
2083         else
2084                 value = 0;
2085
2086         return value;
2087 }
2088
2089 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2090 {
2091         /* The GPIO should be swapped if swap register is set and active */
2092         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2093                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2094         int gpio_shift = gpio_num +
2095                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2096         u32 gpio_mask = (1 << gpio_shift);
2097         u32 gpio_reg;
2098
2099         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2100                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2101                 return -EINVAL;
2102         }
2103
2104         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2105         /* read GPIO and mask except the float bits */
2106         gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2107
2108         switch (mode) {
2109         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2110                 DP(NETIF_MSG_LINK,
2111                    "Set GPIO %d (shift %d) -> output low\n",
2112                    gpio_num, gpio_shift);
2113                 /* clear FLOAT and set CLR */
2114                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2115                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2116                 break;
2117
2118         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2119                 DP(NETIF_MSG_LINK,
2120                    "Set GPIO %d (shift %d) -> output high\n",
2121                    gpio_num, gpio_shift);
2122                 /* clear FLOAT and set SET */
2123                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2124                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2125                 break;
2126
2127         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2128                 DP(NETIF_MSG_LINK,
2129                    "Set GPIO %d (shift %d) -> input\n",
2130                    gpio_num, gpio_shift);
2131                 /* set FLOAT */
2132                 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2133                 break;
2134
2135         default:
2136                 break;
2137         }
2138
2139         REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2140         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2141
2142         return 0;
2143 }
2144
2145 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2146 {
2147         u32 gpio_reg = 0;
2148         int rc = 0;
2149
2150         /* Any port swapping should be handled by caller. */
2151
2152         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2153         /* read GPIO and mask except the float bits */
2154         gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2155         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2156         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2157         gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2158
2159         switch (mode) {
2160         case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2161                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2162                 /* set CLR */
2163                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2164                 break;
2165
2166         case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2167                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2168                 /* set SET */
2169                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2170                 break;
2171
2172         case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2173                 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2174                 /* set FLOAT */
2175                 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2176                 break;
2177
2178         default:
2179                 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2180                 rc = -EINVAL;
2181                 break;
2182         }
2183
2184         if (rc == 0)
2185                 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2186
2187         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2188
2189         return rc;
2190 }
2191
2192 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2193 {
2194         /* The GPIO should be swapped if swap register is set and active */
2195         int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2196                          REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2197         int gpio_shift = gpio_num +
2198                         (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2199         u32 gpio_mask = (1 << gpio_shift);
2200         u32 gpio_reg;
2201
2202         if (gpio_num > MISC_REGISTERS_GPIO_3) {
2203                 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2204                 return -EINVAL;
2205         }
2206
2207         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2208         /* read GPIO int */
2209         gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2210
2211         switch (mode) {
2212         case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2213                 DP(NETIF_MSG_LINK,
2214                    "Clear GPIO INT %d (shift %d) -> output low\n",
2215                    gpio_num, gpio_shift);
2216                 /* clear SET and set CLR */
2217                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2218                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2219                 break;
2220
2221         case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2222                 DP(NETIF_MSG_LINK,
2223                    "Set GPIO INT %d (shift %d) -> output high\n",
2224                    gpio_num, gpio_shift);
2225                 /* clear CLR and set SET */
2226                 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2227                 gpio_reg |=  (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2228                 break;
2229
2230         default:
2231                 break;
2232         }
2233
2234         REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2235         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2236
2237         return 0;
2238 }
2239
2240 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2241 {
2242         u32 spio_reg;
2243
2244         /* Only 2 SPIOs are configurable */
2245         if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2246                 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2247                 return -EINVAL;
2248         }
2249
2250         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2251         /* read SPIO and mask except the float bits */
2252         spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2253
2254         switch (mode) {
2255         case MISC_SPIO_OUTPUT_LOW:
2256                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2257                 /* clear FLOAT and set CLR */
2258                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2259                 spio_reg |=  (spio << MISC_SPIO_CLR_POS);
2260                 break;
2261
2262         case MISC_SPIO_OUTPUT_HIGH:
2263                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2264                 /* clear FLOAT and set SET */
2265                 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2266                 spio_reg |=  (spio << MISC_SPIO_SET_POS);
2267                 break;
2268
2269         case MISC_SPIO_INPUT_HI_Z:
2270                 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2271                 /* set FLOAT */
2272                 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2273                 break;
2274
2275         default:
2276                 break;
2277         }
2278
2279         REG_WR(bp, MISC_REG_SPIO, spio_reg);
2280         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2281
2282         return 0;
2283 }
2284
2285 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2286 {
2287         u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2288         switch (bp->link_vars.ieee_fc &
2289                 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2290         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2291                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2292                                                    ADVERTISED_Pause);
2293                 break;
2294
2295         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2296                 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2297                                                   ADVERTISED_Pause);
2298                 break;
2299
2300         case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2301                 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2302                 break;
2303
2304         default:
2305                 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2306                                                    ADVERTISED_Pause);
2307                 break;
2308         }
2309 }
2310
2311 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2312 {
2313         /* Initialize link parameters structure variables
2314          * It is recommended to turn off RX FC for jumbo frames
2315          *  for better performance
2316          */
2317         if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2318                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2319         else
2320                 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2321 }
2322
2323 static void bnx2x_init_dropless_fc(struct bnx2x *bp)
2324 {
2325         u32 pause_enabled = 0;
2326
2327         if (!CHIP_IS_E1(bp) && bp->dropless_fc && bp->link_vars.link_up) {
2328                 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2329                         pause_enabled = 1;
2330
2331                 REG_WR(bp, BAR_USTRORM_INTMEM +
2332                            USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp)),
2333                        pause_enabled);
2334         }
2335
2336         DP(NETIF_MSG_IFUP | NETIF_MSG_LINK, "dropless_fc is %s\n",
2337            pause_enabled ? "enabled" : "disabled");
2338 }
2339
2340 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2341 {
2342         int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2343         u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2344
2345         if (!BP_NOMCP(bp)) {
2346                 bnx2x_set_requested_fc(bp);
2347                 bnx2x_acquire_phy_lock(bp);
2348
2349                 if (load_mode == LOAD_DIAG) {
2350                         struct link_params *lp = &bp->link_params;
2351                         lp->loopback_mode = LOOPBACK_XGXS;
2352                         /* do PHY loopback at 10G speed, if possible */
2353                         if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2354                                 if (lp->speed_cap_mask[cfx_idx] &
2355                                     PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2356                                         lp->req_line_speed[cfx_idx] =
2357                                         SPEED_10000;
2358                                 else
2359                                         lp->req_line_speed[cfx_idx] =
2360                                         SPEED_1000;
2361                         }
2362                 }
2363
2364                 if (load_mode == LOAD_LOOPBACK_EXT) {
2365                         struct link_params *lp = &bp->link_params;
2366                         lp->loopback_mode = LOOPBACK_EXT;
2367                 }
2368
2369                 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2370
2371                 bnx2x_release_phy_lock(bp);
2372
2373                 bnx2x_init_dropless_fc(bp);
2374
2375                 bnx2x_calc_fc_adv(bp);
2376
2377                 if (bp->link_vars.link_up) {
2378                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2379                         bnx2x_link_report(bp);
2380                 }
2381                 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2382                 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2383                 return rc;
2384         }
2385         BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2386         return -EINVAL;
2387 }
2388
2389 void bnx2x_link_set(struct bnx2x *bp)
2390 {
2391         if (!BP_NOMCP(bp)) {
2392                 bnx2x_acquire_phy_lock(bp);
2393                 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2394                 bnx2x_release_phy_lock(bp);
2395
2396                 bnx2x_init_dropless_fc(bp);
2397
2398                 bnx2x_calc_fc_adv(bp);
2399         } else
2400                 BNX2X_ERR("Bootcode is missing - can not set link\n");
2401 }
2402
2403 static void bnx2x__link_reset(struct bnx2x *bp)
2404 {
2405         if (!BP_NOMCP(bp)) {
2406                 bnx2x_acquire_phy_lock(bp);
2407                 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2408                 bnx2x_release_phy_lock(bp);
2409         } else
2410                 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2411 }
2412
2413 void bnx2x_force_link_reset(struct bnx2x *bp)
2414 {
2415         bnx2x_acquire_phy_lock(bp);
2416         bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2417         bnx2x_release_phy_lock(bp);
2418 }
2419
2420 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2421 {
2422         u8 rc = 0;
2423
2424         if (!BP_NOMCP(bp)) {
2425                 bnx2x_acquire_phy_lock(bp);
2426                 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2427                                      is_serdes);
2428                 bnx2x_release_phy_lock(bp);
2429         } else
2430                 BNX2X_ERR("Bootcode is missing - can not test link\n");
2431
2432         return rc;
2433 }
2434
2435 /* Calculates the sum of vn_min_rates.
2436    It's needed for further normalizing of the min_rates.
2437    Returns:
2438      sum of vn_min_rates.
2439        or
2440      0 - if all the min_rates are 0.
2441      In the later case fairness algorithm should be deactivated.
2442      If not all min_rates are zero then those that are zeroes will be set to 1.
2443  */
2444 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2445                                       struct cmng_init_input *input)
2446 {
2447         int all_zero = 1;
2448         int vn;
2449
2450         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2451                 u32 vn_cfg = bp->mf_config[vn];
2452                 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2453                                    FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2454
2455                 /* Skip hidden vns */
2456                 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2457                         vn_min_rate = 0;
2458                 /* If min rate is zero - set it to 1 */
2459                 else if (!vn_min_rate)
2460                         vn_min_rate = DEF_MIN_RATE;
2461                 else
2462                         all_zero = 0;
2463
2464                 input->vnic_min_rate[vn] = vn_min_rate;
2465         }
2466
2467         /* if ETS or all min rates are zeros - disable fairness */
2468         if (BNX2X_IS_ETS_ENABLED(bp)) {
2469                 input->flags.cmng_enables &=
2470                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2471                 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2472         } else if (all_zero) {
2473                 input->flags.cmng_enables &=
2474                                         ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2475                 DP(NETIF_MSG_IFUP,
2476                    "All MIN values are zeroes fairness will be disabled\n");
2477         } else
2478                 input->flags.cmng_enables |=
2479                                         CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2480 }
2481
2482 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2483                                     struct cmng_init_input *input)
2484 {
2485         u16 vn_max_rate;
2486         u32 vn_cfg = bp->mf_config[vn];
2487
2488         if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2489                 vn_max_rate = 0;
2490         else {
2491                 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2492
2493                 if (IS_MF_SI(bp)) {
2494                         /* maxCfg in percents of linkspeed */
2495                         vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2496                 } else /* SD modes */
2497                         /* maxCfg is absolute in 100Mb units */
2498                         vn_max_rate = maxCfg * 100;
2499         }
2500
2501         DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2502
2503         input->vnic_max_rate[vn] = vn_max_rate;
2504 }
2505
2506 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2507 {
2508         if (CHIP_REV_IS_SLOW(bp))
2509                 return CMNG_FNS_NONE;
2510         if (IS_MF(bp))
2511                 return CMNG_FNS_MINMAX;
2512
2513         return CMNG_FNS_NONE;
2514 }
2515
2516 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2517 {
2518         int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2519
2520         if (BP_NOMCP(bp))
2521                 return; /* what should be the default value in this case */
2522
2523         /* For 2 port configuration the absolute function number formula
2524          * is:
2525          *      abs_func = 2 * vn + BP_PORT + BP_PATH
2526          *
2527          *      and there are 4 functions per port
2528          *
2529          * For 4 port configuration it is
2530          *      abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2531          *
2532          *      and there are 2 functions per port
2533          */
2534         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2535                 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2536
2537                 if (func >= E1H_FUNC_MAX)
2538                         break;
2539
2540                 bp->mf_config[vn] =
2541                         MF_CFG_RD(bp, func_mf_config[func].config);
2542         }
2543         if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2544                 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2545                 bp->flags |= MF_FUNC_DIS;
2546         } else {
2547                 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2548                 bp->flags &= ~MF_FUNC_DIS;
2549         }
2550 }
2551
2552 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2553 {
2554         struct cmng_init_input input;
2555         memset(&input, 0, sizeof(struct cmng_init_input));
2556
2557         input.port_rate = bp->link_vars.line_speed;
2558
2559         if (cmng_type == CMNG_FNS_MINMAX && input.port_rate) {
2560                 int vn;
2561
2562                 /* read mf conf from shmem */
2563                 if (read_cfg)
2564                         bnx2x_read_mf_cfg(bp);
2565
2566                 /* vn_weight_sum and enable fairness if not 0 */
2567                 bnx2x_calc_vn_min(bp, &input);
2568
2569                 /* calculate and set min-max rate for each vn */
2570                 if (bp->port.pmf)
2571                         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2572                                 bnx2x_calc_vn_max(bp, vn, &input);
2573
2574                 /* always enable rate shaping and fairness */
2575                 input.flags.cmng_enables |=
2576                                         CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2577
2578                 bnx2x_init_cmng(&input, &bp->cmng);
2579                 return;
2580         }
2581
2582         /* rate shaping and fairness are disabled */
2583         DP(NETIF_MSG_IFUP,
2584            "rate shaping and fairness are disabled\n");
2585 }
2586
2587 static void storm_memset_cmng(struct bnx2x *bp,
2588                               struct cmng_init *cmng,
2589                               u8 port)
2590 {
2591         int vn;
2592         size_t size = sizeof(struct cmng_struct_per_port);
2593
2594         u32 addr = BAR_XSTRORM_INTMEM +
2595                         XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2596
2597         __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2598
2599         for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2600                 int func = func_by_vn(bp, vn);
2601
2602                 addr = BAR_XSTRORM_INTMEM +
2603                        XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2604                 size = sizeof(struct rate_shaping_vars_per_vn);
2605                 __storm_memset_struct(bp, addr, size,
2606                                       (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2607
2608                 addr = BAR_XSTRORM_INTMEM +
2609                        XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2610                 size = sizeof(struct fairness_vars_per_vn);
2611                 __storm_memset_struct(bp, addr, size,
2612                                       (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2613         }
2614 }
2615
2616 /* init cmng mode in HW according to local configuration */
2617 void bnx2x_set_local_cmng(struct bnx2x *bp)
2618 {
2619         int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2620
2621         if (cmng_fns != CMNG_FNS_NONE) {
2622                 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2623                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2624         } else {
2625                 /* rate shaping and fairness are disabled */
2626                 DP(NETIF_MSG_IFUP,
2627                    "single function mode without fairness\n");
2628         }
2629 }
2630
2631 /* This function is called upon link interrupt */
2632 static void bnx2x_link_attn(struct bnx2x *bp)
2633 {
2634         /* Make sure that we are synced with the current statistics */
2635         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2636
2637         bnx2x_link_update(&bp->link_params, &bp->link_vars);
2638
2639         bnx2x_init_dropless_fc(bp);
2640
2641         if (bp->link_vars.link_up) {
2642
2643                 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2644                         struct host_port_stats *pstats;
2645
2646                         pstats = bnx2x_sp(bp, port_stats);
2647                         /* reset old mac stats */
2648                         memset(&(pstats->mac_stx[0]), 0,
2649                                sizeof(struct mac_stx));
2650                 }
2651                 if (bp->state == BNX2X_STATE_OPEN)
2652                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2653         }
2654
2655         if (bp->link_vars.link_up && bp->link_vars.line_speed)
2656                 bnx2x_set_local_cmng(bp);
2657
2658         __bnx2x_link_report(bp);
2659
2660         if (IS_MF(bp))
2661                 bnx2x_link_sync_notify(bp);
2662 }
2663
2664 void bnx2x__link_status_update(struct bnx2x *bp)
2665 {
2666         if (bp->state != BNX2X_STATE_OPEN)
2667                 return;
2668
2669         /* read updated dcb configuration */
2670         if (IS_PF(bp)) {
2671                 bnx2x_dcbx_pmf_update(bp);
2672                 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2673                 if (bp->link_vars.link_up)
2674                         bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2675                 else
2676                         bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2677                         /* indicate link status */
2678                 bnx2x_link_report(bp);
2679
2680         } else { /* VF */
2681                 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2682                                           SUPPORTED_10baseT_Full |
2683                                           SUPPORTED_100baseT_Half |
2684                                           SUPPORTED_100baseT_Full |
2685                                           SUPPORTED_1000baseT_Full |
2686                                           SUPPORTED_2500baseX_Full |
2687                                           SUPPORTED_10000baseT_Full |
2688                                           SUPPORTED_TP |
2689                                           SUPPORTED_FIBRE |
2690                                           SUPPORTED_Autoneg |
2691                                           SUPPORTED_Pause |
2692                                           SUPPORTED_Asym_Pause);
2693                 bp->port.advertising[0] = bp->port.supported[0];
2694
2695                 bp->link_params.bp = bp;
2696                 bp->link_params.port = BP_PORT(bp);
2697                 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2698                 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2699                 bp->link_params.req_line_speed[0] = SPEED_10000;
2700                 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2701                 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2702                 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2703                 bp->link_vars.line_speed = SPEED_10000;
2704                 bp->link_vars.link_status =
2705                         (LINK_STATUS_LINK_UP |
2706                          LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2707                 bp->link_vars.link_up = 1;
2708                 bp->link_vars.duplex = DUPLEX_FULL;
2709                 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2710                 __bnx2x_link_report(bp);
2711
2712                 bnx2x_sample_bulletin(bp);
2713
2714                 /* if bulletin board did not have an update for link status
2715                  * __bnx2x_link_report will report current status
2716                  * but it will NOT duplicate report in case of already reported
2717                  * during sampling bulletin board.
2718                  */
2719                 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2720         }
2721 }
2722
2723 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2724                                   u16 vlan_val, u8 allowed_prio)
2725 {
2726         struct bnx2x_func_state_params func_params = {NULL};
2727         struct bnx2x_func_afex_update_params *f_update_params =
2728                 &func_params.params.afex_update;
2729
2730         func_params.f_obj = &bp->func_obj;
2731         func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2732
2733         /* no need to wait for RAMROD completion, so don't
2734          * set RAMROD_COMP_WAIT flag
2735          */
2736
2737         f_update_params->vif_id = vifid;
2738         f_update_params->afex_default_vlan = vlan_val;
2739         f_update_params->allowed_priorities = allowed_prio;
2740
2741         /* if ramrod can not be sent, response to MCP immediately */
2742         if (bnx2x_func_state_change(bp, &func_params) < 0)
2743                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2744
2745         return 0;
2746 }
2747
2748 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2749                                           u16 vif_index, u8 func_bit_map)
2750 {
2751         struct bnx2x_func_state_params func_params = {NULL};
2752         struct bnx2x_func_afex_viflists_params *update_params =
2753                 &func_params.params.afex_viflists;
2754         int rc;
2755         u32 drv_msg_code;
2756
2757         /* validate only LIST_SET and LIST_GET are received from switch */
2758         if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2759                 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2760                           cmd_type);
2761
2762         func_params.f_obj = &bp->func_obj;
2763         func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2764
2765         /* set parameters according to cmd_type */
2766         update_params->afex_vif_list_command = cmd_type;
2767         update_params->vif_list_index = vif_index;
2768         update_params->func_bit_map =
2769                 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2770         update_params->func_to_clear = 0;
2771         drv_msg_code =
2772                 (cmd_type == VIF_LIST_RULE_GET) ?
2773                 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2774                 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2775
2776         /* if ramrod can not be sent, respond to MCP immediately for
2777          * SET and GET requests (other are not triggered from MCP)
2778          */
2779         rc = bnx2x_func_state_change(bp, &func_params);
2780         if (rc < 0)
2781                 bnx2x_fw_command(bp, drv_msg_code, 0);
2782
2783         return 0;
2784 }
2785
2786 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2787 {
2788         struct afex_stats afex_stats;
2789         u32 func = BP_ABS_FUNC(bp);
2790         u32 mf_config;
2791         u16 vlan_val;
2792         u32 vlan_prio;
2793         u16 vif_id;
2794         u8 allowed_prio;
2795         u8 vlan_mode;
2796         u32 addr_to_write, vifid, addrs, stats_type, i;
2797
2798         if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2799                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2800                 DP(BNX2X_MSG_MCP,
2801                    "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2802                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2803         }
2804
2805         if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2806                 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2807                 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2808                 DP(BNX2X_MSG_MCP,
2809                    "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2810                    vifid, addrs);
2811                 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2812                                                addrs);
2813         }
2814
2815         if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2816                 addr_to_write = SHMEM2_RD(bp,
2817                         afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2818                 stats_type = SHMEM2_RD(bp,
2819                         afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2820
2821                 DP(BNX2X_MSG_MCP,
2822                    "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2823                    addr_to_write);
2824
2825                 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2826
2827                 /* write response to scratchpad, for MCP */
2828                 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2829                         REG_WR(bp, addr_to_write + i*sizeof(u32),
2830                                *(((u32 *)(&afex_stats))+i));
2831
2832                 /* send ack message to MCP */
2833                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2834         }
2835
2836         if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2837                 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2838                 bp->mf_config[BP_VN(bp)] = mf_config;
2839                 DP(BNX2X_MSG_MCP,
2840                    "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2841                    mf_config);
2842
2843                 /* if VIF_SET is "enabled" */
2844                 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2845                         /* set rate limit directly to internal RAM */
2846                         struct cmng_init_input cmng_input;
2847                         struct rate_shaping_vars_per_vn m_rs_vn;
2848                         size_t size = sizeof(struct rate_shaping_vars_per_vn);
2849                         u32 addr = BAR_XSTRORM_INTMEM +
2850                             XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2851
2852                         bp->mf_config[BP_VN(bp)] = mf_config;
2853
2854                         bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2855                         m_rs_vn.vn_counter.rate =
2856                                 cmng_input.vnic_max_rate[BP_VN(bp)];
2857                         m_rs_vn.vn_counter.quota =
2858                                 (m_rs_vn.vn_counter.rate *
2859                                  RS_PERIODIC_TIMEOUT_USEC) / 8;
2860
2861                         __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2862
2863                         /* read relevant values from mf_cfg struct in shmem */
2864                         vif_id =
2865                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2866                                  FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2867                                 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2868                         vlan_val =
2869                                 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2870                                  FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2871                                 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2872                         vlan_prio = (mf_config &
2873                                      FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2874                                     FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2875                         vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2876                         vlan_mode =
2877                                 (MF_CFG_RD(bp,
2878                                            func_mf_config[func].afex_config) &
2879                                  FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2880                                 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2881                         allowed_prio =
2882                                 (MF_CFG_RD(bp,
2883                                            func_mf_config[func].afex_config) &
2884                                  FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2885                                 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2886
2887                         /* send ramrod to FW, return in case of failure */
2888                         if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2889                                                    allowed_prio))
2890                                 return;
2891
2892                         bp->afex_def_vlan_tag = vlan_val;
2893                         bp->afex_vlan_mode = vlan_mode;
2894                 } else {
2895                         /* notify link down because BP->flags is disabled */
2896                         bnx2x_link_report(bp);
2897
2898                         /* send INVALID VIF ramrod to FW */
2899                         bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2900
2901                         /* Reset the default afex VLAN */
2902                         bp->afex_def_vlan_tag = -1;
2903                 }
2904         }
2905 }
2906
2907 static void bnx2x_pmf_update(struct bnx2x *bp)
2908 {
2909         int port = BP_PORT(bp);
2910         u32 val;
2911
2912         bp->port.pmf = 1;
2913         DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2914
2915         /*
2916          * We need the mb() to ensure the ordering between the writing to
2917          * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2918          */
2919         smp_mb();
2920
2921         /* queue a periodic task */
2922         queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2923
2924         bnx2x_dcbx_pmf_update(bp);
2925
2926         /* enable nig attention */
2927         val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2928         if (bp->common.int_block == INT_BLOCK_HC) {
2929                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2930                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2931         } else if (!CHIP_IS_E1x(bp)) {
2932                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2933                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2934         }
2935
2936         bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2937 }
2938
2939 /* end of Link */
2940
2941 /* slow path */
2942
2943 /*
2944  * General service functions
2945  */
2946
2947 /* send the MCP a request, block until there is a reply */
2948 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2949 {
2950         int mb_idx = BP_FW_MB_IDX(bp);
2951         u32 seq;
2952         u32 rc = 0;
2953         u32 cnt = 1;
2954         u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2955
2956         mutex_lock(&bp->fw_mb_mutex);
2957         seq = ++bp->fw_seq;
2958         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2959         SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2960
2961         DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2962                         (command | seq), param);
2963
2964         do {
2965                 /* let the FW do it's magic ... */
2966                 msleep(delay);
2967
2968                 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2969
2970                 /* Give the FW up to 5 second (500*10ms) */
2971         } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2972
2973         DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2974            cnt*delay, rc, seq);
2975
2976         /* is this a reply to our command? */
2977         if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2978                 rc &= FW_MSG_CODE_MASK;
2979         else {
2980                 /* FW BUG! */
2981                 BNX2X_ERR("FW failed to respond!\n");
2982                 bnx2x_fw_dump(bp);
2983                 rc = 0;
2984         }
2985         mutex_unlock(&bp->fw_mb_mutex);
2986
2987         return rc;
2988 }
2989
2990 static void storm_memset_func_cfg(struct bnx2x *bp,
2991                                  struct tstorm_eth_function_common_config *tcfg,
2992                                  u16 abs_fid)
2993 {
2994         size_t size = sizeof(struct tstorm_eth_function_common_config);
2995
2996         u32 addr = BAR_TSTRORM_INTMEM +
2997                         TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2998
2999         __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
3000 }
3001
3002 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
3003 {
3004         if (CHIP_IS_E1x(bp)) {
3005                 struct tstorm_eth_function_common_config tcfg = {0};
3006
3007                 storm_memset_func_cfg(bp, &tcfg, p->func_id);
3008         }
3009
3010         /* Enable the function in the FW */
3011         storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
3012         storm_memset_func_en(bp, p->func_id, 1);
3013
3014         /* spq */
3015         if (p->func_flgs & FUNC_FLG_SPQ) {
3016                 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
3017                 REG_WR(bp, XSEM_REG_FAST_MEMORY +
3018                        XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
3019         }
3020 }
3021
3022 /**
3023  * bnx2x_get_common_flags - Return common flags
3024  *
3025  * @bp          device handle
3026  * @fp          queue handle
3027  * @zero_stats  TRUE if statistics zeroing is needed
3028  *
3029  * Return the flags that are common for the Tx-only and not normal connections.
3030  */
3031 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
3032                                             struct bnx2x_fastpath *fp,
3033                                             bool zero_stats)
3034 {
3035         unsigned long flags = 0;
3036
3037         /* PF driver will always initialize the Queue to an ACTIVE state */
3038         __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
3039
3040         /* tx only connections collect statistics (on the same index as the
3041          * parent connection). The statistics are zeroed when the parent
3042          * connection is initialized.
3043          */
3044
3045         __set_bit(BNX2X_Q_FLG_STATS, &flags);
3046         if (zero_stats)
3047                 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
3048
3049         if (bp->flags & TX_SWITCHING)
3050                 __set_bit(BNX2X_Q_FLG_TX_SWITCH, &flags);
3051
3052         __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
3053         __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
3054
3055 #ifdef BNX2X_STOP_ON_ERROR
3056         __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
3057 #endif
3058
3059         return flags;
3060 }
3061
3062 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
3063                                        struct bnx2x_fastpath *fp,
3064                                        bool leading)
3065 {
3066         unsigned long flags = 0;
3067
3068         /* calculate other queue flags */
3069         if (IS_MF_SD(bp))
3070                 __set_bit(BNX2X_Q_FLG_OV, &flags);
3071
3072         if (IS_FCOE_FP(fp)) {
3073                 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
3074                 /* For FCoE - force usage of default priority (for afex) */
3075                 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
3076         }
3077
3078         if (!fp->disable_tpa) {
3079                 __set_bit(BNX2X_Q_FLG_TPA, &flags);
3080                 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
3081                 if (fp->mode == TPA_MODE_GRO)
3082                         __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
3083         }
3084
3085         if (leading) {
3086                 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
3087                 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3088         }
3089
3090         /* Always set HW VLAN stripping */
3091         __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3092
3093         /* configure silent vlan removal */
3094         if (IS_MF_AFEX(bp))
3095                 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3096
3097         return flags | bnx2x_get_common_flags(bp, fp, true);
3098 }
3099
3100 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3101         struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3102         u8 cos)
3103 {
3104         gen_init->stat_id = bnx2x_stats_id(fp);
3105         gen_init->spcl_id = fp->cl_id;
3106
3107         /* Always use mini-jumbo MTU for FCoE L2 ring */
3108         if (IS_FCOE_FP(fp))
3109                 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3110         else
3111                 gen_init->mtu = bp->dev->mtu;
3112
3113         gen_init->cos = cos;
3114 }
3115
3116 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3117         struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3118         struct bnx2x_rxq_setup_params *rxq_init)
3119 {
3120         u8 max_sge = 0;
3121         u16 sge_sz = 0;
3122         u16 tpa_agg_size = 0;
3123
3124         if (!fp->disable_tpa) {
3125                 pause->sge_th_lo = SGE_TH_LO(bp);
3126                 pause->sge_th_hi = SGE_TH_HI(bp);
3127
3128                 /* validate SGE ring has enough to cross high threshold */
3129                 WARN_ON(bp->dropless_fc &&
3130                                 pause->sge_th_hi + FW_PREFETCH_CNT >
3131                                 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3132
3133                 tpa_agg_size = TPA_AGG_SIZE;
3134                 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3135                         SGE_PAGE_SHIFT;
3136                 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3137                           (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3138                 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3139         }
3140
3141         /* pause - not for e1 */
3142         if (!CHIP_IS_E1(bp)) {
3143                 pause->bd_th_lo = BD_TH_LO(bp);
3144                 pause->bd_th_hi = BD_TH_HI(bp);
3145
3146                 pause->rcq_th_lo = RCQ_TH_LO(bp);
3147                 pause->rcq_th_hi = RCQ_TH_HI(bp);
3148                 /*
3149                  * validate that rings have enough entries to cross
3150                  * high thresholds
3151                  */
3152                 WARN_ON(bp->dropless_fc &&
3153                                 pause->bd_th_hi + FW_PREFETCH_CNT >
3154                                 bp->rx_ring_size);
3155                 WARN_ON(bp->dropless_fc &&
3156                                 pause->rcq_th_hi + FW_PREFETCH_CNT >
3157                                 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3158
3159                 pause->pri_map = 1;
3160         }
3161
3162         /* rxq setup */
3163         rxq_init->dscr_map = fp->rx_desc_mapping;
3164         rxq_init->sge_map = fp->rx_sge_mapping;
3165         rxq_init->rcq_map = fp->rx_comp_mapping;
3166         rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3167
3168         /* This should be a maximum number of data bytes that may be
3169          * placed on the BD (not including paddings).
3170          */
3171         rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3172                            BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3173
3174         rxq_init->cl_qzone_id = fp->cl_qzone_id;
3175         rxq_init->tpa_agg_sz = tpa_agg_size;
3176         rxq_init->sge_buf_sz = sge_sz;
3177         rxq_init->max_sges_pkt = max_sge;
3178         rxq_init->rss_engine_id = BP_FUNC(bp);
3179         rxq_init->mcast_engine_id = BP_FUNC(bp);
3180
3181         /* Maximum number or simultaneous TPA aggregation for this Queue.
3182          *
3183          * For PF Clients it should be the maximum available number.
3184          * VF driver(s) may want to define it to a smaller value.
3185          */
3186         rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3187
3188         rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3189         rxq_init->fw_sb_id = fp->fw_sb_id;
3190
3191         if (IS_FCOE_FP(fp))
3192                 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3193         else
3194                 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3195         /* configure silent vlan removal
3196          * if multi function mode is afex, then mask default vlan
3197          */
3198         if (IS_MF_AFEX(bp)) {
3199                 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3200                 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3201         }
3202 }
3203
3204 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3205         struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3206         u8 cos)
3207 {
3208         txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3209         txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3210         txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3211         txq_init->fw_sb_id = fp->fw_sb_id;
3212
3213         /*
3214          * set the tss leading client id for TX classification ==
3215          * leading RSS client id
3216          */
3217         txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3218
3219         if (IS_FCOE_FP(fp)) {
3220                 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3221                 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3222         }
3223 }
3224
3225 static void bnx2x_pf_init(struct bnx2x *bp)
3226 {
3227         struct bnx2x_func_init_params func_init = {0};
3228         struct event_ring_data eq_data = { {0} };
3229         u16 flags;
3230
3231         if (!CHIP_IS_E1x(bp)) {
3232                 /* reset IGU PF statistics: MSIX + ATTN */
3233                 /* PF */
3234                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3235                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3236                            (CHIP_MODE_IS_4_PORT(bp) ?
3237                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3238                 /* ATTN */
3239                 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3240                            BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3241                            BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3242                            (CHIP_MODE_IS_4_PORT(bp) ?
3243                                 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3244         }
3245
3246         /* function setup flags */
3247         flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3248
3249         /* This flag is relevant for E1x only.
3250          * E2 doesn't have a TPA configuration in a function level.
3251          */
3252         flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3253
3254         func_init.func_flgs = flags;
3255         func_init.pf_id = BP_FUNC(bp);
3256         func_init.func_id = BP_FUNC(bp);
3257         func_init.spq_map = bp->spq_mapping;
3258         func_init.spq_prod = bp->spq_prod_idx;
3259
3260         bnx2x_func_init(bp, &func_init);
3261
3262         memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3263
3264         /*
3265          * Congestion management values depend on the link rate
3266          * There is no active link so initial link rate is set to 10 Gbps.
3267          * When the link comes up The congestion management values are
3268          * re-calculated according to the actual link rate.
3269          */
3270         bp->link_vars.line_speed = SPEED_10000;
3271         bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3272
3273         /* Only the PMF sets the HW */
3274         if (bp->port.pmf)
3275                 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3276
3277         /* init Event Queue - PCI bus guarantees correct endianity*/
3278         eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3279         eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3280         eq_data.producer = bp->eq_prod;
3281         eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3282         eq_data.sb_id = DEF_SB_ID;
3283         storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3284 }
3285
3286 static void bnx2x_e1h_disable(struct bnx2x *bp)
3287 {
3288         int port = BP_PORT(bp);
3289
3290         bnx2x_tx_disable(bp);
3291
3292         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3293 }
3294
3295 static void bnx2x_e1h_enable(struct bnx2x *bp)
3296 {
3297         int port = BP_PORT(bp);
3298
3299         REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3300
3301         /* Tx queue should be only re-enabled */
3302         netif_tx_wake_all_queues(bp->dev);
3303
3304         /*
3305          * Should not call netif_carrier_on since it will be called if the link
3306          * is up when checking for link state
3307          */
3308 }
3309
3310 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3311
3312 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3313 {
3314         struct eth_stats_info *ether_stat =
3315                 &bp->slowpath->drv_info_to_mcp.ether_stat;
3316         struct bnx2x_vlan_mac_obj *mac_obj =
3317                 &bp->sp_objs->mac_obj;
3318         int i;
3319
3320         strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3321                 ETH_STAT_INFO_VERSION_LEN);
3322
3323         /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3324          * mac_local field in ether_stat struct. The base address is offset by 2
3325          * bytes to account for the field being 8 bytes but a mac address is
3326          * only 6 bytes. Likewise, the stride for the get_n_elements function is
3327          * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3328          * allocated by the ether_stat struct, so the macs will land in their
3329          * proper positions.
3330          */
3331         for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3332                 memset(ether_stat->mac_local + i, 0,
3333                        sizeof(ether_stat->mac_local[0]));
3334         mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3335                                 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3336                                 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3337                                 ETH_ALEN);
3338         ether_stat->mtu_size = bp->dev->mtu;
3339         if (bp->dev->features & NETIF_F_RXCSUM)
3340                 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3341         if (bp->dev->features & NETIF_F_TSO)
3342                 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3343         ether_stat->feature_flags |= bp->common.boot_mode;
3344
3345         ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3346
3347         ether_stat->txq_size = bp->tx_ring_size;
3348         ether_stat->rxq_size = bp->rx_ring_size;
3349
3350 #ifdef CONFIG_BNX2X_SRIOV
3351         ether_stat->vf_cnt = IS_SRIOV(bp) ? bp->vfdb->sriov.nr_virtfn : 0;
3352 #endif
3353 }
3354
3355 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3356 {
3357         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3358         struct fcoe_stats_info *fcoe_stat =
3359                 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3360
3361         if (!CNIC_LOADED(bp))
3362                 return;
3363
3364         memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3365
3366         fcoe_stat->qos_priority =
3367                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3368
3369         /* insert FCoE stats from ramrod response */
3370         if (!NO_FCOE(bp)) {
3371                 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3372                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3373                         tstorm_queue_statistics;
3374
3375                 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3376                         &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3377                         xstorm_queue_statistics;
3378
3379                 struct fcoe_statistics_params *fw_fcoe_stat =
3380                         &bp->fw_stats_data->fcoe;
3381
3382                 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3383                           fcoe_stat->rx_bytes_lo,
3384                           fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3385
3386                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3387                           fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3388                           fcoe_stat->rx_bytes_lo,
3389                           fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3390
3391                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3392                           fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3393                           fcoe_stat->rx_bytes_lo,
3394                           fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3395
3396                 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3397                           fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3398                           fcoe_stat->rx_bytes_lo,
3399                           fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3400
3401                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3402                           fcoe_stat->rx_frames_lo,
3403                           fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3404
3405                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3406                           fcoe_stat->rx_frames_lo,
3407                           fcoe_q_tstorm_stats->rcv_ucast_pkts);
3408
3409                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3410                           fcoe_stat->rx_frames_lo,
3411                           fcoe_q_tstorm_stats->rcv_bcast_pkts);
3412
3413                 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3414                           fcoe_stat->rx_frames_lo,
3415                           fcoe_q_tstorm_stats->rcv_mcast_pkts);
3416
3417                 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3418                           fcoe_stat->tx_bytes_lo,
3419                           fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3420
3421                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3422                           fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3423                           fcoe_stat->tx_bytes_lo,
3424                           fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3425
3426                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3427                           fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3428                           fcoe_stat->tx_bytes_lo,
3429                           fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3430
3431                 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3432                           fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3433                           fcoe_stat->tx_bytes_lo,
3434                           fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3435
3436                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3437                           fcoe_stat->tx_frames_lo,
3438                           fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3439
3440                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3441                           fcoe_stat->tx_frames_lo,
3442                           fcoe_q_xstorm_stats->ucast_pkts_sent);
3443
3444                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3445                           fcoe_stat->tx_frames_lo,
3446                           fcoe_q_xstorm_stats->bcast_pkts_sent);
3447
3448                 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3449                           fcoe_stat->tx_frames_lo,
3450                           fcoe_q_xstorm_stats->mcast_pkts_sent);
3451         }
3452
3453         /* ask L5 driver to add data to the struct */
3454         bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3455 }
3456
3457 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3458 {
3459         struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3460         struct iscsi_stats_info *iscsi_stat =
3461                 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3462
3463         if (!CNIC_LOADED(bp))
3464                 return;
3465
3466         memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3467                ETH_ALEN);
3468
3469         iscsi_stat->qos_priority =
3470                 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3471
3472         /* ask L5 driver to add data to the struct */
3473         bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3474 }
3475
3476 /* called due to MCP event (on pmf):
3477  *      reread new bandwidth configuration
3478  *      configure FW
3479  *      notify others function about the change
3480  */
3481 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3482 {
3483         if (bp->link_vars.link_up) {
3484                 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3485                 bnx2x_link_sync_notify(bp);
3486         }
3487         storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3488 }
3489
3490 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3491 {
3492         bnx2x_config_mf_bw(bp);
3493         bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3494 }
3495
3496 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3497 {
3498         DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3499         bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3500 }
3501
3502 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH        (20)
3503 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT         (25)
3504
3505 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3506 {
3507         enum drv_info_opcode op_code;
3508         u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3509         bool release = false;
3510         int wait;
3511
3512         /* if drv_info version supported by MFW doesn't match - send NACK */
3513         if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3514                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3515                 return;
3516         }
3517
3518         op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3519                   DRV_INFO_CONTROL_OP_CODE_SHIFT;
3520
3521         /* Must prevent other flows from accessing drv_info_to_mcp */
3522         mutex_lock(&bp->drv_info_mutex);
3523
3524         memset(&bp->slowpath->drv_info_to_mcp, 0,
3525                sizeof(union drv_info_to_mcp));
3526
3527         switch (op_code) {
3528         case ETH_STATS_OPCODE:
3529                 bnx2x_drv_info_ether_stat(bp);
3530                 break;
3531         case FCOE_STATS_OPCODE:
3532                 bnx2x_drv_info_fcoe_stat(bp);
3533                 break;
3534         case ISCSI_STATS_OPCODE:
3535                 bnx2x_drv_info_iscsi_stat(bp);
3536                 break;
3537         default:
3538                 /* if op code isn't supported - send NACK */
3539                 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3540                 goto out;
3541         }
3542
3543         /* if we got drv_info attn from MFW then these fields are defined in
3544          * shmem2 for sure
3545          */
3546         SHMEM2_WR(bp, drv_info_host_addr_lo,
3547                 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3548         SHMEM2_WR(bp, drv_info_host_addr_hi,
3549                 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3550
3551         bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3552
3553         /* Since possible management wants both this and get_driver_version
3554          * need to wait until management notifies us it finished utilizing
3555          * the buffer.
3556          */
3557         if (!SHMEM2_HAS(bp, mfw_drv_indication)) {
3558                 DP(BNX2X_MSG_MCP, "Management does not support indication\n");
3559         } else if (!bp->drv_info_mng_owner) {
3560                 u32 bit = MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp) >> 1));
3561
3562                 for (wait = 0; wait < BNX2X_UPDATE_DRV_INFO_IND_COUNT; wait++) {
3563                         u32 indication = SHMEM2_RD(bp, mfw_drv_indication);
3564
3565                         /* Management is done; need to clear indication */
3566                         if (indication & bit) {
3567                                 SHMEM2_WR(bp, mfw_drv_indication,
3568                                           indication & ~bit);
3569                                 release = true;
3570                                 break;
3571                         }
3572
3573                         msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH);
3574                 }
3575         }
3576         if (!release) {
3577                 DP(BNX2X_MSG_MCP, "Management did not release indication\n");
3578                 bp->drv_info_mng_owner = true;
3579         }
3580
3581 out:
3582         mutex_unlock(&bp->drv_info_mutex);
3583 }
3584
3585 static u32 bnx2x_update_mng_version_utility(u8 *version, bool bnx2x_format)
3586 {
3587         u8 vals[4];
3588         int i = 0;
3589
3590         if (bnx2x_format) {
3591                 i = sscanf(version, "1.%c%hhd.%hhd.%hhd",
3592                            &vals[0], &vals[1], &vals[2], &vals[3]);
3593                 if (i > 0)
3594                         vals[0] -= '0';
3595         } else {
3596                 i = sscanf(version, "%hhd.%hhd.%hhd.%hhd",
3597                            &vals[0], &vals[1], &vals[2], &vals[3]);
3598         }
3599
3600         while (i < 4)
3601                 vals[i++] = 0;
3602
3603         return (vals[0] << 24) | (vals[1] << 16) | (vals[2] << 8) | vals[3];
3604 }
3605
3606 void bnx2x_update_mng_version(struct bnx2x *bp)
3607 {
3608         u32 iscsiver = DRV_VER_NOT_LOADED;
3609         u32 fcoever = DRV_VER_NOT_LOADED;
3610         u32 ethver = DRV_VER_NOT_LOADED;
3611         int idx = BP_FW_MB_IDX(bp);
3612         u8 *version;
3613
3614         if (!SHMEM2_HAS(bp, func_os_drv_ver))
3615                 return;
3616
3617         mutex_lock(&bp->drv_info_mutex);
3618         /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3619         if (bp->drv_info_mng_owner)
3620                 goto out;
3621
3622         if (bp->state != BNX2X_STATE_OPEN)
3623                 goto out;
3624
3625         /* Parse ethernet driver version */
3626         ethver = bnx2x_update_mng_version_utility(DRV_MODULE_VERSION, true);
3627         if (!CNIC_LOADED(bp))
3628                 goto out;
3629
3630         /* Try getting storage driver version via cnic */
3631         memset(&bp->slowpath->drv_info_to_mcp, 0,
3632                sizeof(union drv_info_to_mcp));
3633         bnx2x_drv_info_iscsi_stat(bp);
3634         version = bp->slowpath->drv_info_to_mcp.iscsi_stat.version;
3635         iscsiver = bnx2x_update_mng_version_utility(version, false);
3636
3637         memset(&bp->slowpath->drv_info_to_mcp, 0,
3638                sizeof(union drv_info_to_mcp));
3639         bnx2x_drv_info_fcoe_stat(bp);
3640         version = bp->slowpath->drv_info_to_mcp.fcoe_stat.version;
3641         fcoever = bnx2x_update_mng_version_utility(version, false);
3642
3643 out:
3644         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ETHERNET], ethver);
3645         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_ISCSI], iscsiver);
3646         SHMEM2_WR(bp, func_os_drv_ver[idx].versions[DRV_PERS_FCOE], fcoever);
3647
3648         mutex_unlock(&bp->drv_info_mutex);
3649
3650         DP(BNX2X_MSG_MCP, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3651            ethver, iscsiver, fcoever);
3652 }
3653
3654 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3655 {
3656         DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3657
3658         if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3659
3660                 /*
3661                  * This is the only place besides the function initialization
3662                  * where the bp->flags can change so it is done without any
3663                  * locks
3664                  */
3665                 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3666                         DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3667                         bp->flags |= MF_FUNC_DIS;
3668
3669                         bnx2x_e1h_disable(bp);
3670                 } else {
3671                         DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3672                         bp->flags &= ~MF_FUNC_DIS;
3673
3674                         bnx2x_e1h_enable(bp);
3675                 }
3676                 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3677         }
3678         if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3679                 bnx2x_config_mf_bw(bp);
3680                 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3681         }
3682
3683         /* Report results to MCP */
3684         if (dcc_event)
3685                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3686         else
3687                 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3688 }
3689
3690 /* must be called under the spq lock */
3691 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3692 {
3693         struct eth_spe *next_spe = bp->spq_prod_bd;
3694
3695         if (bp->spq_prod_bd == bp->spq_last_bd) {
3696                 bp->spq_prod_bd = bp->spq;
3697                 bp->spq_prod_idx = 0;
3698                 DP(BNX2X_MSG_SP, "end of spq\n");
3699         } else {
3700                 bp->spq_prod_bd++;
3701                 bp->spq_prod_idx++;
3702         }
3703         return next_spe;
3704 }
3705
3706 /* must be called under the spq lock */
3707 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3708 {
3709         int func = BP_FUNC(bp);
3710
3711         /*
3712          * Make sure that BD data is updated before writing the producer:
3713          * BD data is written to the memory, the producer is read from the
3714          * memory, thus we need a full memory barrier to ensure the ordering.
3715          */
3716         mb();
3717
3718         REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3719                  bp->spq_prod_idx);
3720         mmiowb();
3721 }
3722
3723 /**
3724  * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3725  *
3726  * @cmd:        command to check
3727  * @cmd_type:   command type
3728  */
3729 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3730 {
3731         if ((cmd_type == NONE_CONNECTION_TYPE) ||
3732             (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3733             (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3734             (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3735             (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3736             (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3737             (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3738                 return true;
3739         else
3740                 return false;
3741 }
3742
3743 /**
3744  * bnx2x_sp_post - place a single command on an SP ring
3745  *
3746  * @bp:         driver handle
3747  * @command:    command to place (e.g. SETUP, FILTER_RULES, etc.)
3748  * @cid:        SW CID the command is related to
3749  * @data_hi:    command private data address (high 32 bits)
3750  * @data_lo:    command private data address (low 32 bits)
3751  * @cmd_type:   command type (e.g. NONE, ETH)
3752  *
3753  * SP data is handled as if it's always an address pair, thus data fields are
3754  * not swapped to little endian in upper functions. Instead this function swaps
3755  * data as if it's two u32 fields.
3756  */
3757 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3758                   u32 data_hi, u32 data_lo, int cmd_type)
3759 {
3760         struct eth_spe *spe;
3761         u16 type;
3762         bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3763
3764 #ifdef BNX2X_STOP_ON_ERROR
3765         if (unlikely(bp->panic)) {
3766                 BNX2X_ERR("Can't post SP when there is panic\n");
3767                 return -EIO;
3768         }
3769 #endif
3770
3771         spin_lock_bh(&bp->spq_lock);
3772
3773         if (common) {
3774                 if (!atomic_read(&bp->eq_spq_left)) {
3775                         BNX2X_ERR("BUG! EQ ring full!\n");
3776                         spin_unlock_bh(&bp->spq_lock);
3777                         bnx2x_panic();
3778                         return -EBUSY;
3779                 }
3780         } else if (!atomic_read(&bp->cq_spq_left)) {
3781                         BNX2X_ERR("BUG! SPQ ring full!\n");
3782                         spin_unlock_bh(&bp->spq_lock);
3783                         bnx2x_panic();
3784                         return -EBUSY;
3785         }
3786
3787         spe = bnx2x_sp_get_next(bp);
3788
3789         /* CID needs port number to be encoded int it */
3790         spe->hdr.conn_and_cmd_data =
3791                         cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3792                                     HW_CID(bp, cid));
3793
3794         /* In some cases, type may already contain the func-id
3795          * mainly in SRIOV related use cases, so we add it here only
3796          * if it's not already set.
3797          */
3798         if (!(cmd_type & SPE_HDR_FUNCTION_ID)) {
3799                 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) &
3800                         SPE_HDR_CONN_TYPE;
3801                 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3802                          SPE_HDR_FUNCTION_ID);
3803         } else {
3804                 type = cmd_type;
3805         }
3806
3807         spe->hdr.type = cpu_to_le16(type);
3808
3809         spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3810         spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3811
3812         /*
3813          * It's ok if the actual decrement is issued towards the memory
3814          * somewhere between the spin_lock and spin_unlock. Thus no
3815          * more explicit memory barrier is needed.
3816          */
3817         if (common)
3818                 atomic_dec(&bp->eq_spq_left);
3819         else
3820                 atomic_dec(&bp->cq_spq_left);
3821
3822         DP(BNX2X_MSG_SP,
3823            "SPQE[%x] (%x:%x)  (cmd, common?) (%d,%d)  hw_cid %x  data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3824            bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3825            (u32)(U64_LO(bp->spq_mapping) +
3826            (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3827            HW_CID(bp, cid), data_hi, data_lo, type,
3828            atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3829
3830         bnx2x_sp_prod_update(bp);
3831         spin_unlock_bh(&bp->spq_lock);
3832         return 0;
3833 }
3834
3835 /* acquire split MCP access lock register */
3836 static int bnx2x_acquire_alr(struct bnx2x *bp)
3837 {
3838         u32 j, val;
3839         int rc = 0;
3840
3841         might_sleep();
3842         for (j = 0; j < 1000; j++) {
3843                 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, MCPR_ACCESS_LOCK_LOCK);
3844                 val = REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK);
3845                 if (val & MCPR_ACCESS_LOCK_LOCK)
3846                         break;
3847
3848                 usleep_range(5000, 10000);
3849         }
3850         if (!(val & MCPR_ACCESS_LOCK_LOCK)) {
3851                 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3852                 rc = -EBUSY;
3853         }
3854
3855         return rc;
3856 }
3857
3858 /* release split MCP access lock register */
3859 static void bnx2x_release_alr(struct bnx2x *bp)
3860 {
3861         REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
3862 }
3863
3864 #define BNX2X_DEF_SB_ATT_IDX    0x0001
3865 #define BNX2X_DEF_SB_IDX        0x0002
3866
3867 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3868 {
3869         struct host_sp_status_block *def_sb = bp->def_status_blk;
3870         u16 rc = 0;
3871
3872         barrier(); /* status block is written to by the chip */
3873         if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3874                 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3875                 rc |= BNX2X_DEF_SB_ATT_IDX;
3876         }
3877
3878         if (bp->def_idx != def_sb->sp_sb.running_index) {
3879                 bp->def_idx = def_sb->sp_sb.running_index;
3880                 rc |= BNX2X_DEF_SB_IDX;
3881         }
3882
3883         /* Do not reorder: indices reading should complete before handling */
3884         barrier();
3885         return rc;
3886 }
3887
3888 /*
3889  * slow path service functions
3890  */
3891
3892 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3893 {
3894         int port = BP_PORT(bp);
3895         u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3896                               MISC_REG_AEU_MASK_ATTN_FUNC_0;
3897         u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3898                                        NIG_REG_MASK_INTERRUPT_PORT0;
3899         u32 aeu_mask;
3900         u32 nig_mask = 0;
3901         u32 reg_addr;
3902
3903         if (bp->attn_state & asserted)
3904                 BNX2X_ERR("IGU ERROR\n");
3905
3906         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3907         aeu_mask = REG_RD(bp, aeu_addr);
3908
3909         DP(NETIF_MSG_HW, "aeu_mask %x  newly asserted %x\n",
3910            aeu_mask, asserted);
3911         aeu_mask &= ~(asserted & 0x3ff);
3912         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3913
3914         REG_WR(bp, aeu_addr, aeu_mask);
3915         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3916
3917         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3918         bp->attn_state |= asserted;
3919         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3920
3921         if (asserted & ATTN_HARD_WIRED_MASK) {
3922                 if (asserted & ATTN_NIG_FOR_FUNC) {
3923
3924                         bnx2x_acquire_phy_lock(bp);
3925
3926                         /* save nig interrupt mask */
3927                         nig_mask = REG_RD(bp, nig_int_mask_addr);
3928
3929                         /* If nig_mask is not set, no need to call the update
3930                          * function.
3931                          */
3932                         if (nig_mask) {
3933                                 REG_WR(bp, nig_int_mask_addr, 0);
3934
3935                                 bnx2x_link_attn(bp);
3936                         }
3937
3938                         /* handle unicore attn? */
3939                 }
3940                 if (asserted & ATTN_SW_TIMER_4_FUNC)
3941                         DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3942
3943                 if (asserted & GPIO_2_FUNC)
3944                         DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3945
3946                 if (asserted & GPIO_3_FUNC)
3947                         DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3948
3949                 if (asserted & GPIO_4_FUNC)
3950                         DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3951
3952                 if (port == 0) {
3953                         if (asserted & ATTN_GENERAL_ATTN_1) {
3954                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3955                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3956                         }
3957                         if (asserted & ATTN_GENERAL_ATTN_2) {
3958                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3959                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3960                         }
3961                         if (asserted & ATTN_GENERAL_ATTN_3) {
3962                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3963                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3964                         }
3965                 } else {
3966                         if (asserted & ATTN_GENERAL_ATTN_4) {
3967                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3968                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3969                         }
3970                         if (asserted & ATTN_GENERAL_ATTN_5) {
3971                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3972                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3973                         }
3974                         if (asserted & ATTN_GENERAL_ATTN_6) {
3975                                 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3976                                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3977                         }
3978                 }
3979
3980         } /* if hardwired */
3981
3982         if (bp->common.int_block == INT_BLOCK_HC)
3983                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3984                             COMMAND_REG_ATTN_BITS_SET);
3985         else
3986                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3987
3988         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3989            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3990         REG_WR(bp, reg_addr, asserted);
3991
3992         /* now set back the mask */
3993         if (asserted & ATTN_NIG_FOR_FUNC) {
3994                 /* Verify that IGU ack through BAR was written before restoring
3995                  * NIG mask. This loop should exit after 2-3 iterations max.
3996                  */
3997                 if (bp->common.int_block != INT_BLOCK_HC) {
3998                         u32 cnt = 0, igu_acked;
3999                         do {
4000                                 igu_acked = REG_RD(bp,
4001                                                    IGU_REG_ATTENTION_ACK_BITS);
4002                         } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
4003                                  (++cnt < MAX_IGU_ATTN_ACK_TO));
4004                         if (!igu_acked)
4005                                 DP(NETIF_MSG_HW,
4006                                    "Failed to verify IGU ack on time\n");
4007                         barrier();
4008                 }
4009                 REG_WR(bp, nig_int_mask_addr, nig_mask);
4010                 bnx2x_release_phy_lock(bp);
4011         }
4012 }
4013
4014 static void bnx2x_fan_failure(struct bnx2x *bp)
4015 {
4016         int port = BP_PORT(bp);
4017         u32 ext_phy_config;
4018         /* mark the failure */
4019         ext_phy_config =
4020                 SHMEM_RD(bp,
4021                          dev_info.port_hw_config[port].external_phy_config);
4022
4023         ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
4024         ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
4025         SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
4026                  ext_phy_config);
4027
4028         /* log the failure */
4029         netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4030                             "Please contact OEM Support for assistance\n");
4031
4032         /* Schedule device reset (unload)
4033          * This is due to some boards consuming sufficient power when driver is
4034          * up to overheat if fan fails.
4035          */
4036         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_FAN_FAILURE, 0);
4037 }
4038
4039 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
4040 {
4041         int port = BP_PORT(bp);
4042         int reg_offset;
4043         u32 val;
4044
4045         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
4046                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
4047
4048         if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
4049
4050                 val = REG_RD(bp, reg_offset);
4051                 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
4052                 REG_WR(bp, reg_offset, val);
4053
4054                 BNX2X_ERR("SPIO5 hw attention\n");
4055
4056                 /* Fan failure attention */
4057                 bnx2x_hw_reset_phy(&bp->link_params);
4058                 bnx2x_fan_failure(bp);
4059         }
4060
4061         if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
4062                 bnx2x_acquire_phy_lock(bp);
4063                 bnx2x_handle_module_detect_int(&bp->link_params);
4064                 bnx2x_release_phy_lock(bp);
4065         }
4066
4067         if (attn & HW_INTERRUT_ASSERT_SET_0) {
4068
4069                 val = REG_RD(bp, reg_offset);
4070                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
4071                 REG_WR(bp, reg_offset, val);
4072
4073                 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4074                           (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
4075                 bnx2x_panic();
4076         }
4077 }
4078
4079 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
4080 {
4081         u32 val;
4082
4083         if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
4084
4085                 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
4086                 BNX2X_ERR("DB hw attention 0x%x\n", val);
4087                 /* DORQ discard attention */
4088                 if (val & 0x2)
4089                         BNX2X_ERR("FATAL error from DORQ\n");
4090         }
4091
4092         if (attn & HW_INTERRUT_ASSERT_SET_1) {
4093
4094                 int port = BP_PORT(bp);
4095                 int reg_offset;
4096
4097                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
4098                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
4099
4100                 val = REG_RD(bp, reg_offset);
4101                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
4102                 REG_WR(bp, reg_offset, val);
4103
4104                 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4105                           (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
4106                 bnx2x_panic();
4107         }
4108 }
4109
4110 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
4111 {
4112         u32 val;
4113
4114         if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
4115
4116                 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
4117                 BNX2X_ERR("CFC hw attention 0x%x\n", val);
4118                 /* CFC error attention */
4119                 if (val & 0x2)
4120                         BNX2X_ERR("FATAL error from CFC\n");
4121         }
4122
4123         if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
4124                 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
4125                 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
4126                 /* RQ_USDMDP_FIFO_OVERFLOW */
4127                 if (val & 0x18000)
4128                         BNX2X_ERR("FATAL error from PXP\n");
4129
4130                 if (!CHIP_IS_E1x(bp)) {
4131                         val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
4132                         BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
4133                 }
4134         }
4135
4136         if (attn & HW_INTERRUT_ASSERT_SET_2) {
4137
4138                 int port = BP_PORT(bp);
4139                 int reg_offset;
4140
4141                 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
4142                                      MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
4143
4144                 val = REG_RD(bp, reg_offset);
4145                 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
4146                 REG_WR(bp, reg_offset, val);
4147
4148                 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4149                           (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
4150                 bnx2x_panic();
4151         }
4152 }
4153
4154 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
4155 {
4156         u32 val;
4157
4158         if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
4159
4160                 if (attn & BNX2X_PMF_LINK_ASSERT) {
4161                         int func = BP_FUNC(bp);
4162
4163                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
4164                         bnx2x_read_mf_cfg(bp);
4165                         bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
4166                                         func_mf_config[BP_ABS_FUNC(bp)].config);
4167                         val = SHMEM_RD(bp,
4168                                        func_mb[BP_FW_MB_IDX(bp)].drv_status);
4169                         if (val & DRV_STATUS_DCC_EVENT_MASK)
4170                                 bnx2x_dcc_event(bp,
4171                                             (val & DRV_STATUS_DCC_EVENT_MASK));
4172
4173                         if (val & DRV_STATUS_SET_MF_BW)
4174                                 bnx2x_set_mf_bw(bp);
4175
4176                         if (val & DRV_STATUS_DRV_INFO_REQ)
4177                                 bnx2x_handle_drv_info_req(bp);
4178
4179                         if (val & DRV_STATUS_VF_DISABLED)
4180                                 bnx2x_schedule_iov_task(bp,
4181                                                         BNX2X_IOV_HANDLE_FLR);
4182
4183                         if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
4184                                 bnx2x_pmf_update(bp);
4185
4186                         if (bp->port.pmf &&
4187                             (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
4188                                 bp->dcbx_enabled > 0)
4189                                 /* start dcbx state machine */
4190                                 bnx2x_dcbx_set_params(bp,
4191                                         BNX2X_DCBX_STATE_NEG_RECEIVED);
4192                         if (val & DRV_STATUS_AFEX_EVENT_MASK)
4193                                 bnx2x_handle_afex_cmd(bp,
4194                                         val & DRV_STATUS_AFEX_EVENT_MASK);
4195                         if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
4196                                 bnx2x_handle_eee_event(bp);
4197                         if (bp->link_vars.periodic_flags &
4198                             PERIODIC_FLAGS_LINK_EVENT) {
4199                                 /*  sync with link */
4200                                 bnx2x_acquire_phy_lock(bp);
4201                                 bp->link_vars.periodic_flags &=
4202                                         ~PERIODIC_FLAGS_LINK_EVENT;
4203                                 bnx2x_release_phy_lock(bp);
4204                                 if (IS_MF(bp))
4205                                         bnx2x_link_sync_notify(bp);
4206                                 bnx2x_link_report(bp);
4207                         }
4208                         /* Always call it here: bnx2x_link_report() will
4209                          * prevent the link indication duplication.
4210                          */
4211                         bnx2x__link_status_update(bp);
4212                 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4213
4214                         BNX2X_ERR("MC assert!\n");
4215                         bnx2x_mc_assert(bp);
4216                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4217                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4218                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4219                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4220                         bnx2x_panic();
4221
4222                 } else if (attn & BNX2X_MCP_ASSERT) {
4223
4224                         BNX2X_ERR("MCP assert!\n");
4225                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4226                         bnx2x_fw_dump(bp);
4227
4228                 } else
4229                         BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4230         }
4231
4232         if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4233                 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4234                 if (attn & BNX2X_GRC_TIMEOUT) {
4235                         val = CHIP_IS_E1(bp) ? 0 :
4236                                         REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4237                         BNX2X_ERR("GRC time-out 0x%08x\n", val);
4238                 }
4239                 if (attn & BNX2X_GRC_RSV) {
4240                         val = CHIP_IS_E1(bp) ? 0 :
4241                                         REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4242                         BNX2X_ERR("GRC reserved 0x%08x\n", val);
4243                 }
4244                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4245         }
4246 }
4247
4248 /*
4249  * Bits map:
4250  * 0-7   - Engine0 load counter.
4251  * 8-15  - Engine1 load counter.
4252  * 16    - Engine0 RESET_IN_PROGRESS bit.
4253  * 17    - Engine1 RESET_IN_PROGRESS bit.
4254  * 18    - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4255  *         on the engine
4256  * 19    - Engine1 ONE_IS_LOADED.
4257  * 20    - Chip reset flow bit. When set none-leader must wait for both engines
4258  *         leader to complete (check for both RESET_IN_PROGRESS bits and not for
4259  *         just the one belonging to its engine).
4260  *
4261  */
4262 #define BNX2X_RECOVERY_GLOB_REG         MISC_REG_GENERIC_POR_1
4263
4264 #define BNX2X_PATH0_LOAD_CNT_MASK       0x000000ff
4265 #define BNX2X_PATH0_LOAD_CNT_SHIFT      0
4266 #define BNX2X_PATH1_LOAD_CNT_MASK       0x0000ff00
4267 #define BNX2X_PATH1_LOAD_CNT_SHIFT      8
4268 #define BNX2X_PATH0_RST_IN_PROG_BIT     0x00010000
4269 #define BNX2X_PATH1_RST_IN_PROG_BIT     0x00020000
4270 #define BNX2X_GLOBAL_RESET_BIT          0x00040000
4271
4272 /*
4273  * Set the GLOBAL_RESET bit.
4274  *
4275  * Should be run under rtnl lock
4276  */
4277 void bnx2x_set_reset_global(struct bnx2x *bp)
4278 {
4279         u32 val;
4280         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4281         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4282         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4283         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4284 }
4285
4286 /*
4287  * Clear the GLOBAL_RESET bit.
4288  *
4289  * Should be run under rtnl lock
4290  */
4291 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4292 {
4293         u32 val;
4294         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4295         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4296         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4297         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4298 }
4299
4300 /*
4301  * Checks the GLOBAL_RESET bit.
4302  *
4303  * should be run under rtnl lock
4304  */
4305 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4306 {
4307         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4308
4309         DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4310         return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4311 }
4312
4313 /*
4314  * Clear RESET_IN_PROGRESS bit for the current engine.
4315  *
4316  * Should be run under rtnl lock
4317  */
4318 static void bnx2x_set_reset_done(struct bnx2x *bp)
4319 {
4320         u32 val;
4321         u32 bit = BP_PATH(bp) ?
4322                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4323         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4324         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4325
4326         /* Clear the bit */
4327         val &= ~bit;
4328         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4329
4330         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4331 }
4332
4333 /*
4334  * Set RESET_IN_PROGRESS for the current engine.
4335  *
4336  * should be run under rtnl lock
4337  */
4338 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4339 {
4340         u32 val;
4341         u32 bit = BP_PATH(bp) ?
4342                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4343         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4344         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4345
4346         /* Set the bit */
4347         val |= bit;
4348         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4349         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4350 }
4351
4352 /*
4353  * Checks the RESET_IN_PROGRESS bit for the given engine.
4354  * should be run under rtnl lock
4355  */
4356 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4357 {
4358         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4359         u32 bit = engine ?
4360                 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4361
4362         /* return false if bit is set */
4363         return (val & bit) ? false : true;
4364 }
4365
4366 /*
4367  * set pf load for the current pf.
4368  *
4369  * should be run under rtnl lock
4370  */
4371 void bnx2x_set_pf_load(struct bnx2x *bp)
4372 {
4373         u32 val1, val;
4374         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4375                              BNX2X_PATH0_LOAD_CNT_MASK;
4376         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4377                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4378
4379         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4380         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4381
4382         DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4383
4384         /* get the current counter value */
4385         val1 = (val & mask) >> shift;
4386
4387         /* set bit of that PF */
4388         val1 |= (1 << bp->pf_num);
4389
4390         /* clear the old value */
4391         val &= ~mask;
4392
4393         /* set the new one */
4394         val |= ((val1 << shift) & mask);
4395
4396         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4397         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4398 }
4399
4400 /**
4401  * bnx2x_clear_pf_load - clear pf load mark
4402  *
4403  * @bp:         driver handle
4404  *
4405  * Should be run under rtnl lock.
4406  * Decrements the load counter for the current engine. Returns
4407  * whether other functions are still loaded
4408  */
4409 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4410 {
4411         u32 val1, val;
4412         u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4413                              BNX2X_PATH0_LOAD_CNT_MASK;
4414         u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4415                              BNX2X_PATH0_LOAD_CNT_SHIFT;
4416
4417         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4418         val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4419         DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4420
4421         /* get the current counter value */
4422         val1 = (val & mask) >> shift;
4423
4424         /* clear bit of that PF */
4425         val1 &= ~(1 << bp->pf_num);
4426
4427         /* clear the old value */
4428         val &= ~mask;
4429
4430         /* set the new one */
4431         val |= ((val1 << shift) & mask);
4432
4433         REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4434         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4435         return val1 != 0;
4436 }
4437
4438 /*
4439  * Read the load status for the current engine.
4440  *
4441  * should be run under rtnl lock
4442  */
4443 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4444 {
4445         u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4446                              BNX2X_PATH0_LOAD_CNT_MASK);
4447         u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4448                              BNX2X_PATH0_LOAD_CNT_SHIFT);
4449         u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4450
4451         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4452
4453         val = (val & mask) >> shift;
4454
4455         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4456            engine, val);
4457
4458         return val != 0;
4459 }
4460
4461 static void _print_parity(struct bnx2x *bp, u32 reg)
4462 {
4463         pr_cont(" [0x%08x] ", REG_RD(bp, reg));
4464 }
4465
4466 static void _print_next_block(int idx, const char *blk)
4467 {
4468         pr_cont("%s%s", idx ? ", " : "", blk);
4469 }
4470
4471 static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
4472                                             int *par_num, bool print)
4473 {
4474         u32 cur_bit;
4475         bool res;
4476         int i;
4477
4478         res = false;
4479
4480         for (i = 0; sig; i++) {
4481                 cur_bit = (0x1UL << i);
4482                 if (sig & cur_bit) {
4483                         res |= true; /* Each bit is real error! */
4484
4485                         if (print) {
4486                                 switch (cur_bit) {
4487                                 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4488                                         _print_next_block((*par_num)++, "BRB");
4489                                         _print_parity(bp,
4490                                                       BRB1_REG_BRB1_PRTY_STS);
4491                                         break;
4492                                 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4493                                         _print_next_block((*par_num)++,
4494                                                           "PARSER");
4495                                         _print_parity(bp, PRS_REG_PRS_PRTY_STS);
4496                                         break;
4497                                 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4498                                         _print_next_block((*par_num)++, "TSDM");
4499                                         _print_parity(bp,
4500                                                       TSDM_REG_TSDM_PRTY_STS);
4501                                         break;
4502                                 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4503                                         _print_next_block((*par_num)++,
4504                                                           "SEARCHER");
4505                                         _print_parity(bp, SRC_REG_SRC_PRTY_STS);
4506                                         break;
4507                                 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4508                                         _print_next_block((*par_num)++, "TCM");
4509                                         _print_parity(bp, TCM_REG_TCM_PRTY_STS);
4510                                         break;
4511                                 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4512                                         _print_next_block((*par_num)++,
4513                                                           "TSEMI");
4514                                         _print_parity(bp,
4515                                                       TSEM_REG_TSEM_PRTY_STS_0);
4516                                         _print_parity(bp,
4517                                                       TSEM_REG_TSEM_PRTY_STS_1);
4518                                         break;
4519                                 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4520                                         _print_next_block((*par_num)++, "XPB");
4521                                         _print_parity(bp, GRCBASE_XPB +
4522                                                           PB_REG_PB_PRTY_STS);
4523                                         break;
4524                                 }
4525                         }
4526
4527                         /* Clear the bit */
4528                         sig &= ~cur_bit;
4529                 }
4530         }
4531
4532         return res;
4533 }
4534
4535 static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
4536                                             int *par_num, bool *global,
4537                                             bool print)
4538 {
4539         u32 cur_bit;
4540         bool res;
4541         int i;
4542
4543         res = false;
4544
4545         for (i = 0; sig; i++) {
4546                 cur_bit = (0x1UL << i);
4547                 if (sig & cur_bit) {
4548                         res |= true; /* Each bit is real error! */
4549                         switch (cur_bit) {
4550                         case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4551                                 if (print) {
4552                                         _print_next_block((*par_num)++, "PBF");
4553                                         _print_parity(bp, PBF_REG_PBF_PRTY_STS);
4554                                 }
4555                                 break;
4556                         case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4557                                 if (print) {
4558                                         _print_next_block((*par_num)++, "QM");
4559                                         _print_parity(bp, QM_REG_QM_PRTY_STS);
4560                                 }
4561                                 break;
4562                         case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4563                                 if (print) {
4564                                         _print_next_block((*par_num)++, "TM");
4565                                         _print_parity(bp, TM_REG_TM_PRTY_STS);
4566                                 }
4567                                 break;
4568                         case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4569                                 if (print) {
4570                                         _print_next_block((*par_num)++, "XSDM");
4571                                         _print_parity(bp,
4572                                                       XSDM_REG_XSDM_PRTY_STS);
4573                                 }
4574                                 break;
4575                         case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4576                                 if (print) {
4577                                         _print_next_block((*par_num)++, "XCM");
4578                                         _print_parity(bp, XCM_REG_XCM_PRTY_STS);
4579                                 }
4580                                 break;
4581                         case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4582                                 if (print) {
4583                                         _print_next_block((*par_num)++,
4584                                                           "XSEMI");
4585                                         _print_parity(bp,
4586                                                       XSEM_REG_XSEM_PRTY_STS_0);
4587                                         _print_parity(bp,
4588                                                       XSEM_REG_XSEM_PRTY_STS_1);
4589                                 }
4590                                 break;
4591                         case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4592                                 if (print) {
4593                                         _print_next_block((*par_num)++,
4594                                                           "DOORBELLQ");
4595                                         _print_parity(bp,
4596                                                       DORQ_REG_DORQ_PRTY_STS);
4597                                 }
4598                                 break;
4599                         case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4600                                 if (print) {
4601                                         _print_next_block((*par_num)++, "NIG");
4602                                         if (CHIP_IS_E1x(bp)) {
4603                                                 _print_parity(bp,
4604                                                         NIG_REG_NIG_PRTY_STS);
4605                                         } else {
4606                                                 _print_parity(bp,
4607                                                         NIG_REG_NIG_PRTY_STS_0);
4608                                                 _print_parity(bp,
4609                                                         NIG_REG_NIG_PRTY_STS_1);
4610                                         }
4611                                 }
4612                                 break;
4613                         case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4614                                 if (print)
4615                                         _print_next_block((*par_num)++,
4616                                                           "VAUX PCI CORE");
4617                                 *global = true;
4618                                 break;
4619                         case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4620                                 if (print) {
4621                                         _print_next_block((*par_num)++,
4622                                                           "DEBUG");
4623                                         _print_parity(bp, DBG_REG_DBG_PRTY_STS);
4624                                 }
4625                                 break;
4626                         case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4627                                 if (print) {
4628                                         _print_next_block((*par_num)++, "USDM");
4629                                         _print_parity(bp,
4630                                                       USDM_REG_USDM_PRTY_STS);
4631                                 }
4632                                 break;
4633                         case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4634                                 if (print) {
4635                                         _print_next_block((*par_num)++, "UCM");
4636                                         _print_parity(bp, UCM_REG_UCM_PRTY_STS);
4637                                 }
4638                                 break;
4639                         case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4640                                 if (print) {
4641                                         _print_next_block((*par_num)++,
4642                                                           "USEMI");
4643                                         _print_parity(bp,
4644                                                       USEM_REG_USEM_PRTY_STS_0);
4645                                         _print_parity(bp,
4646                                                       USEM_REG_USEM_PRTY_STS_1);
4647                                 }
4648                                 break;
4649                         case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4650                                 if (print) {
4651                                         _print_next_block((*par_num)++, "UPB");
4652                                         _print_parity(bp, GRCBASE_UPB +
4653                                                           PB_REG_PB_PRTY_STS);
4654                                 }
4655                                 break;
4656                         case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4657                                 if (print) {
4658                                         _print_next_block((*par_num)++, "CSDM");
4659                                         _print_parity(bp,
4660                                                       CSDM_REG_CSDM_PRTY_STS);
4661                                 }
4662                                 break;
4663                         case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4664                                 if (print) {
4665                                         _print_next_block((*par_num)++, "CCM");
4666                                         _print_parity(bp, CCM_REG_CCM_PRTY_STS);
4667                                 }
4668                                 break;
4669                         }
4670
4671                         /* Clear the bit */
4672                         sig &= ~cur_bit;
4673                 }
4674         }
4675
4676         return res;
4677 }
4678
4679 static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
4680                                             int *par_num, bool print)
4681 {
4682         u32 cur_bit;
4683         bool res;
4684         int i;
4685
4686         res = false;
4687
4688         for (i = 0; sig; i++) {
4689                 cur_bit = (0x1UL << i);
4690                 if (sig & cur_bit) {
4691                         res = true; /* Each bit is real error! */
4692                         if (print) {
4693                                 switch (cur_bit) {
4694                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4695                                         _print_next_block((*par_num)++,
4696                                                           "CSEMI");
4697                                         _print_parity(bp,
4698                                                       CSEM_REG_CSEM_PRTY_STS_0);
4699                                         _print_parity(bp,
4700                                                       CSEM_REG_CSEM_PRTY_STS_1);
4701                                         break;
4702                                 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4703                                         _print_next_block((*par_num)++, "PXP");
4704                                         _print_parity(bp, PXP_REG_PXP_PRTY_STS);
4705                                         _print_parity(bp,
4706                                                       PXP2_REG_PXP2_PRTY_STS_0);
4707                                         _print_parity(bp,
4708                                                       PXP2_REG_PXP2_PRTY_STS_1);
4709                                         break;
4710                                 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4711                                         _print_next_block((*par_num)++,
4712                                                           "PXPPCICLOCKCLIENT");
4713                                         break;
4714                                 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4715                                         _print_next_block((*par_num)++, "CFC");
4716                                         _print_parity(bp,
4717                                                       CFC_REG_CFC_PRTY_STS);
4718                                         break;
4719                                 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4720                                         _print_next_block((*par_num)++, "CDU");
4721                                         _print_parity(bp, CDU_REG_CDU_PRTY_STS);
4722                                         break;
4723                                 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4724                                         _print_next_block((*par_num)++, "DMAE");
4725                                         _print_parity(bp,
4726                                                       DMAE_REG_DMAE_PRTY_STS);
4727                                         break;
4728                                 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4729                                         _print_next_block((*par_num)++, "IGU");
4730                                         if (CHIP_IS_E1x(bp))
4731                                                 _print_parity(bp,
4732                                                         HC_REG_HC_PRTY_STS);
4733                                         else
4734                                                 _print_parity(bp,
4735                                                         IGU_REG_IGU_PRTY_STS);
4736                                         break;
4737                                 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4738                                         _print_next_block((*par_num)++, "MISC");
4739                                         _print_parity(bp,
4740                                                       MISC_REG_MISC_PRTY_STS);
4741                                         break;
4742                                 }
4743                         }
4744
4745                         /* Clear the bit */
4746                         sig &= ~cur_bit;
4747                 }
4748         }
4749
4750         return res;
4751 }
4752
4753 static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
4754                                             int *par_num, bool *global,
4755                                             bool print)
4756 {
4757         bool res = false;
4758         u32 cur_bit;
4759         int i;
4760
4761         for (i = 0; sig; i++) {
4762                 cur_bit = (0x1UL << i);
4763                 if (sig & cur_bit) {
4764                         switch (cur_bit) {
4765                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4766                                 if (print)
4767                                         _print_next_block((*par_num)++,
4768                                                           "MCP ROM");
4769                                 *global = true;
4770                                 res = true;
4771                                 break;
4772                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4773                                 if (print)
4774                                         _print_next_block((*par_num)++,
4775                                                           "MCP UMP RX");
4776                                 *global = true;
4777                                 res = true;
4778                                 break;
4779                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4780                                 if (print)
4781                                         _print_next_block((*par_num)++,
4782                                                           "MCP UMP TX");
4783                                 *global = true;
4784                                 res = true;
4785                                 break;
4786                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4787                                 if (print)
4788                                         _print_next_block((*par_num)++,
4789                                                           "MCP SCPAD");
4790                                 /* clear latched SCPAD PATIRY from MCP */
4791                                 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
4792                                        1UL << 10);
4793                                 break;
4794                         }
4795
4796                         /* Clear the bit */
4797                         sig &= ~cur_bit;
4798                 }
4799         }
4800
4801         return res;
4802 }
4803
4804 static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
4805                                             int *par_num, bool print)
4806 {
4807         u32 cur_bit;
4808         bool res;
4809         int i;
4810
4811         res = false;
4812
4813         for (i = 0; sig; i++) {
4814                 cur_bit = (0x1UL << i);
4815                 if (sig & cur_bit) {
4816                         res = true; /* Each bit is real error! */
4817                         if (print) {
4818                                 switch (cur_bit) {
4819                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4820                                         _print_next_block((*par_num)++,
4821                                                           "PGLUE_B");
4822                                         _print_parity(bp,
4823                                                       PGLUE_B_REG_PGLUE_B_PRTY_STS);
4824                                         break;
4825                                 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4826                                         _print_next_block((*par_num)++, "ATC");
4827                                         _print_parity(bp,
4828                                                       ATC_REG_ATC_PRTY_STS);
4829                                         break;
4830                                 }
4831                         }
4832                         /* Clear the bit */
4833                         sig &= ~cur_bit;
4834                 }
4835         }
4836
4837         return res;
4838 }
4839
4840 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4841                               u32 *sig)
4842 {
4843         bool res = false;
4844
4845         if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4846             (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4847             (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4848             (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4849             (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4850                 int par_num = 0;
4851                 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4852                                  "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4853                           sig[0] & HW_PRTY_ASSERT_SET_0,
4854                           sig[1] & HW_PRTY_ASSERT_SET_1,
4855                           sig[2] & HW_PRTY_ASSERT_SET_2,
4856                           sig[3] & HW_PRTY_ASSERT_SET_3,
4857                           sig[4] & HW_PRTY_ASSERT_SET_4);
4858                 if (print)
4859                         netdev_err(bp->dev,
4860                                    "Parity errors detected in blocks: ");
4861                 res |= bnx2x_check_blocks_with_parity0(bp,
4862                         sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
4863                 res |= bnx2x_check_blocks_with_parity1(bp,
4864                         sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
4865                 res |= bnx2x_check_blocks_with_parity2(bp,
4866                         sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
4867                 res |= bnx2x_check_blocks_with_parity3(bp,
4868                         sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
4869                 res |= bnx2x_check_blocks_with_parity4(bp,
4870                         sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
4871
4872                 if (print)
4873                         pr_cont("\n");
4874         }
4875
4876         return res;
4877 }
4878
4879 /**
4880  * bnx2x_chk_parity_attn - checks for parity attentions.
4881  *
4882  * @bp:         driver handle
4883  * @global:     true if there was a global attention
4884  * @print:      show parity attention in syslog
4885  */
4886 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4887 {
4888         struct attn_route attn = { {0} };
4889         int port = BP_PORT(bp);
4890
4891         attn.sig[0] = REG_RD(bp,
4892                 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4893                              port*4);
4894         attn.sig[1] = REG_RD(bp,
4895                 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4896                              port*4);
4897         attn.sig[2] = REG_RD(bp,
4898                 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4899                              port*4);
4900         attn.sig[3] = REG_RD(bp,
4901                 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4902                              port*4);
4903         /* Since MCP attentions can't be disabled inside the block, we need to
4904          * read AEU registers to see whether they're currently disabled
4905          */
4906         attn.sig[3] &= ((REG_RD(bp,
4907                                 !port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
4908                                       : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
4909                          MISC_AEU_ENABLE_MCP_PRTY_BITS) |
4910                         ~MISC_AEU_ENABLE_MCP_PRTY_BITS);
4911
4912         if (!CHIP_IS_E1x(bp))
4913                 attn.sig[4] = REG_RD(bp,
4914                         MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4915                                      port*4);
4916
4917         return bnx2x_parity_attn(bp, global, print, attn.sig);
4918 }
4919
4920 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4921 {
4922         u32 val;
4923         if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4924
4925                 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4926                 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4927                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4928                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4929                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4930                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4931                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4932                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4933                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4934                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4935                 if (val &
4936                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4937                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4938                 if (val &
4939                     PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4940                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4941                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4942                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4943                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4944                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4945                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4946                         BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4947         }
4948         if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4949                 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4950                 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4951                 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4952                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4953                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4954                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4955                 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4956                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4957                 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4958                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4959                 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4960                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4961                 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4962                         BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4963         }
4964
4965         if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4966                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4967                 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4968                 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4969                     AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4970         }
4971 }
4972
4973 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4974 {
4975         struct attn_route attn, *group_mask;
4976         int port = BP_PORT(bp);
4977         int index;
4978         u32 reg_addr;
4979         u32 val;
4980         u32 aeu_mask;
4981         bool global = false;
4982
4983         /* need to take HW lock because MCP or other port might also
4984            try to handle this event */
4985         bnx2x_acquire_alr(bp);
4986
4987         if (bnx2x_chk_parity_attn(bp, &global, true)) {
4988 #ifndef BNX2X_STOP_ON_ERROR
4989                 bp->recovery_state = BNX2X_RECOVERY_INIT;
4990                 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4991                 /* Disable HW interrupts */
4992                 bnx2x_int_disable(bp);
4993                 /* In case of parity errors don't handle attentions so that
4994                  * other function would "see" parity errors.
4995                  */
4996 #else
4997                 bnx2x_panic();
4998 #endif
4999                 bnx2x_release_alr(bp);
5000                 return;
5001         }
5002
5003         attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
5004         attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
5005         attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
5006         attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
5007         if (!CHIP_IS_E1x(bp))
5008                 attn.sig[4] =
5009                       REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
5010         else
5011                 attn.sig[4] = 0;
5012
5013         DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
5014            attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
5015
5016         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5017                 if (deasserted & (1 << index)) {
5018                         group_mask = &bp->attn_group[index];
5019
5020                         DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
5021                            index,
5022                            group_mask->sig[0], group_mask->sig[1],
5023                            group_mask->sig[2], group_mask->sig[3],
5024                            group_mask->sig[4]);
5025
5026                         bnx2x_attn_int_deasserted4(bp,
5027                                         attn.sig[4] & group_mask->sig[4]);
5028                         bnx2x_attn_int_deasserted3(bp,
5029                                         attn.sig[3] & group_mask->sig[3]);
5030                         bnx2x_attn_int_deasserted1(bp,
5031                                         attn.sig[1] & group_mask->sig[1]);
5032                         bnx2x_attn_int_deasserted2(bp,
5033                                         attn.sig[2] & group_mask->sig[2]);
5034                         bnx2x_attn_int_deasserted0(bp,
5035                                         attn.sig[0] & group_mask->sig[0]);
5036                 }
5037         }
5038
5039         bnx2x_release_alr(bp);
5040
5041         if (bp->common.int_block == INT_BLOCK_HC)
5042                 reg_addr = (HC_REG_COMMAND_REG + port*32 +
5043                             COMMAND_REG_ATTN_BITS_CLR);
5044         else
5045                 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
5046
5047         val = ~deasserted;
5048         DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
5049            (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
5050         REG_WR(bp, reg_addr, val);
5051
5052         if (~bp->attn_state & deasserted)
5053                 BNX2X_ERR("IGU ERROR\n");
5054
5055         reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
5056                           MISC_REG_AEU_MASK_ATTN_FUNC_0;
5057
5058         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5059         aeu_mask = REG_RD(bp, reg_addr);
5060
5061         DP(NETIF_MSG_HW, "aeu_mask %x  newly deasserted %x\n",
5062            aeu_mask, deasserted);
5063         aeu_mask |= (deasserted & 0x3ff);
5064         DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
5065
5066         REG_WR(bp, reg_addr, aeu_mask);
5067         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
5068
5069         DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
5070         bp->attn_state &= ~deasserted;
5071         DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
5072 }
5073
5074 static void bnx2x_attn_int(struct bnx2x *bp)
5075 {
5076         /* read local copy of bits */
5077         u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
5078                                                                 attn_bits);
5079         u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
5080                                                                 attn_bits_ack);
5081         u32 attn_state = bp->attn_state;
5082
5083         /* look for changed bits */
5084         u32 asserted   =  attn_bits & ~attn_ack & ~attn_state;
5085         u32 deasserted = ~attn_bits &  attn_ack &  attn_state;
5086
5087         DP(NETIF_MSG_HW,
5088            "attn_bits %x  attn_ack %x  asserted %x  deasserted %x\n",
5089            attn_bits, attn_ack, asserted, deasserted);
5090
5091         if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
5092                 BNX2X_ERR("BAD attention state\n");
5093
5094         /* handle bits that were raised */
5095         if (asserted)
5096                 bnx2x_attn_int_asserted(bp, asserted);
5097
5098         if (deasserted)
5099                 bnx2x_attn_int_deasserted(bp, deasserted);
5100 }
5101
5102 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
5103                       u16 index, u8 op, u8 update)
5104 {
5105         u32 igu_addr = bp->igu_base_addr;
5106         igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
5107         bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
5108                              igu_addr);
5109 }
5110
5111 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
5112 {
5113         /* No memory barriers */
5114         storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
5115         mmiowb(); /* keep prod updates ordered */
5116 }
5117
5118 static int  bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
5119                                       union event_ring_elem *elem)
5120 {
5121         u8 err = elem->message.error;
5122
5123         if (!bp->cnic_eth_dev.starting_cid  ||
5124             (cid < bp->cnic_eth_dev.starting_cid &&
5125             cid != bp->cnic_eth_dev.iscsi_l2_cid))
5126                 return 1;
5127
5128         DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
5129
5130         if (unlikely(err)) {
5131
5132                 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5133                           cid);
5134                 bnx2x_panic_dump(bp, false);
5135         }
5136         bnx2x_cnic_cfc_comp(bp, cid, err);
5137         return 0;
5138 }
5139
5140 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
5141 {
5142         struct bnx2x_mcast_ramrod_params rparam;
5143         int rc;
5144
5145         memset(&rparam, 0, sizeof(rparam));
5146
5147         rparam.mcast_obj = &bp->mcast_obj;
5148
5149         netif_addr_lock_bh(bp->dev);
5150
5151         /* Clear pending state for the last command */
5152         bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
5153
5154         /* If there are pending mcast commands - send them */
5155         if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
5156                 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
5157                 if (rc < 0)
5158                         BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5159                                   rc);
5160         }
5161
5162         netif_addr_unlock_bh(bp->dev);
5163 }
5164
5165 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
5166                                             union event_ring_elem *elem)
5167 {
5168         unsigned long ramrod_flags = 0;
5169         int rc = 0;
5170         u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
5171         struct bnx2x_vlan_mac_obj *vlan_mac_obj;
5172
5173         /* Always push next commands out, don't wait here */
5174         __set_bit(RAMROD_CONT, &ramrod_flags);
5175
5176         switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
5177                             >> BNX2X_SWCID_SHIFT) {
5178         case BNX2X_FILTER_MAC_PENDING:
5179                 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
5180                 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
5181                         vlan_mac_obj = &bp->iscsi_l2_mac_obj;
5182                 else
5183                         vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
5184
5185                 break;
5186         case BNX2X_FILTER_MCAST_PENDING:
5187                 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
5188                 /* This is only relevant for 57710 where multicast MACs are
5189                  * configured as unicast MACs using the same ramrod.
5190                  */
5191                 bnx2x_handle_mcast_eqe(bp);
5192                 return;
5193         default:
5194                 BNX2X_ERR("Unsupported classification command: %d\n",
5195                           elem->message.data.eth_event.echo);
5196                 return;
5197         }
5198
5199         rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
5200
5201         if (rc < 0)
5202                 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
5203         else if (rc > 0)
5204                 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
5205 }
5206
5207 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
5208
5209 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
5210 {
5211         netif_addr_lock_bh(bp->dev);
5212
5213         clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5214
5215         /* Send rx_mode command again if was requested */
5216         if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
5217                 bnx2x_set_storm_rx_mode(bp);
5218         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
5219                                     &bp->sp_state))
5220                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
5221         else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
5222                                     &bp->sp_state))
5223                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
5224
5225         netif_addr_unlock_bh(bp->dev);
5226 }
5227
5228 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
5229                                               union event_ring_elem *elem)
5230 {
5231         if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
5232                 DP(BNX2X_MSG_SP,
5233                    "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5234                    elem->message.data.vif_list_event.func_bit_map);
5235                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
5236                         elem->message.data.vif_list_event.func_bit_map);
5237         } else if (elem->message.data.vif_list_event.echo ==
5238                    VIF_LIST_RULE_SET) {
5239                 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
5240                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
5241         }
5242 }
5243
5244 /* called with rtnl_lock */
5245 static void bnx2x_after_function_update(struct bnx2x *bp)
5246 {
5247         int q, rc;
5248         struct bnx2x_fastpath *fp;
5249         struct bnx2x_queue_state_params queue_params = {NULL};
5250         struct bnx2x_queue_update_params *q_update_params =
5251                 &queue_params.params.update;
5252
5253         /* Send Q update command with afex vlan removal values for all Qs */
5254         queue_params.cmd = BNX2X_Q_CMD_UPDATE;
5255
5256         /* set silent vlan removal values according to vlan mode */
5257         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5258                   &q_update_params->update_flags);
5259         __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
5260                   &q_update_params->update_flags);
5261         __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5262
5263         /* in access mode mark mask and value are 0 to strip all vlans */
5264         if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
5265                 q_update_params->silent_removal_value = 0;
5266                 q_update_params->silent_removal_mask = 0;
5267         } else {
5268                 q_update_params->silent_removal_value =
5269                         (bp->afex_def_vlan_tag & VLAN_VID_MASK);
5270                 q_update_params->silent_removal_mask = VLAN_VID_MASK;
5271         }
5272
5273         for_each_eth_queue(bp, q) {
5274                 /* Set the appropriate Queue object */
5275                 fp = &bp->fp[q];
5276                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5277
5278                 /* send the ramrod */
5279                 rc = bnx2x_queue_state_change(bp, &queue_params);
5280                 if (rc < 0)
5281                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5282                                   q);
5283         }
5284
5285         if (!NO_FCOE(bp) && CNIC_ENABLED(bp)) {
5286                 fp = &bp->fp[FCOE_IDX(bp)];
5287                 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
5288
5289                 /* clear pending completion bit */
5290                 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
5291
5292                 /* mark latest Q bit */
5293                 smp_mb__before_atomic();
5294                 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
5295                 smp_mb__after_atomic();
5296
5297                 /* send Q update ramrod for FCoE Q */
5298                 rc = bnx2x_queue_state_change(bp, &queue_params);
5299                 if (rc < 0)
5300                         BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5301                                   q);
5302         } else {
5303                 /* If no FCoE ring - ACK MCP now */
5304                 bnx2x_link_report(bp);
5305                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5306         }
5307 }
5308
5309 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
5310         struct bnx2x *bp, u32 cid)
5311 {
5312         DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
5313
5314         if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
5315                 return &bnx2x_fcoe_sp_obj(bp, q_obj);
5316         else
5317                 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
5318 }
5319
5320 static void bnx2x_eq_int(struct bnx2x *bp)
5321 {
5322         u16 hw_cons, sw_cons, sw_prod;
5323         union event_ring_elem *elem;
5324         u8 echo;
5325         u32 cid;
5326         u8 opcode;
5327         int rc, spqe_cnt = 0;
5328         struct bnx2x_queue_sp_obj *q_obj;
5329         struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5330         struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5331
5332         hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5333
5334         /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5335          * when we get the next-page we need to adjust so the loop
5336          * condition below will be met. The next element is the size of a
5337          * regular element and hence incrementing by 1
5338          */
5339         if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5340                 hw_cons++;
5341
5342         /* This function may never run in parallel with itself for a
5343          * specific bp, thus there is no need in "paired" read memory
5344          * barrier here.
5345          */
5346         sw_cons = bp->eq_cons;
5347         sw_prod = bp->eq_prod;
5348
5349         DP(BNX2X_MSG_SP, "EQ:  hw_cons %u  sw_cons %u bp->eq_spq_left %x\n",
5350                         hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5351
5352         for (; sw_cons != hw_cons;
5353               sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5354
5355                 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5356
5357                 rc = bnx2x_iov_eq_sp_event(bp, elem);
5358                 if (!rc) {
5359                         DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5360                            rc);
5361                         goto next_spqe;
5362                 }
5363
5364                 /* elem CID originates from FW; actually LE */
5365                 cid = SW_CID((__force __le32)
5366                              elem->message.data.cfc_del_event.cid);
5367                 opcode = elem->message.opcode;
5368
5369                 /* handle eq element */
5370                 switch (opcode) {
5371                 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5372                         bnx2x_vf_mbx_schedule(bp,
5373                                               &elem->message.data.vf_pf_event);
5374                         continue;
5375
5376                 case EVENT_RING_OPCODE_STAT_QUERY:
5377                         DP_AND((BNX2X_MSG_SP | BNX2X_MSG_STATS),
5378                                "got statistics comp event %d\n",
5379                                bp->stats_comp++);
5380                         /* nothing to do with stats comp */
5381                         goto next_spqe;
5382
5383                 case EVENT_RING_OPCODE_CFC_DEL:
5384                         /* handle according to cid range */
5385                         /*
5386                          * we may want to verify here that the bp state is
5387                          * HALTING
5388                          */
5389                         DP(BNX2X_MSG_SP,
5390                            "got delete ramrod for MULTI[%d]\n", cid);
5391
5392                         if (CNIC_LOADED(bp) &&
5393                             !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5394                                 goto next_spqe;
5395
5396                         q_obj = bnx2x_cid_to_q_obj(bp, cid);
5397
5398                         if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5399                                 break;
5400
5401                         goto next_spqe;
5402
5403                 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5404                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5405                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5406                         if (f_obj->complete_cmd(bp, f_obj,
5407                                                 BNX2X_F_CMD_TX_STOP))
5408                                 break;
5409                         goto next_spqe;
5410
5411                 case EVENT_RING_OPCODE_START_TRAFFIC:
5412                         DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5413                         bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5414                         if (f_obj->complete_cmd(bp, f_obj,
5415                                                 BNX2X_F_CMD_TX_START))
5416                                 break;
5417                         goto next_spqe;
5418
5419                 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5420                         echo = elem->message.data.function_update_event.echo;
5421                         if (echo == SWITCH_UPDATE) {
5422                                 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5423                                    "got FUNC_SWITCH_UPDATE ramrod\n");
5424                                 if (f_obj->complete_cmd(
5425                                         bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5426                                         break;
5427
5428                         } else {
5429                                 int cmd = BNX2X_SP_RTNL_AFEX_F_UPDATE;
5430
5431                                 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5432                                    "AFEX: ramrod completed FUNCTION_UPDATE\n");
5433                                 f_obj->complete_cmd(bp, f_obj,
5434                                                     BNX2X_F_CMD_AFEX_UPDATE);
5435
5436                                 /* We will perform the Queues update from
5437                                  * sp_rtnl task as all Queue SP operations
5438                                  * should run under rtnl_lock.
5439                                  */
5440                                 bnx2x_schedule_sp_rtnl(bp, cmd, 0);
5441                         }
5442
5443                         goto next_spqe;
5444
5445                 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5446                         f_obj->complete_cmd(bp, f_obj,
5447                                             BNX2X_F_CMD_AFEX_VIFLISTS);
5448                         bnx2x_after_afex_vif_lists(bp, elem);
5449                         goto next_spqe;
5450                 case EVENT_RING_OPCODE_FUNCTION_START:
5451                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5452                            "got FUNC_START ramrod\n");
5453                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5454                                 break;
5455
5456                         goto next_spqe;
5457
5458                 case EVENT_RING_OPCODE_FUNCTION_STOP:
5459                         DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5460                            "got FUNC_STOP ramrod\n");
5461                         if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5462                                 break;
5463
5464                         goto next_spqe;
5465
5466                 case EVENT_RING_OPCODE_SET_TIMESYNC:
5467                         DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
5468                            "got set_timesync ramrod completion\n");
5469                         if (f_obj->complete_cmd(bp, f_obj,
5470                                                 BNX2X_F_CMD_SET_TIMESYNC))
5471                                 break;
5472                         goto next_spqe;
5473                 }
5474
5475                 switch (opcode | bp->state) {
5476                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5477                       BNX2X_STATE_OPEN):
5478                 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5479                       BNX2X_STATE_OPENING_WAIT4_PORT):
5480                         cid = elem->message.data.eth_event.echo &
5481                                 BNX2X_SWCID_MASK;
5482                         DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5483                            cid);
5484                         rss_raw->clear_pending(rss_raw);
5485                         break;
5486
5487                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5488                 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5489                 case (EVENT_RING_OPCODE_SET_MAC |
5490                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5491                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5492                       BNX2X_STATE_OPEN):
5493                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5494                       BNX2X_STATE_DIAG):
5495                 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5496                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5497                         DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5498                         bnx2x_handle_classification_eqe(bp, elem);
5499                         break;
5500
5501                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5502                       BNX2X_STATE_OPEN):
5503                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5504                       BNX2X_STATE_DIAG):
5505                 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5506                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5507                         DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5508                         bnx2x_handle_mcast_eqe(bp);
5509                         break;
5510
5511                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5512                       BNX2X_STATE_OPEN):
5513                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5514                       BNX2X_STATE_DIAG):
5515                 case (EVENT_RING_OPCODE_FILTERS_RULES |
5516                       BNX2X_STATE_CLOSING_WAIT4_HALT):
5517                         DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5518                         bnx2x_handle_rx_mode_eqe(bp);
5519                         break;
5520                 default:
5521                         /* unknown event log error and continue */
5522                         BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5523                                   elem->message.opcode, bp->state);
5524                 }
5525 next_spqe:
5526                 spqe_cnt++;
5527         } /* for */
5528
5529         smp_mb__before_atomic();
5530         atomic_add(spqe_cnt, &bp->eq_spq_left);
5531
5532         bp->eq_cons = sw_cons;
5533         bp->eq_prod = sw_prod;
5534         /* Make sure that above mem writes were issued towards the memory */
5535         smp_wmb();
5536
5537         /* update producer */
5538         bnx2x_update_eq_prod(bp, bp->eq_prod);
5539 }
5540
5541 static void bnx2x_sp_task(struct work_struct *work)
5542 {
5543         struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5544
5545         DP(BNX2X_MSG_SP, "sp task invoked\n");
5546
5547         /* make sure the atomic interrupt_occurred has been written */
5548         smp_rmb();
5549         if (atomic_read(&bp->interrupt_occurred)) {
5550
5551                 /* what work needs to be performed? */
5552                 u16 status = bnx2x_update_dsb_idx(bp);
5553
5554                 DP(BNX2X_MSG_SP, "status %x\n", status);
5555                 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5556                 atomic_set(&bp->interrupt_occurred, 0);
5557
5558                 /* HW attentions */
5559                 if (status & BNX2X_DEF_SB_ATT_IDX) {
5560                         bnx2x_attn_int(bp);
5561                         status &= ~BNX2X_DEF_SB_ATT_IDX;
5562                 }
5563
5564                 /* SP events: STAT_QUERY and others */
5565                 if (status & BNX2X_DEF_SB_IDX) {
5566                         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5567
5568                 if (FCOE_INIT(bp) &&
5569                             (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5570                                 /* Prevent local bottom-halves from running as
5571                                  * we are going to change the local NAPI list.
5572                                  */
5573                                 local_bh_disable();
5574                                 napi_schedule(&bnx2x_fcoe(bp, napi));
5575                                 local_bh_enable();
5576                         }
5577
5578                         /* Handle EQ completions */
5579                         bnx2x_eq_int(bp);
5580                         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5581                                      le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5582
5583                         status &= ~BNX2X_DEF_SB_IDX;
5584                 }
5585
5586                 /* if status is non zero then perhaps something went wrong */
5587                 if (unlikely(status))
5588                         DP(BNX2X_MSG_SP,
5589                            "got an unknown interrupt! (status 0x%x)\n", status);
5590
5591                 /* ack status block only if something was actually handled */
5592                 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5593                              le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5594         }
5595
5596         /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5597         if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5598                                &bp->sp_state)) {
5599                 bnx2x_link_report(bp);
5600                 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5601         }
5602 }
5603
5604 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5605 {
5606         struct net_device *dev = dev_instance;
5607         struct bnx2x *bp = netdev_priv(dev);
5608
5609         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5610                      IGU_INT_DISABLE, 0);
5611
5612 #ifdef BNX2X_STOP_ON_ERROR
5613         if (unlikely(bp->panic))
5614                 return IRQ_HANDLED;
5615 #endif
5616
5617         if (CNIC_LOADED(bp)) {
5618                 struct cnic_ops *c_ops;
5619
5620                 rcu_read_lock();
5621                 c_ops = rcu_dereference(bp->cnic_ops);
5622                 if (c_ops)
5623                         c_ops->cnic_handler(bp->cnic_data, NULL);
5624                 rcu_read_unlock();
5625         }
5626
5627         /* schedule sp task to perform default status block work, ack
5628          * attentions and enable interrupts.
5629          */
5630         bnx2x_schedule_sp_task(bp);
5631
5632         return IRQ_HANDLED;
5633 }
5634
5635 /* end of slow path */
5636
5637 void bnx2x_drv_pulse(struct bnx2x *bp)
5638 {
5639         SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5640                  bp->fw_drv_pulse_wr_seq);
5641 }
5642
5643 static void bnx2x_timer(unsigned long data)
5644 {
5645         struct bnx2x *bp = (struct bnx2x *) data;
5646
5647         if (!netif_running(bp->dev))
5648                 return;
5649
5650         if (IS_PF(bp) &&
5651             !BP_NOMCP(bp)) {
5652                 int mb_idx = BP_FW_MB_IDX(bp);
5653                 u16 drv_pulse;
5654                 u16 mcp_pulse;
5655
5656                 ++bp->fw_drv_pulse_wr_seq;
5657                 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5658                 drv_pulse = bp->fw_drv_pulse_wr_seq;
5659                 bnx2x_drv_pulse(bp);
5660
5661                 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5662                              MCP_PULSE_SEQ_MASK);
5663                 /* The delta between driver pulse and mcp response
5664                  * should not get too big. If the MFW is more than 5 pulses
5665                  * behind, we should worry about it enough to generate an error
5666                  * log.
5667                  */
5668                 if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
5669                         BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5670                                   drv_pulse, mcp_pulse);
5671         }
5672
5673         if (bp->state == BNX2X_STATE_OPEN)
5674                 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5675
5676         /* sample pf vf bulletin board for new posts from pf */
5677         if (IS_VF(bp))
5678                 bnx2x_timer_sriov(bp);
5679
5680         mod_timer(&bp->timer, jiffies + bp->current_interval);
5681 }
5682
5683 /* end of Statistics */
5684
5685 /* nic init */
5686
5687 /*
5688  * nic init service functions
5689  */
5690
5691 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5692 {
5693         u32 i;
5694         if (!(len%4) && !(addr%4))
5695                 for (i = 0; i < len; i += 4)
5696                         REG_WR(bp, addr + i, fill);
5697         else
5698                 for (i = 0; i < len; i++)
5699                         REG_WR8(bp, addr + i, fill);
5700 }
5701
5702 /* helper: writes FP SP data to FW - data_size in dwords */
5703 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5704                                 int fw_sb_id,
5705                                 u32 *sb_data_p,
5706                                 u32 data_size)
5707 {
5708         int index;
5709         for (index = 0; index < data_size; index++)
5710                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5711                         CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5712                         sizeof(u32)*index,
5713                         *(sb_data_p + index));
5714 }
5715
5716 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5717 {
5718         u32 *sb_data_p;
5719         u32 data_size = 0;
5720         struct hc_status_block_data_e2 sb_data_e2;
5721         struct hc_status_block_data_e1x sb_data_e1x;
5722
5723         /* disable the function first */
5724         if (!CHIP_IS_E1x(bp)) {
5725                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5726                 sb_data_e2.common.state = SB_DISABLED;
5727                 sb_data_e2.common.p_func.vf_valid = false;
5728                 sb_data_p = (u32 *)&sb_data_e2;
5729                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5730         } else {
5731                 memset(&sb_data_e1x, 0,
5732                        sizeof(struct hc_status_block_data_e1x));
5733                 sb_data_e1x.common.state = SB_DISABLED;
5734                 sb_data_e1x.common.p_func.vf_valid = false;
5735                 sb_data_p = (u32 *)&sb_data_e1x;
5736                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5737         }
5738         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5739
5740         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5741                         CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5742                         CSTORM_STATUS_BLOCK_SIZE);
5743         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5744                         CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5745                         CSTORM_SYNC_BLOCK_SIZE);
5746 }
5747
5748 /* helper:  writes SP SB data to FW */
5749 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5750                 struct hc_sp_status_block_data *sp_sb_data)
5751 {
5752         int func = BP_FUNC(bp);
5753         int i;
5754         for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5755                 REG_WR(bp, BAR_CSTRORM_INTMEM +
5756                         CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5757                         i*sizeof(u32),
5758                         *((u32 *)sp_sb_data + i));
5759 }
5760
5761 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5762 {
5763         int func = BP_FUNC(bp);
5764         struct hc_sp_status_block_data sp_sb_data;
5765         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5766
5767         sp_sb_data.state = SB_DISABLED;
5768         sp_sb_data.p_func.vf_valid = false;
5769
5770         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5771
5772         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5773                         CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5774                         CSTORM_SP_STATUS_BLOCK_SIZE);
5775         bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5776                         CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5777                         CSTORM_SP_SYNC_BLOCK_SIZE);
5778 }
5779
5780 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5781                                            int igu_sb_id, int igu_seg_id)
5782 {
5783         hc_sm->igu_sb_id = igu_sb_id;
5784         hc_sm->igu_seg_id = igu_seg_id;
5785         hc_sm->timer_value = 0xFF;
5786         hc_sm->time_to_expire = 0xFFFFFFFF;
5787 }
5788
5789 /* allocates state machine ids. */
5790 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5791 {
5792         /* zero out state machine indices */
5793         /* rx indices */
5794         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5795
5796         /* tx indices */
5797         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5798         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5799         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5800         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5801
5802         /* map indices */
5803         /* rx indices */
5804         index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5805                 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5806
5807         /* tx indices */
5808         index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5809                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5810         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5811                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5812         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5813                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5814         index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5815                 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5816 }
5817
5818 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5819                           u8 vf_valid, int fw_sb_id, int igu_sb_id)
5820 {
5821         int igu_seg_id;
5822
5823         struct hc_status_block_data_e2 sb_data_e2;
5824         struct hc_status_block_data_e1x sb_data_e1x;
5825         struct hc_status_block_sm  *hc_sm_p;
5826         int data_size;
5827         u32 *sb_data_p;
5828
5829         if (CHIP_INT_MODE_IS_BC(bp))
5830                 igu_seg_id = HC_SEG_ACCESS_NORM;
5831         else
5832                 igu_seg_id = IGU_SEG_ACCESS_NORM;
5833
5834         bnx2x_zero_fp_sb(bp, fw_sb_id);
5835
5836         if (!CHIP_IS_E1x(bp)) {
5837                 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5838                 sb_data_e2.common.state = SB_ENABLED;
5839                 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5840                 sb_data_e2.common.p_func.vf_id = vfid;
5841                 sb_data_e2.common.p_func.vf_valid = vf_valid;
5842                 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5843                 sb_data_e2.common.same_igu_sb_1b = true;
5844                 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5845                 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5846                 hc_sm_p = sb_data_e2.common.state_machine;
5847                 sb_data_p = (u32 *)&sb_data_e2;
5848                 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5849                 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5850         } else {
5851                 memset(&sb_data_e1x, 0,
5852                        sizeof(struct hc_status_block_data_e1x));
5853                 sb_data_e1x.common.state = SB_ENABLED;
5854                 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5855                 sb_data_e1x.common.p_func.vf_id = 0xff;
5856                 sb_data_e1x.common.p_func.vf_valid = false;
5857                 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5858                 sb_data_e1x.common.same_igu_sb_1b = true;
5859                 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5860                 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5861                 hc_sm_p = sb_data_e1x.common.state_machine;
5862                 sb_data_p = (u32 *)&sb_data_e1x;
5863                 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5864                 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5865         }
5866
5867         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5868                                        igu_sb_id, igu_seg_id);
5869         bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5870                                        igu_sb_id, igu_seg_id);
5871
5872         DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5873
5874         /* write indices to HW - PCI guarantees endianity of regpairs */
5875         bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5876 }
5877
5878 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5879                                      u16 tx_usec, u16 rx_usec)
5880 {
5881         bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5882                                     false, rx_usec);
5883         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5884                                        HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5885                                        tx_usec);
5886         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5887                                        HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5888                                        tx_usec);
5889         bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5890                                        HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5891                                        tx_usec);
5892 }
5893
5894 static void bnx2x_init_def_sb(struct bnx2x *bp)
5895 {
5896         struct host_sp_status_block *def_sb = bp->def_status_blk;
5897         dma_addr_t mapping = bp->def_status_blk_mapping;
5898         int igu_sp_sb_index;
5899         int igu_seg_id;
5900         int port = BP_PORT(bp);
5901         int func = BP_FUNC(bp);
5902         int reg_offset, reg_offset_en5;
5903         u64 section;
5904         int index;
5905         struct hc_sp_status_block_data sp_sb_data;
5906         memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5907
5908         if (CHIP_INT_MODE_IS_BC(bp)) {
5909                 igu_sp_sb_index = DEF_SB_IGU_ID;
5910                 igu_seg_id = HC_SEG_ACCESS_DEF;
5911         } else {
5912                 igu_sp_sb_index = bp->igu_dsb_id;
5913                 igu_seg_id = IGU_SEG_ACCESS_DEF;
5914         }
5915
5916         /* ATTN */
5917         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5918                                             atten_status_block);
5919         def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5920
5921         bp->attn_state = 0;
5922
5923         reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5924                              MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5925         reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5926                                  MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5927         for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5928                 int sindex;
5929                 /* take care of sig[0]..sig[4] */
5930                 for (sindex = 0; sindex < 4; sindex++)
5931                         bp->attn_group[index].sig[sindex] =
5932                            REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5933
5934                 if (!CHIP_IS_E1x(bp))
5935                         /*
5936                          * enable5 is separate from the rest of the registers,
5937                          * and therefore the address skip is 4
5938                          * and not 16 between the different groups
5939                          */
5940                         bp->attn_group[index].sig[4] = REG_RD(bp,
5941                                         reg_offset_en5 + 0x4*index);
5942                 else
5943                         bp->attn_group[index].sig[4] = 0;
5944         }
5945
5946         if (bp->common.int_block == INT_BLOCK_HC) {
5947                 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5948                                      HC_REG_ATTN_MSG0_ADDR_L);
5949
5950                 REG_WR(bp, reg_offset, U64_LO(section));
5951                 REG_WR(bp, reg_offset + 4, U64_HI(section));
5952         } else if (!CHIP_IS_E1x(bp)) {
5953                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5954                 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5955         }
5956
5957         section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5958                                             sp_sb);
5959
5960         bnx2x_zero_sp_sb(bp);
5961
5962         /* PCI guarantees endianity of regpairs */
5963         sp_sb_data.state                = SB_ENABLED;
5964         sp_sb_data.host_sb_addr.lo      = U64_LO(section);
5965         sp_sb_data.host_sb_addr.hi      = U64_HI(section);
5966         sp_sb_data.igu_sb_id            = igu_sp_sb_index;
5967         sp_sb_data.igu_seg_id           = igu_seg_id;
5968         sp_sb_data.p_func.pf_id         = func;
5969         sp_sb_data.p_func.vnic_id       = BP_VN(bp);
5970         sp_sb_data.p_func.vf_id         = 0xff;
5971
5972         bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5973
5974         bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5975 }
5976
5977 void bnx2x_update_coalesce(struct bnx2x *bp)
5978 {
5979         int i;
5980
5981         for_each_eth_queue(bp, i)
5982                 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5983                                          bp->tx_ticks, bp->rx_ticks);
5984 }
5985
5986 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5987 {
5988         spin_lock_init(&bp->spq_lock);
5989         atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5990
5991         bp->spq_prod_idx = 0;
5992         bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5993         bp->spq_prod_bd = bp->spq;
5994         bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5995 }
5996
5997 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5998 {
5999         int i;
6000         for (i = 1; i <= NUM_EQ_PAGES; i++) {
6001                 union event_ring_elem *elem =
6002                         &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
6003
6004                 elem->next_page.addr.hi =
6005                         cpu_to_le32(U64_HI(bp->eq_mapping +
6006                                    BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
6007                 elem->next_page.addr.lo =
6008                         cpu_to_le32(U64_LO(bp->eq_mapping +
6009                                    BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
6010         }
6011         bp->eq_cons = 0;
6012         bp->eq_prod = NUM_EQ_DESC;
6013         bp->eq_cons_sb = BNX2X_EQ_INDEX;
6014         /* we want a warning message before it gets wrought... */
6015         atomic_set(&bp->eq_spq_left,
6016                 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
6017 }
6018
6019 /* called with netif_addr_lock_bh() */
6020 static int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
6021                                unsigned long rx_mode_flags,
6022                                unsigned long rx_accept_flags,
6023                                unsigned long tx_accept_flags,
6024                                unsigned long ramrod_flags)
6025 {
6026         struct bnx2x_rx_mode_ramrod_params ramrod_param;
6027         int rc;
6028
6029         memset(&ramrod_param, 0, sizeof(ramrod_param));
6030
6031         /* Prepare ramrod parameters */
6032         ramrod_param.cid = 0;
6033         ramrod_param.cl_id = cl_id;
6034         ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
6035         ramrod_param.func_id = BP_FUNC(bp);
6036
6037         ramrod_param.pstate = &bp->sp_state;
6038         ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
6039
6040         ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
6041         ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
6042
6043         set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
6044
6045         ramrod_param.ramrod_flags = ramrod_flags;
6046         ramrod_param.rx_mode_flags = rx_mode_flags;
6047
6048         ramrod_param.rx_accept_flags = rx_accept_flags;
6049         ramrod_param.tx_accept_flags = tx_accept_flags;
6050
6051         rc = bnx2x_config_rx_mode(bp, &ramrod_param);
6052         if (rc < 0) {
6053                 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
6054                 return rc;
6055         }
6056
6057         return 0;
6058 }
6059
6060 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
6061                                    unsigned long *rx_accept_flags,
6062                                    unsigned long *tx_accept_flags)
6063 {
6064         /* Clear the flags first */
6065         *rx_accept_flags = 0;
6066         *tx_accept_flags = 0;
6067
6068         switch (rx_mode) {
6069         case BNX2X_RX_MODE_NONE:
6070                 /*
6071                  * 'drop all' supersedes any accept flags that may have been
6072                  * passed to the function.
6073                  */
6074                 break;
6075         case BNX2X_RX_MODE_NORMAL:
6076                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6077                 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
6078                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6079
6080                 /* internal switching mode */
6081                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6082                 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
6083                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6084
6085                 break;
6086         case BNX2X_RX_MODE_ALLMULTI:
6087                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6088                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6089                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6090
6091                 /* internal switching mode */
6092                 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6093                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6094                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6095
6096                 break;
6097         case BNX2X_RX_MODE_PROMISC:
6098                 /* According to definition of SI mode, iface in promisc mode
6099                  * should receive matched and unmatched (in resolution of port)
6100                  * unicast packets.
6101                  */
6102                 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
6103                 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
6104                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
6105                 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
6106
6107                 /* internal switching mode */
6108                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
6109                 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
6110
6111                 if (IS_MF_SI(bp))
6112                         __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
6113                 else
6114                         __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
6115
6116                 break;
6117         default:
6118                 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
6119                 return -EINVAL;
6120         }
6121
6122         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
6123         if (rx_mode != BNX2X_RX_MODE_NONE) {
6124                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
6125                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
6126         }
6127
6128         return 0;
6129 }
6130
6131 /* called with netif_addr_lock_bh() */
6132 static int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
6133 {
6134         unsigned long rx_mode_flags = 0, ramrod_flags = 0;
6135         unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
6136         int rc;
6137
6138         if (!NO_FCOE(bp))
6139                 /* Configure rx_mode of FCoE Queue */
6140                 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
6141
6142         rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
6143                                      &tx_accept_flags);
6144         if (rc)
6145                 return rc;
6146
6147         __set_bit(RAMROD_RX, &ramrod_flags);
6148         __set_bit(RAMROD_TX, &ramrod_flags);
6149
6150         return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
6151                                    rx_accept_flags, tx_accept_flags,
6152                                    ramrod_flags);
6153 }
6154
6155 static void bnx2x_init_internal_common(struct bnx2x *bp)
6156 {
6157         int i;
6158
6159         /* Zero this manually as its initialization is
6160            currently missing in the initTool */
6161         for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
6162                 REG_WR(bp, BAR_USTRORM_INTMEM +
6163                        USTORM_AGG_DATA_OFFSET + i * 4, 0);
6164         if (!CHIP_IS_E1x(bp)) {
6165                 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
6166                         CHIP_INT_MODE_IS_BC(bp) ?
6167                         HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
6168         }
6169 }
6170
6171 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
6172 {
6173         switch (load_code) {
6174         case FW_MSG_CODE_DRV_LOAD_COMMON:
6175         case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
6176                 bnx2x_init_internal_common(bp);
6177                 /* no break */
6178
6179         case FW_MSG_CODE_DRV_LOAD_PORT:
6180                 /* nothing to do */
6181                 /* no break */
6182
6183         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
6184                 /* internal memory per function is
6185                    initialized inside bnx2x_pf_init */
6186                 break;
6187
6188         default:
6189                 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
6190                 break;
6191         }
6192 }
6193
6194 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
6195 {
6196         return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
6197 }
6198
6199 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
6200 {
6201         return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
6202 }
6203
6204 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
6205 {
6206         if (CHIP_IS_E1x(fp->bp))
6207                 return BP_L_ID(fp->bp) + fp->index;
6208         else    /* We want Client ID to be the same as IGU SB ID for 57712 */
6209                 return bnx2x_fp_igu_sb_id(fp);
6210 }
6211
6212 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
6213 {
6214         struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
6215         u8 cos;
6216         unsigned long q_type = 0;
6217         u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
6218         fp->rx_queue = fp_idx;
6219         fp->cid = fp_idx;
6220         fp->cl_id = bnx2x_fp_cl_id(fp);
6221         fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
6222         fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
6223         /* qZone id equals to FW (per path) client id */
6224         fp->cl_qzone_id  = bnx2x_fp_qzone_id(fp);
6225
6226         /* init shortcut */
6227         fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
6228
6229         /* Setup SB indices */
6230         fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
6231
6232         /* Configure Queue State object */
6233         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6234         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6235
6236         BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
6237
6238         /* init tx data */
6239         for_each_cos_in_tx_queue(fp, cos) {
6240                 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
6241                                   CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
6242                                   FP_COS_TO_TXQ(fp, cos, bp),
6243                                   BNX2X_TX_SB_INDEX_BASE + cos, fp);
6244                 cids[cos] = fp->txdata_ptr[cos]->cid;
6245         }
6246
6247         /* nothing more for vf to do here */
6248         if (IS_VF(bp))
6249                 return;
6250
6251         bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
6252                       fp->fw_sb_id, fp->igu_sb_id);
6253         bnx2x_update_fpsb_idx(fp);
6254         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
6255                              fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6256                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6257
6258         /**
6259          * Configure classification DBs: Always enable Tx switching
6260          */
6261         bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
6262
6263         DP(NETIF_MSG_IFUP,
6264            "queue[%d]:  bnx2x_init_sb(%p,%p)  cl_id %d  fw_sb %d  igu_sb %d\n",
6265            fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6266            fp->igu_sb_id);
6267 }
6268
6269 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
6270 {
6271         int i;
6272
6273         for (i = 1; i <= NUM_TX_RINGS; i++) {
6274                 struct eth_tx_next_bd *tx_next_bd =
6275                         &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
6276
6277                 tx_next_bd->addr_hi =
6278                         cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
6279                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6280                 tx_next_bd->addr_lo =
6281                         cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
6282                                     BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
6283         }
6284
6285         *txdata->tx_cons_sb = cpu_to_le16(0);
6286
6287         SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
6288         txdata->tx_db.data.zero_fill1 = 0;
6289         txdata->tx_db.data.prod = 0;
6290
6291         txdata->tx_pkt_prod = 0;
6292         txdata->tx_pkt_cons = 0;
6293         txdata->tx_bd_prod = 0;
6294         txdata->tx_bd_cons = 0;
6295         txdata->tx_pkt = 0;
6296 }
6297
6298 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
6299 {
6300         int i;
6301
6302         for_each_tx_queue_cnic(bp, i)
6303                 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6304 }
6305
6306 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6307 {
6308         int i;
6309         u8 cos;
6310
6311         for_each_eth_queue(bp, i)
6312                 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6313                         bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6314 }
6315
6316 static void bnx2x_init_fcoe_fp(struct bnx2x *bp)
6317 {
6318         struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
6319         unsigned long q_type = 0;
6320
6321         bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp);
6322         bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp,
6323                                                      BNX2X_FCOE_ETH_CL_ID_IDX);
6324         bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp);
6325         bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID;
6326         bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id;
6327         bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX;
6328         bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]),
6329                           fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX,
6330                           fp);
6331
6332         DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index);
6333
6334         /* qZone id equals to FW (per path) client id */
6335         bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp);
6336         /* init shortcut */
6337         bnx2x_fcoe(bp, ustorm_rx_prods_offset) =
6338                 bnx2x_rx_ustorm_prods_offset(fp);
6339
6340         /* Configure Queue State object */
6341         __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
6342         __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
6343
6344         /* No multi-CoS for FCoE L2 client */
6345         BUG_ON(fp->max_cos != 1);
6346
6347         bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id,
6348                              &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
6349                              bnx2x_sp_mapping(bp, q_rdata), q_type);
6350
6351         DP(NETIF_MSG_IFUP,
6352            "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6353            fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
6354            fp->igu_sb_id);
6355 }
6356
6357 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6358 {
6359         if (!NO_FCOE(bp))
6360                 bnx2x_init_fcoe_fp(bp);
6361
6362         bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6363                       BNX2X_VF_ID_INVALID, false,
6364                       bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6365
6366         /* ensure status block indices were read */
6367         rmb();
6368         bnx2x_init_rx_rings_cnic(bp);
6369         bnx2x_init_tx_rings_cnic(bp);
6370
6371         /* flush all */
6372         mb();
6373         mmiowb();
6374 }
6375
6376 void bnx2x_pre_irq_nic_init(struct bnx2x *bp)
6377 {
6378         int i;
6379
6380         /* Setup NIC internals and enable interrupts */
6381         for_each_eth_queue(bp, i)
6382                 bnx2x_init_eth_fp(bp, i);
6383
6384         /* ensure status block indices were read */
6385         rmb();
6386         bnx2x_init_rx_rings(bp);
6387         bnx2x_init_tx_rings(bp);
6388
6389         if (IS_PF(bp)) {
6390                 /* Initialize MOD_ABS interrupts */
6391                 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6392                                        bp->common.shmem_base,
6393                                        bp->common.shmem2_base, BP_PORT(bp));
6394
6395                 /* initialize the default status block and sp ring */
6396                 bnx2x_init_def_sb(bp);
6397                 bnx2x_update_dsb_idx(bp);
6398                 bnx2x_init_sp_ring(bp);
6399         } else {
6400                 bnx2x_memset_stats(bp);
6401         }
6402 }
6403
6404 void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code)
6405 {
6406         bnx2x_init_eq_ring(bp);
6407         bnx2x_init_internal(bp, load_code);
6408         bnx2x_pf_init(bp);
6409         bnx2x_stats_init(bp);
6410
6411         /* flush all before enabling interrupts */
6412         mb();
6413         mmiowb();
6414
6415         bnx2x_int_enable(bp);
6416
6417         /* Check for SPIO5 */
6418         bnx2x_attn_int_deasserted0(bp,
6419                 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6420                                    AEU_INPUTS_ATTN_BITS_SPIO5);
6421 }
6422
6423 /* gzip service functions */
6424 static int bnx2x_gunzip_init(struct bnx2x *bp)
6425 {
6426         bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6427                                             &bp->gunzip_mapping, GFP_KERNEL);
6428         if (bp->gunzip_buf  == NULL)
6429                 goto gunzip_nomem1;
6430
6431         bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6432         if (bp->strm  == NULL)
6433                 goto gunzip_nomem2;
6434
6435         bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6436         if (bp->strm->workspace == NULL)
6437                 goto gunzip_nomem3;
6438
6439         return 0;
6440
6441 gunzip_nomem3:
6442         kfree(bp->strm);
6443         bp->strm = NULL;
6444
6445 gunzip_nomem2:
6446         dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6447                           bp->gunzip_mapping);
6448         bp->gunzip_buf = NULL;
6449
6450 gunzip_nomem1:
6451         BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6452         return -ENOMEM;
6453 }
6454
6455 static void bnx2x_gunzip_end(struct bnx2x *bp)
6456 {
6457         if (bp->strm) {
6458                 vfree(bp->strm->workspace);
6459                 kfree(bp->strm);
6460                 bp->strm = NULL;
6461         }
6462
6463         if (bp->gunzip_buf) {
6464                 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6465                                   bp->gunzip_mapping);
6466                 bp->gunzip_buf = NULL;
6467         }
6468 }
6469
6470 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6471 {
6472         int n, rc;
6473
6474         /* check gzip header */
6475         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6476                 BNX2X_ERR("Bad gzip header\n");
6477                 return -EINVAL;
6478         }
6479
6480         n = 10;
6481
6482 #define FNAME                           0x8
6483
6484         if (zbuf[3] & FNAME)
6485                 while ((zbuf[n++] != 0) && (n < len));
6486
6487         bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6488         bp->strm->avail_in = len - n;
6489         bp->strm->next_out = bp->gunzip_buf;
6490         bp->strm->avail_out = FW_BUF_SIZE;
6491
6492         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6493         if (rc != Z_OK)
6494                 return rc;
6495
6496         rc = zlib_inflate(bp->strm, Z_FINISH);
6497         if ((rc != Z_OK) && (rc != Z_STREAM_END))
6498                 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6499                            bp->strm->msg);
6500
6501         bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6502         if (bp->gunzip_outlen & 0x3)
6503                 netdev_err(bp->dev,
6504                            "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6505                                 bp->gunzip_outlen);
6506         bp->gunzip_outlen >>= 2;
6507
6508         zlib_inflateEnd(bp->strm);
6509
6510         if (rc == Z_STREAM_END)
6511                 return 0;
6512
6513         return rc;
6514 }
6515
6516 /* nic load/unload */
6517
6518 /*
6519  * General service functions
6520  */
6521
6522 /* send a NIG loopback debug packet */
6523 static void bnx2x_lb_pckt(struct bnx2x *bp)
6524 {
6525         u32 wb_write[3];
6526
6527         /* Ethernet source and destination addresses */
6528         wb_write[0] = 0x55555555;
6529         wb_write[1] = 0x55555555;
6530         wb_write[2] = 0x20;             /* SOP */
6531         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6532
6533         /* NON-IP protocol */
6534         wb_write[0] = 0x09000000;
6535         wb_write[1] = 0x55555555;
6536         wb_write[2] = 0x10;             /* EOP, eop_bvalid = 0 */
6537         REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6538 }
6539
6540 /* some of the internal memories
6541  * are not directly readable from the driver
6542  * to test them we send debug packets
6543  */
6544 static int bnx2x_int_mem_test(struct bnx2x *bp)
6545 {
6546         int factor;
6547         int count, i;
6548         u32 val = 0;
6549
6550         if (CHIP_REV_IS_FPGA(bp))
6551                 factor = 120;
6552         else if (CHIP_REV_IS_EMUL(bp))
6553                 factor = 200;
6554         else
6555                 factor = 1;
6556
6557         /* Disable inputs of parser neighbor blocks */
6558         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6559         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6560         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6561         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6562
6563         /*  Write 0 to parser credits for CFC search request */
6564         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6565
6566         /* send Ethernet packet */
6567         bnx2x_lb_pckt(bp);
6568
6569         /* TODO do i reset NIG statistic? */
6570         /* Wait until NIG register shows 1 packet of size 0x10 */
6571         count = 1000 * factor;
6572         while (count) {
6573
6574                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6575                 val = *bnx2x_sp(bp, wb_data[0]);
6576                 if (val == 0x10)
6577                         break;
6578
6579                 usleep_range(10000, 20000);
6580                 count--;
6581         }
6582         if (val != 0x10) {
6583                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6584                 return -1;
6585         }
6586
6587         /* Wait until PRS register shows 1 packet */
6588         count = 1000 * factor;
6589         while (count) {
6590                 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6591                 if (val == 1)
6592                         break;
6593
6594                 usleep_range(10000, 20000);
6595                 count--;
6596         }
6597         if (val != 0x1) {
6598                 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6599                 return -2;
6600         }
6601
6602         /* Reset and init BRB, PRS */
6603         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6604         msleep(50);
6605         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6606         msleep(50);
6607         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6608         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6609
6610         DP(NETIF_MSG_HW, "part2\n");
6611
6612         /* Disable inputs of parser neighbor blocks */
6613         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6614         REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6615         REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6616         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6617
6618         /* Write 0 to parser credits for CFC search request */
6619         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6620
6621         /* send 10 Ethernet packets */
6622         for (i = 0; i < 10; i++)
6623                 bnx2x_lb_pckt(bp);
6624
6625         /* Wait until NIG register shows 10 + 1
6626            packets of size 11*0x10 = 0xb0 */
6627         count = 1000 * factor;
6628         while (count) {
6629
6630                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6631                 val = *bnx2x_sp(bp, wb_data[0]);
6632                 if (val == 0xb0)
6633                         break;
6634
6635                 usleep_range(10000, 20000);
6636                 count--;
6637         }
6638         if (val != 0xb0) {
6639                 BNX2X_ERR("NIG timeout  val = 0x%x\n", val);
6640                 return -3;
6641         }
6642
6643         /* Wait until PRS register shows 2 packets */
6644         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6645         if (val != 2)
6646                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6647
6648         /* Write 1 to parser credits for CFC search request */
6649         REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6650
6651         /* Wait until PRS register shows 3 packets */
6652         msleep(10 * factor);
6653         /* Wait until NIG register shows 1 packet of size 0x10 */
6654         val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6655         if (val != 3)
6656                 BNX2X_ERR("PRS timeout  val = 0x%x\n", val);
6657
6658         /* clear NIG EOP FIFO */
6659         for (i = 0; i < 11; i++)
6660                 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6661         val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6662         if (val != 1) {
6663                 BNX2X_ERR("clear of NIG failed\n");
6664                 return -4;
6665         }
6666
6667         /* Reset and init BRB, PRS, NIG */
6668         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6669         msleep(50);
6670         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6671         msleep(50);
6672         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6673         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6674         if (!CNIC_SUPPORT(bp))
6675                 /* set NIC mode */
6676                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6677
6678         /* Enable inputs of parser neighbor blocks */
6679         REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6680         REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6681         REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6682         REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6683
6684         DP(NETIF_MSG_HW, "done\n");
6685
6686         return 0; /* OK */
6687 }
6688
6689 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6690 {
6691         u32 val;
6692
6693         REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6694         if (!CHIP_IS_E1x(bp))
6695                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6696         else
6697                 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6698         REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6699         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6700         /*
6701          * mask read length error interrupts in brb for parser
6702          * (parsing unit and 'checksum and crc' unit)
6703          * these errors are legal (PU reads fixed length and CAC can cause
6704          * read length error on truncated packets)
6705          */
6706         REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6707         REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6708         REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6709         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6710         REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6711         REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6712 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6713 /*      REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6714         REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6715         REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6716         REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6717 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6718 /*      REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6719         REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6720         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6721         REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6722         REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6723 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6724 /*      REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6725
6726         val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT  |
6727                 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6728                 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6729         if (!CHIP_IS_E1x(bp))
6730                 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6731                         PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6732         REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6733
6734         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6735         REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6736         REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6737 /*      REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6738
6739         if (!CHIP_IS_E1x(bp))
6740                 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6741                 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6742
6743         REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6744         REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6745 /*      REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6746         REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18);         /* bit 3,4 masked */
6747 }
6748
6749 static void bnx2x_reset_common(struct bnx2x *bp)
6750 {
6751         u32 val = 0x1400;
6752
6753         /* reset_common */
6754         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6755                0xd3ffff7f);
6756
6757         if (CHIP_IS_E3(bp)) {
6758                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6759                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6760         }
6761
6762         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6763 }
6764
6765 static void bnx2x_setup_dmae(struct bnx2x *bp)
6766 {
6767         bp->dmae_ready = 0;
6768         spin_lock_init(&bp->dmae_lock);
6769 }
6770
6771 static void bnx2x_init_pxp(struct bnx2x *bp)
6772 {
6773         u16 devctl;
6774         int r_order, w_order;
6775
6776         pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6777         DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6778         w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6779         if (bp->mrrs == -1)
6780                 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6781         else {
6782                 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6783                 r_order = bp->mrrs;
6784         }
6785
6786         bnx2x_init_pxp_arb(bp, r_order, w_order);
6787 }
6788
6789 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6790 {
6791         int is_required;
6792         u32 val;
6793         int port;
6794
6795         if (BP_NOMCP(bp))
6796                 return;
6797
6798         is_required = 0;
6799         val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6800               SHARED_HW_CFG_FAN_FAILURE_MASK;
6801
6802         if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6803                 is_required = 1;
6804
6805         /*
6806          * The fan failure mechanism is usually related to the PHY type since
6807          * the power consumption of the board is affected by the PHY. Currently,
6808          * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6809          */
6810         else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6811                 for (port = PORT_0; port < PORT_MAX; port++) {
6812                         is_required |=
6813                                 bnx2x_fan_failure_det_req(
6814                                         bp,
6815                                         bp->common.shmem_base,
6816                                         bp->common.shmem2_base,
6817                                         port);
6818                 }
6819
6820         DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6821
6822         if (is_required == 0)
6823                 return;
6824
6825         /* Fan failure is indicated by SPIO 5 */
6826         bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6827
6828         /* set to active low mode */
6829         val = REG_RD(bp, MISC_REG_SPIO_INT);
6830         val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6831         REG_WR(bp, MISC_REG_SPIO_INT, val);
6832
6833         /* enable interrupt to signal the IGU */
6834         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6835         val |= MISC_SPIO_SPIO5;
6836         REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6837 }
6838
6839 void bnx2x_pf_disable(struct bnx2x *bp)
6840 {
6841         u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6842         val &= ~IGU_PF_CONF_FUNC_EN;
6843
6844         REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6845         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6846         REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6847 }
6848
6849 static void bnx2x__common_init_phy(struct bnx2x *bp)
6850 {
6851         u32 shmem_base[2], shmem2_base[2];
6852         /* Avoid common init in case MFW supports LFA */
6853         if (SHMEM2_RD(bp, size) >
6854             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6855                 return;
6856         shmem_base[0] =  bp->common.shmem_base;
6857         shmem2_base[0] = bp->common.shmem2_base;
6858         if (!CHIP_IS_E1x(bp)) {
6859                 shmem_base[1] =
6860                         SHMEM2_RD(bp, other_shmem_base_addr);
6861                 shmem2_base[1] =
6862                         SHMEM2_RD(bp, other_shmem2_base_addr);
6863         }
6864         bnx2x_acquire_phy_lock(bp);
6865         bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6866                               bp->common.chip_id);
6867         bnx2x_release_phy_lock(bp);
6868 }
6869
6870 /**
6871  * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6872  *
6873  * @bp:         driver handle
6874  */
6875 static int bnx2x_init_hw_common(struct bnx2x *bp)
6876 {
6877         u32 val;
6878
6879         DP(NETIF_MSG_HW, "starting common init  func %d\n", BP_ABS_FUNC(bp));
6880
6881         /*
6882          * take the RESET lock to protect undi_unload flow from accessing
6883          * registers while we're resetting the chip
6884          */
6885         bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6886
6887         bnx2x_reset_common(bp);
6888         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6889
6890         val = 0xfffc;
6891         if (CHIP_IS_E3(bp)) {
6892                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6893                 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6894         }
6895         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6896
6897         bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6898
6899         bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6900
6901         if (!CHIP_IS_E1x(bp)) {
6902                 u8 abs_func_id;
6903
6904                 /**
6905                  * 4-port mode or 2-port mode we need to turn of master-enable
6906                  * for everyone, after that, turn it back on for self.
6907                  * so, we disregard multi-function or not, and always disable
6908                  * for all functions on the given path, this means 0,2,4,6 for
6909                  * path 0 and 1,3,5,7 for path 1
6910                  */
6911                 for (abs_func_id = BP_PATH(bp);
6912                      abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6913                         if (abs_func_id == BP_ABS_FUNC(bp)) {
6914                                 REG_WR(bp,
6915                                     PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6916                                     1);
6917                                 continue;
6918                         }
6919
6920                         bnx2x_pretend_func(bp, abs_func_id);
6921                         /* clear pf enable */
6922                         bnx2x_pf_disable(bp);
6923                         bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6924                 }
6925         }
6926
6927         bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6928         if (CHIP_IS_E1(bp)) {
6929                 /* enable HW interrupt from PXP on USDM overflow
6930                    bit 16 on INT_MASK_0 */
6931                 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6932         }
6933
6934         bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6935         bnx2x_init_pxp(bp);
6936
6937 #ifdef __BIG_ENDIAN
6938         REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6939         REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6940         REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6941         REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6942         REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6943         /* make sure this value is 0 */
6944         REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6945
6946 /*      REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6947         REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6948         REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6949         REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6950         REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6951 #endif
6952
6953         bnx2x_ilt_init_page_size(bp, INITOP_SET);
6954
6955         if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6956                 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6957
6958         /* let the HW do it's magic ... */
6959         msleep(100);
6960         /* finish PXP init */
6961         val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6962         if (val != 1) {
6963                 BNX2X_ERR("PXP2 CFG failed\n");
6964                 return -EBUSY;
6965         }
6966         val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6967         if (val != 1) {
6968                 BNX2X_ERR("PXP2 RD_INIT failed\n");
6969                 return -EBUSY;
6970         }
6971
6972         /* Timers bug workaround E2 only. We need to set the entire ILT to
6973          * have entries with value "0" and valid bit on.
6974          * This needs to be done by the first PF that is loaded in a path
6975          * (i.e. common phase)
6976          */
6977         if (!CHIP_IS_E1x(bp)) {
6978 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6979  * (i.e. vnic3) to start even if it is marked as "scan-off".
6980  * This occurs when a different function (func2,3) is being marked
6981  * as "scan-off". Real-life scenario for example: if a driver is being
6982  * load-unloaded while func6,7 are down. This will cause the timer to access
6983  * the ilt, translate to a logical address and send a request to read/write.
6984  * Since the ilt for the function that is down is not valid, this will cause
6985  * a translation error which is unrecoverable.
6986  * The Workaround is intended to make sure that when this happens nothing fatal
6987  * will occur. The workaround:
6988  *      1.  First PF driver which loads on a path will:
6989  *              a.  After taking the chip out of reset, by using pretend,
6990  *                  it will write "0" to the following registers of
6991  *                  the other vnics.
6992  *                  REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6993  *                  REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6994  *                  REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6995  *                  And for itself it will write '1' to
6996  *                  PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6997  *                  dmae-operations (writing to pram for example.)
6998  *                  note: can be done for only function 6,7 but cleaner this
6999  *                        way.
7000  *              b.  Write zero+valid to the entire ILT.
7001  *              c.  Init the first_timers_ilt_entry, last_timers_ilt_entry of
7002  *                  VNIC3 (of that port). The range allocated will be the
7003  *                  entire ILT. This is needed to prevent  ILT range error.
7004  *      2.  Any PF driver load flow:
7005  *              a.  ILT update with the physical addresses of the allocated
7006  *                  logical pages.
7007  *              b.  Wait 20msec. - note that this timeout is needed to make
7008  *                  sure there are no requests in one of the PXP internal
7009  *                  queues with "old" ILT addresses.
7010  *              c.  PF enable in the PGLC.
7011  *              d.  Clear the was_error of the PF in the PGLC. (could have
7012  *                  occurred while driver was down)
7013  *              e.  PF enable in the CFC (WEAK + STRONG)
7014  *              f.  Timers scan enable
7015  *      3.  PF driver unload flow:
7016  *              a.  Clear the Timers scan_en.
7017  *              b.  Polling for scan_on=0 for that PF.
7018  *              c.  Clear the PF enable bit in the PXP.
7019  *              d.  Clear the PF enable in the CFC (WEAK + STRONG)
7020  *              e.  Write zero+valid to all ILT entries (The valid bit must
7021  *                  stay set)
7022  *              f.  If this is VNIC 3 of a port then also init
7023  *                  first_timers_ilt_entry to zero and last_timers_ilt_entry
7024  *                  to the last entry in the ILT.
7025  *
7026  *      Notes:
7027  *      Currently the PF error in the PGLC is non recoverable.
7028  *      In the future the there will be a recovery routine for this error.
7029  *      Currently attention is masked.
7030  *      Having an MCP lock on the load/unload process does not guarantee that
7031  *      there is no Timer disable during Func6/7 enable. This is because the
7032  *      Timers scan is currently being cleared by the MCP on FLR.
7033  *      Step 2.d can be done only for PF6/7 and the driver can also check if
7034  *      there is error before clearing it. But the flow above is simpler and
7035  *      more general.
7036  *      All ILT entries are written by zero+valid and not just PF6/7
7037  *      ILT entries since in the future the ILT entries allocation for
7038  *      PF-s might be dynamic.
7039  */
7040                 struct ilt_client_info ilt_cli;
7041                 struct bnx2x_ilt ilt;
7042                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
7043                 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
7044
7045                 /* initialize dummy TM client */
7046                 ilt_cli.start = 0;
7047                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
7048                 ilt_cli.client_num = ILT_CLIENT_TM;
7049
7050                 /* Step 1: set zeroes to all ilt page entries with valid bit on
7051                  * Step 2: set the timers first/last ilt entry to point
7052                  * to the entire range to prevent ILT range error for 3rd/4th
7053                  * vnic (this code assumes existence of the vnic)
7054                  *
7055                  * both steps performed by call to bnx2x_ilt_client_init_op()
7056                  * with dummy TM client
7057                  *
7058                  * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7059                  * and his brother are split registers
7060                  */
7061                 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
7062                 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
7063                 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
7064
7065                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
7066                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
7067                 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
7068         }
7069
7070         REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
7071         REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
7072
7073         if (!CHIP_IS_E1x(bp)) {
7074                 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
7075                                 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
7076                 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
7077
7078                 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
7079
7080                 /* let the HW do it's magic ... */
7081                 do {
7082                         msleep(200);
7083                         val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
7084                 } while (factor-- && (val != 1));
7085
7086                 if (val != 1) {
7087                         BNX2X_ERR("ATC_INIT failed\n");
7088                         return -EBUSY;
7089                 }
7090         }
7091
7092         bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
7093
7094         bnx2x_iov_init_dmae(bp);
7095
7096         /* clean the DMAE memory */
7097         bp->dmae_ready = 1;
7098         bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
7099
7100         bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
7101
7102         bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
7103
7104         bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
7105
7106         bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
7107
7108         bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
7109         bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
7110         bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
7111         bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
7112
7113         bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
7114
7115         /* QM queues pointers table */
7116         bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
7117
7118         /* soft reset pulse */
7119         REG_WR(bp, QM_REG_SOFT_RESET, 1);
7120         REG_WR(bp, QM_REG_SOFT_RESET, 0);
7121
7122         if (CNIC_SUPPORT(bp))
7123                 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
7124
7125         bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
7126
7127         if (!CHIP_REV_IS_SLOW(bp))
7128                 /* enable hw interrupt from doorbell Q */
7129                 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
7130
7131         bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
7132
7133         bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
7134         REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
7135
7136         if (!CHIP_IS_E1(bp))
7137                 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
7138
7139         if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
7140                 if (IS_MF_AFEX(bp)) {
7141                         /* configure that VNTag and VLAN headers must be
7142                          * received in afex mode
7143                          */
7144                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
7145                         REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
7146                         REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
7147                         REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
7148                         REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
7149                 } else {
7150                         /* Bit-map indicating which L2 hdrs may appear
7151                          * after the basic Ethernet header
7152                          */
7153                         REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
7154                                bp->path_has_ovlan ? 7 : 6);
7155                 }
7156         }
7157
7158         bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
7159         bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
7160         bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
7161         bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
7162
7163         if (!CHIP_IS_E1x(bp)) {
7164                 /* reset VFC memories */
7165                 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7166                            VFC_MEMORIES_RST_REG_CAM_RST |
7167                            VFC_MEMORIES_RST_REG_RAM_RST);
7168                 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
7169                            VFC_MEMORIES_RST_REG_CAM_RST |
7170                            VFC_MEMORIES_RST_REG_RAM_RST);
7171
7172                 msleep(20);
7173         }
7174
7175         bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
7176         bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
7177         bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
7178         bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
7179
7180         /* sync semi rtc */
7181         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
7182                0x80000000);
7183         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
7184                0x80000000);
7185
7186         bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
7187         bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
7188         bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
7189
7190         if (!CHIP_IS_E1x(bp)) {
7191                 if (IS_MF_AFEX(bp)) {
7192                         /* configure that VNTag and VLAN headers must be
7193                          * sent in afex mode
7194                          */
7195                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
7196                         REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
7197                         REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
7198                         REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
7199                         REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
7200                 } else {
7201                         REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
7202                                bp->path_has_ovlan ? 7 : 6);
7203                 }
7204         }
7205
7206         REG_WR(bp, SRC_REG_SOFT_RST, 1);
7207
7208         bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
7209
7210         if (CNIC_SUPPORT(bp)) {
7211                 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
7212                 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
7213                 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
7214                 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
7215                 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
7216                 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
7217                 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
7218                 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
7219                 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
7220                 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
7221         }
7222         REG_WR(bp, SRC_REG_SOFT_RST, 0);
7223
7224         if (sizeof(union cdu_context) != 1024)
7225                 /* we currently assume that a context is 1024 bytes */
7226                 dev_alert(&bp->pdev->dev,
7227                           "please adjust the size of cdu_context(%ld)\n",
7228                           (long)sizeof(union cdu_context));
7229
7230         bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
7231         val = (4 << 24) + (0 << 12) + 1024;
7232         REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
7233
7234         bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
7235         REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
7236         /* enable context validation interrupt from CFC */
7237         REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
7238
7239         /* set the thresholds to prevent CFC/CDU race */
7240         REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
7241
7242         bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
7243
7244         if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
7245                 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
7246
7247         bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
7248         bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
7249
7250         /* Reset PCIE errors for debug */
7251         REG_WR(bp, 0x2814, 0xffffffff);
7252         REG_WR(bp, 0x3820, 0xffffffff);
7253
7254         if (!CHIP_IS_E1x(bp)) {
7255                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
7256                            (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
7257                                 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
7258                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
7259                            (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
7260                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
7261                                 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
7262                 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
7263                            (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
7264                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
7265                                 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
7266         }
7267
7268         bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
7269         if (!CHIP_IS_E1(bp)) {
7270                 /* in E3 this done in per-port section */
7271                 if (!CHIP_IS_E3(bp))
7272                         REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
7273         }
7274         if (CHIP_IS_E1H(bp))
7275                 /* not applicable for E2 (and above ...) */
7276                 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
7277
7278         if (CHIP_REV_IS_SLOW(bp))
7279                 msleep(200);
7280
7281         /* finish CFC init */
7282         val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
7283         if (val != 1) {
7284                 BNX2X_ERR("CFC LL_INIT failed\n");
7285                 return -EBUSY;
7286         }
7287         val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
7288         if (val != 1) {
7289                 BNX2X_ERR("CFC AC_INIT failed\n");
7290                 return -EBUSY;
7291         }
7292         val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
7293         if (val != 1) {
7294                 BNX2X_ERR("CFC CAM_INIT failed\n");
7295                 return -EBUSY;
7296         }
7297         REG_WR(bp, CFC_REG_DEBUG0, 0);
7298
7299         if (CHIP_IS_E1(bp)) {
7300                 /* read NIG statistic
7301                    to see if this is our first up since powerup */
7302                 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
7303                 val = *bnx2x_sp(bp, wb_data[0]);
7304
7305                 /* do internal memory self test */
7306                 if ((val == 0) && bnx2x_int_mem_test(bp)) {
7307                         BNX2X_ERR("internal mem self test failed\n");
7308                         return -EBUSY;
7309                 }
7310         }
7311
7312         bnx2x_setup_fan_failure_detection(bp);
7313
7314         /* clear PXP2 attentions */
7315         REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
7316
7317         bnx2x_enable_blocks_attention(bp);
7318         bnx2x_enable_blocks_parity(bp);
7319
7320         if (!BP_NOMCP(bp)) {
7321                 if (CHIP_IS_E1x(bp))
7322                         bnx2x__common_init_phy(bp);
7323         } else
7324                 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7325
7326         return 0;
7327 }
7328
7329 /**
7330  * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7331  *
7332  * @bp:         driver handle
7333  */
7334 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
7335 {
7336         int rc = bnx2x_init_hw_common(bp);
7337
7338         if (rc)
7339                 return rc;
7340
7341         /* In E2 2-PORT mode, same ext phy is used for the two paths */
7342         if (!BP_NOMCP(bp))
7343                 bnx2x__common_init_phy(bp);
7344
7345         return 0;
7346 }
7347
7348 static int bnx2x_init_hw_port(struct bnx2x *bp)
7349 {
7350         int port = BP_PORT(bp);
7351         int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7352         u32 low, high;
7353         u32 val, reg;
7354
7355         DP(NETIF_MSG_HW, "starting port init  port %d\n", port);
7356
7357         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7358
7359         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7360         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7361         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7362
7363         /* Timers bug workaround: disables the pf_master bit in pglue at
7364          * common phase, we need to enable it here before any dmae access are
7365          * attempted. Therefore we manually added the enable-master to the
7366          * port phase (it also happens in the function phase)
7367          */
7368         if (!CHIP_IS_E1x(bp))
7369                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7370
7371         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7372         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7373         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7374         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7375
7376         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7377         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7378         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7379         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7380
7381         /* QM cid (connection) count */
7382         bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7383
7384         if (CNIC_SUPPORT(bp)) {
7385                 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7386                 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7387                 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7388         }
7389
7390         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7391
7392         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7393
7394         if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7395
7396                 if (IS_MF(bp))
7397                         low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7398                 else if (bp->dev->mtu > 4096) {
7399                         if (bp->flags & ONE_PORT_FLAG)
7400                                 low = 160;
7401                         else {
7402                                 val = bp->dev->mtu;
7403                                 /* (24*1024 + val*4)/256 */
7404                                 low = 96 + (val/64) +
7405                                                 ((val % 64) ? 1 : 0);
7406                         }
7407                 } else
7408                         low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7409                 high = low + 56;        /* 14*1024/256 */
7410                 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7411                 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7412         }
7413
7414         if (CHIP_MODE_IS_4_PORT(bp))
7415                 REG_WR(bp, (BP_PORT(bp) ?
7416                             BRB1_REG_MAC_GUARANTIED_1 :
7417                             BRB1_REG_MAC_GUARANTIED_0), 40);
7418
7419         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7420         if (CHIP_IS_E3B0(bp)) {
7421                 if (IS_MF_AFEX(bp)) {
7422                         /* configure headers for AFEX mode */
7423                         REG_WR(bp, BP_PORT(bp) ?
7424                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7425                                PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7426                         REG_WR(bp, BP_PORT(bp) ?
7427                                PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7428                                PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7429                         REG_WR(bp, BP_PORT(bp) ?
7430                                PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7431                                PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7432                 } else {
7433                         /* Ovlan exists only if we are in multi-function +
7434                          * switch-dependent mode, in switch-independent there
7435                          * is no ovlan headers
7436                          */
7437                         REG_WR(bp, BP_PORT(bp) ?
7438                                PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7439                                PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7440                                (bp->path_has_ovlan ? 7 : 6));
7441                 }
7442         }
7443
7444         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7445         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7446         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7447         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7448
7449         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7450         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7451         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7452         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7453
7454         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7455         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7456
7457         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7458
7459         if (CHIP_IS_E1x(bp)) {
7460                 /* configure PBF to work without PAUSE mtu 9000 */
7461                 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7462
7463                 /* update threshold */
7464                 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7465                 /* update init credit */
7466                 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7467
7468                 /* probe changes */
7469                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7470                 udelay(50);
7471                 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7472         }
7473
7474         if (CNIC_SUPPORT(bp))
7475                 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7476
7477         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7478         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7479
7480         if (CHIP_IS_E1(bp)) {
7481                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7482                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7483         }
7484         bnx2x_init_block(bp, BLOCK_HC, init_phase);
7485
7486         bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7487
7488         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7489         /* init aeu_mask_attn_func_0/1:
7490          *  - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7491          *  - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7492          *             bits 4-7 are used for "per vn group attention" */
7493         val = IS_MF(bp) ? 0xF7 : 0x7;
7494         /* Enable DCBX attention for all but E1 */
7495         val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7496         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7497
7498         /* SCPAD_PARITY should NOT trigger close the gates */
7499         reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
7500         REG_WR(bp, reg,
7501                REG_RD(bp, reg) &
7502                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7503
7504         reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
7505         REG_WR(bp, reg,
7506                REG_RD(bp, reg) &
7507                ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
7508
7509         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7510
7511         if (!CHIP_IS_E1x(bp)) {
7512                 /* Bit-map indicating which L2 hdrs may appear after the
7513                  * basic Ethernet header
7514                  */
7515                 if (IS_MF_AFEX(bp))
7516                         REG_WR(bp, BP_PORT(bp) ?
7517                                NIG_REG_P1_HDRS_AFTER_BASIC :
7518                                NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7519                 else
7520                         REG_WR(bp, BP_PORT(bp) ?
7521                                NIG_REG_P1_HDRS_AFTER_BASIC :
7522                                NIG_REG_P0_HDRS_AFTER_BASIC,
7523                                IS_MF_SD(bp) ? 7 : 6);
7524
7525                 if (CHIP_IS_E3(bp))
7526                         REG_WR(bp, BP_PORT(bp) ?
7527                                    NIG_REG_LLH1_MF_MODE :
7528                                    NIG_REG_LLH_MF_MODE, IS_MF(bp));
7529         }
7530         if (!CHIP_IS_E3(bp))
7531                 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7532
7533         if (!CHIP_IS_E1(bp)) {
7534                 /* 0x2 disable mf_ov, 0x1 enable */
7535                 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7536                        (IS_MF_SD(bp) ? 0x1 : 0x2));
7537
7538                 if (!CHIP_IS_E1x(bp)) {
7539                         val = 0;
7540                         switch (bp->mf_mode) {
7541                         case MULTI_FUNCTION_SD:
7542                                 val = 1;
7543                                 break;
7544                         case MULTI_FUNCTION_SI:
7545                         case MULTI_FUNCTION_AFEX:
7546                                 val = 2;
7547                                 break;
7548                         }
7549
7550                         REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7551                                                   NIG_REG_LLH0_CLS_TYPE), val);
7552                 }
7553                 {
7554                         REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7555                         REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7556                         REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7557                 }
7558         }
7559
7560         /* If SPIO5 is set to generate interrupts, enable it for this port */
7561         val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7562         if (val & MISC_SPIO_SPIO5) {
7563                 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7564                                        MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7565                 val = REG_RD(bp, reg_addr);
7566                 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7567                 REG_WR(bp, reg_addr, val);
7568         }
7569
7570         return 0;
7571 }
7572
7573 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7574 {
7575         int reg;
7576         u32 wb_write[2];
7577
7578         if (CHIP_IS_E1(bp))
7579                 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7580         else
7581                 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7582
7583         wb_write[0] = ONCHIP_ADDR1(addr);
7584         wb_write[1] = ONCHIP_ADDR2(addr);
7585         REG_WR_DMAE(bp, reg, wb_write, 2);
7586 }
7587
7588 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7589 {
7590         u32 data, ctl, cnt = 100;
7591         u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7592         u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7593         u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7594         u32 sb_bit =  1 << (idu_sb_id%32);
7595         u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7596         u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7597
7598         /* Not supported in BC mode */
7599         if (CHIP_INT_MODE_IS_BC(bp))
7600                 return;
7601
7602         data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7603                         << IGU_REGULAR_CLEANUP_TYPE_SHIFT)      |
7604                 IGU_REGULAR_CLEANUP_SET                         |
7605                 IGU_REGULAR_BCLEANUP;
7606
7607         ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT         |
7608               func_encode << IGU_CTRL_REG_FID_SHIFT             |
7609               IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7610
7611         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7612                          data, igu_addr_data);
7613         REG_WR(bp, igu_addr_data, data);
7614         mmiowb();
7615         barrier();
7616         DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7617                           ctl, igu_addr_ctl);
7618         REG_WR(bp, igu_addr_ctl, ctl);
7619         mmiowb();
7620         barrier();
7621
7622         /* wait for clean up to finish */
7623         while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7624                 msleep(20);
7625
7626         if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7627                 DP(NETIF_MSG_HW,
7628                    "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7629                           idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7630         }
7631 }
7632
7633 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7634 {
7635         bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7636 }
7637
7638 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7639 {
7640         u32 i, base = FUNC_ILT_BASE(func);
7641         for (i = base; i < base + ILT_PER_FUNC; i++)
7642                 bnx2x_ilt_wr(bp, i, 0);
7643 }
7644
7645 static void bnx2x_init_searcher(struct bnx2x *bp)
7646 {
7647         int port = BP_PORT(bp);
7648         bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7649         /* T1 hash bits value determines the T1 number of entries */
7650         REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7651 }
7652
7653 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7654 {
7655         int rc;
7656         struct bnx2x_func_state_params func_params = {NULL};
7657         struct bnx2x_func_switch_update_params *switch_update_params =
7658                 &func_params.params.switch_update;
7659
7660         /* Prepare parameters for function state transitions */
7661         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7662         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7663
7664         func_params.f_obj = &bp->func_obj;
7665         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7666
7667         /* Function parameters */
7668         __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
7669                   &switch_update_params->changes);
7670         if (suspend)
7671                 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
7672                           &switch_update_params->changes);
7673
7674         rc = bnx2x_func_state_change(bp, &func_params);
7675
7676         return rc;
7677 }
7678
7679 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7680 {
7681         int rc, i, port = BP_PORT(bp);
7682         int vlan_en = 0, mac_en[NUM_MACS];
7683
7684         /* Close input from network */
7685         if (bp->mf_mode == SINGLE_FUNCTION) {
7686                 bnx2x_set_rx_filter(&bp->link_params, 0);
7687         } else {
7688                 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7689                                    NIG_REG_LLH0_FUNC_EN);
7690                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7691                           NIG_REG_LLH0_FUNC_EN, 0);
7692                 for (i = 0; i < NUM_MACS; i++) {
7693                         mac_en[i] = REG_RD(bp, port ?
7694                                              (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7695                                               4 * i) :
7696                                              (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7697                                               4 * i));
7698                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7699                                               4 * i) :
7700                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7701                 }
7702         }
7703
7704         /* Close BMC to host */
7705         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7706                NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7707
7708         /* Suspend Tx switching to the PF. Completion of this ramrod
7709          * further guarantees that all the packets of that PF / child
7710          * VFs in BRB were processed by the Parser, so it is safe to
7711          * change the NIC_MODE register.
7712          */
7713         rc = bnx2x_func_switch_update(bp, 1);
7714         if (rc) {
7715                 BNX2X_ERR("Can't suspend tx-switching!\n");
7716                 return rc;
7717         }
7718
7719         /* Change NIC_MODE register */
7720         REG_WR(bp, PRS_REG_NIC_MODE, 0);
7721
7722         /* Open input from network */
7723         if (bp->mf_mode == SINGLE_FUNCTION) {
7724                 bnx2x_set_rx_filter(&bp->link_params, 1);
7725         } else {
7726                 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7727                           NIG_REG_LLH0_FUNC_EN, vlan_en);
7728                 for (i = 0; i < NUM_MACS; i++) {
7729                         REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7730                                               4 * i) :
7731                                   (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7732                                   mac_en[i]);
7733                 }
7734         }
7735
7736         /* Enable BMC to host */
7737         REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7738                NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7739
7740         /* Resume Tx switching to the PF */
7741         rc = bnx2x_func_switch_update(bp, 0);
7742         if (rc) {
7743                 BNX2X_ERR("Can't resume tx-switching!\n");
7744                 return rc;
7745         }
7746
7747         DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7748         return 0;
7749 }
7750
7751 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7752 {
7753         int rc;
7754
7755         bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7756
7757         if (CONFIGURE_NIC_MODE(bp)) {
7758                 /* Configure searcher as part of function hw init */
7759                 bnx2x_init_searcher(bp);
7760
7761                 /* Reset NIC mode */
7762                 rc = bnx2x_reset_nic_mode(bp);
7763                 if (rc)
7764                         BNX2X_ERR("Can't change NIC mode!\n");
7765                 return rc;
7766         }
7767
7768         return 0;
7769 }
7770
7771 static int bnx2x_init_hw_func(struct bnx2x *bp)
7772 {
7773         int port = BP_PORT(bp);
7774         int func = BP_FUNC(bp);
7775         int init_phase = PHASE_PF0 + func;
7776         struct bnx2x_ilt *ilt = BP_ILT(bp);
7777         u16 cdu_ilt_start;
7778         u32 addr, val;
7779         u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7780         int i, main_mem_width, rc;
7781
7782         DP(NETIF_MSG_HW, "starting func init  func %d\n", func);
7783
7784         /* FLR cleanup - hmmm */
7785         if (!CHIP_IS_E1x(bp)) {
7786                 rc = bnx2x_pf_flr_clnup(bp);
7787                 if (rc) {
7788                         bnx2x_fw_dump(bp);
7789                         return rc;
7790                 }
7791         }
7792
7793         /* set MSI reconfigure capability */
7794         if (bp->common.int_block == INT_BLOCK_HC) {
7795                 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7796                 val = REG_RD(bp, addr);
7797                 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7798                 REG_WR(bp, addr, val);
7799         }
7800
7801         bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7802         bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7803
7804         ilt = BP_ILT(bp);
7805         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7806
7807         if (IS_SRIOV(bp))
7808                 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7809         cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7810
7811         /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7812          * those of the VFs, so start line should be reset
7813          */
7814         cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7815         for (i = 0; i < L2_ILT_LINES(bp); i++) {
7816                 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7817                 ilt->lines[cdu_ilt_start + i].page_mapping =
7818                         bp->context[i].cxt_mapping;
7819                 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7820         }
7821
7822         bnx2x_ilt_init_op(bp, INITOP_SET);
7823
7824         if (!CONFIGURE_NIC_MODE(bp)) {
7825                 bnx2x_init_searcher(bp);
7826                 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7827                 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7828         } else {
7829                 /* Set NIC mode */
7830                 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7831                 DP(NETIF_MSG_IFUP, "NIC MODE configured\n");
7832         }
7833
7834         if (!CHIP_IS_E1x(bp)) {
7835                 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7836
7837                 /* Turn on a single ISR mode in IGU if driver is going to use
7838                  * INT#x or MSI
7839                  */
7840                 if (!(bp->flags & USING_MSIX_FLAG))
7841                         pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7842                 /*
7843                  * Timers workaround bug: function init part.
7844                  * Need to wait 20msec after initializing ILT,
7845                  * needed to make sure there are no requests in
7846                  * one of the PXP internal queues with "old" ILT addresses
7847                  */
7848                 msleep(20);
7849                 /*
7850                  * Master enable - Due to WB DMAE writes performed before this
7851                  * register is re-initialized as part of the regular function
7852                  * init
7853                  */
7854                 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7855                 /* Enable the function in IGU */
7856                 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7857         }
7858
7859         bp->dmae_ready = 1;
7860
7861         bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7862
7863         if (!CHIP_IS_E1x(bp))
7864                 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7865
7866         bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7867         bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7868         bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7869         bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7870         bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7871         bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7872         bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7873         bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7874         bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7875         bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7876         bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7877         bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7878         bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7879
7880         if (!CHIP_IS_E1x(bp))
7881                 REG_WR(bp, QM_REG_PF_EN, 1);
7882
7883         if (!CHIP_IS_E1x(bp)) {
7884                 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7885                 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7886                 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7887                 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7888         }
7889         bnx2x_init_block(bp, BLOCK_QM, init_phase);
7890
7891         bnx2x_init_block(bp, BLOCK_TM, init_phase);
7892         bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7893         REG_WR(bp, DORQ_REG_MODE_ACT, 1); /* no dpm */
7894
7895         bnx2x_iov_init_dq(bp);
7896
7897         bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7898         bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7899         bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7900         bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7901         bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7902         bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7903         bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7904         bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7905         bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7906         if (!CHIP_IS_E1x(bp))
7907                 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7908
7909         bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7910
7911         bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7912
7913         if (!CHIP_IS_E1x(bp))
7914                 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7915
7916         if (IS_MF(bp)) {
7917                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7918                 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7919         }
7920
7921         bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7922
7923         /* HC init per function */
7924         if (bp->common.int_block == INT_BLOCK_HC) {
7925                 if (CHIP_IS_E1H(bp)) {
7926                         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7927
7928                         REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7929                         REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7930                 }
7931                 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7932
7933         } else {
7934                 int num_segs, sb_idx, prod_offset;
7935
7936                 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7937
7938                 if (!CHIP_IS_E1x(bp)) {
7939                         REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7940                         REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7941                 }
7942
7943                 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7944
7945                 if (!CHIP_IS_E1x(bp)) {
7946                         int dsb_idx = 0;
7947                         /**
7948                          * Producer memory:
7949                          * E2 mode: address 0-135 match to the mapping memory;
7950                          * 136 - PF0 default prod; 137 - PF1 default prod;
7951                          * 138 - PF2 default prod; 139 - PF3 default prod;
7952                          * 140 - PF0 attn prod;    141 - PF1 attn prod;
7953                          * 142 - PF2 attn prod;    143 - PF3 attn prod;
7954                          * 144-147 reserved.
7955                          *
7956                          * E1.5 mode - In backward compatible mode;
7957                          * for non default SB; each even line in the memory
7958                          * holds the U producer and each odd line hold
7959                          * the C producer. The first 128 producers are for
7960                          * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7961                          * producers are for the DSB for each PF.
7962                          * Each PF has five segments: (the order inside each
7963                          * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7964                          * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7965                          * 144-147 attn prods;
7966                          */
7967                         /* non-default-status-blocks */
7968                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7969                                 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7970                         for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7971                                 prod_offset = (bp->igu_base_sb + sb_idx) *
7972                                         num_segs;
7973
7974                                 for (i = 0; i < num_segs; i++) {
7975                                         addr = IGU_REG_PROD_CONS_MEMORY +
7976                                                         (prod_offset + i) * 4;
7977                                         REG_WR(bp, addr, 0);
7978                                 }
7979                                 /* send consumer update with value 0 */
7980                                 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7981                                              USTORM_ID, 0, IGU_INT_NOP, 1);
7982                                 bnx2x_igu_clear_sb(bp,
7983                                                    bp->igu_base_sb + sb_idx);
7984                         }
7985
7986                         /* default-status-blocks */
7987                         num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7988                                 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7989
7990                         if (CHIP_MODE_IS_4_PORT(bp))
7991                                 dsb_idx = BP_FUNC(bp);
7992                         else
7993                                 dsb_idx = BP_VN(bp);
7994
7995                         prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7996                                        IGU_BC_BASE_DSB_PROD + dsb_idx :
7997                                        IGU_NORM_BASE_DSB_PROD + dsb_idx);
7998
7999                         /*
8000                          * igu prods come in chunks of E1HVN_MAX (4) -
8001                          * does not matters what is the current chip mode
8002                          */
8003                         for (i = 0; i < (num_segs * E1HVN_MAX);
8004                              i += E1HVN_MAX) {
8005                                 addr = IGU_REG_PROD_CONS_MEMORY +
8006                                                         (prod_offset + i)*4;
8007                                 REG_WR(bp, addr, 0);
8008                         }
8009                         /* send consumer update with 0 */
8010                         if (CHIP_INT_MODE_IS_BC(bp)) {
8011                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8012                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8013                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8014                                              CSTORM_ID, 0, IGU_INT_NOP, 1);
8015                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8016                                              XSTORM_ID, 0, IGU_INT_NOP, 1);
8017                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8018                                              TSTORM_ID, 0, IGU_INT_NOP, 1);
8019                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8020                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8021                         } else {
8022                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8023                                              USTORM_ID, 0, IGU_INT_NOP, 1);
8024                                 bnx2x_ack_sb(bp, bp->igu_dsb_id,
8025                                              ATTENTION_ID, 0, IGU_INT_NOP, 1);
8026                         }
8027                         bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
8028
8029                         /* !!! These should become driver const once
8030                            rf-tool supports split-68 const */
8031                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
8032                         REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
8033                         REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
8034                         REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
8035                         REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
8036                         REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
8037                 }
8038         }
8039
8040         /* Reset PCIE errors for debug */
8041         REG_WR(bp, 0x2114, 0xffffffff);
8042         REG_WR(bp, 0x2120, 0xffffffff);
8043
8044         if (CHIP_IS_E1x(bp)) {
8045                 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
8046                 main_mem_base = HC_REG_MAIN_MEMORY +
8047                                 BP_PORT(bp) * (main_mem_size * 4);
8048                 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
8049                 main_mem_width = 8;
8050
8051                 val = REG_RD(bp, main_mem_prty_clr);
8052                 if (val)
8053                         DP(NETIF_MSG_HW,
8054                            "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8055                            val);
8056
8057                 /* Clear "false" parity errors in MSI-X table */
8058                 for (i = main_mem_base;
8059                      i < main_mem_base + main_mem_size * 4;
8060                      i += main_mem_width) {
8061                         bnx2x_read_dmae(bp, i, main_mem_width / 4);
8062                         bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
8063                                          i, main_mem_width / 4);
8064                 }
8065                 /* Clear HC parity attention */
8066                 REG_RD(bp, main_mem_prty_clr);
8067         }
8068
8069 #ifdef BNX2X_STOP_ON_ERROR
8070         /* Enable STORMs SP logging */
8071         REG_WR8(bp, BAR_USTRORM_INTMEM +
8072                USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8073         REG_WR8(bp, BAR_TSTRORM_INTMEM +
8074                TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8075         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8076                CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8077         REG_WR8(bp, BAR_XSTRORM_INTMEM +
8078                XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
8079 #endif
8080
8081         bnx2x_phy_probe(&bp->link_params);
8082
8083         return 0;
8084 }
8085
8086 void bnx2x_free_mem_cnic(struct bnx2x *bp)
8087 {
8088         bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
8089
8090         if (!CHIP_IS_E1x(bp))
8091                 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
8092                                sizeof(struct host_hc_status_block_e2));
8093         else
8094                 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
8095                                sizeof(struct host_hc_status_block_e1x));
8096
8097         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8098 }
8099
8100 void bnx2x_free_mem(struct bnx2x *bp)
8101 {
8102         int i;
8103
8104         BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
8105                        bp->fw_stats_data_sz + bp->fw_stats_req_sz);
8106
8107         if (IS_VF(bp))
8108                 return;
8109
8110         BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
8111                        sizeof(struct host_sp_status_block));
8112
8113         BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
8114                        sizeof(struct bnx2x_slowpath));
8115
8116         for (i = 0; i < L2_ILT_LINES(bp); i++)
8117                 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
8118                                bp->context[i].size);
8119         bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
8120
8121         BNX2X_FREE(bp->ilt->lines);
8122
8123         BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
8124
8125         BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
8126                        BCM_PAGE_SIZE * NUM_EQ_PAGES);
8127
8128         BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
8129
8130         bnx2x_iov_free_mem(bp);
8131 }
8132
8133 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
8134 {
8135         if (!CHIP_IS_E1x(bp)) {
8136                 /* size = the status block + ramrod buffers */
8137                 bp->cnic_sb.e2_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8138                                                     sizeof(struct host_hc_status_block_e2));
8139                 if (!bp->cnic_sb.e2_sb)
8140                         goto alloc_mem_err;
8141         } else {
8142                 bp->cnic_sb.e1x_sb = BNX2X_PCI_ALLOC(&bp->cnic_sb_mapping,
8143                                                      sizeof(struct host_hc_status_block_e1x));
8144                 if (!bp->cnic_sb.e1x_sb)
8145                         goto alloc_mem_err;
8146         }
8147
8148         if (CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8149                 /* allocate searcher T2 table, as it wasn't allocated before */
8150                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8151                 if (!bp->t2)
8152                         goto alloc_mem_err;
8153         }
8154
8155         /* write address to which L5 should insert its values */
8156         bp->cnic_eth_dev.addr_drv_info_to_mcp =
8157                 &bp->slowpath->drv_info_to_mcp;
8158
8159         if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
8160                 goto alloc_mem_err;
8161
8162         return 0;
8163
8164 alloc_mem_err:
8165         bnx2x_free_mem_cnic(bp);
8166         BNX2X_ERR("Can't allocate memory\n");
8167         return -ENOMEM;
8168 }
8169
8170 int bnx2x_alloc_mem(struct bnx2x *bp)
8171 {
8172         int i, allocated, context_size;
8173
8174         if (!CONFIGURE_NIC_MODE(bp) && !bp->t2) {
8175                 /* allocate searcher T2 table */
8176                 bp->t2 = BNX2X_PCI_ALLOC(&bp->t2_mapping, SRC_T2_SZ);
8177                 if (!bp->t2)
8178                         goto alloc_mem_err;
8179         }
8180
8181         bp->def_status_blk = BNX2X_PCI_ALLOC(&bp->def_status_blk_mapping,
8182                                              sizeof(struct host_sp_status_block));
8183         if (!bp->def_status_blk)
8184                 goto alloc_mem_err;
8185
8186         bp->slowpath = BNX2X_PCI_ALLOC(&bp->slowpath_mapping,
8187                                        sizeof(struct bnx2x_slowpath));
8188         if (!bp->slowpath)
8189                 goto alloc_mem_err;
8190
8191         /* Allocate memory for CDU context:
8192          * This memory is allocated separately and not in the generic ILT
8193          * functions because CDU differs in few aspects:
8194          * 1. There are multiple entities allocating memory for context -
8195          * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8196          * its own ILT lines.
8197          * 2. Since CDU page-size is not a single 4KB page (which is the case
8198          * for the other ILT clients), to be efficient we want to support
8199          * allocation of sub-page-size in the last entry.
8200          * 3. Context pointers are used by the driver to pass to FW / update
8201          * the context (for the other ILT clients the pointers are used just to
8202          * free the memory during unload).
8203          */
8204         context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
8205
8206         for (i = 0, allocated = 0; allocated < context_size; i++) {
8207                 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
8208                                           (context_size - allocated));
8209                 bp->context[i].vcxt = BNX2X_PCI_ALLOC(&bp->context[i].cxt_mapping,
8210                                                       bp->context[i].size);
8211                 if (!bp->context[i].vcxt)
8212                         goto alloc_mem_err;
8213                 allocated += bp->context[i].size;
8214         }
8215         bp->ilt->lines = kcalloc(ILT_MAX_LINES, sizeof(struct ilt_line),
8216                                  GFP_KERNEL);
8217         if (!bp->ilt->lines)
8218                 goto alloc_mem_err;
8219
8220         if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
8221                 goto alloc_mem_err;
8222
8223         if (bnx2x_iov_alloc_mem(bp))
8224                 goto alloc_mem_err;
8225
8226         /* Slow path ring */
8227         bp->spq = BNX2X_PCI_ALLOC(&bp->spq_mapping, BCM_PAGE_SIZE);
8228         if (!bp->spq)
8229                 goto alloc_mem_err;
8230
8231         /* EQ */
8232         bp->eq_ring = BNX2X_PCI_ALLOC(&bp->eq_mapping,
8233                                       BCM_PAGE_SIZE * NUM_EQ_PAGES);
8234         if (!bp->eq_ring)
8235                 goto alloc_mem_err;
8236
8237         return 0;
8238
8239 alloc_mem_err:
8240         bnx2x_free_mem(bp);
8241         BNX2X_ERR("Can't allocate memory\n");
8242         return -ENOMEM;
8243 }
8244
8245 /*
8246  * Init service functions
8247  */
8248
8249 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
8250                       struct bnx2x_vlan_mac_obj *obj, bool set,
8251                       int mac_type, unsigned long *ramrod_flags)
8252 {
8253         int rc;
8254         struct bnx2x_vlan_mac_ramrod_params ramrod_param;
8255
8256         memset(&ramrod_param, 0, sizeof(ramrod_param));
8257
8258         /* Fill general parameters */
8259         ramrod_param.vlan_mac_obj = obj;
8260         ramrod_param.ramrod_flags = *ramrod_flags;
8261
8262         /* Fill a user request section if needed */
8263         if (!test_bit(RAMROD_CONT, ramrod_flags)) {
8264                 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
8265
8266                 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
8267
8268                 /* Set the command: ADD or DEL */
8269                 if (set)
8270                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
8271                 else
8272                         ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
8273         }
8274
8275         rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
8276
8277         if (rc == -EEXIST) {
8278                 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
8279                 /* do not treat adding same MAC as error */
8280                 rc = 0;
8281         } else if (rc < 0)
8282                 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
8283
8284         return rc;
8285 }
8286
8287 int bnx2x_del_all_macs(struct bnx2x *bp,
8288                        struct bnx2x_vlan_mac_obj *mac_obj,
8289                        int mac_type, bool wait_for_comp)
8290 {
8291         int rc;
8292         unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
8293
8294         /* Wait for completion of requested */
8295         if (wait_for_comp)
8296                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8297
8298         /* Set the mac type of addresses we want to clear */
8299         __set_bit(mac_type, &vlan_mac_flags);
8300
8301         rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
8302         if (rc < 0)
8303                 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
8304
8305         return rc;
8306 }
8307
8308 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
8309 {
8310         if (is_zero_ether_addr(bp->dev->dev_addr) &&
8311             (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
8312                 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
8313                    "Ignoring Zero MAC for STORAGE SD mode\n");
8314                 return 0;
8315         }
8316
8317         if (IS_PF(bp)) {
8318                 unsigned long ramrod_flags = 0;
8319
8320                 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
8321                 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
8322                 return bnx2x_set_mac_one(bp, bp->dev->dev_addr,
8323                                          &bp->sp_objs->mac_obj, set,
8324                                          BNX2X_ETH_MAC, &ramrod_flags);
8325         } else { /* vf */
8326                 return bnx2x_vfpf_config_mac(bp, bp->dev->dev_addr,
8327                                              bp->fp->index, true);
8328         }
8329 }
8330
8331 int bnx2x_setup_leading(struct bnx2x *bp)
8332 {
8333         if (IS_PF(bp))
8334                 return bnx2x_setup_queue(bp, &bp->fp[0], true);
8335         else /* VF */
8336                 return bnx2x_vfpf_setup_q(bp, &bp->fp[0], true);
8337 }
8338
8339 /**
8340  * bnx2x_set_int_mode - configure interrupt mode
8341  *
8342  * @bp:         driver handle
8343  *
8344  * In case of MSI-X it will also try to enable MSI-X.
8345  */
8346 int bnx2x_set_int_mode(struct bnx2x *bp)
8347 {
8348         int rc = 0;
8349
8350         if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX) {
8351                 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8352                 return -EINVAL;
8353         }
8354
8355         switch (int_mode) {
8356         case BNX2X_INT_MODE_MSIX:
8357                 /* attempt to enable msix */
8358                 rc = bnx2x_enable_msix(bp);
8359
8360                 /* msix attained */
8361                 if (!rc)
8362                         return 0;
8363
8364                 /* vfs use only msix */
8365                 if (rc && IS_VF(bp))
8366                         return rc;
8367
8368                 /* failed to enable multiple MSI-X */
8369                 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8370                                bp->num_queues,
8371                                1 + bp->num_cnic_queues);
8372
8373                 /* falling through... */
8374         case BNX2X_INT_MODE_MSI:
8375                 bnx2x_enable_msi(bp);
8376
8377                 /* falling through... */
8378         case BNX2X_INT_MODE_INTX:
8379                 bp->num_ethernet_queues = 1;
8380                 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
8381                 BNX2X_DEV_INFO("set number of queues to 1\n");
8382                 break;
8383         default:
8384                 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8385                 return -EINVAL;
8386         }
8387         return 0;
8388 }
8389
8390 /* must be called prior to any HW initializations */
8391 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8392 {
8393         if (IS_SRIOV(bp))
8394                 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8395         return L2_ILT_LINES(bp);
8396 }
8397
8398 void bnx2x_ilt_set_info(struct bnx2x *bp)
8399 {
8400         struct ilt_client_info *ilt_client;
8401         struct bnx2x_ilt *ilt = BP_ILT(bp);
8402         u16 line = 0;
8403
8404         ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8405         DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8406
8407         /* CDU */
8408         ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8409         ilt_client->client_num = ILT_CLIENT_CDU;
8410         ilt_client->page_size = CDU_ILT_PAGE_SZ;
8411         ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8412         ilt_client->start = line;
8413         line += bnx2x_cid_ilt_lines(bp);
8414
8415         if (CNIC_SUPPORT(bp))
8416                 line += CNIC_ILT_LINES;
8417         ilt_client->end = line - 1;
8418
8419         DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8420            ilt_client->start,
8421            ilt_client->end,
8422            ilt_client->page_size,
8423            ilt_client->flags,
8424            ilog2(ilt_client->page_size >> 12));
8425
8426         /* QM */
8427         if (QM_INIT(bp->qm_cid_count)) {
8428                 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8429                 ilt_client->client_num = ILT_CLIENT_QM;
8430                 ilt_client->page_size = QM_ILT_PAGE_SZ;
8431                 ilt_client->flags = 0;
8432                 ilt_client->start = line;
8433
8434                 /* 4 bytes for each cid */
8435                 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8436                                                          QM_ILT_PAGE_SZ);
8437
8438                 ilt_client->end = line - 1;
8439
8440                 DP(NETIF_MSG_IFUP,
8441                    "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8442                    ilt_client->start,
8443                    ilt_client->end,
8444                    ilt_client->page_size,
8445                    ilt_client->flags,
8446                    ilog2(ilt_client->page_size >> 12));
8447         }
8448
8449         if (CNIC_SUPPORT(bp)) {
8450                 /* SRC */
8451                 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8452                 ilt_client->client_num = ILT_CLIENT_SRC;
8453                 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8454                 ilt_client->flags = 0;
8455                 ilt_client->start = line;
8456                 line += SRC_ILT_LINES;
8457                 ilt_client->end = line - 1;
8458
8459                 DP(NETIF_MSG_IFUP,
8460                    "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8461                    ilt_client->start,
8462                    ilt_client->end,
8463                    ilt_client->page_size,
8464                    ilt_client->flags,
8465                    ilog2(ilt_client->page_size >> 12));
8466
8467                 /* TM */
8468                 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8469                 ilt_client->client_num = ILT_CLIENT_TM;
8470                 ilt_client->page_size = TM_ILT_PAGE_SZ;
8471                 ilt_client->flags = 0;
8472                 ilt_client->start = line;
8473                 line += TM_ILT_LINES;
8474                 ilt_client->end = line - 1;
8475
8476                 DP(NETIF_MSG_IFUP,
8477                    "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8478                    ilt_client->start,
8479                    ilt_client->end,
8480                    ilt_client->page_size,
8481                    ilt_client->flags,
8482                    ilog2(ilt_client->page_size >> 12));
8483         }
8484
8485         BUG_ON(line > ILT_MAX_LINES);
8486 }
8487
8488 /**
8489  * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8490  *
8491  * @bp:                 driver handle
8492  * @fp:                 pointer to fastpath
8493  * @init_params:        pointer to parameters structure
8494  *
8495  * parameters configured:
8496  *      - HC configuration
8497  *      - Queue's CDU context
8498  */
8499 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8500         struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8501 {
8502         u8 cos;
8503         int cxt_index, cxt_offset;
8504
8505         /* FCoE Queue uses Default SB, thus has no HC capabilities */
8506         if (!IS_FCOE_FP(fp)) {
8507                 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8508                 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8509
8510                 /* If HC is supported, enable host coalescing in the transition
8511                  * to INIT state.
8512                  */
8513                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8514                 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8515
8516                 /* HC rate */
8517                 init_params->rx.hc_rate = bp->rx_ticks ?
8518                         (1000000 / bp->rx_ticks) : 0;
8519                 init_params->tx.hc_rate = bp->tx_ticks ?
8520                         (1000000 / bp->tx_ticks) : 0;
8521
8522                 /* FW SB ID */
8523                 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8524                         fp->fw_sb_id;
8525
8526                 /*
8527                  * CQ index among the SB indices: FCoE clients uses the default
8528                  * SB, therefore it's different.
8529                  */
8530                 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8531                 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8532         }
8533
8534         /* set maximum number of COSs supported by this queue */
8535         init_params->max_cos = fp->max_cos;
8536
8537         DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8538             fp->index, init_params->max_cos);
8539
8540         /* set the context pointers queue object */
8541         for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8542                 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8543                 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8544                                 ILT_PAGE_CIDS);
8545                 init_params->cxts[cos] =
8546                         &bp->context[cxt_index].vcxt[cxt_offset].eth;
8547         }
8548 }
8549
8550 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8551                         struct bnx2x_queue_state_params *q_params,
8552                         struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8553                         int tx_index, bool leading)
8554 {
8555         memset(tx_only_params, 0, sizeof(*tx_only_params));
8556
8557         /* Set the command */
8558         q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8559
8560         /* Set tx-only QUEUE flags: don't zero statistics */
8561         tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8562
8563         /* choose the index of the cid to send the slow path on */
8564         tx_only_params->cid_index = tx_index;
8565
8566         /* Set general TX_ONLY_SETUP parameters */
8567         bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8568
8569         /* Set Tx TX_ONLY_SETUP parameters */
8570         bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8571
8572         DP(NETIF_MSG_IFUP,
8573            "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8574            tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8575            q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8576            tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8577
8578         /* send the ramrod */
8579         return bnx2x_queue_state_change(bp, q_params);
8580 }
8581
8582 /**
8583  * bnx2x_setup_queue - setup queue
8584  *
8585  * @bp:         driver handle
8586  * @fp:         pointer to fastpath
8587  * @leading:    is leading
8588  *
8589  * This function performs 2 steps in a Queue state machine
8590  *      actually: 1) RESET->INIT 2) INIT->SETUP
8591  */
8592
8593 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8594                        bool leading)
8595 {
8596         struct bnx2x_queue_state_params q_params = {NULL};
8597         struct bnx2x_queue_setup_params *setup_params =
8598                                                 &q_params.params.setup;
8599         struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8600                                                 &q_params.params.tx_only;
8601         int rc;
8602         u8 tx_index;
8603
8604         DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8605
8606         /* reset IGU state skip FCoE L2 queue */
8607         if (!IS_FCOE_FP(fp))
8608                 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8609                              IGU_INT_ENABLE, 0);
8610
8611         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8612         /* We want to wait for completion in this context */
8613         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8614
8615         /* Prepare the INIT parameters */
8616         bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8617
8618         /* Set the command */
8619         q_params.cmd = BNX2X_Q_CMD_INIT;
8620
8621         /* Change the state to INIT */
8622         rc = bnx2x_queue_state_change(bp, &q_params);
8623         if (rc) {
8624                 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8625                 return rc;
8626         }
8627
8628         DP(NETIF_MSG_IFUP, "init complete\n");
8629
8630         /* Now move the Queue to the SETUP state... */
8631         memset(setup_params, 0, sizeof(*setup_params));
8632
8633         /* Set QUEUE flags */
8634         setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8635
8636         /* Set general SETUP parameters */
8637         bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8638                                 FIRST_TX_COS_INDEX);
8639
8640         bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8641                             &setup_params->rxq_params);
8642
8643         bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8644                            FIRST_TX_COS_INDEX);
8645
8646         /* Set the command */
8647         q_params.cmd = BNX2X_Q_CMD_SETUP;
8648
8649         if (IS_FCOE_FP(fp))
8650                 bp->fcoe_init = true;
8651
8652         /* Change the state to SETUP */
8653         rc = bnx2x_queue_state_change(bp, &q_params);
8654         if (rc) {
8655                 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8656                 return rc;
8657         }
8658
8659         /* loop through the relevant tx-only indices */
8660         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8661               tx_index < fp->max_cos;
8662               tx_index++) {
8663
8664                 /* prepare and send tx-only ramrod*/
8665                 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8666                                           tx_only_params, tx_index, leading);
8667                 if (rc) {
8668                         BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8669                                   fp->index, tx_index);
8670                         return rc;
8671                 }
8672         }
8673
8674         return rc;
8675 }
8676
8677 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8678 {
8679         struct bnx2x_fastpath *fp = &bp->fp[index];
8680         struct bnx2x_fp_txdata *txdata;
8681         struct bnx2x_queue_state_params q_params = {NULL};
8682         int rc, tx_index;
8683
8684         DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8685
8686         q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8687         /* We want to wait for completion in this context */
8688         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8689
8690         /* close tx-only connections */
8691         for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8692              tx_index < fp->max_cos;
8693              tx_index++){
8694
8695                 /* ascertain this is a normal queue*/
8696                 txdata = fp->txdata_ptr[tx_index];
8697
8698                 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8699                                                         txdata->txq_index);
8700
8701                 /* send halt terminate on tx-only connection */
8702                 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8703                 memset(&q_params.params.terminate, 0,
8704                        sizeof(q_params.params.terminate));
8705                 q_params.params.terminate.cid_index = tx_index;
8706
8707                 rc = bnx2x_queue_state_change(bp, &q_params);
8708                 if (rc)
8709                         return rc;
8710
8711                 /* send halt terminate on tx-only connection */
8712                 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8713                 memset(&q_params.params.cfc_del, 0,
8714                        sizeof(q_params.params.cfc_del));
8715                 q_params.params.cfc_del.cid_index = tx_index;
8716                 rc = bnx2x_queue_state_change(bp, &q_params);
8717                 if (rc)
8718                         return rc;
8719         }
8720         /* Stop the primary connection: */
8721         /* ...halt the connection */
8722         q_params.cmd = BNX2X_Q_CMD_HALT;
8723         rc = bnx2x_queue_state_change(bp, &q_params);
8724         if (rc)
8725                 return rc;
8726
8727         /* ...terminate the connection */
8728         q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8729         memset(&q_params.params.terminate, 0,
8730                sizeof(q_params.params.terminate));
8731         q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8732         rc = bnx2x_queue_state_change(bp, &q_params);
8733         if (rc)
8734                 return rc;
8735         /* ...delete cfc entry */
8736         q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8737         memset(&q_params.params.cfc_del, 0,
8738                sizeof(q_params.params.cfc_del));
8739         q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8740         return bnx2x_queue_state_change(bp, &q_params);
8741 }
8742
8743 static void bnx2x_reset_func(struct bnx2x *bp)
8744 {
8745         int port = BP_PORT(bp);
8746         int func = BP_FUNC(bp);
8747         int i;
8748
8749         /* Disable the function in the FW */
8750         REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8751         REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8752         REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8753         REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8754
8755         /* FP SBs */
8756         for_each_eth_queue(bp, i) {
8757                 struct bnx2x_fastpath *fp = &bp->fp[i];
8758                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8759                            CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8760                            SB_DISABLED);
8761         }
8762
8763         if (CNIC_LOADED(bp))
8764                 /* CNIC SB */
8765                 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8766                         CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8767                         (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8768
8769         /* SP SB */
8770         REG_WR8(bp, BAR_CSTRORM_INTMEM +
8771                 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8772                 SB_DISABLED);
8773
8774         for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8775                 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8776                        0);
8777
8778         /* Configure IGU */
8779         if (bp->common.int_block == INT_BLOCK_HC) {
8780                 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8781                 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8782         } else {
8783                 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8784                 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8785         }
8786
8787         if (CNIC_LOADED(bp)) {
8788                 /* Disable Timer scan */
8789                 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8790                 /*
8791                  * Wait for at least 10ms and up to 2 second for the timers
8792                  * scan to complete
8793                  */
8794                 for (i = 0; i < 200; i++) {
8795                         usleep_range(10000, 20000);
8796                         if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8797                                 break;
8798                 }
8799         }
8800         /* Clear ILT */
8801         bnx2x_clear_func_ilt(bp, func);
8802
8803         /* Timers workaround bug for E2: if this is vnic-3,
8804          * we need to set the entire ilt range for this timers.
8805          */
8806         if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8807                 struct ilt_client_info ilt_cli;
8808                 /* use dummy TM client */
8809                 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8810                 ilt_cli.start = 0;
8811                 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8812                 ilt_cli.client_num = ILT_CLIENT_TM;
8813
8814                 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8815         }
8816
8817         /* this assumes that reset_port() called before reset_func()*/
8818         if (!CHIP_IS_E1x(bp))
8819                 bnx2x_pf_disable(bp);
8820
8821         bp->dmae_ready = 0;
8822 }
8823
8824 static void bnx2x_reset_port(struct bnx2x *bp)
8825 {
8826         int port = BP_PORT(bp);
8827         u32 val;
8828
8829         /* Reset physical Link */
8830         bnx2x__link_reset(bp);
8831
8832         REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8833
8834         /* Do not rcv packets to BRB */
8835         REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8836         /* Do not direct rcv packets that are not for MCP to the BRB */
8837         REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8838                            NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8839
8840         /* Configure AEU */
8841         REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8842
8843         msleep(100);
8844         /* Check for BRB port occupancy */
8845         val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8846         if (val)
8847                 DP(NETIF_MSG_IFDOWN,
8848                    "BRB1 is not empty  %d blocks are occupied\n", val);
8849
8850         /* TODO: Close Doorbell port? */
8851 }
8852
8853 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8854 {
8855         struct bnx2x_func_state_params func_params = {NULL};
8856
8857         /* Prepare parameters for function state transitions */
8858         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8859
8860         func_params.f_obj = &bp->func_obj;
8861         func_params.cmd = BNX2X_F_CMD_HW_RESET;
8862
8863         func_params.params.hw_init.load_phase = load_code;
8864
8865         return bnx2x_func_state_change(bp, &func_params);
8866 }
8867
8868 static int bnx2x_func_stop(struct bnx2x *bp)
8869 {
8870         struct bnx2x_func_state_params func_params = {NULL};
8871         int rc;
8872
8873         /* Prepare parameters for function state transitions */
8874         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8875         func_params.f_obj = &bp->func_obj;
8876         func_params.cmd = BNX2X_F_CMD_STOP;
8877
8878         /*
8879          * Try to stop the function the 'good way'. If fails (in case
8880          * of a parity error during bnx2x_chip_cleanup()) and we are
8881          * not in a debug mode, perform a state transaction in order to
8882          * enable further HW_RESET transaction.
8883          */
8884         rc = bnx2x_func_state_change(bp, &func_params);
8885         if (rc) {
8886 #ifdef BNX2X_STOP_ON_ERROR
8887                 return rc;
8888 #else
8889                 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8890                 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8891                 return bnx2x_func_state_change(bp, &func_params);
8892 #endif
8893         }
8894
8895         return 0;
8896 }
8897
8898 /**
8899  * bnx2x_send_unload_req - request unload mode from the MCP.
8900  *
8901  * @bp:                 driver handle
8902  * @unload_mode:        requested function's unload mode
8903  *
8904  * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8905  */
8906 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8907 {
8908         u32 reset_code = 0;
8909         int port = BP_PORT(bp);
8910
8911         /* Select the UNLOAD request mode */
8912         if (unload_mode == UNLOAD_NORMAL)
8913                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8914
8915         else if (bp->flags & NO_WOL_FLAG)
8916                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8917
8918         else if (bp->wol) {
8919                 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8920                 u8 *mac_addr = bp->dev->dev_addr;
8921                 struct pci_dev *pdev = bp->pdev;
8922                 u32 val;
8923                 u16 pmc;
8924
8925                 /* The mac address is written to entries 1-4 to
8926                  * preserve entry 0 which is used by the PMF
8927                  */
8928                 u8 entry = (BP_VN(bp) + 1)*8;
8929
8930                 val = (mac_addr[0] << 8) | mac_addr[1];
8931                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8932
8933                 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8934                       (mac_addr[4] << 8) | mac_addr[5];
8935                 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8936
8937                 /* Enable the PME and clear the status */
8938                 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &pmc);
8939                 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8940                 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc);
8941
8942                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8943
8944         } else
8945                 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8946
8947         /* Send the request to the MCP */
8948         if (!BP_NOMCP(bp))
8949                 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8950         else {
8951                 int path = BP_PATH(bp);
8952
8953                 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d]      %d, %d, %d\n",
8954                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8955                    bnx2x_load_count[path][2]);
8956                 bnx2x_load_count[path][0]--;
8957                 bnx2x_load_count[path][1 + port]--;
8958                 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d]  %d, %d, %d\n",
8959                    path, bnx2x_load_count[path][0], bnx2x_load_count[path][1],
8960                    bnx2x_load_count[path][2]);
8961                 if (bnx2x_load_count[path][0] == 0)
8962                         reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8963                 else if (bnx2x_load_count[path][1 + port] == 0)
8964                         reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8965                 else
8966                         reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8967         }
8968
8969         return reset_code;
8970 }
8971
8972 /**
8973  * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8974  *
8975  * @bp:         driver handle
8976  * @keep_link:          true iff link should be kept up
8977  */
8978 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8979 {
8980         u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8981
8982         /* Report UNLOAD_DONE to MCP */
8983         if (!BP_NOMCP(bp))
8984                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8985 }
8986
8987 static int bnx2x_func_wait_started(struct bnx2x *bp)
8988 {
8989         int tout = 50;
8990         int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8991
8992         if (!bp->port.pmf)
8993                 return 0;
8994
8995         /*
8996          * (assumption: No Attention from MCP at this stage)
8997          * PMF probably in the middle of TX disable/enable transaction
8998          * 1. Sync IRS for default SB
8999          * 2. Sync SP queue - this guarantees us that attention handling started
9000          * 3. Wait, that TX disable/enable transaction completes
9001          *
9002          * 1+2 guarantee that if DCBx attention was scheduled it already changed
9003          * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9004          * received completion for the transaction the state is TX_STOPPED.
9005          * State will return to STARTED after completion of TX_STOPPED-->STARTED
9006          * transaction.
9007          */
9008
9009         /* make sure default SB ISR is done */
9010         if (msix)
9011                 synchronize_irq(bp->msix_table[0].vector);
9012         else
9013                 synchronize_irq(bp->pdev->irq);
9014
9015         flush_workqueue(bnx2x_wq);
9016         flush_workqueue(bnx2x_iov_wq);
9017
9018         while (bnx2x_func_get_state(bp, &bp->func_obj) !=
9019                                 BNX2X_F_STATE_STARTED && tout--)
9020                 msleep(20);
9021
9022         if (bnx2x_func_get_state(bp, &bp->func_obj) !=
9023                                                 BNX2X_F_STATE_STARTED) {
9024 #ifdef BNX2X_STOP_ON_ERROR
9025                 BNX2X_ERR("Wrong function state\n");
9026                 return -EBUSY;
9027 #else
9028                 /*
9029                  * Failed to complete the transaction in a "good way"
9030                  * Force both transactions with CLR bit
9031                  */
9032                 struct bnx2x_func_state_params func_params = {NULL};
9033
9034                 DP(NETIF_MSG_IFDOWN,
9035                    "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9036
9037                 func_params.f_obj = &bp->func_obj;
9038                 __set_bit(RAMROD_DRV_CLR_ONLY,
9039                                         &func_params.ramrod_flags);
9040
9041                 /* STARTED-->TX_ST0PPED */
9042                 func_params.cmd = BNX2X_F_CMD_TX_STOP;
9043                 bnx2x_func_state_change(bp, &func_params);
9044
9045                 /* TX_ST0PPED-->STARTED */
9046                 func_params.cmd = BNX2X_F_CMD_TX_START;
9047                 return bnx2x_func_state_change(bp, &func_params);
9048 #endif
9049         }
9050
9051         return 0;
9052 }
9053
9054 static void bnx2x_disable_ptp(struct bnx2x *bp)
9055 {
9056         int port = BP_PORT(bp);
9057
9058         /* Disable sending PTP packets to host */
9059         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
9060                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
9061
9062         /* Reset PTP event detection rules */
9063         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
9064                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
9065         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
9066                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
9067         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
9068                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
9069         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
9070                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
9071
9072         /* Disable the PTP feature */
9073         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
9074                NIG_REG_P0_PTP_EN, 0x0);
9075 }
9076
9077 /* Called during unload, to stop PTP-related stuff */
9078 void bnx2x_stop_ptp(struct bnx2x *bp)
9079 {
9080         /* Cancel PTP work queue. Should be done after the Tx queues are
9081          * drained to prevent additional scheduling.
9082          */
9083         cancel_work_sync(&bp->ptp_task);
9084
9085         if (bp->ptp_tx_skb) {
9086                 dev_kfree_skb_any(bp->ptp_tx_skb);
9087                 bp->ptp_tx_skb = NULL;
9088         }
9089
9090         /* Disable PTP in HW */
9091         bnx2x_disable_ptp(bp);
9092
9093         DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
9094 }
9095
9096 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
9097 {
9098         int port = BP_PORT(bp);
9099         int i, rc = 0;
9100         u8 cos;
9101         struct bnx2x_mcast_ramrod_params rparam = {NULL};
9102         u32 reset_code;
9103
9104         /* Wait until tx fastpath tasks complete */
9105         for_each_tx_queue(bp, i) {
9106                 struct bnx2x_fastpath *fp = &bp->fp[i];
9107
9108                 for_each_cos_in_tx_queue(fp, cos)
9109                         rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
9110 #ifdef BNX2X_STOP_ON_ERROR
9111                 if (rc)
9112                         return;
9113 #endif
9114         }
9115
9116         /* Give HW time to discard old tx messages */
9117         usleep_range(1000, 2000);
9118
9119         /* Clean all ETH MACs */
9120         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
9121                                 false);
9122         if (rc < 0)
9123                 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
9124
9125         /* Clean up UC list  */
9126         rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
9127                                 true);
9128         if (rc < 0)
9129                 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9130                           rc);
9131
9132         /* Disable LLH */
9133         if (!CHIP_IS_E1(bp))
9134                 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
9135
9136         /* Set "drop all" (stop Rx).
9137          * We need to take a netif_addr_lock() here in order to prevent
9138          * a race between the completion code and this code.
9139          */
9140         netif_addr_lock_bh(bp->dev);
9141         /* Schedule the rx_mode command */
9142         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
9143                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
9144         else
9145                 bnx2x_set_storm_rx_mode(bp);
9146
9147         /* Cleanup multicast configuration */
9148         rparam.mcast_obj = &bp->mcast_obj;
9149         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
9150         if (rc < 0)
9151                 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
9152
9153         netif_addr_unlock_bh(bp->dev);
9154
9155         bnx2x_iov_chip_cleanup(bp);
9156
9157         /*
9158          * Send the UNLOAD_REQUEST to the MCP. This will return if
9159          * this function should perform FUNC, PORT or COMMON HW
9160          * reset.
9161          */
9162         reset_code = bnx2x_send_unload_req(bp, unload_mode);
9163
9164         /*
9165          * (assumption: No Attention from MCP at this stage)
9166          * PMF probably in the middle of TX disable/enable transaction
9167          */
9168         rc = bnx2x_func_wait_started(bp);
9169         if (rc) {
9170                 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9171 #ifdef BNX2X_STOP_ON_ERROR
9172                 return;
9173 #endif
9174         }
9175
9176         /* Close multi and leading connections
9177          * Completions for ramrods are collected in a synchronous way
9178          */
9179         for_each_eth_queue(bp, i)
9180                 if (bnx2x_stop_queue(bp, i))
9181 #ifdef BNX2X_STOP_ON_ERROR
9182                         return;
9183 #else
9184                         goto unload_error;
9185 #endif
9186
9187         if (CNIC_LOADED(bp)) {
9188                 for_each_cnic_queue(bp, i)
9189                         if (bnx2x_stop_queue(bp, i))
9190 #ifdef BNX2X_STOP_ON_ERROR
9191                                 return;
9192 #else
9193                                 goto unload_error;
9194 #endif
9195         }
9196
9197         /* If SP settings didn't get completed so far - something
9198          * very wrong has happen.
9199          */
9200         if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
9201                 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9202
9203 #ifndef BNX2X_STOP_ON_ERROR
9204 unload_error:
9205 #endif
9206         rc = bnx2x_func_stop(bp);
9207         if (rc) {
9208                 BNX2X_ERR("Function stop failed!\n");
9209 #ifdef BNX2X_STOP_ON_ERROR
9210                 return;
9211 #endif
9212         }
9213
9214         /* stop_ptp should be after the Tx queues are drained to prevent
9215          * scheduling to the cancelled PTP work queue. It should also be after
9216          * function stop ramrod is sent, since as part of this ramrod FW access
9217          * PTP registers.
9218          */
9219         bnx2x_stop_ptp(bp);
9220
9221         /* Disable HW interrupts, NAPI */
9222         bnx2x_netif_stop(bp, 1);
9223         /* Delete all NAPI objects */
9224         bnx2x_del_all_napi(bp);
9225         if (CNIC_LOADED(bp))
9226                 bnx2x_del_all_napi_cnic(bp);
9227
9228         /* Release IRQs */
9229         bnx2x_free_irq(bp);
9230
9231         /* Reset the chip */
9232         rc = bnx2x_reset_hw(bp, reset_code);
9233         if (rc)
9234                 BNX2X_ERR("HW_RESET failed\n");
9235
9236         /* Report UNLOAD_DONE to MCP */
9237         bnx2x_send_unload_done(bp, keep_link);
9238 }
9239
9240 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
9241 {
9242         u32 val;
9243
9244         DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
9245
9246         if (CHIP_IS_E1(bp)) {
9247                 int port = BP_PORT(bp);
9248                 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
9249                         MISC_REG_AEU_MASK_ATTN_FUNC_0;
9250
9251                 val = REG_RD(bp, addr);
9252                 val &= ~(0x300);
9253                 REG_WR(bp, addr, val);
9254         } else {
9255                 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
9256                 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
9257                          MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
9258                 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
9259         }
9260 }
9261
9262 /* Close gates #2, #3 and #4: */
9263 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
9264 {
9265         u32 val;
9266
9267         /* Gates #2 and #4a are closed/opened for "not E1" only */
9268         if (!CHIP_IS_E1(bp)) {
9269                 /* #4 */
9270                 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
9271                 /* #2 */
9272                 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
9273         }
9274
9275         /* #3 */
9276         if (CHIP_IS_E1x(bp)) {
9277                 /* Prevent interrupts from HC on both ports */
9278                 val = REG_RD(bp, HC_REG_CONFIG_1);
9279                 REG_WR(bp, HC_REG_CONFIG_1,
9280                        (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
9281                        (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
9282
9283                 val = REG_RD(bp, HC_REG_CONFIG_0);
9284                 REG_WR(bp, HC_REG_CONFIG_0,
9285                        (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
9286                        (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
9287         } else {
9288                 /* Prevent incoming interrupts in IGU */
9289                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
9290
9291                 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
9292                        (!close) ?
9293                        (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
9294                        (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
9295         }
9296
9297         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
9298                 close ? "closing" : "opening");
9299         mmiowb();
9300 }
9301
9302 #define SHARED_MF_CLP_MAGIC  0x80000000 /* `magic' bit */
9303
9304 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
9305 {
9306         /* Do some magic... */
9307         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9308         *magic_val = val & SHARED_MF_CLP_MAGIC;
9309         MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
9310 }
9311
9312 /**
9313  * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9314  *
9315  * @bp:         driver handle
9316  * @magic_val:  old value of the `magic' bit.
9317  */
9318 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
9319 {
9320         /* Restore the `magic' bit value... */
9321         u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
9322         MF_CFG_WR(bp, shared_mf_config.clp_mb,
9323                 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
9324 }
9325
9326 /**
9327  * bnx2x_reset_mcp_prep - prepare for MCP reset.
9328  *
9329  * @bp:         driver handle
9330  * @magic_val:  old value of 'magic' bit.
9331  *
9332  * Takes care of CLP configurations.
9333  */
9334 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
9335 {
9336         u32 shmem;
9337         u32 validity_offset;
9338
9339         DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
9340
9341         /* Set `magic' bit in order to save MF config */
9342         if (!CHIP_IS_E1(bp))
9343                 bnx2x_clp_reset_prep(bp, magic_val);
9344
9345         /* Get shmem offset */
9346         shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9347         validity_offset =
9348                 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
9349
9350         /* Clear validity map flags */
9351         if (shmem > 0)
9352                 REG_WR(bp, shmem + validity_offset, 0);
9353 }
9354
9355 #define MCP_TIMEOUT      5000   /* 5 seconds (in ms) */
9356 #define MCP_ONE_TIMEOUT  100    /* 100 ms */
9357
9358 /**
9359  * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9360  *
9361  * @bp: driver handle
9362  */
9363 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
9364 {
9365         /* special handling for emulation and FPGA,
9366            wait 10 times longer */
9367         if (CHIP_REV_IS_SLOW(bp))
9368                 msleep(MCP_ONE_TIMEOUT*10);
9369         else
9370                 msleep(MCP_ONE_TIMEOUT);
9371 }
9372
9373 /*
9374  * initializes bp->common.shmem_base and waits for validity signature to appear
9375  */
9376 static int bnx2x_init_shmem(struct bnx2x *bp)
9377 {
9378         int cnt = 0;
9379         u32 val = 0;
9380
9381         do {
9382                 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
9383                 if (bp->common.shmem_base) {
9384                         val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
9385                         if (val & SHR_MEM_VALIDITY_MB)
9386                                 return 0;
9387                 }
9388
9389                 bnx2x_mcp_wait_one(bp);
9390
9391         } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
9392
9393         BNX2X_ERR("BAD MCP validity signature\n");
9394
9395         return -ENODEV;
9396 }
9397
9398 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
9399 {
9400         int rc = bnx2x_init_shmem(bp);
9401
9402         /* Restore the `magic' bit value */
9403         if (!CHIP_IS_E1(bp))
9404                 bnx2x_clp_reset_done(bp, magic_val);
9405
9406         return rc;
9407 }
9408
9409 static void bnx2x_pxp_prep(struct bnx2x *bp)
9410 {
9411         if (!CHIP_IS_E1(bp)) {
9412                 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
9413                 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
9414                 mmiowb();
9415         }
9416 }
9417
9418 /*
9419  * Reset the whole chip except for:
9420  *      - PCIE core
9421  *      - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9422  *              one reset bit)
9423  *      - IGU
9424  *      - MISC (including AEU)
9425  *      - GRC
9426  *      - RBCN, RBCP
9427  */
9428 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9429 {
9430         u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9431         u32 global_bits2, stay_reset2;
9432
9433         /*
9434          * Bits that have to be set in reset_mask2 if we want to reset 'global'
9435          * (per chip) blocks.
9436          */
9437         global_bits2 =
9438                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9439                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9440
9441         /* Don't reset the following blocks.
9442          * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9443          *            reset, as in 4 port device they might still be owned
9444          *            by the MCP (there is only one leader per path).
9445          */
9446         not_reset_mask1 =
9447                 MISC_REGISTERS_RESET_REG_1_RST_HC |
9448                 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9449                 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9450
9451         not_reset_mask2 =
9452                 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9453                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9454                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9455                 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9456                 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9457                 MISC_REGISTERS_RESET_REG_2_RST_GRC  |
9458                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9459                 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9460                 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9461                 MISC_REGISTERS_RESET_REG_2_PGLC |
9462                 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9463                 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9464                 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9465                 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9466                 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9467                 MISC_REGISTERS_RESET_REG_2_UMAC1;
9468
9469         /*
9470          * Keep the following blocks in reset:
9471          *  - all xxMACs are handled by the bnx2x_link code.
9472          */
9473         stay_reset2 =
9474                 MISC_REGISTERS_RESET_REG_2_XMAC |
9475                 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9476
9477         /* Full reset masks according to the chip */
9478         reset_mask1 = 0xffffffff;
9479
9480         if (CHIP_IS_E1(bp))
9481                 reset_mask2 = 0xffff;
9482         else if (CHIP_IS_E1H(bp))
9483                 reset_mask2 = 0x1ffff;
9484         else if (CHIP_IS_E2(bp))
9485                 reset_mask2 = 0xfffff;
9486         else /* CHIP_IS_E3 */
9487                 reset_mask2 = 0x3ffffff;
9488
9489         /* Don't reset global blocks unless we need to */
9490         if (!global)
9491                 reset_mask2 &= ~global_bits2;
9492
9493         /*
9494          * In case of attention in the QM, we need to reset PXP
9495          * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9496          * because otherwise QM reset would release 'close the gates' shortly
9497          * before resetting the PXP, then the PSWRQ would send a write
9498          * request to PGLUE. Then when PXP is reset, PGLUE would try to
9499          * read the payload data from PSWWR, but PSWWR would not
9500          * respond. The write queue in PGLUE would stuck, dmae commands
9501          * would not return. Therefore it's important to reset the second
9502          * reset register (containing the
9503          * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9504          * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9505          * bit).
9506          */
9507         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9508                reset_mask2 & (~not_reset_mask2));
9509
9510         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9511                reset_mask1 & (~not_reset_mask1));
9512
9513         barrier();
9514         mmiowb();
9515
9516         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9517                reset_mask2 & (~stay_reset2));
9518
9519         barrier();
9520         mmiowb();
9521
9522         REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9523         mmiowb();
9524 }
9525
9526 /**
9527  * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9528  * It should get cleared in no more than 1s.
9529  *
9530  * @bp: driver handle
9531  *
9532  * It should get cleared in no more than 1s. Returns 0 if
9533  * pending writes bit gets cleared.
9534  */
9535 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9536 {
9537         u32 cnt = 1000;
9538         u32 pend_bits = 0;
9539
9540         do {
9541                 pend_bits  = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9542
9543                 if (pend_bits == 0)
9544                         break;
9545
9546                 usleep_range(1000, 2000);
9547         } while (cnt-- > 0);
9548
9549         if (cnt <= 0) {
9550                 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9551                           pend_bits);
9552                 return -EBUSY;
9553         }
9554
9555         return 0;
9556 }
9557
9558 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9559 {
9560         int cnt = 1000;
9561         u32 val = 0;
9562         u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9563         u32 tags_63_32 = 0;
9564
9565         /* Empty the Tetris buffer, wait for 1s */
9566         do {
9567                 sr_cnt  = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9568                 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9569                 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9570                 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9571                 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9572                 if (CHIP_IS_E3(bp))
9573                         tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9574
9575                 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9576                     ((port_is_idle_0 & 0x1) == 0x1) &&
9577                     ((port_is_idle_1 & 0x1) == 0x1) &&
9578                     (pgl_exp_rom2 == 0xffffffff) &&
9579                     (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9580                         break;
9581                 usleep_range(1000, 2000);
9582         } while (cnt-- > 0);
9583
9584         if (cnt <= 0) {
9585                 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9586                 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9587                           sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9588                           pgl_exp_rom2);
9589                 return -EAGAIN;
9590         }
9591
9592         barrier();
9593
9594         /* Close gates #2, #3 and #4 */
9595         bnx2x_set_234_gates(bp, true);
9596
9597         /* Poll for IGU VQs for 57712 and newer chips */
9598         if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9599                 return -EAGAIN;
9600
9601         /* TBD: Indicate that "process kill" is in progress to MCP */
9602
9603         /* Clear "unprepared" bit */
9604         REG_WR(bp, MISC_REG_UNPREPARED, 0);
9605         barrier();
9606
9607         /* Make sure all is written to the chip before the reset */
9608         mmiowb();
9609
9610         /* Wait for 1ms to empty GLUE and PCI-E core queues,
9611          * PSWHST, GRC and PSWRD Tetris buffer.
9612          */
9613         usleep_range(1000, 2000);
9614
9615         /* Prepare to chip reset: */
9616         /* MCP */
9617         if (global)
9618                 bnx2x_reset_mcp_prep(bp, &val);
9619
9620         /* PXP */
9621         bnx2x_pxp_prep(bp);
9622         barrier();
9623
9624         /* reset the chip */
9625         bnx2x_process_kill_chip_reset(bp, global);
9626         barrier();
9627
9628         /* clear errors in PGB */
9629         if (!CHIP_IS_E1x(bp))
9630                 REG_WR(bp, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f);
9631
9632         /* Recover after reset: */
9633         /* MCP */
9634         if (global && bnx2x_reset_mcp_comp(bp, val))
9635                 return -EAGAIN;
9636
9637         /* TBD: Add resetting the NO_MCP mode DB here */
9638
9639         /* Open the gates #2, #3 and #4 */
9640         bnx2x_set_234_gates(bp, false);
9641
9642         /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9643          * reset state, re-enable attentions. */
9644
9645         return 0;
9646 }
9647
9648 static int bnx2x_leader_reset(struct bnx2x *bp)
9649 {
9650         int rc = 0;
9651         bool global = bnx2x_reset_is_global(bp);
9652         u32 load_code;
9653
9654         /* if not going to reset MCP - load "fake" driver to reset HW while
9655          * driver is owner of the HW
9656          */
9657         if (!global && !BP_NOMCP(bp)) {
9658                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9659                                              DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9660                 if (!load_code) {
9661                         BNX2X_ERR("MCP response failure, aborting\n");
9662                         rc = -EAGAIN;
9663                         goto exit_leader_reset;
9664                 }
9665                 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9666                     (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9667                         BNX2X_ERR("MCP unexpected resp, aborting\n");
9668                         rc = -EAGAIN;
9669                         goto exit_leader_reset2;
9670                 }
9671                 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9672                 if (!load_code) {
9673                         BNX2X_ERR("MCP response failure, aborting\n");
9674                         rc = -EAGAIN;
9675                         goto exit_leader_reset2;
9676                 }
9677         }
9678
9679         /* Try to recover after the failure */
9680         if (bnx2x_process_kill(bp, global)) {
9681                 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9682                           BP_PATH(bp));
9683                 rc = -EAGAIN;
9684                 goto exit_leader_reset2;
9685         }
9686
9687         /*
9688          * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9689          * state.
9690          */
9691         bnx2x_set_reset_done(bp);
9692         if (global)
9693                 bnx2x_clear_reset_global(bp);
9694
9695 exit_leader_reset2:
9696         /* unload "fake driver" if it was loaded */
9697         if (!global && !BP_NOMCP(bp)) {
9698                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9699                 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9700         }
9701 exit_leader_reset:
9702         bp->is_leader = 0;
9703         bnx2x_release_leader_lock(bp);
9704         smp_mb();
9705         return rc;
9706 }
9707
9708 static void bnx2x_recovery_failed(struct bnx2x *bp)
9709 {
9710         netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9711
9712         /* Disconnect this device */
9713         netif_device_detach(bp->dev);
9714
9715         /*
9716          * Block ifup for all function on this engine until "process kill"
9717          * or power cycle.
9718          */
9719         bnx2x_set_reset_in_progress(bp);
9720
9721         /* Shut down the power */
9722         bnx2x_set_power_state(bp, PCI_D3hot);
9723
9724         bp->recovery_state = BNX2X_RECOVERY_FAILED;
9725
9726         smp_mb();
9727 }
9728
9729 /*
9730  * Assumption: runs under rtnl lock. This together with the fact
9731  * that it's called only from bnx2x_sp_rtnl() ensure that it
9732  * will never be called when netif_running(bp->dev) is false.
9733  */
9734 static void bnx2x_parity_recover(struct bnx2x *bp)
9735 {
9736         bool global = false;
9737         u32 error_recovered, error_unrecovered;
9738         bool is_parity;
9739
9740         DP(NETIF_MSG_HW, "Handling parity\n");
9741         while (1) {
9742                 switch (bp->recovery_state) {
9743                 case BNX2X_RECOVERY_INIT:
9744                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9745                         is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9746                         WARN_ON(!is_parity);
9747
9748                         /* Try to get a LEADER_LOCK HW lock */
9749                         if (bnx2x_trylock_leader_lock(bp)) {
9750                                 bnx2x_set_reset_in_progress(bp);
9751                                 /*
9752                                  * Check if there is a global attention and if
9753                                  * there was a global attention, set the global
9754                                  * reset bit.
9755                                  */
9756
9757                                 if (global)
9758                                         bnx2x_set_reset_global(bp);
9759
9760                                 bp->is_leader = 1;
9761                         }
9762
9763                         /* Stop the driver */
9764                         /* If interface has been removed - break */
9765                         if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9766                                 return;
9767
9768                         bp->recovery_state = BNX2X_RECOVERY_WAIT;
9769
9770                         /* Ensure "is_leader", MCP command sequence and
9771                          * "recovery_state" update values are seen on other
9772                          * CPUs.
9773                          */
9774                         smp_mb();
9775                         break;
9776
9777                 case BNX2X_RECOVERY_WAIT:
9778                         DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9779                         if (bp->is_leader) {
9780                                 int other_engine = BP_PATH(bp) ? 0 : 1;
9781                                 bool other_load_status =
9782                                         bnx2x_get_load_status(bp, other_engine);
9783                                 bool load_status =
9784                                         bnx2x_get_load_status(bp, BP_PATH(bp));
9785                                 global = bnx2x_reset_is_global(bp);
9786
9787                                 /*
9788                                  * In case of a parity in a global block, let
9789                                  * the first leader that performs a
9790                                  * leader_reset() reset the global blocks in
9791                                  * order to clear global attentions. Otherwise
9792                                  * the gates will remain closed for that
9793                                  * engine.
9794                                  */
9795                                 if (load_status ||
9796                                     (global && other_load_status)) {
9797                                         /* Wait until all other functions get
9798                                          * down.
9799                                          */
9800                                         schedule_delayed_work(&bp->sp_rtnl_task,
9801                                                                 HZ/10);
9802                                         return;
9803                                 } else {
9804                                         /* If all other functions got down -
9805                                          * try to bring the chip back to
9806                                          * normal. In any case it's an exit
9807                                          * point for a leader.
9808                                          */
9809                                         if (bnx2x_leader_reset(bp)) {
9810                                                 bnx2x_recovery_failed(bp);
9811                                                 return;
9812                                         }
9813
9814                                         /* If we are here, means that the
9815                                          * leader has succeeded and doesn't
9816                                          * want to be a leader any more. Try
9817                                          * to continue as a none-leader.
9818                                          */
9819                                         break;
9820                                 }
9821                         } else { /* non-leader */
9822                                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9823                                         /* Try to get a LEADER_LOCK HW lock as
9824                                          * long as a former leader may have
9825                                          * been unloaded by the user or
9826                                          * released a leadership by another
9827                                          * reason.
9828                                          */
9829                                         if (bnx2x_trylock_leader_lock(bp)) {
9830                                                 /* I'm a leader now! Restart a
9831                                                  * switch case.
9832                                                  */
9833                                                 bp->is_leader = 1;
9834                                                 break;
9835                                         }
9836
9837                                         schedule_delayed_work(&bp->sp_rtnl_task,
9838                                                                 HZ/10);
9839                                         return;
9840
9841                                 } else {
9842                                         /*
9843                                          * If there was a global attention, wait
9844                                          * for it to be cleared.
9845                                          */
9846                                         if (bnx2x_reset_is_global(bp)) {
9847                                                 schedule_delayed_work(
9848                                                         &bp->sp_rtnl_task,
9849                                                         HZ/10);
9850                                                 return;
9851                                         }
9852
9853                                         error_recovered =
9854                                           bp->eth_stats.recoverable_error;
9855                                         error_unrecovered =
9856                                           bp->eth_stats.unrecoverable_error;
9857                                         bp->recovery_state =
9858                                                 BNX2X_RECOVERY_NIC_LOADING;
9859                                         if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9860                                                 error_unrecovered++;
9861                                                 netdev_err(bp->dev,
9862                                                            "Recovery failed. Power cycle needed\n");
9863                                                 /* Disconnect this device */
9864                                                 netif_device_detach(bp->dev);
9865                                                 /* Shut down the power */
9866                                                 bnx2x_set_power_state(
9867                                                         bp, PCI_D3hot);
9868                                                 smp_mb();
9869                                         } else {
9870                                                 bp->recovery_state =
9871                                                         BNX2X_RECOVERY_DONE;
9872                                                 error_recovered++;
9873                                                 smp_mb();
9874                                         }
9875                                         bp->eth_stats.recoverable_error =
9876                                                 error_recovered;
9877                                         bp->eth_stats.unrecoverable_error =
9878                                                 error_unrecovered;
9879
9880                                         return;
9881                                 }
9882                         }
9883                 default:
9884                         return;
9885                 }
9886         }
9887 }
9888
9889 static int bnx2x_close(struct net_device *dev);
9890
9891 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9892  * scheduled on a general queue in order to prevent a dead lock.
9893  */
9894 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9895 {
9896         struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9897
9898         rtnl_lock();
9899
9900         if (!netif_running(bp->dev)) {
9901                 rtnl_unlock();
9902                 return;
9903         }
9904
9905         if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9906 #ifdef BNX2X_STOP_ON_ERROR
9907                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9908                           "you will need to reboot when done\n");
9909                 goto sp_rtnl_not_reset;
9910 #endif
9911                 /*
9912                  * Clear all pending SP commands as we are going to reset the
9913                  * function anyway.
9914                  */
9915                 bp->sp_rtnl_state = 0;
9916                 smp_mb();
9917
9918                 bnx2x_parity_recover(bp);
9919
9920                 rtnl_unlock();
9921                 return;
9922         }
9923
9924         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9925 #ifdef BNX2X_STOP_ON_ERROR
9926                 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9927                           "you will need to reboot when done\n");
9928                 goto sp_rtnl_not_reset;
9929 #endif
9930
9931                 /*
9932                  * Clear all pending SP commands as we are going to reset the
9933                  * function anyway.
9934                  */
9935                 bp->sp_rtnl_state = 0;
9936                 smp_mb();
9937
9938                 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9939                 bnx2x_nic_load(bp, LOAD_NORMAL);
9940
9941                 rtnl_unlock();
9942                 return;
9943         }
9944 #ifdef BNX2X_STOP_ON_ERROR
9945 sp_rtnl_not_reset:
9946 #endif
9947         if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9948                 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9949         if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9950                 bnx2x_after_function_update(bp);
9951         /*
9952          * in case of fan failure we need to reset id if the "stop on error"
9953          * debug flag is set, since we trying to prevent permanent overheating
9954          * damage
9955          */
9956         if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9957                 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9958                 netif_device_detach(bp->dev);
9959                 bnx2x_close(bp->dev);
9960                 rtnl_unlock();
9961                 return;
9962         }
9963
9964         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9965                 DP(BNX2X_MSG_SP,
9966                    "sending set mcast vf pf channel message from rtnl sp-task\n");
9967                 bnx2x_vfpf_set_mcast(bp->dev);
9968         }
9969         if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
9970                                &bp->sp_rtnl_state)){
9971                 if (!test_bit(__LINK_STATE_NOCARRIER, &bp->dev->state)) {
9972                         bnx2x_tx_disable(bp);
9973                         BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
9974                 }
9975         }
9976
9977         if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE, &bp->sp_rtnl_state)) {
9978                 DP(BNX2X_MSG_SP, "Handling Rx Mode setting\n");
9979                 bnx2x_set_rx_mode_inner(bp);
9980         }
9981
9982         if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9983                                &bp->sp_rtnl_state))
9984                 bnx2x_pf_set_vfs_vlan(bp);
9985
9986         if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP, &bp->sp_rtnl_state)) {
9987                 bnx2x_dcbx_stop_hw_tx(bp);
9988                 bnx2x_dcbx_resume_hw_tx(bp);
9989         }
9990
9991         if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION,
9992                                &bp->sp_rtnl_state))
9993                 bnx2x_update_mng_version(bp);
9994
9995         /* work which needs rtnl lock not-taken (as it takes the lock itself and
9996          * can be called from other contexts as well)
9997          */
9998         rtnl_unlock();
9999
10000         /* enable SR-IOV if applicable */
10001         if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
10002                                                &bp->sp_rtnl_state)) {
10003                 bnx2x_disable_sriov(bp);
10004                 bnx2x_enable_sriov(bp);
10005         }
10006 }
10007
10008 static void bnx2x_period_task(struct work_struct *work)
10009 {
10010         struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
10011
10012         if (!netif_running(bp->dev))
10013                 goto period_task_exit;
10014
10015         if (CHIP_REV_IS_SLOW(bp)) {
10016                 BNX2X_ERR("period task called on emulation, ignoring\n");
10017                 goto period_task_exit;
10018         }
10019
10020         bnx2x_acquire_phy_lock(bp);
10021         /*
10022          * The barrier is needed to ensure the ordering between the writing to
10023          * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10024          * the reading here.
10025          */
10026         smp_mb();
10027         if (bp->port.pmf) {
10028                 bnx2x_period_func(&bp->link_params, &bp->link_vars);
10029
10030                 /* Re-queue task in 1 sec */
10031                 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
10032         }
10033
10034         bnx2x_release_phy_lock(bp);
10035 period_task_exit:
10036         return;
10037 }
10038
10039 /*
10040  * Init service functions
10041  */
10042
10043 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
10044 {
10045         u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
10046         u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
10047         return base + (BP_ABS_FUNC(bp)) * stride;
10048 }
10049
10050 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
10051                                         struct bnx2x_mac_vals *vals)
10052 {
10053         u32 val, base_addr, offset, mask, reset_reg;
10054         bool mac_stopped = false;
10055         u8 port = BP_PORT(bp);
10056
10057         /* reset addresses as they also mark which values were changed */
10058         vals->bmac_addr = 0;
10059         vals->umac_addr = 0;
10060         vals->xmac_addr = 0;
10061         vals->emac_addr = 0;
10062
10063         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
10064
10065         if (!CHIP_IS_E3(bp)) {
10066                 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
10067                 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
10068                 if ((mask & reset_reg) && val) {
10069                         u32 wb_data[2];
10070                         BNX2X_DEV_INFO("Disable bmac Rx\n");
10071                         base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
10072                                                 : NIG_REG_INGRESS_BMAC0_MEM;
10073                         offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
10074                                                 : BIGMAC_REGISTER_BMAC_CONTROL;
10075
10076                         /*
10077                          * use rd/wr since we cannot use dmae. This is safe
10078                          * since MCP won't access the bus due to the request
10079                          * to unload, and no function on the path can be
10080                          * loaded at this time.
10081                          */
10082                         wb_data[0] = REG_RD(bp, base_addr + offset);
10083                         wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
10084                         vals->bmac_addr = base_addr + offset;
10085                         vals->bmac_val[0] = wb_data[0];
10086                         vals->bmac_val[1] = wb_data[1];
10087                         wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
10088                         REG_WR(bp, vals->bmac_addr, wb_data[0]);
10089                         REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
10090                 }
10091                 BNX2X_DEV_INFO("Disable emac Rx\n");
10092                 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
10093                 vals->emac_val = REG_RD(bp, vals->emac_addr);
10094                 REG_WR(bp, vals->emac_addr, 0);
10095                 mac_stopped = true;
10096         } else {
10097                 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
10098                         BNX2X_DEV_INFO("Disable xmac Rx\n");
10099                         base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
10100                         val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
10101                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10102                                val & ~(1 << 1));
10103                         REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
10104                                val | (1 << 1));
10105                         vals->xmac_addr = base_addr + XMAC_REG_CTRL;
10106                         vals->xmac_val = REG_RD(bp, vals->xmac_addr);
10107                         REG_WR(bp, vals->xmac_addr, 0);
10108                         mac_stopped = true;
10109                 }
10110                 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
10111                 if (mask & reset_reg) {
10112                         BNX2X_DEV_INFO("Disable umac Rx\n");
10113                         base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
10114                         vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
10115                         vals->umac_val = REG_RD(bp, vals->umac_addr);
10116                         REG_WR(bp, vals->umac_addr, 0);
10117                         mac_stopped = true;
10118                 }
10119         }
10120
10121         if (mac_stopped)
10122                 msleep(20);
10123 }
10124
10125 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10126 #define BNX2X_PREV_UNDI_RCQ(val)        ((val) & 0xffff)
10127 #define BNX2X_PREV_UNDI_BD(val)         ((val) >> 16 & 0xffff)
10128 #define BNX2X_PREV_UNDI_PROD(rcq, bd)   ((bd) << 16 | (rcq))
10129
10130 #define BCM_5710_UNDI_FW_MF_MAJOR       (0x07)
10131 #define BCM_5710_UNDI_FW_MF_MINOR       (0x08)
10132 #define BCM_5710_UNDI_FW_MF_VERS        (0x05)
10133 #define BNX2X_PREV_UNDI_MF_PORT(p) (BAR_TSTRORM_INTMEM + 0x150c + ((p) << 4))
10134 #define BNX2X_PREV_UNDI_MF_FUNC(f) (BAR_TSTRORM_INTMEM + 0x184c + ((f) << 4))
10135
10136 static bool bnx2x_prev_is_after_undi(struct bnx2x *bp)
10137 {
10138         /* UNDI marks its presence in DORQ -
10139          * it initializes CID offset for normal bell to 0x7
10140          */
10141         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10142             MISC_REGISTERS_RESET_REG_1_RST_DORQ))
10143                 return false;
10144
10145         if (REG_RD(bp, DORQ_REG_NORM_CID_OFST) == 0x7) {
10146                 BNX2X_DEV_INFO("UNDI previously loaded\n");
10147                 return true;
10148         }
10149
10150         return false;
10151 }
10152
10153 static bool bnx2x_prev_unload_undi_fw_supports_mf(struct bnx2x *bp)
10154 {
10155         u8 major, minor, version;
10156         u32 fw;
10157
10158         /* Must check that FW is loaded */
10159         if (!(REG_RD(bp, MISC_REG_RESET_REG_1) &
10160              MISC_REGISTERS_RESET_REG_1_RST_XSEM)) {
10161                 BNX2X_DEV_INFO("XSEM is reset - UNDI MF FW is not loaded\n");
10162                 return false;
10163         }
10164
10165         /* Read Currently loaded FW version */
10166         fw = REG_RD(bp, XSEM_REG_PRAM);
10167         major = fw & 0xff;
10168         minor = (fw >> 0x8) & 0xff;
10169         version = (fw >> 0x10) & 0xff;
10170         BNX2X_DEV_INFO("Loaded FW: 0x%08x: Major 0x%02x Minor 0x%02x Version 0x%02x\n",
10171                        fw, major, minor, version);
10172
10173         if (major > BCM_5710_UNDI_FW_MF_MAJOR)
10174                 return true;
10175
10176         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10177             (minor > BCM_5710_UNDI_FW_MF_MINOR))
10178                 return true;
10179
10180         if ((major == BCM_5710_UNDI_FW_MF_MAJOR) &&
10181             (minor == BCM_5710_UNDI_FW_MF_MINOR) &&
10182             (version >= BCM_5710_UNDI_FW_MF_VERS))
10183                 return true;
10184
10185         return false;
10186 }
10187
10188 static void bnx2x_prev_unload_undi_mf(struct bnx2x *bp)
10189 {
10190         int i;
10191
10192         /* Due to legacy (FW) code, the first function on each engine has a
10193          * different offset macro from the rest of the functions.
10194          * Setting this for all 8 functions is harmless regardless of whether
10195          * this is actually a multi-function device.
10196          */
10197         for (i = 0; i < 2; i++)
10198                 REG_WR(bp, BNX2X_PREV_UNDI_MF_PORT(i), 1);
10199
10200         for (i = 2; i < 8; i++)
10201                 REG_WR(bp, BNX2X_PREV_UNDI_MF_FUNC(i - 2), 1);
10202
10203         BNX2X_DEV_INFO("UNDI FW (MF) set to discard\n");
10204 }
10205
10206 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
10207 {
10208         u16 rcq, bd;
10209         u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
10210
10211         rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
10212         bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
10213
10214         tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
10215         REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
10216
10217         BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10218                        port, bd, rcq);
10219 }
10220
10221 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
10222 {
10223         u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
10224                                   DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
10225         if (!rc) {
10226                 BNX2X_ERR("MCP response failure, aborting\n");
10227                 return -EBUSY;
10228         }
10229
10230         return 0;
10231 }
10232
10233 static struct bnx2x_prev_path_list *
10234                 bnx2x_prev_path_get_entry(struct bnx2x *bp)
10235 {
10236         struct bnx2x_prev_path_list *tmp_list;
10237
10238         list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
10239                 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
10240                     bp->pdev->bus->number == tmp_list->bus &&
10241                     BP_PATH(bp) == tmp_list->path)
10242                         return tmp_list;
10243
10244         return NULL;
10245 }
10246
10247 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
10248 {
10249         struct bnx2x_prev_path_list *tmp_list;
10250         int rc;
10251
10252         rc = down_interruptible(&bnx2x_prev_sem);
10253         if (rc) {
10254                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10255                 return rc;
10256         }
10257
10258         tmp_list = bnx2x_prev_path_get_entry(bp);
10259         if (tmp_list) {
10260                 tmp_list->aer = 1;
10261                 rc = 0;
10262         } else {
10263                 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10264                           BP_PATH(bp));
10265         }
10266
10267         up(&bnx2x_prev_sem);
10268
10269         return rc;
10270 }
10271
10272 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
10273 {
10274         struct bnx2x_prev_path_list *tmp_list;
10275         bool rc = false;
10276
10277         if (down_trylock(&bnx2x_prev_sem))
10278                 return false;
10279
10280         tmp_list = bnx2x_prev_path_get_entry(bp);
10281         if (tmp_list) {
10282                 if (tmp_list->aer) {
10283                         DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
10284                            BP_PATH(bp));
10285                 } else {
10286                         rc = true;
10287                         BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10288                                        BP_PATH(bp));
10289                 }
10290         }
10291
10292         up(&bnx2x_prev_sem);
10293
10294         return rc;
10295 }
10296
10297 bool bnx2x_port_after_undi(struct bnx2x *bp)
10298 {
10299         struct bnx2x_prev_path_list *entry;
10300         bool val;
10301
10302         down(&bnx2x_prev_sem);
10303
10304         entry = bnx2x_prev_path_get_entry(bp);
10305         val = !!(entry && (entry->undi & (1 << BP_PORT(bp))));
10306
10307         up(&bnx2x_prev_sem);
10308
10309         return val;
10310 }
10311
10312 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
10313 {
10314         struct bnx2x_prev_path_list *tmp_list;
10315         int rc;
10316
10317         rc = down_interruptible(&bnx2x_prev_sem);
10318         if (rc) {
10319                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10320                 return rc;
10321         }
10322
10323         /* Check whether the entry for this path already exists */
10324         tmp_list = bnx2x_prev_path_get_entry(bp);
10325         if (tmp_list) {
10326                 if (!tmp_list->aer) {
10327                         BNX2X_ERR("Re-Marking the path.\n");
10328                 } else {
10329                         DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
10330                            BP_PATH(bp));
10331                         tmp_list->aer = 0;
10332                 }
10333                 up(&bnx2x_prev_sem);
10334                 return 0;
10335         }
10336         up(&bnx2x_prev_sem);
10337
10338         /* Create an entry for this path and add it */
10339         tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
10340         if (!tmp_list) {
10341                 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10342                 return -ENOMEM;
10343         }
10344
10345         tmp_list->bus = bp->pdev->bus->number;
10346         tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
10347         tmp_list->path = BP_PATH(bp);
10348         tmp_list->aer = 0;
10349         tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
10350
10351         rc = down_interruptible(&bnx2x_prev_sem);
10352         if (rc) {
10353                 BNX2X_ERR("Received %d when tried to take lock\n", rc);
10354                 kfree(tmp_list);
10355         } else {
10356                 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
10357                    BP_PATH(bp));
10358                 list_add(&tmp_list->list, &bnx2x_prev_list);
10359                 up(&bnx2x_prev_sem);
10360         }
10361
10362         return rc;
10363 }
10364
10365 static int bnx2x_do_flr(struct bnx2x *bp)
10366 {
10367         struct pci_dev *dev = bp->pdev;
10368
10369         if (CHIP_IS_E1x(bp)) {
10370                 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10371                 return -EINVAL;
10372         }
10373
10374         /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10375         if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
10376                 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10377                           bp->common.bc_ver);
10378                 return -EINVAL;
10379         }
10380
10381         if (!pci_wait_for_pending_transaction(dev))
10382                 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
10383
10384         BNX2X_DEV_INFO("Initiating FLR\n");
10385         bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
10386
10387         return 0;
10388 }
10389
10390 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
10391 {
10392         int rc;
10393
10394         BNX2X_DEV_INFO("Uncommon unload Flow\n");
10395
10396         /* Test if previous unload process was already finished for this path */
10397         if (bnx2x_prev_is_path_marked(bp))
10398                 return bnx2x_prev_mcp_done(bp);
10399
10400         BNX2X_DEV_INFO("Path is unmarked\n");
10401
10402         /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10403         if (bnx2x_prev_is_after_undi(bp))
10404                 goto out;
10405
10406         /* If function has FLR capabilities, and existing FW version matches
10407          * the one required, then FLR will be sufficient to clean any residue
10408          * left by previous driver
10409          */
10410         rc = bnx2x_compare_fw_ver(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION, false);
10411
10412         if (!rc) {
10413                 /* fw version is good */
10414                 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10415                 rc = bnx2x_do_flr(bp);
10416         }
10417
10418         if (!rc) {
10419                 /* FLR was performed */
10420                 BNX2X_DEV_INFO("FLR successful\n");
10421                 return 0;
10422         }
10423
10424         BNX2X_DEV_INFO("Could not FLR\n");
10425
10426 out:
10427         /* Close the MCP request, return failure*/
10428         rc = bnx2x_prev_mcp_done(bp);
10429         if (!rc)
10430                 rc = BNX2X_PREV_WAIT_NEEDED;
10431
10432         return rc;
10433 }
10434
10435 static int bnx2x_prev_unload_common(struct bnx2x *bp)
10436 {
10437         u32 reset_reg, tmp_reg = 0, rc;
10438         bool prev_undi = false;
10439         struct bnx2x_mac_vals mac_vals;
10440
10441         /* It is possible a previous function received 'common' answer,
10442          * but hasn't loaded yet, therefore creating a scenario of
10443          * multiple functions receiving 'common' on the same path.
10444          */
10445         BNX2X_DEV_INFO("Common unload Flow\n");
10446
10447         memset(&mac_vals, 0, sizeof(mac_vals));
10448
10449         if (bnx2x_prev_is_path_marked(bp))
10450                 return bnx2x_prev_mcp_done(bp);
10451
10452         reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
10453
10454         /* Reset should be performed after BRB is emptied */
10455         if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
10456                 u32 timer_count = 1000;
10457                 bool need_write = true;
10458
10459                 /* Close the MAC Rx to prevent BRB from filling up */
10460                 bnx2x_prev_unload_close_mac(bp, &mac_vals);
10461
10462                 /* close LLH filters towards the BRB */
10463                 bnx2x_set_rx_filter(&bp->link_params, 0);
10464
10465                 /* Check if the UNDI driver was previously loaded */
10466                 if (bnx2x_prev_is_after_undi(bp)) {
10467                         prev_undi = true;
10468                         /* clear the UNDI indication */
10469                         REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
10470                         /* clear possible idle check errors */
10471                         REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
10472                 }
10473                 if (!CHIP_IS_E1x(bp))
10474                         /* block FW from writing to host */
10475                         REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
10476
10477                 /* wait until BRB is empty */
10478                 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10479                 while (timer_count) {
10480                         u32 prev_brb = tmp_reg;
10481
10482                         tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
10483                         if (!tmp_reg)
10484                                 break;
10485
10486                         BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
10487
10488                         /* reset timer as long as BRB actually gets emptied */
10489                         if (prev_brb > tmp_reg)
10490                                 timer_count = 1000;
10491                         else
10492                                 timer_count--;
10493
10494                         /* New UNDI FW supports MF and contains better
10495                          * cleaning methods - might be redundant but harmless.
10496                          */
10497                         if (bnx2x_prev_unload_undi_fw_supports_mf(bp)) {
10498                                 if (need_write) {
10499                                         bnx2x_prev_unload_undi_mf(bp);
10500                                         need_write = false;
10501                                 }
10502                         } else if (prev_undi) {
10503                                 /* If UNDI resides in memory,
10504                                  * manually increment it
10505                                  */
10506                                 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
10507                         }
10508                         udelay(10);
10509                 }
10510
10511                 if (!timer_count)
10512                         BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10513         }
10514
10515         /* No packets are in the pipeline, path is ready for reset */
10516         bnx2x_reset_common(bp);
10517
10518         if (mac_vals.xmac_addr)
10519                 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
10520         if (mac_vals.umac_addr)
10521                 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
10522         if (mac_vals.emac_addr)
10523                 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
10524         if (mac_vals.bmac_addr) {
10525                 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
10526                 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
10527         }
10528
10529         rc = bnx2x_prev_mark_path(bp, prev_undi);
10530         if (rc) {
10531                 bnx2x_prev_mcp_done(bp);
10532                 return rc;
10533         }
10534
10535         return bnx2x_prev_mcp_done(bp);
10536 }
10537
10538 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10539  * and boot began, or when kdump kernel was loaded. Either case would invalidate
10540  * the addresses of the transaction, resulting in was-error bit set in the pci
10541  * causing all hw-to-host pcie transactions to timeout. If this happened we want
10542  * to clear the interrupt which detected this from the pglueb and the was done
10543  * bit
10544  */
10545 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10546 {
10547         if (!CHIP_IS_E1x(bp)) {
10548                 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10549                 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10550                         DP(BNX2X_MSG_SP,
10551                            "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10552                         REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10553                                1 << BP_FUNC(bp));
10554                 }
10555         }
10556 }
10557
10558 static int bnx2x_prev_unload(struct bnx2x *bp)
10559 {
10560         int time_counter = 10;
10561         u32 rc, fw, hw_lock_reg, hw_lock_val;
10562         BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10563
10564         /* clear hw from errors which may have resulted from an interrupted
10565          * dmae transaction.
10566          */
10567         bnx2x_prev_interrupted_dmae(bp);
10568
10569         /* Release previously held locks */
10570         hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10571                       (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10572                       (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10573
10574         hw_lock_val = REG_RD(bp, hw_lock_reg);
10575         if (hw_lock_val) {
10576                 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10577                         BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10578                         REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10579                                (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10580                 }
10581
10582                 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10583                 REG_WR(bp, hw_lock_reg, 0xffffffff);
10584         } else
10585                 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10586
10587         if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10588                 BNX2X_DEV_INFO("Release previously held alr\n");
10589                 bnx2x_release_alr(bp);
10590         }
10591
10592         do {
10593                 int aer = 0;
10594                 /* Lock MCP using an unload request */
10595                 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10596                 if (!fw) {
10597                         BNX2X_ERR("MCP response failure, aborting\n");
10598                         rc = -EBUSY;
10599                         break;
10600                 }
10601
10602                 rc = down_interruptible(&bnx2x_prev_sem);
10603                 if (rc) {
10604                         BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10605                                   rc);
10606                 } else {
10607                         /* If Path is marked by EEH, ignore unload status */
10608                         aer = !!(bnx2x_prev_path_get_entry(bp) &&
10609                                  bnx2x_prev_path_get_entry(bp)->aer);
10610                         up(&bnx2x_prev_sem);
10611                 }
10612
10613                 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10614                         rc = bnx2x_prev_unload_common(bp);
10615                         break;
10616                 }
10617
10618                 /* non-common reply from MCP might require looping */
10619                 rc = bnx2x_prev_unload_uncommon(bp);
10620                 if (rc != BNX2X_PREV_WAIT_NEEDED)
10621                         break;
10622
10623                 msleep(20);
10624         } while (--time_counter);
10625
10626         if (!time_counter || rc) {
10627                 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10628                 rc = -EPROBE_DEFER;
10629         }
10630
10631         /* Mark function if its port was used to boot from SAN */
10632         if (bnx2x_port_after_undi(bp))
10633                 bp->link_params.feature_config_flags |=
10634                         FEATURE_CONFIG_BOOT_FROM_SAN;
10635
10636         BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10637
10638         return rc;
10639 }
10640
10641 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10642 {
10643         u32 val, val2, val3, val4, id, boot_mode;
10644         u16 pmc;
10645
10646         /* Get the chip revision id and number. */
10647         /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10648         val = REG_RD(bp, MISC_REG_CHIP_NUM);
10649         id = ((val & 0xffff) << 16);
10650         val = REG_RD(bp, MISC_REG_CHIP_REV);
10651         id |= ((val & 0xf) << 12);
10652
10653         /* Metal is read from PCI regs, but we can't access >=0x400 from
10654          * the configuration space (so we need to reg_rd)
10655          */
10656         val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10657         id |= (((val >> 24) & 0xf) << 4);
10658         val = REG_RD(bp, MISC_REG_BOND_ID);
10659         id |= (val & 0xf);
10660         bp->common.chip_id = id;
10661
10662         /* force 57811 according to MISC register */
10663         if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10664                 if (CHIP_IS_57810(bp))
10665                         bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10666                                 (bp->common.chip_id & 0x0000FFFF);
10667                 else if (CHIP_IS_57810_MF(bp))
10668                         bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10669                                 (bp->common.chip_id & 0x0000FFFF);
10670                 bp->common.chip_id |= 0x1;
10671         }
10672
10673         /* Set doorbell size */
10674         bp->db_size = (1 << BNX2X_DB_SHIFT);
10675
10676         if (!CHIP_IS_E1x(bp)) {
10677                 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10678                 if ((val & 1) == 0)
10679                         val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10680                 else
10681                         val = (val >> 1) & 1;
10682                 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10683                                                        "2_PORT_MODE");
10684                 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10685                                                  CHIP_2_PORT_MODE;
10686
10687                 if (CHIP_MODE_IS_4_PORT(bp))
10688                         bp->pfid = (bp->pf_num >> 1);   /* 0..3 */
10689                 else
10690                         bp->pfid = (bp->pf_num & 0x6);  /* 0, 2, 4, 6 */
10691         } else {
10692                 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10693                 bp->pfid = bp->pf_num;                  /* 0..7 */
10694         }
10695
10696         BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10697
10698         bp->link_params.chip_id = bp->common.chip_id;
10699         BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10700
10701         val = (REG_RD(bp, 0x2874) & 0x55);
10702         if ((bp->common.chip_id & 0x1) ||
10703             (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10704                 bp->flags |= ONE_PORT_FLAG;
10705                 BNX2X_DEV_INFO("single port device\n");
10706         }
10707
10708         val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10709         bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10710                                  (val & MCPR_NVM_CFG4_FLASH_SIZE));
10711         BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10712                        bp->common.flash_size, bp->common.flash_size);
10713
10714         bnx2x_init_shmem(bp);
10715
10716         bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10717                                         MISC_REG_GENERIC_CR_1 :
10718                                         MISC_REG_GENERIC_CR_0));
10719
10720         bp->link_params.shmem_base = bp->common.shmem_base;
10721         bp->link_params.shmem2_base = bp->common.shmem2_base;
10722         if (SHMEM2_RD(bp, size) >
10723             (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10724                 bp->link_params.lfa_base =
10725                 REG_RD(bp, bp->common.shmem2_base +
10726                        (u32)offsetof(struct shmem2_region,
10727                                      lfa_host_addr[BP_PORT(bp)]));
10728         else
10729                 bp->link_params.lfa_base = 0;
10730         BNX2X_DEV_INFO("shmem offset 0x%x  shmem2 offset 0x%x\n",
10731                        bp->common.shmem_base, bp->common.shmem2_base);
10732
10733         if (!bp->common.shmem_base) {
10734                 BNX2X_DEV_INFO("MCP not active\n");
10735                 bp->flags |= NO_MCP_FLAG;
10736                 return;
10737         }
10738
10739         bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10740         BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10741
10742         bp->link_params.hw_led_mode = ((bp->common.hw_config &
10743                                         SHARED_HW_CFG_LED_MODE_MASK) >>
10744                                        SHARED_HW_CFG_LED_MODE_SHIFT);
10745
10746         bp->link_params.feature_config_flags = 0;
10747         val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10748         if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10749                 bp->link_params.feature_config_flags |=
10750                                 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10751         else
10752                 bp->link_params.feature_config_flags &=
10753                                 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10754
10755         val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10756         bp->common.bc_ver = val;
10757         BNX2X_DEV_INFO("bc_ver %X\n", val);
10758         if (val < BNX2X_BC_VER) {
10759                 /* for now only warn
10760                  * later we might need to enforce this */
10761                 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10762                           BNX2X_BC_VER, val);
10763         }
10764         bp->link_params.feature_config_flags |=
10765                                 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10766                                 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10767
10768         bp->link_params.feature_config_flags |=
10769                 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10770                 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10771         bp->link_params.feature_config_flags |=
10772                 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10773                 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10774         bp->link_params.feature_config_flags |=
10775                 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10776                 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10777
10778         bp->link_params.feature_config_flags |=
10779                 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10780                 FEATURE_CONFIG_MT_SUPPORT : 0;
10781
10782         bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10783                         BC_SUPPORTS_PFC_STATS : 0;
10784
10785         bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10786                         BC_SUPPORTS_FCOE_FEATURES : 0;
10787
10788         bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10789                         BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10790
10791         bp->flags |= (val >= REQ_BC_VER_4_RMMOD_CMD) ?
10792                         BC_SUPPORTS_RMMOD_CMD : 0;
10793
10794         boot_mode = SHMEM_RD(bp,
10795                         dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10796                         PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10797         switch (boot_mode) {
10798         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10799                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10800                 break;
10801         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10802                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10803                 break;
10804         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10805                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10806                 break;
10807         case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10808                 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10809                 break;
10810         }
10811
10812         pci_read_config_word(bp->pdev, bp->pdev->pm_cap + PCI_PM_PMC, &pmc);
10813         bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10814
10815         BNX2X_DEV_INFO("%sWoL capable\n",
10816                        (bp->flags & NO_WOL_FLAG) ? "not " : "");
10817
10818         val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10819         val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10820         val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10821         val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10822
10823         dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10824                  val, val2, val3, val4);
10825 }
10826
10827 #define IGU_FID(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10828 #define IGU_VEC(val)    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10829
10830 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10831 {
10832         int pfid = BP_FUNC(bp);
10833         int igu_sb_id;
10834         u32 val;
10835         u8 fid, igu_sb_cnt = 0;
10836
10837         bp->igu_base_sb = 0xff;
10838         if (CHIP_INT_MODE_IS_BC(bp)) {
10839                 int vn = BP_VN(bp);
10840                 igu_sb_cnt = bp->igu_sb_cnt;
10841                 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10842                         FP_SB_MAX_E1x;
10843
10844                 bp->igu_dsb_id =  E1HVN_MAX * FP_SB_MAX_E1x +
10845                         (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10846
10847                 return 0;
10848         }
10849
10850         /* IGU in normal mode - read CAM */
10851         for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10852              igu_sb_id++) {
10853                 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10854                 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10855                         continue;
10856                 fid = IGU_FID(val);
10857                 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10858                         if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10859                                 continue;
10860                         if (IGU_VEC(val) == 0)
10861                                 /* default status block */
10862                                 bp->igu_dsb_id = igu_sb_id;
10863                         else {
10864                                 if (bp->igu_base_sb == 0xff)
10865                                         bp->igu_base_sb = igu_sb_id;
10866                                 igu_sb_cnt++;
10867                         }
10868                 }
10869         }
10870
10871 #ifdef CONFIG_PCI_MSI
10872         /* Due to new PF resource allocation by MFW T7.4 and above, it's
10873          * optional that number of CAM entries will not be equal to the value
10874          * advertised in PCI.
10875          * Driver should use the minimal value of both as the actual status
10876          * block count
10877          */
10878         bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10879 #endif
10880
10881         if (igu_sb_cnt == 0) {
10882                 BNX2X_ERR("CAM configuration error\n");
10883                 return -EINVAL;
10884         }
10885
10886         return 0;
10887 }
10888
10889 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10890 {
10891         int cfg_size = 0, idx, port = BP_PORT(bp);
10892
10893         /* Aggregation of supported attributes of all external phys */
10894         bp->port.supported[0] = 0;
10895         bp->port.supported[1] = 0;
10896         switch (bp->link_params.num_phys) {
10897         case 1:
10898                 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10899                 cfg_size = 1;
10900                 break;
10901         case 2:
10902                 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10903                 cfg_size = 1;
10904                 break;
10905         case 3:
10906                 if (bp->link_params.multi_phy_config &
10907                     PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10908                         bp->port.supported[1] =
10909                                 bp->link_params.phy[EXT_PHY1].supported;
10910                         bp->port.supported[0] =
10911                                 bp->link_params.phy[EXT_PHY2].supported;
10912                 } else {
10913                         bp->port.supported[0] =
10914                                 bp->link_params.phy[EXT_PHY1].supported;
10915                         bp->port.supported[1] =
10916                                 bp->link_params.phy[EXT_PHY2].supported;
10917                 }
10918                 cfg_size = 2;
10919                 break;
10920         }
10921
10922         if (!(bp->port.supported[0] || bp->port.supported[1])) {
10923                 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10924                            SHMEM_RD(bp,
10925                            dev_info.port_hw_config[port].external_phy_config),
10926                            SHMEM_RD(bp,
10927                            dev_info.port_hw_config[port].external_phy_config2));
10928                         return;
10929         }
10930
10931         if (CHIP_IS_E3(bp))
10932                 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10933         else {
10934                 switch (switch_cfg) {
10935                 case SWITCH_CFG_1G:
10936                         bp->port.phy_addr = REG_RD(
10937                                 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10938                         break;
10939                 case SWITCH_CFG_10G:
10940                         bp->port.phy_addr = REG_RD(
10941                                 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10942                         break;
10943                 default:
10944                         BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10945                                   bp->port.link_config[0]);
10946                         return;
10947                 }
10948         }
10949         BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10950         /* mask what we support according to speed_cap_mask per configuration */
10951         for (idx = 0; idx < cfg_size; idx++) {
10952                 if (!(bp->link_params.speed_cap_mask[idx] &
10953                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10954                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10955
10956                 if (!(bp->link_params.speed_cap_mask[idx] &
10957                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10958                         bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10959
10960                 if (!(bp->link_params.speed_cap_mask[idx] &
10961                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10962                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10963
10964                 if (!(bp->link_params.speed_cap_mask[idx] &
10965                                 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10966                         bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10967
10968                 if (!(bp->link_params.speed_cap_mask[idx] &
10969                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10970                         bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10971                                                      SUPPORTED_1000baseT_Full);
10972
10973                 if (!(bp->link_params.speed_cap_mask[idx] &
10974                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10975                         bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10976
10977                 if (!(bp->link_params.speed_cap_mask[idx] &
10978                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10979                         bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10980
10981                 if (!(bp->link_params.speed_cap_mask[idx] &
10982                                         PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
10983                         bp->port.supported[idx] &= ~SUPPORTED_20000baseKR2_Full;
10984         }
10985
10986         BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10987                        bp->port.supported[1]);
10988 }
10989
10990 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10991 {
10992         u32 link_config, idx, cfg_size = 0;
10993         bp->port.advertising[0] = 0;
10994         bp->port.advertising[1] = 0;
10995         switch (bp->link_params.num_phys) {
10996         case 1:
10997         case 2:
10998                 cfg_size = 1;
10999                 break;
11000         case 3:
11001                 cfg_size = 2;
11002                 break;
11003         }
11004         for (idx = 0; idx < cfg_size; idx++) {
11005                 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
11006                 link_config = bp->port.link_config[idx];
11007                 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
11008                 case PORT_FEATURE_LINK_SPEED_AUTO:
11009                         if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
11010                                 bp->link_params.req_line_speed[idx] =
11011                                         SPEED_AUTO_NEG;
11012                                 bp->port.advertising[idx] |=
11013                                         bp->port.supported[idx];
11014                                 if (bp->link_params.phy[EXT_PHY1].type ==
11015                                     PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
11016                                         bp->port.advertising[idx] |=
11017                                         (SUPPORTED_100baseT_Half |
11018                                          SUPPORTED_100baseT_Full);
11019                         } else {
11020                                 /* force 10G, no AN */
11021                                 bp->link_params.req_line_speed[idx] =
11022                                         SPEED_10000;
11023                                 bp->port.advertising[idx] |=
11024                                         (ADVERTISED_10000baseT_Full |
11025                                          ADVERTISED_FIBRE);
11026                                 continue;
11027                         }
11028                         break;
11029
11030                 case PORT_FEATURE_LINK_SPEED_10M_FULL:
11031                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
11032                                 bp->link_params.req_line_speed[idx] =
11033                                         SPEED_10;
11034                                 bp->port.advertising[idx] |=
11035                                         (ADVERTISED_10baseT_Full |
11036                                          ADVERTISED_TP);
11037                         } else {
11038                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11039                                             link_config,
11040                                     bp->link_params.speed_cap_mask[idx]);
11041                                 return;
11042                         }
11043                         break;
11044
11045                 case PORT_FEATURE_LINK_SPEED_10M_HALF:
11046                         if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
11047                                 bp->link_params.req_line_speed[idx] =
11048                                         SPEED_10;
11049                                 bp->link_params.req_duplex[idx] =
11050                                         DUPLEX_HALF;
11051                                 bp->port.advertising[idx] |=
11052                                         (ADVERTISED_10baseT_Half |
11053                                          ADVERTISED_TP);
11054                         } else {
11055                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11056                                             link_config,
11057                                           bp->link_params.speed_cap_mask[idx]);
11058                                 return;
11059                         }
11060                         break;
11061
11062                 case PORT_FEATURE_LINK_SPEED_100M_FULL:
11063                         if (bp->port.supported[idx] &
11064                             SUPPORTED_100baseT_Full) {
11065                                 bp->link_params.req_line_speed[idx] =
11066                                         SPEED_100;
11067                                 bp->port.advertising[idx] |=
11068                                         (ADVERTISED_100baseT_Full |
11069                                          ADVERTISED_TP);
11070                         } else {
11071                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11072                                             link_config,
11073                                           bp->link_params.speed_cap_mask[idx]);
11074                                 return;
11075                         }
11076                         break;
11077
11078                 case PORT_FEATURE_LINK_SPEED_100M_HALF:
11079                         if (bp->port.supported[idx] &
11080                             SUPPORTED_100baseT_Half) {
11081                                 bp->link_params.req_line_speed[idx] =
11082                                                                 SPEED_100;
11083                                 bp->link_params.req_duplex[idx] =
11084                                                                 DUPLEX_HALF;
11085                                 bp->port.advertising[idx] |=
11086                                         (ADVERTISED_100baseT_Half |
11087                                          ADVERTISED_TP);
11088                         } else {
11089                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11090                                     link_config,
11091                                     bp->link_params.speed_cap_mask[idx]);
11092                                 return;
11093                         }
11094                         break;
11095
11096                 case PORT_FEATURE_LINK_SPEED_1G:
11097                         if (bp->port.supported[idx] &
11098                             SUPPORTED_1000baseT_Full) {
11099                                 bp->link_params.req_line_speed[idx] =
11100                                         SPEED_1000;
11101                                 bp->port.advertising[idx] |=
11102                                         (ADVERTISED_1000baseT_Full |
11103                                          ADVERTISED_TP);
11104                         } else {
11105                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11106                                     link_config,
11107                                     bp->link_params.speed_cap_mask[idx]);
11108                                 return;
11109                         }
11110                         break;
11111
11112                 case PORT_FEATURE_LINK_SPEED_2_5G:
11113                         if (bp->port.supported[idx] &
11114                             SUPPORTED_2500baseX_Full) {
11115                                 bp->link_params.req_line_speed[idx] =
11116                                         SPEED_2500;
11117                                 bp->port.advertising[idx] |=
11118                                         (ADVERTISED_2500baseX_Full |
11119                                                 ADVERTISED_TP);
11120                         } else {
11121                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11122                                     link_config,
11123                                     bp->link_params.speed_cap_mask[idx]);
11124                                 return;
11125                         }
11126                         break;
11127
11128                 case PORT_FEATURE_LINK_SPEED_10G_CX4:
11129                         if (bp->port.supported[idx] &
11130                             SUPPORTED_10000baseT_Full) {
11131                                 bp->link_params.req_line_speed[idx] =
11132                                         SPEED_10000;
11133                                 bp->port.advertising[idx] |=
11134                                         (ADVERTISED_10000baseT_Full |
11135                                                 ADVERTISED_FIBRE);
11136                         } else {
11137                                 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x  speed_cap_mask 0x%x\n",
11138                                     link_config,
11139                                     bp->link_params.speed_cap_mask[idx]);
11140                                 return;
11141                         }
11142                         break;
11143                 case PORT_FEATURE_LINK_SPEED_20G:
11144                         bp->link_params.req_line_speed[idx] = SPEED_20000;
11145
11146                         break;
11147                 default:
11148                         BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11149                                   link_config);
11150                                 bp->link_params.req_line_speed[idx] =
11151                                                         SPEED_AUTO_NEG;
11152                                 bp->port.advertising[idx] =
11153                                                 bp->port.supported[idx];
11154                         break;
11155                 }
11156
11157                 bp->link_params.req_flow_ctrl[idx] = (link_config &
11158                                          PORT_FEATURE_FLOW_CONTROL_MASK);
11159                 if (bp->link_params.req_flow_ctrl[idx] ==
11160                     BNX2X_FLOW_CTRL_AUTO) {
11161                         if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
11162                                 bp->link_params.req_flow_ctrl[idx] =
11163                                                         BNX2X_FLOW_CTRL_NONE;
11164                         else
11165                                 bnx2x_set_requested_fc(bp);
11166                 }
11167
11168                 BNX2X_DEV_INFO("req_line_speed %d  req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11169                                bp->link_params.req_line_speed[idx],
11170                                bp->link_params.req_duplex[idx],
11171                                bp->link_params.req_flow_ctrl[idx],
11172                                bp->port.advertising[idx]);
11173         }
11174 }
11175
11176 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
11177 {
11178         __be16 mac_hi_be = cpu_to_be16(mac_hi);
11179         __be32 mac_lo_be = cpu_to_be32(mac_lo);
11180         memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
11181         memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
11182 }
11183
11184 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
11185 {
11186         int port = BP_PORT(bp);
11187         u32 config;
11188         u32 ext_phy_type, ext_phy_config, eee_mode;
11189
11190         bp->link_params.bp = bp;
11191         bp->link_params.port = port;
11192
11193         bp->link_params.lane_config =
11194                 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
11195
11196         bp->link_params.speed_cap_mask[0] =
11197                 SHMEM_RD(bp,
11198                          dev_info.port_hw_config[port].speed_capability_mask) &
11199                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11200         bp->link_params.speed_cap_mask[1] =
11201                 SHMEM_RD(bp,
11202                          dev_info.port_hw_config[port].speed_capability_mask2) &
11203                 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK;
11204         bp->port.link_config[0] =
11205                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
11206
11207         bp->port.link_config[1] =
11208                 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
11209
11210         bp->link_params.multi_phy_config =
11211                 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
11212         /* If the device is capable of WoL, set the default state according
11213          * to the HW
11214          */
11215         config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
11216         bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
11217                    (config & PORT_FEATURE_WOL_ENABLED));
11218
11219         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11220             PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
11221                 bp->flags |= NO_ISCSI_FLAG;
11222         if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
11223             PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
11224                 bp->flags |= NO_FCOE_FLAG;
11225
11226         BNX2X_DEV_INFO("lane_config 0x%08x  speed_cap_mask0 0x%08x  link_config0 0x%08x\n",
11227                        bp->link_params.lane_config,
11228                        bp->link_params.speed_cap_mask[0],
11229                        bp->port.link_config[0]);
11230
11231         bp->link_params.switch_cfg = (bp->port.link_config[0] &
11232                                       PORT_FEATURE_CONNECTED_SWITCH_MASK);
11233         bnx2x_phy_probe(&bp->link_params);
11234         bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
11235
11236         bnx2x_link_settings_requested(bp);
11237
11238         /*
11239          * If connected directly, work with the internal PHY, otherwise, work
11240          * with the external PHY
11241          */
11242         ext_phy_config =
11243                 SHMEM_RD(bp,
11244                          dev_info.port_hw_config[port].external_phy_config);
11245         ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
11246         if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
11247                 bp->mdio.prtad = bp->port.phy_addr;
11248
11249         else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
11250                  (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
11251                 bp->mdio.prtad =
11252                         XGXS_EXT_PHY_ADDR(ext_phy_config);
11253
11254         /* Configure link feature according to nvram value */
11255         eee_mode = (((SHMEM_RD(bp, dev_info.
11256                       port_feature_config[port].eee_power_mode)) &
11257                      PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
11258                     PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
11259         if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
11260                 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
11261                                            EEE_MODE_ENABLE_LPI |
11262                                            EEE_MODE_OUTPUT_TIME;
11263         } else {
11264                 bp->link_params.eee_mode = 0;
11265         }
11266 }
11267
11268 void bnx2x_get_iscsi_info(struct bnx2x *bp)
11269 {
11270         u32 no_flags = NO_ISCSI_FLAG;
11271         int port = BP_PORT(bp);
11272         u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11273                                 drv_lic_key[port].max_iscsi_conn);
11274
11275         if (!CNIC_SUPPORT(bp)) {
11276                 bp->flags |= no_flags;
11277                 return;
11278         }
11279
11280         /* Get the number of maximum allowed iSCSI connections */
11281         bp->cnic_eth_dev.max_iscsi_conn =
11282                 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
11283                 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
11284
11285         BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11286                        bp->cnic_eth_dev.max_iscsi_conn);
11287
11288         /*
11289          * If maximum allowed number of connections is zero -
11290          * disable the feature.
11291          */
11292         if (!bp->cnic_eth_dev.max_iscsi_conn)
11293                 bp->flags |= no_flags;
11294 }
11295
11296 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
11297 {
11298         /* Port info */
11299         bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11300                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
11301         bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11302                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
11303
11304         /* Node info */
11305         bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11306                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
11307         bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11308                 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
11309 }
11310
11311 static int bnx2x_shared_fcoe_funcs(struct bnx2x *bp)
11312 {
11313         u8 count = 0;
11314
11315         if (IS_MF(bp)) {
11316                 u8 fid;
11317
11318                 /* iterate over absolute function ids for this path: */
11319                 for (fid = BP_PATH(bp); fid < E2_FUNC_MAX * 2; fid += 2) {
11320                         if (IS_MF_SD(bp)) {
11321                                 u32 cfg = MF_CFG_RD(bp,
11322                                                     func_mf_config[fid].config);
11323
11324                                 if (!(cfg & FUNC_MF_CFG_FUNC_HIDE) &&
11325                                     ((cfg & FUNC_MF_CFG_PROTOCOL_MASK) ==
11326                                             FUNC_MF_CFG_PROTOCOL_FCOE))
11327                                         count++;
11328                         } else {
11329                                 u32 cfg = MF_CFG_RD(bp,
11330                                                     func_ext_config[fid].
11331                                                                       func_cfg);
11332
11333                                 if ((cfg & MACP_FUNC_CFG_FLAGS_ENABLED) &&
11334                                     (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD))
11335                                         count++;
11336                         }
11337                 }
11338         } else { /* SF */
11339                 int port, port_cnt = CHIP_MODE_IS_4_PORT(bp) ? 2 : 1;
11340
11341                 for (port = 0; port < port_cnt; port++) {
11342                         u32 lic = SHMEM_RD(bp,
11343                                            drv_lic_key[port].max_fcoe_conn) ^
11344                                   FW_ENCODE_32BIT_PATTERN;
11345                         if (lic)
11346                                 count++;
11347                 }
11348         }
11349
11350         return count;
11351 }
11352
11353 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
11354 {
11355         int port = BP_PORT(bp);
11356         int func = BP_ABS_FUNC(bp);
11357         u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
11358                                 drv_lic_key[port].max_fcoe_conn);
11359         u8 num_fcoe_func = bnx2x_shared_fcoe_funcs(bp);
11360
11361         if (!CNIC_SUPPORT(bp)) {
11362                 bp->flags |= NO_FCOE_FLAG;
11363                 return;
11364         }
11365
11366         /* Get the number of maximum allowed FCoE connections */
11367         bp->cnic_eth_dev.max_fcoe_conn =
11368                 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
11369                 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
11370
11371         /* Calculate the number of maximum allowed FCoE tasks */
11372         bp->cnic_eth_dev.max_fcoe_exchanges = MAX_NUM_FCOE_TASKS_PER_ENGINE;
11373
11374         /* check if FCoE resources must be shared between different functions */
11375         if (num_fcoe_func)
11376                 bp->cnic_eth_dev.max_fcoe_exchanges /= num_fcoe_func;
11377
11378         /* Read the WWN: */
11379         if (!IS_MF(bp)) {
11380                 /* Port info */
11381                 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
11382                         SHMEM_RD(bp,
11383                                  dev_info.port_hw_config[port].
11384                                  fcoe_wwn_port_name_upper);
11385                 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
11386                         SHMEM_RD(bp,
11387                                  dev_info.port_hw_config[port].
11388                                  fcoe_wwn_port_name_lower);
11389
11390                 /* Node info */
11391                 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
11392                         SHMEM_RD(bp,
11393                                  dev_info.port_hw_config[port].
11394                                  fcoe_wwn_node_name_upper);
11395                 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
11396                         SHMEM_RD(bp,
11397                                  dev_info.port_hw_config[port].
11398                                  fcoe_wwn_node_name_lower);
11399         } else if (!IS_MF_SD(bp)) {
11400                 /*
11401                  * Read the WWN info only if the FCoE feature is enabled for
11402                  * this function.
11403                  */
11404                 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
11405                         bnx2x_get_ext_wwn_info(bp, func);
11406
11407         } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
11408                 bnx2x_get_ext_wwn_info(bp, func);
11409         }
11410
11411         BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
11412
11413         /*
11414          * If maximum allowed number of connections is zero -
11415          * disable the feature.
11416          */
11417         if (!bp->cnic_eth_dev.max_fcoe_conn)
11418                 bp->flags |= NO_FCOE_FLAG;
11419 }
11420
11421 static void bnx2x_get_cnic_info(struct bnx2x *bp)
11422 {
11423         /*
11424          * iSCSI may be dynamically disabled but reading
11425          * info here we will decrease memory usage by driver
11426          * if the feature is disabled for good
11427          */
11428         bnx2x_get_iscsi_info(bp);
11429         bnx2x_get_fcoe_info(bp);
11430 }
11431
11432 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
11433 {
11434         u32 val, val2;
11435         int func = BP_ABS_FUNC(bp);
11436         int port = BP_PORT(bp);
11437         u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
11438         u8 *fip_mac = bp->fip_mac;
11439
11440         if (IS_MF(bp)) {
11441                 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11442                  * FCoE MAC then the appropriate feature should be disabled.
11443                  * In non SD mode features configuration comes from struct
11444                  * func_ext_config.
11445                  */
11446                 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
11447                         u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
11448                         if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
11449                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11450                                                  iscsi_mac_addr_upper);
11451                                 val = MF_CFG_RD(bp, func_ext_config[func].
11452                                                 iscsi_mac_addr_lower);
11453                                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11454                                 BNX2X_DEV_INFO
11455                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11456                         } else {
11457                                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11458                         }
11459
11460                         if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
11461                                 val2 = MF_CFG_RD(bp, func_ext_config[func].
11462                                                  fcoe_mac_addr_upper);
11463                                 val = MF_CFG_RD(bp, func_ext_config[func].
11464                                                 fcoe_mac_addr_lower);
11465                                 bnx2x_set_mac_buf(fip_mac, val, val2);
11466                                 BNX2X_DEV_INFO
11467                                         ("Read FCoE L2 MAC: %pM\n", fip_mac);
11468                         } else {
11469                                 bp->flags |= NO_FCOE_FLAG;
11470                         }
11471
11472                         bp->mf_ext_config = cfg;
11473
11474                 } else { /* SD MODE */
11475                         if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
11476                                 /* use primary mac as iscsi mac */
11477                                 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
11478
11479                                 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11480                                 BNX2X_DEV_INFO
11481                                         ("Read iSCSI MAC: %pM\n", iscsi_mac);
11482                         } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
11483                                 /* use primary mac as fip mac */
11484                                 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
11485                                 BNX2X_DEV_INFO("SD FCoE MODE\n");
11486                                 BNX2X_DEV_INFO
11487                                         ("Read FIP MAC: %pM\n", fip_mac);
11488                         }
11489                 }
11490
11491                 /* If this is a storage-only interface, use SAN mac as
11492                  * primary MAC. Notice that for SD this is already the case,
11493                  * as the SAN mac was copied from the primary MAC.
11494                  */
11495                 if (IS_MF_FCOE_AFEX(bp))
11496                         memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
11497         } else {
11498                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11499                                 iscsi_mac_upper);
11500                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11501                                iscsi_mac_lower);
11502                 bnx2x_set_mac_buf(iscsi_mac, val, val2);
11503
11504                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
11505                                 fcoe_fip_mac_upper);
11506                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
11507                                fcoe_fip_mac_lower);
11508                 bnx2x_set_mac_buf(fip_mac, val, val2);
11509         }
11510
11511         /* Disable iSCSI OOO if MAC configuration is invalid. */
11512         if (!is_valid_ether_addr(iscsi_mac)) {
11513                 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
11514                 memset(iscsi_mac, 0, ETH_ALEN);
11515         }
11516
11517         /* Disable FCoE if MAC configuration is invalid. */
11518         if (!is_valid_ether_addr(fip_mac)) {
11519                 bp->flags |= NO_FCOE_FLAG;
11520                 memset(bp->fip_mac, 0, ETH_ALEN);
11521         }
11522 }
11523
11524 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
11525 {
11526         u32 val, val2;
11527         int func = BP_ABS_FUNC(bp);
11528         int port = BP_PORT(bp);
11529
11530         /* Zero primary MAC configuration */
11531         memset(bp->dev->dev_addr, 0, ETH_ALEN);
11532
11533         if (BP_NOMCP(bp)) {
11534                 BNX2X_ERROR("warning: random MAC workaround active\n");
11535                 eth_hw_addr_random(bp->dev);
11536         } else if (IS_MF(bp)) {
11537                 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
11538                 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
11539                 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
11540                     (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
11541                         bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11542
11543                 if (CNIC_SUPPORT(bp))
11544                         bnx2x_get_cnic_mac_hwinfo(bp);
11545         } else {
11546                 /* in SF read MACs from port configuration */
11547                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11548                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11549                 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
11550
11551                 if (CNIC_SUPPORT(bp))
11552                         bnx2x_get_cnic_mac_hwinfo(bp);
11553         }
11554
11555         if (!BP_NOMCP(bp)) {
11556                 /* Read physical port identifier from shmem */
11557                 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
11558                 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
11559                 bnx2x_set_mac_buf(bp->phys_port_id, val, val2);
11560                 bp->flags |= HAS_PHYS_PORT_ID;
11561         }
11562
11563         memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
11564
11565         if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
11566                 dev_err(&bp->pdev->dev,
11567                         "bad Ethernet MAC address configuration: %pM\n"
11568                         "change it manually before bringing up the appropriate network interface\n",
11569                         bp->dev->dev_addr);
11570 }
11571
11572 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
11573 {
11574         int tmp;
11575         u32 cfg;
11576
11577         if (IS_VF(bp))
11578                 return 0;
11579
11580         if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
11581                 /* Take function: tmp = func */
11582                 tmp = BP_ABS_FUNC(bp);
11583                 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
11584                 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
11585         } else {
11586                 /* Take port: tmp = port */
11587                 tmp = BP_PORT(bp);
11588                 cfg = SHMEM_RD(bp,
11589                                dev_info.port_hw_config[tmp].generic_features);
11590                 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
11591         }
11592         return cfg;
11593 }
11594
11595 static int bnx2x_get_hwinfo(struct bnx2x *bp)
11596 {
11597         int /*abs*/func = BP_ABS_FUNC(bp);
11598         int vn;
11599         u32 val = 0;
11600         int rc = 0;
11601
11602         bnx2x_get_common_hwinfo(bp);
11603
11604         /*
11605          * initialize IGU parameters
11606          */
11607         if (CHIP_IS_E1x(bp)) {
11608                 bp->common.int_block = INT_BLOCK_HC;
11609
11610                 bp->igu_dsb_id = DEF_SB_IGU_ID;
11611                 bp->igu_base_sb = 0;
11612         } else {
11613                 bp->common.int_block = INT_BLOCK_IGU;
11614
11615                 /* do not allow device reset during IGU info processing */
11616                 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11617
11618                 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11619
11620                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11621                         int tout = 5000;
11622
11623                         BNX2X_DEV_INFO("FORCING Normal Mode\n");
11624
11625                         val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11626                         REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11627                         REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11628
11629                         while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11630                                 tout--;
11631                                 usleep_range(1000, 2000);
11632                         }
11633
11634                         if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11635                                 dev_err(&bp->pdev->dev,
11636                                         "FORCING Normal Mode failed!!!\n");
11637                                 bnx2x_release_hw_lock(bp,
11638                                                       HW_LOCK_RESOURCE_RESET);
11639                                 return -EPERM;
11640                         }
11641                 }
11642
11643                 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11644                         BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11645                         bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11646                 } else
11647                         BNX2X_DEV_INFO("IGU Normal Mode\n");
11648
11649                 rc = bnx2x_get_igu_cam_info(bp);
11650                 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11651                 if (rc)
11652                         return rc;
11653         }
11654
11655         /*
11656          * set base FW non-default (fast path) status block id, this value is
11657          * used to initialize the fw_sb_id saved on the fp/queue structure to
11658          * determine the id used by the FW.
11659          */
11660         if (CHIP_IS_E1x(bp))
11661                 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11662         else /*
11663               * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11664               * the same queue are indicated on the same IGU SB). So we prefer
11665               * FW and IGU SBs to be the same value.
11666               */
11667                 bp->base_fw_ndsb = bp->igu_base_sb;
11668
11669         BNX2X_DEV_INFO("igu_dsb_id %d  igu_base_sb %d  igu_sb_cnt %d\n"
11670                        "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11671                        bp->igu_sb_cnt, bp->base_fw_ndsb);
11672
11673         /*
11674          * Initialize MF configuration
11675          */
11676
11677         bp->mf_ov = 0;
11678         bp->mf_mode = 0;
11679         vn = BP_VN(bp);
11680
11681         if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11682                 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11683                                bp->common.shmem2_base, SHMEM2_RD(bp, size),
11684                               (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11685
11686                 if (SHMEM2_HAS(bp, mf_cfg_addr))
11687                         bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11688                 else
11689                         bp->common.mf_cfg_base = bp->common.shmem_base +
11690                                 offsetof(struct shmem_region, func_mb) +
11691                                 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11692                 /*
11693                  * get mf configuration:
11694                  * 1. Existence of MF configuration
11695                  * 2. MAC address must be legal (check only upper bytes)
11696                  *    for  Switch-Independent mode;
11697                  *    OVLAN must be legal for Switch-Dependent mode
11698                  * 3. SF_MODE configures specific MF mode
11699                  */
11700                 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11701                         /* get mf configuration */
11702                         val = SHMEM_RD(bp,
11703                                        dev_info.shared_feature_config.config);
11704                         val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11705
11706                         switch (val) {
11707                         case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11708                                 val = MF_CFG_RD(bp, func_mf_config[func].
11709                                                 mac_upper);
11710                                 /* check for legal mac (upper bytes)*/
11711                                 if (val != 0xffff) {
11712                                         bp->mf_mode = MULTI_FUNCTION_SI;
11713                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11714                                                    func_mf_config[func].config);
11715                                 } else
11716                                         BNX2X_DEV_INFO("illegal MAC address for SI\n");
11717                                 break;
11718                         case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11719                                 if ((!CHIP_IS_E1x(bp)) &&
11720                                     (MF_CFG_RD(bp, func_mf_config[func].
11721                                                mac_upper) != 0xffff) &&
11722                                     (SHMEM2_HAS(bp,
11723                                                 afex_driver_support))) {
11724                                         bp->mf_mode = MULTI_FUNCTION_AFEX;
11725                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11726                                                 func_mf_config[func].config);
11727                                 } else {
11728                                         BNX2X_DEV_INFO("can not configure afex mode\n");
11729                                 }
11730                                 break;
11731                         case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11732                                 /* get OV configuration */
11733                                 val = MF_CFG_RD(bp,
11734                                         func_mf_config[FUNC_0].e1hov_tag);
11735                                 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11736
11737                                 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11738                                         bp->mf_mode = MULTI_FUNCTION_SD;
11739                                         bp->mf_config[vn] = MF_CFG_RD(bp,
11740                                                 func_mf_config[func].config);
11741                                 } else
11742                                         BNX2X_DEV_INFO("illegal OV for SD\n");
11743                                 break;
11744                         case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11745                                 bp->mf_config[vn] = 0;
11746                                 break;
11747                         default:
11748                                 /* Unknown configuration: reset mf_config */
11749                                 bp->mf_config[vn] = 0;
11750                                 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11751                         }
11752                 }
11753
11754                 BNX2X_DEV_INFO("%s function mode\n",
11755                                IS_MF(bp) ? "multi" : "single");
11756
11757                 switch (bp->mf_mode) {
11758                 case MULTI_FUNCTION_SD:
11759                         val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11760                               FUNC_MF_CFG_E1HOV_TAG_MASK;
11761                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11762                                 bp->mf_ov = val;
11763                                 bp->path_has_ovlan = true;
11764
11765                                 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11766                                                func, bp->mf_ov, bp->mf_ov);
11767                         } else {
11768                                 dev_err(&bp->pdev->dev,
11769                                         "No valid MF OV for func %d, aborting\n",
11770                                         func);
11771                                 return -EPERM;
11772                         }
11773                         break;
11774                 case MULTI_FUNCTION_AFEX:
11775                         BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11776                         break;
11777                 case MULTI_FUNCTION_SI:
11778                         BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11779                                        func);
11780                         break;
11781                 default:
11782                         if (vn) {
11783                                 dev_err(&bp->pdev->dev,
11784                                         "VN %d is in a single function mode, aborting\n",
11785                                         vn);
11786                                 return -EPERM;
11787                         }
11788                         break;
11789                 }
11790
11791                 /* check if other port on the path needs ovlan:
11792                  * Since MF configuration is shared between ports
11793                  * Possible mixed modes are only
11794                  * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11795                  */
11796                 if (CHIP_MODE_IS_4_PORT(bp) &&
11797                     !bp->path_has_ovlan &&
11798                     !IS_MF(bp) &&
11799                     bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11800                         u8 other_port = !BP_PORT(bp);
11801                         u8 other_func = BP_PATH(bp) + 2*other_port;
11802                         val = MF_CFG_RD(bp,
11803                                         func_mf_config[other_func].e1hov_tag);
11804                         if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11805                                 bp->path_has_ovlan = true;
11806                 }
11807         }
11808
11809         /* adjust igu_sb_cnt to MF for E1H */
11810         if (CHIP_IS_E1H(bp) && IS_MF(bp))
11811                 bp->igu_sb_cnt = min_t(u8, bp->igu_sb_cnt, E1H_MAX_MF_SB_COUNT);
11812
11813         /* port info */
11814         bnx2x_get_port_hwinfo(bp);
11815
11816         /* Get MAC addresses */
11817         bnx2x_get_mac_hwinfo(bp);
11818
11819         bnx2x_get_cnic_info(bp);
11820
11821         return rc;
11822 }
11823
11824 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11825 {
11826         int cnt, i, block_end, rodi;
11827         char vpd_start[BNX2X_VPD_LEN+1];
11828         char str_id_reg[VENDOR_ID_LEN+1];
11829         char str_id_cap[VENDOR_ID_LEN+1];
11830         char *vpd_data;
11831         char *vpd_extended_data = NULL;
11832         u8 len;
11833
11834         cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11835         memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11836
11837         if (cnt < BNX2X_VPD_LEN)
11838                 goto out_not_found;
11839
11840         /* VPD RO tag should be first tag after identifier string, hence
11841          * we should be able to find it in first BNX2X_VPD_LEN chars
11842          */
11843         i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11844                              PCI_VPD_LRDT_RO_DATA);
11845         if (i < 0)
11846                 goto out_not_found;
11847
11848         block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11849                     pci_vpd_lrdt_size(&vpd_start[i]);
11850
11851         i += PCI_VPD_LRDT_TAG_SIZE;
11852
11853         if (block_end > BNX2X_VPD_LEN) {
11854                 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11855                 if (vpd_extended_data  == NULL)
11856                         goto out_not_found;
11857
11858                 /* read rest of vpd image into vpd_extended_data */
11859                 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11860                 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11861                                    block_end - BNX2X_VPD_LEN,
11862                                    vpd_extended_data + BNX2X_VPD_LEN);
11863                 if (cnt < (block_end - BNX2X_VPD_LEN))
11864                         goto out_not_found;
11865                 vpd_data = vpd_extended_data;
11866         } else
11867                 vpd_data = vpd_start;
11868
11869         /* now vpd_data holds full vpd content in both cases */
11870
11871         rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11872                                    PCI_VPD_RO_KEYWORD_MFR_ID);
11873         if (rodi < 0)
11874                 goto out_not_found;
11875
11876         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11877
11878         if (len != VENDOR_ID_LEN)
11879                 goto out_not_found;
11880
11881         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11882
11883         /* vendor specific info */
11884         snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11885         snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11886         if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11887             !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11888
11889                 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11890                                                 PCI_VPD_RO_KEYWORD_VENDOR0);
11891                 if (rodi >= 0) {
11892                         len = pci_vpd_info_field_size(&vpd_data[rodi]);
11893
11894                         rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11895
11896                         if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11897                                 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11898                                 bp->fw_ver[len] = ' ';
11899                         }
11900                 }
11901                 kfree(vpd_extended_data);
11902                 return;
11903         }
11904 out_not_found:
11905         kfree(vpd_extended_data);
11906         return;
11907 }
11908
11909 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11910 {
11911         u32 flags = 0;
11912
11913         if (CHIP_REV_IS_FPGA(bp))
11914                 SET_FLAGS(flags, MODE_FPGA);
11915         else if (CHIP_REV_IS_EMUL(bp))
11916                 SET_FLAGS(flags, MODE_EMUL);
11917         else
11918                 SET_FLAGS(flags, MODE_ASIC);
11919
11920         if (CHIP_MODE_IS_4_PORT(bp))
11921                 SET_FLAGS(flags, MODE_PORT4);
11922         else
11923                 SET_FLAGS(flags, MODE_PORT2);
11924
11925         if (CHIP_IS_E2(bp))
11926                 SET_FLAGS(flags, MODE_E2);
11927         else if (CHIP_IS_E3(bp)) {
11928                 SET_FLAGS(flags, MODE_E3);
11929                 if (CHIP_REV(bp) == CHIP_REV_Ax)
11930                         SET_FLAGS(flags, MODE_E3_A0);
11931                 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11932                         SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11933         }
11934
11935         if (IS_MF(bp)) {
11936                 SET_FLAGS(flags, MODE_MF);
11937                 switch (bp->mf_mode) {
11938                 case MULTI_FUNCTION_SD:
11939                         SET_FLAGS(flags, MODE_MF_SD);
11940                         break;
11941                 case MULTI_FUNCTION_SI:
11942                         SET_FLAGS(flags, MODE_MF_SI);
11943                         break;
11944                 case MULTI_FUNCTION_AFEX:
11945                         SET_FLAGS(flags, MODE_MF_AFEX);
11946                         break;
11947                 }
11948         } else
11949                 SET_FLAGS(flags, MODE_SF);
11950
11951 #if defined(__LITTLE_ENDIAN)
11952         SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11953 #else /*(__BIG_ENDIAN)*/
11954         SET_FLAGS(flags, MODE_BIG_ENDIAN);
11955 #endif
11956         INIT_MODE_FLAGS(bp) = flags;
11957 }
11958
11959 static int bnx2x_init_bp(struct bnx2x *bp)
11960 {
11961         int func;
11962         int rc;
11963
11964         mutex_init(&bp->port.phy_mutex);
11965         mutex_init(&bp->fw_mb_mutex);
11966         mutex_init(&bp->drv_info_mutex);
11967         bp->drv_info_mng_owner = false;
11968         spin_lock_init(&bp->stats_lock);
11969         sema_init(&bp->stats_sema, 1);
11970
11971         INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11972         INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11973         INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11974         INIT_DELAYED_WORK(&bp->iov_task, bnx2x_iov_task);
11975         if (IS_PF(bp)) {
11976                 rc = bnx2x_get_hwinfo(bp);
11977                 if (rc)
11978                         return rc;
11979         } else {
11980                 eth_zero_addr(bp->dev->dev_addr);
11981         }
11982
11983         bnx2x_set_modes_bitmap(bp);
11984
11985         rc = bnx2x_alloc_mem_bp(bp);
11986         if (rc)
11987                 return rc;
11988
11989         bnx2x_read_fwinfo(bp);
11990
11991         func = BP_FUNC(bp);
11992
11993         /* need to reset chip if undi was active */
11994         if (IS_PF(bp) && !BP_NOMCP(bp)) {
11995                 /* init fw_seq */
11996                 bp->fw_seq =
11997                         SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11998                                                         DRV_MSG_SEQ_NUMBER_MASK;
11999                 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
12000
12001                 rc = bnx2x_prev_unload(bp);
12002                 if (rc) {
12003                         bnx2x_free_mem_bp(bp);
12004                         return rc;
12005                 }
12006         }
12007
12008         if (CHIP_REV_IS_FPGA(bp))
12009                 dev_err(&bp->pdev->dev, "FPGA detected\n");
12010
12011         if (BP_NOMCP(bp) && (func == 0))
12012                 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
12013
12014         bp->disable_tpa = disable_tpa;
12015         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
12016         /* Reduce memory usage in kdump environment by disabling TPA */
12017         bp->disable_tpa |= reset_devices;
12018
12019         /* Set TPA flags */
12020         if (bp->disable_tpa) {
12021                 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12022                 bp->dev->features &= ~NETIF_F_LRO;
12023         } else {
12024                 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
12025                 bp->dev->features |= NETIF_F_LRO;
12026         }
12027
12028         if (CHIP_IS_E1(bp))
12029                 bp->dropless_fc = 0;
12030         else
12031                 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
12032
12033         bp->mrrs = mrrs;
12034
12035         bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
12036         if (IS_VF(bp))
12037                 bp->rx_ring_size = MAX_RX_AVAIL;
12038
12039         /* make sure that the numbers are in the right granularity */
12040         bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
12041         bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
12042
12043         bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
12044
12045         init_timer(&bp->timer);
12046         bp->timer.expires = jiffies + bp->current_interval;
12047         bp->timer.data = (unsigned long) bp;
12048         bp->timer.function = bnx2x_timer;
12049
12050         if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
12051             SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
12052             SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
12053             SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
12054                 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
12055                 bnx2x_dcbx_init_params(bp);
12056         } else {
12057                 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
12058         }
12059
12060         if (CHIP_IS_E1x(bp))
12061                 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
12062         else
12063                 bp->cnic_base_cl_id = FP_SB_MAX_E2;
12064
12065         /* multiple tx priority */
12066         if (IS_VF(bp))
12067                 bp->max_cos = 1;
12068         else if (CHIP_IS_E1x(bp))
12069                 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
12070         else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
12071                 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
12072         else if (CHIP_IS_E3B0(bp))
12073                 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
12074         else
12075                 BNX2X_ERR("unknown chip %x revision %x\n",
12076                           CHIP_NUM(bp), CHIP_REV(bp));
12077         BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
12078
12079         /* We need at least one default status block for slow-path events,
12080          * second status block for the L2 queue, and a third status block for
12081          * CNIC if supported.
12082          */
12083         if (IS_VF(bp))
12084                 bp->min_msix_vec_cnt = 1;
12085         else if (CNIC_SUPPORT(bp))
12086                 bp->min_msix_vec_cnt = 3;
12087         else /* PF w/o cnic */
12088                 bp->min_msix_vec_cnt = 2;
12089         BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
12090
12091         bp->dump_preset_idx = 1;
12092
12093         if (CHIP_IS_E3B0(bp))
12094                 bp->flags |= PTP_SUPPORTED;
12095
12096         return rc;
12097 }
12098
12099 /****************************************************************************
12100 * General service functions
12101 ****************************************************************************/
12102
12103 /*
12104  * net_device service functions
12105  */
12106
12107 /* called with rtnl_lock */
12108 static int bnx2x_open(struct net_device *dev)
12109 {
12110         struct bnx2x *bp = netdev_priv(dev);
12111         int rc;
12112
12113         bp->stats_init = true;
12114
12115         netif_carrier_off(dev);
12116
12117         bnx2x_set_power_state(bp, PCI_D0);
12118
12119         /* If parity had happen during the unload, then attentions
12120          * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12121          * want the first function loaded on the current engine to
12122          * complete the recovery.
12123          * Parity recovery is only relevant for PF driver.
12124          */
12125         if (IS_PF(bp)) {
12126                 int other_engine = BP_PATH(bp) ? 0 : 1;
12127                 bool other_load_status, load_status;
12128                 bool global = false;
12129
12130                 other_load_status = bnx2x_get_load_status(bp, other_engine);
12131                 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
12132                 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
12133                     bnx2x_chk_parity_attn(bp, &global, true)) {
12134                         do {
12135                                 /* If there are attentions and they are in a
12136                                  * global blocks, set the GLOBAL_RESET bit
12137                                  * regardless whether it will be this function
12138                                  * that will complete the recovery or not.
12139                                  */
12140                                 if (global)
12141                                         bnx2x_set_reset_global(bp);
12142
12143                                 /* Only the first function on the current
12144                                  * engine should try to recover in open. In case
12145                                  * of attentions in global blocks only the first
12146                                  * in the chip should try to recover.
12147                                  */
12148                                 if ((!load_status &&
12149                                      (!global || !other_load_status)) &&
12150                                       bnx2x_trylock_leader_lock(bp) &&
12151                                       !bnx2x_leader_reset(bp)) {
12152                                         netdev_info(bp->dev,
12153                                                     "Recovered in open\n");
12154                                         break;
12155                                 }
12156
12157                                 /* recovery has failed... */
12158                                 bnx2x_set_power_state(bp, PCI_D3hot);
12159                                 bp->recovery_state = BNX2X_RECOVERY_FAILED;
12160
12161                                 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12162                                           "If you still see this message after a few retries then power cycle is required.\n");
12163
12164                                 return -EAGAIN;
12165                         } while (0);
12166                 }
12167         }
12168
12169         bp->recovery_state = BNX2X_RECOVERY_DONE;
12170         rc = bnx2x_nic_load(bp, LOAD_OPEN);
12171         if (rc)
12172                 return rc;
12173         return 0;
12174 }
12175
12176 /* called with rtnl_lock */
12177 static int bnx2x_close(struct net_device *dev)
12178 {
12179         struct bnx2x *bp = netdev_priv(dev);
12180
12181         /* Unload the driver, release IRQs */
12182         bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
12183
12184         return 0;
12185 }
12186
12187 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
12188                                       struct bnx2x_mcast_ramrod_params *p)
12189 {
12190         int mc_count = netdev_mc_count(bp->dev);
12191         struct bnx2x_mcast_list_elem *mc_mac =
12192                 kcalloc(mc_count, sizeof(*mc_mac), GFP_ATOMIC);
12193         struct netdev_hw_addr *ha;
12194
12195         if (!mc_mac)
12196                 return -ENOMEM;
12197
12198         INIT_LIST_HEAD(&p->mcast_list);
12199
12200         netdev_for_each_mc_addr(ha, bp->dev) {
12201                 mc_mac->mac = bnx2x_mc_addr(ha);
12202                 list_add_tail(&mc_mac->link, &p->mcast_list);
12203                 mc_mac++;
12204         }
12205
12206         p->mcast_list_len = mc_count;
12207
12208         return 0;
12209 }
12210
12211 static void bnx2x_free_mcast_macs_list(
12212         struct bnx2x_mcast_ramrod_params *p)
12213 {
12214         struct bnx2x_mcast_list_elem *mc_mac =
12215                 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
12216                                  link);
12217
12218         WARN_ON(!mc_mac);
12219         kfree(mc_mac);
12220 }
12221
12222 /**
12223  * bnx2x_set_uc_list - configure a new unicast MACs list.
12224  *
12225  * @bp: driver handle
12226  *
12227  * We will use zero (0) as a MAC type for these MACs.
12228  */
12229 static int bnx2x_set_uc_list(struct bnx2x *bp)
12230 {
12231         int rc;
12232         struct net_device *dev = bp->dev;
12233         struct netdev_hw_addr *ha;
12234         struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
12235         unsigned long ramrod_flags = 0;
12236
12237         /* First schedule a cleanup up of old configuration */
12238         rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
12239         if (rc < 0) {
12240                 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
12241                 return rc;
12242         }
12243
12244         netdev_for_each_uc_addr(ha, dev) {
12245                 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
12246                                        BNX2X_UC_LIST_MAC, &ramrod_flags);
12247                 if (rc == -EEXIST) {
12248                         DP(BNX2X_MSG_SP,
12249                            "Failed to schedule ADD operations: %d\n", rc);
12250                         /* do not treat adding same MAC as error */
12251                         rc = 0;
12252
12253                 } else if (rc < 0) {
12254
12255                         BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12256                                   rc);
12257                         return rc;
12258                 }
12259         }
12260
12261         /* Execute the pending commands */
12262         __set_bit(RAMROD_CONT, &ramrod_flags);
12263         return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
12264                                  BNX2X_UC_LIST_MAC, &ramrod_flags);
12265 }
12266
12267 static int bnx2x_set_mc_list(struct bnx2x *bp)
12268 {
12269         struct net_device *dev = bp->dev;
12270         struct bnx2x_mcast_ramrod_params rparam = {NULL};
12271         int rc = 0;
12272
12273         rparam.mcast_obj = &bp->mcast_obj;
12274
12275         /* first, clear all configured multicast MACs */
12276         rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
12277         if (rc < 0) {
12278                 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
12279                 return rc;
12280         }
12281
12282         /* then, configure a new MACs list */
12283         if (netdev_mc_count(dev)) {
12284                 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
12285                 if (rc) {
12286                         BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12287                                   rc);
12288                         return rc;
12289                 }
12290
12291                 /* Now add the new MACs */
12292                 rc = bnx2x_config_mcast(bp, &rparam,
12293                                         BNX2X_MCAST_CMD_ADD);
12294                 if (rc < 0)
12295                         BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12296                                   rc);
12297
12298                 bnx2x_free_mcast_macs_list(&rparam);
12299         }
12300
12301         return rc;
12302 }
12303
12304 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12305 static void bnx2x_set_rx_mode(struct net_device *dev)
12306 {
12307         struct bnx2x *bp = netdev_priv(dev);
12308
12309         if (bp->state != BNX2X_STATE_OPEN) {
12310                 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
12311                 return;
12312         } else {
12313                 /* Schedule an SP task to handle rest of change */
12314                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_RX_MODE,
12315                                        NETIF_MSG_IFUP);
12316         }
12317 }
12318
12319 void bnx2x_set_rx_mode_inner(struct bnx2x *bp)
12320 {
12321         u32 rx_mode = BNX2X_RX_MODE_NORMAL;
12322
12323         DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
12324
12325         netif_addr_lock_bh(bp->dev);
12326
12327         if (bp->dev->flags & IFF_PROMISC) {
12328                 rx_mode = BNX2X_RX_MODE_PROMISC;
12329         } else if ((bp->dev->flags & IFF_ALLMULTI) ||
12330                    ((netdev_mc_count(bp->dev) > BNX2X_MAX_MULTICAST) &&
12331                     CHIP_IS_E1(bp))) {
12332                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12333         } else {
12334                 if (IS_PF(bp)) {
12335                         /* some multicasts */
12336                         if (bnx2x_set_mc_list(bp) < 0)
12337                                 rx_mode = BNX2X_RX_MODE_ALLMULTI;
12338
12339                         /* release bh lock, as bnx2x_set_uc_list might sleep */
12340                         netif_addr_unlock_bh(bp->dev);
12341                         if (bnx2x_set_uc_list(bp) < 0)
12342                                 rx_mode = BNX2X_RX_MODE_PROMISC;
12343                         netif_addr_lock_bh(bp->dev);
12344                 } else {
12345                         /* configuring mcast to a vf involves sleeping (when we
12346                          * wait for the pf's response).
12347                          */
12348                         bnx2x_schedule_sp_rtnl(bp,
12349                                                BNX2X_SP_RTNL_VFPF_MCAST, 0);
12350                 }
12351         }
12352
12353         bp->rx_mode = rx_mode;
12354         /* handle ISCSI SD mode */
12355         if (IS_MF_ISCSI_SD(bp))
12356                 bp->rx_mode = BNX2X_RX_MODE_NONE;
12357
12358         /* Schedule the rx_mode command */
12359         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
12360                 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
12361                 netif_addr_unlock_bh(bp->dev);
12362                 return;
12363         }
12364
12365         if (IS_PF(bp)) {
12366                 bnx2x_set_storm_rx_mode(bp);
12367                 netif_addr_unlock_bh(bp->dev);
12368         } else {
12369                 /* VF will need to request the PF to make this change, and so
12370                  * the VF needs to release the bottom-half lock prior to the
12371                  * request (as it will likely require sleep on the VF side)
12372                  */
12373                 netif_addr_unlock_bh(bp->dev);
12374                 bnx2x_vfpf_storm_rx_mode(bp);
12375         }
12376 }
12377
12378 /* called with rtnl_lock */
12379 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
12380                            int devad, u16 addr)
12381 {
12382         struct bnx2x *bp = netdev_priv(netdev);
12383         u16 value;
12384         int rc;
12385
12386         DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12387            prtad, devad, addr);
12388
12389         /* The HW expects different devad if CL22 is used */
12390         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12391
12392         bnx2x_acquire_phy_lock(bp);
12393         rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
12394         bnx2x_release_phy_lock(bp);
12395         DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
12396
12397         if (!rc)
12398                 rc = value;
12399         return rc;
12400 }
12401
12402 /* called with rtnl_lock */
12403 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
12404                             u16 addr, u16 value)
12405 {
12406         struct bnx2x *bp = netdev_priv(netdev);
12407         int rc;
12408
12409         DP(NETIF_MSG_LINK,
12410            "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12411            prtad, devad, addr, value);
12412
12413         /* The HW expects different devad if CL22 is used */
12414         devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
12415
12416         bnx2x_acquire_phy_lock(bp);
12417         rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
12418         bnx2x_release_phy_lock(bp);
12419         return rc;
12420 }
12421
12422 /* called with rtnl_lock */
12423 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
12424 {
12425         struct bnx2x *bp = netdev_priv(dev);
12426         struct mii_ioctl_data *mdio = if_mii(ifr);
12427
12428         if (!netif_running(dev))
12429                 return -EAGAIN;
12430
12431         switch (cmd) {
12432         case SIOCSHWTSTAMP:
12433                 return bnx2x_hwtstamp_ioctl(bp, ifr);
12434         default:
12435                 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12436                    mdio->phy_id, mdio->reg_num, mdio->val_in);
12437                 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
12438         }
12439 }
12440
12441 #ifdef CONFIG_NET_POLL_CONTROLLER
12442 static void poll_bnx2x(struct net_device *dev)
12443 {
12444         struct bnx2x *bp = netdev_priv(dev);
12445         int i;
12446
12447         for_each_eth_queue(bp, i) {
12448                 struct bnx2x_fastpath *fp = &bp->fp[i];
12449                 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
12450         }
12451 }
12452 #endif
12453
12454 static int bnx2x_validate_addr(struct net_device *dev)
12455 {
12456         struct bnx2x *bp = netdev_priv(dev);
12457
12458         /* query the bulletin board for mac address configured by the PF */
12459         if (IS_VF(bp))
12460                 bnx2x_sample_bulletin(bp);
12461
12462         if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
12463                 BNX2X_ERR("Non-valid Ethernet address\n");
12464                 return -EADDRNOTAVAIL;
12465         }
12466         return 0;
12467 }
12468
12469 static int bnx2x_get_phys_port_id(struct net_device *netdev,
12470                                   struct netdev_phys_port_id *ppid)
12471 {
12472         struct bnx2x *bp = netdev_priv(netdev);
12473
12474         if (!(bp->flags & HAS_PHYS_PORT_ID))
12475                 return -EOPNOTSUPP;
12476
12477         ppid->id_len = sizeof(bp->phys_port_id);
12478         memcpy(ppid->id, bp->phys_port_id, ppid->id_len);
12479
12480         return 0;
12481 }
12482
12483 static const struct net_device_ops bnx2x_netdev_ops = {
12484         .ndo_open               = bnx2x_open,
12485         .ndo_stop               = bnx2x_close,
12486         .ndo_start_xmit         = bnx2x_start_xmit,
12487         .ndo_select_queue       = bnx2x_select_queue,
12488         .ndo_set_rx_mode        = bnx2x_set_rx_mode,
12489         .ndo_set_mac_address    = bnx2x_change_mac_addr,
12490         .ndo_validate_addr      = bnx2x_validate_addr,
12491         .ndo_do_ioctl           = bnx2x_ioctl,
12492         .ndo_change_mtu         = bnx2x_change_mtu,
12493         .ndo_fix_features       = bnx2x_fix_features,
12494         .ndo_set_features       = bnx2x_set_features,
12495         .ndo_tx_timeout         = bnx2x_tx_timeout,
12496 #ifdef CONFIG_NET_POLL_CONTROLLER
12497         .ndo_poll_controller    = poll_bnx2x,
12498 #endif
12499         .ndo_setup_tc           = bnx2x_setup_tc,
12500 #ifdef CONFIG_BNX2X_SRIOV
12501         .ndo_set_vf_mac         = bnx2x_set_vf_mac,
12502         .ndo_set_vf_vlan        = bnx2x_set_vf_vlan,
12503         .ndo_get_vf_config      = bnx2x_get_vf_config,
12504 #endif
12505 #ifdef NETDEV_FCOE_WWNN
12506         .ndo_fcoe_get_wwn       = bnx2x_fcoe_get_wwn,
12507 #endif
12508
12509 #ifdef CONFIG_NET_RX_BUSY_POLL
12510         .ndo_busy_poll          = bnx2x_low_latency_recv,
12511 #endif
12512         .ndo_get_phys_port_id   = bnx2x_get_phys_port_id,
12513         .ndo_set_vf_link_state  = bnx2x_set_vf_link_state,
12514 };
12515
12516 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
12517 {
12518         struct device *dev = &bp->pdev->dev;
12519
12520         if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)) != 0 &&
12521             dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)) != 0) {
12522                 dev_err(dev, "System does not support DMA, aborting\n");
12523                 return -EIO;
12524         }
12525
12526         return 0;
12527 }
12528
12529 static void bnx2x_disable_pcie_error_reporting(struct bnx2x *bp)
12530 {
12531         if (bp->flags & AER_ENABLED) {
12532                 pci_disable_pcie_error_reporting(bp->pdev);
12533                 bp->flags &= ~AER_ENABLED;
12534         }
12535 }
12536
12537 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
12538                           struct net_device *dev, unsigned long board_type)
12539 {
12540         int rc;
12541         u32 pci_cfg_dword;
12542         bool chip_is_e1x = (board_type == BCM57710 ||
12543                             board_type == BCM57711 ||
12544                             board_type == BCM57711E);
12545
12546         SET_NETDEV_DEV(dev, &pdev->dev);
12547
12548         bp->dev = dev;
12549         bp->pdev = pdev;
12550
12551         rc = pci_enable_device(pdev);
12552         if (rc) {
12553                 dev_err(&bp->pdev->dev,
12554                         "Cannot enable PCI device, aborting\n");
12555                 goto err_out;
12556         }
12557
12558         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
12559                 dev_err(&bp->pdev->dev,
12560                         "Cannot find PCI device base address, aborting\n");
12561                 rc = -ENODEV;
12562                 goto err_out_disable;
12563         }
12564
12565         if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
12566                 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
12567                 rc = -ENODEV;
12568                 goto err_out_disable;
12569         }
12570
12571         pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
12572         if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
12573             PCICFG_REVESION_ID_ERROR_VAL) {
12574                 pr_err("PCI device error, probably due to fan failure, aborting\n");
12575                 rc = -ENODEV;
12576                 goto err_out_disable;
12577         }
12578
12579         if (atomic_read(&pdev->enable_cnt) == 1) {
12580                 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
12581                 if (rc) {
12582                         dev_err(&bp->pdev->dev,
12583                                 "Cannot obtain PCI resources, aborting\n");
12584                         goto err_out_disable;
12585                 }
12586
12587                 pci_set_master(pdev);
12588                 pci_save_state(pdev);
12589         }
12590
12591         if (IS_PF(bp)) {
12592                 if (!pdev->pm_cap) {
12593                         dev_err(&bp->pdev->dev,
12594                                 "Cannot find power management capability, aborting\n");
12595                         rc = -EIO;
12596                         goto err_out_release;
12597                 }
12598         }
12599
12600         if (!pci_is_pcie(pdev)) {
12601                 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
12602                 rc = -EIO;
12603                 goto err_out_release;
12604         }
12605
12606         rc = bnx2x_set_coherency_mask(bp);
12607         if (rc)
12608                 goto err_out_release;
12609
12610         dev->mem_start = pci_resource_start(pdev, 0);
12611         dev->base_addr = dev->mem_start;
12612         dev->mem_end = pci_resource_end(pdev, 0);
12613
12614         dev->irq = pdev->irq;
12615
12616         bp->regview = pci_ioremap_bar(pdev, 0);
12617         if (!bp->regview) {
12618                 dev_err(&bp->pdev->dev,
12619                         "Cannot map register space, aborting\n");
12620                 rc = -ENOMEM;
12621                 goto err_out_release;
12622         }
12623
12624         /* In E1/E1H use pci device function given by kernel.
12625          * In E2/E3 read physical function from ME register since these chips
12626          * support Physical Device Assignment where kernel BDF maybe arbitrary
12627          * (depending on hypervisor).
12628          */
12629         if (chip_is_e1x) {
12630                 bp->pf_num = PCI_FUNC(pdev->devfn);
12631         } else {
12632                 /* chip is E2/3*/
12633                 pci_read_config_dword(bp->pdev,
12634                                       PCICFG_ME_REGISTER, &pci_cfg_dword);
12635                 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
12636                                   ME_REG_ABS_PF_NUM_SHIFT);
12637         }
12638         BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
12639
12640         /* clean indirect addresses */
12641         pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
12642                                PCICFG_VENDOR_ID_OFFSET);
12643
12644         /* AER (Advanced Error reporting) configuration */
12645         rc = pci_enable_pcie_error_reporting(pdev);
12646         if (!rc)
12647                 bp->flags |= AER_ENABLED;
12648         else
12649                 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc);
12650
12651         /*
12652          * Clean the following indirect addresses for all functions since it
12653          * is not used by the driver.
12654          */
12655         if (IS_PF(bp)) {
12656                 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12657                 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12658                 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12659                 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12660
12661                 if (chip_is_e1x) {
12662                         REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12663                         REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12664                         REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12665                         REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12666                 }
12667
12668                 /* Enable internal target-read (in case we are probed after PF
12669                  * FLR). Must be done prior to any BAR read access. Only for
12670                  * 57712 and up
12671                  */
12672                 if (!chip_is_e1x)
12673                         REG_WR(bp,
12674                                PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12675         }
12676
12677         dev->watchdog_timeo = TX_TIMEOUT;
12678
12679         dev->netdev_ops = &bnx2x_netdev_ops;
12680         bnx2x_set_ethtool_ops(bp, dev);
12681
12682         dev->priv_flags |= IFF_UNICAST_FLT;
12683
12684         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12685                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12686                 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12687                 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12688         if (!CHIP_IS_E1x(bp)) {
12689                 dev->hw_features |= NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL |
12690                                     NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
12691                 dev->hw_enc_features =
12692                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12693                         NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12694                         NETIF_F_GSO_IPIP |
12695                         NETIF_F_GSO_SIT |
12696                         NETIF_F_GSO_GRE | NETIF_F_GSO_UDP_TUNNEL;
12697         }
12698
12699         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12700                 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12701
12702         dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12703         dev->features |= NETIF_F_HIGHDMA;
12704
12705         /* Add Loopback capability to the device */
12706         dev->hw_features |= NETIF_F_LOOPBACK;
12707
12708 #ifdef BCM_DCBNL
12709         dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12710 #endif
12711
12712         /* get_port_hwinfo() will set prtad and mmds properly */
12713         bp->mdio.prtad = MDIO_PRTAD_NONE;
12714         bp->mdio.mmds = 0;
12715         bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12716         bp->mdio.dev = dev;
12717         bp->mdio.mdio_read = bnx2x_mdio_read;
12718         bp->mdio.mdio_write = bnx2x_mdio_write;
12719
12720         return 0;
12721
12722 err_out_release:
12723         if (atomic_read(&pdev->enable_cnt) == 1)
12724                 pci_release_regions(pdev);
12725
12726 err_out_disable:
12727         pci_disable_device(pdev);
12728
12729 err_out:
12730         return rc;
12731 }
12732
12733 static int bnx2x_check_firmware(struct bnx2x *bp)
12734 {
12735         const struct firmware *firmware = bp->firmware;
12736         struct bnx2x_fw_file_hdr *fw_hdr;
12737         struct bnx2x_fw_file_section *sections;
12738         u32 offset, len, num_ops;
12739         __be16 *ops_offsets;
12740         int i;
12741         const u8 *fw_ver;
12742
12743         if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12744                 BNX2X_ERR("Wrong FW size\n");
12745                 return -EINVAL;
12746         }
12747
12748         fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12749         sections = (struct bnx2x_fw_file_section *)fw_hdr;
12750
12751         /* Make sure none of the offsets and sizes make us read beyond
12752          * the end of the firmware data */
12753         for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12754                 offset = be32_to_cpu(sections[i].offset);
12755                 len = be32_to_cpu(sections[i].len);
12756                 if (offset + len > firmware->size) {
12757                         BNX2X_ERR("Section %d length is out of bounds\n", i);
12758                         return -EINVAL;
12759                 }
12760         }
12761
12762         /* Likewise for the init_ops offsets */
12763         offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12764         ops_offsets = (__force __be16 *)(firmware->data + offset);
12765         num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12766
12767         for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12768                 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12769                         BNX2X_ERR("Section offset %d is out of bounds\n", i);
12770                         return -EINVAL;
12771                 }
12772         }
12773
12774         /* Check FW version */
12775         offset = be32_to_cpu(fw_hdr->fw_version.offset);
12776         fw_ver = firmware->data + offset;
12777         if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12778             (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12779             (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12780             (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12781                 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12782                        fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12783                        BCM_5710_FW_MAJOR_VERSION,
12784                        BCM_5710_FW_MINOR_VERSION,
12785                        BCM_5710_FW_REVISION_VERSION,
12786                        BCM_5710_FW_ENGINEERING_VERSION);
12787                 return -EINVAL;
12788         }
12789
12790         return 0;
12791 }
12792
12793 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12794 {
12795         const __be32 *source = (const __be32 *)_source;
12796         u32 *target = (u32 *)_target;
12797         u32 i;
12798
12799         for (i = 0; i < n/4; i++)
12800                 target[i] = be32_to_cpu(source[i]);
12801 }
12802
12803 /*
12804    Ops array is stored in the following format:
12805    {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12806  */
12807 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12808 {
12809         const __be32 *source = (const __be32 *)_source;
12810         struct raw_op *target = (struct raw_op *)_target;
12811         u32 i, j, tmp;
12812
12813         for (i = 0, j = 0; i < n/8; i++, j += 2) {
12814                 tmp = be32_to_cpu(source[j]);
12815                 target[i].op = (tmp >> 24) & 0xff;
12816                 target[i].offset = tmp & 0xffffff;
12817                 target[i].raw_data = be32_to_cpu(source[j + 1]);
12818         }
12819 }
12820
12821 /* IRO array is stored in the following format:
12822  * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12823  */
12824 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12825 {
12826         const __be32 *source = (const __be32 *)_source;
12827         struct iro *target = (struct iro *)_target;
12828         u32 i, j, tmp;
12829
12830         for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12831                 target[i].base = be32_to_cpu(source[j]);
12832                 j++;
12833                 tmp = be32_to_cpu(source[j]);
12834                 target[i].m1 = (tmp >> 16) & 0xffff;
12835                 target[i].m2 = tmp & 0xffff;
12836                 j++;
12837                 tmp = be32_to_cpu(source[j]);
12838                 target[i].m3 = (tmp >> 16) & 0xffff;
12839                 target[i].size = tmp & 0xffff;
12840                 j++;
12841         }
12842 }
12843
12844 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12845 {
12846         const __be16 *source = (const __be16 *)_source;
12847         u16 *target = (u16 *)_target;
12848         u32 i;
12849
12850         for (i = 0; i < n/2; i++)
12851                 target[i] = be16_to_cpu(source[i]);
12852 }
12853
12854 #define BNX2X_ALLOC_AND_SET(arr, lbl, func)                             \
12855 do {                                                                    \
12856         u32 len = be32_to_cpu(fw_hdr->arr.len);                         \
12857         bp->arr = kmalloc(len, GFP_KERNEL);                             \
12858         if (!bp->arr)                                                   \
12859                 goto lbl;                                               \
12860         func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset),      \
12861              (u8 *)bp->arr, len);                                       \
12862 } while (0)
12863
12864 static int bnx2x_init_firmware(struct bnx2x *bp)
12865 {
12866         const char *fw_file_name;
12867         struct bnx2x_fw_file_hdr *fw_hdr;
12868         int rc;
12869
12870         if (bp->firmware)
12871                 return 0;
12872
12873         if (CHIP_IS_E1(bp))
12874                 fw_file_name = FW_FILE_NAME_E1;
12875         else if (CHIP_IS_E1H(bp))
12876                 fw_file_name = FW_FILE_NAME_E1H;
12877         else if (!CHIP_IS_E1x(bp))
12878                 fw_file_name = FW_FILE_NAME_E2;
12879         else {
12880                 BNX2X_ERR("Unsupported chip revision\n");
12881                 return -EINVAL;
12882         }
12883         BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12884
12885         rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12886         if (rc) {
12887                 BNX2X_ERR("Can't load firmware file %s\n",
12888                           fw_file_name);
12889                 goto request_firmware_exit;
12890         }
12891
12892         rc = bnx2x_check_firmware(bp);
12893         if (rc) {
12894                 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12895                 goto request_firmware_exit;
12896         }
12897
12898         fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12899
12900         /* Initialize the pointers to the init arrays */
12901         /* Blob */
12902         BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12903
12904         /* Opcodes */
12905         BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12906
12907         /* Offsets */
12908         BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12909                             be16_to_cpu_n);
12910
12911         /* STORMs firmware */
12912         INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12913                         be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12914         INIT_TSEM_PRAM_DATA(bp)      = bp->firmware->data +
12915                         be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12916         INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12917                         be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12918         INIT_USEM_PRAM_DATA(bp)      = bp->firmware->data +
12919                         be32_to_cpu(fw_hdr->usem_pram_data.offset);
12920         INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12921                         be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12922         INIT_XSEM_PRAM_DATA(bp)      = bp->firmware->data +
12923                         be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12924         INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12925                         be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12926         INIT_CSEM_PRAM_DATA(bp)      = bp->firmware->data +
12927                         be32_to_cpu(fw_hdr->csem_pram_data.offset);
12928         /* IRO */
12929         BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12930
12931         return 0;
12932
12933 iro_alloc_err:
12934         kfree(bp->init_ops_offsets);
12935 init_offsets_alloc_err:
12936         kfree(bp->init_ops);
12937 init_ops_alloc_err:
12938         kfree(bp->init_data);
12939 request_firmware_exit:
12940         release_firmware(bp->firmware);
12941         bp->firmware = NULL;
12942
12943         return rc;
12944 }
12945
12946 static void bnx2x_release_firmware(struct bnx2x *bp)
12947 {
12948         kfree(bp->init_ops_offsets);
12949         kfree(bp->init_ops);
12950         kfree(bp->init_data);
12951         release_firmware(bp->firmware);
12952         bp->firmware = NULL;
12953 }
12954
12955 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12956         .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12957         .init_hw_cmn      = bnx2x_init_hw_common,
12958         .init_hw_port     = bnx2x_init_hw_port,
12959         .init_hw_func     = bnx2x_init_hw_func,
12960
12961         .reset_hw_cmn     = bnx2x_reset_common,
12962         .reset_hw_port    = bnx2x_reset_port,
12963         .reset_hw_func    = bnx2x_reset_func,
12964
12965         .gunzip_init      = bnx2x_gunzip_init,
12966         .gunzip_end       = bnx2x_gunzip_end,
12967
12968         .init_fw          = bnx2x_init_firmware,
12969         .release_fw       = bnx2x_release_firmware,
12970 };
12971
12972 void bnx2x__init_func_obj(struct bnx2x *bp)
12973 {
12974         /* Prepare DMAE related driver resources */
12975         bnx2x_setup_dmae(bp);
12976
12977         bnx2x_init_func_obj(bp, &bp->func_obj,
12978                             bnx2x_sp(bp, func_rdata),
12979                             bnx2x_sp_mapping(bp, func_rdata),
12980                             bnx2x_sp(bp, func_afex_rdata),
12981                             bnx2x_sp_mapping(bp, func_afex_rdata),
12982                             &bnx2x_func_sp_drv);
12983 }
12984
12985 /* must be called after sriov-enable */
12986 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12987 {
12988         int cid_count = BNX2X_L2_MAX_CID(bp);
12989
12990         if (IS_SRIOV(bp))
12991                 cid_count += BNX2X_VF_CIDS;
12992
12993         if (CNIC_SUPPORT(bp))
12994                 cid_count += CNIC_CID_MAX;
12995
12996         return roundup(cid_count, QM_CID_ROUND);
12997 }
12998
12999 /**
13000  * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13001  *
13002  * @dev:        pci device
13003  *
13004  */
13005 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev, int cnic_cnt)
13006 {
13007         int index;
13008         u16 control = 0;
13009
13010         /*
13011          * If MSI-X is not supported - return number of SBs needed to support
13012          * one fast path queue: one FP queue + SB for CNIC
13013          */
13014         if (!pdev->msix_cap) {
13015                 dev_info(&pdev->dev, "no msix capability found\n");
13016                 return 1 + cnic_cnt;
13017         }
13018         dev_info(&pdev->dev, "msix capability found\n");
13019
13020         /*
13021          * The value in the PCI configuration space is the index of the last
13022          * entry, namely one less than the actual size of the table, which is
13023          * exactly what we want to return from this function: number of all SBs
13024          * without the default SB.
13025          * For VFs there is no default SB, then we return (index+1).
13026          */
13027         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &control);
13028
13029         index = control & PCI_MSIX_FLAGS_QSIZE;
13030
13031         return index;
13032 }
13033
13034 static int set_max_cos_est(int chip_id)
13035 {
13036         switch (chip_id) {
13037         case BCM57710:
13038         case BCM57711:
13039         case BCM57711E:
13040                 return BNX2X_MULTI_TX_COS_E1X;
13041         case BCM57712:
13042         case BCM57712_MF:
13043                 return BNX2X_MULTI_TX_COS_E2_E3A0;
13044         case BCM57800:
13045         case BCM57800_MF:
13046         case BCM57810:
13047         case BCM57810_MF:
13048         case BCM57840_4_10:
13049         case BCM57840_2_20:
13050         case BCM57840_O:
13051         case BCM57840_MFO:
13052         case BCM57840_MF:
13053         case BCM57811:
13054         case BCM57811_MF:
13055                 return BNX2X_MULTI_TX_COS_E3B0;
13056         case BCM57712_VF:
13057         case BCM57800_VF:
13058         case BCM57810_VF:
13059         case BCM57840_VF:
13060         case BCM57811_VF:
13061                 return 1;
13062         default:
13063                 pr_err("Unknown board_type (%d), aborting\n", chip_id);
13064                 return -ENODEV;
13065         }
13066 }
13067
13068 static int set_is_vf(int chip_id)
13069 {
13070         switch (chip_id) {
13071         case BCM57712_VF:
13072         case BCM57800_VF:
13073         case BCM57810_VF:
13074         case BCM57840_VF:
13075         case BCM57811_VF:
13076                 return true;
13077         default:
13078                 return false;
13079         }
13080 }
13081
13082 /* nig_tsgen registers relative address */
13083 #define tsgen_ctrl 0x0
13084 #define tsgen_freecount 0x10
13085 #define tsgen_synctime_t0 0x20
13086 #define tsgen_offset_t0 0x28
13087 #define tsgen_drift_t0 0x30
13088 #define tsgen_synctime_t1 0x58
13089 #define tsgen_offset_t1 0x60
13090 #define tsgen_drift_t1 0x68
13091
13092 /* FW workaround for setting drift */
13093 static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
13094                                           int best_val, int best_period)
13095 {
13096         struct bnx2x_func_state_params func_params = {NULL};
13097         struct bnx2x_func_set_timesync_params *set_timesync_params =
13098                 &func_params.params.set_timesync;
13099
13100         /* Prepare parameters for function state transitions */
13101         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
13102         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
13103
13104         func_params.f_obj = &bp->func_obj;
13105         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
13106
13107         /* Function parameters */
13108         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
13109         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
13110         set_timesync_params->add_sub_drift_adjust_value =
13111                 drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
13112         set_timesync_params->drift_adjust_value = best_val;
13113         set_timesync_params->drift_adjust_period = best_period;
13114
13115         return bnx2x_func_state_change(bp, &func_params);
13116 }
13117
13118 static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
13119 {
13120         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13121         int rc;
13122         int drift_dir = 1;
13123         int val, period, period1, period2, dif, dif1, dif2;
13124         int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
13125
13126         DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
13127
13128         if (!netif_running(bp->dev)) {
13129                 DP(BNX2X_MSG_PTP,
13130                    "PTP adjfreq called while the interface is down\n");
13131                 return -EFAULT;
13132         }
13133
13134         if (ppb < 0) {
13135                 ppb = -ppb;
13136                 drift_dir = 0;
13137         }
13138
13139         if (ppb == 0) {
13140                 best_val = 1;
13141                 best_period = 0x1FFFFFF;
13142         } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
13143                 best_val = 31;
13144                 best_period = 1;
13145         } else {
13146                 /* Changed not to allow val = 8, 16, 24 as these values
13147                  * are not supported in workaround.
13148                  */
13149                 for (val = 0; val <= 31; val++) {
13150                         if ((val & 0x7) == 0)
13151                                 continue;
13152                         period1 = val * 1000000 / ppb;
13153                         period2 = period1 + 1;
13154                         if (period1 != 0)
13155                                 dif1 = ppb - (val * 1000000 / period1);
13156                         else
13157                                 dif1 = BNX2X_MAX_PHC_DRIFT;
13158                         if (dif1 < 0)
13159                                 dif1 = -dif1;
13160                         dif2 = ppb - (val * 1000000 / period2);
13161                         if (dif2 < 0)
13162                                 dif2 = -dif2;
13163                         dif = (dif1 < dif2) ? dif1 : dif2;
13164                         period = (dif1 < dif2) ? period1 : period2;
13165                         if (dif < best_dif) {
13166                                 best_dif = dif;
13167                                 best_val = val;
13168                                 best_period = period;
13169                         }
13170                 }
13171         }
13172
13173         rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
13174                                             best_period);
13175         if (rc) {
13176                 BNX2X_ERR("Failed to set drift\n");
13177                 return -EFAULT;
13178         }
13179
13180         DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
13181            best_period);
13182
13183         return 0;
13184 }
13185
13186 static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
13187 {
13188         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13189         u64 now;
13190
13191         DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
13192
13193         now = timecounter_read(&bp->timecounter);
13194         now += delta;
13195         /* Re-init the timecounter */
13196         timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
13197
13198         return 0;
13199 }
13200
13201 static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
13202 {
13203         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13204         u64 ns;
13205         u32 remainder;
13206
13207         ns = timecounter_read(&bp->timecounter);
13208
13209         DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
13210
13211         ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
13212         ts->tv_nsec = remainder;
13213
13214         return 0;
13215 }
13216
13217 static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
13218                              const struct timespec *ts)
13219 {
13220         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13221         u64 ns;
13222
13223         ns = ts->tv_sec * 1000000000ULL;
13224         ns += ts->tv_nsec;
13225
13226         DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
13227
13228         /* Re-init the timecounter */
13229         timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
13230
13231         return 0;
13232 }
13233
13234 /* Enable (or disable) ancillary features of the phc subsystem */
13235 static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
13236                             struct ptp_clock_request *rq, int on)
13237 {
13238         struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
13239
13240         BNX2X_ERR("PHC ancillary features are not supported\n");
13241         return -ENOTSUPP;
13242 }
13243
13244 void bnx2x_register_phc(struct bnx2x *bp)
13245 {
13246         /* Fill the ptp_clock_info struct and register PTP clock*/
13247         bp->ptp_clock_info.owner = THIS_MODULE;
13248         snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
13249         bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
13250         bp->ptp_clock_info.n_alarm = 0;
13251         bp->ptp_clock_info.n_ext_ts = 0;
13252         bp->ptp_clock_info.n_per_out = 0;
13253         bp->ptp_clock_info.pps = 0;
13254         bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
13255         bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
13256         bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
13257         bp->ptp_clock_info.settime = bnx2x_ptp_settime;
13258         bp->ptp_clock_info.enable = bnx2x_ptp_enable;
13259
13260         bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
13261         if (IS_ERR(bp->ptp_clock)) {
13262                 bp->ptp_clock = NULL;
13263                 BNX2X_ERR("PTP clock registeration failed\n");
13264         }
13265 }
13266
13267 static int bnx2x_init_one(struct pci_dev *pdev,
13268                                     const struct pci_device_id *ent)
13269 {
13270         struct net_device *dev = NULL;
13271         struct bnx2x *bp;
13272         enum pcie_link_width pcie_width;
13273         enum pci_bus_speed pcie_speed;
13274         int rc, max_non_def_sbs;
13275         int rx_count, tx_count, rss_count, doorbell_size;
13276         int max_cos_est;
13277         bool is_vf;
13278         int cnic_cnt;
13279
13280         /* An estimated maximum supported CoS number according to the chip
13281          * version.
13282          * We will try to roughly estimate the maximum number of CoSes this chip
13283          * may support in order to minimize the memory allocated for Tx
13284          * netdev_queue's. This number will be accurately calculated during the
13285          * initialization of bp->max_cos based on the chip versions AND chip
13286          * revision in the bnx2x_init_bp().
13287          */
13288         max_cos_est = set_max_cos_est(ent->driver_data);
13289         if (max_cos_est < 0)
13290                 return max_cos_est;
13291         is_vf = set_is_vf(ent->driver_data);
13292         cnic_cnt = is_vf ? 0 : 1;
13293
13294         max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt);
13295
13296         /* add another SB for VF as it has no default SB */
13297         max_non_def_sbs += is_vf ? 1 : 0;
13298
13299         /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13300         rss_count = max_non_def_sbs - cnic_cnt;
13301
13302         if (rss_count < 1)
13303                 return -EINVAL;
13304
13305         /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13306         rx_count = rss_count + cnic_cnt;
13307
13308         /* Maximum number of netdev Tx queues:
13309          * Maximum TSS queues * Maximum supported number of CoS  + FCoE L2
13310          */
13311         tx_count = rss_count * max_cos_est + cnic_cnt;
13312
13313         /* dev zeroed in init_etherdev */
13314         dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
13315         if (!dev)
13316                 return -ENOMEM;
13317
13318         bp = netdev_priv(dev);
13319
13320         bp->flags = 0;
13321         if (is_vf)
13322                 bp->flags |= IS_VF_FLAG;
13323
13324         bp->igu_sb_cnt = max_non_def_sbs;
13325         bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
13326         bp->msg_enable = debug;
13327         bp->cnic_support = cnic_cnt;
13328         bp->cnic_probe = bnx2x_cnic_probe;
13329
13330         pci_set_drvdata(pdev, dev);
13331
13332         rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
13333         if (rc < 0) {
13334                 free_netdev(dev);
13335                 return rc;
13336         }
13337
13338         BNX2X_DEV_INFO("This is a %s function\n",
13339                        IS_PF(bp) ? "physical" : "virtual");
13340         BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
13341         BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
13342         BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13343                        tx_count, rx_count);
13344
13345         rc = bnx2x_init_bp(bp);
13346         if (rc)
13347                 goto init_one_exit;
13348
13349         /* Map doorbells here as we need the real value of bp->max_cos which
13350          * is initialized in bnx2x_init_bp() to determine the number of
13351          * l2 connections.
13352          */
13353         if (IS_VF(bp)) {
13354                 bp->doorbells = bnx2x_vf_doorbells(bp);
13355                 rc = bnx2x_vf_pci_alloc(bp);
13356                 if (rc)
13357                         goto init_one_exit;
13358         } else {
13359                 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
13360                 if (doorbell_size > pci_resource_len(pdev, 2)) {
13361                         dev_err(&bp->pdev->dev,
13362                                 "Cannot map doorbells, bar size too small, aborting\n");
13363                         rc = -ENOMEM;
13364                         goto init_one_exit;
13365                 }
13366                 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
13367                                                 doorbell_size);
13368         }
13369         if (!bp->doorbells) {
13370                 dev_err(&bp->pdev->dev,
13371                         "Cannot map doorbell space, aborting\n");
13372                 rc = -ENOMEM;
13373                 goto init_one_exit;
13374         }
13375
13376         if (IS_VF(bp)) {
13377                 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
13378                 if (rc)
13379                         goto init_one_exit;
13380         }
13381
13382         /* Enable SRIOV if capability found in configuration space */
13383         rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
13384         if (rc)
13385                 goto init_one_exit;
13386
13387         /* calc qm_cid_count */
13388         bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
13389         BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
13390
13391         /* disable FCOE L2 queue for E1x*/
13392         if (CHIP_IS_E1x(bp))
13393                 bp->flags |= NO_FCOE_FLAG;
13394
13395         /* Set bp->num_queues for MSI-X mode*/
13396         bnx2x_set_num_queues(bp);
13397
13398         /* Configure interrupt mode: try to enable MSI-X/MSI if
13399          * needed.
13400          */
13401         rc = bnx2x_set_int_mode(bp);
13402         if (rc) {
13403                 dev_err(&pdev->dev, "Cannot set interrupts\n");
13404                 goto init_one_exit;
13405         }
13406         BNX2X_DEV_INFO("set interrupts successfully\n");
13407
13408         /* register the net device */
13409         rc = register_netdev(dev);
13410         if (rc) {
13411                 dev_err(&pdev->dev, "Cannot register net device\n");
13412                 goto init_one_exit;
13413         }
13414         BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
13415
13416         if (!NO_FCOE(bp)) {
13417                 /* Add storage MAC address */
13418                 rtnl_lock();
13419                 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13420                 rtnl_unlock();
13421         }
13422         if (pcie_get_minimum_link(bp->pdev, &pcie_speed, &pcie_width) ||
13423             pcie_speed == PCI_SPEED_UNKNOWN ||
13424             pcie_width == PCIE_LNK_WIDTH_UNKNOWN)
13425                 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13426         else
13427                 BNX2X_DEV_INFO(
13428                        "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13429                        board_info[ent->driver_data].name,
13430                        (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
13431                        pcie_width,
13432                        pcie_speed == PCIE_SPEED_2_5GT ? "2.5GHz" :
13433                        pcie_speed == PCIE_SPEED_5_0GT ? "5.0GHz" :
13434                        pcie_speed == PCIE_SPEED_8_0GT ? "8.0GHz" :
13435                        "Unknown",
13436                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
13437
13438         bnx2x_register_phc(bp);
13439
13440         return 0;
13441
13442 init_one_exit:
13443         bnx2x_disable_pcie_error_reporting(bp);
13444
13445         if (bp->regview)
13446                 iounmap(bp->regview);
13447
13448         if (IS_PF(bp) && bp->doorbells)
13449                 iounmap(bp->doorbells);
13450
13451         free_netdev(dev);
13452
13453         if (atomic_read(&pdev->enable_cnt) == 1)
13454                 pci_release_regions(pdev);
13455
13456         pci_disable_device(pdev);
13457
13458         return rc;
13459 }
13460
13461 static void __bnx2x_remove(struct pci_dev *pdev,
13462                            struct net_device *dev,
13463                            struct bnx2x *bp,
13464                            bool remove_netdev)
13465 {
13466         if (bp->ptp_clock) {
13467                 ptp_clock_unregister(bp->ptp_clock);
13468                 bp->ptp_clock = NULL;
13469         }
13470
13471         /* Delete storage MAC address */
13472         if (!NO_FCOE(bp)) {
13473                 rtnl_lock();
13474                 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
13475                 rtnl_unlock();
13476         }
13477
13478 #ifdef BCM_DCBNL
13479         /* Delete app tlvs from dcbnl */
13480         bnx2x_dcbnl_update_applist(bp, true);
13481 #endif
13482
13483         if (IS_PF(bp) &&
13484             !BP_NOMCP(bp) &&
13485             (bp->flags & BC_SUPPORTS_RMMOD_CMD))
13486                 bnx2x_fw_command(bp, DRV_MSG_CODE_RMMOD, 0);
13487
13488         /* Close the interface - either directly or implicitly */
13489         if (remove_netdev) {
13490                 unregister_netdev(dev);
13491         } else {
13492                 rtnl_lock();
13493                 dev_close(dev);
13494                 rtnl_unlock();
13495         }
13496
13497         bnx2x_iov_remove_one(bp);
13498
13499         /* Power on: we can't let PCI layer write to us while we are in D3 */
13500         if (IS_PF(bp))
13501                 bnx2x_set_power_state(bp, PCI_D0);
13502
13503         /* Disable MSI/MSI-X */
13504         bnx2x_disable_msi(bp);
13505
13506         /* Power off */
13507         if (IS_PF(bp))
13508                 bnx2x_set_power_state(bp, PCI_D3hot);
13509
13510         /* Make sure RESET task is not scheduled before continuing */
13511         cancel_delayed_work_sync(&bp->sp_rtnl_task);
13512
13513         /* send message via vfpf channel to release the resources of this vf */
13514         if (IS_VF(bp))
13515                 bnx2x_vfpf_release(bp);
13516
13517         /* Assumes no further PCIe PM changes will occur */
13518         if (system_state == SYSTEM_POWER_OFF) {
13519                 pci_wake_from_d3(pdev, bp->wol);
13520                 pci_set_power_state(pdev, PCI_D3hot);
13521         }
13522
13523         bnx2x_disable_pcie_error_reporting(bp);
13524         if (remove_netdev) {
13525                 if (bp->regview)
13526                         iounmap(bp->regview);
13527
13528                 /* For vfs, doorbells are part of the regview and were unmapped
13529                  * along with it. FW is only loaded by PF.
13530                  */
13531                 if (IS_PF(bp)) {
13532                         if (bp->doorbells)
13533                                 iounmap(bp->doorbells);
13534
13535                         bnx2x_release_firmware(bp);
13536                 } else {
13537                         bnx2x_vf_pci_dealloc(bp);
13538                 }
13539                 bnx2x_free_mem_bp(bp);
13540
13541                 free_netdev(dev);
13542
13543                 if (atomic_read(&pdev->enable_cnt) == 1)
13544                         pci_release_regions(pdev);
13545
13546                 pci_disable_device(pdev);
13547         }
13548 }
13549
13550 static void bnx2x_remove_one(struct pci_dev *pdev)
13551 {
13552         struct net_device *dev = pci_get_drvdata(pdev);
13553         struct bnx2x *bp;
13554
13555         if (!dev) {
13556                 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
13557                 return;
13558         }
13559         bp = netdev_priv(dev);
13560
13561         __bnx2x_remove(pdev, dev, bp, true);
13562 }
13563
13564 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
13565 {
13566         bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
13567
13568         bp->rx_mode = BNX2X_RX_MODE_NONE;
13569
13570         if (CNIC_LOADED(bp))
13571                 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
13572
13573         /* Stop Tx */
13574         bnx2x_tx_disable(bp);
13575         /* Delete all NAPI objects */
13576         bnx2x_del_all_napi(bp);
13577         if (CNIC_LOADED(bp))
13578                 bnx2x_del_all_napi_cnic(bp);
13579         netdev_reset_tc(bp->dev);
13580
13581         del_timer_sync(&bp->timer);
13582         cancel_delayed_work_sync(&bp->sp_task);
13583         cancel_delayed_work_sync(&bp->period_task);
13584
13585         spin_lock_bh(&bp->stats_lock);
13586         bp->stats_state = STATS_STATE_DISABLED;
13587         spin_unlock_bh(&bp->stats_lock);
13588
13589         bnx2x_save_statistics(bp);
13590
13591         netif_carrier_off(bp->dev);
13592
13593         return 0;
13594 }
13595
13596 /**
13597  * bnx2x_io_error_detected - called when PCI error is detected
13598  * @pdev: Pointer to PCI device
13599  * @state: The current pci connection state
13600  *
13601  * This function is called after a PCI bus error affecting
13602  * this device has been detected.
13603  */
13604 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
13605                                                 pci_channel_state_t state)
13606 {
13607         struct net_device *dev = pci_get_drvdata(pdev);
13608         struct bnx2x *bp = netdev_priv(dev);
13609
13610         rtnl_lock();
13611
13612         BNX2X_ERR("IO error detected\n");
13613
13614         netif_device_detach(dev);
13615
13616         if (state == pci_channel_io_perm_failure) {
13617                 rtnl_unlock();
13618                 return PCI_ERS_RESULT_DISCONNECT;
13619         }
13620
13621         if (netif_running(dev))
13622                 bnx2x_eeh_nic_unload(bp);
13623
13624         bnx2x_prev_path_mark_eeh(bp);
13625
13626         pci_disable_device(pdev);
13627
13628         rtnl_unlock();
13629
13630         /* Request a slot reset */
13631         return PCI_ERS_RESULT_NEED_RESET;
13632 }
13633
13634 /**
13635  * bnx2x_io_slot_reset - called after the PCI bus has been reset
13636  * @pdev: Pointer to PCI device
13637  *
13638  * Restart the card from scratch, as if from a cold-boot.
13639  */
13640 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
13641 {
13642         struct net_device *dev = pci_get_drvdata(pdev);
13643         struct bnx2x *bp = netdev_priv(dev);
13644         int i;
13645
13646         rtnl_lock();
13647         BNX2X_ERR("IO slot reset initializing...\n");
13648         if (pci_enable_device(pdev)) {
13649                 dev_err(&pdev->dev,
13650                         "Cannot re-enable PCI device after reset\n");
13651                 rtnl_unlock();
13652                 return PCI_ERS_RESULT_DISCONNECT;
13653         }
13654
13655         pci_set_master(pdev);
13656         pci_restore_state(pdev);
13657         pci_save_state(pdev);
13658
13659         if (netif_running(dev))
13660                 bnx2x_set_power_state(bp, PCI_D0);
13661
13662         if (netif_running(dev)) {
13663                 BNX2X_ERR("IO slot reset --> driver unload\n");
13664
13665                 /* MCP should have been reset; Need to wait for validity */
13666                 bnx2x_init_shmem(bp);
13667
13668                 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
13669                         u32 v;
13670
13671                         v = SHMEM2_RD(bp,
13672                                       drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
13673                         SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
13674                                   v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
13675                 }
13676                 bnx2x_drain_tx_queues(bp);
13677                 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
13678                 bnx2x_netif_stop(bp, 1);
13679                 bnx2x_free_irq(bp);
13680
13681                 /* Report UNLOAD_DONE to MCP */
13682                 bnx2x_send_unload_done(bp, true);
13683
13684                 bp->sp_state = 0;
13685                 bp->port.pmf = 0;
13686
13687                 bnx2x_prev_unload(bp);
13688
13689                 /* We should have reseted the engine, so It's fair to
13690                  * assume the FW will no longer write to the bnx2x driver.
13691                  */
13692                 bnx2x_squeeze_objects(bp);
13693                 bnx2x_free_skbs(bp);
13694                 for_each_rx_queue(bp, i)
13695                         bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
13696                 bnx2x_free_fp_mem(bp);
13697                 bnx2x_free_mem(bp);
13698
13699                 bp->state = BNX2X_STATE_CLOSED;
13700         }
13701
13702         rtnl_unlock();
13703
13704         /* If AER, perform cleanup of the PCIe registers */
13705         if (bp->flags & AER_ENABLED) {
13706                 if (pci_cleanup_aer_uncorrect_error_status(pdev))
13707                         BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
13708                 else
13709                         DP(NETIF_MSG_HW, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
13710         }
13711
13712         return PCI_ERS_RESULT_RECOVERED;
13713 }
13714
13715 /**
13716  * bnx2x_io_resume - called when traffic can start flowing again
13717  * @pdev: Pointer to PCI device
13718  *
13719  * This callback is called when the error recovery driver tells us that
13720  * its OK to resume normal operation.
13721  */
13722 static void bnx2x_io_resume(struct pci_dev *pdev)
13723 {
13724         struct net_device *dev = pci_get_drvdata(pdev);
13725         struct bnx2x *bp = netdev_priv(dev);
13726
13727         if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
13728                 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
13729                 return;
13730         }
13731
13732         rtnl_lock();
13733
13734         bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
13735                                                         DRV_MSG_SEQ_NUMBER_MASK;
13736
13737         if (netif_running(dev))
13738                 bnx2x_nic_load(bp, LOAD_NORMAL);
13739
13740         netif_device_attach(dev);
13741
13742         rtnl_unlock();
13743 }
13744
13745 static const struct pci_error_handlers bnx2x_err_handler = {
13746         .error_detected = bnx2x_io_error_detected,
13747         .slot_reset     = bnx2x_io_slot_reset,
13748         .resume         = bnx2x_io_resume,
13749 };
13750
13751 static void bnx2x_shutdown(struct pci_dev *pdev)
13752 {
13753         struct net_device *dev = pci_get_drvdata(pdev);
13754         struct bnx2x *bp;
13755
13756         if (!dev)
13757                 return;
13758
13759         bp = netdev_priv(dev);
13760         if (!bp)
13761                 return;
13762
13763         rtnl_lock();
13764         netif_device_detach(dev);
13765         rtnl_unlock();
13766
13767         /* Don't remove the netdevice, as there are scenarios which will cause
13768          * the kernel to hang, e.g., when trying to remove bnx2i while the
13769          * rootfs is mounted from SAN.
13770          */
13771         __bnx2x_remove(pdev, dev, bp, false);
13772 }
13773
13774 static struct pci_driver bnx2x_pci_driver = {
13775         .name        = DRV_MODULE_NAME,
13776         .id_table    = bnx2x_pci_tbl,
13777         .probe       = bnx2x_init_one,
13778         .remove      = bnx2x_remove_one,
13779         .suspend     = bnx2x_suspend,
13780         .resume      = bnx2x_resume,
13781         .err_handler = &bnx2x_err_handler,
13782 #ifdef CONFIG_BNX2X_SRIOV
13783         .sriov_configure = bnx2x_sriov_configure,
13784 #endif
13785         .shutdown    = bnx2x_shutdown,
13786 };
13787
13788 static int __init bnx2x_init(void)
13789 {
13790         int ret;
13791
13792         pr_info("%s", version);
13793
13794         bnx2x_wq = create_singlethread_workqueue("bnx2x");
13795         if (bnx2x_wq == NULL) {
13796                 pr_err("Cannot create workqueue\n");
13797                 return -ENOMEM;
13798         }
13799         bnx2x_iov_wq = create_singlethread_workqueue("bnx2x_iov");
13800         if (!bnx2x_iov_wq) {
13801                 pr_err("Cannot create iov workqueue\n");
13802                 destroy_workqueue(bnx2x_wq);
13803                 return -ENOMEM;
13804         }
13805
13806         ret = pci_register_driver(&bnx2x_pci_driver);
13807         if (ret) {
13808                 pr_err("Cannot register driver\n");
13809                 destroy_workqueue(bnx2x_wq);
13810                 destroy_workqueue(bnx2x_iov_wq);
13811         }
13812         return ret;
13813 }
13814
13815 static void __exit bnx2x_cleanup(void)
13816 {
13817         struct list_head *pos, *q;
13818
13819         pci_unregister_driver(&bnx2x_pci_driver);
13820
13821         destroy_workqueue(bnx2x_wq);
13822         destroy_workqueue(bnx2x_iov_wq);
13823
13824         /* Free globally allocated resources */
13825         list_for_each_safe(pos, q, &bnx2x_prev_list) {
13826                 struct bnx2x_prev_path_list *tmp =
13827                         list_entry(pos, struct bnx2x_prev_path_list, list);
13828                 list_del(pos);
13829                 kfree(tmp);
13830         }
13831 }
13832
13833 void bnx2x_notify_link_changed(struct bnx2x *bp)
13834 {
13835         REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
13836 }
13837
13838 module_init(bnx2x_init);
13839 module_exit(bnx2x_cleanup);
13840
13841 /**
13842  * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13843  *
13844  * @bp:         driver handle
13845  * @set:        set or clear the CAM entry
13846  *
13847  * This function will wait until the ramrod completion returns.
13848  * Return 0 if success, -ENODEV if ramrod doesn't return.
13849  */
13850 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
13851 {
13852         unsigned long ramrod_flags = 0;
13853
13854         __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
13855         return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
13856                                  &bp->iscsi_l2_mac_obj, true,
13857                                  BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
13858 }
13859
13860 /* count denotes the number of new completions we have seen */
13861 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
13862 {
13863         struct eth_spe *spe;
13864         int cxt_index, cxt_offset;
13865
13866 #ifdef BNX2X_STOP_ON_ERROR
13867         if (unlikely(bp->panic))
13868                 return;
13869 #endif
13870
13871         spin_lock_bh(&bp->spq_lock);
13872         BUG_ON(bp->cnic_spq_pending < count);
13873         bp->cnic_spq_pending -= count;
13874
13875         for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
13876                 u16 type =  (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
13877                                 & SPE_HDR_CONN_TYPE) >>
13878                                 SPE_HDR_CONN_TYPE_SHIFT;
13879                 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
13880                                 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
13881
13882                 /* Set validation for iSCSI L2 client before sending SETUP
13883                  *  ramrod
13884                  */
13885                 if (type == ETH_CONNECTION_TYPE) {
13886                         if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
13887                                 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
13888                                         ILT_PAGE_CIDS;
13889                                 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
13890                                         (cxt_index * ILT_PAGE_CIDS);
13891                                 bnx2x_set_ctx_validation(bp,
13892                                         &bp->context[cxt_index].
13893                                                          vcxt[cxt_offset].eth,
13894                                         BNX2X_ISCSI_ETH_CID(bp));
13895                         }
13896                 }
13897
13898                 /*
13899                  * There may be not more than 8 L2, not more than 8 L5 SPEs
13900                  * and in the air. We also check that number of outstanding
13901                  * COMMON ramrods is not more than the EQ and SPQ can
13902                  * accommodate.
13903                  */
13904                 if (type == ETH_CONNECTION_TYPE) {
13905                         if (!atomic_read(&bp->cq_spq_left))
13906                                 break;
13907                         else
13908                                 atomic_dec(&bp->cq_spq_left);
13909                 } else if (type == NONE_CONNECTION_TYPE) {
13910                         if (!atomic_read(&bp->eq_spq_left))
13911                                 break;
13912                         else
13913                                 atomic_dec(&bp->eq_spq_left);
13914                 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13915                            (type == FCOE_CONNECTION_TYPE)) {
13916                         if (bp->cnic_spq_pending >=
13917                             bp->cnic_eth_dev.max_kwqe_pending)
13918                                 break;
13919                         else
13920                                 bp->cnic_spq_pending++;
13921                 } else {
13922                         BNX2X_ERR("Unknown SPE type: %d\n", type);
13923                         bnx2x_panic();
13924                         break;
13925                 }
13926
13927                 spe = bnx2x_sp_get_next(bp);
13928                 *spe = *bp->cnic_kwq_cons;
13929
13930                 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13931                    bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13932
13933                 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13934                         bp->cnic_kwq_cons = bp->cnic_kwq;
13935                 else
13936                         bp->cnic_kwq_cons++;
13937         }
13938         bnx2x_sp_prod_update(bp);
13939         spin_unlock_bh(&bp->spq_lock);
13940 }
13941
13942 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13943                                struct kwqe_16 *kwqes[], u32 count)
13944 {
13945         struct bnx2x *bp = netdev_priv(dev);
13946         int i;
13947
13948 #ifdef BNX2X_STOP_ON_ERROR
13949         if (unlikely(bp->panic)) {
13950                 BNX2X_ERR("Can't post to SP queue while panic\n");
13951                 return -EIO;
13952         }
13953 #endif
13954
13955         if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13956             (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13957                 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13958                 return -EAGAIN;
13959         }
13960
13961         spin_lock_bh(&bp->spq_lock);
13962
13963         for (i = 0; i < count; i++) {
13964                 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13965
13966                 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13967                         break;
13968
13969                 *bp->cnic_kwq_prod = *spe;
13970
13971                 bp->cnic_kwq_pending++;
13972
13973                 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13974                    spe->hdr.conn_and_cmd_data, spe->hdr.type,
13975                    spe->data.update_data_addr.hi,
13976                    spe->data.update_data_addr.lo,
13977                    bp->cnic_kwq_pending);
13978
13979                 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13980                         bp->cnic_kwq_prod = bp->cnic_kwq;
13981                 else
13982                         bp->cnic_kwq_prod++;
13983         }
13984
13985         spin_unlock_bh(&bp->spq_lock);
13986
13987         if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13988                 bnx2x_cnic_sp_post(bp, 0);
13989
13990         return i;
13991 }
13992
13993 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13994 {
13995         struct cnic_ops *c_ops;
13996         int rc = 0;
13997
13998         mutex_lock(&bp->cnic_mutex);
13999         c_ops = rcu_dereference_protected(bp->cnic_ops,
14000                                           lockdep_is_held(&bp->cnic_mutex));
14001         if (c_ops)
14002                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14003         mutex_unlock(&bp->cnic_mutex);
14004
14005         return rc;
14006 }
14007
14008 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
14009 {
14010         struct cnic_ops *c_ops;
14011         int rc = 0;
14012
14013         rcu_read_lock();
14014         c_ops = rcu_dereference(bp->cnic_ops);
14015         if (c_ops)
14016                 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
14017         rcu_read_unlock();
14018
14019         return rc;
14020 }
14021
14022 /*
14023  * for commands that have no data
14024  */
14025 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
14026 {
14027         struct cnic_ctl_info ctl = {0};
14028
14029         ctl.cmd = cmd;
14030
14031         return bnx2x_cnic_ctl_send(bp, &ctl);
14032 }
14033
14034 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
14035 {
14036         struct cnic_ctl_info ctl = {0};
14037
14038         /* first we tell CNIC and only then we count this as a completion */
14039         ctl.cmd = CNIC_CTL_COMPLETION_CMD;
14040         ctl.data.comp.cid = cid;
14041         ctl.data.comp.error = err;
14042
14043         bnx2x_cnic_ctl_send_bh(bp, &ctl);
14044         bnx2x_cnic_sp_post(bp, 0);
14045 }
14046
14047 /* Called with netif_addr_lock_bh() taken.
14048  * Sets an rx_mode config for an iSCSI ETH client.
14049  * Doesn't block.
14050  * Completion should be checked outside.
14051  */
14052 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
14053 {
14054         unsigned long accept_flags = 0, ramrod_flags = 0;
14055         u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14056         int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
14057
14058         if (start) {
14059                 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14060                  * because it's the only way for UIO Queue to accept
14061                  * multicasts (in non-promiscuous mode only one Queue per
14062                  * function will receive multicast packets (leading in our
14063                  * case).
14064                  */
14065                 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
14066                 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
14067                 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
14068                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
14069
14070                 /* Clear STOP_PENDING bit if START is requested */
14071                 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
14072
14073                 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
14074         } else
14075                 /* Clear START_PENDING bit if STOP is requested */
14076                 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
14077
14078         if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
14079                 set_bit(sched_state, &bp->sp_state);
14080         else {
14081                 __set_bit(RAMROD_RX, &ramrod_flags);
14082                 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
14083                                     ramrod_flags);
14084         }
14085 }
14086
14087 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
14088 {
14089         struct bnx2x *bp = netdev_priv(dev);
14090         int rc = 0;
14091
14092         switch (ctl->cmd) {
14093         case DRV_CTL_CTXTBL_WR_CMD: {
14094                 u32 index = ctl->data.io.offset;
14095                 dma_addr_t addr = ctl->data.io.dma_addr;
14096
14097                 bnx2x_ilt_wr(bp, index, addr);
14098                 break;
14099         }
14100
14101         case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
14102                 int count = ctl->data.credit.credit_count;
14103
14104                 bnx2x_cnic_sp_post(bp, count);
14105                 break;
14106         }
14107
14108         /* rtnl_lock is held.  */
14109         case DRV_CTL_START_L2_CMD: {
14110                 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14111                 unsigned long sp_bits = 0;
14112
14113                 /* Configure the iSCSI classification object */
14114                 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
14115                                    cp->iscsi_l2_client_id,
14116                                    cp->iscsi_l2_cid, BP_FUNC(bp),
14117                                    bnx2x_sp(bp, mac_rdata),
14118                                    bnx2x_sp_mapping(bp, mac_rdata),
14119                                    BNX2X_FILTER_MAC_PENDING,
14120                                    &bp->sp_state, BNX2X_OBJ_TYPE_RX,
14121                                    &bp->macs_pool);
14122
14123                 /* Set iSCSI MAC address */
14124                 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
14125                 if (rc)
14126                         break;
14127
14128                 mmiowb();
14129                 barrier();
14130
14131                 /* Start accepting on iSCSI L2 ring */
14132
14133                 netif_addr_lock_bh(dev);
14134                 bnx2x_set_iscsi_eth_rx_mode(bp, true);
14135                 netif_addr_unlock_bh(dev);
14136
14137                 /* bits to wait on */
14138                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14139                 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
14140
14141                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14142                         BNX2X_ERR("rx_mode completion timed out!\n");
14143
14144                 break;
14145         }
14146
14147         /* rtnl_lock is held.  */
14148         case DRV_CTL_STOP_L2_CMD: {
14149                 unsigned long sp_bits = 0;
14150
14151                 /* Stop accepting on iSCSI L2 ring */
14152                 netif_addr_lock_bh(dev);
14153                 bnx2x_set_iscsi_eth_rx_mode(bp, false);
14154                 netif_addr_unlock_bh(dev);
14155
14156                 /* bits to wait on */
14157                 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
14158                 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
14159
14160                 if (!bnx2x_wait_sp_comp(bp, sp_bits))
14161                         BNX2X_ERR("rx_mode completion timed out!\n");
14162
14163                 mmiowb();
14164                 barrier();
14165
14166                 /* Unset iSCSI L2 MAC */
14167                 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
14168                                         BNX2X_ISCSI_ETH_MAC, true);
14169                 break;
14170         }
14171         case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
14172                 int count = ctl->data.credit.credit_count;
14173
14174                 smp_mb__before_atomic();
14175                 atomic_add(count, &bp->cq_spq_left);
14176                 smp_mb__after_atomic();
14177                 break;
14178         }
14179         case DRV_CTL_ULP_REGISTER_CMD: {
14180                 int ulp_type = ctl->data.register_data.ulp_type;
14181
14182                 if (CHIP_IS_E3(bp)) {
14183                         int idx = BP_FW_MB_IDX(bp);
14184                         u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14185                         int path = BP_PATH(bp);
14186                         int port = BP_PORT(bp);
14187                         int i;
14188                         u32 scratch_offset;
14189                         u32 *host_addr;
14190
14191                         /* first write capability to shmem2 */
14192                         if (ulp_type == CNIC_ULP_ISCSI)
14193                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14194                         else if (ulp_type == CNIC_ULP_FCOE)
14195                                 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14196                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14197
14198                         if ((ulp_type != CNIC_ULP_FCOE) ||
14199                             (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
14200                             (!(bp->flags &  BC_SUPPORTS_FCOE_FEATURES)))
14201                                 break;
14202
14203                         /* if reached here - should write fcoe capabilities */
14204                         scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
14205                         if (!scratch_offset)
14206                                 break;
14207                         scratch_offset += offsetof(struct glob_ncsi_oem_data,
14208                                                    fcoe_features[path][port]);
14209                         host_addr = (u32 *) &(ctl->data.register_data.
14210                                               fcoe_features);
14211                         for (i = 0; i < sizeof(struct fcoe_capabilities);
14212                              i += 4)
14213                                 REG_WR(bp, scratch_offset + i,
14214                                        *(host_addr + i/4));
14215                 }
14216                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14217                 break;
14218         }
14219
14220         case DRV_CTL_ULP_UNREGISTER_CMD: {
14221                 int ulp_type = ctl->data.ulp_type;
14222
14223                 if (CHIP_IS_E3(bp)) {
14224                         int idx = BP_FW_MB_IDX(bp);
14225                         u32 cap;
14226
14227                         cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
14228                         if (ulp_type == CNIC_ULP_ISCSI)
14229                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
14230                         else if (ulp_type == CNIC_ULP_FCOE)
14231                                 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
14232                         SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
14233                 }
14234                 bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14235                 break;
14236         }
14237
14238         default:
14239                 BNX2X_ERR("unknown command %x\n", ctl->cmd);
14240                 rc = -EINVAL;
14241         }
14242
14243         return rc;
14244 }
14245
14246 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
14247 {
14248         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14249
14250         if (bp->flags & USING_MSIX_FLAG) {
14251                 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
14252                 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
14253                 cp->irq_arr[0].vector = bp->msix_table[1].vector;
14254         } else {
14255                 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
14256                 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
14257         }
14258         if (!CHIP_IS_E1x(bp))
14259                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
14260         else
14261                 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
14262
14263         cp->irq_arr[0].status_blk_num =  bnx2x_cnic_fw_sb_id(bp);
14264         cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
14265         cp->irq_arr[1].status_blk = bp->def_status_blk;
14266         cp->irq_arr[1].status_blk_num = DEF_SB_ID;
14267         cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
14268
14269         cp->num_irq = 2;
14270 }
14271
14272 void bnx2x_setup_cnic_info(struct bnx2x *bp)
14273 {
14274         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14275
14276         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14277                              bnx2x_cid_ilt_lines(bp);
14278         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14279         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14280         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14281
14282         DP(NETIF_MSG_IFUP, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14283            BNX2X_1st_NON_L2_ETH_CID(bp), cp->starting_cid, cp->fcoe_init_cid,
14284            cp->iscsi_l2_cid);
14285
14286         if (NO_ISCSI_OOO(bp))
14287                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14288 }
14289
14290 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
14291                                void *data)
14292 {
14293         struct bnx2x *bp = netdev_priv(dev);
14294         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14295         int rc;
14296
14297         DP(NETIF_MSG_IFUP, "Register_cnic called\n");
14298
14299         if (ops == NULL) {
14300                 BNX2X_ERR("NULL ops received\n");
14301                 return -EINVAL;
14302         }
14303
14304         if (!CNIC_SUPPORT(bp)) {
14305                 BNX2X_ERR("Can't register CNIC when not supported\n");
14306                 return -EOPNOTSUPP;
14307         }
14308
14309         if (!CNIC_LOADED(bp)) {
14310                 rc = bnx2x_load_cnic(bp);
14311                 if (rc) {
14312                         BNX2X_ERR("CNIC-related load failed\n");
14313                         return rc;
14314                 }
14315         }
14316
14317         bp->cnic_enabled = true;
14318
14319         bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
14320         if (!bp->cnic_kwq)
14321                 return -ENOMEM;
14322
14323         bp->cnic_kwq_cons = bp->cnic_kwq;
14324         bp->cnic_kwq_prod = bp->cnic_kwq;
14325         bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
14326
14327         bp->cnic_spq_pending = 0;
14328         bp->cnic_kwq_pending = 0;
14329
14330         bp->cnic_data = data;
14331
14332         cp->num_irq = 0;
14333         cp->drv_state |= CNIC_DRV_STATE_REGD;
14334         cp->iro_arr = bp->iro_arr;
14335
14336         bnx2x_setup_cnic_irq_info(bp);
14337
14338         rcu_assign_pointer(bp->cnic_ops, ops);
14339
14340         /* Schedule driver to read CNIC driver versions */
14341         bnx2x_schedule_sp_rtnl(bp, BNX2X_SP_RTNL_GET_DRV_VERSION, 0);
14342
14343         return 0;
14344 }
14345
14346 static int bnx2x_unregister_cnic(struct net_device *dev)
14347 {
14348         struct bnx2x *bp = netdev_priv(dev);
14349         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14350
14351         mutex_lock(&bp->cnic_mutex);
14352         cp->drv_state = 0;
14353         RCU_INIT_POINTER(bp->cnic_ops, NULL);
14354         mutex_unlock(&bp->cnic_mutex);
14355         synchronize_rcu();
14356         bp->cnic_enabled = false;
14357         kfree(bp->cnic_kwq);
14358         bp->cnic_kwq = NULL;
14359
14360         return 0;
14361 }
14362
14363 static struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
14364 {
14365         struct bnx2x *bp = netdev_priv(dev);
14366         struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
14367
14368         /* If both iSCSI and FCoE are disabled - return NULL in
14369          * order to indicate CNIC that it should not try to work
14370          * with this device.
14371          */
14372         if (NO_ISCSI(bp) && NO_FCOE(bp))
14373                 return NULL;
14374
14375         cp->drv_owner = THIS_MODULE;
14376         cp->chip_id = CHIP_ID(bp);
14377         cp->pdev = bp->pdev;
14378         cp->io_base = bp->regview;
14379         cp->io_base2 = bp->doorbells;
14380         cp->max_kwqe_pending = 8;
14381         cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
14382         cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
14383                              bnx2x_cid_ilt_lines(bp);
14384         cp->ctx_tbl_len = CNIC_ILT_LINES;
14385         cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
14386         cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
14387         cp->drv_ctl = bnx2x_drv_ctl;
14388         cp->drv_register_cnic = bnx2x_register_cnic;
14389         cp->drv_unregister_cnic = bnx2x_unregister_cnic;
14390         cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
14391         cp->iscsi_l2_client_id =
14392                 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
14393         cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
14394
14395         if (NO_ISCSI_OOO(bp))
14396                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
14397
14398         if (NO_ISCSI(bp))
14399                 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
14400
14401         if (NO_FCOE(bp))
14402                 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
14403
14404         BNX2X_DEV_INFO(
14405                 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
14406            cp->ctx_blk_size,
14407            cp->ctx_tbl_offset,
14408            cp->ctx_tbl_len,
14409            cp->starting_cid);
14410         return cp;
14411 }
14412
14413 static u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
14414 {
14415         struct bnx2x *bp = fp->bp;
14416         u32 offset = BAR_USTRORM_INTMEM;
14417
14418         if (IS_VF(bp))
14419                 return bnx2x_vf_ustorm_prods_offset(bp, fp);
14420         else if (!CHIP_IS_E1x(bp))
14421                 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
14422         else
14423                 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
14424
14425         return offset;
14426 }
14427
14428 /* called only on E1H or E2.
14429  * When pretending to be PF, the pretend value is the function number 0...7
14430  * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
14431  * combination
14432  */
14433 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
14434 {
14435         u32 pretend_reg;
14436
14437         if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
14438                 return -1;
14439
14440         /* get my own pretend register */
14441         pretend_reg = bnx2x_get_pretend_reg(bp);
14442         REG_WR(bp, pretend_reg, pretend_func_val);
14443         REG_RD(bp, pretend_reg);
14444         return 0;
14445 }
14446
14447 static void bnx2x_ptp_task(struct work_struct *work)
14448 {
14449         struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
14450         int port = BP_PORT(bp);
14451         u32 val_seq;
14452         u64 timestamp, ns;
14453         struct skb_shared_hwtstamps shhwtstamps;
14454
14455         /* Read Tx timestamp registers */
14456         val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14457                          NIG_REG_P0_TLLH_PTP_BUF_SEQID);
14458         if (val_seq & 0x10000) {
14459                 /* There is a valid timestamp value */
14460                 timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
14461                                    NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
14462                 timestamp <<= 32;
14463                 timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
14464                                     NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
14465                 /* Reset timestamp register to allow new timestamp */
14466                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14467                        NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14468                 ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14469
14470                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
14471                 shhwtstamps.hwtstamp = ns_to_ktime(ns);
14472                 skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
14473                 dev_kfree_skb_any(bp->ptp_tx_skb);
14474                 bp->ptp_tx_skb = NULL;
14475
14476                 DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
14477                    timestamp, ns);
14478         } else {
14479                 DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
14480                 /* Reschedule to keep checking for a valid timestamp value */
14481                 schedule_work(&bp->ptp_task);
14482         }
14483 }
14484
14485 void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
14486 {
14487         int port = BP_PORT(bp);
14488         u64 timestamp, ns;
14489
14490         timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
14491                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
14492         timestamp <<= 32;
14493         timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
14494                             NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
14495
14496         /* Reset timestamp register to allow new timestamp */
14497         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14498                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14499
14500         ns = timecounter_cyc2time(&bp->timecounter, timestamp);
14501
14502         skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
14503
14504         DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
14505            timestamp, ns);
14506 }
14507
14508 /* Read the PHC */
14509 static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
14510 {
14511         struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
14512         int port = BP_PORT(bp);
14513         u32 wb_data[2];
14514         u64 phc_cycles;
14515
14516         REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
14517                     NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
14518         phc_cycles = wb_data[1];
14519         phc_cycles = (phc_cycles << 32) + wb_data[0];
14520
14521         DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
14522
14523         return phc_cycles;
14524 }
14525
14526 static void bnx2x_init_cyclecounter(struct bnx2x *bp)
14527 {
14528         memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
14529         bp->cyclecounter.read = bnx2x_cyclecounter_read;
14530         bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
14531         bp->cyclecounter.shift = 1;
14532         bp->cyclecounter.mult = 1;
14533 }
14534
14535 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
14536 {
14537         struct bnx2x_func_state_params func_params = {NULL};
14538         struct bnx2x_func_set_timesync_params *set_timesync_params =
14539                 &func_params.params.set_timesync;
14540
14541         /* Prepare parameters for function state transitions */
14542         __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
14543         __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
14544
14545         func_params.f_obj = &bp->func_obj;
14546         func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
14547
14548         /* Function parameters */
14549         set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
14550         set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
14551
14552         return bnx2x_func_state_change(bp, &func_params);
14553 }
14554
14555 int bnx2x_enable_ptp_packets(struct bnx2x *bp)
14556 {
14557         struct bnx2x_queue_state_params q_params;
14558         int rc, i;
14559
14560         /* send queue update ramrod to enable PTP packets */
14561         memset(&q_params, 0, sizeof(q_params));
14562         __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
14563         q_params.cmd = BNX2X_Q_CMD_UPDATE;
14564         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
14565                   &q_params.params.update.update_flags);
14566         __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
14567                   &q_params.params.update.update_flags);
14568
14569         /* send the ramrod on all the queues of the PF */
14570         for_each_eth_queue(bp, i) {
14571                 struct bnx2x_fastpath *fp = &bp->fp[i];
14572
14573                 /* Set the appropriate Queue object */
14574                 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
14575
14576                 /* Update the Queue state */
14577                 rc = bnx2x_queue_state_change(bp, &q_params);
14578                 if (rc) {
14579                         BNX2X_ERR("Failed to enable PTP packets\n");
14580                         return rc;
14581                 }
14582         }
14583
14584         return 0;
14585 }
14586
14587 int bnx2x_configure_ptp_filters(struct bnx2x *bp)
14588 {
14589         int port = BP_PORT(bp);
14590         int rc;
14591
14592         if (!bp->hwtstamp_ioctl_called)
14593                 return 0;
14594
14595         switch (bp->tx_type) {
14596         case HWTSTAMP_TX_ON:
14597                 bp->flags |= TX_TIMESTAMPING_EN;
14598                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14599                        NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
14600                 REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14601                        NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
14602                 break;
14603         case HWTSTAMP_TX_ONESTEP_SYNC:
14604                 BNX2X_ERR("One-step timestamping is not supported\n");
14605                 return -ERANGE;
14606         }
14607
14608         switch (bp->rx_filter) {
14609         case HWTSTAMP_FILTER_NONE:
14610                 break;
14611         case HWTSTAMP_FILTER_ALL:
14612         case HWTSTAMP_FILTER_SOME:
14613                 bp->rx_filter = HWTSTAMP_FILTER_NONE;
14614                 break;
14615         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
14616         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
14617         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
14618                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
14619                 /* Initialize PTP detection for UDP/IPv4 events */
14620                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14621                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
14622                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14623                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
14624                 break;
14625         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
14626         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
14627         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
14628                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
14629                 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
14630                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14631                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
14632                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14633                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
14634                 break;
14635         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
14636         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
14637         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
14638                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
14639                 /* Initialize PTP detection L2 events */
14640                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14641                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
14642                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14643                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
14644
14645                 break;
14646         case HWTSTAMP_FILTER_PTP_V2_EVENT:
14647         case HWTSTAMP_FILTER_PTP_V2_SYNC:
14648         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
14649                 bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
14650                 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
14651                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14652                        NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
14653                 REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14654                        NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
14655                 break;
14656         }
14657
14658         /* Indicate to FW that this PF expects recorded PTP packets */
14659         rc = bnx2x_enable_ptp_packets(bp);
14660         if (rc)
14661                 return rc;
14662
14663         /* Enable sending PTP packets to host */
14664         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14665                NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
14666
14667         return 0;
14668 }
14669
14670 static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
14671 {
14672         struct hwtstamp_config config;
14673         int rc;
14674
14675         DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
14676
14677         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
14678                 return -EFAULT;
14679
14680         DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
14681            config.tx_type, config.rx_filter);
14682
14683         if (config.flags) {
14684                 BNX2X_ERR("config.flags is reserved for future use\n");
14685                 return -EINVAL;
14686         }
14687
14688         bp->hwtstamp_ioctl_called = 1;
14689         bp->tx_type = config.tx_type;
14690         bp->rx_filter = config.rx_filter;
14691
14692         rc = bnx2x_configure_ptp_filters(bp);
14693         if (rc)
14694                 return rc;
14695
14696         config.rx_filter = bp->rx_filter;
14697
14698         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
14699                 -EFAULT : 0;
14700 }
14701
14702 /* Configrues HW for PTP */
14703 static int bnx2x_configure_ptp(struct bnx2x *bp)
14704 {
14705         int rc, port = BP_PORT(bp);
14706         u32 wb_data[2];
14707
14708         /* Reset PTP event detection rules - will be configured in the IOCTL */
14709         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
14710                NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
14711         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
14712                NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
14713         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
14714                NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
14715         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
14716                NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
14717
14718         /* Disable PTP packets to host - will be configured in the IOCTL*/
14719         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
14720                NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
14721
14722         /* Enable the PTP feature */
14723         REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
14724                NIG_REG_P0_PTP_EN, 0x3F);
14725
14726         /* Enable the free-running counter */
14727         wb_data[0] = 0;
14728         wb_data[1] = 0;
14729         REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
14730
14731         /* Reset drift register (offset register is not reset) */
14732         rc = bnx2x_send_reset_timesync_ramrod(bp);
14733         if (rc) {
14734                 BNX2X_ERR("Failed to reset PHC drift register\n");
14735                 return -EFAULT;
14736         }
14737
14738         /* Reset possibly old timestamps */
14739         REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
14740                NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
14741         REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
14742                NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
14743
14744         return 0;
14745 }
14746
14747 /* Called during load, to initialize PTP-related stuff */
14748 void bnx2x_init_ptp(struct bnx2x *bp)
14749 {
14750         int rc;
14751
14752         /* Configure PTP in HW */
14753         rc = bnx2x_configure_ptp(bp);
14754         if (rc) {
14755                 BNX2X_ERR("Stopping PTP initialization\n");
14756                 return;
14757         }
14758
14759         /* Init work queue for Tx timestamping */
14760         INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
14761
14762         /* Init cyclecounter and timecounter. This is done only in the first
14763          * load. If done in every load, PTP application will fail when doing
14764          * unload / load (e.g. MTU change) while it is running.
14765          */
14766         if (!bp->timecounter_init_done) {
14767                 bnx2x_init_cyclecounter(bp);
14768                 timecounter_init(&bp->timecounter, &bp->cyclecounter,
14769                                  ktime_to_ns(ktime_get_real()));
14770                 bp->timecounter_init_done = 1;
14771         }
14772
14773         DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
14774 }