drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2016 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 164
  73
  74 enum board_idx {
  75         BCM57301,
  76         BCM57302,
  77         BCM57304,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57404_NPAR,
  82         BCM57314,
  83         BCM57304_VF,
  84         BCM57404_VF,
  85 };
  86
  87 /* indexed by enum above */
  88 static const struct {
  89         char *name;
  90 } board_info[] = {
  91         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  92         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
  93         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  94         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
  95         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  96         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
  97         { "Broadcom BCM57404 NetXtreme-E Ethernet Partition" },
  98         { "Broadcom BCM57314 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  99         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
 100         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
 101 };
 102
 103 static const struct pci_device_id bnxt_pci_tbl[] = {
 104         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 105         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 106         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 107         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 108         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 109         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 110         { PCI_VDEVICE(BROADCOM, 0x16d4), .driver_data = BCM57404_NPAR },
 111         { PCI_VDEVICE(BROADCOM, 0x16df), .driver_data = BCM57314 },
 112 #ifdef CONFIG_BNXT_SRIOV
 113         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 114         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 115 #endif
 116         { 0 }
 117 };
 118
 119 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 120
 121 static const u16 bnxt_vf_req_snif[] = {
 122         HWRM_FUNC_CFG,
 123         HWRM_PORT_PHY_QCFG,
 124         HWRM_CFA_L2_FILTER_ALLOC,
 125 };
 126
 127 static const u16 bnxt_async_events_arr[] = {
 128         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE,
 129         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD,
 130         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED,
 131         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE,
 132         HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE,
 133 };
 134
 135 static bool bnxt_vf_pciid(enum board_idx idx)
 136 {
 137         return (idx == BCM57304_VF || idx == BCM57404_VF);
 138 }
 139
 140 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 141 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 142 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 143
 144 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 145                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 146
 147 #define BNXT_CP_DB(db, raw_cons)                                        \
 148                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 149
 150 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 151                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 152
 153 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 154 {
 155         /* Tell compiler to fetch tx indices from memory. */
 156         barrier();
 157
 158         return bp->tx_ring_size -
 159                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 160 }
 161
 162 static const u16 bnxt_lhint_arr[] = {
 163         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 164         TX_BD_FLAGS_LHINT_512_TO_1023,
 165         TX_BD_FLAGS_LHINT_1024_TO_2047,
 166         TX_BD_FLAGS_LHINT_1024_TO_2047,
 167         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 168         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 169         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 170         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 171         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 172         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 173         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 174         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 175         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 176         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 177         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 178         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 179         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 180         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 181         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 182 };
 183
 184 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 185 {
 186         struct bnxt *bp = netdev_priv(dev);
 187         struct tx_bd *txbd;
 188         struct tx_bd_ext *txbd1;
 189         struct netdev_queue *txq;
 190         int i;
 191         dma_addr_t mapping;
 192         unsigned int length, pad = 0;
 193         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 194         u16 prod, last_frag;
 195         struct pci_dev *pdev = bp->pdev;
 196         struct bnxt_tx_ring_info *txr;
 197         struct bnxt_sw_tx_bd *tx_buf;
 198
 199         i = skb_get_queue_mapping(skb);
 200         if (unlikely(i >= bp->tx_nr_rings)) {
 201                 dev_kfree_skb_any(skb);
 202                 return NETDEV_TX_OK;
 203         }
 204
 205         txr = &bp->tx_ring[i];
 206         txq = netdev_get_tx_queue(dev, i);
 207         prod = txr->tx_prod;
 208
 209         free_size = bnxt_tx_avail(bp, txr);
 210         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 211                 netif_tx_stop_queue(txq);
 212                 return NETDEV_TX_BUSY;
 213         }
 214
 215         length = skb->len;
 216         len = skb_headlen(skb);
 217         last_frag = skb_shinfo(skb)->nr_frags;
 218
 219         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 220
 221         txbd->tx_bd_opaque = prod;
 222
 223         tx_buf = &txr->tx_buf_ring[prod];
 224         tx_buf->skb = skb;
 225         tx_buf->nr_frags = last_frag;
 226
 227         vlan_tag_flags = 0;
 228         cfa_action = 0;
 229         if (skb_vlan_tag_present(skb)) {
 230                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 231                                  skb_vlan_tag_get(skb);
 232                 /* Currently supports 8021Q, 8021AD vlan offloads
 233                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 234                  */
 235                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 236                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 237         }
 238
 239         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 240                 struct tx_push_buffer *tx_push_buf = txr->tx_push;
 241                 struct tx_push_bd *tx_push = &tx_push_buf->push_bd;
 242                 struct tx_bd_ext *tx_push1 = &tx_push->txbd2;
 243                 void *pdata = tx_push_buf->data;
 244                 u64 *end;
 245                 int j, push_len;
 246
 247                 /* Set COAL_NOW to be ready quickly for the next push */
 248                 tx_push->tx_bd_len_flags_type =
 249                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 250                                         TX_BD_TYPE_LONG_TX_BD |
 251                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 252                                         TX_BD_FLAGS_COAL_NOW |
 253                                         TX_BD_FLAGS_PACKET_END |
 254                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 255
 256                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 257                         tx_push1->tx_bd_hsize_lflags =
 258                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 259                 else
 260                         tx_push1->tx_bd_hsize_lflags = 0;
 261
 262                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 263                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 264
 265                 end = pdata + length;
 266                 end = PTR_ALIGN(end, 8) - 1;
 267                 *end = 0;
 268
 269                 skb_copy_from_linear_data(skb, pdata, len);
 270                 pdata += len;
 271                 for (j = 0; j < last_frag; j++) {
 272                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 273                         void *fptr;
 274
 275                         fptr = skb_frag_address_safe(frag);
 276                         if (!fptr)
 277                                 goto normal_tx;
 278
 279                         memcpy(pdata, fptr, skb_frag_size(frag));
 280                         pdata += skb_frag_size(frag);
 281                 }
 282
 283                 txbd->tx_bd_len_flags_type = tx_push->tx_bd_len_flags_type;
 284                 txbd->tx_bd_haddr = txr->data_mapping;
 285                 prod = NEXT_TX(prod);
 286                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 287                 memcpy(txbd, tx_push1, sizeof(*txbd));
 288                 prod = NEXT_TX(prod);
 289                 tx_push->doorbell =
 290                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 291                 txr->tx_prod = prod;
 292
 293                 tx_buf->is_push = 1;
 294                 netdev_tx_sent_queue(txq, skb->len);
 295                 wmb();  /* Sync is_push and byte queue before pushing data */
 296
 297                 push_len = (length + sizeof(*tx_push) + 7) / 8;
 298                 if (push_len > 16) {
 299                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf, 16);
 300                         __iowrite64_copy(txr->tx_doorbell + 4, tx_push_buf + 1,
 301                                          push_len - 16);
 302                 } else {
 303                         __iowrite64_copy(txr->tx_doorbell, tx_push_buf,
 304                                          push_len);
 305                 }
 306
 307                 goto tx_done;
 308         }
 309
 310 normal_tx:
 311         if (length < BNXT_MIN_PKT_SIZE) {
 312                 pad = BNXT_MIN_PKT_SIZE - length;
 313                 if (skb_pad(skb, pad)) {
 314                         /* SKB already freed. */
 315                         tx_buf->skb = NULL;
 316                         return NETDEV_TX_OK;
 317                 }
 318                 length = BNXT_MIN_PKT_SIZE;
 319         }
 320
 321         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 322
 323         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 324                 dev_kfree_skb_any(skb);
 325                 tx_buf->skb = NULL;
 326                 return NETDEV_TX_OK;
 327         }
 328
 329         dma_unmap_addr_set(tx_buf, mapping, mapping);
 330         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 331                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 332
 333         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 334
 335         prod = NEXT_TX(prod);
 336         txbd1 = (struct tx_bd_ext *)
 337                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 338
 339         txbd1->tx_bd_hsize_lflags = 0;
 340         if (skb_is_gso(skb)) {
 341                 u32 hdr_len;
 342
 343                 if (skb->encapsulation)
 344                         hdr_len = skb_inner_network_offset(skb) +
 345                                 skb_inner_network_header_len(skb) +
 346                                 inner_tcp_hdrlen(skb);
 347                 else
 348                         hdr_len = skb_transport_offset(skb) +
 349                                 tcp_hdrlen(skb);
 350
 351                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 352                                         TX_BD_FLAGS_T_IPID |
 353                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 354                 length = skb_shinfo(skb)->gso_size;
 355                 txbd1->tx_bd_mss = cpu_to_le32(length);
 356                 length += hdr_len;
 357         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 358                 txbd1->tx_bd_hsize_lflags =
 359                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 360                 txbd1->tx_bd_mss = 0;
 361         }
 362
 363         length >>= 9;
 364         flags |= bnxt_lhint_arr[length];
 365         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 366
 367         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 368         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 369         for (i = 0; i < last_frag; i++) {
 370                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 371
 372                 prod = NEXT_TX(prod);
 373                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 374
 375                 len = skb_frag_size(frag);
 376                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 377                                            DMA_TO_DEVICE);
 378
 379                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 380                         goto tx_dma_error;
 381
 382                 tx_buf = &txr->tx_buf_ring[prod];
 383                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 384
 385                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 386
 387                 flags = len << TX_BD_LEN_SHIFT;
 388                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 389         }
 390
 391         flags &= ~TX_BD_LEN;
 392         txbd->tx_bd_len_flags_type =
 393                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 394                             TX_BD_FLAGS_PACKET_END);
 395
 396         netdev_tx_sent_queue(txq, skb->len);
 397
 398         /* Sync BD data before updating doorbell */
 399         wmb();
 400
 401         prod = NEXT_TX(prod);
 402         txr->tx_prod = prod;
 403
 404         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 405         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 406
 407 tx_done:
 408
 409         mmiowb();
 410
 411         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 412                 netif_tx_stop_queue(txq);
 413
 414                 /* netif_tx_stop_queue() must be done before checking
 415                  * tx index in bnxt_tx_avail() below, because in
 416                  * bnxt_tx_int(), we update tx index before checking for
 417                  * netif_tx_queue_stopped().
 418                  */
 419                 smp_mb();
 420                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 421                         netif_tx_wake_queue(txq);
 422         }
 423         return NETDEV_TX_OK;
 424
 425 tx_dma_error:
 426         last_frag = i;
 427
 428         /* start back at beginning and unmap skb */
 429         prod = txr->tx_prod;
 430         tx_buf = &txr->tx_buf_ring[prod];
 431         tx_buf->skb = NULL;
 432         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 433                          skb_headlen(skb), PCI_DMA_TODEVICE);
 434         prod = NEXT_TX(prod);
 435
 436         /* unmap remaining mapped pages */
 437         for (i = 0; i < last_frag; i++) {
 438                 prod = NEXT_TX(prod);
 439                 tx_buf = &txr->tx_buf_ring[prod];
 440                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 441                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 442                                PCI_DMA_TODEVICE);
 443         }
 444
 445         dev_kfree_skb_any(skb);
 446         return NETDEV_TX_OK;
 447 }
 448
 449 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 450 {
 451         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 452         int index = txr - &bp->tx_ring[0];
 453         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 454         u16 cons = txr->tx_cons;
 455         struct pci_dev *pdev = bp->pdev;
 456         int i;
 457         unsigned int tx_bytes = 0;
 458
 459         for (i = 0; i < nr_pkts; i++) {
 460                 struct bnxt_sw_tx_bd *tx_buf;
 461                 struct sk_buff *skb;
 462                 int j, last;
 463
 464                 tx_buf = &txr->tx_buf_ring[cons];
 465                 cons = NEXT_TX(cons);
 466                 skb = tx_buf->skb;
 467                 tx_buf->skb = NULL;
 468
 469                 if (tx_buf->is_push) {
 470                         tx_buf->is_push = 0;
 471                         goto next_tx_int;
 472                 }
 473
 474                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 475                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 476                 last = tx_buf->nr_frags;
 477
 478                 for (j = 0; j < last; j++) {
 479                         cons = NEXT_TX(cons);
 480                         tx_buf = &txr->tx_buf_ring[cons];
 481                         dma_unmap_page(
 482                                 &pdev->dev,
 483                                 dma_unmap_addr(tx_buf, mapping),
 484                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 485                                 PCI_DMA_TODEVICE);
 486                 }
 487
 488 next_tx_int:
 489                 cons = NEXT_TX(cons);
 490
 491                 tx_bytes += skb->len;
 492                 dev_kfree_skb_any(skb);
 493         }
 494
 495         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 496         txr->tx_cons = cons;
 497
 498         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 499          * before checking for netif_tx_queue_stopped().  Without the
 500          * memory barrier, there is a small possibility that bnxt_start_xmit()
 501          * will miss it and cause the queue to be stopped forever.
 502          */
 503         smp_mb();
 504
 505         if (unlikely(netif_tx_queue_stopped(txq)) &&
 506             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 507                 __netif_tx_lock(txq, smp_processor_id());
 508                 if (netif_tx_queue_stopped(txq) &&
 509                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 510                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 511                         netif_tx_wake_queue(txq);
 512                 __netif_tx_unlock(txq);
 513         }
 514 }
 515
 516 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 517                                        gfp_t gfp)
 518 {
 519         u8 *data;
 520         struct pci_dev *pdev = bp->pdev;
 521
 522         data = kmalloc(bp->rx_buf_size, gfp);
 523         if (!data)
 524                 return NULL;
 525
 526         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 527                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 528
 529         if (dma_mapping_error(&pdev->dev, *mapping)) {
 530                 kfree(data);
 531                 data = NULL;
 532         }
 533         return data;
 534 }
 535
 536 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 537                                      struct bnxt_rx_ring_info *rxr,
 538                                      u16 prod, gfp_t gfp)
 539 {
 540         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 541         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 542         u8 *data;
 543         dma_addr_t mapping;
 544
 545         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 546         if (!data)
 547                 return -ENOMEM;
 548
 549         rx_buf->data = data;
 550         dma_unmap_addr_set(rx_buf, mapping, mapping);
 551
 552         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 553
 554         return 0;
 555 }
 556
 557 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 558                                u8 *data)
 559 {
 560         u16 prod = rxr->rx_prod;
 561         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 562         struct rx_bd *cons_bd, *prod_bd;
 563
 564         prod_rx_buf = &rxr->rx_buf_ring[prod];
 565         cons_rx_buf = &rxr->rx_buf_ring[cons];
 566
 567         prod_rx_buf->data = data;
 568
 569         dma_unmap_addr_set(prod_rx_buf, mapping,
 570                            dma_unmap_addr(cons_rx_buf, mapping));
 571
 572         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 573         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 574
 575         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 576 }
 577
 578 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 579 {
 580         u16 next, max = rxr->rx_agg_bmap_size;
 581
 582         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 583         if (next >= max)
 584                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 585         return next;
 586 }
 587
 588 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 589                                      struct bnxt_rx_ring_info *rxr,
 590                                      u16 prod, gfp_t gfp)
 591 {
 592         struct rx_bd *rxbd =
 593                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 594         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 595         struct pci_dev *pdev = bp->pdev;
 596         struct page *page;
 597         dma_addr_t mapping;
 598         u16 sw_prod = rxr->rx_sw_agg_prod;
 599         unsigned int offset = 0;
 600
 601         if (PAGE_SIZE > BNXT_RX_PAGE_SIZE) {
 602                 page = rxr->rx_page;
 603                 if (!page) {
 604                         page = alloc_page(gfp);
 605                         if (!page)
 606                                 return -ENOMEM;
 607                         rxr->rx_page = page;
 608                         rxr->rx_page_offset = 0;
 609                 }
 610                 offset = rxr->rx_page_offset;
 611                 rxr->rx_page_offset += BNXT_RX_PAGE_SIZE;
 612                 if (rxr->rx_page_offset == PAGE_SIZE)
 613                         rxr->rx_page = NULL;
 614                 else
 615                         get_page(page);
 616         } else {
 617                 page = alloc_page(gfp);
 618                 if (!page)
 619                         return -ENOMEM;
 620         }
 621
 622         mapping = dma_map_page(&pdev->dev, page, offset, BNXT_RX_PAGE_SIZE,
 623                                PCI_DMA_FROMDEVICE);
 624         if (dma_mapping_error(&pdev->dev, mapping)) {
 625                 __free_page(page);
 626                 return -EIO;
 627         }
 628
 629         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 630                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 631
 632         __set_bit(sw_prod, rxr->rx_agg_bmap);
 633         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 634         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 635
 636         rx_agg_buf->page = page;
 637         rx_agg_buf->offset = offset;
 638         rx_agg_buf->mapping = mapping;
 639         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 640         rxbd->rx_bd_opaque = sw_prod;
 641         return 0;
 642 }
 643
 644 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 645                                    u32 agg_bufs)
 646 {
 647         struct bnxt *bp = bnapi->bp;
 648         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 649         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 650         u16 prod = rxr->rx_agg_prod;
 651         u16 sw_prod = rxr->rx_sw_agg_prod;
 652         u32 i;
 653
 654         for (i = 0; i < agg_bufs; i++) {
 655                 u16 cons;
 656                 struct rx_agg_cmp *agg;
 657                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 658                 struct rx_bd *prod_bd;
 659                 struct page *page;
 660
 661                 agg = (struct rx_agg_cmp *)
 662                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 663                 cons = agg->rx_agg_cmp_opaque;
 664                 __clear_bit(cons, rxr->rx_agg_bmap);
 665
 666                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 667                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 668
 669                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 670                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 671                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 672
 673                 /* It is possible for sw_prod to be equal to cons, so
 674                  * set cons_rx_buf->page to NULL first.
 675                  */
 676                 page = cons_rx_buf->page;
 677                 cons_rx_buf->page = NULL;
 678                 prod_rx_buf->page = page;
 679                 prod_rx_buf->offset = cons_rx_buf->offset;
 680
 681                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 682
 683                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 684
 685                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 686                 prod_bd->rx_bd_opaque = sw_prod;
 687
 688                 prod = NEXT_RX_AGG(prod);
 689                 sw_prod = NEXT_RX_AGG(sw_prod);
 690                 cp_cons = NEXT_CMP(cp_cons);
 691         }
 692         rxr->rx_agg_prod = prod;
 693         rxr->rx_sw_agg_prod = sw_prod;
 694 }
 695
 696 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 697                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 698                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 699                                    unsigned int len)
 700 {
 701         int err;
 702         struct sk_buff *skb;
 703
 704         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 705         if (unlikely(err)) {
 706                 bnxt_reuse_rx_data(rxr, cons, data);
 707                 return NULL;
 708         }
 709
 710         skb = build_skb(data, 0);
 711         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 712                          PCI_DMA_FROMDEVICE);
 713         if (!skb) {
 714                 kfree(data);
 715                 return NULL;
 716         }
 717
 718         skb_reserve(skb, BNXT_RX_OFFSET);
 719         skb_put(skb, len);
 720         return skb;
 721 }
 722
 723 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 724                                      struct sk_buff *skb, u16 cp_cons,
 725                                      u32 agg_bufs)
 726 {
 727         struct pci_dev *pdev = bp->pdev;
 728         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 729         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 730         u16 prod = rxr->rx_agg_prod;
 731         u32 i;
 732
 733         for (i = 0; i < agg_bufs; i++) {
 734                 u16 cons, frag_len;
 735                 struct rx_agg_cmp *agg;
 736                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 737                 struct page *page;
 738                 dma_addr_t mapping;
 739
 740                 agg = (struct rx_agg_cmp *)
 741                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 742                 cons = agg->rx_agg_cmp_opaque;
 743                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 744                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 745
 746                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 747                 skb_fill_page_desc(skb, i, cons_rx_buf->page,
 748                                    cons_rx_buf->offset, frag_len);
 749                 __clear_bit(cons, rxr->rx_agg_bmap);
 750
 751                 /* It is possible for bnxt_alloc_rx_page() to allocate
 752                  * a sw_prod index that equals the cons index, so we
 753                  * need to clear the cons entry now.
 754                  */
 755                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 756                 page = cons_rx_buf->page;
 757                 cons_rx_buf->page = NULL;
 758
 759                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 760                         struct skb_shared_info *shinfo;
 761                         unsigned int nr_frags;
 762
 763                         shinfo = skb_shinfo(skb);
 764                         nr_frags = --shinfo->nr_frags;
 765                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 766
 767                         dev_kfree_skb(skb);
 768
 769                         cons_rx_buf->page = page;
 770
 771                         /* Update prod since possibly some pages have been
 772                          * allocated already.
 773                          */
 774                         rxr->rx_agg_prod = prod;
 775                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 776                         return NULL;
 777                 }
 778
 779                 dma_unmap_page(&pdev->dev, mapping, BNXT_RX_PAGE_SIZE,
 780                                PCI_DMA_FROMDEVICE);
 781
 782                 skb->data_len += frag_len;
 783                 skb->len += frag_len;
 784                 skb->truesize += PAGE_SIZE;
 785
 786                 prod = NEXT_RX_AGG(prod);
 787                 cp_cons = NEXT_CMP(cp_cons);
 788         }
 789         rxr->rx_agg_prod = prod;
 790         return skb;
 791 }
 792
 793 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 794                                u8 agg_bufs, u32 *raw_cons)
 795 {
 796         u16 last;
 797         struct rx_agg_cmp *agg;
 798
 799         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 800         last = RING_CMP(*raw_cons);
 801         agg = (struct rx_agg_cmp *)
 802                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 803         return RX_AGG_CMP_VALID(agg, *raw_cons);
 804 }
 805
 806 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 807                                             unsigned int len,
 808                                             dma_addr_t mapping)
 809 {
 810         struct bnxt *bp = bnapi->bp;
 811         struct pci_dev *pdev = bp->pdev;
 812         struct sk_buff *skb;
 813
 814         skb = napi_alloc_skb(&bnapi->napi, len);
 815         if (!skb)
 816                 return NULL;
 817
 818         dma_sync_single_for_cpu(&pdev->dev, mapping,
 819                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 820
 821         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 822
 823         dma_sync_single_for_device(&pdev->dev, mapping,
 824                                    bp->rx_copy_thresh,
 825                                    PCI_DMA_FROMDEVICE);
 826
 827         skb_put(skb, len);
 828         return skb;
 829 }
 830
 831 static int bnxt_discard_rx(struct bnxt *bp, struct bnxt_napi *bnapi,
 832                            u32 *raw_cons, void *cmp)
 833 {
 834         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 835         struct rx_cmp *rxcmp = cmp;
 836         u32 tmp_raw_cons = *raw_cons;
 837         u8 cmp_type, agg_bufs = 0;
 838
 839         cmp_type = RX_CMP_TYPE(rxcmp);
 840
 841         if (cmp_type == CMP_TYPE_RX_L2_CMP) {
 842                 agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) &
 843                             RX_CMP_AGG_BUFS) >>
 844                            RX_CMP_AGG_BUFS_SHIFT;
 845         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
 846                 struct rx_tpa_end_cmp *tpa_end = cmp;
 847
 848                 agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 849                             RX_TPA_END_CMP_AGG_BUFS) >>
 850                            RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 851         }
 852
 853         if (agg_bufs) {
 854                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
 855                         return -EBUSY;
 856         }
 857         *raw_cons = tmp_raw_cons;
 858         return 0;
 859 }
 860
 861 static void bnxt_sched_reset(struct bnxt *bp, struct bnxt_rx_ring_info *rxr)
 862 {
 863         if (!rxr->bnapi->in_reset) {
 864                 rxr->bnapi->in_reset = true;
 865                 set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
 866                 schedule_work(&bp->sp_task);
 867         }
 868         rxr->rx_next_cons = 0xffff;
 869 }
 870
 871 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 872                            struct rx_tpa_start_cmp *tpa_start,
 873                            struct rx_tpa_start_cmp_ext *tpa_start1)
 874 {
 875         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 876         u16 cons, prod;
 877         struct bnxt_tpa_info *tpa_info;
 878         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 879         struct rx_bd *prod_bd;
 880         dma_addr_t mapping;
 881
 882         cons = tpa_start->rx_tpa_start_cmp_opaque;
 883         prod = rxr->rx_prod;
 884         cons_rx_buf = &rxr->rx_buf_ring[cons];
 885         prod_rx_buf = &rxr->rx_buf_ring[prod];
 886         tpa_info = &rxr->rx_tpa[agg_id];
 887
 888         if (unlikely(cons != rxr->rx_next_cons)) {
 889                 bnxt_sched_reset(bp, rxr);
 890                 return;
 891         }
 892
 893         prod_rx_buf->data = tpa_info->data;
 894
 895         mapping = tpa_info->mapping;
 896         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 897
 898         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 899
 900         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 901
 902         tpa_info->data = cons_rx_buf->data;
 903         cons_rx_buf->data = NULL;
 904         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 905
 906         tpa_info->len =
 907                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 908                                 RX_TPA_START_CMP_LEN_SHIFT;
 909         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 910                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 911
 912                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 913                 tpa_info->gso_type = SKB_GSO_TCPV4;
 914                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 915                 if (hash_type == 3)
 916                         tpa_info->gso_type = SKB_GSO_TCPV6;
 917                 tpa_info->rss_hash =
 918                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 919         } else {
 920                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 921                 tpa_info->gso_type = 0;
 922                 if (netif_msg_rx_err(bp))
 923                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 924         }
 925         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 926         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 927
 928         rxr->rx_prod = NEXT_RX(prod);
 929         cons = NEXT_RX(cons);
 930         rxr->rx_next_cons = NEXT_RX(cons);
 931         cons_rx_buf = &rxr->rx_buf_ring[cons];
 932
 933         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 934         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 935         cons_rx_buf->data = NULL;
 936 }
 937
 938 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 939                            u16 cp_cons, u32 agg_bufs)
 940 {
 941         if (agg_bufs)
 942                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 943 }
 944
 945 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 946 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 947
 948 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 949                                            struct rx_tpa_end_cmp *tpa_end,
 950                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 951                                            struct sk_buff *skb)
 952 {
 953 #ifdef CONFIG_INET
 954         struct tcphdr *th;
 955         int payload_off, tcp_opt_len = 0;
 956         int len, nw_off;
 957         u16 segs;
 958
 959         segs = TPA_END_TPA_SEGS(tpa_end);
 960         if (segs == 1)
 961                 return skb;
 962
 963         NAPI_GRO_CB(skb)->count = segs;
 964         skb_shinfo(skb)->gso_size =
 965                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 966         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 967         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 968                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 969                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 970         if (TPA_END_GRO_TS(tpa_end))
 971                 tcp_opt_len = 12;
 972
 973         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 974                 struct iphdr *iph;
 975
 976                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 977                          ETH_HLEN;
 978                 skb_set_network_header(skb, nw_off);
 979                 iph = ip_hdr(skb);
 980                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 981                 len = skb->len - skb_transport_offset(skb);
 982                 th = tcp_hdr(skb);
 983                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 984         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 985                 struct ipv6hdr *iph;
 986
 987                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 988                          ETH_HLEN;
 989                 skb_set_network_header(skb, nw_off);
 990                 iph = ipv6_hdr(skb);
 991                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 992                 len = skb->len - skb_transport_offset(skb);
 993                 th = tcp_hdr(skb);
 994                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 995         } else {
 996                 dev_kfree_skb_any(skb);
 997                 return NULL;
 998         }
 999         tcp_gro_complete(skb);
1000
1001         if (nw_off) { /* tunnel */
1002                 struct udphdr *uh = NULL;
1003
1004                 if (skb->protocol == htons(ETH_P_IP)) {
1005                         struct iphdr *iph = (struct iphdr *)skb->data;
1006
1007                         if (iph->protocol == IPPROTO_UDP)
1008                                 uh = (struct udphdr *)(iph + 1);
1009                 } else {
1010                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
1011
1012                         if (iph->nexthdr == IPPROTO_UDP)
1013                                 uh = (struct udphdr *)(iph + 1);
1014                 }
1015                 if (uh) {
1016                         if (uh->check)
1017                                 skb_shinfo(skb)->gso_type |=
1018                                         SKB_GSO_UDP_TUNNEL_CSUM;
1019                         else
1020                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
1021                 }
1022         }
1023 #endif
1024         return skb;
1025 }
1026
1027 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
1028                                            struct bnxt_napi *bnapi,
1029                                            u32 *raw_cons,
1030                                            struct rx_tpa_end_cmp *tpa_end,
1031                                            struct rx_tpa_end_cmp_ext *tpa_end1,
1032                                            bool *agg_event)
1033 {
1034         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1035         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1036         u8 agg_id = TPA_END_AGG_ID(tpa_end);
1037         u8 *data, agg_bufs;
1038         u16 cp_cons = RING_CMP(*raw_cons);
1039         unsigned int len;
1040         struct bnxt_tpa_info *tpa_info;
1041         dma_addr_t mapping;
1042         struct sk_buff *skb;
1043
1044         if (unlikely(bnapi->in_reset)) {
1045                 int rc = bnxt_discard_rx(bp, bnapi, raw_cons, tpa_end);
1046
1047                 if (rc < 0)
1048                         return ERR_PTR(-EBUSY);
1049                 return NULL;
1050         }
1051
1052         tpa_info = &rxr->rx_tpa[agg_id];
1053         data = tpa_info->data;
1054         prefetch(data);
1055         len = tpa_info->len;
1056         mapping = tpa_info->mapping;
1057
1058         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
1059                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
1060
1061         if (agg_bufs) {
1062                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
1063                         return ERR_PTR(-EBUSY);
1064
1065                 *agg_event = true;
1066                 cp_cons = NEXT_CMP(cp_cons);
1067         }
1068
1069         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
1070                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1071                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
1072                             agg_bufs, (int)MAX_SKB_FRAGS);
1073                 return NULL;
1074         }
1075
1076         if (len <= bp->rx_copy_thresh) {
1077                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
1078                 if (!skb) {
1079                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1080                         return NULL;
1081                 }
1082         } else {
1083                 u8 *new_data;
1084                 dma_addr_t new_mapping;
1085
1086                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
1087                 if (!new_data) {
1088                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1089                         return NULL;
1090                 }
1091
1092                 tpa_info->data = new_data;
1093                 tpa_info->mapping = new_mapping;
1094
1095                 skb = build_skb(data, 0);
1096                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
1097                                  PCI_DMA_FROMDEVICE);
1098
1099                 if (!skb) {
1100                         kfree(data);
1101                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1102                         return NULL;
1103                 }
1104                 skb_reserve(skb, BNXT_RX_OFFSET);
1105                 skb_put(skb, len);
1106         }
1107
1108         if (agg_bufs) {
1109                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1110                 if (!skb) {
1111                         /* Page reuse already handled by bnxt_rx_pages(). */
1112                         return NULL;
1113                 }
1114         }
1115         skb->protocol = eth_type_trans(skb, bp->dev);
1116
1117         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1118                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1119
1120         if ((tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) &&
1121             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1122                 u16 vlan_proto = tpa_info->metadata >>
1123                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1124                 u16 vtag = tpa_info->metadata & RX_CMP_FLAGS2_METADATA_VID_MASK;
1125
1126                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1127         }
1128
1129         skb_checksum_none_assert(skb);
1130         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1131                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1132                 skb->csum_level =
1133                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1134         }
1135
1136         if (TPA_END_GRO(tpa_end))
1137                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1138
1139         return skb;
1140 }
1141
1142 /* returns the following:
1143  * 1       - 1 packet successfully received
1144  * 0       - successful TPA_START, packet not completed yet
1145  * -EBUSY  - completion ring does not have all the agg buffers yet
1146  * -ENOMEM - packet aborted due to out of memory
1147  * -EIO    - packet aborted due to hw error indicated in BD
1148  */
1149 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1150                        bool *agg_event)
1151 {
1152         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1153         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1154         struct net_device *dev = bp->dev;
1155         struct rx_cmp *rxcmp;
1156         struct rx_cmp_ext *rxcmp1;
1157         u32 tmp_raw_cons = *raw_cons;
1158         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1159         struct bnxt_sw_rx_bd *rx_buf;
1160         unsigned int len;
1161         u8 *data, agg_bufs, cmp_type;
1162         dma_addr_t dma_addr;
1163         struct sk_buff *skb;
1164         int rc = 0;
1165
1166         rxcmp = (struct rx_cmp *)
1167                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1168
1169         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1170         cp_cons = RING_CMP(tmp_raw_cons);
1171         rxcmp1 = (struct rx_cmp_ext *)
1172                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1173
1174         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1175                 return -EBUSY;
1176
1177         cmp_type = RX_CMP_TYPE(rxcmp);
1178
1179         prod = rxr->rx_prod;
1180
1181         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1182                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1183                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1184
1185                 goto next_rx_no_prod;
1186
1187         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1188                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1189                                    (struct rx_tpa_end_cmp *)rxcmp,
1190                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1191                                    agg_event);
1192
1193                 if (unlikely(IS_ERR(skb)))
1194                         return -EBUSY;
1195
1196                 rc = -ENOMEM;
1197                 if (likely(skb)) {
1198                         skb_record_rx_queue(skb, bnapi->index);
1199                         skb_mark_napi_id(skb, &bnapi->napi);
1200                         if (bnxt_busy_polling(bnapi))
1201                                 netif_receive_skb(skb);
1202                         else
1203                                 napi_gro_receive(&bnapi->napi, skb);
1204                         rc = 1;
1205                 }
1206                 goto next_rx_no_prod;
1207         }
1208
1209         cons = rxcmp->rx_cmp_opaque;
1210         rx_buf = &rxr->rx_buf_ring[cons];
1211         data = rx_buf->data;
1212         if (unlikely(cons != rxr->rx_next_cons)) {
1213                 int rc1 = bnxt_discard_rx(bp, bnapi, raw_cons, rxcmp);
1214
1215                 bnxt_sched_reset(bp, rxr);
1216                 return rc1;
1217         }
1218         prefetch(data);
1219
1220         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1221                                 RX_CMP_AGG_BUFS_SHIFT;
1222
1223         if (agg_bufs) {
1224                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1225                         return -EBUSY;
1226
1227                 cp_cons = NEXT_CMP(cp_cons);
1228                 *agg_event = true;
1229         }
1230
1231         rx_buf->data = NULL;
1232         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1233                 bnxt_reuse_rx_data(rxr, cons, data);
1234                 if (agg_bufs)
1235                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1236
1237                 rc = -EIO;
1238                 goto next_rx;
1239         }
1240
1241         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1242         dma_addr = dma_unmap_addr(rx_buf, mapping);
1243
1244         if (len <= bp->rx_copy_thresh) {
1245                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1246                 bnxt_reuse_rx_data(rxr, cons, data);
1247                 if (!skb) {
1248                         rc = -ENOMEM;
1249                         goto next_rx;
1250                 }
1251         } else {
1252                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1253                 if (!skb) {
1254                         rc = -ENOMEM;
1255                         goto next_rx;
1256                 }
1257         }
1258
1259         if (agg_bufs) {
1260                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1261                 if (!skb) {
1262                         rc = -ENOMEM;
1263                         goto next_rx;
1264                 }
1265         }
1266
1267         if (RX_CMP_HASH_VALID(rxcmp)) {
1268                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1269                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1270
1271                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1272                 if (hash_type != 1 && hash_type != 3)
1273                         type = PKT_HASH_TYPE_L3;
1274                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1275         }
1276
1277         skb->protocol = eth_type_trans(skb, dev);
1278
1279         if ((rxcmp1->rx_cmp_flags2 &
1280              cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) &&
1281             (skb->dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
1282                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1283                 u16 vtag = meta_data & RX_CMP_FLAGS2_METADATA_VID_MASK;
1284                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1285
1286                 __vlan_hwaccel_put_tag(skb, htons(vlan_proto), vtag);
1287         }
1288
1289         skb_checksum_none_assert(skb);
1290         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1291                 if (dev->features & NETIF_F_RXCSUM) {
1292                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1293                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1294                 }
1295         } else {
1296                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1297                         if (dev->features & NETIF_F_RXCSUM)
1298                                 cpr->rx_l4_csum_errors++;
1299                 }
1300         }
1301
1302         skb_record_rx_queue(skb, bnapi->index);
1303         skb_mark_napi_id(skb, &bnapi->napi);
1304         if (bnxt_busy_polling(bnapi))
1305                 netif_receive_skb(skb);
1306         else
1307                 napi_gro_receive(&bnapi->napi, skb);
1308         rc = 1;
1309
1310 next_rx:
1311         rxr->rx_prod = NEXT_RX(prod);
1312         rxr->rx_next_cons = NEXT_RX(cons);
1313
1314 next_rx_no_prod:
1315         *raw_cons = tmp_raw_cons;
1316
1317         return rc;
1318 }
1319
1320 #define BNXT_GET_EVENT_PORT(data)       \
1321         ((data) &                               \
1322          HWRM_ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK)
1323
1324 static int bnxt_async_event_process(struct bnxt *bp,
1325                                     struct hwrm_async_event_cmpl *cmpl)
1326 {
1327         u16 event_id = le16_to_cpu(cmpl->event_id);
1328
1329         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1330         switch (event_id) {
1331         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE: {
1332                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1333                 struct bnxt_link_info *link_info = &bp->link_info;
1334
1335                 if (BNXT_VF(bp))
1336                         goto async_event_process_exit;
1337                 if (data1 & 0x20000) {
1338                         u16 fw_speed = link_info->force_link_speed;
1339                         u32 speed = bnxt_fw_to_ethtool_speed(fw_speed);
1340
1341                         netdev_warn(bp->dev, "Link speed %d no longer supported\n",
1342                                     speed);
1343                 }
1344                 /* fall thru */
1345         }
1346         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1347                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1348                 break;
1349         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD:
1350                 set_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event);
1351                 break;
1352         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED: {
1353                 u32 data1 = le32_to_cpu(cmpl->event_data1);
1354                 u16 port_id = BNXT_GET_EVENT_PORT(data1);
1355
1356                 if (BNXT_VF(bp))
1357                         break;
1358
1359                 if (bp->pf.port_id != port_id)
1360                         break;
1361
1362                 set_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event);
1363                 break;
1364         }
1365         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE:
1366                 if (BNXT_PF(bp))
1367                         goto async_event_process_exit;
1368                 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event);
1369                 break;
1370         default:
1371                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1372                            event_id);
1373                 goto async_event_process_exit;
1374         }
1375         schedule_work(&bp->sp_task);
1376 async_event_process_exit:
1377         return 0;
1378 }
1379
1380 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1381 {
1382         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1383         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1384         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1385                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1386
1387         switch (cmpl_type) {
1388         case CMPL_BASE_TYPE_HWRM_DONE:
1389                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1390                 if (seq_id == bp->hwrm_intr_seq_id)
1391                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1392                 else
1393                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1394                 break;
1395
1396         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1397                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1398
1399                 if ((vf_id < bp->pf.first_vf_id) ||
1400                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1401                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1402                                    vf_id);
1403                         return -EINVAL;
1404                 }
1405
1406                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1407                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1408                 schedule_work(&bp->sp_task);
1409                 break;
1410
1411         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1412                 bnxt_async_event_process(bp,
1413                                          (struct hwrm_async_event_cmpl *)txcmp);
1414
1415         default:
1416                 break;
1417         }
1418
1419         return 0;
1420 }
1421
1422 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1423 {
1424         struct bnxt_napi *bnapi = dev_instance;
1425         struct bnxt *bp = bnapi->bp;
1426         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1427         u32 cons = RING_CMP(cpr->cp_raw_cons);
1428
1429         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1430         napi_schedule(&bnapi->napi);
1431         return IRQ_HANDLED;
1432 }
1433
1434 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1435 {
1436         u32 raw_cons = cpr->cp_raw_cons;
1437         u16 cons = RING_CMP(raw_cons);
1438         struct tx_cmp *txcmp;
1439
1440         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1441
1442         return TX_CMP_VALID(txcmp, raw_cons);
1443 }
1444
1445 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1446 {
1447         struct bnxt_napi *bnapi = dev_instance;
1448         struct bnxt *bp = bnapi->bp;
1449         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1450         u32 cons = RING_CMP(cpr->cp_raw_cons);
1451         u32 int_status;
1452
1453         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1454
1455         if (!bnxt_has_work(bp, cpr)) {
1456                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1457                 /* return if erroneous interrupt */
1458                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1459                         return IRQ_NONE;
1460         }
1461
1462         /* disable ring IRQ */
1463         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1464
1465         /* Return here if interrupt is shared and is disabled. */
1466         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1467                 return IRQ_HANDLED;
1468
1469         napi_schedule(&bnapi->napi);
1470         return IRQ_HANDLED;
1471 }
1472
1473 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1474 {
1475         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1476         u32 raw_cons = cpr->cp_raw_cons;
1477         u32 cons;
1478         int tx_pkts = 0;
1479         int rx_pkts = 0;
1480         bool rx_event = false;
1481         bool agg_event = false;
1482         struct tx_cmp *txcmp;
1483
1484         while (1) {
1485                 int rc;
1486
1487                 cons = RING_CMP(raw_cons);
1488                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1489
1490                 if (!TX_CMP_VALID(txcmp, raw_cons))
1491                         break;
1492
1493                 /* The valid test of the entry must be done first before
1494                  * reading any further.
1495                  */
1496                 dma_rmb();
1497                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1498                         tx_pkts++;
1499                         /* return full budget so NAPI will complete. */
1500                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1501                                 rx_pkts = budget;
1502                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1503                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1504                         if (likely(rc >= 0))
1505                                 rx_pkts += rc;
1506                         else if (rc == -EBUSY)  /* partial completion */
1507                                 break;
1508                         rx_event = true;
1509                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1510                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1511                                     (TX_CMP_TYPE(txcmp) ==
1512                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1513                                     (TX_CMP_TYPE(txcmp) ==
1514                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1515                         bnxt_hwrm_handler(bp, txcmp);
1516                 }
1517                 raw_cons = NEXT_RAW_CMP(raw_cons);
1518
1519                 if (rx_pkts == budget)
1520                         break;
1521         }
1522
1523         cpr->cp_raw_cons = raw_cons;
1524         /* ACK completion ring before freeing tx ring and producing new
1525          * buffers in rx/agg rings to prevent overflowing the completion
1526          * ring.
1527          */
1528         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1529
1530         if (tx_pkts)
1531                 bnxt_tx_int(bp, bnapi, tx_pkts);
1532
1533         if (rx_event) {
1534                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1535
1536                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1537                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1538                 if (agg_event) {
1539                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1540                                rxr->rx_agg_doorbell);
1541                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1542                                rxr->rx_agg_doorbell);
1543                 }
1544         }
1545         return rx_pkts;
1546 }
1547
1548 static int bnxt_poll(struct napi_struct *napi, int budget)
1549 {
1550         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1551         struct bnxt *bp = bnapi->bp;
1552         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1553         int work_done = 0;
1554
1555         if (!bnxt_lock_napi(bnapi))
1556                 return budget;
1557
1558         while (1) {
1559                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1560
1561                 if (work_done >= budget)
1562                         break;
1563
1564                 if (!bnxt_has_work(bp, cpr)) {
1565                         napi_complete(napi);
1566                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1567                         break;
1568                 }
1569         }
1570         mmiowb();
1571         bnxt_unlock_napi(bnapi);
1572         return work_done;
1573 }
1574
1575 #ifdef CONFIG_NET_RX_BUSY_POLL
1576 static int bnxt_busy_poll(struct napi_struct *napi)
1577 {
1578         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1579         struct bnxt *bp = bnapi->bp;
1580         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1581         int rx_work, budget = 4;
1582
1583         if (atomic_read(&bp->intr_sem) != 0)
1584                 return LL_FLUSH_FAILED;
1585
1586         if (!bnxt_lock_poll(bnapi))
1587                 return LL_FLUSH_BUSY;
1588
1589         rx_work = bnxt_poll_work(bp, bnapi, budget);
1590
1591         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1592
1593         bnxt_unlock_poll(bnapi);
1594         return rx_work;
1595 }
1596 #endif
1597
1598 static void bnxt_free_tx_skbs(struct bnxt *bp)
1599 {
1600         int i, max_idx;
1601         struct pci_dev *pdev = bp->pdev;
1602
1603         if (!bp->tx_ring)
1604                 return;
1605
1606         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1607         for (i = 0; i < bp->tx_nr_rings; i++) {
1608                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1609                 int j;
1610
1611                 for (j = 0; j < max_idx;) {
1612                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1613                         struct sk_buff *skb = tx_buf->skb;
1614                         int k, last;
1615
1616                         if (!skb) {
1617                                 j++;
1618                                 continue;
1619                         }
1620
1621                         tx_buf->skb = NULL;
1622
1623                         if (tx_buf->is_push) {
1624                                 dev_kfree_skb(skb);
1625                                 j += 2;
1626                                 continue;
1627                         }
1628
1629                         dma_unmap_single(&pdev->dev,
1630                                          dma_unmap_addr(tx_buf, mapping),
1631                                          skb_headlen(skb),
1632                                          PCI_DMA_TODEVICE);
1633
1634                         last = tx_buf->nr_frags;
1635                         j += 2;
1636                         for (k = 0; k < last; k++, j++) {
1637                                 int ring_idx = j & bp->tx_ring_mask;
1638                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1639
1640                                 tx_buf = &txr->tx_buf_ring[ring_idx];
1641                                 dma_unmap_page(
1642                                         &pdev->dev,
1643                                         dma_unmap_addr(tx_buf, mapping),
1644                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1645                         }
1646                         dev_kfree_skb(skb);
1647                 }
1648                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1649         }
1650 }
1651
1652 static void bnxt_free_rx_skbs(struct bnxt *bp)
1653 {
1654         int i, max_idx, max_agg_idx;
1655         struct pci_dev *pdev = bp->pdev;
1656
1657         if (!bp->rx_ring)
1658                 return;
1659
1660         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1661         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1662         for (i = 0; i < bp->rx_nr_rings; i++) {
1663                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1664                 int j;
1665
1666                 if (rxr->rx_tpa) {
1667                         for (j = 0; j < MAX_TPA; j++) {
1668                                 struct bnxt_tpa_info *tpa_info =
1669                                                         &rxr->rx_tpa[j];
1670                                 u8 *data = tpa_info->data;
1671
1672                                 if (!data)
1673                                         continue;
1674
1675                                 dma_unmap_single(
1676                                         &pdev->dev,
1677                                         dma_unmap_addr(tpa_info, mapping),
1678                                         bp->rx_buf_use_size,
1679                                         PCI_DMA_FROMDEVICE);
1680
1681                                 tpa_info->data = NULL;
1682
1683                                 kfree(data);
1684                         }
1685                 }
1686
1687                 for (j = 0; j < max_idx; j++) {
1688                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1689                         u8 *data = rx_buf->data;
1690
1691                         if (!data)
1692                                 continue;
1693
1694                         dma_unmap_single(&pdev->dev,
1695                                          dma_unmap_addr(rx_buf, mapping),
1696                                          bp->rx_buf_use_size,
1697                                          PCI_DMA_FROMDEVICE);
1698
1699                         rx_buf->data = NULL;
1700
1701                         kfree(data);
1702                 }
1703
1704                 for (j = 0; j < max_agg_idx; j++) {
1705                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1706                                 &rxr->rx_agg_ring[j];
1707                         struct page *page = rx_agg_buf->page;
1708
1709                         if (!page)
1710                                 continue;
1711
1712                         dma_unmap_page(&pdev->dev,
1713                                        dma_unmap_addr(rx_agg_buf, mapping),
1714                                        BNXT_RX_PAGE_SIZE, PCI_DMA_FROMDEVICE);
1715
1716                         rx_agg_buf->page = NULL;
1717                         __clear_bit(j, rxr->rx_agg_bmap);
1718
1719                         __free_page(page);
1720                 }
1721                 if (rxr->rx_page) {
1722                         __free_page(rxr->rx_page);
1723                         rxr->rx_page = NULL;
1724                 }
1725         }
1726 }
1727
1728 static void bnxt_free_skbs(struct bnxt *bp)
1729 {
1730         bnxt_free_tx_skbs(bp);
1731         bnxt_free_rx_skbs(bp);
1732 }
1733
1734 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1735 {
1736         struct pci_dev *pdev = bp->pdev;
1737         int i;
1738
1739         for (i = 0; i < ring->nr_pages; i++) {
1740                 if (!ring->pg_arr[i])
1741                         continue;
1742
1743                 dma_free_coherent(&pdev->dev, ring->page_size,
1744                                   ring->pg_arr[i], ring->dma_arr[i]);
1745
1746                 ring->pg_arr[i] = NULL;
1747         }
1748         if (ring->pg_tbl) {
1749                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1750                                   ring->pg_tbl, ring->pg_tbl_map);
1751                 ring->pg_tbl = NULL;
1752         }
1753         if (ring->vmem_size && *ring->vmem) {
1754                 vfree(*ring->vmem);
1755                 *ring->vmem = NULL;
1756         }
1757 }
1758
1759 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1760 {
1761         int i;
1762         struct pci_dev *pdev = bp->pdev;
1763
1764         if (ring->nr_pages > 1) {
1765                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1766                                                   ring->nr_pages * 8,
1767                                                   &ring->pg_tbl_map,
1768                                                   GFP_KERNEL);
1769                 if (!ring->pg_tbl)
1770                         return -ENOMEM;
1771         }
1772
1773         for (i = 0; i < ring->nr_pages; i++) {
1774                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1775                                                      ring->page_size,
1776                                                      &ring->dma_arr[i],
1777                                                      GFP_KERNEL);
1778                 if (!ring->pg_arr[i])
1779                         return -ENOMEM;
1780
1781                 if (ring->nr_pages > 1)
1782                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1783         }
1784
1785         if (ring->vmem_size) {
1786                 *ring->vmem = vzalloc(ring->vmem_size);
1787                 if (!(*ring->vmem))
1788                         return -ENOMEM;
1789         }
1790         return 0;
1791 }
1792
1793 static void bnxt_free_rx_rings(struct bnxt *bp)
1794 {
1795         int i;
1796
1797         if (!bp->rx_ring)
1798                 return;
1799
1800         for (i = 0; i < bp->rx_nr_rings; i++) {
1801                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1802                 struct bnxt_ring_struct *ring;
1803
1804                 kfree(rxr->rx_tpa);
1805                 rxr->rx_tpa = NULL;
1806
1807                 kfree(rxr->rx_agg_bmap);
1808                 rxr->rx_agg_bmap = NULL;
1809
1810                 ring = &rxr->rx_ring_struct;
1811                 bnxt_free_ring(bp, ring);
1812
1813                 ring = &rxr->rx_agg_ring_struct;
1814                 bnxt_free_ring(bp, ring);
1815         }
1816 }
1817
1818 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1819 {
1820         int i, rc, agg_rings = 0, tpa_rings = 0;
1821
1822         if (!bp->rx_ring)
1823                 return -ENOMEM;
1824
1825         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1826                 agg_rings = 1;
1827
1828         if (bp->flags & BNXT_FLAG_TPA)
1829                 tpa_rings = 1;
1830
1831         for (i = 0; i < bp->rx_nr_rings; i++) {
1832                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1833                 struct bnxt_ring_struct *ring;
1834
1835                 ring = &rxr->rx_ring_struct;
1836
1837                 rc = bnxt_alloc_ring(bp, ring);
1838                 if (rc)
1839                         return rc;
1840
1841                 if (agg_rings) {
1842                         u16 mem_size;
1843
1844                         ring = &rxr->rx_agg_ring_struct;
1845                         rc = bnxt_alloc_ring(bp, ring);
1846                         if (rc)
1847                                 return rc;
1848
1849                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1850                         mem_size = rxr->rx_agg_bmap_size / 8;
1851                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1852                         if (!rxr->rx_agg_bmap)
1853                                 return -ENOMEM;
1854
1855                         if (tpa_rings) {
1856                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1857                                                 sizeof(struct bnxt_tpa_info),
1858                                                 GFP_KERNEL);
1859                                 if (!rxr->rx_tpa)
1860                                         return -ENOMEM;
1861                         }
1862                 }
1863         }
1864         return 0;
1865 }
1866
1867 static void bnxt_free_tx_rings(struct bnxt *bp)
1868 {
1869         int i;
1870         struct pci_dev *pdev = bp->pdev;
1871
1872         if (!bp->tx_ring)
1873                 return;
1874
1875         for (i = 0; i < bp->tx_nr_rings; i++) {
1876                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1877                 struct bnxt_ring_struct *ring;
1878
1879                 if (txr->tx_push) {
1880                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1881                                           txr->tx_push, txr->tx_push_mapping);
1882                         txr->tx_push = NULL;
1883                 }
1884
1885                 ring = &txr->tx_ring_struct;
1886
1887                 bnxt_free_ring(bp, ring);
1888         }
1889 }
1890
1891 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1892 {
1893         int i, j, rc;
1894         struct pci_dev *pdev = bp->pdev;
1895
1896         bp->tx_push_size = 0;
1897         if (bp->tx_push_thresh) {
1898                 int push_size;
1899
1900                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1901                                         bp->tx_push_thresh);
1902
1903                 if (push_size > 256) {
1904                         push_size = 0;
1905                         bp->tx_push_thresh = 0;
1906                 }
1907
1908                 bp->tx_push_size = push_size;
1909         }
1910
1911         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1912                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1913                 struct bnxt_ring_struct *ring;
1914
1915                 ring = &txr->tx_ring_struct;
1916
1917                 rc = bnxt_alloc_ring(bp, ring);
1918                 if (rc)
1919                         return rc;
1920
1921                 if (bp->tx_push_size) {
1922                         dma_addr_t mapping;
1923
1924                         /* One pre-allocated DMA buffer to backup
1925                          * TX push operation
1926                          */
1927                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1928                                                 bp->tx_push_size,
1929                                                 &txr->tx_push_mapping,
1930                                                 GFP_KERNEL);
1931
1932                         if (!txr->tx_push)
1933                                 return -ENOMEM;
1934
1935                         mapping = txr->tx_push_mapping +
1936                                 sizeof(struct tx_push_bd);
1937                         txr->data_mapping = cpu_to_le64(mapping);
1938
1939                         memset(txr->tx_push, 0, sizeof(struct tx_push_bd));
1940                 }
1941                 ring->queue_id = bp->q_info[j].queue_id;
1942                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1943                         j++;
1944         }
1945         return 0;
1946 }
1947
1948 static void bnxt_free_cp_rings(struct bnxt *bp)
1949 {
1950         int i;
1951
1952         if (!bp->bnapi)
1953                 return;
1954
1955         for (i = 0; i < bp->cp_nr_rings; i++) {
1956                 struct bnxt_napi *bnapi = bp->bnapi[i];
1957                 struct bnxt_cp_ring_info *cpr;
1958                 struct bnxt_ring_struct *ring;
1959
1960                 if (!bnapi)
1961                         continue;
1962
1963                 cpr = &bnapi->cp_ring;
1964                 ring = &cpr->cp_ring_struct;
1965
1966                 bnxt_free_ring(bp, ring);
1967         }
1968 }
1969
1970 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1971 {
1972         int i, rc;
1973
1974         for (i = 0; i < bp->cp_nr_rings; i++) {
1975                 struct bnxt_napi *bnapi = bp->bnapi[i];
1976                 struct bnxt_cp_ring_info *cpr;
1977                 struct bnxt_ring_struct *ring;
1978
1979                 if (!bnapi)
1980                         continue;
1981
1982                 cpr = &bnapi->cp_ring;
1983                 ring = &cpr->cp_ring_struct;
1984
1985                 rc = bnxt_alloc_ring(bp, ring);
1986                 if (rc)
1987                         return rc;
1988         }
1989         return 0;
1990 }
1991
1992 static void bnxt_init_ring_struct(struct bnxt *bp)
1993 {
1994         int i;
1995
1996         for (i = 0; i < bp->cp_nr_rings; i++) {
1997                 struct bnxt_napi *bnapi = bp->bnapi[i];
1998                 struct bnxt_cp_ring_info *cpr;
1999                 struct bnxt_rx_ring_info *rxr;
2000                 struct bnxt_tx_ring_info *txr;
2001                 struct bnxt_ring_struct *ring;
2002
2003                 if (!bnapi)
2004                         continue;
2005
2006                 cpr = &bnapi->cp_ring;
2007                 ring = &cpr->cp_ring_struct;
2008                 ring->nr_pages = bp->cp_nr_pages;
2009                 ring->page_size = HW_CMPD_RING_SIZE;
2010                 ring->pg_arr = (void **)cpr->cp_desc_ring;
2011                 ring->dma_arr = cpr->cp_desc_mapping;
2012                 ring->vmem_size = 0;
2013
2014                 rxr = bnapi->rx_ring;
2015                 if (!rxr)
2016                         goto skip_rx;
2017
2018                 ring = &rxr->rx_ring_struct;
2019                 ring->nr_pages = bp->rx_nr_pages;
2020                 ring->page_size = HW_RXBD_RING_SIZE;
2021                 ring->pg_arr = (void **)rxr->rx_desc_ring;
2022                 ring->dma_arr = rxr->rx_desc_mapping;
2023                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
2024                 ring->vmem = (void **)&rxr->rx_buf_ring;
2025
2026                 ring = &rxr->rx_agg_ring_struct;
2027                 ring->nr_pages = bp->rx_agg_nr_pages;
2028                 ring->page_size = HW_RXBD_RING_SIZE;
2029                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
2030                 ring->dma_arr = rxr->rx_agg_desc_mapping;
2031                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
2032                 ring->vmem = (void **)&rxr->rx_agg_ring;
2033
2034 skip_rx:
2035                 txr = bnapi->tx_ring;
2036                 if (!txr)
2037                         continue;
2038
2039                 ring = &txr->tx_ring_struct;
2040                 ring->nr_pages = bp->tx_nr_pages;
2041                 ring->page_size = HW_RXBD_RING_SIZE;
2042                 ring->pg_arr = (void **)txr->tx_desc_ring;
2043                 ring->dma_arr = txr->tx_desc_mapping;
2044                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
2045                 ring->vmem = (void **)&txr->tx_buf_ring;
2046         }
2047 }
2048
2049 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
2050 {
2051         int i;
2052         u32 prod;
2053         struct rx_bd **rx_buf_ring;
2054
2055         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
2056         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
2057                 int j;
2058                 struct rx_bd *rxbd;
2059
2060                 rxbd = rx_buf_ring[i];
2061                 if (!rxbd)
2062                         continue;
2063
2064                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
2065                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
2066                         rxbd->rx_bd_opaque = prod;
2067                 }
2068         }
2069 }
2070
2071 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
2072 {
2073         struct net_device *dev = bp->dev;
2074         struct bnxt_rx_ring_info *rxr;
2075         struct bnxt_ring_struct *ring;
2076         u32 prod, type;
2077         int i;
2078
2079         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
2080                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
2081
2082         if (NET_IP_ALIGN == 2)
2083                 type |= RX_BD_FLAGS_SOP;
2084
2085         rxr = &bp->rx_ring[ring_nr];
2086         ring = &rxr->rx_ring_struct;
2087         bnxt_init_rxbd_pages(ring, type);
2088
2089         prod = rxr->rx_prod;
2090         for (i = 0; i < bp->rx_ring_size; i++) {
2091                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
2092                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
2093                                     ring_nr, i, bp->rx_ring_size);
2094                         break;
2095                 }
2096                 prod = NEXT_RX(prod);
2097         }
2098         rxr->rx_prod = prod;
2099         ring->fw_ring_id = INVALID_HW_RING_ID;
2100
2101         ring = &rxr->rx_agg_ring_struct;
2102         ring->fw_ring_id = INVALID_HW_RING_ID;
2103
2104         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
2105                 return 0;
2106
2107         type = ((u32)BNXT_RX_PAGE_SIZE << RX_BD_LEN_SHIFT) |
2108                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
2109
2110         bnxt_init_rxbd_pages(ring, type);
2111
2112         prod = rxr->rx_agg_prod;
2113         for (i = 0; i < bp->rx_agg_ring_size; i++) {
2114                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
2115                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
2116                                     ring_nr, i, bp->rx_ring_size);
2117                         break;
2118                 }
2119                 prod = NEXT_RX_AGG(prod);
2120         }
2121         rxr->rx_agg_prod = prod;
2122
2123         if (bp->flags & BNXT_FLAG_TPA) {
2124                 if (rxr->rx_tpa) {
2125                         u8 *data;
2126                         dma_addr_t mapping;
2127
2128                         for (i = 0; i < MAX_TPA; i++) {
2129                                 data = __bnxt_alloc_rx_data(bp, &mapping,
2130                                                             GFP_KERNEL);
2131                                 if (!data)
2132                                         return -ENOMEM;
2133
2134                                 rxr->rx_tpa[i].data = data;
2135                                 rxr->rx_tpa[i].mapping = mapping;
2136                         }
2137                 } else {
2138                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
2139                         return -ENOMEM;
2140                 }
2141         }
2142
2143         return 0;
2144 }
2145
2146 static int bnxt_init_rx_rings(struct bnxt *bp)
2147 {
2148         int i, rc = 0;
2149
2150         for (i = 0; i < bp->rx_nr_rings; i++) {
2151                 rc = bnxt_init_one_rx_ring(bp, i);
2152                 if (rc)
2153                         break;
2154         }
2155
2156         return rc;
2157 }
2158
2159 static int bnxt_init_tx_rings(struct bnxt *bp)
2160 {
2161         u16 i;
2162
2163         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2164                                    MAX_SKB_FRAGS + 1);
2165
2166         for (i = 0; i < bp->tx_nr_rings; i++) {
2167                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2168                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2169
2170                 ring->fw_ring_id = INVALID_HW_RING_ID;
2171         }
2172
2173         return 0;
2174 }
2175
2176 static void bnxt_free_ring_grps(struct bnxt *bp)
2177 {
2178         kfree(bp->grp_info);
2179         bp->grp_info = NULL;
2180 }
2181
2182 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2183 {
2184         int i;
2185
2186         if (irq_re_init) {
2187                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2188                                        sizeof(struct bnxt_ring_grp_info),
2189                                        GFP_KERNEL);
2190                 if (!bp->grp_info)
2191                         return -ENOMEM;
2192         }
2193         for (i = 0; i < bp->cp_nr_rings; i++) {
2194                 if (irq_re_init)
2195                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2196                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2197                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2198                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2199                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2200         }
2201         return 0;
2202 }
2203
2204 static void bnxt_free_vnics(struct bnxt *bp)
2205 {
2206         kfree(bp->vnic_info);
2207         bp->vnic_info = NULL;
2208         bp->nr_vnics = 0;
2209 }
2210
2211 static int bnxt_alloc_vnics(struct bnxt *bp)
2212 {
2213         int num_vnics = 1;
2214
2215 #ifdef CONFIG_RFS_ACCEL
2216         if (bp->flags & BNXT_FLAG_RFS)
2217                 num_vnics += bp->rx_nr_rings;
2218 #endif
2219
2220         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2221                                 GFP_KERNEL);
2222         if (!bp->vnic_info)
2223                 return -ENOMEM;
2224
2225         bp->nr_vnics = num_vnics;
2226         return 0;
2227 }
2228
2229 static void bnxt_init_vnics(struct bnxt *bp)
2230 {
2231         int i;
2232
2233         for (i = 0; i < bp->nr_vnics; i++) {
2234                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2235
2236                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2237                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2238                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2239
2240                 if (bp->vnic_info[i].rss_hash_key) {
2241                         if (i == 0)
2242                                 prandom_bytes(vnic->rss_hash_key,
2243                                               HW_HASH_KEY_SIZE);
2244                         else
2245                                 memcpy(vnic->rss_hash_key,
2246                                        bp->vnic_info[0].rss_hash_key,
2247                                        HW_HASH_KEY_SIZE);
2248                 }
2249         }
2250 }
2251
2252 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2253 {
2254         int pages;
2255
2256         pages = ring_size / desc_per_pg;
2257
2258         if (!pages)
2259                 return 1;
2260
2261         pages++;
2262
2263         while (pages & (pages - 1))
2264                 pages++;
2265
2266         return pages;
2267 }
2268
2269 static void bnxt_set_tpa_flags(struct bnxt *bp)
2270 {
2271         bp->flags &= ~BNXT_FLAG_TPA;
2272         if (bp->dev->features & NETIF_F_LRO)
2273                 bp->flags |= BNXT_FLAG_LRO;
2274         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2275                 bp->flags |= BNXT_FLAG_GRO;
2276 }
2277
2278 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2279  * be set on entry.
2280  */
2281 void bnxt_set_ring_params(struct bnxt *bp)
2282 {
2283         u32 ring_size, rx_size, rx_space;
2284         u32 agg_factor = 0, agg_ring_size = 0;
2285
2286         /* 8 for CRC and VLAN */
2287         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2288
2289         rx_space = rx_size + NET_SKB_PAD +
2290                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2291
2292         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2293         ring_size = bp->rx_ring_size;
2294         bp->rx_agg_ring_size = 0;
2295         bp->rx_agg_nr_pages = 0;
2296
2297         if (bp->flags & BNXT_FLAG_TPA)
2298                 agg_factor = min_t(u32, 4, 65536 / BNXT_RX_PAGE_SIZE);
2299
2300         bp->flags &= ~BNXT_FLAG_JUMBO;
2301         if (rx_space > PAGE_SIZE) {
2302                 u32 jumbo_factor;
2303
2304                 bp->flags |= BNXT_FLAG_JUMBO;
2305                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2306                 if (jumbo_factor > agg_factor)
2307                         agg_factor = jumbo_factor;
2308         }
2309         agg_ring_size = ring_size * agg_factor;
2310
2311         if (agg_ring_size) {
2312                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2313                                                         RX_DESC_CNT);
2314                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2315                         u32 tmp = agg_ring_size;
2316
2317                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2318                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2319                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2320                                     tmp, agg_ring_size);
2321                 }
2322                 bp->rx_agg_ring_size = agg_ring_size;
2323                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2324                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2325                 rx_space = rx_size + NET_SKB_PAD +
2326                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2327         }
2328
2329         bp->rx_buf_use_size = rx_size;
2330         bp->rx_buf_size = rx_space;
2331
2332         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2333         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2334
2335         ring_size = bp->tx_ring_size;
2336         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2337         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2338
2339         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2340         bp->cp_ring_size = ring_size;
2341
2342         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2343         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2344                 bp->cp_nr_pages = MAX_CP_PAGES;
2345                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2346                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2347                             ring_size, bp->cp_ring_size);
2348         }
2349         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2350         bp->cp_ring_mask = bp->cp_bit - 1;
2351 }
2352
2353 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2354 {
2355         int i;
2356         struct bnxt_vnic_info *vnic;
2357         struct pci_dev *pdev = bp->pdev;
2358
2359         if (!bp->vnic_info)
2360                 return;
2361
2362         for (i = 0; i < bp->nr_vnics; i++) {
2363                 vnic = &bp->vnic_info[i];
2364
2365                 kfree(vnic->fw_grp_ids);
2366                 vnic->fw_grp_ids = NULL;
2367
2368                 kfree(vnic->uc_list);
2369                 vnic->uc_list = NULL;
2370
2371                 if (vnic->mc_list) {
2372                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2373                                           vnic->mc_list, vnic->mc_list_mapping);
2374                         vnic->mc_list = NULL;
2375                 }
2376
2377                 if (vnic->rss_table) {
2378                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2379                                           vnic->rss_table,
2380                                           vnic->rss_table_dma_addr);
2381                         vnic->rss_table = NULL;
2382                 }
2383
2384                 vnic->rss_hash_key = NULL;
2385                 vnic->flags = 0;
2386         }
2387 }
2388
2389 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2390 {
2391         int i, rc = 0, size;
2392         struct bnxt_vnic_info *vnic;
2393         struct pci_dev *pdev = bp->pdev;
2394         int max_rings;
2395
2396         for (i = 0; i < bp->nr_vnics; i++) {
2397                 vnic = &bp->vnic_info[i];
2398
2399                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2400                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2401
2402                         if (mem_size > 0) {
2403                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2404                                 if (!vnic->uc_list) {
2405                                         rc = -ENOMEM;
2406                                         goto out;
2407                                 }
2408                         }
2409                 }
2410
2411                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2412                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2413                         vnic->mc_list =
2414                                 dma_alloc_coherent(&pdev->dev,
2415                                                    vnic->mc_list_size,
2416                                                    &vnic->mc_list_mapping,
2417                                                    GFP_KERNEL);
2418                         if (!vnic->mc_list) {
2419                                 rc = -ENOMEM;
2420                                 goto out;
2421                         }
2422                 }
2423
2424                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2425                         max_rings = bp->rx_nr_rings;
2426                 else
2427                         max_rings = 1;
2428
2429                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2430                 if (!vnic->fw_grp_ids) {
2431                         rc = -ENOMEM;
2432                         goto out;
2433                 }
2434
2435                 /* Allocate rss table and hash key */
2436                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2437                                                      &vnic->rss_table_dma_addr,
2438                                                      GFP_KERNEL);
2439                 if (!vnic->rss_table) {
2440                         rc = -ENOMEM;
2441                         goto out;
2442                 }
2443
2444                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2445
2446                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2447                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2448         }
2449         return 0;
2450
2451 out:
2452         return rc;
2453 }
2454
2455 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2456 {
2457         struct pci_dev *pdev = bp->pdev;
2458
2459         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2460                           bp->hwrm_cmd_resp_dma_addr);
2461
2462         bp->hwrm_cmd_resp_addr = NULL;
2463         if (bp->hwrm_dbg_resp_addr) {
2464                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2465                                   bp->hwrm_dbg_resp_addr,
2466                                   bp->hwrm_dbg_resp_dma_addr);
2467
2468                 bp->hwrm_dbg_resp_addr = NULL;
2469         }
2470 }
2471
2472 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2473 {
2474         struct pci_dev *pdev = bp->pdev;
2475
2476         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2477                                                    &bp->hwrm_cmd_resp_dma_addr,
2478                                                    GFP_KERNEL);
2479         if (!bp->hwrm_cmd_resp_addr)
2480                 return -ENOMEM;
2481         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2482                                                     HWRM_DBG_REG_BUF_SIZE,
2483                                                     &bp->hwrm_dbg_resp_dma_addr,
2484                                                     GFP_KERNEL);
2485         if (!bp->hwrm_dbg_resp_addr)
2486                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2487
2488         return 0;
2489 }
2490
2491 static void bnxt_free_stats(struct bnxt *bp)
2492 {
2493         u32 size, i;
2494         struct pci_dev *pdev = bp->pdev;
2495
2496         if (bp->hw_rx_port_stats) {
2497                 dma_free_coherent(&pdev->dev, bp->hw_port_stats_size,
2498                                   bp->hw_rx_port_stats,
2499                                   bp->hw_rx_port_stats_map);
2500                 bp->hw_rx_port_stats = NULL;
2501                 bp->flags &= ~BNXT_FLAG_PORT_STATS;
2502         }
2503
2504         if (!bp->bnapi)
2505                 return;
2506
2507         size = sizeof(struct ctx_hw_stats);
2508
2509         for (i = 0; i < bp->cp_nr_rings; i++) {
2510                 struct bnxt_napi *bnapi = bp->bnapi[i];
2511                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2512
2513                 if (cpr->hw_stats) {
2514                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2515                                           cpr->hw_stats_map);
2516                         cpr->hw_stats = NULL;
2517                 }
2518         }
2519 }
2520
2521 static int bnxt_alloc_stats(struct bnxt *bp)
2522 {
2523         u32 size, i;
2524         struct pci_dev *pdev = bp->pdev;
2525
2526         size = sizeof(struct ctx_hw_stats);
2527
2528         for (i = 0; i < bp->cp_nr_rings; i++) {
2529                 struct bnxt_napi *bnapi = bp->bnapi[i];
2530                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2531
2532                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2533                                                    &cpr->hw_stats_map,
2534                                                    GFP_KERNEL);
2535                 if (!cpr->hw_stats)
2536                         return -ENOMEM;
2537
2538                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2539         }
2540
2541         if (BNXT_PF(bp)) {
2542                 bp->hw_port_stats_size = sizeof(struct rx_port_stats) +
2543                                          sizeof(struct tx_port_stats) + 1024;
2544
2545                 bp->hw_rx_port_stats =
2546                         dma_alloc_coherent(&pdev->dev, bp->hw_port_stats_size,
2547                                            &bp->hw_rx_port_stats_map,
2548                                            GFP_KERNEL);
2549                 if (!bp->hw_rx_port_stats)
2550                         return -ENOMEM;
2551
2552                 bp->hw_tx_port_stats = (void *)(bp->hw_rx_port_stats + 1) +
2553                                        512;
2554                 bp->hw_tx_port_stats_map = bp->hw_rx_port_stats_map +
2555                                            sizeof(struct rx_port_stats) + 512;
2556                 bp->flags |= BNXT_FLAG_PORT_STATS;
2557         }
2558         return 0;
2559 }
2560
2561 static void bnxt_clear_ring_indices(struct bnxt *bp)
2562 {
2563         int i;
2564
2565         if (!bp->bnapi)
2566                 return;
2567
2568         for (i = 0; i < bp->cp_nr_rings; i++) {
2569                 struct bnxt_napi *bnapi = bp->bnapi[i];
2570                 struct bnxt_cp_ring_info *cpr;
2571                 struct bnxt_rx_ring_info *rxr;
2572                 struct bnxt_tx_ring_info *txr;
2573
2574                 if (!bnapi)
2575                         continue;
2576
2577                 cpr = &bnapi->cp_ring;
2578                 cpr->cp_raw_cons = 0;
2579
2580                 txr = bnapi->tx_ring;
2581                 if (txr) {
2582                         txr->tx_prod = 0;
2583                         txr->tx_cons = 0;
2584                 }
2585
2586                 rxr = bnapi->rx_ring;
2587                 if (rxr) {
2588                         rxr->rx_prod = 0;
2589                         rxr->rx_agg_prod = 0;
2590                         rxr->rx_sw_agg_prod = 0;
2591                         rxr->rx_next_cons = 0;
2592                 }
2593         }
2594 }
2595
2596 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2597 {
2598 #ifdef CONFIG_RFS_ACCEL
2599         int i;
2600
2601         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2602          * safe to delete the hash table.
2603          */
2604         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2605                 struct hlist_head *head;
2606                 struct hlist_node *tmp;
2607                 struct bnxt_ntuple_filter *fltr;
2608
2609                 head = &bp->ntp_fltr_hash_tbl[i];
2610                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2611                         hlist_del(&fltr->hash);
2612                         kfree(fltr);
2613                 }
2614         }
2615         if (irq_reinit) {
2616                 kfree(bp->ntp_fltr_bmap);
2617                 bp->ntp_fltr_bmap = NULL;
2618         }
2619         bp->ntp_fltr_count = 0;
2620 #endif
2621 }
2622
2623 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2624 {
2625 #ifdef CONFIG_RFS_ACCEL
2626         int i, rc = 0;
2627
2628         if (!(bp->flags & BNXT_FLAG_RFS))
2629                 return 0;
2630
2631         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2632                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2633
2634         bp->ntp_fltr_count = 0;
2635         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2636                                     GFP_KERNEL);
2637
2638         if (!bp->ntp_fltr_bmap)
2639                 rc = -ENOMEM;
2640
2641         return rc;
2642 #else
2643         return 0;
2644 #endif
2645 }
2646
2647 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2648 {
2649         bnxt_free_vnic_attributes(bp);
2650         bnxt_free_tx_rings(bp);
2651         bnxt_free_rx_rings(bp);
2652         bnxt_free_cp_rings(bp);
2653         bnxt_free_ntp_fltrs(bp, irq_re_init);
2654         if (irq_re_init) {
2655                 bnxt_free_stats(bp);
2656                 bnxt_free_ring_grps(bp);
2657                 bnxt_free_vnics(bp);
2658                 kfree(bp->tx_ring);
2659                 bp->tx_ring = NULL;
2660                 kfree(bp->rx_ring);
2661                 bp->rx_ring = NULL;
2662                 kfree(bp->bnapi);
2663                 bp->bnapi = NULL;
2664         } else {
2665                 bnxt_clear_ring_indices(bp);
2666         }
2667 }
2668
2669 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2670 {
2671         int i, j, rc, size, arr_size;
2672         void *bnapi;
2673
2674         if (irq_re_init) {
2675                 /* Allocate bnapi mem pointer array and mem block for
2676                  * all queues
2677                  */
2678                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2679                                 bp->cp_nr_rings);
2680                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2681                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2682                 if (!bnapi)
2683                         return -ENOMEM;
2684
2685                 bp->bnapi = bnapi;
2686                 bnapi += arr_size;
2687                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2688                         bp->bnapi[i] = bnapi;
2689                         bp->bnapi[i]->index = i;
2690                         bp->bnapi[i]->bp = bp;
2691                 }
2692
2693                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2694                                       sizeof(struct bnxt_rx_ring_info),
2695                                       GFP_KERNEL);
2696                 if (!bp->rx_ring)
2697                         return -ENOMEM;
2698
2699                 for (i = 0; i < bp->rx_nr_rings; i++) {
2700                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2701                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2702                 }
2703
2704                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2705                                       sizeof(struct bnxt_tx_ring_info),
2706                                       GFP_KERNEL);
2707                 if (!bp->tx_ring)
2708                         return -ENOMEM;
2709
2710                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
2711                         j = 0;
2712                 else
2713                         j = bp->rx_nr_rings;
2714
2715                 for (i = 0; i < bp->tx_nr_rings; i++, j++) {
2716                         bp->tx_ring[i].bnapi = bp->bnapi[j];
2717                         bp->bnapi[j]->tx_ring = &bp->tx_ring[i];
2718                 }
2719
2720                 rc = bnxt_alloc_stats(bp);
2721                 if (rc)
2722                         goto alloc_mem_err;
2723
2724                 rc = bnxt_alloc_ntp_fltrs(bp);
2725                 if (rc)
2726                         goto alloc_mem_err;
2727
2728                 rc = bnxt_alloc_vnics(bp);
2729                 if (rc)
2730                         goto alloc_mem_err;
2731         }
2732
2733         bnxt_init_ring_struct(bp);
2734
2735         rc = bnxt_alloc_rx_rings(bp);
2736         if (rc)
2737                 goto alloc_mem_err;
2738
2739         rc = bnxt_alloc_tx_rings(bp);
2740         if (rc)
2741                 goto alloc_mem_err;
2742
2743         rc = bnxt_alloc_cp_rings(bp);
2744         if (rc)
2745                 goto alloc_mem_err;
2746
2747         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2748                                   BNXT_VNIC_UCAST_FLAG;
2749         rc = bnxt_alloc_vnic_attributes(bp);
2750         if (rc)
2751                 goto alloc_mem_err;
2752         return 0;
2753
2754 alloc_mem_err:
2755         bnxt_free_mem(bp, true);
2756         return rc;
2757 }
2758
2759 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2760                             u16 cmpl_ring, u16 target_id)
2761 {
2762         struct input *req = request;
2763
2764         req->req_type = cpu_to_le16(req_type);
2765         req->cmpl_ring = cpu_to_le16(cmpl_ring);
2766         req->target_id = cpu_to_le16(target_id);
2767         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2768 }
2769
2770 static int bnxt_hwrm_do_send_msg(struct bnxt *bp, void *msg, u32 msg_len,
2771                                  int timeout, bool silent)
2772 {
2773         int i, intr_process, rc, tmo_count;
2774         struct input *req = msg;
2775         u32 *data = msg;
2776         __le32 *resp_len, *valid;
2777         u16 cp_ring_id, len = 0;
2778         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2779
2780         req->seq_id = cpu_to_le16(bp->hwrm_cmd_seq++);
2781         memset(resp, 0, PAGE_SIZE);
2782         cp_ring_id = le16_to_cpu(req->cmpl_ring);
2783         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2784
2785         /* Write request msg to hwrm channel */
2786         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2787
2788         for (i = msg_len; i < BNXT_HWRM_MAX_REQ_LEN; i += 4)
2789                 writel(0, bp->bar0 + i);
2790
2791         /* currently supports only one outstanding message */
2792         if (intr_process)
2793                 bp->hwrm_intr_seq_id = le16_to_cpu(req->seq_id);
2794
2795         /* Ring channel doorbell */
2796         writel(1, bp->bar0 + 0x100);
2797
2798         if (!timeout)
2799                 timeout = DFLT_HWRM_CMD_TIMEOUT;
2800
2801         i = 0;
2802         tmo_count = timeout * 40;
2803         if (intr_process) {
2804                 /* Wait until hwrm response cmpl interrupt is processed */
2805                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2806                        i++ < tmo_count) {
2807                         usleep_range(25, 40);
2808                 }
2809
2810                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2811                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2812                                    le16_to_cpu(req->req_type));
2813                         return -1;
2814                 }
2815         } else {
2816                 /* Check if response len is updated */
2817                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2818                 for (i = 0; i < tmo_count; i++) {
2819                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2820                               HWRM_RESP_LEN_SFT;
2821                         if (len)
2822                                 break;
2823                         usleep_range(25, 40);
2824                 }
2825
2826                 if (i >= tmo_count) {
2827                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2828                                    timeout, le16_to_cpu(req->req_type),
2829                                    le16_to_cpu(req->seq_id), len);
2830                         return -1;
2831                 }
2832
2833                 /* Last word of resp contains valid bit */
2834                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2835                 for (i = 0; i < 5; i++) {
2836                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2837                                 break;
2838                         udelay(1);
2839                 }
2840
2841                 if (i >= 5) {
2842                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2843                                    timeout, le16_to_cpu(req->req_type),
2844                                    le16_to_cpu(req->seq_id), len, *valid);
2845                         return -1;
2846                 }
2847         }
2848
2849         rc = le16_to_cpu(resp->error_code);
2850         if (rc && !silent)
2851                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2852                            le16_to_cpu(resp->req_type),
2853                            le16_to_cpu(resp->seq_id), rc);
2854         return rc;
2855 }
2856
2857 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2858 {
2859         return bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, false);
2860 }
2861
2862 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2863 {
2864         int rc;
2865
2866         mutex_lock(&bp->hwrm_cmd_lock);
2867         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2868         mutex_unlock(&bp->hwrm_cmd_lock);
2869         return rc;
2870 }
2871
2872 int hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 msg_len,
2873                              int timeout)
2874 {
2875         int rc;
2876
2877         mutex_lock(&bp->hwrm_cmd_lock);
2878         rc = bnxt_hwrm_do_send_msg(bp, msg, msg_len, timeout, true);
2879         mutex_unlock(&bp->hwrm_cmd_lock);
2880         return rc;
2881 }
2882
2883 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2884 {
2885         struct hwrm_func_drv_rgtr_input req = {0};
2886         int i;
2887         DECLARE_BITMAP(async_events_bmap, 256);
2888         u32 *events = (u32 *)async_events_bmap;
2889
2890         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2891
2892         req.enables =
2893                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2894                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2895                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2896
2897         memset(async_events_bmap, 0, sizeof(async_events_bmap));
2898         for (i = 0; i < ARRAY_SIZE(bnxt_async_events_arr); i++)
2899                 __set_bit(bnxt_async_events_arr[i], async_events_bmap);
2900
2901         for (i = 0; i < 8; i++)
2902                 req.async_event_fwd[i] |= cpu_to_le32(events[i]);
2903
2904         req.os_type = cpu_to_le16(FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX);
2905         req.ver_maj = DRV_VER_MAJ;
2906         req.ver_min = DRV_VER_MIN;
2907         req.ver_upd = DRV_VER_UPD;
2908
2909         if (BNXT_PF(bp)) {
2910                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2911                 u32 *data = (u32 *)vf_req_snif_bmap;
2912
2913                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2914                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2915                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2916
2917                 for (i = 0; i < 8; i++)
2918                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2919
2920                 req.enables |=
2921                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2922         }
2923
2924         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2925 }
2926
2927 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2928 {
2929         struct hwrm_func_drv_unrgtr_input req = {0};
2930
2931         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2932         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2933 }
2934
2935 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2936 {
2937         u32 rc = 0;
2938         struct hwrm_tunnel_dst_port_free_input req = {0};
2939
2940         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2941         req.tunnel_type = tunnel_type;
2942
2943         switch (tunnel_type) {
2944         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2945                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2946                 break;
2947         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2948                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2949                 break;
2950         default:
2951                 break;
2952         }
2953
2954         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2955         if (rc)
2956                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2957                            rc);
2958         return rc;
2959 }
2960
2961 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2962                                            u8 tunnel_type)
2963 {
2964         u32 rc = 0;
2965         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2966         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2967
2968         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2969
2970         req.tunnel_type = tunnel_type;
2971         req.tunnel_dst_port_val = port;
2972
2973         mutex_lock(&bp->hwrm_cmd_lock);
2974         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2975         if (rc) {
2976                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2977                            rc);
2978                 goto err_out;
2979         }
2980
2981         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2982                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2983
2984         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2985                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2986 err_out:
2987         mutex_unlock(&bp->hwrm_cmd_lock);
2988         return rc;
2989 }
2990
2991 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2992 {
2993         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2994         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2995
2996         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2997         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2998
2999         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
3000         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
3001         req.mask = cpu_to_le32(vnic->rx_mask);
3002         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3003 }
3004
3005 #ifdef CONFIG_RFS_ACCEL
3006 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
3007                                             struct bnxt_ntuple_filter *fltr)
3008 {
3009         struct hwrm_cfa_ntuple_filter_free_input req = {0};
3010
3011         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
3012         req.ntuple_filter_id = fltr->filter_id;
3013         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3014 }
3015
3016 #define BNXT_NTP_FLTR_FLAGS                                     \
3017         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
3018          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
3019          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
3020          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
3021          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
3022          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
3023          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
3024          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
3025          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
3026          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
3027          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
3028          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
3029          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
3030          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
3031
3032 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
3033                                              struct bnxt_ntuple_filter *fltr)
3034 {
3035         int rc = 0;
3036         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
3037         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
3038                 bp->hwrm_cmd_resp_addr;
3039         struct flow_keys *keys = &fltr->fkeys;
3040         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
3041
3042         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
3043         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
3044
3045         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
3046
3047         req.ethertype = htons(ETH_P_IP);
3048         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
3049         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
3050         req.ip_protocol = keys->basic.ip_proto;
3051
3052         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
3053         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3054         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
3055         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
3056
3057         req.src_port = keys->ports.src;
3058         req.src_port_mask = cpu_to_be16(0xffff);
3059         req.dst_port = keys->ports.dst;
3060         req.dst_port_mask = cpu_to_be16(0xffff);
3061
3062         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
3063         mutex_lock(&bp->hwrm_cmd_lock);
3064         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3065         if (!rc)
3066                 fltr->filter_id = resp->ntuple_filter_id;
3067         mutex_unlock(&bp->hwrm_cmd_lock);
3068         return rc;
3069 }
3070 #endif
3071
3072 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
3073                                      u8 *mac_addr)
3074 {
3075         u32 rc = 0;
3076         struct hwrm_cfa_l2_filter_alloc_input req = {0};
3077         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3078
3079         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
3080         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
3081                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
3082         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
3083         req.enables =
3084                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
3085                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
3086                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
3087         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
3088         req.l2_addr_mask[0] = 0xff;
3089         req.l2_addr_mask[1] = 0xff;
3090         req.l2_addr_mask[2] = 0xff;
3091         req.l2_addr_mask[3] = 0xff;
3092         req.l2_addr_mask[4] = 0xff;
3093         req.l2_addr_mask[5] = 0xff;
3094
3095         mutex_lock(&bp->hwrm_cmd_lock);
3096         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3097         if (!rc)
3098                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
3099                                                         resp->l2_filter_id;
3100         mutex_unlock(&bp->hwrm_cmd_lock);
3101         return rc;
3102 }
3103
3104 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
3105 {
3106         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
3107         int rc = 0;
3108
3109         /* Any associated ntuple filters will also be cleared by firmware. */
3110         mutex_lock(&bp->hwrm_cmd_lock);
3111         for (i = 0; i < num_of_vnics; i++) {
3112                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3113
3114                 for (j = 0; j < vnic->uc_filter_count; j++) {
3115                         struct hwrm_cfa_l2_filter_free_input req = {0};
3116
3117                         bnxt_hwrm_cmd_hdr_init(bp, &req,
3118                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
3119
3120                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
3121
3122                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3123                                                 HWRM_CMD_TIMEOUT);
3124                 }
3125                 vnic->uc_filter_count = 0;
3126         }
3127         mutex_unlock(&bp->hwrm_cmd_lock);
3128
3129         return rc;
3130 }
3131
3132 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
3133 {
3134         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3135         struct hwrm_vnic_tpa_cfg_input req = {0};
3136
3137         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
3138
3139         if (tpa_flags) {
3140                 u16 mss = bp->dev->mtu - 40;
3141                 u32 nsegs, n, segs = 0, flags;
3142
3143                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
3144                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
3145                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
3146                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
3147                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
3148                 if (tpa_flags & BNXT_FLAG_GRO)
3149                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
3150
3151                 req.flags = cpu_to_le32(flags);
3152
3153                 req.enables =
3154                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
3155                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
3156                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
3157
3158                 /* Number of segs are log2 units, and first packet is not
3159                  * included as part of this units.
3160                  */
3161                 if (mss <= BNXT_RX_PAGE_SIZE) {
3162                         n = BNXT_RX_PAGE_SIZE / mss;
3163                         nsegs = (MAX_SKB_FRAGS - 1) * n;
3164                 } else {
3165                         n = mss / BNXT_RX_PAGE_SIZE;
3166                         if (mss & (BNXT_RX_PAGE_SIZE - 1))
3167                                 n++;
3168                         nsegs = (MAX_SKB_FRAGS - n) / n;
3169                 }
3170
3171                 segs = ilog2(nsegs);
3172                 req.max_agg_segs = cpu_to_le16(segs);
3173                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
3174
3175                 req.min_agg_len = cpu_to_le32(512);
3176         }
3177         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3178
3179         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3180 }
3181
3182 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
3183 {
3184         u32 i, j, max_rings;
3185         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3186         struct hwrm_vnic_rss_cfg_input req = {0};
3187
3188         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
3189                 return 0;
3190
3191         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
3192         if (set_rss) {
3193                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
3194                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
3195                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
3196                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
3197
3198                 req.hash_type = cpu_to_le32(vnic->hash_type);
3199
3200                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3201                         max_rings = bp->rx_nr_rings;
3202                 else
3203                         max_rings = 1;
3204
3205                 /* Fill the RSS indirection table with ring group ids */
3206                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3207                         if (j == max_rings)
3208                                 j = 0;
3209                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3210                 }
3211
3212                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3213                 req.hash_key_tbl_addr =
3214                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3215         }
3216         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3217         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3218 }
3219
3220 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3221 {
3222         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3223         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3224
3225         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3226         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3227                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3228                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3229         req.enables =
3230                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3231                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3232         /* thresholds not implemented in firmware yet */
3233         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3234         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3235         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3236         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3237 }
3238
3239 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3240 {
3241         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3242
3243         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3244         req.rss_cos_lb_ctx_id =
3245                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3246
3247         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3248         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3249 }
3250
3251 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3252 {
3253         int i;
3254
3255         for (i = 0; i < bp->nr_vnics; i++) {
3256                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3257
3258                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3259                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3260         }
3261         bp->rsscos_nr_ctxs = 0;
3262 }
3263
3264 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3265 {
3266         int rc;
3267         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3268         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3269                                                 bp->hwrm_cmd_resp_addr;
3270
3271         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3272                                -1);
3273
3274         mutex_lock(&bp->hwrm_cmd_lock);
3275         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3276         if (!rc)
3277                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3278                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3279         mutex_unlock(&bp->hwrm_cmd_lock);
3280
3281         return rc;
3282 }
3283
3284 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3285 {
3286         unsigned int ring = 0, grp_idx;
3287         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3288         struct hwrm_vnic_cfg_input req = {0};
3289         u16 def_vlan = 0;
3290
3291         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3292         /* Only RSS support for now TBD: COS & LB */
3293         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3294                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3295         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3296         req.cos_rule = cpu_to_le16(0xffff);
3297         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3298                 ring = 0;
3299         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3300                 ring = vnic_id - 1;
3301
3302         grp_idx = bp->rx_ring[ring].bnapi->index;
3303         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3304         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3305
3306         req.lb_rule = cpu_to_le16(0xffff);
3307         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3308                               VLAN_HLEN);
3309
3310 #ifdef CONFIG_BNXT_SRIOV
3311         if (BNXT_VF(bp))
3312                 def_vlan = bp->vf.vlan;
3313 #endif
3314         if ((bp->flags & BNXT_FLAG_STRIP_VLAN) || def_vlan)
3315                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3316
3317         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3318 }
3319
3320 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3321 {
3322         u32 rc = 0;
3323
3324         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3325                 struct hwrm_vnic_free_input req = {0};
3326
3327                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3328                 req.vnic_id =
3329                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3330
3331                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3332                 if (rc)
3333                         return rc;
3334                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3335         }
3336         return rc;
3337 }
3338
3339 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3340 {
3341         u16 i;
3342
3343         for (i = 0; i < bp->nr_vnics; i++)
3344                 bnxt_hwrm_vnic_free_one(bp, i);
3345 }
3346
3347 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3348                                 unsigned int start_rx_ring_idx,
3349                                 unsigned int nr_rings)
3350 {
3351         int rc = 0;
3352         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3353         struct hwrm_vnic_alloc_input req = {0};
3354         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3355
3356         /* map ring groups to this vnic */
3357         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3358                 grp_idx = bp->rx_ring[i].bnapi->index;
3359                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3360                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3361                                    j, nr_rings);
3362                         break;
3363                 }
3364                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3365                                         bp->grp_info[grp_idx].fw_grp_id;
3366         }
3367
3368         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3369         if (vnic_id == 0)
3370                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3371
3372         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3373
3374         mutex_lock(&bp->hwrm_cmd_lock);
3375         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3376         if (!rc)
3377                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3378         mutex_unlock(&bp->hwrm_cmd_lock);
3379         return rc;
3380 }
3381
3382 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3383 {
3384         u16 i;
3385         u32 rc = 0;
3386
3387         mutex_lock(&bp->hwrm_cmd_lock);
3388         for (i = 0; i < bp->rx_nr_rings; i++) {
3389                 struct hwrm_ring_grp_alloc_input req = {0};
3390                 struct hwrm_ring_grp_alloc_output *resp =
3391                                         bp->hwrm_cmd_resp_addr;
3392                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3393
3394                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3395
3396                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3397                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3398                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3399                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3400
3401                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3402                                         HWRM_CMD_TIMEOUT);
3403                 if (rc)
3404                         break;
3405
3406                 bp->grp_info[grp_idx].fw_grp_id =
3407                         le32_to_cpu(resp->ring_group_id);
3408         }
3409         mutex_unlock(&bp->hwrm_cmd_lock);
3410         return rc;
3411 }
3412
3413 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3414 {
3415         u16 i;
3416         u32 rc = 0;
3417         struct hwrm_ring_grp_free_input req = {0};
3418
3419         if (!bp->grp_info)
3420                 return 0;
3421
3422         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3423
3424         mutex_lock(&bp->hwrm_cmd_lock);
3425         for (i = 0; i < bp->cp_nr_rings; i++) {
3426                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3427                         continue;
3428                 req.ring_group_id =
3429                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3430
3431                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3432                                         HWRM_CMD_TIMEOUT);
3433                 if (rc)
3434                         break;
3435                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3436         }
3437         mutex_unlock(&bp->hwrm_cmd_lock);
3438         return rc;
3439 }
3440
3441 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3442                                     struct bnxt_ring_struct *ring,
3443                                     u32 ring_type, u32 map_index,
3444                                     u32 stats_ctx_id)
3445 {
3446         int rc = 0, err = 0;
3447         struct hwrm_ring_alloc_input req = {0};
3448         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3449         u16 ring_id;
3450
3451         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3452
3453         req.enables = 0;
3454         if (ring->nr_pages > 1) {
3455                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3456                 /* Page size is in log2 units */
3457                 req.page_size = BNXT_PAGE_SHIFT;
3458                 req.page_tbl_depth = 1;
3459         } else {
3460                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3461         }
3462         req.fbo = 0;
3463         /* Association of ring index with doorbell index and MSIX number */
3464         req.logical_id = cpu_to_le16(map_index);
3465
3466         switch (ring_type) {
3467         case HWRM_RING_ALLOC_TX:
3468                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3469                 /* Association of transmit ring with completion ring */
3470                 req.cmpl_ring_id =
3471                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3472                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3473                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3474                 req.queue_id = cpu_to_le16(ring->queue_id);
3475                 break;
3476         case HWRM_RING_ALLOC_RX:
3477                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3478                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3479                 break;
3480         case HWRM_RING_ALLOC_AGG:
3481                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3482                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3483                 break;
3484         case HWRM_RING_ALLOC_CMPL:
3485                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3486                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3487                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3488                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3489                 break;
3490         default:
3491                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3492                            ring_type);
3493                 return -1;
3494         }
3495
3496         mutex_lock(&bp->hwrm_cmd_lock);
3497         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3498         err = le16_to_cpu(resp->error_code);
3499         ring_id = le16_to_cpu(resp->ring_id);
3500         mutex_unlock(&bp->hwrm_cmd_lock);
3501
3502         if (rc || err) {
3503                 switch (ring_type) {
3504                 case RING_FREE_REQ_RING_TYPE_CMPL:
3505                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3506                                    rc, err);
3507                         return -1;
3508
3509                 case RING_FREE_REQ_RING_TYPE_RX:
3510                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3511                                    rc, err);
3512                         return -1;
3513
3514                 case RING_FREE_REQ_RING_TYPE_TX:
3515                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3516                                    rc, err);
3517                         return -1;
3518
3519                 default:
3520                         netdev_err(bp->dev, "Invalid ring\n");
3521                         return -1;
3522                 }
3523         }
3524         ring->fw_ring_id = ring_id;
3525         return rc;
3526 }
3527
3528 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3529 {
3530         int i, rc = 0;
3531
3532         for (i = 0; i < bp->cp_nr_rings; i++) {
3533                 struct bnxt_napi *bnapi = bp->bnapi[i];
3534                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3535                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3536
3537                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3538                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3539                                               INVALID_STATS_CTX_ID);
3540                 if (rc)
3541                         goto err_out;
3542                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3543                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3544         }
3545
3546         for (i = 0; i < bp->tx_nr_rings; i++) {
3547                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3548                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3549                 u32 map_idx = txr->bnapi->index;
3550                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3551
3552                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3553                                               map_idx, fw_stats_ctx);
3554                 if (rc)
3555                         goto err_out;
3556                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3557         }
3558
3559         for (i = 0; i < bp->rx_nr_rings; i++) {
3560                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3561                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3562                 u32 map_idx = rxr->bnapi->index;
3563
3564                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3565                                               map_idx, INVALID_STATS_CTX_ID);
3566                 if (rc)
3567                         goto err_out;
3568                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3569                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3570                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3571         }
3572
3573         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3574                 for (i = 0; i < bp->rx_nr_rings; i++) {
3575                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3576                         struct bnxt_ring_struct *ring =
3577                                                 &rxr->rx_agg_ring_struct;
3578                         u32 grp_idx = rxr->bnapi->index;
3579                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3580
3581                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3582                                                       HWRM_RING_ALLOC_AGG,
3583                                                       map_idx,
3584                                                       INVALID_STATS_CTX_ID);
3585                         if (rc)
3586                                 goto err_out;
3587
3588                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3589                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3590                                rxr->rx_agg_doorbell);
3591                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3592                 }
3593         }
3594 err_out:
3595         return rc;
3596 }
3597
3598 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3599                                    struct bnxt_ring_struct *ring,
3600                                    u32 ring_type, int cmpl_ring_id)
3601 {
3602         int rc;
3603         struct hwrm_ring_free_input req = {0};
3604         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3605         u16 error_code;
3606
3607         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, cmpl_ring_id, -1);
3608         req.ring_type = ring_type;
3609         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3610
3611         mutex_lock(&bp->hwrm_cmd_lock);
3612         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3613         error_code = le16_to_cpu(resp->error_code);
3614         mutex_unlock(&bp->hwrm_cmd_lock);
3615
3616         if (rc || error_code) {
3617                 switch (ring_type) {
3618                 case RING_FREE_REQ_RING_TYPE_CMPL:
3619                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3620                                    rc);
3621                         return rc;
3622                 case RING_FREE_REQ_RING_TYPE_RX:
3623                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3624                                    rc);
3625                         return rc;
3626                 case RING_FREE_REQ_RING_TYPE_TX:
3627                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3628                                    rc);
3629                         return rc;
3630                 default:
3631                         netdev_err(bp->dev, "Invalid ring\n");
3632                         return -1;
3633                 }
3634         }
3635         return 0;
3636 }
3637
3638 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3639 {
3640         int i;
3641
3642         if (!bp->bnapi)
3643                 return;
3644
3645         for (i = 0; i < bp->tx_nr_rings; i++) {
3646                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3647                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3648                 u32 grp_idx = txr->bnapi->index;
3649                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3650
3651                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3652                         hwrm_ring_free_send_msg(bp, ring,
3653                                                 RING_FREE_REQ_RING_TYPE_TX,
3654                                                 close_path ? cmpl_ring_id :
3655                                                 INVALID_HW_RING_ID);
3656                         ring->fw_ring_id = INVALID_HW_RING_ID;
3657                 }
3658         }
3659
3660         for (i = 0; i < bp->rx_nr_rings; i++) {
3661                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3662                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3663                 u32 grp_idx = rxr->bnapi->index;
3664                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3665
3666                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3667                         hwrm_ring_free_send_msg(bp, ring,
3668                                                 RING_FREE_REQ_RING_TYPE_RX,
3669                                                 close_path ? cmpl_ring_id :
3670                                                 INVALID_HW_RING_ID);
3671                         ring->fw_ring_id = INVALID_HW_RING_ID;
3672                         bp->grp_info[grp_idx].rx_fw_ring_id =
3673                                 INVALID_HW_RING_ID;
3674                 }
3675         }
3676
3677         for (i = 0; i < bp->rx_nr_rings; i++) {
3678                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3679                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3680                 u32 grp_idx = rxr->bnapi->index;
3681                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3682
3683                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3684                         hwrm_ring_free_send_msg(bp, ring,
3685                                                 RING_FREE_REQ_RING_TYPE_RX,
3686                                                 close_path ? cmpl_ring_id :
3687                                                 INVALID_HW_RING_ID);
3688                         ring->fw_ring_id = INVALID_HW_RING_ID;
3689                         bp->grp_info[grp_idx].agg_fw_ring_id =
3690                                 INVALID_HW_RING_ID;
3691                 }
3692         }
3693
3694         for (i = 0; i < bp->cp_nr_rings; i++) {
3695                 struct bnxt_napi *bnapi = bp->bnapi[i];
3696                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3697                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3698
3699                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3700                         hwrm_ring_free_send_msg(bp, ring,
3701                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3702                                                 INVALID_HW_RING_ID);
3703                         ring->fw_ring_id = INVALID_HW_RING_ID;
3704                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3705                 }
3706         }
3707 }
3708
3709 static void bnxt_hwrm_set_coal_params(struct bnxt *bp, u32 max_bufs,
3710         u32 buf_tmrs, u16 flags,
3711         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input *req)
3712 {
3713         req->flags = cpu_to_le16(flags);
3714         req->num_cmpl_dma_aggr = cpu_to_le16((u16)max_bufs);
3715         req->num_cmpl_dma_aggr_during_int = cpu_to_le16(max_bufs >> 16);
3716         req->cmpl_aggr_dma_tmr = cpu_to_le16((u16)buf_tmrs);
3717         req->cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmrs >> 16);
3718         /* Minimum time between 2 interrupts set to buf_tmr x 2 */
3719         req->int_lat_tmr_min = cpu_to_le16((u16)buf_tmrs * 2);
3720         req->int_lat_tmr_max = cpu_to_le16((u16)buf_tmrs * 4);
3721         req->num_cmpl_aggr_int = cpu_to_le16((u16)max_bufs * 4);
3722 }
3723
3724 int bnxt_hwrm_set_coal(struct bnxt *bp)
3725 {
3726         int i, rc = 0;
3727         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req_rx = {0},
3728                                                            req_tx = {0}, *req;
3729         u16 max_buf, max_buf_irq;
3730         u16 buf_tmr, buf_tmr_irq;
3731         u32 flags;
3732
3733         bnxt_hwrm_cmd_hdr_init(bp, &req_rx,
3734                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3735         bnxt_hwrm_cmd_hdr_init(bp, &req_tx,
3736                                HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS, -1, -1);
3737
3738         /* Each rx completion (2 records) should be DMAed immediately.
3739          * DMA 1/4 of the completion buffers at a time.
3740          */
3741         max_buf = min_t(u16, bp->rx_coal_bufs / 4, 2);
3742         /* max_buf must not be zero */
3743         max_buf = clamp_t(u16, max_buf, 1, 63);
3744         max_buf_irq = clamp_t(u16, bp->rx_coal_bufs_irq, 1, 63);
3745         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks);
3746         /* buf timer set to 1/4 of interrupt timer */
3747         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3748         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->rx_coal_ticks_irq);
3749         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3750
3751         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3752
3753         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3754          * if coal_ticks is less than 25 us.
3755          */
3756         if (bp->rx_coal_ticks < 25)
3757                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3758
3759         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3760                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_rx);
3761
3762         /* max_buf must not be zero */
3763         max_buf = clamp_t(u16, bp->tx_coal_bufs, 1, 63);
3764         max_buf_irq = clamp_t(u16, bp->tx_coal_bufs_irq, 1, 63);
3765         buf_tmr = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks);
3766         /* buf timer set to 1/4 of interrupt timer */
3767         buf_tmr = max_t(u16, buf_tmr / 4, 1);
3768         buf_tmr_irq = BNXT_USEC_TO_COAL_TIMER(bp->tx_coal_ticks_irq);
3769         buf_tmr_irq = max_t(u16, buf_tmr_irq, 1);
3770
3771         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3772         bnxt_hwrm_set_coal_params(bp, max_buf_irq << 16 | max_buf,
3773                                   buf_tmr_irq << 16 | buf_tmr, flags, &req_tx);
3774
3775         mutex_lock(&bp->hwrm_cmd_lock);
3776         for (i = 0; i < bp->cp_nr_rings; i++) {
3777                 struct bnxt_napi *bnapi = bp->bnapi[i];
3778
3779                 req = &req_rx;
3780                 if (!bnapi->rx_ring)
3781                         req = &req_tx;
3782                 req->ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3783
3784                 rc = _hwrm_send_message(bp, req, sizeof(*req),
3785                                         HWRM_CMD_TIMEOUT);
3786                 if (rc)
3787                         break;
3788         }
3789         mutex_unlock(&bp->hwrm_cmd_lock);
3790         return rc;
3791 }
3792
3793 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3794 {
3795         int rc = 0, i;
3796         struct hwrm_stat_ctx_free_input req = {0};
3797
3798         if (!bp->bnapi)
3799                 return 0;
3800
3801         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3802
3803         mutex_lock(&bp->hwrm_cmd_lock);
3804         for (i = 0; i < bp->cp_nr_rings; i++) {
3805                 struct bnxt_napi *bnapi = bp->bnapi[i];
3806                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3807
3808                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3809                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3810
3811                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3812                                                 HWRM_CMD_TIMEOUT);
3813                         if (rc)
3814                                 break;
3815
3816                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3817                 }
3818         }
3819         mutex_unlock(&bp->hwrm_cmd_lock);
3820         return rc;
3821 }
3822
3823 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3824 {
3825         int rc = 0, i;
3826         struct hwrm_stat_ctx_alloc_input req = {0};
3827         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3828
3829         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3830
3831         req.update_period_ms = cpu_to_le32(1000);
3832
3833         mutex_lock(&bp->hwrm_cmd_lock);
3834         for (i = 0; i < bp->cp_nr_rings; i++) {
3835                 struct bnxt_napi *bnapi = bp->bnapi[i];
3836                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3837
3838                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3839
3840                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3841                                         HWRM_CMD_TIMEOUT);
3842                 if (rc)
3843                         break;
3844
3845                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3846
3847                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3848         }
3849         mutex_unlock(&bp->hwrm_cmd_lock);
3850         return 0;
3851 }
3852
3853 static int bnxt_hwrm_func_qcfg(struct bnxt *bp)
3854 {
3855         struct hwrm_func_qcfg_input req = {0};
3856         struct hwrm_func_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
3857         int rc;
3858
3859         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCFG, -1, -1);
3860         req.fid = cpu_to_le16(0xffff);
3861         mutex_lock(&bp->hwrm_cmd_lock);
3862         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3863         if (rc)
3864                 goto func_qcfg_exit;
3865
3866 #ifdef CONFIG_BNXT_SRIOV
3867         if (BNXT_VF(bp)) {
3868                 struct bnxt_vf_info *vf = &bp->vf;
3869
3870                 vf->vlan = le16_to_cpu(resp->vlan) & VLAN_VID_MASK;
3871         }
3872 #endif
3873         switch (resp->port_partition_type) {
3874         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0:
3875         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5:
3876         case FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0:
3877                 bp->port_partition_type = resp->port_partition_type;
3878                 break;
3879         }
3880
3881 func_qcfg_exit:
3882         mutex_unlock(&bp->hwrm_cmd_lock);
3883         return rc;
3884 }
3885
3886 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3887 {
3888         int rc = 0;
3889         struct hwrm_func_qcaps_input req = {0};
3890         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3891
3892         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3893         req.fid = cpu_to_le16(0xffff);
3894
3895         mutex_lock(&bp->hwrm_cmd_lock);
3896         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3897         if (rc)
3898                 goto hwrm_func_qcaps_exit;
3899
3900         if (BNXT_PF(bp)) {
3901                 struct bnxt_pf_info *pf = &bp->pf;
3902
3903                 pf->fw_fid = le16_to_cpu(resp->fid);
3904                 pf->port_id = le16_to_cpu(resp->port_id);
3905                 memcpy(pf->mac_addr, resp->mac_address, ETH_ALEN);
3906                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3907                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3908                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3909                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3910                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3911                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3912                 if (!pf->max_hw_ring_grps)
3913                         pf->max_hw_ring_grps = pf->max_tx_rings;
3914                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3915                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3916                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3917                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3918                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3919                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3920                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3921                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3922                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3923                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3924                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3925         } else {
3926 #ifdef CONFIG_BNXT_SRIOV
3927                 struct bnxt_vf_info *vf = &bp->vf;
3928
3929                 vf->fw_fid = le16_to_cpu(resp->fid);
3930                 memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);
3931                 if (is_valid_ether_addr(vf->mac_addr))
3932                         /* overwrite netdev dev_adr with admin VF MAC */
3933                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3934                 else
3935                         random_ether_addr(bp->dev->dev_addr);
3936
3937                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3938                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3939                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3940                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3941                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3942                 if (!vf->max_hw_ring_grps)
3943                         vf->max_hw_ring_grps = vf->max_tx_rings;
3944                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3945                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3946                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3947 #endif
3948         }
3949
3950         bp->tx_push_thresh = 0;
3951         if (resp->flags &
3952             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3953                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3954
3955 hwrm_func_qcaps_exit:
3956         mutex_unlock(&bp->hwrm_cmd_lock);
3957         return rc;
3958 }
3959
3960 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3961 {
3962         struct hwrm_func_reset_input req = {0};
3963
3964         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3965         req.enables = 0;
3966
3967         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3968 }
3969
3970 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3971 {
3972         int rc = 0;
3973         struct hwrm_queue_qportcfg_input req = {0};
3974         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3975         u8 i, *qptr;
3976
3977         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3978
3979         mutex_lock(&bp->hwrm_cmd_lock);
3980         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3981         if (rc)
3982                 goto qportcfg_exit;
3983
3984         if (!resp->max_configurable_queues) {
3985                 rc = -EINVAL;
3986                 goto qportcfg_exit;
3987         }
3988         bp->max_tc = resp->max_configurable_queues;
3989         if (bp->max_tc > BNXT_MAX_QUEUE)
3990                 bp->max_tc = BNXT_MAX_QUEUE;
3991
3992         qptr = &resp->queue_id0;
3993         for (i = 0; i < bp->max_tc; i++) {
3994                 bp->q_info[i].queue_id = *qptr++;
3995                 bp->q_info[i].queue_profile = *qptr++;
3996         }
3997
3998 qportcfg_exit:
3999         mutex_unlock(&bp->hwrm_cmd_lock);
4000         return rc;
4001 }
4002
4003 static int bnxt_hwrm_ver_get(struct bnxt *bp)
4004 {
4005         int rc;
4006         struct hwrm_ver_get_input req = {0};
4007         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
4008
4009         bp->hwrm_max_req_len = HWRM_MAX_REQ_LEN;
4010         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
4011         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
4012         req.hwrm_intf_min = HWRM_VERSION_MINOR;
4013         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
4014         mutex_lock(&bp->hwrm_cmd_lock);
4015         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4016         if (rc)
4017                 goto hwrm_ver_get_exit;
4018
4019         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
4020
4021         bp->hwrm_spec_code = resp->hwrm_intf_maj << 16 |
4022                              resp->hwrm_intf_min << 8 | resp->hwrm_intf_upd;
4023         if (resp->hwrm_intf_maj < 1) {
4024                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
4025                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
4026                             resp->hwrm_intf_upd);
4027                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
4028         }
4029         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "%d.%d.%d/%d.%d.%d",
4030                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
4031                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
4032
4033         bp->hwrm_cmd_timeout = le16_to_cpu(resp->def_req_timeout);
4034         if (!bp->hwrm_cmd_timeout)
4035                 bp->hwrm_cmd_timeout = DFLT_HWRM_CMD_TIMEOUT;
4036
4037         if (resp->hwrm_intf_maj >= 1)
4038                 bp->hwrm_max_req_len = le16_to_cpu(resp->max_req_win_len);
4039
4040         bp->chip_num = le16_to_cpu(resp->chip_num);
4041
4042 hwrm_ver_get_exit:
4043         mutex_unlock(&bp->hwrm_cmd_lock);
4044         return rc;
4045 }
4046
4047 static int bnxt_hwrm_port_qstats(struct bnxt *bp)
4048 {
4049         int rc;
4050         struct bnxt_pf_info *pf = &bp->pf;
4051         struct hwrm_port_qstats_input req = {0};
4052
4053         if (!(bp->flags & BNXT_FLAG_PORT_STATS))
4054                 return 0;
4055
4056         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_QSTATS, -1, -1);
4057         req.port_id = cpu_to_le16(pf->port_id);
4058         req.tx_stat_host_addr = cpu_to_le64(bp->hw_tx_port_stats_map);
4059         req.rx_stat_host_addr = cpu_to_le64(bp->hw_rx_port_stats_map);
4060         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4061         return rc;
4062 }
4063
4064 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
4065 {
4066         if (bp->vxlan_port_cnt) {
4067                 bnxt_hwrm_tunnel_dst_port_free(
4068                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
4069         }
4070         bp->vxlan_port_cnt = 0;
4071         if (bp->nge_port_cnt) {
4072                 bnxt_hwrm_tunnel_dst_port_free(
4073                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
4074         }
4075         bp->nge_port_cnt = 0;
4076 }
4077
4078 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
4079 {
4080         int rc, i;
4081         u32 tpa_flags = 0;
4082
4083         if (set_tpa)
4084                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
4085         for (i = 0; i < bp->nr_vnics; i++) {
4086                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
4087                 if (rc) {
4088                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
4089                                    rc, i);
4090                         return rc;
4091                 }
4092         }
4093         return 0;
4094 }
4095
4096 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
4097 {
4098         int i;
4099
4100         for (i = 0; i < bp->nr_vnics; i++)
4101                 bnxt_hwrm_vnic_set_rss(bp, i, false);
4102 }
4103
4104 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
4105                                     bool irq_re_init)
4106 {
4107         if (bp->vnic_info) {
4108                 bnxt_hwrm_clear_vnic_filter(bp);
4109                 /* clear all RSS setting before free vnic ctx */
4110                 bnxt_hwrm_clear_vnic_rss(bp);
4111                 bnxt_hwrm_vnic_ctx_free(bp);
4112                 /* before free the vnic, undo the vnic tpa settings */
4113                 if (bp->flags & BNXT_FLAG_TPA)
4114                         bnxt_set_tpa(bp, false);
4115                 bnxt_hwrm_vnic_free(bp);
4116         }
4117         bnxt_hwrm_ring_free(bp, close_path);
4118         bnxt_hwrm_ring_grp_free(bp);
4119         if (irq_re_init) {
4120                 bnxt_hwrm_stat_ctx_free(bp);
4121                 bnxt_hwrm_free_tunnel_ports(bp);
4122         }
4123 }
4124
4125 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
4126 {
4127         int rc;
4128
4129         /* allocate context for vnic */
4130         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
4131         if (rc) {
4132                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4133                            vnic_id, rc);
4134                 goto vnic_setup_err;
4135         }
4136         bp->rsscos_nr_ctxs++;
4137
4138         /* configure default vnic, ring grp */
4139         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
4140         if (rc) {
4141                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
4142                            vnic_id, rc);
4143                 goto vnic_setup_err;
4144         }
4145
4146         /* Enable RSS hashing on vnic */
4147         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
4148         if (rc) {
4149                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
4150                            vnic_id, rc);
4151                 goto vnic_setup_err;
4152         }
4153
4154         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
4155                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
4156                 if (rc) {
4157                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
4158                                    vnic_id, rc);
4159                 }
4160         }
4161
4162 vnic_setup_err:
4163         return rc;
4164 }
4165
4166 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
4167 {
4168 #ifdef CONFIG_RFS_ACCEL
4169         int i, rc = 0;
4170
4171         for (i = 0; i < bp->rx_nr_rings; i++) {
4172                 u16 vnic_id = i + 1;
4173                 u16 ring_id = i;
4174
4175                 if (vnic_id >= bp->nr_vnics)
4176                         break;
4177
4178                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
4179                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
4180                 if (rc) {
4181                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
4182                                    vnic_id, rc);
4183                         break;
4184                 }
4185                 rc = bnxt_setup_vnic(bp, vnic_id);
4186                 if (rc)
4187                         break;
4188         }
4189         return rc;
4190 #else
4191         return 0;
4192 #endif
4193 }
4194
4195 static int bnxt_cfg_rx_mode(struct bnxt *);
4196 static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
4197
4198 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
4199 {
4200         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4201         int rc = 0;
4202
4203         if (irq_re_init) {
4204                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
4205                 if (rc) {
4206                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
4207                                    rc);
4208                         goto err_out;
4209                 }
4210         }
4211
4212         rc = bnxt_hwrm_ring_alloc(bp);
4213         if (rc) {
4214                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
4215                 goto err_out;
4216         }
4217
4218         rc = bnxt_hwrm_ring_grp_alloc(bp);
4219         if (rc) {
4220                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
4221                 goto err_out;
4222         }
4223
4224         /* default vnic 0 */
4225         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
4226         if (rc) {
4227                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
4228                 goto err_out;
4229         }
4230
4231         rc = bnxt_setup_vnic(bp, 0);
4232         if (rc)
4233                 goto err_out;
4234
4235         if (bp->flags & BNXT_FLAG_RFS) {
4236                 rc = bnxt_alloc_rfs_vnics(bp);
4237                 if (rc)
4238                         goto err_out;
4239         }
4240
4241         if (bp->flags & BNXT_FLAG_TPA) {
4242                 rc = bnxt_set_tpa(bp, true);
4243                 if (rc)
4244                         goto err_out;
4245         }
4246
4247         if (BNXT_VF(bp))
4248                 bnxt_update_vf_mac(bp);
4249
4250         /* Filter for default vnic 0 */
4251         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
4252         if (rc) {
4253                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
4254                 goto err_out;
4255         }
4256         vnic->uc_filter_count = 1;
4257
4258         vnic->rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
4259
4260         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4261                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4262
4263         if (bp->dev->flags & IFF_ALLMULTI) {
4264                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4265                 vnic->mc_list_count = 0;
4266         } else {
4267                 u32 mask = 0;
4268
4269                 bnxt_mc_list_updated(bp, &mask);
4270                 vnic->rx_mask |= mask;
4271         }
4272
4273         rc = bnxt_cfg_rx_mode(bp);
4274         if (rc)
4275                 goto err_out;
4276
4277         rc = bnxt_hwrm_set_coal(bp);
4278         if (rc)
4279                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
4280                             rc);
4281
4282         if (BNXT_VF(bp)) {
4283                 bnxt_hwrm_func_qcfg(bp);
4284                 netdev_update_features(bp->dev);
4285         }
4286
4287         return 0;
4288
4289 err_out:
4290         bnxt_hwrm_resource_free(bp, 0, true);
4291
4292         return rc;
4293 }
4294
4295 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
4296 {
4297         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
4298         return 0;
4299 }
4300
4301 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
4302 {
4303         bnxt_init_rx_rings(bp);
4304         bnxt_init_tx_rings(bp);
4305         bnxt_init_ring_grps(bp, irq_re_init);
4306         bnxt_init_vnics(bp);
4307
4308         return bnxt_init_chip(bp, irq_re_init);
4309 }
4310
4311 static void bnxt_disable_int(struct bnxt *bp)
4312 {
4313         int i;
4314
4315         if (!bp->bnapi)
4316                 return;
4317
4318         for (i = 0; i < bp->cp_nr_rings; i++) {
4319                 struct bnxt_napi *bnapi = bp->bnapi[i];
4320                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4321
4322                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4323         }
4324 }
4325
4326 static void bnxt_enable_int(struct bnxt *bp)
4327 {
4328         int i;
4329
4330         atomic_set(&bp->intr_sem, 0);
4331         for (i = 0; i < bp->cp_nr_rings; i++) {
4332                 struct bnxt_napi *bnapi = bp->bnapi[i];
4333                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4334
4335                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4336         }
4337 }
4338
4339 static int bnxt_set_real_num_queues(struct bnxt *bp)
4340 {
4341         int rc;
4342         struct net_device *dev = bp->dev;
4343
4344         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4345         if (rc)
4346                 return rc;
4347
4348         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4349         if (rc)
4350                 return rc;
4351
4352 #ifdef CONFIG_RFS_ACCEL
4353         if (bp->flags & BNXT_FLAG_RFS)
4354                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4355 #endif
4356
4357         return rc;
4358 }
4359
4360 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4361                            bool shared)
4362 {
4363         int _rx = *rx, _tx = *tx;
4364
4365         if (shared) {
4366                 *rx = min_t(int, _rx, max);
4367                 *tx = min_t(int, _tx, max);
4368         } else {
4369                 if (max < 2)
4370                         return -ENOMEM;
4371
4372                 while (_rx + _tx > max) {
4373                         if (_rx > _tx && _rx > 1)
4374                                 _rx--;
4375                         else if (_tx > 1)
4376                                 _tx--;
4377                 }
4378                 *rx = _rx;
4379                 *tx = _tx;
4380         }
4381         return 0;
4382 }
4383
4384 static int bnxt_setup_msix(struct bnxt *bp)
4385 {
4386         struct msix_entry *msix_ent;
4387         struct net_device *dev = bp->dev;
4388         int i, total_vecs, rc = 0, min = 1;
4389         const int len = sizeof(bp->irq_tbl[0].name);
4390
4391         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4392         total_vecs = bp->cp_nr_rings;
4393
4394         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4395         if (!msix_ent)
4396                 return -ENOMEM;
4397
4398         for (i = 0; i < total_vecs; i++) {
4399                 msix_ent[i].entry = i;
4400                 msix_ent[i].vector = 0;
4401         }
4402
4403         if (!(bp->flags & BNXT_FLAG_SHARED_RINGS))
4404                 min = 2;
4405
4406         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, min, total_vecs);
4407         if (total_vecs < 0) {
4408                 rc = -ENODEV;
4409                 goto msix_setup_exit;
4410         }
4411
4412         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4413         if (bp->irq_tbl) {
4414                 int tcs;
4415
4416                 /* Trim rings based upon num of vectors allocated */
4417                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4418                                      total_vecs, min == 1);
4419                 if (rc)
4420                         goto msix_setup_exit;
4421
4422                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4423                 tcs = netdev_get_num_tc(dev);
4424                 if (tcs > 1) {
4425                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4426                         if (bp->tx_nr_rings_per_tc == 0) {
4427                                 netdev_reset_tc(dev);
4428                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4429                         } else {
4430                                 int i, off, count;
4431
4432                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4433                                 for (i = 0; i < tcs; i++) {
4434                                         count = bp->tx_nr_rings_per_tc;
4435                                         off = i * count;
4436                                         netdev_set_tc_queue(dev, i, count, off);
4437                                 }
4438                         }
4439                 }
4440                 bp->cp_nr_rings = total_vecs;
4441
4442                 for (i = 0; i < bp->cp_nr_rings; i++) {
4443                         char *attr;
4444
4445                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4446                         if (bp->flags & BNXT_FLAG_SHARED_RINGS)
4447                                 attr = "TxRx";
4448                         else if (i < bp->rx_nr_rings)
4449                                 attr = "rx";
4450                         else
4451                                 attr = "tx";
4452
4453                         snprintf(bp->irq_tbl[i].name, len,
4454                                  "%s-%s-%d", dev->name, attr, i);
4455                         bp->irq_tbl[i].handler = bnxt_msix;
4456                 }
4457                 rc = bnxt_set_real_num_queues(bp);
4458                 if (rc)
4459                         goto msix_setup_exit;
4460         } else {
4461                 rc = -ENOMEM;
4462                 goto msix_setup_exit;
4463         }
4464         bp->flags |= BNXT_FLAG_USING_MSIX;
4465         kfree(msix_ent);
4466         return 0;
4467
4468 msix_setup_exit:
4469         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4470         pci_disable_msix(bp->pdev);
4471         kfree(msix_ent);
4472         return rc;
4473 }
4474
4475 static int bnxt_setup_inta(struct bnxt *bp)
4476 {
4477         int rc;
4478         const int len = sizeof(bp->irq_tbl[0].name);
4479
4480         if (netdev_get_num_tc(bp->dev))
4481                 netdev_reset_tc(bp->dev);
4482
4483         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4484         if (!bp->irq_tbl) {
4485                 rc = -ENOMEM;
4486                 return rc;
4487         }
4488         bp->rx_nr_rings = 1;
4489         bp->tx_nr_rings = 1;
4490         bp->cp_nr_rings = 1;
4491         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4492         bp->flags |= BNXT_FLAG_SHARED_RINGS;
4493         bp->irq_tbl[0].vector = bp->pdev->irq;
4494         snprintf(bp->irq_tbl[0].name, len,
4495                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4496         bp->irq_tbl[0].handler = bnxt_inta;
4497         rc = bnxt_set_real_num_queues(bp);
4498         return rc;
4499 }
4500
4501 static int bnxt_setup_int_mode(struct bnxt *bp)
4502 {
4503         int rc = 0;
4504
4505         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4506                 rc = bnxt_setup_msix(bp);
4507
4508         if (!(bp->flags & BNXT_FLAG_USING_MSIX) && BNXT_PF(bp)) {
4509                 /* fallback to INTA */
4510                 rc = bnxt_setup_inta(bp);
4511         }
4512         return rc;
4513 }
4514
4515 static void bnxt_free_irq(struct bnxt *bp)
4516 {
4517         struct bnxt_irq *irq;
4518         int i;
4519
4520 #ifdef CONFIG_RFS_ACCEL
4521         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4522         bp->dev->rx_cpu_rmap = NULL;
4523 #endif
4524         if (!bp->irq_tbl)
4525                 return;
4526
4527         for (i = 0; i < bp->cp_nr_rings; i++) {
4528                 irq = &bp->irq_tbl[i];
4529                 if (irq->requested)
4530                         free_irq(irq->vector, bp->bnapi[i]);
4531                 irq->requested = 0;
4532         }
4533         if (bp->flags & BNXT_FLAG_USING_MSIX)
4534                 pci_disable_msix(bp->pdev);
4535         kfree(bp->irq_tbl);
4536         bp->irq_tbl = NULL;
4537 }
4538
4539 static int bnxt_request_irq(struct bnxt *bp)
4540 {
4541         int i, j, rc = 0;
4542         unsigned long flags = 0;
4543 #ifdef CONFIG_RFS_ACCEL
4544         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4545 #endif
4546
4547         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4548                 flags = IRQF_SHARED;
4549
4550         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4551                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4552 #ifdef CONFIG_RFS_ACCEL
4553                 if (rmap && bp->bnapi[i]->rx_ring) {
4554                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4555                         if (rc)
4556                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4557                                             j);
4558                         j++;
4559                 }
4560 #endif
4561                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4562                                  bp->bnapi[i]);
4563                 if (rc)
4564                         break;
4565
4566                 irq->requested = 1;
4567         }
4568         return rc;
4569 }
4570
4571 static void bnxt_del_napi(struct bnxt *bp)
4572 {
4573         int i;
4574
4575         if (!bp->bnapi)
4576                 return;
4577
4578         for (i = 0; i < bp->cp_nr_rings; i++) {
4579                 struct bnxt_napi *bnapi = bp->bnapi[i];
4580
4581                 napi_hash_del(&bnapi->napi);
4582                 netif_napi_del(&bnapi->napi);
4583         }
4584 }
4585
4586 static void bnxt_init_napi(struct bnxt *bp)
4587 {
4588         int i;
4589         struct bnxt_napi *bnapi;
4590
4591         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4592                 for (i = 0; i < bp->cp_nr_rings; i++) {
4593                         bnapi = bp->bnapi[i];
4594                         netif_napi_add(bp->dev, &bnapi->napi,
4595                                        bnxt_poll, 64);
4596                 }
4597         } else {
4598                 bnapi = bp->bnapi[0];
4599                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4600         }
4601 }
4602
4603 static void bnxt_disable_napi(struct bnxt *bp)
4604 {
4605         int i;
4606
4607         if (!bp->bnapi)
4608                 return;
4609
4610         for (i = 0; i < bp->cp_nr_rings; i++) {
4611                 napi_disable(&bp->bnapi[i]->napi);
4612                 bnxt_disable_poll(bp->bnapi[i]);
4613         }
4614 }
4615
4616 static void bnxt_enable_napi(struct bnxt *bp)
4617 {
4618         int i;
4619
4620         for (i = 0; i < bp->cp_nr_rings; i++) {
4621                 bp->bnapi[i]->in_reset = false;
4622                 bnxt_enable_poll(bp->bnapi[i]);
4623                 napi_enable(&bp->bnapi[i]->napi);
4624         }
4625 }
4626
4627 static void bnxt_tx_disable(struct bnxt *bp)
4628 {
4629         int i;
4630         struct bnxt_tx_ring_info *txr;
4631         struct netdev_queue *txq;
4632
4633         if (bp->tx_ring) {
4634                 for (i = 0; i < bp->tx_nr_rings; i++) {
4635                         txr = &bp->tx_ring[i];
4636                         txq = netdev_get_tx_queue(bp->dev, i);
4637                         __netif_tx_lock(txq, smp_processor_id());
4638                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4639                         __netif_tx_unlock(txq);
4640                 }
4641         }
4642         /* Stop all TX queues */
4643         netif_tx_disable(bp->dev);
4644         netif_carrier_off(bp->dev);
4645 }
4646
4647 static void bnxt_tx_enable(struct bnxt *bp)
4648 {
4649         int i;
4650         struct bnxt_tx_ring_info *txr;
4651         struct netdev_queue *txq;
4652
4653         for (i = 0; i < bp->tx_nr_rings; i++) {
4654                 txr = &bp->tx_ring[i];
4655                 txq = netdev_get_tx_queue(bp->dev, i);
4656                 txr->dev_state = 0;
4657         }
4658         netif_tx_wake_all_queues(bp->dev);
4659         if (bp->link_info.link_up)
4660                 netif_carrier_on(bp->dev);
4661 }
4662
4663 static void bnxt_report_link(struct bnxt *bp)
4664 {
4665         if (bp->link_info.link_up) {
4666                 const char *duplex;
4667                 const char *flow_ctrl;
4668                 u16 speed;
4669
4670                 netif_carrier_on(bp->dev);
4671                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4672                         duplex = "full";
4673                 else
4674                         duplex = "half";
4675                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4676                         flow_ctrl = "ON - receive & transmit";
4677                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4678                         flow_ctrl = "ON - transmit";
4679                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4680                         flow_ctrl = "ON - receive";
4681                 else
4682                         flow_ctrl = "none";
4683                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4684                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4685                             speed, duplex, flow_ctrl);
4686                 if (bp->flags & BNXT_FLAG_EEE_CAP)
4687                         netdev_info(bp->dev, "EEE is %s\n",
4688                                     bp->eee.eee_active ? "active" :
4689                                                          "not active");
4690         } else {
4691                 netif_carrier_off(bp->dev);
4692                 netdev_err(bp->dev, "NIC Link is Down\n");
4693         }
4694 }
4695
4696 static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)
4697 {
4698         int rc = 0;
4699         struct hwrm_port_phy_qcaps_input req = {0};
4700         struct hwrm_port_phy_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
4701
4702         if (bp->hwrm_spec_code < 0x10201)
4703                 return 0;
4704
4705         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCAPS, -1, -1);
4706
4707         mutex_lock(&bp->hwrm_cmd_lock);
4708         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4709         if (rc)
4710                 goto hwrm_phy_qcaps_exit;
4711
4712         if (resp->eee_supported & PORT_PHY_QCAPS_RESP_EEE_SUPPORTED) {
4713                 struct ethtool_eee *eee = &bp->eee;
4714                 u16 fw_speeds = le16_to_cpu(resp->supported_speeds_eee_mode);
4715
4716                 bp->flags |= BNXT_FLAG_EEE_CAP;
4717                 eee->supported = _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4718                 bp->lpi_tmr_lo = le32_to_cpu(resp->tx_lpi_timer_low) &
4719                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK;
4720                 bp->lpi_tmr_hi = le32_to_cpu(resp->valid_tx_lpi_timer_high) &
4721                                  PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK;
4722         }
4723
4724 hwrm_phy_qcaps_exit:
4725         mutex_unlock(&bp->hwrm_cmd_lock);
4726         return rc;
4727 }
4728
4729 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4730 {
4731         int rc = 0;
4732         struct bnxt_link_info *link_info = &bp->link_info;
4733         struct hwrm_port_phy_qcfg_input req = {0};
4734         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4735         u8 link_up = link_info->link_up;
4736
4737         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4738
4739         mutex_lock(&bp->hwrm_cmd_lock);
4740         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4741         if (rc) {
4742                 mutex_unlock(&bp->hwrm_cmd_lock);
4743                 return rc;
4744         }
4745
4746         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4747         link_info->phy_link_status = resp->link;
4748         link_info->duplex =  resp->duplex;
4749         link_info->pause = resp->pause;
4750         link_info->auto_mode = resp->auto_mode;
4751         link_info->auto_pause_setting = resp->auto_pause;
4752         link_info->lp_pause = resp->link_partner_adv_pause;
4753         link_info->force_pause_setting = resp->force_pause;
4754         link_info->duplex_setting = resp->duplex;
4755         if (link_info->phy_link_status == BNXT_LINK_LINK)
4756                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4757         else
4758                 link_info->link_speed = 0;
4759         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4760         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4761         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4762         link_info->lp_auto_link_speeds =
4763                 le16_to_cpu(resp->link_partner_adv_speeds);
4764         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4765         link_info->phy_ver[0] = resp->phy_maj;
4766         link_info->phy_ver[1] = resp->phy_min;
4767         link_info->phy_ver[2] = resp->phy_bld;
4768         link_info->media_type = resp->media_type;
4769         link_info->phy_type = resp->phy_type;
4770         link_info->transceiver = resp->xcvr_pkg_type;
4771         link_info->phy_addr = resp->eee_config_phy_addr &
4772                               PORT_PHY_QCFG_RESP_PHY_ADDR_MASK;
4773         link_info->module_status = resp->module_status;
4774
4775         if (bp->flags & BNXT_FLAG_EEE_CAP) {
4776                 struct ethtool_eee *eee = &bp->eee;
4777                 u16 fw_speeds;
4778
4779                 eee->eee_active = 0;
4780                 if (resp->eee_config_phy_addr &
4781                     PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE) {
4782                         eee->eee_active = 1;
4783                         fw_speeds = le16_to_cpu(
4784                                 resp->link_partner_adv_eee_link_speed_mask);
4785                         eee->lp_advertised =
4786                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4787                 }
4788
4789                 /* Pull initial EEE config */
4790                 if (!chng_link_state) {
4791                         if (resp->eee_config_phy_addr &
4792                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED)
4793                                 eee->eee_enabled = 1;
4794
4795                         fw_speeds = le16_to_cpu(resp->adv_eee_link_speed_mask);
4796                         eee->advertised =
4797                                 _bnxt_fw_to_ethtool_adv_spds(fw_speeds, 0);
4798
4799                         if (resp->eee_config_phy_addr &
4800                             PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI) {
4801                                 __le32 tmr;
4802
4803                                 eee->tx_lpi_enabled = 1;
4804                                 tmr = resp->xcvr_identifier_type_tx_lpi_timer;
4805                                 eee->tx_lpi_timer = le32_to_cpu(tmr) &
4806                                         PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK;
4807                         }
4808                 }
4809         }
4810         /* TODO: need to add more logic to report VF link */
4811         if (chng_link_state) {
4812                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4813                         link_info->link_up = 1;
4814                 else
4815                         link_info->link_up = 0;
4816                 if (link_up != link_info->link_up)
4817                         bnxt_report_link(bp);
4818         } else {
4819                 /* alwasy link down if not require to update link state */
4820                 link_info->link_up = 0;
4821         }
4822         mutex_unlock(&bp->hwrm_cmd_lock);
4823         return 0;
4824 }
4825
4826 static void bnxt_get_port_module_status(struct bnxt *bp)
4827 {
4828         struct bnxt_link_info *link_info = &bp->link_info;
4829         struct hwrm_port_phy_qcfg_output *resp = &link_info->phy_qcfg_resp;
4830         u8 module_status;
4831
4832         if (bnxt_update_link(bp, true))
4833                 return;
4834
4835         module_status = link_info->module_status;
4836         switch (module_status) {
4837         case PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX:
4838         case PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN:
4839         case PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG:
4840                 netdev_warn(bp->dev, "Unqualified SFP+ module detected on port %d\n",
4841                             bp->pf.port_id);
4842                 if (bp->hwrm_spec_code >= 0x10201) {
4843                         netdev_warn(bp->dev, "Module part number %s\n",
4844                                     resp->phy_vendor_partnumber);
4845                 }
4846                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX)
4847                         netdev_warn(bp->dev, "TX is disabled\n");
4848                 if (module_status == PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN)
4849                         netdev_warn(bp->dev, "SFP+ module is shutdown\n");
4850         }
4851 }
4852
4853 static void
4854 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4855 {
4856         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4857                 if (bp->hwrm_spec_code >= 0x10201)
4858                         req->auto_pause =
4859                                 PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE;
4860                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4861                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4862                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4863                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_TX;
4864                 req->enables |=
4865                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4866         } else {
4867                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4868                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4869                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4870                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4871                 req->enables |=
4872                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4873                 if (bp->hwrm_spec_code >= 0x10201) {
4874                         req->auto_pause = req->force_pause;
4875                         req->enables |= cpu_to_le32(
4876                                 PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4877                 }
4878         }
4879 }
4880
4881 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4882                                       struct hwrm_port_phy_cfg_input *req)
4883 {
4884         u8 autoneg = bp->link_info.autoneg;
4885         u16 fw_link_speed = bp->link_info.req_link_speed;
4886         u32 advertising = bp->link_info.advertising;
4887
4888         if (autoneg & BNXT_AUTONEG_SPEED) {
4889                 req->auto_mode |=
4890                         PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;
4891
4892                 req->enables |= cpu_to_le32(
4893                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4894                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4895
4896                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4897                 req->flags |=
4898                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4899         } else {
4900                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4901                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4902         }
4903
4904         /* tell chimp that the setting takes effect immediately */
4905         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4906 }
4907
4908 int bnxt_hwrm_set_pause(struct bnxt *bp)
4909 {
4910         struct hwrm_port_phy_cfg_input req = {0};
4911         int rc;
4912
4913         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4914         bnxt_hwrm_set_pause_common(bp, &req);
4915
4916         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4917             bp->link_info.force_link_chng)
4918                 bnxt_hwrm_set_link_common(bp, &req);
4919
4920         mutex_lock(&bp->hwrm_cmd_lock);
4921         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4922         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4923                 /* since changing of pause setting doesn't trigger any link
4924                  * change event, the driver needs to update the current pause
4925                  * result upon successfully return of the phy_cfg command
4926                  */
4927                 bp->link_info.pause =
4928                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4929                 bp->link_info.auto_pause_setting = 0;
4930                 if (!bp->link_info.force_link_chng)
4931                         bnxt_report_link(bp);
4932         }
4933         bp->link_info.force_link_chng = false;
4934         mutex_unlock(&bp->hwrm_cmd_lock);
4935         return rc;
4936 }
4937
4938 static void bnxt_hwrm_set_eee(struct bnxt *bp,
4939                               struct hwrm_port_phy_cfg_input *req)
4940 {
4941         struct ethtool_eee *eee = &bp->eee;
4942
4943         if (eee->eee_enabled) {
4944                 u16 eee_speeds;
4945                 u32 flags = PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE;
4946
4947                 if (eee->tx_lpi_enabled)
4948                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE;
4949                 else
4950                         flags |= PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE;
4951
4952                 req->flags |= cpu_to_le32(flags);
4953                 eee_speeds = bnxt_get_fw_auto_link_speeds(eee->advertised);
4954                 req->eee_link_speed_mask = cpu_to_le16(eee_speeds);
4955                 req->tx_lpi_timer = cpu_to_le32(eee->tx_lpi_timer);
4956         } else {
4957                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE);
4958         }
4959 }
4960
4961 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause, bool set_eee)
4962 {
4963         struct hwrm_port_phy_cfg_input req = {0};
4964
4965         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4966         if (set_pause)
4967                 bnxt_hwrm_set_pause_common(bp, &req);
4968
4969         bnxt_hwrm_set_link_common(bp, &req);
4970
4971         if (set_eee)
4972                 bnxt_hwrm_set_eee(bp, &req);
4973         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4974 }
4975
4976 static int bnxt_hwrm_shutdown_link(struct bnxt *bp)
4977 {
4978         struct hwrm_port_phy_cfg_input req = {0};
4979
4980         if (!BNXT_SINGLE_PF(bp))
4981                 return 0;
4982
4983         if (pci_num_vf(bp->pdev))
4984                 return 0;
4985
4986         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4987         req.flags = cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DOWN);
4988         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4989 }
4990
4991 static bool bnxt_eee_config_ok(struct bnxt *bp)
4992 {
4993         struct ethtool_eee *eee = &bp->eee;
4994         struct bnxt_link_info *link_info = &bp->link_info;
4995
4996         if (!(bp->flags & BNXT_FLAG_EEE_CAP))
4997                 return true;
4998
4999         if (eee->eee_enabled) {
5000                 u32 advertising =
5001                         _bnxt_fw_to_ethtool_adv_spds(link_info->advertising, 0);
5002
5003                 if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5004                         eee->eee_enabled = 0;
5005                         return false;
5006                 }
5007                 if (eee->advertised & ~advertising) {
5008                         eee->advertised = advertising & eee->supported;
5009                         return false;
5010                 }
5011         }
5012         return true;
5013 }
5014
5015 static int bnxt_update_phy_setting(struct bnxt *bp)
5016 {
5017         int rc;
5018         bool update_link = false;
5019         bool update_pause = false;
5020         bool update_eee = false;
5021         struct bnxt_link_info *link_info = &bp->link_info;
5022
5023         rc = bnxt_update_link(bp, true);
5024         if (rc) {
5025                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
5026                            rc);
5027                 return rc;
5028         }
5029         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5030             (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) !=
5031             link_info->req_flow_ctrl)
5032                 update_pause = true;
5033         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
5034             link_info->force_pause_setting != link_info->req_flow_ctrl)
5035                 update_pause = true;
5036         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
5037                 if (BNXT_AUTO_MODE(link_info->auto_mode))
5038                         update_link = true;
5039                 if (link_info->req_link_speed != link_info->force_link_speed)
5040                         update_link = true;
5041                 if (link_info->req_duplex != link_info->duplex_setting)
5042                         update_link = true;
5043         } else {
5044                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
5045                         update_link = true;
5046                 if (link_info->advertising != link_info->auto_link_speeds)
5047                         update_link = true;
5048         }
5049
5050         if (!bnxt_eee_config_ok(bp))
5051                 update_eee = true;
5052
5053         if (update_link)
5054                 rc = bnxt_hwrm_set_link_setting(bp, update_pause, update_eee);
5055         else if (update_pause)
5056                 rc = bnxt_hwrm_set_pause(bp);
5057         if (rc) {
5058                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
5059                            rc);
5060                 return rc;
5061         }
5062
5063         return rc;
5064 }
5065
5066 /* Common routine to pre-map certain register block to different GRC window.
5067  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
5068  * in PF and 3 windows in VF that can be customized to map in different
5069  * register blocks.
5070  */
5071 static void bnxt_preset_reg_win(struct bnxt *bp)
5072 {
5073         if (BNXT_PF(bp)) {
5074                 /* CAG registers map to GRC window #4 */
5075                 writel(BNXT_CAG_REG_BASE,
5076                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
5077         }
5078 }
5079
5080 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5081 {
5082         int rc = 0;
5083
5084         bnxt_preset_reg_win(bp);
5085         netif_carrier_off(bp->dev);
5086         if (irq_re_init) {
5087                 rc = bnxt_setup_int_mode(bp);
5088                 if (rc) {
5089                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
5090                                    rc);
5091                         return rc;
5092                 }
5093         }
5094         if ((bp->flags & BNXT_FLAG_RFS) &&
5095             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
5096                 /* disable RFS if falling back to INTA */
5097                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
5098                 bp->flags &= ~BNXT_FLAG_RFS;
5099         }
5100
5101         rc = bnxt_alloc_mem(bp, irq_re_init);
5102         if (rc) {
5103                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
5104                 goto open_err_free_mem;
5105         }
5106
5107         if (irq_re_init) {
5108                 bnxt_init_napi(bp);
5109                 rc = bnxt_request_irq(bp);
5110                 if (rc) {
5111                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
5112                         goto open_err;
5113                 }
5114         }
5115
5116         bnxt_enable_napi(bp);
5117
5118         rc = bnxt_init_nic(bp, irq_re_init);
5119         if (rc) {
5120                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
5121                 goto open_err;
5122         }
5123
5124         if (link_re_init) {
5125                 rc = bnxt_update_phy_setting(bp);
5126                 if (rc)
5127                         netdev_warn(bp->dev, "failed to update phy settings\n");
5128         }
5129
5130         if (irq_re_init) {
5131 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
5132                 vxlan_get_rx_port(bp->dev);
5133 #endif
5134                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
5135                                 bp, htons(0x17c1),
5136                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
5137                         bp->nge_port_cnt = 1;
5138         }
5139
5140         set_bit(BNXT_STATE_OPEN, &bp->state);
5141         bnxt_enable_int(bp);
5142         /* Enable TX queues */
5143         bnxt_tx_enable(bp);
5144         mod_timer(&bp->timer, jiffies + bp->current_interval);
5145         /* Poll link status and check for SFP+ module status */
5146         bnxt_get_port_module_status(bp);
5147
5148         return 0;
5149
5150 open_err:
5151         bnxt_disable_napi(bp);
5152         bnxt_del_napi(bp);
5153
5154 open_err_free_mem:
5155         bnxt_free_skbs(bp);
5156         bnxt_free_irq(bp);
5157         bnxt_free_mem(bp, true);
5158         return rc;
5159 }
5160
5161 /* rtnl_lock held */
5162 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5163 {
5164         int rc = 0;
5165
5166         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
5167         if (rc) {
5168                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
5169                 dev_close(bp->dev);
5170         }
5171         return rc;
5172 }
5173
5174 static int bnxt_open(struct net_device *dev)
5175 {
5176         struct bnxt *bp = netdev_priv(dev);
5177         int rc = 0;
5178
5179         rc = bnxt_hwrm_func_reset(bp);
5180         if (rc) {
5181                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
5182                            rc);
5183                 rc = -1;
5184                 return rc;
5185         }
5186         return __bnxt_open_nic(bp, true, true);
5187 }
5188
5189 static void bnxt_disable_int_sync(struct bnxt *bp)
5190 {
5191         int i;
5192
5193         atomic_inc(&bp->intr_sem);
5194         if (!netif_running(bp->dev))
5195                 return;
5196
5197         bnxt_disable_int(bp);
5198         for (i = 0; i < bp->cp_nr_rings; i++)
5199                 synchronize_irq(bp->irq_tbl[i].vector);
5200 }
5201
5202 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
5203 {
5204         int rc = 0;
5205
5206 #ifdef CONFIG_BNXT_SRIOV
5207         if (bp->sriov_cfg) {
5208                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
5209                                                       !bp->sriov_cfg,
5210                                                       BNXT_SRIOV_CFG_WAIT_TMO);
5211                 if (rc)
5212                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
5213         }
5214 #endif
5215         /* Change device state to avoid TX queue wake up's */
5216         bnxt_tx_disable(bp);
5217
5218         clear_bit(BNXT_STATE_OPEN, &bp->state);
5219         smp_mb__after_atomic();
5220         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
5221                 msleep(20);
5222
5223         /* Flush rings before disabling interrupts */
5224         bnxt_shutdown_nic(bp, irq_re_init);
5225
5226         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
5227
5228         bnxt_disable_napi(bp);
5229         bnxt_disable_int_sync(bp);
5230         del_timer_sync(&bp->timer);
5231         bnxt_free_skbs(bp);
5232
5233         if (irq_re_init) {
5234                 bnxt_free_irq(bp);
5235                 bnxt_del_napi(bp);
5236         }
5237         bnxt_free_mem(bp, irq_re_init);
5238         return rc;
5239 }
5240
5241 static int bnxt_close(struct net_device *dev)
5242 {
5243         struct bnxt *bp = netdev_priv(dev);
5244
5245         bnxt_close_nic(bp, true, true);
5246         bnxt_hwrm_shutdown_link(bp);
5247         return 0;
5248 }
5249
5250 /* rtnl_lock held */
5251 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5252 {
5253         switch (cmd) {
5254         case SIOCGMIIPHY:
5255                 /* fallthru */
5256         case SIOCGMIIREG: {
5257                 if (!netif_running(dev))
5258                         return -EAGAIN;
5259
5260                 return 0;
5261         }
5262
5263         case SIOCSMIIREG:
5264                 if (!netif_running(dev))
5265                         return -EAGAIN;
5266
5267                 return 0;
5268
5269         default:
5270                 /* do nothing */
5271                 break;
5272         }
5273         return -EOPNOTSUPP;
5274 }
5275
5276 static struct rtnl_link_stats64 *
5277 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
5278 {
5279         u32 i;
5280         struct bnxt *bp = netdev_priv(dev);
5281
5282         memset(stats, 0, sizeof(struct rtnl_link_stats64));
5283
5284         if (!bp->bnapi)
5285                 return stats;
5286
5287         /* TODO check if we need to synchronize with bnxt_close path */
5288         for (i = 0; i < bp->cp_nr_rings; i++) {
5289                 struct bnxt_napi *bnapi = bp->bnapi[i];
5290                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5291                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
5292
5293                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
5294                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
5295                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
5296
5297                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
5298                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
5299                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
5300
5301                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
5302                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
5303                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
5304
5305                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
5306                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
5307                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
5308
5309                 stats->rx_missed_errors +=
5310                         le64_to_cpu(hw_stats->rx_discard_pkts);
5311
5312                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
5313
5314                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
5315         }
5316
5317         if (bp->flags & BNXT_FLAG_PORT_STATS) {
5318                 struct rx_port_stats *rx = bp->hw_rx_port_stats;
5319                 struct tx_port_stats *tx = bp->hw_tx_port_stats;
5320
5321                 stats->rx_crc_errors = le64_to_cpu(rx->rx_fcs_err_frames);
5322                 stats->rx_frame_errors = le64_to_cpu(rx->rx_align_err_frames);
5323                 stats->rx_length_errors = le64_to_cpu(rx->rx_undrsz_frames) +
5324                                           le64_to_cpu(rx->rx_ovrsz_frames) +
5325                                           le64_to_cpu(rx->rx_runt_frames);
5326                 stats->rx_errors = le64_to_cpu(rx->rx_false_carrier_frames) +
5327                                    le64_to_cpu(rx->rx_jbr_frames);
5328                 stats->collisions = le64_to_cpu(tx->tx_total_collisions);
5329                 stats->tx_fifo_errors = le64_to_cpu(tx->tx_fifo_underruns);
5330                 stats->tx_errors = le64_to_cpu(tx->tx_err);
5331         }
5332
5333         return stats;
5334 }
5335
5336 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
5337 {
5338         struct net_device *dev = bp->dev;
5339         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5340         struct netdev_hw_addr *ha;
5341         u8 *haddr;
5342         int mc_count = 0;
5343         bool update = false;
5344         int off = 0;
5345
5346         netdev_for_each_mc_addr(ha, dev) {
5347                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
5348                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5349                         vnic->mc_list_count = 0;
5350                         return false;
5351                 }
5352                 haddr = ha->addr;
5353                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
5354                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
5355                         update = true;
5356                 }
5357                 off += ETH_ALEN;
5358                 mc_count++;
5359         }
5360         if (mc_count)
5361                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
5362
5363         if (mc_count != vnic->mc_list_count) {
5364                 vnic->mc_list_count = mc_count;
5365                 update = true;
5366         }
5367         return update;
5368 }
5369
5370 static bool bnxt_uc_list_updated(struct bnxt *bp)
5371 {
5372         struct net_device *dev = bp->dev;
5373         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5374         struct netdev_hw_addr *ha;
5375         int off = 0;
5376
5377         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
5378                 return true;
5379
5380         netdev_for_each_uc_addr(ha, dev) {
5381                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
5382                         return true;
5383
5384                 off += ETH_ALEN;
5385         }
5386         return false;
5387 }
5388
5389 static void bnxt_set_rx_mode(struct net_device *dev)
5390 {
5391         struct bnxt *bp = netdev_priv(dev);
5392         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5393         u32 mask = vnic->rx_mask;
5394         bool mc_update = false;
5395         bool uc_update;
5396
5397         if (!netif_running(dev))
5398                 return;
5399
5400         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
5401                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
5402                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
5403
5404         /* Only allow PF to be in promiscuous mode */
5405         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
5406                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5407
5408         uc_update = bnxt_uc_list_updated(bp);
5409
5410         if (dev->flags & IFF_ALLMULTI) {
5411                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
5412                 vnic->mc_list_count = 0;
5413         } else {
5414                 mc_update = bnxt_mc_list_updated(bp, &mask);
5415         }
5416
5417         if (mask != vnic->rx_mask || uc_update || mc_update) {
5418                 vnic->rx_mask = mask;
5419
5420                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
5421                 schedule_work(&bp->sp_task);
5422         }
5423 }
5424
5425 static int bnxt_cfg_rx_mode(struct bnxt *bp)
5426 {
5427         struct net_device *dev = bp->dev;
5428         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
5429         struct netdev_hw_addr *ha;
5430         int i, off = 0, rc;
5431         bool uc_update;
5432
5433         netif_addr_lock_bh(dev);
5434         uc_update = bnxt_uc_list_updated(bp);
5435         netif_addr_unlock_bh(dev);
5436
5437         if (!uc_update)
5438                 goto skip_uc;
5439
5440         mutex_lock(&bp->hwrm_cmd_lock);
5441         for (i = 1; i < vnic->uc_filter_count; i++) {
5442                 struct hwrm_cfa_l2_filter_free_input req = {0};
5443
5444                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
5445                                        -1);
5446
5447                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
5448
5449                 rc = _hwrm_send_message(bp, &req, sizeof(req),
5450                                         HWRM_CMD_TIMEOUT);
5451         }
5452         mutex_unlock(&bp->hwrm_cmd_lock);
5453
5454         vnic->uc_filter_count = 1;
5455
5456         netif_addr_lock_bh(dev);
5457         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
5458                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
5459         } else {
5460                 netdev_for_each_uc_addr(ha, dev) {
5461                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
5462                         off += ETH_ALEN;
5463                         vnic->uc_filter_count++;
5464                 }
5465         }
5466         netif_addr_unlock_bh(dev);
5467
5468         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
5469                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
5470                 if (rc) {
5471                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
5472                                    rc);
5473                         vnic->uc_filter_count = i;
5474                         return rc;
5475                 }
5476         }
5477
5478 skip_uc:
5479         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
5480         if (rc)
5481                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
5482                            rc);
5483
5484         return rc;
5485 }
5486
5487 static bool bnxt_rfs_capable(struct bnxt *bp)
5488 {
5489 #ifdef CONFIG_RFS_ACCEL
5490         struct bnxt_pf_info *pf = &bp->pf;
5491         int vnics;
5492
5493         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
5494                 return false;
5495
5496         vnics = 1 + bp->rx_nr_rings;
5497         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
5498                 return false;
5499
5500         return true;
5501 #else
5502         return false;
5503 #endif
5504 }
5505
5506 static netdev_features_t bnxt_fix_features(struct net_device *dev,
5507                                            netdev_features_t features)
5508 {
5509         struct bnxt *bp = netdev_priv(dev);
5510
5511         if (!bnxt_rfs_capable(bp))
5512                 features &= ~NETIF_F_NTUPLE;
5513
5514         /* Both CTAG and STAG VLAN accelaration on the RX side have to be
5515          * turned on or off together.
5516          */
5517         if ((features & (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) !=
5518             (NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX)) {
5519                 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
5520                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5521                                       NETIF_F_HW_VLAN_STAG_RX);
5522                 else
5523                         features |= NETIF_F_HW_VLAN_CTAG_RX |
5524                                     NETIF_F_HW_VLAN_STAG_RX;
5525         }
5526 #ifdef CONFIG_BNXT_SRIOV
5527         if (BNXT_VF(bp)) {
5528                 if (bp->vf.vlan) {
5529                         features &= ~(NETIF_F_HW_VLAN_CTAG_RX |
5530                                       NETIF_F_HW_VLAN_STAG_RX);
5531                 }
5532         }
5533 #endif
5534         return features;
5535 }
5536
5537 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
5538 {
5539         struct bnxt *bp = netdev_priv(dev);
5540         u32 flags = bp->flags;
5541         u32 changes;
5542         int rc = 0;
5543         bool re_init = false;
5544         bool update_tpa = false;
5545
5546         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
5547         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5548                 flags |= BNXT_FLAG_GRO;
5549         if (features & NETIF_F_LRO)
5550                 flags |= BNXT_FLAG_LRO;
5551
5552         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5553                 flags |= BNXT_FLAG_STRIP_VLAN;
5554
5555         if (features & NETIF_F_NTUPLE)
5556                 flags |= BNXT_FLAG_RFS;
5557
5558         changes = flags ^ bp->flags;
5559         if (changes & BNXT_FLAG_TPA) {
5560                 update_tpa = true;
5561                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5562                     (flags & BNXT_FLAG_TPA) == 0)
5563                         re_init = true;
5564         }
5565
5566         if (changes & ~BNXT_FLAG_TPA)
5567                 re_init = true;
5568
5569         if (flags != bp->flags) {
5570                 u32 old_flags = bp->flags;
5571
5572                 bp->flags = flags;
5573
5574                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5575                         if (update_tpa)
5576                                 bnxt_set_ring_params(bp);
5577                         return rc;
5578                 }
5579
5580                 if (re_init) {
5581                         bnxt_close_nic(bp, false, false);
5582                         if (update_tpa)
5583                                 bnxt_set_ring_params(bp);
5584
5585                         return bnxt_open_nic(bp, false, false);
5586                 }
5587                 if (update_tpa) {
5588                         rc = bnxt_set_tpa(bp,
5589                                           (flags & BNXT_FLAG_TPA) ?
5590                                           true : false);
5591                         if (rc)
5592                                 bp->flags = old_flags;
5593                 }
5594         }
5595         return rc;
5596 }
5597
5598 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5599 {
5600         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5601         int i = bnapi->index;
5602
5603         if (!txr)
5604                 return;
5605
5606         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5607                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5608                     txr->tx_cons);
5609 }
5610
5611 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5612 {
5613         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5614         int i = bnapi->index;
5615
5616         if (!rxr)
5617                 return;
5618
5619         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5620                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5621                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5622                     rxr->rx_sw_agg_prod);
5623 }
5624
5625 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5626 {
5627         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5628         int i = bnapi->index;
5629
5630         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5631                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5632 }
5633
5634 static void bnxt_dbg_dump_states(struct bnxt *bp)
5635 {
5636         int i;
5637         struct bnxt_napi *bnapi;
5638
5639         for (i = 0; i < bp->cp_nr_rings; i++) {
5640                 bnapi = bp->bnapi[i];
5641                 if (netif_msg_drv(bp)) {
5642                         bnxt_dump_tx_sw_state(bnapi);
5643                         bnxt_dump_rx_sw_state(bnapi);
5644                         bnxt_dump_cp_sw_state(bnapi);
5645                 }
5646         }
5647 }
5648
5649 static void bnxt_reset_task(struct bnxt *bp, bool silent)
5650 {
5651         if (!silent)
5652                 bnxt_dbg_dump_states(bp);
5653         if (netif_running(bp->dev)) {
5654                 bnxt_close_nic(bp, false, false);
5655                 bnxt_open_nic(bp, false, false);
5656         }
5657 }
5658
5659 static void bnxt_tx_timeout(struct net_device *dev)
5660 {
5661         struct bnxt *bp = netdev_priv(dev);
5662
5663         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5664         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5665         schedule_work(&bp->sp_task);
5666 }
5667
5668 #ifdef CONFIG_NET_POLL_CONTROLLER
5669 static void bnxt_poll_controller(struct net_device *dev)
5670 {
5671         struct bnxt *bp = netdev_priv(dev);
5672         int i;
5673
5674         for (i = 0; i < bp->cp_nr_rings; i++) {
5675                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5676
5677                 disable_irq(irq->vector);
5678                 irq->handler(irq->vector, bp->bnapi[i]);
5679                 enable_irq(irq->vector);
5680         }
5681 }
5682 #endif
5683
5684 static void bnxt_timer(unsigned long data)
5685 {
5686         struct bnxt *bp = (struct bnxt *)data;
5687         struct net_device *dev = bp->dev;
5688
5689         if (!netif_running(dev))
5690                 return;
5691
5692         if (atomic_read(&bp->intr_sem) != 0)
5693                 goto bnxt_restart_timer;
5694
5695         if (bp->link_info.link_up && (bp->flags & BNXT_FLAG_PORT_STATS)) {
5696                 set_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event);
5697                 schedule_work(&bp->sp_task);
5698         }
5699 bnxt_restart_timer:
5700         mod_timer(&bp->timer, jiffies + bp->current_interval);
5701 }
5702
5703 /* Only called from bnxt_sp_task() */
5704 static void bnxt_reset(struct bnxt *bp, bool silent)
5705 {
5706         /* bnxt_reset_task() calls bnxt_close_nic() which waits
5707          * for BNXT_STATE_IN_SP_TASK to clear.
5708          * If there is a parallel dev_close(), bnxt_close() may be holding
5709          * rtnl() and waiting for BNXT_STATE_IN_SP_TASK to clear.  So we
5710          * must clear BNXT_STATE_IN_SP_TASK before holding rtnl().
5711          */
5712         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5713         rtnl_lock();
5714         if (test_bit(BNXT_STATE_OPEN, &bp->state))
5715                 bnxt_reset_task(bp, silent);
5716         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5717         rtnl_unlock();
5718 }
5719
5720 static void bnxt_cfg_ntp_filters(struct bnxt *);
5721
5722 static void bnxt_sp_task(struct work_struct *work)
5723 {
5724         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5725         int rc;
5726
5727         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5728         smp_mb__after_atomic();
5729         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5730                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5731                 return;
5732         }
5733
5734         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5735                 bnxt_cfg_rx_mode(bp);
5736
5737         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5738                 bnxt_cfg_ntp_filters(bp);
5739         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5740                 rc = bnxt_update_link(bp, true);
5741                 if (rc)
5742                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5743                                    rc);
5744         }
5745         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5746                 bnxt_hwrm_exec_fwd_req(bp);
5747         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5748                 bnxt_hwrm_tunnel_dst_port_alloc(
5749                         bp, bp->vxlan_port,
5750                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5751         }
5752         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5753                 bnxt_hwrm_tunnel_dst_port_free(
5754                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5755         }
5756         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
5757                 bnxt_reset(bp, false);
5758
5759         if (test_and_clear_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event))
5760                 bnxt_reset(bp, true);
5761
5762         if (test_and_clear_bit(BNXT_HWRM_PORT_MODULE_SP_EVENT, &bp->sp_event))
5763                 bnxt_get_port_module_status(bp);
5764
5765         if (test_and_clear_bit(BNXT_PERIODIC_STATS_SP_EVENT, &bp->sp_event))
5766                 bnxt_hwrm_port_qstats(bp);
5767
5768         smp_mb__before_atomic();
5769         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5770 }
5771
5772 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5773 {
5774         int rc;
5775         struct bnxt *bp = netdev_priv(dev);
5776
5777         SET_NETDEV_DEV(dev, &pdev->dev);
5778
5779         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5780         rc = pci_enable_device(pdev);
5781         if (rc) {
5782                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5783                 goto init_err;
5784         }
5785
5786         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5787                 dev_err(&pdev->dev,
5788                         "Cannot find PCI device base address, aborting\n");
5789                 rc = -ENODEV;
5790                 goto init_err_disable;
5791         }
5792
5793         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5794         if (rc) {
5795                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5796                 goto init_err_disable;
5797         }
5798
5799         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5800             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5801                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5802                 goto init_err_disable;
5803         }
5804
5805         pci_set_master(pdev);
5806
5807         bp->dev = dev;
5808         bp->pdev = pdev;
5809
5810         bp->bar0 = pci_ioremap_bar(pdev, 0);
5811         if (!bp->bar0) {
5812                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5813                 rc = -ENOMEM;
5814                 goto init_err_release;
5815         }
5816
5817         bp->bar1 = pci_ioremap_bar(pdev, 2);
5818         if (!bp->bar1) {
5819                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5820                 rc = -ENOMEM;
5821                 goto init_err_release;
5822         }
5823
5824         bp->bar2 = pci_ioremap_bar(pdev, 4);
5825         if (!bp->bar2) {
5826                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5827                 rc = -ENOMEM;
5828                 goto init_err_release;
5829         }
5830
5831         pci_enable_pcie_error_reporting(pdev);
5832
5833         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5834
5835         spin_lock_init(&bp->ntp_fltr_lock);
5836
5837         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5838         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5839
5840         /* tick values in micro seconds */
5841         bp->rx_coal_ticks = 12;
5842         bp->rx_coal_bufs = 30;
5843         bp->rx_coal_ticks_irq = 1;
5844         bp->rx_coal_bufs_irq = 2;
5845
5846         bp->tx_coal_ticks = 25;
5847         bp->tx_coal_bufs = 30;
5848         bp->tx_coal_ticks_irq = 2;
5849         bp->tx_coal_bufs_irq = 2;
5850
5851         init_timer(&bp->timer);
5852         bp->timer.data = (unsigned long)bp;
5853         bp->timer.function = bnxt_timer;
5854         bp->current_interval = BNXT_TIMER_INTERVAL;
5855
5856         clear_bit(BNXT_STATE_OPEN, &bp->state);
5857
5858         return 0;
5859
5860 init_err_release:
5861         if (bp->bar2) {
5862                 pci_iounmap(pdev, bp->bar2);
5863                 bp->bar2 = NULL;
5864         }
5865
5866         if (bp->bar1) {
5867                 pci_iounmap(pdev, bp->bar1);
5868                 bp->bar1 = NULL;
5869         }
5870
5871         if (bp->bar0) {
5872                 pci_iounmap(pdev, bp->bar0);
5873                 bp->bar0 = NULL;
5874         }
5875
5876         pci_release_regions(pdev);
5877
5878 init_err_disable:
5879         pci_disable_device(pdev);
5880
5881 init_err:
5882         return rc;
5883 }
5884
5885 /* rtnl_lock held */
5886 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5887 {
5888         struct sockaddr *addr = p;
5889         struct bnxt *bp = netdev_priv(dev);
5890         int rc = 0;
5891
5892         if (!is_valid_ether_addr(addr->sa_data))
5893                 return -EADDRNOTAVAIL;
5894
5895         rc = bnxt_approve_mac(bp, addr->sa_data);
5896         if (rc)
5897                 return rc;
5898
5899         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5900                 return 0;
5901
5902         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5903         if (netif_running(dev)) {
5904                 bnxt_close_nic(bp, false, false);
5905                 rc = bnxt_open_nic(bp, false, false);
5906         }
5907
5908         return rc;
5909 }
5910
5911 /* rtnl_lock held */
5912 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5913 {
5914         struct bnxt *bp = netdev_priv(dev);
5915
5916         if (new_mtu < 60 || new_mtu > 9000)
5917                 return -EINVAL;
5918
5919         if (netif_running(dev))
5920                 bnxt_close_nic(bp, false, false);
5921
5922         dev->mtu = new_mtu;
5923         bnxt_set_ring_params(bp);
5924
5925         if (netif_running(dev))
5926                 return bnxt_open_nic(bp, false, false);
5927
5928         return 0;
5929 }
5930
5931 static int bnxt_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
5932                          struct tc_to_netdev *ntc)
5933 {
5934         struct bnxt *bp = netdev_priv(dev);
5935         u8 tc;
5936
5937         if (ntc->type != TC_SETUP_MQPRIO)
5938                 return -EINVAL;
5939
5940         tc = ntc->tc;
5941
5942         if (tc > bp->max_tc) {
5943                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5944                            tc, bp->max_tc);
5945                 return -EINVAL;
5946         }
5947
5948         if (netdev_get_num_tc(dev) == tc)
5949                 return 0;
5950
5951         if (tc) {
5952                 int max_rx_rings, max_tx_rings, rc;
5953                 bool sh = false;
5954
5955                 if (bp->flags & BNXT_FLAG_SHARED_RINGS)
5956                         sh = true;
5957
5958                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5959                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5960                         return -ENOMEM;
5961         }
5962
5963         /* Needs to close the device and do hw resource re-allocations */
5964         if (netif_running(bp->dev))
5965                 bnxt_close_nic(bp, true, false);
5966
5967         if (tc) {
5968                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5969                 netdev_set_num_tc(dev, tc);
5970         } else {
5971                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5972                 netdev_reset_tc(dev);
5973         }
5974         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5975         bp->num_stat_ctxs = bp->cp_nr_rings;
5976
5977         if (netif_running(bp->dev))
5978                 return bnxt_open_nic(bp, true, false);
5979
5980         return 0;
5981 }
5982
5983 #ifdef CONFIG_RFS_ACCEL
5984 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5985                             struct bnxt_ntuple_filter *f2)
5986 {
5987         struct flow_keys *keys1 = &f1->fkeys;
5988         struct flow_keys *keys2 = &f2->fkeys;
5989
5990         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5991             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5992             keys1->ports.ports == keys2->ports.ports &&
5993             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5994             keys1->basic.n_proto == keys2->basic.n_proto &&
5995             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5996                 return true;
5997
5998         return false;
5999 }
6000
6001 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
6002                               u16 rxq_index, u32 flow_id)
6003 {
6004         struct bnxt *bp = netdev_priv(dev);
6005         struct bnxt_ntuple_filter *fltr, *new_fltr;
6006         struct flow_keys *fkeys;
6007         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
6008         int rc = 0, idx, bit_id;
6009         struct hlist_head *head;
6010
6011         if (skb->encapsulation)
6012                 return -EPROTONOSUPPORT;
6013
6014         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
6015         if (!new_fltr)
6016                 return -ENOMEM;
6017
6018         fkeys = &new_fltr->fkeys;
6019         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
6020                 rc = -EPROTONOSUPPORT;
6021                 goto err_free;
6022         }
6023
6024         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
6025             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
6026              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
6027                 rc = -EPROTONOSUPPORT;
6028                 goto err_free;
6029         }
6030
6031         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
6032
6033         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
6034         head = &bp->ntp_fltr_hash_tbl[idx];
6035         rcu_read_lock();
6036         hlist_for_each_entry_rcu(fltr, head, hash) {
6037                 if (bnxt_fltr_match(fltr, new_fltr)) {
6038                         rcu_read_unlock();
6039                         rc = 0;
6040                         goto err_free;
6041                 }
6042         }
6043         rcu_read_unlock();
6044
6045         spin_lock_bh(&bp->ntp_fltr_lock);
6046         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
6047                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
6048         if (bit_id < 0) {
6049                 spin_unlock_bh(&bp->ntp_fltr_lock);
6050                 rc = -ENOMEM;
6051                 goto err_free;
6052         }
6053
6054         new_fltr->sw_id = (u16)bit_id;
6055         new_fltr->flow_id = flow_id;
6056         new_fltr->rxq = rxq_index;
6057         hlist_add_head_rcu(&new_fltr->hash, head);
6058         bp->ntp_fltr_count++;
6059         spin_unlock_bh(&bp->ntp_fltr_lock);
6060
6061         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
6062         schedule_work(&bp->sp_task);
6063
6064         return new_fltr->sw_id;
6065
6066 err_free:
6067         kfree(new_fltr);
6068         return rc;
6069 }
6070
6071 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6072 {
6073         int i;
6074
6075         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
6076                 struct hlist_head *head;
6077                 struct hlist_node *tmp;
6078                 struct bnxt_ntuple_filter *fltr;
6079                 int rc;
6080
6081                 head = &bp->ntp_fltr_hash_tbl[i];
6082                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
6083                         bool del = false;
6084
6085                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
6086                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
6087                                                         fltr->flow_id,
6088                                                         fltr->sw_id)) {
6089                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
6090                                                                          fltr);
6091                                         del = true;
6092                                 }
6093                         } else {
6094                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
6095                                                                        fltr);
6096                                 if (rc)
6097                                         del = true;
6098                                 else
6099                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
6100                         }
6101
6102                         if (del) {
6103                                 spin_lock_bh(&bp->ntp_fltr_lock);
6104                                 hlist_del_rcu(&fltr->hash);
6105                                 bp->ntp_fltr_count--;
6106                                 spin_unlock_bh(&bp->ntp_fltr_lock);
6107                                 synchronize_rcu();
6108                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
6109                                 kfree(fltr);
6110                         }
6111                 }
6112         }
6113         if (test_and_clear_bit(BNXT_HWRM_PF_UNLOAD_SP_EVENT, &bp->sp_event))
6114                 netdev_info(bp->dev, "Receive PF driver unload event!");
6115 }
6116
6117 #else
6118
6119 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
6120 {
6121 }
6122
6123 #endif /* CONFIG_RFS_ACCEL */
6124
6125 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
6126                                 __be16 port)
6127 {
6128         struct bnxt *bp = netdev_priv(dev);
6129
6130         if (!netif_running(dev))
6131                 return;
6132
6133         if (sa_family != AF_INET6 && sa_family != AF_INET)
6134                 return;
6135
6136         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
6137                 return;
6138
6139         bp->vxlan_port_cnt++;
6140         if (bp->vxlan_port_cnt == 1) {
6141                 bp->vxlan_port = port;
6142                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
6143                 schedule_work(&bp->sp_task);
6144         }
6145 }
6146
6147 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
6148                                 __be16 port)
6149 {
6150         struct bnxt *bp = netdev_priv(dev);
6151
6152         if (!netif_running(dev))
6153                 return;
6154
6155         if (sa_family != AF_INET6 && sa_family != AF_INET)
6156                 return;
6157
6158         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
6159                 bp->vxlan_port_cnt--;
6160
6161                 if (bp->vxlan_port_cnt == 0) {
6162                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
6163                         schedule_work(&bp->sp_task);
6164                 }
6165         }
6166 }
6167
6168 static const struct net_device_ops bnxt_netdev_ops = {
6169         .ndo_open               = bnxt_open,
6170         .ndo_start_xmit         = bnxt_start_xmit,
6171         .ndo_stop               = bnxt_close,
6172         .ndo_get_stats64        = bnxt_get_stats64,
6173         .ndo_set_rx_mode        = bnxt_set_rx_mode,
6174         .ndo_do_ioctl           = bnxt_ioctl,
6175         .ndo_validate_addr      = eth_validate_addr,
6176         .ndo_set_mac_address    = bnxt_change_mac_addr,
6177         .ndo_change_mtu         = bnxt_change_mtu,
6178         .ndo_fix_features       = bnxt_fix_features,
6179         .ndo_set_features       = bnxt_set_features,
6180         .ndo_tx_timeout         = bnxt_tx_timeout,
6181 #ifdef CONFIG_BNXT_SRIOV
6182         .ndo_get_vf_config      = bnxt_get_vf_config,
6183         .ndo_set_vf_mac         = bnxt_set_vf_mac,
6184         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
6185         .ndo_set_vf_rate        = bnxt_set_vf_bw,
6186         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
6187         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
6188 #endif
6189 #ifdef CONFIG_NET_POLL_CONTROLLER
6190         .ndo_poll_controller    = bnxt_poll_controller,
6191 #endif
6192         .ndo_setup_tc           = bnxt_setup_tc,
6193 #ifdef CONFIG_RFS_ACCEL
6194         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
6195 #endif
6196         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
6197         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
6198 #ifdef CONFIG_NET_RX_BUSY_POLL
6199         .ndo_busy_poll          = bnxt_busy_poll,
6200 #endif
6201 };
6202
6203 static void bnxt_remove_one(struct pci_dev *pdev)
6204 {
6205         struct net_device *dev = pci_get_drvdata(pdev);
6206         struct bnxt *bp = netdev_priv(dev);
6207
6208         if (BNXT_PF(bp))
6209                 bnxt_sriov_disable(bp);
6210
6211         pci_disable_pcie_error_reporting(pdev);
6212         unregister_netdev(dev);
6213         cancel_work_sync(&bp->sp_task);
6214         bp->sp_event = 0;
6215
6216         bnxt_hwrm_func_drv_unrgtr(bp);
6217         bnxt_free_hwrm_resources(bp);
6218         pci_iounmap(pdev, bp->bar2);
6219         pci_iounmap(pdev, bp->bar1);
6220         pci_iounmap(pdev, bp->bar0);
6221         free_netdev(dev);
6222
6223         pci_release_regions(pdev);
6224         pci_disable_device(pdev);
6225 }
6226
6227 static int bnxt_probe_phy(struct bnxt *bp)
6228 {
6229         int rc = 0;
6230         struct bnxt_link_info *link_info = &bp->link_info;
6231
6232         rc = bnxt_hwrm_phy_qcaps(bp);
6233         if (rc) {
6234                 netdev_err(bp->dev, "Probe phy can't get phy capabilities (rc: %x)\n",
6235                            rc);
6236                 return rc;
6237         }
6238
6239         rc = bnxt_update_link(bp, false);
6240         if (rc) {
6241                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
6242                            rc);
6243                 return rc;
6244         }
6245
6246         /*initialize the ethool setting copy with NVM settings */
6247         if (BNXT_AUTO_MODE(link_info->auto_mode)) {
6248                 link_info->autoneg = BNXT_AUTONEG_SPEED;
6249                 if (bp->hwrm_spec_code >= 0x10201) {
6250                         if (link_info->auto_pause_setting &
6251                             PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE)
6252                                 link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6253                 } else {
6254                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
6255                 }
6256                 link_info->advertising = link_info->auto_link_speeds;
6257         } else {
6258                 link_info->req_link_speed = link_info->force_link_speed;
6259                 link_info->req_duplex = link_info->duplex_setting;
6260         }
6261         if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
6262                 link_info->req_flow_ctrl =
6263                         link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH;
6264         else
6265                 link_info->req_flow_ctrl = link_info->force_pause_setting;
6266         return rc;
6267 }
6268
6269 static int bnxt_get_max_irq(struct pci_dev *pdev)
6270 {
6271         u16 ctrl;
6272
6273         if (!pdev->msix_cap)
6274                 return 1;
6275
6276         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
6277         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
6278 }
6279
6280 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
6281                                 int *max_cp)
6282 {
6283         int max_ring_grps = 0;
6284
6285 #ifdef CONFIG_BNXT_SRIOV
6286         if (!BNXT_PF(bp)) {
6287                 *max_tx = bp->vf.max_tx_rings;
6288                 *max_rx = bp->vf.max_rx_rings;
6289                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
6290                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
6291                 max_ring_grps = bp->vf.max_hw_ring_grps;
6292         } else
6293 #endif
6294         {
6295                 *max_tx = bp->pf.max_tx_rings;
6296                 *max_rx = bp->pf.max_rx_rings;
6297                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
6298                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
6299                 max_ring_grps = bp->pf.max_hw_ring_grps;
6300         }
6301
6302         if (bp->flags & BNXT_FLAG_AGG_RINGS)
6303                 *max_rx >>= 1;
6304         *max_rx = min_t(int, *max_rx, max_ring_grps);
6305 }
6306
6307 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
6308 {
6309         int rx, tx, cp;
6310
6311         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
6312         if (!rx || !tx || !cp)
6313                 return -ENOMEM;
6314
6315         *max_rx = rx;
6316         *max_tx = tx;
6317         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
6318 }
6319
6320 static int bnxt_set_dflt_rings(struct bnxt *bp)
6321 {
6322         int dflt_rings, max_rx_rings, max_tx_rings, rc;
6323         bool sh = true;
6324
6325         if (sh)
6326                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
6327         dflt_rings = netif_get_num_default_rss_queues();
6328         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
6329         if (rc)
6330                 return rc;
6331         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
6332         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
6333         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
6334         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
6335                                bp->tx_nr_rings + bp->rx_nr_rings;
6336         bp->num_stat_ctxs = bp->cp_nr_rings;
6337         return rc;
6338 }
6339
6340 static void bnxt_parse_log_pcie_link(struct bnxt *bp)
6341 {
6342         enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
6343         enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
6344
6345         if (pcie_get_minimum_link(bp->pdev, &speed, &width) ||
6346             speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN)
6347                 netdev_info(bp->dev, "Failed to determine PCIe Link Info\n");
6348         else
6349                 netdev_info(bp->dev, "PCIe: Speed %s Width x%d\n",
6350                             speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
6351                             speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
6352                             speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
6353                             "Unknown", width);
6354 }
6355
6356 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6357 {
6358         static int version_printed;
6359         struct net_device *dev;
6360         struct bnxt *bp;
6361         int rc, max_irqs;
6362
6363         if (version_printed++ == 0)
6364                 pr_info("%s", version);
6365
6366         max_irqs = bnxt_get_max_irq(pdev);
6367         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
6368         if (!dev)
6369                 return -ENOMEM;
6370
6371         bp = netdev_priv(dev);
6372
6373         if (bnxt_vf_pciid(ent->driver_data))
6374                 bp->flags |= BNXT_FLAG_VF;
6375
6376         if (pdev->msix_cap)
6377                 bp->flags |= BNXT_FLAG_MSIX_CAP;
6378
6379         rc = bnxt_init_board(pdev, dev);
6380         if (rc < 0)
6381                 goto init_err_free;
6382
6383         dev->netdev_ops = &bnxt_netdev_ops;
6384         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
6385         dev->ethtool_ops = &bnxt_ethtool_ops;
6386
6387         pci_set_drvdata(pdev, dev);
6388
6389         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6390                            NETIF_F_TSO | NETIF_F_TSO6 |
6391                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6392                            NETIF_F_GSO_IPXIP4 |
6393                            NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6394                            NETIF_F_GSO_PARTIAL | NETIF_F_RXHASH |
6395                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
6396
6397         dev->hw_enc_features =
6398                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
6399                         NETIF_F_TSO | NETIF_F_TSO6 |
6400                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
6401                         NETIF_F_GSO_UDP_TUNNEL_CSUM | NETIF_F_GSO_GRE_CSUM |
6402                         NETIF_F_GSO_IPXIP4 | NETIF_F_GSO_PARTIAL;
6403         dev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM |
6404                                     NETIF_F_GSO_GRE_CSUM;
6405         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
6406         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
6407                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
6408         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
6409         dev->priv_flags |= IFF_UNICAST_FLT;
6410
6411 #ifdef CONFIG_BNXT_SRIOV
6412         init_waitqueue_head(&bp->sriov_cfg_wait);
6413 #endif
6414         rc = bnxt_alloc_hwrm_resources(bp);
6415         if (rc)
6416                 goto init_err;
6417
6418         mutex_init(&bp->hwrm_cmd_lock);
6419         rc = bnxt_hwrm_ver_get(bp);
6420         if (rc)
6421                 goto init_err;
6422
6423         rc = bnxt_hwrm_func_drv_rgtr(bp);
6424         if (rc)
6425                 goto init_err;
6426
6427         /* Get the MAX capabilities for this function */
6428         rc = bnxt_hwrm_func_qcaps(bp);
6429         if (rc) {
6430                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
6431                            rc);
6432                 rc = -1;
6433                 goto init_err;
6434         }
6435
6436         rc = bnxt_hwrm_queue_qportcfg(bp);
6437         if (rc) {
6438                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
6439                            rc);
6440                 rc = -1;
6441                 goto init_err;
6442         }
6443
6444         bnxt_hwrm_func_qcfg(bp);
6445
6446         bnxt_set_tpa_flags(bp);
6447         bnxt_set_ring_params(bp);
6448         if (BNXT_PF(bp))
6449                 bp->pf.max_irqs = max_irqs;
6450 #if defined(CONFIG_BNXT_SRIOV)
6451         else
6452                 bp->vf.max_irqs = max_irqs;
6453 #endif
6454         bnxt_set_dflt_rings(bp);
6455
6456         if (BNXT_PF(bp)) {
6457                 dev->hw_features |= NETIF_F_NTUPLE;
6458                 if (bnxt_rfs_capable(bp)) {
6459                         bp->flags |= BNXT_FLAG_RFS;
6460                         dev->features |= NETIF_F_NTUPLE;
6461                 }
6462         }
6463
6464         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
6465                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
6466
6467         rc = bnxt_probe_phy(bp);
6468         if (rc)
6469                 goto init_err;
6470
6471         rc = register_netdev(dev);
6472         if (rc)
6473                 goto init_err;
6474
6475         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
6476                     board_info[ent->driver_data].name,
6477                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
6478
6479         bnxt_parse_log_pcie_link(bp);
6480
6481         return 0;
6482
6483 init_err:
6484         pci_iounmap(pdev, bp->bar0);
6485         pci_release_regions(pdev);
6486         pci_disable_device(pdev);
6487
6488 init_err_free:
6489         free_netdev(dev);
6490         return rc;
6491 }
6492
6493 /**
6494  * bnxt_io_error_detected - called when PCI error is detected
6495  * @pdev: Pointer to PCI device
6496  * @state: The current pci connection state
6497  *
6498  * This function is called after a PCI bus error affecting
6499  * this device has been detected.
6500  */
6501 static pci_ers_result_t bnxt_io_error_detected(struct pci_dev *pdev,
6502                                                pci_channel_state_t state)
6503 {
6504         struct net_device *netdev = pci_get_drvdata(pdev);
6505
6506         netdev_info(netdev, "PCI I/O error detected\n");
6507
6508         rtnl_lock();
6509         netif_device_detach(netdev);
6510
6511         if (state == pci_channel_io_perm_failure) {
6512                 rtnl_unlock();
6513                 return PCI_ERS_RESULT_DISCONNECT;
6514         }
6515
6516         if (netif_running(netdev))
6517                 bnxt_close(netdev);
6518
6519         pci_disable_device(pdev);
6520         rtnl_unlock();
6521
6522         /* Request a slot slot reset. */
6523         return PCI_ERS_RESULT_NEED_RESET;
6524 }
6525
6526 /**
6527  * bnxt_io_slot_reset - called after the pci bus has been reset.
6528  * @pdev: Pointer to PCI device
6529  *
6530  * Restart the card from scratch, as if from a cold-boot.
6531  * At this point, the card has exprienced a hard reset,
6532  * followed by fixups by BIOS, and has its config space
6533  * set up identically to what it was at cold boot.
6534  */
6535 static pci_ers_result_t bnxt_io_slot_reset(struct pci_dev *pdev)
6536 {
6537         struct net_device *netdev = pci_get_drvdata(pdev);
6538         struct bnxt *bp = netdev_priv(netdev);
6539         int err = 0;
6540         pci_ers_result_t result = PCI_ERS_RESULT_DISCONNECT;
6541
6542         netdev_info(bp->dev, "PCI Slot Reset\n");
6543
6544         rtnl_lock();
6545
6546         if (pci_enable_device(pdev)) {
6547                 dev_err(&pdev->dev,
6548                         "Cannot re-enable PCI device after reset.\n");
6549         } else {
6550                 pci_set_master(pdev);
6551
6552                 if (netif_running(netdev))
6553                         err = bnxt_open(netdev);
6554
6555                 if (!err)
6556                         result = PCI_ERS_RESULT_RECOVERED;
6557         }
6558
6559         if (result != PCI_ERS_RESULT_RECOVERED && netif_running(netdev))
6560                 dev_close(netdev);
6561
6562         rtnl_unlock();
6563
6564         err = pci_cleanup_aer_uncorrect_error_status(pdev);
6565         if (err) {
6566                 dev_err(&pdev->dev,
6567                         "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
6568                          err); /* non-fatal, continue */
6569         }
6570
6571         return PCI_ERS_RESULT_RECOVERED;
6572 }
6573
6574 /**
6575  * bnxt_io_resume - called when traffic can start flowing again.
6576  * @pdev: Pointer to PCI device
6577  *
6578  * This callback is called when the error recovery driver tells
6579  * us that its OK to resume normal operation.
6580  */
6581 static void bnxt_io_resume(struct pci_dev *pdev)
6582 {
6583         struct net_device *netdev = pci_get_drvdata(pdev);
6584
6585         rtnl_lock();
6586
6587         netif_device_attach(netdev);
6588
6589         rtnl_unlock();
6590 }
6591
6592 static const struct pci_error_handlers bnxt_err_handler = {
6593         .error_detected = bnxt_io_error_detected,
6594         .slot_reset     = bnxt_io_slot_reset,
6595         .resume         = bnxt_io_resume
6596 };
6597
6598 static struct pci_driver bnxt_pci_driver = {
6599         .name           = DRV_MODULE_NAME,
6600         .id_table       = bnxt_pci_tbl,
6601         .probe          = bnxt_init_one,
6602         .remove         = bnxt_remove_one,
6603         .err_handler    = &bnxt_err_handler,
6604 #if defined(CONFIG_BNXT_SRIOV)
6605         .sriov_configure = bnxt_sriov_configure,
6606 #endif
6607 };
6608
6609 module_pci_driver(bnxt_pci_driver);