drivers/net/ethernet/broadcom/bnxt/bnxt.c

   1 /* Broadcom NetXtreme-C/E network driver.
   2  *
   3  * Copyright (c) 2014-2015 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  */
   9
  10 #include <linux/module.h>
  11
  12 #include <linux/stringify.h>
  13 #include <linux/kernel.h>
  14 #include <linux/timer.h>
  15 #include <linux/errno.h>
  16 #include <linux/ioport.h>
  17 #include <linux/slab.h>
  18 #include <linux/vmalloc.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/pci.h>
  21 #include <linux/netdevice.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/skbuff.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/bitops.h>
  26 #include <linux/io.h>
  27 #include <linux/irq.h>
  28 #include <linux/delay.h>
  29 #include <asm/byteorder.h>
  30 #include <asm/page.h>
  31 #include <linux/time.h>
  32 #include <linux/mii.h>
  33 #include <linux/if.h>
  34 #include <linux/if_vlan.h>
  35 #include <net/ip.h>
  36 #include <net/tcp.h>
  37 #include <net/udp.h>
  38 #include <net/checksum.h>
  39 #include <net/ip6_checksum.h>
  40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
  41 #include <net/vxlan.h>
  42 #endif
  43 #ifdef CONFIG_NET_RX_BUSY_POLL
  44 #include <net/busy_poll.h>
  45 #endif
  46 #include <linux/workqueue.h>
  47 #include <linux/prefetch.h>
  48 #include <linux/cache.h>
  49 #include <linux/log2.h>
  50 #include <linux/aer.h>
  51 #include <linux/bitmap.h>
  52 #include <linux/cpu_rmap.h>
  53
  54 #include "bnxt_hsi.h"
  55 #include "bnxt.h"
  56 #include "bnxt_sriov.h"
  57 #include "bnxt_ethtool.h"
  58
  59 #define BNXT_TX_TIMEOUT         (5 * HZ)
  60
  61 static const char version[] =
  62         "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION "\n";
  63
  64 MODULE_LICENSE("GPL");
  65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
  66 MODULE_VERSION(DRV_MODULE_VERSION);
  67
  68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
  69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
  70 #define BNXT_RX_COPY_THRESH 256
  71
  72 #define BNXT_TX_PUSH_THRESH 92
  73
  74 enum board_idx {
  75         BCM57301,
  76         BCM57302,
  77         BCM57304,
  78         BCM57402,
  79         BCM57404,
  80         BCM57406,
  81         BCM57304_VF,
  82         BCM57404_VF,
  83 };
  84
  85 /* indexed by enum above */
  86 static const struct {
  87         char *name;
  88 } board_info[] = {
  89         { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
  90         { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
  91         { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
  92         { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
  93         { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
  94         { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
  95         { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
  96         { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
  97 };
  98
  99 static const struct pci_device_id bnxt_pci_tbl[] = {
 100         { PCI_VDEVICE(BROADCOM, 0x16c8), .driver_data = BCM57301 },
 101         { PCI_VDEVICE(BROADCOM, 0x16c9), .driver_data = BCM57302 },
 102         { PCI_VDEVICE(BROADCOM, 0x16ca), .driver_data = BCM57304 },
 103         { PCI_VDEVICE(BROADCOM, 0x16d0), .driver_data = BCM57402 },
 104         { PCI_VDEVICE(BROADCOM, 0x16d1), .driver_data = BCM57404 },
 105         { PCI_VDEVICE(BROADCOM, 0x16d2), .driver_data = BCM57406 },
 106 #ifdef CONFIG_BNXT_SRIOV
 107         { PCI_VDEVICE(BROADCOM, 0x16cb), .driver_data = BCM57304_VF },
 108         { PCI_VDEVICE(BROADCOM, 0x16d3), .driver_data = BCM57404_VF },
 109 #endif
 110         { 0 }
 111 };
 112
 113 MODULE_DEVICE_TABLE(pci, bnxt_pci_tbl);
 114
 115 static const u16 bnxt_vf_req_snif[] = {
 116         HWRM_FUNC_CFG,
 117         HWRM_PORT_PHY_QCFG,
 118         HWRM_CFA_L2_FILTER_ALLOC,
 119 };
 120
 121 static bool bnxt_vf_pciid(enum board_idx idx)
 122 {
 123         return (idx == BCM57304_VF || idx == BCM57404_VF);
 124 }
 125
 126 #define DB_CP_REARM_FLAGS       (DB_KEY_CP | DB_IDX_VALID)
 127 #define DB_CP_FLAGS             (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
 128 #define DB_CP_IRQ_DIS_FLAGS     (DB_KEY_CP | DB_IRQ_DIS)
 129
 130 #define BNXT_CP_DB_REARM(db, raw_cons)                                  \
 131                 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
 132
 133 #define BNXT_CP_DB(db, raw_cons)                                        \
 134                 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
 135
 136 #define BNXT_CP_DB_IRQ_DIS(db)                                          \
 137                 writel(DB_CP_IRQ_DIS_FLAGS, db)
 138
 139 static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
 140 {
 141         /* Tell compiler to fetch tx indices from memory. */
 142         barrier();
 143
 144         return bp->tx_ring_size -
 145                 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
 146 }
 147
 148 static const u16 bnxt_lhint_arr[] = {
 149         TX_BD_FLAGS_LHINT_512_AND_SMALLER,
 150         TX_BD_FLAGS_LHINT_512_TO_1023,
 151         TX_BD_FLAGS_LHINT_1024_TO_2047,
 152         TX_BD_FLAGS_LHINT_1024_TO_2047,
 153         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 154         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 155         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 156         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 157         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 158         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 159         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 160         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 161         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 162         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 163         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 164         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 165         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 166         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 167         TX_BD_FLAGS_LHINT_2048_AND_LARGER,
 168 };
 169
 170 static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev)
 171 {
 172         struct bnxt *bp = netdev_priv(dev);
 173         struct tx_bd *txbd;
 174         struct tx_bd_ext *txbd1;
 175         struct netdev_queue *txq;
 176         int i;
 177         dma_addr_t mapping;
 178         unsigned int length, pad = 0;
 179         u32 len, free_size, vlan_tag_flags, cfa_action, flags;
 180         u16 prod, last_frag;
 181         struct pci_dev *pdev = bp->pdev;
 182         struct bnxt_tx_ring_info *txr;
 183         struct bnxt_sw_tx_bd *tx_buf;
 184
 185         i = skb_get_queue_mapping(skb);
 186         if (unlikely(i >= bp->tx_nr_rings)) {
 187                 dev_kfree_skb_any(skb);
 188                 return NETDEV_TX_OK;
 189         }
 190
 191         txr = &bp->tx_ring[i];
 192         txq = netdev_get_tx_queue(dev, i);
 193         prod = txr->tx_prod;
 194
 195         free_size = bnxt_tx_avail(bp, txr);
 196         if (unlikely(free_size < skb_shinfo(skb)->nr_frags + 2)) {
 197                 netif_tx_stop_queue(txq);
 198                 return NETDEV_TX_BUSY;
 199         }
 200
 201         length = skb->len;
 202         len = skb_headlen(skb);
 203         last_frag = skb_shinfo(skb)->nr_frags;
 204
 205         txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 206
 207         txbd->tx_bd_opaque = prod;
 208
 209         tx_buf = &txr->tx_buf_ring[prod];
 210         tx_buf->skb = skb;
 211         tx_buf->nr_frags = last_frag;
 212
 213         vlan_tag_flags = 0;
 214         cfa_action = 0;
 215         if (skb_vlan_tag_present(skb)) {
 216                 vlan_tag_flags = TX_BD_CFA_META_KEY_VLAN |
 217                                  skb_vlan_tag_get(skb);
 218                 /* Currently supports 8021Q, 8021AD vlan offloads
 219                  * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
 220                  */
 221                 if (skb->vlan_proto == htons(ETH_P_8021Q))
 222                         vlan_tag_flags |= 1 << TX_BD_CFA_META_TPID_SHIFT;
 223         }
 224
 225         if (free_size == bp->tx_ring_size && length <= bp->tx_push_thresh) {
 226                 struct tx_push_bd *push = txr->tx_push;
 227                 struct tx_bd *tx_push = &push->txbd1;
 228                 struct tx_bd_ext *tx_push1 = &push->txbd2;
 229                 void *pdata = tx_push1 + 1;
 230                 int j;
 231
 232                 /* Set COAL_NOW to be ready quickly for the next push */
 233                 tx_push->tx_bd_len_flags_type =
 234                         cpu_to_le32((length << TX_BD_LEN_SHIFT) |
 235                                         TX_BD_TYPE_LONG_TX_BD |
 236                                         TX_BD_FLAGS_LHINT_512_AND_SMALLER |
 237                                         TX_BD_FLAGS_COAL_NOW |
 238                                         TX_BD_FLAGS_PACKET_END |
 239                                         (2 << TX_BD_FLAGS_BD_CNT_SHIFT));
 240
 241                 if (skb->ip_summed == CHECKSUM_PARTIAL)
 242                         tx_push1->tx_bd_hsize_lflags =
 243                                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 244                 else
 245                         tx_push1->tx_bd_hsize_lflags = 0;
 246
 247                 tx_push1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 248                 tx_push1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 249
 250                 skb_copy_from_linear_data(skb, pdata, len);
 251                 pdata += len;
 252                 for (j = 0; j < last_frag; j++) {
 253                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
 254                         void *fptr;
 255
 256                         fptr = skb_frag_address_safe(frag);
 257                         if (!fptr)
 258                                 goto normal_tx;
 259
 260                         memcpy(pdata, fptr, skb_frag_size(frag));
 261                         pdata += skb_frag_size(frag);
 262                 }
 263
 264                 memcpy(txbd, tx_push, sizeof(*txbd));
 265                 prod = NEXT_TX(prod);
 266                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 267                 memcpy(txbd, tx_push1, sizeof(*txbd));
 268                 prod = NEXT_TX(prod);
 269                 push->doorbell =
 270                         cpu_to_le32(DB_KEY_TX_PUSH | DB_LONG_TX_PUSH | prod);
 271                 txr->tx_prod = prod;
 272
 273                 netdev_tx_sent_queue(txq, skb->len);
 274
 275                 __iowrite64_copy(txr->tx_doorbell, push,
 276                                  (length + sizeof(*push) + 8) / 8);
 277
 278                 tx_buf->is_push = 1;
 279
 280                 goto tx_done;
 281         }
 282
 283 normal_tx:
 284         if (length < BNXT_MIN_PKT_SIZE) {
 285                 pad = BNXT_MIN_PKT_SIZE - length;
 286                 if (skb_pad(skb, pad)) {
 287                         /* SKB already freed. */
 288                         tx_buf->skb = NULL;
 289                         return NETDEV_TX_OK;
 290                 }
 291                 length = BNXT_MIN_PKT_SIZE;
 292         }
 293
 294         mapping = dma_map_single(&pdev->dev, skb->data, len, DMA_TO_DEVICE);
 295
 296         if (unlikely(dma_mapping_error(&pdev->dev, mapping))) {
 297                 dev_kfree_skb_any(skb);
 298                 tx_buf->skb = NULL;
 299                 return NETDEV_TX_OK;
 300         }
 301
 302         dma_unmap_addr_set(tx_buf, mapping, mapping);
 303         flags = (len << TX_BD_LEN_SHIFT) | TX_BD_TYPE_LONG_TX_BD |
 304                 ((last_frag + 2) << TX_BD_FLAGS_BD_CNT_SHIFT);
 305
 306         txbd->tx_bd_haddr = cpu_to_le64(mapping);
 307
 308         prod = NEXT_TX(prod);
 309         txbd1 = (struct tx_bd_ext *)
 310                 &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 311
 312         txbd1->tx_bd_hsize_lflags = 0;
 313         if (skb_is_gso(skb)) {
 314                 u32 hdr_len;
 315
 316                 if (skb->encapsulation)
 317                         hdr_len = skb_inner_network_offset(skb) +
 318                                 skb_inner_network_header_len(skb) +
 319                                 inner_tcp_hdrlen(skb);
 320                 else
 321                         hdr_len = skb_transport_offset(skb) +
 322                                 tcp_hdrlen(skb);
 323
 324                 txbd1->tx_bd_hsize_lflags = cpu_to_le32(TX_BD_FLAGS_LSO |
 325                                         TX_BD_FLAGS_T_IPID |
 326                                         (hdr_len << (TX_BD_HSIZE_SHIFT - 1)));
 327                 length = skb_shinfo(skb)->gso_size;
 328                 txbd1->tx_bd_mss = cpu_to_le32(length);
 329                 length += hdr_len;
 330         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 331                 txbd1->tx_bd_hsize_lflags =
 332                         cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM);
 333                 txbd1->tx_bd_mss = 0;
 334         }
 335
 336         length >>= 9;
 337         flags |= bnxt_lhint_arr[length];
 338         txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 339
 340         txbd1->tx_bd_cfa_meta = cpu_to_le32(vlan_tag_flags);
 341         txbd1->tx_bd_cfa_action = cpu_to_le32(cfa_action);
 342         for (i = 0; i < last_frag; i++) {
 343                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 344
 345                 prod = NEXT_TX(prod);
 346                 txbd = &txr->tx_desc_ring[TX_RING(prod)][TX_IDX(prod)];
 347
 348                 len = skb_frag_size(frag);
 349                 mapping = skb_frag_dma_map(&pdev->dev, frag, 0, len,
 350                                            DMA_TO_DEVICE);
 351
 352                 if (unlikely(dma_mapping_error(&pdev->dev, mapping)))
 353                         goto tx_dma_error;
 354
 355                 tx_buf = &txr->tx_buf_ring[prod];
 356                 dma_unmap_addr_set(tx_buf, mapping, mapping);
 357
 358                 txbd->tx_bd_haddr = cpu_to_le64(mapping);
 359
 360                 flags = len << TX_BD_LEN_SHIFT;
 361                 txbd->tx_bd_len_flags_type = cpu_to_le32(flags);
 362         }
 363
 364         flags &= ~TX_BD_LEN;
 365         txbd->tx_bd_len_flags_type =
 366                 cpu_to_le32(((len + pad) << TX_BD_LEN_SHIFT) | flags |
 367                             TX_BD_FLAGS_PACKET_END);
 368
 369         netdev_tx_sent_queue(txq, skb->len);
 370
 371         /* Sync BD data before updating doorbell */
 372         wmb();
 373
 374         prod = NEXT_TX(prod);
 375         txr->tx_prod = prod;
 376
 377         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 378         writel(DB_KEY_TX | prod, txr->tx_doorbell);
 379
 380 tx_done:
 381
 382         mmiowb();
 383
 384         if (unlikely(bnxt_tx_avail(bp, txr) <= MAX_SKB_FRAGS + 1)) {
 385                 netif_tx_stop_queue(txq);
 386
 387                 /* netif_tx_stop_queue() must be done before checking
 388                  * tx index in bnxt_tx_avail() below, because in
 389                  * bnxt_tx_int(), we update tx index before checking for
 390                  * netif_tx_queue_stopped().
 391                  */
 392                 smp_mb();
 393                 if (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)
 394                         netif_tx_wake_queue(txq);
 395         }
 396         return NETDEV_TX_OK;
 397
 398 tx_dma_error:
 399         last_frag = i;
 400
 401         /* start back at beginning and unmap skb */
 402         prod = txr->tx_prod;
 403         tx_buf = &txr->tx_buf_ring[prod];
 404         tx_buf->skb = NULL;
 405         dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 406                          skb_headlen(skb), PCI_DMA_TODEVICE);
 407         prod = NEXT_TX(prod);
 408
 409         /* unmap remaining mapped pages */
 410         for (i = 0; i < last_frag; i++) {
 411                 prod = NEXT_TX(prod);
 412                 tx_buf = &txr->tx_buf_ring[prod];
 413                 dma_unmap_page(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 414                                skb_frag_size(&skb_shinfo(skb)->frags[i]),
 415                                PCI_DMA_TODEVICE);
 416         }
 417
 418         dev_kfree_skb_any(skb);
 419         return NETDEV_TX_OK;
 420 }
 421
 422 static void bnxt_tx_int(struct bnxt *bp, struct bnxt_napi *bnapi, int nr_pkts)
 423 {
 424         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
 425         int index = txr - &bp->tx_ring[0];
 426         struct netdev_queue *txq = netdev_get_tx_queue(bp->dev, index);
 427         u16 cons = txr->tx_cons;
 428         struct pci_dev *pdev = bp->pdev;
 429         int i;
 430         unsigned int tx_bytes = 0;
 431
 432         for (i = 0; i < nr_pkts; i++) {
 433                 struct bnxt_sw_tx_bd *tx_buf;
 434                 struct sk_buff *skb;
 435                 int j, last;
 436
 437                 tx_buf = &txr->tx_buf_ring[cons];
 438                 cons = NEXT_TX(cons);
 439                 skb = tx_buf->skb;
 440                 tx_buf->skb = NULL;
 441
 442                 if (tx_buf->is_push) {
 443                         tx_buf->is_push = 0;
 444                         goto next_tx_int;
 445                 }
 446
 447                 dma_unmap_single(&pdev->dev, dma_unmap_addr(tx_buf, mapping),
 448                                  skb_headlen(skb), PCI_DMA_TODEVICE);
 449                 last = tx_buf->nr_frags;
 450
 451                 for (j = 0; j < last; j++) {
 452                         cons = NEXT_TX(cons);
 453                         tx_buf = &txr->tx_buf_ring[cons];
 454                         dma_unmap_page(
 455                                 &pdev->dev,
 456                                 dma_unmap_addr(tx_buf, mapping),
 457                                 skb_frag_size(&skb_shinfo(skb)->frags[j]),
 458                                 PCI_DMA_TODEVICE);
 459                 }
 460
 461 next_tx_int:
 462                 cons = NEXT_TX(cons);
 463
 464                 tx_bytes += skb->len;
 465                 dev_kfree_skb_any(skb);
 466         }
 467
 468         netdev_tx_completed_queue(txq, nr_pkts, tx_bytes);
 469         txr->tx_cons = cons;
 470
 471         /* Need to make the tx_cons update visible to bnxt_start_xmit()
 472          * before checking for netif_tx_queue_stopped().  Without the
 473          * memory barrier, there is a small possibility that bnxt_start_xmit()
 474          * will miss it and cause the queue to be stopped forever.
 475          */
 476         smp_mb();
 477
 478         if (unlikely(netif_tx_queue_stopped(txq)) &&
 479             (bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh)) {
 480                 __netif_tx_lock(txq, smp_processor_id());
 481                 if (netif_tx_queue_stopped(txq) &&
 482                     bnxt_tx_avail(bp, txr) > bp->tx_wake_thresh &&
 483                     txr->dev_state != BNXT_DEV_STATE_CLOSING)
 484                         netif_tx_wake_queue(txq);
 485                 __netif_tx_unlock(txq);
 486         }
 487 }
 488
 489 static inline u8 *__bnxt_alloc_rx_data(struct bnxt *bp, dma_addr_t *mapping,
 490                                        gfp_t gfp)
 491 {
 492         u8 *data;
 493         struct pci_dev *pdev = bp->pdev;
 494
 495         data = kmalloc(bp->rx_buf_size, gfp);
 496         if (!data)
 497                 return NULL;
 498
 499         *mapping = dma_map_single(&pdev->dev, data + BNXT_RX_DMA_OFFSET,
 500                                   bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
 501
 502         if (dma_mapping_error(&pdev->dev, *mapping)) {
 503                 kfree(data);
 504                 data = NULL;
 505         }
 506         return data;
 507 }
 508
 509 static inline int bnxt_alloc_rx_data(struct bnxt *bp,
 510                                      struct bnxt_rx_ring_info *rxr,
 511                                      u16 prod, gfp_t gfp)
 512 {
 513         struct rx_bd *rxbd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 514         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[prod];
 515         u8 *data;
 516         dma_addr_t mapping;
 517
 518         data = __bnxt_alloc_rx_data(bp, &mapping, gfp);
 519         if (!data)
 520                 return -ENOMEM;
 521
 522         rx_buf->data = data;
 523         dma_unmap_addr_set(rx_buf, mapping, mapping);
 524
 525         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 526
 527         return 0;
 528 }
 529
 530 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons,
 531                                u8 *data)
 532 {
 533         u16 prod = rxr->rx_prod;
 534         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 535         struct rx_bd *cons_bd, *prod_bd;
 536
 537         prod_rx_buf = &rxr->rx_buf_ring[prod];
 538         cons_rx_buf = &rxr->rx_buf_ring[cons];
 539
 540         prod_rx_buf->data = data;
 541
 542         dma_unmap_addr_set(prod_rx_buf, mapping,
 543                            dma_unmap_addr(cons_rx_buf, mapping));
 544
 545         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 546         cons_bd = &rxr->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
 547
 548         prod_bd->rx_bd_haddr = cons_bd->rx_bd_haddr;
 549 }
 550
 551 static inline u16 bnxt_find_next_agg_idx(struct bnxt_rx_ring_info *rxr, u16 idx)
 552 {
 553         u16 next, max = rxr->rx_agg_bmap_size;
 554
 555         next = find_next_zero_bit(rxr->rx_agg_bmap, max, idx);
 556         if (next >= max)
 557                 next = find_first_zero_bit(rxr->rx_agg_bmap, max);
 558         return next;
 559 }
 560
 561 static inline int bnxt_alloc_rx_page(struct bnxt *bp,
 562                                      struct bnxt_rx_ring_info *rxr,
 563                                      u16 prod, gfp_t gfp)
 564 {
 565         struct rx_bd *rxbd =
 566                 &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 567         struct bnxt_sw_rx_agg_bd *rx_agg_buf;
 568         struct pci_dev *pdev = bp->pdev;
 569         struct page *page;
 570         dma_addr_t mapping;
 571         u16 sw_prod = rxr->rx_sw_agg_prod;
 572
 573         page = alloc_page(gfp);
 574         if (!page)
 575                 return -ENOMEM;
 576
 577         mapping = dma_map_page(&pdev->dev, page, 0, PAGE_SIZE,
 578                                PCI_DMA_FROMDEVICE);
 579         if (dma_mapping_error(&pdev->dev, mapping)) {
 580                 __free_page(page);
 581                 return -EIO;
 582         }
 583
 584         if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 585                 sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 586
 587         __set_bit(sw_prod, rxr->rx_agg_bmap);
 588         rx_agg_buf = &rxr->rx_agg_ring[sw_prod];
 589         rxr->rx_sw_agg_prod = NEXT_RX_AGG(sw_prod);
 590
 591         rx_agg_buf->page = page;
 592         rx_agg_buf->mapping = mapping;
 593         rxbd->rx_bd_haddr = cpu_to_le64(mapping);
 594         rxbd->rx_bd_opaque = sw_prod;
 595         return 0;
 596 }
 597
 598 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi *bnapi, u16 cp_cons,
 599                                    u32 agg_bufs)
 600 {
 601         struct bnxt *bp = bnapi->bp;
 602         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 603         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 604         u16 prod = rxr->rx_agg_prod;
 605         u16 sw_prod = rxr->rx_sw_agg_prod;
 606         u32 i;
 607
 608         for (i = 0; i < agg_bufs; i++) {
 609                 u16 cons;
 610                 struct rx_agg_cmp *agg;
 611                 struct bnxt_sw_rx_agg_bd *cons_rx_buf, *prod_rx_buf;
 612                 struct rx_bd *prod_bd;
 613                 struct page *page;
 614
 615                 agg = (struct rx_agg_cmp *)
 616                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 617                 cons = agg->rx_agg_cmp_opaque;
 618                 __clear_bit(cons, rxr->rx_agg_bmap);
 619
 620                 if (unlikely(test_bit(sw_prod, rxr->rx_agg_bmap)))
 621                         sw_prod = bnxt_find_next_agg_idx(rxr, sw_prod);
 622
 623                 __set_bit(sw_prod, rxr->rx_agg_bmap);
 624                 prod_rx_buf = &rxr->rx_agg_ring[sw_prod];
 625                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 626
 627                 /* It is possible for sw_prod to be equal to cons, so
 628                  * set cons_rx_buf->page to NULL first.
 629                  */
 630                 page = cons_rx_buf->page;
 631                 cons_rx_buf->page = NULL;
 632                 prod_rx_buf->page = page;
 633
 634                 prod_rx_buf->mapping = cons_rx_buf->mapping;
 635
 636                 prod_bd = &rxr->rx_agg_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 637
 638                 prod_bd->rx_bd_haddr = cpu_to_le64(cons_rx_buf->mapping);
 639                 prod_bd->rx_bd_opaque = sw_prod;
 640
 641                 prod = NEXT_RX_AGG(prod);
 642                 sw_prod = NEXT_RX_AGG(sw_prod);
 643                 cp_cons = NEXT_CMP(cp_cons);
 644         }
 645         rxr->rx_agg_prod = prod;
 646         rxr->rx_sw_agg_prod = sw_prod;
 647 }
 648
 649 static struct sk_buff *bnxt_rx_skb(struct bnxt *bp,
 650                                    struct bnxt_rx_ring_info *rxr, u16 cons,
 651                                    u16 prod, u8 *data, dma_addr_t dma_addr,
 652                                    unsigned int len)
 653 {
 654         int err;
 655         struct sk_buff *skb;
 656
 657         err = bnxt_alloc_rx_data(bp, rxr, prod, GFP_ATOMIC);
 658         if (unlikely(err)) {
 659                 bnxt_reuse_rx_data(rxr, cons, data);
 660                 return NULL;
 661         }
 662
 663         skb = build_skb(data, 0);
 664         dma_unmap_single(&bp->pdev->dev, dma_addr, bp->rx_buf_use_size,
 665                          PCI_DMA_FROMDEVICE);
 666         if (!skb) {
 667                 kfree(data);
 668                 return NULL;
 669         }
 670
 671         skb_reserve(skb, BNXT_RX_OFFSET);
 672         skb_put(skb, len);
 673         return skb;
 674 }
 675
 676 static struct sk_buff *bnxt_rx_pages(struct bnxt *bp, struct bnxt_napi *bnapi,
 677                                      struct sk_buff *skb, u16 cp_cons,
 678                                      u32 agg_bufs)
 679 {
 680         struct pci_dev *pdev = bp->pdev;
 681         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 682         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 683         u16 prod = rxr->rx_agg_prod;
 684         u32 i;
 685
 686         for (i = 0; i < agg_bufs; i++) {
 687                 u16 cons, frag_len;
 688                 struct rx_agg_cmp *agg;
 689                 struct bnxt_sw_rx_agg_bd *cons_rx_buf;
 690                 struct page *page;
 691                 dma_addr_t mapping;
 692
 693                 agg = (struct rx_agg_cmp *)
 694                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
 695                 cons = agg->rx_agg_cmp_opaque;
 696                 frag_len = (le32_to_cpu(agg->rx_agg_cmp_len_flags_type) &
 697                             RX_AGG_CMP_LEN) >> RX_AGG_CMP_LEN_SHIFT;
 698
 699                 cons_rx_buf = &rxr->rx_agg_ring[cons];
 700                 skb_fill_page_desc(skb, i, cons_rx_buf->page, 0, frag_len);
 701                 __clear_bit(cons, rxr->rx_agg_bmap);
 702
 703                 /* It is possible for bnxt_alloc_rx_page() to allocate
 704                  * a sw_prod index that equals the cons index, so we
 705                  * need to clear the cons entry now.
 706                  */
 707                 mapping = dma_unmap_addr(cons_rx_buf, mapping);
 708                 page = cons_rx_buf->page;
 709                 cons_rx_buf->page = NULL;
 710
 711                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_ATOMIC) != 0) {
 712                         struct skb_shared_info *shinfo;
 713                         unsigned int nr_frags;
 714
 715                         shinfo = skb_shinfo(skb);
 716                         nr_frags = --shinfo->nr_frags;
 717                         __skb_frag_set_page(&shinfo->frags[nr_frags], NULL);
 718
 719                         dev_kfree_skb(skb);
 720
 721                         cons_rx_buf->page = page;
 722
 723                         /* Update prod since possibly some pages have been
 724                          * allocated already.
 725                          */
 726                         rxr->rx_agg_prod = prod;
 727                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs - i);
 728                         return NULL;
 729                 }
 730
 731                 dma_unmap_page(&pdev->dev, mapping, PAGE_SIZE,
 732                                PCI_DMA_FROMDEVICE);
 733
 734                 skb->data_len += frag_len;
 735                 skb->len += frag_len;
 736                 skb->truesize += PAGE_SIZE;
 737
 738                 prod = NEXT_RX_AGG(prod);
 739                 cp_cons = NEXT_CMP(cp_cons);
 740         }
 741         rxr->rx_agg_prod = prod;
 742         return skb;
 743 }
 744
 745 static int bnxt_agg_bufs_valid(struct bnxt *bp, struct bnxt_cp_ring_info *cpr,
 746                                u8 agg_bufs, u32 *raw_cons)
 747 {
 748         u16 last;
 749         struct rx_agg_cmp *agg;
 750
 751         *raw_cons = ADV_RAW_CMP(*raw_cons, agg_bufs);
 752         last = RING_CMP(*raw_cons);
 753         agg = (struct rx_agg_cmp *)
 754                 &cpr->cp_desc_ring[CP_RING(last)][CP_IDX(last)];
 755         return RX_AGG_CMP_VALID(agg, *raw_cons);
 756 }
 757
 758 static inline struct sk_buff *bnxt_copy_skb(struct bnxt_napi *bnapi, u8 *data,
 759                                             unsigned int len,
 760                                             dma_addr_t mapping)
 761 {
 762         struct bnxt *bp = bnapi->bp;
 763         struct pci_dev *pdev = bp->pdev;
 764         struct sk_buff *skb;
 765
 766         skb = napi_alloc_skb(&bnapi->napi, len);
 767         if (!skb)
 768                 return NULL;
 769
 770         dma_sync_single_for_cpu(&pdev->dev, mapping,
 771                                 bp->rx_copy_thresh, PCI_DMA_FROMDEVICE);
 772
 773         memcpy(skb->data - BNXT_RX_OFFSET, data, len + BNXT_RX_OFFSET);
 774
 775         dma_sync_single_for_device(&pdev->dev, mapping,
 776                                    bp->rx_copy_thresh,
 777                                    PCI_DMA_FROMDEVICE);
 778
 779         skb_put(skb, len);
 780         return skb;
 781 }
 782
 783 static void bnxt_tpa_start(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
 784                            struct rx_tpa_start_cmp *tpa_start,
 785                            struct rx_tpa_start_cmp_ext *tpa_start1)
 786 {
 787         u8 agg_id = TPA_START_AGG_ID(tpa_start);
 788         u16 cons, prod;
 789         struct bnxt_tpa_info *tpa_info;
 790         struct bnxt_sw_rx_bd *cons_rx_buf, *prod_rx_buf;
 791         struct rx_bd *prod_bd;
 792         dma_addr_t mapping;
 793
 794         cons = tpa_start->rx_tpa_start_cmp_opaque;
 795         prod = rxr->rx_prod;
 796         cons_rx_buf = &rxr->rx_buf_ring[cons];
 797         prod_rx_buf = &rxr->rx_buf_ring[prod];
 798         tpa_info = &rxr->rx_tpa[agg_id];
 799
 800         prod_rx_buf->data = tpa_info->data;
 801
 802         mapping = tpa_info->mapping;
 803         dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
 804
 805         prod_bd = &rxr->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
 806
 807         prod_bd->rx_bd_haddr = cpu_to_le64(mapping);
 808
 809         tpa_info->data = cons_rx_buf->data;
 810         cons_rx_buf->data = NULL;
 811         tpa_info->mapping = dma_unmap_addr(cons_rx_buf, mapping);
 812
 813         tpa_info->len =
 814                 le32_to_cpu(tpa_start->rx_tpa_start_cmp_len_flags_type) >>
 815                                 RX_TPA_START_CMP_LEN_SHIFT;
 816         if (likely(TPA_START_HASH_VALID(tpa_start))) {
 817                 u32 hash_type = TPA_START_HASH_TYPE(tpa_start);
 818
 819                 tpa_info->hash_type = PKT_HASH_TYPE_L4;
 820                 tpa_info->gso_type = SKB_GSO_TCPV4;
 821                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
 822                 if (hash_type == 3)
 823                         tpa_info->gso_type = SKB_GSO_TCPV6;
 824                 tpa_info->rss_hash =
 825                         le32_to_cpu(tpa_start->rx_tpa_start_cmp_rss_hash);
 826         } else {
 827                 tpa_info->hash_type = PKT_HASH_TYPE_NONE;
 828                 tpa_info->gso_type = 0;
 829                 if (netif_msg_rx_err(bp))
 830                         netdev_warn(bp->dev, "TPA packet without valid hash\n");
 831         }
 832         tpa_info->flags2 = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_flags2);
 833         tpa_info->metadata = le32_to_cpu(tpa_start1->rx_tpa_start_cmp_metadata);
 834
 835         rxr->rx_prod = NEXT_RX(prod);
 836         cons = NEXT_RX(cons);
 837         cons_rx_buf = &rxr->rx_buf_ring[cons];
 838
 839         bnxt_reuse_rx_data(rxr, cons, cons_rx_buf->data);
 840         rxr->rx_prod = NEXT_RX(rxr->rx_prod);
 841         cons_rx_buf->data = NULL;
 842 }
 843
 844 static void bnxt_abort_tpa(struct bnxt *bp, struct bnxt_napi *bnapi,
 845                            u16 cp_cons, u32 agg_bufs)
 846 {
 847         if (agg_bufs)
 848                 bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
 849 }
 850
 851 #define BNXT_IPV4_HDR_SIZE      (sizeof(struct iphdr) + sizeof(struct tcphdr))
 852 #define BNXT_IPV6_HDR_SIZE      (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
 853
 854 static inline struct sk_buff *bnxt_gro_skb(struct bnxt_tpa_info *tpa_info,
 855                                            struct rx_tpa_end_cmp *tpa_end,
 856                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 857                                            struct sk_buff *skb)
 858 {
 859 #ifdef CONFIG_INET
 860         struct tcphdr *th;
 861         int payload_off, tcp_opt_len = 0;
 862         int len, nw_off;
 863         u16 segs;
 864
 865         segs = TPA_END_TPA_SEGS(tpa_end);
 866         if (segs == 1)
 867                 return skb;
 868
 869         NAPI_GRO_CB(skb)->count = segs;
 870         skb_shinfo(skb)->gso_size =
 871                 le32_to_cpu(tpa_end1->rx_tpa_end_cmp_seg_len);
 872         skb_shinfo(skb)->gso_type = tpa_info->gso_type;
 873         payload_off = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 874                        RX_TPA_END_CMP_PAYLOAD_OFFSET) >>
 875                       RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT;
 876         if (TPA_END_GRO_TS(tpa_end))
 877                 tcp_opt_len = 12;
 878
 879         if (tpa_info->gso_type == SKB_GSO_TCPV4) {
 880                 struct iphdr *iph;
 881
 882                 nw_off = payload_off - BNXT_IPV4_HDR_SIZE - tcp_opt_len -
 883                          ETH_HLEN;
 884                 skb_set_network_header(skb, nw_off);
 885                 iph = ip_hdr(skb);
 886                 skb_set_transport_header(skb, nw_off + sizeof(struct iphdr));
 887                 len = skb->len - skb_transport_offset(skb);
 888                 th = tcp_hdr(skb);
 889                 th->check = ~tcp_v4_check(len, iph->saddr, iph->daddr, 0);
 890         } else if (tpa_info->gso_type == SKB_GSO_TCPV6) {
 891                 struct ipv6hdr *iph;
 892
 893                 nw_off = payload_off - BNXT_IPV6_HDR_SIZE - tcp_opt_len -
 894                          ETH_HLEN;
 895                 skb_set_network_header(skb, nw_off);
 896                 iph = ipv6_hdr(skb);
 897                 skb_set_transport_header(skb, nw_off + sizeof(struct ipv6hdr));
 898                 len = skb->len - skb_transport_offset(skb);
 899                 th = tcp_hdr(skb);
 900                 th->check = ~tcp_v6_check(len, &iph->saddr, &iph->daddr, 0);
 901         } else {
 902                 dev_kfree_skb_any(skb);
 903                 return NULL;
 904         }
 905         tcp_gro_complete(skb);
 906
 907         if (nw_off) { /* tunnel */
 908                 struct udphdr *uh = NULL;
 909
 910                 if (skb->protocol == htons(ETH_P_IP)) {
 911                         struct iphdr *iph = (struct iphdr *)skb->data;
 912
 913                         if (iph->protocol == IPPROTO_UDP)
 914                                 uh = (struct udphdr *)(iph + 1);
 915                 } else {
 916                         struct ipv6hdr *iph = (struct ipv6hdr *)skb->data;
 917
 918                         if (iph->nexthdr == IPPROTO_UDP)
 919                                 uh = (struct udphdr *)(iph + 1);
 920                 }
 921                 if (uh) {
 922                         if (uh->check)
 923                                 skb_shinfo(skb)->gso_type |=
 924                                         SKB_GSO_UDP_TUNNEL_CSUM;
 925                         else
 926                                 skb_shinfo(skb)->gso_type |= SKB_GSO_UDP_TUNNEL;
 927                 }
 928         }
 929 #endif
 930         return skb;
 931 }
 932
 933 static inline struct sk_buff *bnxt_tpa_end(struct bnxt *bp,
 934                                            struct bnxt_napi *bnapi,
 935                                            u32 *raw_cons,
 936                                            struct rx_tpa_end_cmp *tpa_end,
 937                                            struct rx_tpa_end_cmp_ext *tpa_end1,
 938                                            bool *agg_event)
 939 {
 940         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
 941         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
 942         u8 agg_id = TPA_END_AGG_ID(tpa_end);
 943         u8 *data, agg_bufs;
 944         u16 cp_cons = RING_CMP(*raw_cons);
 945         unsigned int len;
 946         struct bnxt_tpa_info *tpa_info;
 947         dma_addr_t mapping;
 948         struct sk_buff *skb;
 949
 950         tpa_info = &rxr->rx_tpa[agg_id];
 951         data = tpa_info->data;
 952         prefetch(data);
 953         len = tpa_info->len;
 954         mapping = tpa_info->mapping;
 955
 956         agg_bufs = (le32_to_cpu(tpa_end->rx_tpa_end_cmp_misc_v1) &
 957                     RX_TPA_END_CMP_AGG_BUFS) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT;
 958
 959         if (agg_bufs) {
 960                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, raw_cons))
 961                         return ERR_PTR(-EBUSY);
 962
 963                 *agg_event = true;
 964                 cp_cons = NEXT_CMP(cp_cons);
 965         }
 966
 967         if (unlikely(agg_bufs > MAX_SKB_FRAGS)) {
 968                 bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 969                 netdev_warn(bp->dev, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
 970                             agg_bufs, (int)MAX_SKB_FRAGS);
 971                 return NULL;
 972         }
 973
 974         if (len <= bp->rx_copy_thresh) {
 975                 skb = bnxt_copy_skb(bnapi, data, len, mapping);
 976                 if (!skb) {
 977                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 978                         return NULL;
 979                 }
 980         } else {
 981                 u8 *new_data;
 982                 dma_addr_t new_mapping;
 983
 984                 new_data = __bnxt_alloc_rx_data(bp, &new_mapping, GFP_ATOMIC);
 985                 if (!new_data) {
 986                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
 987                         return NULL;
 988                 }
 989
 990                 tpa_info->data = new_data;
 991                 tpa_info->mapping = new_mapping;
 992
 993                 skb = build_skb(data, 0);
 994                 dma_unmap_single(&bp->pdev->dev, mapping, bp->rx_buf_use_size,
 995                                  PCI_DMA_FROMDEVICE);
 996
 997                 if (!skb) {
 998                         kfree(data);
 999                         bnxt_abort_tpa(bp, bnapi, cp_cons, agg_bufs);
1000                         return NULL;
1001                 }
1002                 skb_reserve(skb, BNXT_RX_OFFSET);
1003                 skb_put(skb, len);
1004         }
1005
1006         if (agg_bufs) {
1007                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1008                 if (!skb) {
1009                         /* Page reuse already handled by bnxt_rx_pages(). */
1010                         return NULL;
1011                 }
1012         }
1013         skb->protocol = eth_type_trans(skb, bp->dev);
1014
1015         if (tpa_info->hash_type != PKT_HASH_TYPE_NONE)
1016                 skb_set_hash(skb, tpa_info->rss_hash, tpa_info->hash_type);
1017
1018         if (tpa_info->flags2 & RX_CMP_FLAGS2_META_FORMAT_VLAN) {
1019                 netdev_features_t features = skb->dev->features;
1020                 u16 vlan_proto = tpa_info->metadata >>
1021                         RX_CMP_FLAGS2_METADATA_TPID_SFT;
1022
1023                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1024                      vlan_proto == ETH_P_8021Q) ||
1025                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1026                      vlan_proto == ETH_P_8021AD)) {
1027                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1028                                                tpa_info->metadata &
1029                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1030                 }
1031         }
1032
1033         skb_checksum_none_assert(skb);
1034         if (likely(tpa_info->flags2 & RX_TPA_START_CMP_FLAGS2_L4_CS_CALC)) {
1035                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1036                 skb->csum_level =
1037                         (tpa_info->flags2 & RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3;
1038         }
1039
1040         if (TPA_END_GRO(tpa_end))
1041                 skb = bnxt_gro_skb(tpa_info, tpa_end, tpa_end1, skb);
1042
1043         return skb;
1044 }
1045
1046 /* returns the following:
1047  * 1       - 1 packet successfully received
1048  * 0       - successful TPA_START, packet not completed yet
1049  * -EBUSY  - completion ring does not have all the agg buffers yet
1050  * -ENOMEM - packet aborted due to out of memory
1051  * -EIO    - packet aborted due to hw error indicated in BD
1052  */
1053 static int bnxt_rx_pkt(struct bnxt *bp, struct bnxt_napi *bnapi, u32 *raw_cons,
1054                        bool *agg_event)
1055 {
1056         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1057         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1058         struct net_device *dev = bp->dev;
1059         struct rx_cmp *rxcmp;
1060         struct rx_cmp_ext *rxcmp1;
1061         u32 tmp_raw_cons = *raw_cons;
1062         u16 cons, prod, cp_cons = RING_CMP(tmp_raw_cons);
1063         struct bnxt_sw_rx_bd *rx_buf;
1064         unsigned int len;
1065         u8 *data, agg_bufs, cmp_type;
1066         dma_addr_t dma_addr;
1067         struct sk_buff *skb;
1068         int rc = 0;
1069
1070         rxcmp = (struct rx_cmp *)
1071                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1072
1073         tmp_raw_cons = NEXT_RAW_CMP(tmp_raw_cons);
1074         cp_cons = RING_CMP(tmp_raw_cons);
1075         rxcmp1 = (struct rx_cmp_ext *)
1076                         &cpr->cp_desc_ring[CP_RING(cp_cons)][CP_IDX(cp_cons)];
1077
1078         if (!RX_CMP_VALID(rxcmp1, tmp_raw_cons))
1079                 return -EBUSY;
1080
1081         cmp_type = RX_CMP_TYPE(rxcmp);
1082
1083         prod = rxr->rx_prod;
1084
1085         if (cmp_type == CMP_TYPE_RX_L2_TPA_START_CMP) {
1086                 bnxt_tpa_start(bp, rxr, (struct rx_tpa_start_cmp *)rxcmp,
1087                                (struct rx_tpa_start_cmp_ext *)rxcmp1);
1088
1089                 goto next_rx_no_prod;
1090
1091         } else if (cmp_type == CMP_TYPE_RX_L2_TPA_END_CMP) {
1092                 skb = bnxt_tpa_end(bp, bnapi, &tmp_raw_cons,
1093                                    (struct rx_tpa_end_cmp *)rxcmp,
1094                                    (struct rx_tpa_end_cmp_ext *)rxcmp1,
1095                                    agg_event);
1096
1097                 if (unlikely(IS_ERR(skb)))
1098                         return -EBUSY;
1099
1100                 rc = -ENOMEM;
1101                 if (likely(skb)) {
1102                         skb_record_rx_queue(skb, bnapi->index);
1103                         skb_mark_napi_id(skb, &bnapi->napi);
1104                         if (bnxt_busy_polling(bnapi))
1105                                 netif_receive_skb(skb);
1106                         else
1107                                 napi_gro_receive(&bnapi->napi, skb);
1108                         rc = 1;
1109                 }
1110                 goto next_rx_no_prod;
1111         }
1112
1113         cons = rxcmp->rx_cmp_opaque;
1114         rx_buf = &rxr->rx_buf_ring[cons];
1115         data = rx_buf->data;
1116         prefetch(data);
1117
1118         agg_bufs = (le32_to_cpu(rxcmp->rx_cmp_misc_v1) & RX_CMP_AGG_BUFS) >>
1119                                 RX_CMP_AGG_BUFS_SHIFT;
1120
1121         if (agg_bufs) {
1122                 if (!bnxt_agg_bufs_valid(bp, cpr, agg_bufs, &tmp_raw_cons))
1123                         return -EBUSY;
1124
1125                 cp_cons = NEXT_CMP(cp_cons);
1126                 *agg_event = true;
1127         }
1128
1129         rx_buf->data = NULL;
1130         if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L2_ERRORS) {
1131                 bnxt_reuse_rx_data(rxr, cons, data);
1132                 if (agg_bufs)
1133                         bnxt_reuse_rx_agg_bufs(bnapi, cp_cons, agg_bufs);
1134
1135                 rc = -EIO;
1136                 goto next_rx;
1137         }
1138
1139         len = le32_to_cpu(rxcmp->rx_cmp_len_flags_type) >> RX_CMP_LEN_SHIFT;
1140         dma_addr = dma_unmap_addr(rx_buf, mapping);
1141
1142         if (len <= bp->rx_copy_thresh) {
1143                 skb = bnxt_copy_skb(bnapi, data, len, dma_addr);
1144                 bnxt_reuse_rx_data(rxr, cons, data);
1145                 if (!skb) {
1146                         rc = -ENOMEM;
1147                         goto next_rx;
1148                 }
1149         } else {
1150                 skb = bnxt_rx_skb(bp, rxr, cons, prod, data, dma_addr, len);
1151                 if (!skb) {
1152                         rc = -ENOMEM;
1153                         goto next_rx;
1154                 }
1155         }
1156
1157         if (agg_bufs) {
1158                 skb = bnxt_rx_pages(bp, bnapi, skb, cp_cons, agg_bufs);
1159                 if (!skb) {
1160                         rc = -ENOMEM;
1161                         goto next_rx;
1162                 }
1163         }
1164
1165         if (RX_CMP_HASH_VALID(rxcmp)) {
1166                 u32 hash_type = RX_CMP_HASH_TYPE(rxcmp);
1167                 enum pkt_hash_types type = PKT_HASH_TYPE_L4;
1168
1169                 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1170                 if (hash_type != 1 && hash_type != 3)
1171                         type = PKT_HASH_TYPE_L3;
1172                 skb_set_hash(skb, le32_to_cpu(rxcmp->rx_cmp_rss_hash), type);
1173         }
1174
1175         skb->protocol = eth_type_trans(skb, dev);
1176
1177         if (rxcmp1->rx_cmp_flags2 &
1178             cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN)) {
1179                 netdev_features_t features = skb->dev->features;
1180                 u32 meta_data = le32_to_cpu(rxcmp1->rx_cmp_meta_data);
1181                 u16 vlan_proto = meta_data >> RX_CMP_FLAGS2_METADATA_TPID_SFT;
1182
1183                 if (((features & NETIF_F_HW_VLAN_CTAG_RX) &&
1184                      vlan_proto == ETH_P_8021Q) ||
1185                     ((features & NETIF_F_HW_VLAN_STAG_RX) &&
1186                      vlan_proto == ETH_P_8021AD))
1187                         __vlan_hwaccel_put_tag(skb, htons(vlan_proto),
1188                                                meta_data &
1189                                                RX_CMP_FLAGS2_METADATA_VID_MASK);
1190         }
1191
1192         skb_checksum_none_assert(skb);
1193         if (RX_CMP_L4_CS_OK(rxcmp1)) {
1194                 if (dev->features & NETIF_F_RXCSUM) {
1195                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1196                         skb->csum_level = RX_CMP_ENCAP(rxcmp1);
1197                 }
1198         } else {
1199                 if (rxcmp1->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS) {
1200                         if (dev->features & NETIF_F_RXCSUM)
1201                                 cpr->rx_l4_csum_errors++;
1202                 }
1203         }
1204
1205         skb_record_rx_queue(skb, bnapi->index);
1206         skb_mark_napi_id(skb, &bnapi->napi);
1207         if (bnxt_busy_polling(bnapi))
1208                 netif_receive_skb(skb);
1209         else
1210                 napi_gro_receive(&bnapi->napi, skb);
1211         rc = 1;
1212
1213 next_rx:
1214         rxr->rx_prod = NEXT_RX(prod);
1215
1216 next_rx_no_prod:
1217         *raw_cons = tmp_raw_cons;
1218
1219         return rc;
1220 }
1221
1222 static int bnxt_async_event_process(struct bnxt *bp,
1223                                     struct hwrm_async_event_cmpl *cmpl)
1224 {
1225         u16 event_id = le16_to_cpu(cmpl->event_id);
1226
1227         /* TODO CHIMP_FW: Define event id's for link change, error etc */
1228         switch (event_id) {
1229         case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE:
1230                 set_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event);
1231                 schedule_work(&bp->sp_task);
1232                 break;
1233         default:
1234                 netdev_err(bp->dev, "unhandled ASYNC event (id 0x%x)\n",
1235                            event_id);
1236                 break;
1237         }
1238         return 0;
1239 }
1240
1241 static int bnxt_hwrm_handler(struct bnxt *bp, struct tx_cmp *txcmp)
1242 {
1243         u16 cmpl_type = TX_CMP_TYPE(txcmp), vf_id, seq_id;
1244         struct hwrm_cmpl *h_cmpl = (struct hwrm_cmpl *)txcmp;
1245         struct hwrm_fwd_req_cmpl *fwd_req_cmpl =
1246                                 (struct hwrm_fwd_req_cmpl *)txcmp;
1247
1248         switch (cmpl_type) {
1249         case CMPL_BASE_TYPE_HWRM_DONE:
1250                 seq_id = le16_to_cpu(h_cmpl->sequence_id);
1251                 if (seq_id == bp->hwrm_intr_seq_id)
1252                         bp->hwrm_intr_seq_id = HWRM_SEQ_ID_INVALID;
1253                 else
1254                         netdev_err(bp->dev, "Invalid hwrm seq id %d\n", seq_id);
1255                 break;
1256
1257         case CMPL_BASE_TYPE_HWRM_FWD_REQ:
1258                 vf_id = le16_to_cpu(fwd_req_cmpl->source_id);
1259
1260                 if ((vf_id < bp->pf.first_vf_id) ||
1261                     (vf_id >= bp->pf.first_vf_id + bp->pf.active_vfs)) {
1262                         netdev_err(bp->dev, "Msg contains invalid VF id %x\n",
1263                                    vf_id);
1264                         return -EINVAL;
1265                 }
1266
1267                 set_bit(vf_id - bp->pf.first_vf_id, bp->pf.vf_event_bmap);
1268                 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event);
1269                 schedule_work(&bp->sp_task);
1270                 break;
1271
1272         case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT:
1273                 bnxt_async_event_process(bp,
1274                                          (struct hwrm_async_event_cmpl *)txcmp);
1275
1276         default:
1277                 break;
1278         }
1279
1280         return 0;
1281 }
1282
1283 static irqreturn_t bnxt_msix(int irq, void *dev_instance)
1284 {
1285         struct bnxt_napi *bnapi = dev_instance;
1286         struct bnxt *bp = bnapi->bp;
1287         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1288         u32 cons = RING_CMP(cpr->cp_raw_cons);
1289
1290         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1291         napi_schedule(&bnapi->napi);
1292         return IRQ_HANDLED;
1293 }
1294
1295 static inline int bnxt_has_work(struct bnxt *bp, struct bnxt_cp_ring_info *cpr)
1296 {
1297         u32 raw_cons = cpr->cp_raw_cons;
1298         u16 cons = RING_CMP(raw_cons);
1299         struct tx_cmp *txcmp;
1300
1301         txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1302
1303         return TX_CMP_VALID(txcmp, raw_cons);
1304 }
1305
1306 static irqreturn_t bnxt_inta(int irq, void *dev_instance)
1307 {
1308         struct bnxt_napi *bnapi = dev_instance;
1309         struct bnxt *bp = bnapi->bp;
1310         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1311         u32 cons = RING_CMP(cpr->cp_raw_cons);
1312         u32 int_status;
1313
1314         prefetch(&cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)]);
1315
1316         if (!bnxt_has_work(bp, cpr)) {
1317                 int_status = readl(bp->bar0 + BNXT_CAG_REG_LEGACY_INT_STATUS);
1318                 /* return if erroneous interrupt */
1319                 if (!(int_status & (0x10000 << cpr->cp_ring_struct.fw_ring_id)))
1320                         return IRQ_NONE;
1321         }
1322
1323         /* disable ring IRQ */
1324         BNXT_CP_DB_IRQ_DIS(cpr->cp_doorbell);
1325
1326         /* Return here if interrupt is shared and is disabled. */
1327         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1328                 return IRQ_HANDLED;
1329
1330         napi_schedule(&bnapi->napi);
1331         return IRQ_HANDLED;
1332 }
1333
1334 static int bnxt_poll_work(struct bnxt *bp, struct bnxt_napi *bnapi, int budget)
1335 {
1336         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1337         u32 raw_cons = cpr->cp_raw_cons;
1338         u32 cons;
1339         int tx_pkts = 0;
1340         int rx_pkts = 0;
1341         bool rx_event = false;
1342         bool agg_event = false;
1343         struct tx_cmp *txcmp;
1344
1345         while (1) {
1346                 int rc;
1347
1348                 cons = RING_CMP(raw_cons);
1349                 txcmp = &cpr->cp_desc_ring[CP_RING(cons)][CP_IDX(cons)];
1350
1351                 if (!TX_CMP_VALID(txcmp, raw_cons))
1352                         break;
1353
1354                 if (TX_CMP_TYPE(txcmp) == CMP_TYPE_TX_L2_CMP) {
1355                         tx_pkts++;
1356                         /* return full budget so NAPI will complete. */
1357                         if (unlikely(tx_pkts > bp->tx_wake_thresh))
1358                                 rx_pkts = budget;
1359                 } else if ((TX_CMP_TYPE(txcmp) & 0x30) == 0x10) {
1360                         rc = bnxt_rx_pkt(bp, bnapi, &raw_cons, &agg_event);
1361                         if (likely(rc >= 0))
1362                                 rx_pkts += rc;
1363                         else if (rc == -EBUSY)  /* partial completion */
1364                                 break;
1365                         rx_event = true;
1366                 } else if (unlikely((TX_CMP_TYPE(txcmp) ==
1367                                      CMPL_BASE_TYPE_HWRM_DONE) ||
1368                                     (TX_CMP_TYPE(txcmp) ==
1369                                      CMPL_BASE_TYPE_HWRM_FWD_REQ) ||
1370                                     (TX_CMP_TYPE(txcmp) ==
1371                                      CMPL_BASE_TYPE_HWRM_ASYNC_EVENT))) {
1372                         bnxt_hwrm_handler(bp, txcmp);
1373                 }
1374                 raw_cons = NEXT_RAW_CMP(raw_cons);
1375
1376                 if (rx_pkts == budget)
1377                         break;
1378         }
1379
1380         cpr->cp_raw_cons = raw_cons;
1381         /* ACK completion ring before freeing tx ring and producing new
1382          * buffers in rx/agg rings to prevent overflowing the completion
1383          * ring.
1384          */
1385         BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
1386
1387         if (tx_pkts)
1388                 bnxt_tx_int(bp, bnapi, tx_pkts);
1389
1390         if (rx_event) {
1391                 struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
1392
1393                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1394                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
1395                 if (agg_event) {
1396                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1397                                rxr->rx_agg_doorbell);
1398                         writel(DB_KEY_RX | rxr->rx_agg_prod,
1399                                rxr->rx_agg_doorbell);
1400                 }
1401         }
1402         return rx_pkts;
1403 }
1404
1405 static int bnxt_poll(struct napi_struct *napi, int budget)
1406 {
1407         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1408         struct bnxt *bp = bnapi->bp;
1409         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1410         int work_done = 0;
1411
1412         if (!bnxt_lock_napi(bnapi))
1413                 return budget;
1414
1415         while (1) {
1416                 work_done += bnxt_poll_work(bp, bnapi, budget - work_done);
1417
1418                 if (work_done >= budget)
1419                         break;
1420
1421                 if (!bnxt_has_work(bp, cpr)) {
1422                         napi_complete(napi);
1423                         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1424                         break;
1425                 }
1426         }
1427         mmiowb();
1428         bnxt_unlock_napi(bnapi);
1429         return work_done;
1430 }
1431
1432 #ifdef CONFIG_NET_RX_BUSY_POLL
1433 static int bnxt_busy_poll(struct napi_struct *napi)
1434 {
1435         struct bnxt_napi *bnapi = container_of(napi, struct bnxt_napi, napi);
1436         struct bnxt *bp = bnapi->bp;
1437         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
1438         int rx_work, budget = 4;
1439
1440         if (atomic_read(&bp->intr_sem) != 0)
1441                 return LL_FLUSH_FAILED;
1442
1443         if (!bnxt_lock_poll(bnapi))
1444                 return LL_FLUSH_BUSY;
1445
1446         rx_work = bnxt_poll_work(bp, bnapi, budget);
1447
1448         BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
1449
1450         bnxt_unlock_poll(bnapi);
1451         return rx_work;
1452 }
1453 #endif
1454
1455 static void bnxt_free_tx_skbs(struct bnxt *bp)
1456 {
1457         int i, max_idx;
1458         struct pci_dev *pdev = bp->pdev;
1459
1460         if (!bp->tx_ring)
1461                 return;
1462
1463         max_idx = bp->tx_nr_pages * TX_DESC_CNT;
1464         for (i = 0; i < bp->tx_nr_rings; i++) {
1465                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1466                 int j;
1467
1468                 for (j = 0; j < max_idx;) {
1469                         struct bnxt_sw_tx_bd *tx_buf = &txr->tx_buf_ring[j];
1470                         struct sk_buff *skb = tx_buf->skb;
1471                         int k, last;
1472
1473                         if (!skb) {
1474                                 j++;
1475                                 continue;
1476                         }
1477
1478                         tx_buf->skb = NULL;
1479
1480                         if (tx_buf->is_push) {
1481                                 dev_kfree_skb(skb);
1482                                 j += 2;
1483                                 continue;
1484                         }
1485
1486                         dma_unmap_single(&pdev->dev,
1487                                          dma_unmap_addr(tx_buf, mapping),
1488                                          skb_headlen(skb),
1489                                          PCI_DMA_TODEVICE);
1490
1491                         last = tx_buf->nr_frags;
1492                         j += 2;
1493                         for (k = 0; k < last; k++, j = NEXT_TX(j)) {
1494                                 skb_frag_t *frag = &skb_shinfo(skb)->frags[k];
1495
1496                                 tx_buf = &txr->tx_buf_ring[j];
1497                                 dma_unmap_page(
1498                                         &pdev->dev,
1499                                         dma_unmap_addr(tx_buf, mapping),
1500                                         skb_frag_size(frag), PCI_DMA_TODEVICE);
1501                         }
1502                         dev_kfree_skb(skb);
1503                 }
1504                 netdev_tx_reset_queue(netdev_get_tx_queue(bp->dev, i));
1505         }
1506 }
1507
1508 static void bnxt_free_rx_skbs(struct bnxt *bp)
1509 {
1510         int i, max_idx, max_agg_idx;
1511         struct pci_dev *pdev = bp->pdev;
1512
1513         if (!bp->rx_ring)
1514                 return;
1515
1516         max_idx = bp->rx_nr_pages * RX_DESC_CNT;
1517         max_agg_idx = bp->rx_agg_nr_pages * RX_DESC_CNT;
1518         for (i = 0; i < bp->rx_nr_rings; i++) {
1519                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1520                 int j;
1521
1522                 if (rxr->rx_tpa) {
1523                         for (j = 0; j < MAX_TPA; j++) {
1524                                 struct bnxt_tpa_info *tpa_info =
1525                                                         &rxr->rx_tpa[j];
1526                                 u8 *data = tpa_info->data;
1527
1528                                 if (!data)
1529                                         continue;
1530
1531                                 dma_unmap_single(
1532                                         &pdev->dev,
1533                                         dma_unmap_addr(tpa_info, mapping),
1534                                         bp->rx_buf_use_size,
1535                                         PCI_DMA_FROMDEVICE);
1536
1537                                 tpa_info->data = NULL;
1538
1539                                 kfree(data);
1540                         }
1541                 }
1542
1543                 for (j = 0; j < max_idx; j++) {
1544                         struct bnxt_sw_rx_bd *rx_buf = &rxr->rx_buf_ring[j];
1545                         u8 *data = rx_buf->data;
1546
1547                         if (!data)
1548                                 continue;
1549
1550                         dma_unmap_single(&pdev->dev,
1551                                          dma_unmap_addr(rx_buf, mapping),
1552                                          bp->rx_buf_use_size,
1553                                          PCI_DMA_FROMDEVICE);
1554
1555                         rx_buf->data = NULL;
1556
1557                         kfree(data);
1558                 }
1559
1560                 for (j = 0; j < max_agg_idx; j++) {
1561                         struct bnxt_sw_rx_agg_bd *rx_agg_buf =
1562                                 &rxr->rx_agg_ring[j];
1563                         struct page *page = rx_agg_buf->page;
1564
1565                         if (!page)
1566                                 continue;
1567
1568                         dma_unmap_page(&pdev->dev,
1569                                        dma_unmap_addr(rx_agg_buf, mapping),
1570                                        PAGE_SIZE, PCI_DMA_FROMDEVICE);
1571
1572                         rx_agg_buf->page = NULL;
1573                         __clear_bit(j, rxr->rx_agg_bmap);
1574
1575                         __free_page(page);
1576                 }
1577         }
1578 }
1579
1580 static void bnxt_free_skbs(struct bnxt *bp)
1581 {
1582         bnxt_free_tx_skbs(bp);
1583         bnxt_free_rx_skbs(bp);
1584 }
1585
1586 static void bnxt_free_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1587 {
1588         struct pci_dev *pdev = bp->pdev;
1589         int i;
1590
1591         for (i = 0; i < ring->nr_pages; i++) {
1592                 if (!ring->pg_arr[i])
1593                         continue;
1594
1595                 dma_free_coherent(&pdev->dev, ring->page_size,
1596                                   ring->pg_arr[i], ring->dma_arr[i]);
1597
1598                 ring->pg_arr[i] = NULL;
1599         }
1600         if (ring->pg_tbl) {
1601                 dma_free_coherent(&pdev->dev, ring->nr_pages * 8,
1602                                   ring->pg_tbl, ring->pg_tbl_map);
1603                 ring->pg_tbl = NULL;
1604         }
1605         if (ring->vmem_size && *ring->vmem) {
1606                 vfree(*ring->vmem);
1607                 *ring->vmem = NULL;
1608         }
1609 }
1610
1611 static int bnxt_alloc_ring(struct bnxt *bp, struct bnxt_ring_struct *ring)
1612 {
1613         int i;
1614         struct pci_dev *pdev = bp->pdev;
1615
1616         if (ring->nr_pages > 1) {
1617                 ring->pg_tbl = dma_alloc_coherent(&pdev->dev,
1618                                                   ring->nr_pages * 8,
1619                                                   &ring->pg_tbl_map,
1620                                                   GFP_KERNEL);
1621                 if (!ring->pg_tbl)
1622                         return -ENOMEM;
1623         }
1624
1625         for (i = 0; i < ring->nr_pages; i++) {
1626                 ring->pg_arr[i] = dma_alloc_coherent(&pdev->dev,
1627                                                      ring->page_size,
1628                                                      &ring->dma_arr[i],
1629                                                      GFP_KERNEL);
1630                 if (!ring->pg_arr[i])
1631                         return -ENOMEM;
1632
1633                 if (ring->nr_pages > 1)
1634                         ring->pg_tbl[i] = cpu_to_le64(ring->dma_arr[i]);
1635         }
1636
1637         if (ring->vmem_size) {
1638                 *ring->vmem = vzalloc(ring->vmem_size);
1639                 if (!(*ring->vmem))
1640                         return -ENOMEM;
1641         }
1642         return 0;
1643 }
1644
1645 static void bnxt_free_rx_rings(struct bnxt *bp)
1646 {
1647         int i;
1648
1649         if (!bp->rx_ring)
1650                 return;
1651
1652         for (i = 0; i < bp->rx_nr_rings; i++) {
1653                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1654                 struct bnxt_ring_struct *ring;
1655
1656                 kfree(rxr->rx_tpa);
1657                 rxr->rx_tpa = NULL;
1658
1659                 kfree(rxr->rx_agg_bmap);
1660                 rxr->rx_agg_bmap = NULL;
1661
1662                 ring = &rxr->rx_ring_struct;
1663                 bnxt_free_ring(bp, ring);
1664
1665                 ring = &rxr->rx_agg_ring_struct;
1666                 bnxt_free_ring(bp, ring);
1667         }
1668 }
1669
1670 static int bnxt_alloc_rx_rings(struct bnxt *bp)
1671 {
1672         int i, rc, agg_rings = 0, tpa_rings = 0;
1673
1674         if (!bp->rx_ring)
1675                 return -ENOMEM;
1676
1677         if (bp->flags & BNXT_FLAG_AGG_RINGS)
1678                 agg_rings = 1;
1679
1680         if (bp->flags & BNXT_FLAG_TPA)
1681                 tpa_rings = 1;
1682
1683         for (i = 0; i < bp->rx_nr_rings; i++) {
1684                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
1685                 struct bnxt_ring_struct *ring;
1686
1687                 ring = &rxr->rx_ring_struct;
1688
1689                 rc = bnxt_alloc_ring(bp, ring);
1690                 if (rc)
1691                         return rc;
1692
1693                 if (agg_rings) {
1694                         u16 mem_size;
1695
1696                         ring = &rxr->rx_agg_ring_struct;
1697                         rc = bnxt_alloc_ring(bp, ring);
1698                         if (rc)
1699                                 return rc;
1700
1701                         rxr->rx_agg_bmap_size = bp->rx_agg_ring_mask + 1;
1702                         mem_size = rxr->rx_agg_bmap_size / 8;
1703                         rxr->rx_agg_bmap = kzalloc(mem_size, GFP_KERNEL);
1704                         if (!rxr->rx_agg_bmap)
1705                                 return -ENOMEM;
1706
1707                         if (tpa_rings) {
1708                                 rxr->rx_tpa = kcalloc(MAX_TPA,
1709                                                 sizeof(struct bnxt_tpa_info),
1710                                                 GFP_KERNEL);
1711                                 if (!rxr->rx_tpa)
1712                                         return -ENOMEM;
1713                         }
1714                 }
1715         }
1716         return 0;
1717 }
1718
1719 static void bnxt_free_tx_rings(struct bnxt *bp)
1720 {
1721         int i;
1722         struct pci_dev *pdev = bp->pdev;
1723
1724         if (!bp->tx_ring)
1725                 return;
1726
1727         for (i = 0; i < bp->tx_nr_rings; i++) {
1728                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1729                 struct bnxt_ring_struct *ring;
1730
1731                 if (txr->tx_push) {
1732                         dma_free_coherent(&pdev->dev, bp->tx_push_size,
1733                                           txr->tx_push, txr->tx_push_mapping);
1734                         txr->tx_push = NULL;
1735                 }
1736
1737                 ring = &txr->tx_ring_struct;
1738
1739                 bnxt_free_ring(bp, ring);
1740         }
1741 }
1742
1743 static int bnxt_alloc_tx_rings(struct bnxt *bp)
1744 {
1745         int i, j, rc;
1746         struct pci_dev *pdev = bp->pdev;
1747
1748         bp->tx_push_size = 0;
1749         if (bp->tx_push_thresh) {
1750                 int push_size;
1751
1752                 push_size  = L1_CACHE_ALIGN(sizeof(struct tx_push_bd) +
1753                                         bp->tx_push_thresh);
1754
1755                 if (push_size > 128) {
1756                         push_size = 0;
1757                         bp->tx_push_thresh = 0;
1758                 }
1759
1760                 bp->tx_push_size = push_size;
1761         }
1762
1763         for (i = 0, j = 0; i < bp->tx_nr_rings; i++) {
1764                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
1765                 struct bnxt_ring_struct *ring;
1766
1767                 ring = &txr->tx_ring_struct;
1768
1769                 rc = bnxt_alloc_ring(bp, ring);
1770                 if (rc)
1771                         return rc;
1772
1773                 if (bp->tx_push_size) {
1774                         struct tx_bd *txbd;
1775                         dma_addr_t mapping;
1776
1777                         /* One pre-allocated DMA buffer to backup
1778                          * TX push operation
1779                          */
1780                         txr->tx_push = dma_alloc_coherent(&pdev->dev,
1781                                                 bp->tx_push_size,
1782                                                 &txr->tx_push_mapping,
1783                                                 GFP_KERNEL);
1784
1785                         if (!txr->tx_push)
1786                                 return -ENOMEM;
1787
1788                         txbd = &txr->tx_push->txbd1;
1789
1790                         mapping = txr->tx_push_mapping +
1791                                 sizeof(struct tx_push_bd);
1792                         txbd->tx_bd_haddr = cpu_to_le64(mapping);
1793
1794                         memset(txbd + 1, 0, sizeof(struct tx_bd_ext));
1795                 }
1796                 ring->queue_id = bp->q_info[j].queue_id;
1797                 if (i % bp->tx_nr_rings_per_tc == (bp->tx_nr_rings_per_tc - 1))
1798                         j++;
1799         }
1800         return 0;
1801 }
1802
1803 static void bnxt_free_cp_rings(struct bnxt *bp)
1804 {
1805         int i;
1806
1807         if (!bp->bnapi)
1808                 return;
1809
1810         for (i = 0; i < bp->cp_nr_rings; i++) {
1811                 struct bnxt_napi *bnapi = bp->bnapi[i];
1812                 struct bnxt_cp_ring_info *cpr;
1813                 struct bnxt_ring_struct *ring;
1814
1815                 if (!bnapi)
1816                         continue;
1817
1818                 cpr = &bnapi->cp_ring;
1819                 ring = &cpr->cp_ring_struct;
1820
1821                 bnxt_free_ring(bp, ring);
1822         }
1823 }
1824
1825 static int bnxt_alloc_cp_rings(struct bnxt *bp)
1826 {
1827         int i, rc;
1828
1829         for (i = 0; i < bp->cp_nr_rings; i++) {
1830                 struct bnxt_napi *bnapi = bp->bnapi[i];
1831                 struct bnxt_cp_ring_info *cpr;
1832                 struct bnxt_ring_struct *ring;
1833
1834                 if (!bnapi)
1835                         continue;
1836
1837                 cpr = &bnapi->cp_ring;
1838                 ring = &cpr->cp_ring_struct;
1839
1840                 rc = bnxt_alloc_ring(bp, ring);
1841                 if (rc)
1842                         return rc;
1843         }
1844         return 0;
1845 }
1846
1847 static void bnxt_init_ring_struct(struct bnxt *bp)
1848 {
1849         int i;
1850
1851         for (i = 0; i < bp->cp_nr_rings; i++) {
1852                 struct bnxt_napi *bnapi = bp->bnapi[i];
1853                 struct bnxt_cp_ring_info *cpr;
1854                 struct bnxt_rx_ring_info *rxr;
1855                 struct bnxt_tx_ring_info *txr;
1856                 struct bnxt_ring_struct *ring;
1857
1858                 if (!bnapi)
1859                         continue;
1860
1861                 cpr = &bnapi->cp_ring;
1862                 ring = &cpr->cp_ring_struct;
1863                 ring->nr_pages = bp->cp_nr_pages;
1864                 ring->page_size = HW_CMPD_RING_SIZE;
1865                 ring->pg_arr = (void **)cpr->cp_desc_ring;
1866                 ring->dma_arr = cpr->cp_desc_mapping;
1867                 ring->vmem_size = 0;
1868
1869                 rxr = bnapi->rx_ring;
1870                 if (!rxr)
1871                         goto skip_rx;
1872
1873                 ring = &rxr->rx_ring_struct;
1874                 ring->nr_pages = bp->rx_nr_pages;
1875                 ring->page_size = HW_RXBD_RING_SIZE;
1876                 ring->pg_arr = (void **)rxr->rx_desc_ring;
1877                 ring->dma_arr = rxr->rx_desc_mapping;
1878                 ring->vmem_size = SW_RXBD_RING_SIZE * bp->rx_nr_pages;
1879                 ring->vmem = (void **)&rxr->rx_buf_ring;
1880
1881                 ring = &rxr->rx_agg_ring_struct;
1882                 ring->nr_pages = bp->rx_agg_nr_pages;
1883                 ring->page_size = HW_RXBD_RING_SIZE;
1884                 ring->pg_arr = (void **)rxr->rx_agg_desc_ring;
1885                 ring->dma_arr = rxr->rx_agg_desc_mapping;
1886                 ring->vmem_size = SW_RXBD_AGG_RING_SIZE * bp->rx_agg_nr_pages;
1887                 ring->vmem = (void **)&rxr->rx_agg_ring;
1888
1889 skip_rx:
1890                 txr = bnapi->tx_ring;
1891                 if (!txr)
1892                         continue;
1893
1894                 ring = &txr->tx_ring_struct;
1895                 ring->nr_pages = bp->tx_nr_pages;
1896                 ring->page_size = HW_RXBD_RING_SIZE;
1897                 ring->pg_arr = (void **)txr->tx_desc_ring;
1898                 ring->dma_arr = txr->tx_desc_mapping;
1899                 ring->vmem_size = SW_TXBD_RING_SIZE * bp->tx_nr_pages;
1900                 ring->vmem = (void **)&txr->tx_buf_ring;
1901         }
1902 }
1903
1904 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct *ring, u32 type)
1905 {
1906         int i;
1907         u32 prod;
1908         struct rx_bd **rx_buf_ring;
1909
1910         rx_buf_ring = (struct rx_bd **)ring->pg_arr;
1911         for (i = 0, prod = 0; i < ring->nr_pages; i++) {
1912                 int j;
1913                 struct rx_bd *rxbd;
1914
1915                 rxbd = rx_buf_ring[i];
1916                 if (!rxbd)
1917                         continue;
1918
1919                 for (j = 0; j < RX_DESC_CNT; j++, rxbd++, prod++) {
1920                         rxbd->rx_bd_len_flags_type = cpu_to_le32(type);
1921                         rxbd->rx_bd_opaque = prod;
1922                 }
1923         }
1924 }
1925
1926 static int bnxt_init_one_rx_ring(struct bnxt *bp, int ring_nr)
1927 {
1928         struct net_device *dev = bp->dev;
1929         struct bnxt_rx_ring_info *rxr;
1930         struct bnxt_ring_struct *ring;
1931         u32 prod, type;
1932         int i;
1933
1934         type = (bp->rx_buf_use_size << RX_BD_LEN_SHIFT) |
1935                 RX_BD_TYPE_RX_PACKET_BD | RX_BD_FLAGS_EOP;
1936
1937         if (NET_IP_ALIGN == 2)
1938                 type |= RX_BD_FLAGS_SOP;
1939
1940         rxr = &bp->rx_ring[ring_nr];
1941         ring = &rxr->rx_ring_struct;
1942         bnxt_init_rxbd_pages(ring, type);
1943
1944         prod = rxr->rx_prod;
1945         for (i = 0; i < bp->rx_ring_size; i++) {
1946                 if (bnxt_alloc_rx_data(bp, rxr, prod, GFP_KERNEL) != 0) {
1947                         netdev_warn(dev, "init'ed rx ring %d with %d/%d skbs only\n",
1948                                     ring_nr, i, bp->rx_ring_size);
1949                         break;
1950                 }
1951                 prod = NEXT_RX(prod);
1952         }
1953         rxr->rx_prod = prod;
1954         ring->fw_ring_id = INVALID_HW_RING_ID;
1955
1956         ring = &rxr->rx_agg_ring_struct;
1957         ring->fw_ring_id = INVALID_HW_RING_ID;
1958
1959         if (!(bp->flags & BNXT_FLAG_AGG_RINGS))
1960                 return 0;
1961
1962         type = ((u32)PAGE_SIZE << RX_BD_LEN_SHIFT) |
1963                 RX_BD_TYPE_RX_AGG_BD | RX_BD_FLAGS_SOP;
1964
1965         bnxt_init_rxbd_pages(ring, type);
1966
1967         prod = rxr->rx_agg_prod;
1968         for (i = 0; i < bp->rx_agg_ring_size; i++) {
1969                 if (bnxt_alloc_rx_page(bp, rxr, prod, GFP_KERNEL) != 0) {
1970                         netdev_warn(dev, "init'ed rx ring %d with %d/%d pages only\n",
1971                                     ring_nr, i, bp->rx_ring_size);
1972                         break;
1973                 }
1974                 prod = NEXT_RX_AGG(prod);
1975         }
1976         rxr->rx_agg_prod = prod;
1977
1978         if (bp->flags & BNXT_FLAG_TPA) {
1979                 if (rxr->rx_tpa) {
1980                         u8 *data;
1981                         dma_addr_t mapping;
1982
1983                         for (i = 0; i < MAX_TPA; i++) {
1984                                 data = __bnxt_alloc_rx_data(bp, &mapping,
1985                                                             GFP_KERNEL);
1986                                 if (!data)
1987                                         return -ENOMEM;
1988
1989                                 rxr->rx_tpa[i].data = data;
1990                                 rxr->rx_tpa[i].mapping = mapping;
1991                         }
1992                 } else {
1993                         netdev_err(bp->dev, "No resource allocated for LRO/GRO\n");
1994                         return -ENOMEM;
1995                 }
1996         }
1997
1998         return 0;
1999 }
2000
2001 static int bnxt_init_rx_rings(struct bnxt *bp)
2002 {
2003         int i, rc = 0;
2004
2005         for (i = 0; i < bp->rx_nr_rings; i++) {
2006                 rc = bnxt_init_one_rx_ring(bp, i);
2007                 if (rc)
2008                         break;
2009         }
2010
2011         return rc;
2012 }
2013
2014 static int bnxt_init_tx_rings(struct bnxt *bp)
2015 {
2016         u16 i;
2017
2018         bp->tx_wake_thresh = max_t(int, bp->tx_ring_size / 2,
2019                                    MAX_SKB_FRAGS + 1);
2020
2021         for (i = 0; i < bp->tx_nr_rings; i++) {
2022                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
2023                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
2024
2025                 ring->fw_ring_id = INVALID_HW_RING_ID;
2026         }
2027
2028         return 0;
2029 }
2030
2031 static void bnxt_free_ring_grps(struct bnxt *bp)
2032 {
2033         kfree(bp->grp_info);
2034         bp->grp_info = NULL;
2035 }
2036
2037 static int bnxt_init_ring_grps(struct bnxt *bp, bool irq_re_init)
2038 {
2039         int i;
2040
2041         if (irq_re_init) {
2042                 bp->grp_info = kcalloc(bp->cp_nr_rings,
2043                                        sizeof(struct bnxt_ring_grp_info),
2044                                        GFP_KERNEL);
2045                 if (!bp->grp_info)
2046                         return -ENOMEM;
2047         }
2048         for (i = 0; i < bp->cp_nr_rings; i++) {
2049                 if (irq_re_init)
2050                         bp->grp_info[i].fw_stats_ctx = INVALID_HW_RING_ID;
2051                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
2052                 bp->grp_info[i].rx_fw_ring_id = INVALID_HW_RING_ID;
2053                 bp->grp_info[i].agg_fw_ring_id = INVALID_HW_RING_ID;
2054                 bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
2055         }
2056         return 0;
2057 }
2058
2059 static void bnxt_free_vnics(struct bnxt *bp)
2060 {
2061         kfree(bp->vnic_info);
2062         bp->vnic_info = NULL;
2063         bp->nr_vnics = 0;
2064 }
2065
2066 static int bnxt_alloc_vnics(struct bnxt *bp)
2067 {
2068         int num_vnics = 1;
2069
2070 #ifdef CONFIG_RFS_ACCEL
2071         if (bp->flags & BNXT_FLAG_RFS)
2072                 num_vnics += bp->rx_nr_rings;
2073 #endif
2074
2075         bp->vnic_info = kcalloc(num_vnics, sizeof(struct bnxt_vnic_info),
2076                                 GFP_KERNEL);
2077         if (!bp->vnic_info)
2078                 return -ENOMEM;
2079
2080         bp->nr_vnics = num_vnics;
2081         return 0;
2082 }
2083
2084 static void bnxt_init_vnics(struct bnxt *bp)
2085 {
2086         int i;
2087
2088         for (i = 0; i < bp->nr_vnics; i++) {
2089                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2090
2091                 vnic->fw_vnic_id = INVALID_HW_RING_ID;
2092                 vnic->fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
2093                 vnic->fw_l2_ctx_id = INVALID_HW_RING_ID;
2094
2095                 if (bp->vnic_info[i].rss_hash_key) {
2096                         if (i == 0)
2097                                 prandom_bytes(vnic->rss_hash_key,
2098                                               HW_HASH_KEY_SIZE);
2099                         else
2100                                 memcpy(vnic->rss_hash_key,
2101                                        bp->vnic_info[0].rss_hash_key,
2102                                        HW_HASH_KEY_SIZE);
2103                 }
2104         }
2105 }
2106
2107 static int bnxt_calc_nr_ring_pages(u32 ring_size, int desc_per_pg)
2108 {
2109         int pages;
2110
2111         pages = ring_size / desc_per_pg;
2112
2113         if (!pages)
2114                 return 1;
2115
2116         pages++;
2117
2118         while (pages & (pages - 1))
2119                 pages++;
2120
2121         return pages;
2122 }
2123
2124 static void bnxt_set_tpa_flags(struct bnxt *bp)
2125 {
2126         bp->flags &= ~BNXT_FLAG_TPA;
2127         if (bp->dev->features & NETIF_F_LRO)
2128                 bp->flags |= BNXT_FLAG_LRO;
2129         if ((bp->dev->features & NETIF_F_GRO) && (bp->pdev->revision > 0))
2130                 bp->flags |= BNXT_FLAG_GRO;
2131 }
2132
2133 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2134  * be set on entry.
2135  */
2136 void bnxt_set_ring_params(struct bnxt *bp)
2137 {
2138         u32 ring_size, rx_size, rx_space;
2139         u32 agg_factor = 0, agg_ring_size = 0;
2140
2141         /* 8 for CRC and VLAN */
2142         rx_size = SKB_DATA_ALIGN(bp->dev->mtu + ETH_HLEN + NET_IP_ALIGN + 8);
2143
2144         rx_space = rx_size + NET_SKB_PAD +
2145                 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2146
2147         bp->rx_copy_thresh = BNXT_RX_COPY_THRESH;
2148         ring_size = bp->rx_ring_size;
2149         bp->rx_agg_ring_size = 0;
2150         bp->rx_agg_nr_pages = 0;
2151
2152         if (bp->flags & BNXT_FLAG_TPA)
2153                 agg_factor = 4;
2154
2155         bp->flags &= ~BNXT_FLAG_JUMBO;
2156         if (rx_space > PAGE_SIZE) {
2157                 u32 jumbo_factor;
2158
2159                 bp->flags |= BNXT_FLAG_JUMBO;
2160                 jumbo_factor = PAGE_ALIGN(bp->dev->mtu - 40) >> PAGE_SHIFT;
2161                 if (jumbo_factor > agg_factor)
2162                         agg_factor = jumbo_factor;
2163         }
2164         agg_ring_size = ring_size * agg_factor;
2165
2166         if (agg_ring_size) {
2167                 bp->rx_agg_nr_pages = bnxt_calc_nr_ring_pages(agg_ring_size,
2168                                                         RX_DESC_CNT);
2169                 if (bp->rx_agg_nr_pages > MAX_RX_AGG_PAGES) {
2170                         u32 tmp = agg_ring_size;
2171
2172                         bp->rx_agg_nr_pages = MAX_RX_AGG_PAGES;
2173                         agg_ring_size = MAX_RX_AGG_PAGES * RX_DESC_CNT - 1;
2174                         netdev_warn(bp->dev, "rx agg ring size %d reduced to %d.\n",
2175                                     tmp, agg_ring_size);
2176                 }
2177                 bp->rx_agg_ring_size = agg_ring_size;
2178                 bp->rx_agg_ring_mask = (bp->rx_agg_nr_pages * RX_DESC_CNT) - 1;
2179                 rx_size = SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH + NET_IP_ALIGN);
2180                 rx_space = rx_size + NET_SKB_PAD +
2181                         SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
2182         }
2183
2184         bp->rx_buf_use_size = rx_size;
2185         bp->rx_buf_size = rx_space;
2186
2187         bp->rx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, RX_DESC_CNT);
2188         bp->rx_ring_mask = (bp->rx_nr_pages * RX_DESC_CNT) - 1;
2189
2190         ring_size = bp->tx_ring_size;
2191         bp->tx_nr_pages = bnxt_calc_nr_ring_pages(ring_size, TX_DESC_CNT);
2192         bp->tx_ring_mask = (bp->tx_nr_pages * TX_DESC_CNT) - 1;
2193
2194         ring_size = bp->rx_ring_size * (2 + agg_factor) + bp->tx_ring_size;
2195         bp->cp_ring_size = ring_size;
2196
2197         bp->cp_nr_pages = bnxt_calc_nr_ring_pages(ring_size, CP_DESC_CNT);
2198         if (bp->cp_nr_pages > MAX_CP_PAGES) {
2199                 bp->cp_nr_pages = MAX_CP_PAGES;
2200                 bp->cp_ring_size = MAX_CP_PAGES * CP_DESC_CNT - 1;
2201                 netdev_warn(bp->dev, "completion ring size %d reduced to %d.\n",
2202                             ring_size, bp->cp_ring_size);
2203         }
2204         bp->cp_bit = bp->cp_nr_pages * CP_DESC_CNT;
2205         bp->cp_ring_mask = bp->cp_bit - 1;
2206 }
2207
2208 static void bnxt_free_vnic_attributes(struct bnxt *bp)
2209 {
2210         int i;
2211         struct bnxt_vnic_info *vnic;
2212         struct pci_dev *pdev = bp->pdev;
2213
2214         if (!bp->vnic_info)
2215                 return;
2216
2217         for (i = 0; i < bp->nr_vnics; i++) {
2218                 vnic = &bp->vnic_info[i];
2219
2220                 kfree(vnic->fw_grp_ids);
2221                 vnic->fw_grp_ids = NULL;
2222
2223                 kfree(vnic->uc_list);
2224                 vnic->uc_list = NULL;
2225
2226                 if (vnic->mc_list) {
2227                         dma_free_coherent(&pdev->dev, vnic->mc_list_size,
2228                                           vnic->mc_list, vnic->mc_list_mapping);
2229                         vnic->mc_list = NULL;
2230                 }
2231
2232                 if (vnic->rss_table) {
2233                         dma_free_coherent(&pdev->dev, PAGE_SIZE,
2234                                           vnic->rss_table,
2235                                           vnic->rss_table_dma_addr);
2236                         vnic->rss_table = NULL;
2237                 }
2238
2239                 vnic->rss_hash_key = NULL;
2240                 vnic->flags = 0;
2241         }
2242 }
2243
2244 static int bnxt_alloc_vnic_attributes(struct bnxt *bp)
2245 {
2246         int i, rc = 0, size;
2247         struct bnxt_vnic_info *vnic;
2248         struct pci_dev *pdev = bp->pdev;
2249         int max_rings;
2250
2251         for (i = 0; i < bp->nr_vnics; i++) {
2252                 vnic = &bp->vnic_info[i];
2253
2254                 if (vnic->flags & BNXT_VNIC_UCAST_FLAG) {
2255                         int mem_size = (BNXT_MAX_UC_ADDRS - 1) * ETH_ALEN;
2256
2257                         if (mem_size > 0) {
2258                                 vnic->uc_list = kmalloc(mem_size, GFP_KERNEL);
2259                                 if (!vnic->uc_list) {
2260                                         rc = -ENOMEM;
2261                                         goto out;
2262                                 }
2263                         }
2264                 }
2265
2266                 if (vnic->flags & BNXT_VNIC_MCAST_FLAG) {
2267                         vnic->mc_list_size = BNXT_MAX_MC_ADDRS * ETH_ALEN;
2268                         vnic->mc_list =
2269                                 dma_alloc_coherent(&pdev->dev,
2270                                                    vnic->mc_list_size,
2271                                                    &vnic->mc_list_mapping,
2272                                                    GFP_KERNEL);
2273                         if (!vnic->mc_list) {
2274                                 rc = -ENOMEM;
2275                                 goto out;
2276                         }
2277                 }
2278
2279                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
2280                         max_rings = bp->rx_nr_rings;
2281                 else
2282                         max_rings = 1;
2283
2284                 vnic->fw_grp_ids = kcalloc(max_rings, sizeof(u16), GFP_KERNEL);
2285                 if (!vnic->fw_grp_ids) {
2286                         rc = -ENOMEM;
2287                         goto out;
2288                 }
2289
2290                 /* Allocate rss table and hash key */
2291                 vnic->rss_table = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2292                                                      &vnic->rss_table_dma_addr,
2293                                                      GFP_KERNEL);
2294                 if (!vnic->rss_table) {
2295                         rc = -ENOMEM;
2296                         goto out;
2297                 }
2298
2299                 size = L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE * sizeof(u16));
2300
2301                 vnic->rss_hash_key = ((void *)vnic->rss_table) + size;
2302                 vnic->rss_hash_key_dma_addr = vnic->rss_table_dma_addr + size;
2303         }
2304         return 0;
2305
2306 out:
2307         return rc;
2308 }
2309
2310 static void bnxt_free_hwrm_resources(struct bnxt *bp)
2311 {
2312         struct pci_dev *pdev = bp->pdev;
2313
2314         dma_free_coherent(&pdev->dev, PAGE_SIZE, bp->hwrm_cmd_resp_addr,
2315                           bp->hwrm_cmd_resp_dma_addr);
2316
2317         bp->hwrm_cmd_resp_addr = NULL;
2318         if (bp->hwrm_dbg_resp_addr) {
2319                 dma_free_coherent(&pdev->dev, HWRM_DBG_REG_BUF_SIZE,
2320                                   bp->hwrm_dbg_resp_addr,
2321                                   bp->hwrm_dbg_resp_dma_addr);
2322
2323                 bp->hwrm_dbg_resp_addr = NULL;
2324         }
2325 }
2326
2327 static int bnxt_alloc_hwrm_resources(struct bnxt *bp)
2328 {
2329         struct pci_dev *pdev = bp->pdev;
2330
2331         bp->hwrm_cmd_resp_addr = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
2332                                                    &bp->hwrm_cmd_resp_dma_addr,
2333                                                    GFP_KERNEL);
2334         if (!bp->hwrm_cmd_resp_addr)
2335                 return -ENOMEM;
2336         bp->hwrm_dbg_resp_addr = dma_alloc_coherent(&pdev->dev,
2337                                                     HWRM_DBG_REG_BUF_SIZE,
2338                                                     &bp->hwrm_dbg_resp_dma_addr,
2339                                                     GFP_KERNEL);
2340         if (!bp->hwrm_dbg_resp_addr)
2341                 netdev_warn(bp->dev, "fail to alloc debug register dma mem\n");
2342
2343         return 0;
2344 }
2345
2346 static void bnxt_free_stats(struct bnxt *bp)
2347 {
2348         u32 size, i;
2349         struct pci_dev *pdev = bp->pdev;
2350
2351         if (!bp->bnapi)
2352                 return;
2353
2354         size = sizeof(struct ctx_hw_stats);
2355
2356         for (i = 0; i < bp->cp_nr_rings; i++) {
2357                 struct bnxt_napi *bnapi = bp->bnapi[i];
2358                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2359
2360                 if (cpr->hw_stats) {
2361                         dma_free_coherent(&pdev->dev, size, cpr->hw_stats,
2362                                           cpr->hw_stats_map);
2363                         cpr->hw_stats = NULL;
2364                 }
2365         }
2366 }
2367
2368 static int bnxt_alloc_stats(struct bnxt *bp)
2369 {
2370         u32 size, i;
2371         struct pci_dev *pdev = bp->pdev;
2372
2373         size = sizeof(struct ctx_hw_stats);
2374
2375         for (i = 0; i < bp->cp_nr_rings; i++) {
2376                 struct bnxt_napi *bnapi = bp->bnapi[i];
2377                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
2378
2379                 cpr->hw_stats = dma_alloc_coherent(&pdev->dev, size,
2380                                                    &cpr->hw_stats_map,
2381                                                    GFP_KERNEL);
2382                 if (!cpr->hw_stats)
2383                         return -ENOMEM;
2384
2385                 cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
2386         }
2387         return 0;
2388 }
2389
2390 static void bnxt_clear_ring_indices(struct bnxt *bp)
2391 {
2392         int i;
2393
2394         if (!bp->bnapi)
2395                 return;
2396
2397         for (i = 0; i < bp->cp_nr_rings; i++) {
2398                 struct bnxt_napi *bnapi = bp->bnapi[i];
2399                 struct bnxt_cp_ring_info *cpr;
2400                 struct bnxt_rx_ring_info *rxr;
2401                 struct bnxt_tx_ring_info *txr;
2402
2403                 if (!bnapi)
2404                         continue;
2405
2406                 cpr = &bnapi->cp_ring;
2407                 cpr->cp_raw_cons = 0;
2408
2409                 txr = bnapi->tx_ring;
2410                 if (txr) {
2411                         txr->tx_prod = 0;
2412                         txr->tx_cons = 0;
2413                 }
2414
2415                 rxr = bnapi->rx_ring;
2416                 if (rxr) {
2417                         rxr->rx_prod = 0;
2418                         rxr->rx_agg_prod = 0;
2419                         rxr->rx_sw_agg_prod = 0;
2420                 }
2421         }
2422 }
2423
2424 static void bnxt_free_ntp_fltrs(struct bnxt *bp, bool irq_reinit)
2425 {
2426 #ifdef CONFIG_RFS_ACCEL
2427         int i;
2428
2429         /* Under rtnl_lock and all our NAPIs have been disabled.  It's
2430          * safe to delete the hash table.
2431          */
2432         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
2433                 struct hlist_head *head;
2434                 struct hlist_node *tmp;
2435                 struct bnxt_ntuple_filter *fltr;
2436
2437                 head = &bp->ntp_fltr_hash_tbl[i];
2438                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
2439                         hlist_del(&fltr->hash);
2440                         kfree(fltr);
2441                 }
2442         }
2443         if (irq_reinit) {
2444                 kfree(bp->ntp_fltr_bmap);
2445                 bp->ntp_fltr_bmap = NULL;
2446         }
2447         bp->ntp_fltr_count = 0;
2448 #endif
2449 }
2450
2451 static int bnxt_alloc_ntp_fltrs(struct bnxt *bp)
2452 {
2453 #ifdef CONFIG_RFS_ACCEL
2454         int i, rc = 0;
2455
2456         if (!(bp->flags & BNXT_FLAG_RFS))
2457                 return 0;
2458
2459         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++)
2460                 INIT_HLIST_HEAD(&bp->ntp_fltr_hash_tbl[i]);
2461
2462         bp->ntp_fltr_count = 0;
2463         bp->ntp_fltr_bmap = kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR),
2464                                     GFP_KERNEL);
2465
2466         if (!bp->ntp_fltr_bmap)
2467                 rc = -ENOMEM;
2468
2469         return rc;
2470 #else
2471         return 0;
2472 #endif
2473 }
2474
2475 static void bnxt_free_mem(struct bnxt *bp, bool irq_re_init)
2476 {
2477         bnxt_free_vnic_attributes(bp);
2478         bnxt_free_tx_rings(bp);
2479         bnxt_free_rx_rings(bp);
2480         bnxt_free_cp_rings(bp);
2481         bnxt_free_ntp_fltrs(bp, irq_re_init);
2482         if (irq_re_init) {
2483                 bnxt_free_stats(bp);
2484                 bnxt_free_ring_grps(bp);
2485                 bnxt_free_vnics(bp);
2486                 kfree(bp->tx_ring);
2487                 bp->tx_ring = NULL;
2488                 kfree(bp->rx_ring);
2489                 bp->rx_ring = NULL;
2490                 kfree(bp->bnapi);
2491                 bp->bnapi = NULL;
2492         } else {
2493                 bnxt_clear_ring_indices(bp);
2494         }
2495 }
2496
2497 static int bnxt_alloc_mem(struct bnxt *bp, bool irq_re_init)
2498 {
2499         int i, rc, size, arr_size;
2500         void *bnapi;
2501
2502         if (irq_re_init) {
2503                 /* Allocate bnapi mem pointer array and mem block for
2504                  * all queues
2505                  */
2506                 arr_size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi *) *
2507                                 bp->cp_nr_rings);
2508                 size = L1_CACHE_ALIGN(sizeof(struct bnxt_napi));
2509                 bnapi = kzalloc(arr_size + size * bp->cp_nr_rings, GFP_KERNEL);
2510                 if (!bnapi)
2511                         return -ENOMEM;
2512
2513                 bp->bnapi = bnapi;
2514                 bnapi += arr_size;
2515                 for (i = 0; i < bp->cp_nr_rings; i++, bnapi += size) {
2516                         bp->bnapi[i] = bnapi;
2517                         bp->bnapi[i]->index = i;
2518                         bp->bnapi[i]->bp = bp;
2519                 }
2520
2521                 bp->rx_ring = kcalloc(bp->rx_nr_rings,
2522                                       sizeof(struct bnxt_rx_ring_info),
2523                                       GFP_KERNEL);
2524                 if (!bp->rx_ring)
2525                         return -ENOMEM;
2526
2527                 for (i = 0; i < bp->rx_nr_rings; i++) {
2528                         bp->rx_ring[i].bnapi = bp->bnapi[i];
2529                         bp->bnapi[i]->rx_ring = &bp->rx_ring[i];
2530                 }
2531
2532                 bp->tx_ring = kcalloc(bp->tx_nr_rings,
2533                                       sizeof(struct bnxt_tx_ring_info),
2534                                       GFP_KERNEL);
2535                 if (!bp->tx_ring)
2536                         return -ENOMEM;
2537
2538                 for (i = 0; i < bp->tx_nr_rings; i++) {
2539                         bp->tx_ring[i].bnapi = bp->bnapi[i];
2540                         bp->bnapi[i]->tx_ring = &bp->tx_ring[i];
2541                 }
2542
2543                 rc = bnxt_alloc_stats(bp);
2544                 if (rc)
2545                         goto alloc_mem_err;
2546
2547                 rc = bnxt_alloc_ntp_fltrs(bp);
2548                 if (rc)
2549                         goto alloc_mem_err;
2550
2551                 rc = bnxt_alloc_vnics(bp);
2552                 if (rc)
2553                         goto alloc_mem_err;
2554         }
2555
2556         bnxt_init_ring_struct(bp);
2557
2558         rc = bnxt_alloc_rx_rings(bp);
2559         if (rc)
2560                 goto alloc_mem_err;
2561
2562         rc = bnxt_alloc_tx_rings(bp);
2563         if (rc)
2564                 goto alloc_mem_err;
2565
2566         rc = bnxt_alloc_cp_rings(bp);
2567         if (rc)
2568                 goto alloc_mem_err;
2569
2570         bp->vnic_info[0].flags |= BNXT_VNIC_RSS_FLAG | BNXT_VNIC_MCAST_FLAG |
2571                                   BNXT_VNIC_UCAST_FLAG;
2572         rc = bnxt_alloc_vnic_attributes(bp);
2573         if (rc)
2574                 goto alloc_mem_err;
2575         return 0;
2576
2577 alloc_mem_err:
2578         bnxt_free_mem(bp, true);
2579         return rc;
2580 }
2581
2582 void bnxt_hwrm_cmd_hdr_init(struct bnxt *bp, void *request, u16 req_type,
2583                             u16 cmpl_ring, u16 target_id)
2584 {
2585         struct hwrm_cmd_req_hdr *req = request;
2586
2587         req->cmpl_ring_req_type =
2588                 cpu_to_le32(req_type | (cmpl_ring << HWRM_CMPL_RING_SFT));
2589         req->target_id_seq_id = cpu_to_le32(target_id << HWRM_TARGET_FID_SFT);
2590         req->resp_addr = cpu_to_le64(bp->hwrm_cmd_resp_dma_addr);
2591 }
2592
2593 int _hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2594 {
2595         int i, intr_process, rc;
2596         struct hwrm_cmd_req_hdr *req = msg;
2597         u32 *data = msg;
2598         __le32 *resp_len, *valid;
2599         u16 cp_ring_id, len = 0;
2600         struct hwrm_err_output *resp = bp->hwrm_cmd_resp_addr;
2601
2602         req->target_id_seq_id |= cpu_to_le32(bp->hwrm_cmd_seq++);
2603         memset(resp, 0, PAGE_SIZE);
2604         cp_ring_id = (le32_to_cpu(req->cmpl_ring_req_type) &
2605                       HWRM_CMPL_RING_MASK) >>
2606                      HWRM_CMPL_RING_SFT;
2607         intr_process = (cp_ring_id == INVALID_HW_RING_ID) ? 0 : 1;
2608
2609         /* Write request msg to hwrm channel */
2610         __iowrite32_copy(bp->bar0, data, msg_len / 4);
2611
2612         /* currently supports only one outstanding message */
2613         if (intr_process)
2614                 bp->hwrm_intr_seq_id = le32_to_cpu(req->target_id_seq_id) &
2615                                        HWRM_SEQ_ID_MASK;
2616
2617         /* Ring channel doorbell */
2618         writel(1, bp->bar0 + 0x100);
2619
2620         i = 0;
2621         if (intr_process) {
2622                 /* Wait until hwrm response cmpl interrupt is processed */
2623                 while (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID &&
2624                        i++ < timeout) {
2625                         usleep_range(600, 800);
2626                 }
2627
2628                 if (bp->hwrm_intr_seq_id != HWRM_SEQ_ID_INVALID) {
2629                         netdev_err(bp->dev, "Resp cmpl intr err msg: 0x%x\n",
2630                                    req->cmpl_ring_req_type);
2631                         return -1;
2632                 }
2633         } else {
2634                 /* Check if response len is updated */
2635                 resp_len = bp->hwrm_cmd_resp_addr + HWRM_RESP_LEN_OFFSET;
2636                 for (i = 0; i < timeout; i++) {
2637                         len = (le32_to_cpu(*resp_len) & HWRM_RESP_LEN_MASK) >>
2638                               HWRM_RESP_LEN_SFT;
2639                         if (len)
2640                                 break;
2641                         usleep_range(600, 800);
2642                 }
2643
2644                 if (i >= timeout) {
2645                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2646                                    timeout, req->cmpl_ring_req_type,
2647                                    req->target_id_seq_id, *resp_len);
2648                         return -1;
2649                 }
2650
2651                 /* Last word of resp contains valid bit */
2652                 valid = bp->hwrm_cmd_resp_addr + len - 4;
2653                 for (i = 0; i < timeout; i++) {
2654                         if (le32_to_cpu(*valid) & HWRM_RESP_VALID_MASK)
2655                                 break;
2656                         usleep_range(600, 800);
2657                 }
2658
2659                 if (i >= timeout) {
2660                         netdev_err(bp->dev, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2661                                    timeout, req->cmpl_ring_req_type,
2662                                    req->target_id_seq_id, len, *valid);
2663                         return -1;
2664                 }
2665         }
2666
2667         rc = le16_to_cpu(resp->error_code);
2668         if (rc) {
2669                 netdev_err(bp->dev, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2670                            le16_to_cpu(resp->req_type),
2671                            le16_to_cpu(resp->seq_id), rc);
2672                 return rc;
2673         }
2674         return 0;
2675 }
2676
2677 int hwrm_send_message(struct bnxt *bp, void *msg, u32 msg_len, int timeout)
2678 {
2679         int rc;
2680
2681         mutex_lock(&bp->hwrm_cmd_lock);
2682         rc = _hwrm_send_message(bp, msg, msg_len, timeout);
2683         mutex_unlock(&bp->hwrm_cmd_lock);
2684         return rc;
2685 }
2686
2687 static int bnxt_hwrm_func_drv_rgtr(struct bnxt *bp)
2688 {
2689         struct hwrm_func_drv_rgtr_input req = {0};
2690         int i;
2691
2692         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_RGTR, -1, -1);
2693
2694         req.enables =
2695                 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE |
2696                             FUNC_DRV_RGTR_REQ_ENABLES_VER |
2697                             FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD);
2698
2699         /* TODO: current async event fwd bits are not defined and the firmware
2700          * only checks if it is non-zero to enable async event forwarding
2701          */
2702         req.async_event_fwd[0] |= cpu_to_le32(1);
2703         req.os_type = cpu_to_le16(1);
2704         req.ver_maj = DRV_VER_MAJ;
2705         req.ver_min = DRV_VER_MIN;
2706         req.ver_upd = DRV_VER_UPD;
2707
2708         if (BNXT_PF(bp)) {
2709                 DECLARE_BITMAP(vf_req_snif_bmap, 256);
2710                 u32 *data = (u32 *)vf_req_snif_bmap;
2711
2712                 memset(vf_req_snif_bmap, 0, sizeof(vf_req_snif_bmap));
2713                 for (i = 0; i < ARRAY_SIZE(bnxt_vf_req_snif); i++)
2714                         __set_bit(bnxt_vf_req_snif[i], vf_req_snif_bmap);
2715
2716                 for (i = 0; i < 8; i++)
2717                         req.vf_req_fwd[i] = cpu_to_le32(data[i]);
2718
2719                 req.enables |=
2720                         cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD);
2721         }
2722
2723         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2724 }
2725
2726 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt *bp)
2727 {
2728         struct hwrm_func_drv_unrgtr_input req = {0};
2729
2730         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_DRV_UNRGTR, -1, -1);
2731         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2732 }
2733
2734 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt *bp, u8 tunnel_type)
2735 {
2736         u32 rc = 0;
2737         struct hwrm_tunnel_dst_port_free_input req = {0};
2738
2739         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_FREE, -1, -1);
2740         req.tunnel_type = tunnel_type;
2741
2742         switch (tunnel_type) {
2743         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN:
2744                 req.tunnel_dst_port_id = bp->vxlan_fw_dst_port_id;
2745                 break;
2746         case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE:
2747                 req.tunnel_dst_port_id = bp->nge_fw_dst_port_id;
2748                 break;
2749         default:
2750                 break;
2751         }
2752
2753         rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2754         if (rc)
2755                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2756                            rc);
2757         return rc;
2758 }
2759
2760 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt *bp, __be16 port,
2761                                            u8 tunnel_type)
2762 {
2763         u32 rc = 0;
2764         struct hwrm_tunnel_dst_port_alloc_input req = {0};
2765         struct hwrm_tunnel_dst_port_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2766
2767         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_TUNNEL_DST_PORT_ALLOC, -1, -1);
2768
2769         req.tunnel_type = tunnel_type;
2770         req.tunnel_dst_port_val = port;
2771
2772         mutex_lock(&bp->hwrm_cmd_lock);
2773         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2774         if (rc) {
2775                 netdev_err(bp->dev, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2776                            rc);
2777                 goto err_out;
2778         }
2779
2780         if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN)
2781                 bp->vxlan_fw_dst_port_id = resp->tunnel_dst_port_id;
2782
2783         else if (tunnel_type & TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE)
2784                 bp->nge_fw_dst_port_id = resp->tunnel_dst_port_id;
2785 err_out:
2786         mutex_unlock(&bp->hwrm_cmd_lock);
2787         return rc;
2788 }
2789
2790 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt *bp, u16 vnic_id)
2791 {
2792         struct hwrm_cfa_l2_set_rx_mask_input req = {0};
2793         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2794
2795         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_SET_RX_MASK, -1, -1);
2796         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
2797
2798         req.num_mc_entries = cpu_to_le32(vnic->mc_list_count);
2799         req.mc_tbl_addr = cpu_to_le64(vnic->mc_list_mapping);
2800         req.mask = cpu_to_le32(vnic->rx_mask);
2801         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2802 }
2803
2804 #ifdef CONFIG_RFS_ACCEL
2805 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt *bp,
2806                                             struct bnxt_ntuple_filter *fltr)
2807 {
2808         struct hwrm_cfa_ntuple_filter_free_input req = {0};
2809
2810         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_FREE, -1, -1);
2811         req.ntuple_filter_id = fltr->filter_id;
2812         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2813 }
2814
2815 #define BNXT_NTP_FLTR_FLAGS                                     \
2816         (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID |     \
2817          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE |        \
2818          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR |      \
2819          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE |      \
2820          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR |       \
2821          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK |  \
2822          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR |       \
2823          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK |  \
2824          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL |      \
2825          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT |         \
2826          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK |    \
2827          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT |         \
2828          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK |    \
2829          CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2830
2831 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt *bp,
2832                                              struct bnxt_ntuple_filter *fltr)
2833 {
2834         int rc = 0;
2835         struct hwrm_cfa_ntuple_filter_alloc_input req = {0};
2836         struct hwrm_cfa_ntuple_filter_alloc_output *resp =
2837                 bp->hwrm_cmd_resp_addr;
2838         struct flow_keys *keys = &fltr->fkeys;
2839         struct bnxt_vnic_info *vnic = &bp->vnic_info[fltr->rxq + 1];
2840
2841         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_NTUPLE_FILTER_ALLOC, -1, -1);
2842         req.l2_filter_id = bp->vnic_info[0].fw_l2_filter_id[0];
2843
2844         req.enables = cpu_to_le32(BNXT_NTP_FLTR_FLAGS);
2845
2846         req.ethertype = htons(ETH_P_IP);
2847         memcpy(req.src_macaddr, fltr->src_mac_addr, ETH_ALEN);
2848         req.ip_addr_type = CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4;
2849         req.ip_protocol = keys->basic.ip_proto;
2850
2851         req.src_ipaddr[0] = keys->addrs.v4addrs.src;
2852         req.src_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2853         req.dst_ipaddr[0] = keys->addrs.v4addrs.dst;
2854         req.dst_ipaddr_mask[0] = cpu_to_be32(0xffffffff);
2855
2856         req.src_port = keys->ports.src;
2857         req.src_port_mask = cpu_to_be16(0xffff);
2858         req.dst_port = keys->ports.dst;
2859         req.dst_port_mask = cpu_to_be16(0xffff);
2860
2861         req.dst_id = cpu_to_le16(vnic->fw_vnic_id);
2862         mutex_lock(&bp->hwrm_cmd_lock);
2863         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2864         if (!rc)
2865                 fltr->filter_id = resp->ntuple_filter_id;
2866         mutex_unlock(&bp->hwrm_cmd_lock);
2867         return rc;
2868 }
2869 #endif
2870
2871 static int bnxt_hwrm_set_vnic_filter(struct bnxt *bp, u16 vnic_id, u16 idx,
2872                                      u8 *mac_addr)
2873 {
2874         u32 rc = 0;
2875         struct hwrm_cfa_l2_filter_alloc_input req = {0};
2876         struct hwrm_cfa_l2_filter_alloc_output *resp = bp->hwrm_cmd_resp_addr;
2877
2878         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_ALLOC, -1, -1);
2879         req.flags = cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX |
2880                                 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST);
2881         req.dst_id = cpu_to_le16(bp->vnic_info[vnic_id].fw_vnic_id);
2882         req.enables =
2883                 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR |
2884                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID |
2885                             CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK);
2886         memcpy(req.l2_addr, mac_addr, ETH_ALEN);
2887         req.l2_addr_mask[0] = 0xff;
2888         req.l2_addr_mask[1] = 0xff;
2889         req.l2_addr_mask[2] = 0xff;
2890         req.l2_addr_mask[3] = 0xff;
2891         req.l2_addr_mask[4] = 0xff;
2892         req.l2_addr_mask[5] = 0xff;
2893
2894         mutex_lock(&bp->hwrm_cmd_lock);
2895         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2896         if (!rc)
2897                 bp->vnic_info[vnic_id].fw_l2_filter_id[idx] =
2898                                                         resp->l2_filter_id;
2899         mutex_unlock(&bp->hwrm_cmd_lock);
2900         return rc;
2901 }
2902
2903 static int bnxt_hwrm_clear_vnic_filter(struct bnxt *bp)
2904 {
2905         u16 i, j, num_of_vnics = 1; /* only vnic 0 supported */
2906         int rc = 0;
2907
2908         /* Any associated ntuple filters will also be cleared by firmware. */
2909         mutex_lock(&bp->hwrm_cmd_lock);
2910         for (i = 0; i < num_of_vnics; i++) {
2911                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
2912
2913                 for (j = 0; j < vnic->uc_filter_count; j++) {
2914                         struct hwrm_cfa_l2_filter_free_input req = {0};
2915
2916                         bnxt_hwrm_cmd_hdr_init(bp, &req,
2917                                                HWRM_CFA_L2_FILTER_FREE, -1, -1);
2918
2919                         req.l2_filter_id = vnic->fw_l2_filter_id[j];
2920
2921                         rc = _hwrm_send_message(bp, &req, sizeof(req),
2922                                                 HWRM_CMD_TIMEOUT);
2923                 }
2924                 vnic->uc_filter_count = 0;
2925         }
2926         mutex_unlock(&bp->hwrm_cmd_lock);
2927
2928         return rc;
2929 }
2930
2931 static int bnxt_hwrm_vnic_set_tpa(struct bnxt *bp, u16 vnic_id, u32 tpa_flags)
2932 {
2933         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2934         struct hwrm_vnic_tpa_cfg_input req = {0};
2935
2936         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_TPA_CFG, -1, -1);
2937
2938         if (tpa_flags) {
2939                 u16 mss = bp->dev->mtu - 40;
2940                 u32 nsegs, n, segs = 0, flags;
2941
2942                 flags = VNIC_TPA_CFG_REQ_FLAGS_TPA |
2943                         VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA |
2944                         VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE |
2945                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN |
2946                         VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ;
2947                 if (tpa_flags & BNXT_FLAG_GRO)
2948                         flags |= VNIC_TPA_CFG_REQ_FLAGS_GRO;
2949
2950                 req.flags = cpu_to_le32(flags);
2951
2952                 req.enables =
2953                         cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS |
2954                                     VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS |
2955                                     VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN);
2956
2957                 /* Number of segs are log2 units, and first packet is not
2958                  * included as part of this units.
2959                  */
2960                 if (mss <= PAGE_SIZE) {
2961                         n = PAGE_SIZE / mss;
2962                         nsegs = (MAX_SKB_FRAGS - 1) * n;
2963                 } else {
2964                         n = mss / PAGE_SIZE;
2965                         if (mss & (PAGE_SIZE - 1))
2966                                 n++;
2967                         nsegs = (MAX_SKB_FRAGS - n) / n;
2968                 }
2969
2970                 segs = ilog2(nsegs);
2971                 req.max_agg_segs = cpu_to_le16(segs);
2972                 req.max_aggs = cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX);
2973
2974                 req.min_agg_len = cpu_to_le32(512);
2975         }
2976         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
2977
2978         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
2979 }
2980
2981 static int bnxt_hwrm_vnic_set_rss(struct bnxt *bp, u16 vnic_id, bool set_rss)
2982 {
2983         u32 i, j, max_rings;
2984         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
2985         struct hwrm_vnic_rss_cfg_input req = {0};
2986
2987         if (vnic->fw_rss_cos_lb_ctx == INVALID_HW_RING_ID)
2988                 return 0;
2989
2990         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_CFG, -1, -1);
2991         if (set_rss) {
2992                 vnic->hash_type = BNXT_RSS_HASH_TYPE_FLAG_IPV4 |
2993                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 |
2994                                  BNXT_RSS_HASH_TYPE_FLAG_IPV6 |
2995                                  BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6;
2996
2997                 req.hash_type = cpu_to_le32(vnic->hash_type);
2998
2999                 if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3000                         max_rings = bp->rx_nr_rings;
3001                 else
3002                         max_rings = 1;
3003
3004                 /* Fill the RSS indirection table with ring group ids */
3005                 for (i = 0, j = 0; i < HW_HASH_INDEX_SIZE; i++, j++) {
3006                         if (j == max_rings)
3007                                 j = 0;
3008                         vnic->rss_table[i] = cpu_to_le16(vnic->fw_grp_ids[j]);
3009                 }
3010
3011                 req.ring_grp_tbl_addr = cpu_to_le64(vnic->rss_table_dma_addr);
3012                 req.hash_key_tbl_addr =
3013                         cpu_to_le64(vnic->rss_hash_key_dma_addr);
3014         }
3015         req.rss_ctx_idx = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3016         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3017 }
3018
3019 static int bnxt_hwrm_vnic_set_hds(struct bnxt *bp, u16 vnic_id)
3020 {
3021         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3022         struct hwrm_vnic_plcmodes_cfg_input req = {0};
3023
3024         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_PLCMODES_CFG, -1, -1);
3025         req.flags = cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT |
3026                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 |
3027                                 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6);
3028         req.enables =
3029                 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID |
3030                             VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID);
3031         /* thresholds not implemented in firmware yet */
3032         req.jumbo_thresh = cpu_to_le16(bp->rx_copy_thresh);
3033         req.hds_threshold = cpu_to_le16(bp->rx_copy_thresh);
3034         req.vnic_id = cpu_to_le32(vnic->fw_vnic_id);
3035         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3036 }
3037
3038 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt *bp, u16 vnic_id)
3039 {
3040         struct hwrm_vnic_rss_cos_lb_ctx_free_input req = {0};
3041
3042         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_FREE, -1, -1);
3043         req.rss_cos_lb_ctx_id =
3044                 cpu_to_le16(bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx);
3045
3046         hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3047         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3048 }
3049
3050 static void bnxt_hwrm_vnic_ctx_free(struct bnxt *bp)
3051 {
3052         int i;
3053
3054         for (i = 0; i < bp->nr_vnics; i++) {
3055                 struct bnxt_vnic_info *vnic = &bp->vnic_info[i];
3056
3057                 if (vnic->fw_rss_cos_lb_ctx != INVALID_HW_RING_ID)
3058                         bnxt_hwrm_vnic_ctx_free_one(bp, i);
3059         }
3060         bp->rsscos_nr_ctxs = 0;
3061 }
3062
3063 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt *bp, u16 vnic_id)
3064 {
3065         int rc;
3066         struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req = {0};
3067         struct hwrm_vnic_rss_cos_lb_ctx_alloc_output *resp =
3068                                                 bp->hwrm_cmd_resp_addr;
3069
3070         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC, -1,
3071                                -1);
3072
3073         mutex_lock(&bp->hwrm_cmd_lock);
3074         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3075         if (!rc)
3076                 bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx =
3077                         le16_to_cpu(resp->rss_cos_lb_ctx_id);
3078         mutex_unlock(&bp->hwrm_cmd_lock);
3079
3080         return rc;
3081 }
3082
3083 static int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id)
3084 {
3085         unsigned int ring = 0, grp_idx;
3086         struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id];
3087         struct hwrm_vnic_cfg_input req = {0};
3088
3089         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_CFG, -1, -1);
3090         /* Only RSS support for now TBD: COS & LB */
3091         req.enables = cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP |
3092                                   VNIC_CFG_REQ_ENABLES_RSS_RULE);
3093         req.rss_rule = cpu_to_le16(vnic->fw_rss_cos_lb_ctx);
3094         req.cos_rule = cpu_to_le16(0xffff);
3095         if (vnic->flags & BNXT_VNIC_RSS_FLAG)
3096                 ring = 0;
3097         else if (vnic->flags & BNXT_VNIC_RFS_FLAG)
3098                 ring = vnic_id - 1;
3099
3100         grp_idx = bp->rx_ring[ring].bnapi->index;
3101         req.vnic_id = cpu_to_le16(vnic->fw_vnic_id);
3102         req.dflt_ring_grp = cpu_to_le16(bp->grp_info[grp_idx].fw_grp_id);
3103
3104         req.lb_rule = cpu_to_le16(0xffff);
3105         req.mru = cpu_to_le16(bp->dev->mtu + ETH_HLEN + ETH_FCS_LEN +
3106                               VLAN_HLEN);
3107
3108         if (bp->flags & BNXT_FLAG_STRIP_VLAN)
3109                 req.flags |= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE);
3110
3111         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3112 }
3113
3114 static int bnxt_hwrm_vnic_free_one(struct bnxt *bp, u16 vnic_id)
3115 {
3116         u32 rc = 0;
3117
3118         if (bp->vnic_info[vnic_id].fw_vnic_id != INVALID_HW_RING_ID) {
3119                 struct hwrm_vnic_free_input req = {0};
3120
3121                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_FREE, -1, -1);
3122                 req.vnic_id =
3123                         cpu_to_le32(bp->vnic_info[vnic_id].fw_vnic_id);
3124
3125                 rc = hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3126                 if (rc)
3127                         return rc;
3128                 bp->vnic_info[vnic_id].fw_vnic_id = INVALID_HW_RING_ID;
3129         }
3130         return rc;
3131 }
3132
3133 static void bnxt_hwrm_vnic_free(struct bnxt *bp)
3134 {
3135         u16 i;
3136
3137         for (i = 0; i < bp->nr_vnics; i++)
3138                 bnxt_hwrm_vnic_free_one(bp, i);
3139 }
3140
3141 static int bnxt_hwrm_vnic_alloc(struct bnxt *bp, u16 vnic_id,
3142                                 unsigned int start_rx_ring_idx,
3143                                 unsigned int nr_rings)
3144 {
3145         int rc = 0;
3146         unsigned int i, j, grp_idx, end_idx = start_rx_ring_idx + nr_rings;
3147         struct hwrm_vnic_alloc_input req = {0};
3148         struct hwrm_vnic_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3149
3150         /* map ring groups to this vnic */
3151         for (i = start_rx_ring_idx, j = 0; i < end_idx; i++, j++) {
3152                 grp_idx = bp->rx_ring[i].bnapi->index;
3153                 if (bp->grp_info[grp_idx].fw_grp_id == INVALID_HW_RING_ID) {
3154                         netdev_err(bp->dev, "Not enough ring groups avail:%x req:%x\n",
3155                                    j, nr_rings);
3156                         break;
3157                 }
3158                 bp->vnic_info[vnic_id].fw_grp_ids[j] =
3159                                         bp->grp_info[grp_idx].fw_grp_id;
3160         }
3161
3162         bp->vnic_info[vnic_id].fw_rss_cos_lb_ctx = INVALID_HW_RING_ID;
3163         if (vnic_id == 0)
3164                 req.flags = cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT);
3165
3166         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VNIC_ALLOC, -1, -1);
3167
3168         mutex_lock(&bp->hwrm_cmd_lock);
3169         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3170         if (!rc)
3171                 bp->vnic_info[vnic_id].fw_vnic_id = le32_to_cpu(resp->vnic_id);
3172         mutex_unlock(&bp->hwrm_cmd_lock);
3173         return rc;
3174 }
3175
3176 static int bnxt_hwrm_ring_grp_alloc(struct bnxt *bp)
3177 {
3178         u16 i;
3179         u32 rc = 0;
3180
3181         mutex_lock(&bp->hwrm_cmd_lock);
3182         for (i = 0; i < bp->rx_nr_rings; i++) {
3183                 struct hwrm_ring_grp_alloc_input req = {0};
3184                 struct hwrm_ring_grp_alloc_output *resp =
3185                                         bp->hwrm_cmd_resp_addr;
3186                 unsigned int grp_idx = bp->rx_ring[i].bnapi->index;
3187
3188                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_ALLOC, -1, -1);
3189
3190                 req.cr = cpu_to_le16(bp->grp_info[grp_idx].cp_fw_ring_id);
3191                 req.rr = cpu_to_le16(bp->grp_info[grp_idx].rx_fw_ring_id);
3192                 req.ar = cpu_to_le16(bp->grp_info[grp_idx].agg_fw_ring_id);
3193                 req.sc = cpu_to_le16(bp->grp_info[grp_idx].fw_stats_ctx);
3194
3195                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3196                                         HWRM_CMD_TIMEOUT);
3197                 if (rc)
3198                         break;
3199
3200                 bp->grp_info[grp_idx].fw_grp_id =
3201                         le32_to_cpu(resp->ring_group_id);
3202         }
3203         mutex_unlock(&bp->hwrm_cmd_lock);
3204         return rc;
3205 }
3206
3207 static int bnxt_hwrm_ring_grp_free(struct bnxt *bp)
3208 {
3209         u16 i;
3210         u32 rc = 0;
3211         struct hwrm_ring_grp_free_input req = {0};
3212
3213         if (!bp->grp_info)
3214                 return 0;
3215
3216         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_GRP_FREE, -1, -1);
3217
3218         mutex_lock(&bp->hwrm_cmd_lock);
3219         for (i = 0; i < bp->cp_nr_rings; i++) {
3220                 if (bp->grp_info[i].fw_grp_id == INVALID_HW_RING_ID)
3221                         continue;
3222                 req.ring_group_id =
3223                         cpu_to_le32(bp->grp_info[i].fw_grp_id);
3224
3225                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3226                                         HWRM_CMD_TIMEOUT);
3227                 if (rc)
3228                         break;
3229                 bp->grp_info[i].fw_grp_id = INVALID_HW_RING_ID;
3230         }
3231         mutex_unlock(&bp->hwrm_cmd_lock);
3232         return rc;
3233 }
3234
3235 static int hwrm_ring_alloc_send_msg(struct bnxt *bp,
3236                                     struct bnxt_ring_struct *ring,
3237                                     u32 ring_type, u32 map_index,
3238                                     u32 stats_ctx_id)
3239 {
3240         int rc = 0, err = 0;
3241         struct hwrm_ring_alloc_input req = {0};
3242         struct hwrm_ring_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3243         u16 ring_id;
3244
3245         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_ALLOC, -1, -1);
3246
3247         req.enables = 0;
3248         if (ring->nr_pages > 1) {
3249                 req.page_tbl_addr = cpu_to_le64(ring->pg_tbl_map);
3250                 /* Page size is in log2 units */
3251                 req.page_size = BNXT_PAGE_SHIFT;
3252                 req.page_tbl_depth = 1;
3253         } else {
3254                 req.page_tbl_addr =  cpu_to_le64(ring->dma_arr[0]);
3255         }
3256         req.fbo = 0;
3257         /* Association of ring index with doorbell index and MSIX number */
3258         req.logical_id = cpu_to_le16(map_index);
3259
3260         switch (ring_type) {
3261         case HWRM_RING_ALLOC_TX:
3262                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_TX;
3263                 /* Association of transmit ring with completion ring */
3264                 req.cmpl_ring_id =
3265                         cpu_to_le16(bp->grp_info[map_index].cp_fw_ring_id);
3266                 req.length = cpu_to_le32(bp->tx_ring_mask + 1);
3267                 req.stat_ctx_id = cpu_to_le32(stats_ctx_id);
3268                 req.queue_id = cpu_to_le16(ring->queue_id);
3269                 break;
3270         case HWRM_RING_ALLOC_RX:
3271                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3272                 req.length = cpu_to_le32(bp->rx_ring_mask + 1);
3273                 break;
3274         case HWRM_RING_ALLOC_AGG:
3275                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_RX;
3276                 req.length = cpu_to_le32(bp->rx_agg_ring_mask + 1);
3277                 break;
3278         case HWRM_RING_ALLOC_CMPL:
3279                 req.ring_type = RING_ALLOC_REQ_RING_TYPE_CMPL;
3280                 req.length = cpu_to_le32(bp->cp_ring_mask + 1);
3281                 if (bp->flags & BNXT_FLAG_USING_MSIX)
3282                         req.int_mode = RING_ALLOC_REQ_INT_MODE_MSIX;
3283                 break;
3284         default:
3285                 netdev_err(bp->dev, "hwrm alloc invalid ring type %d\n",
3286                            ring_type);
3287                 return -1;
3288         }
3289
3290         mutex_lock(&bp->hwrm_cmd_lock);
3291         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3292         err = le16_to_cpu(resp->error_code);
3293         ring_id = le16_to_cpu(resp->ring_id);
3294         mutex_unlock(&bp->hwrm_cmd_lock);
3295
3296         if (rc || err) {
3297                 switch (ring_type) {
3298                 case RING_FREE_REQ_RING_TYPE_CMPL:
3299                         netdev_err(bp->dev, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3300                                    rc, err);
3301                         return -1;
3302
3303                 case RING_FREE_REQ_RING_TYPE_RX:
3304                         netdev_err(bp->dev, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3305                                    rc, err);
3306                         return -1;
3307
3308                 case RING_FREE_REQ_RING_TYPE_TX:
3309                         netdev_err(bp->dev, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3310                                    rc, err);
3311                         return -1;
3312
3313                 default:
3314                         netdev_err(bp->dev, "Invalid ring\n");
3315                         return -1;
3316                 }
3317         }
3318         ring->fw_ring_id = ring_id;
3319         return rc;
3320 }
3321
3322 static int bnxt_hwrm_ring_alloc(struct bnxt *bp)
3323 {
3324         int i, rc = 0;
3325
3326         for (i = 0; i < bp->cp_nr_rings; i++) {
3327                 struct bnxt_napi *bnapi = bp->bnapi[i];
3328                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3329                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3330
3331                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_CMPL, i,
3332                                               INVALID_STATS_CTX_ID);
3333                 if (rc)
3334                         goto err_out;
3335                 cpr->cp_doorbell = bp->bar1 + i * 0x80;
3336                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
3337                 bp->grp_info[i].cp_fw_ring_id = ring->fw_ring_id;
3338         }
3339
3340         for (i = 0; i < bp->tx_nr_rings; i++) {
3341                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3342                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3343                 u32 map_idx = txr->bnapi->index;
3344                 u16 fw_stats_ctx = bp->grp_info[map_idx].fw_stats_ctx;
3345
3346                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_TX,
3347                                               map_idx, fw_stats_ctx);
3348                 if (rc)
3349                         goto err_out;
3350                 txr->tx_doorbell = bp->bar1 + map_idx * 0x80;
3351         }
3352
3353         for (i = 0; i < bp->rx_nr_rings; i++) {
3354                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3355                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3356                 u32 map_idx = rxr->bnapi->index;
3357
3358                 rc = hwrm_ring_alloc_send_msg(bp, ring, HWRM_RING_ALLOC_RX,
3359                                               map_idx, INVALID_STATS_CTX_ID);
3360                 if (rc)
3361                         goto err_out;
3362                 rxr->rx_doorbell = bp->bar1 + map_idx * 0x80;
3363                 writel(DB_KEY_RX | rxr->rx_prod, rxr->rx_doorbell);
3364                 bp->grp_info[map_idx].rx_fw_ring_id = ring->fw_ring_id;
3365         }
3366
3367         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3368                 for (i = 0; i < bp->rx_nr_rings; i++) {
3369                         struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3370                         struct bnxt_ring_struct *ring =
3371                                                 &rxr->rx_agg_ring_struct;
3372                         u32 grp_idx = rxr->bnapi->index;
3373                         u32 map_idx = grp_idx + bp->rx_nr_rings;
3374
3375                         rc = hwrm_ring_alloc_send_msg(bp, ring,
3376                                                       HWRM_RING_ALLOC_AGG,
3377                                                       map_idx,
3378                                                       INVALID_STATS_CTX_ID);
3379                         if (rc)
3380                                 goto err_out;
3381
3382                         rxr->rx_agg_doorbell = bp->bar1 + map_idx * 0x80;
3383                         writel(DB_KEY_RX | rxr->rx_agg_prod,
3384                                rxr->rx_agg_doorbell);
3385                         bp->grp_info[grp_idx].agg_fw_ring_id = ring->fw_ring_id;
3386                 }
3387         }
3388 err_out:
3389         return rc;
3390 }
3391
3392 static int hwrm_ring_free_send_msg(struct bnxt *bp,
3393                                    struct bnxt_ring_struct *ring,
3394                                    u32 ring_type, int cmpl_ring_id)
3395 {
3396         int rc;
3397         struct hwrm_ring_free_input req = {0};
3398         struct hwrm_ring_free_output *resp = bp->hwrm_cmd_resp_addr;
3399         u16 error_code;
3400
3401         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_FREE, -1, -1);
3402         req.ring_type = ring_type;
3403         req.ring_id = cpu_to_le16(ring->fw_ring_id);
3404
3405         mutex_lock(&bp->hwrm_cmd_lock);
3406         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3407         error_code = le16_to_cpu(resp->error_code);
3408         mutex_unlock(&bp->hwrm_cmd_lock);
3409
3410         if (rc || error_code) {
3411                 switch (ring_type) {
3412                 case RING_FREE_REQ_RING_TYPE_CMPL:
3413                         netdev_err(bp->dev, "hwrm_ring_free cp failed. rc:%d\n",
3414                                    rc);
3415                         return rc;
3416                 case RING_FREE_REQ_RING_TYPE_RX:
3417                         netdev_err(bp->dev, "hwrm_ring_free rx failed. rc:%d\n",
3418                                    rc);
3419                         return rc;
3420                 case RING_FREE_REQ_RING_TYPE_TX:
3421                         netdev_err(bp->dev, "hwrm_ring_free tx failed. rc:%d\n",
3422                                    rc);
3423                         return rc;
3424                 default:
3425                         netdev_err(bp->dev, "Invalid ring\n");
3426                         return -1;
3427                 }
3428         }
3429         return 0;
3430 }
3431
3432 static void bnxt_hwrm_ring_free(struct bnxt *bp, bool close_path)
3433 {
3434         int i;
3435
3436         if (!bp->bnapi)
3437                 return;
3438
3439         for (i = 0; i < bp->tx_nr_rings; i++) {
3440                 struct bnxt_tx_ring_info *txr = &bp->tx_ring[i];
3441                 struct bnxt_ring_struct *ring = &txr->tx_ring_struct;
3442                 u32 grp_idx = txr->bnapi->index;
3443                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3444
3445                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3446                         hwrm_ring_free_send_msg(bp, ring,
3447                                                 RING_FREE_REQ_RING_TYPE_TX,
3448                                                 close_path ? cmpl_ring_id :
3449                                                 INVALID_HW_RING_ID);
3450                         ring->fw_ring_id = INVALID_HW_RING_ID;
3451                 }
3452         }
3453
3454         for (i = 0; i < bp->rx_nr_rings; i++) {
3455                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3456                 struct bnxt_ring_struct *ring = &rxr->rx_ring_struct;
3457                 u32 grp_idx = rxr->bnapi->index;
3458                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3459
3460                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3461                         hwrm_ring_free_send_msg(bp, ring,
3462                                                 RING_FREE_REQ_RING_TYPE_RX,
3463                                                 close_path ? cmpl_ring_id :
3464                                                 INVALID_HW_RING_ID);
3465                         ring->fw_ring_id = INVALID_HW_RING_ID;
3466                         bp->grp_info[grp_idx].rx_fw_ring_id =
3467                                 INVALID_HW_RING_ID;
3468                 }
3469         }
3470
3471         for (i = 0; i < bp->rx_nr_rings; i++) {
3472                 struct bnxt_rx_ring_info *rxr = &bp->rx_ring[i];
3473                 struct bnxt_ring_struct *ring = &rxr->rx_agg_ring_struct;
3474                 u32 grp_idx = rxr->bnapi->index;
3475                 u32 cmpl_ring_id = bp->grp_info[grp_idx].cp_fw_ring_id;
3476
3477                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3478                         hwrm_ring_free_send_msg(bp, ring,
3479                                                 RING_FREE_REQ_RING_TYPE_RX,
3480                                                 close_path ? cmpl_ring_id :
3481                                                 INVALID_HW_RING_ID);
3482                         ring->fw_ring_id = INVALID_HW_RING_ID;
3483                         bp->grp_info[grp_idx].agg_fw_ring_id =
3484                                 INVALID_HW_RING_ID;
3485                 }
3486         }
3487
3488         for (i = 0; i < bp->cp_nr_rings; i++) {
3489                 struct bnxt_napi *bnapi = bp->bnapi[i];
3490                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3491                 struct bnxt_ring_struct *ring = &cpr->cp_ring_struct;
3492
3493                 if (ring->fw_ring_id != INVALID_HW_RING_ID) {
3494                         hwrm_ring_free_send_msg(bp, ring,
3495                                                 RING_FREE_REQ_RING_TYPE_CMPL,
3496                                                 INVALID_HW_RING_ID);
3497                         ring->fw_ring_id = INVALID_HW_RING_ID;
3498                         bp->grp_info[i].cp_fw_ring_id = INVALID_HW_RING_ID;
3499                 }
3500         }
3501 }
3502
3503 int bnxt_hwrm_set_coal(struct bnxt *bp)
3504 {
3505         int i, rc = 0;
3506         struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req = {0};
3507         u16 max_buf, max_buf_irq;
3508         u16 buf_tmr, buf_tmr_irq;
3509         u32 flags;
3510
3511         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS,
3512                                -1, -1);
3513
3514         /* Each rx completion (2 records) should be DMAed immediately */
3515         max_buf = min_t(u16, bp->coal_bufs / 4, 2);
3516         /* max_buf must not be zero */
3517         max_buf = clamp_t(u16, max_buf, 1, 63);
3518         max_buf_irq = clamp_t(u16, bp->coal_bufs_irq, 1, 63);
3519         buf_tmr = max_t(u16, bp->coal_ticks / 4, 1);
3520         buf_tmr_irq = max_t(u16, bp->coal_ticks_irq, 1);
3521
3522         flags = RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET;
3523
3524         /* RING_IDLE generates more IRQs for lower latency.  Enable it only
3525          * if coal_ticks is less than 25 us.
3526          */
3527         if (BNXT_COAL_TIMER_TO_USEC(bp->coal_ticks) < 25)
3528                 flags |= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE;
3529
3530         req.flags = cpu_to_le16(flags);
3531         req.num_cmpl_dma_aggr = cpu_to_le16(max_buf);
3532         req.num_cmpl_dma_aggr_during_int = cpu_to_le16(max_buf_irq);
3533         req.cmpl_aggr_dma_tmr = cpu_to_le16(buf_tmr);
3534         req.cmpl_aggr_dma_tmr_during_int = cpu_to_le16(buf_tmr_irq);
3535         req.int_lat_tmr_min = cpu_to_le16(buf_tmr);
3536         req.int_lat_tmr_max = cpu_to_le16(bp->coal_ticks);
3537         req.num_cmpl_aggr_int = cpu_to_le16(bp->coal_bufs);
3538
3539         mutex_lock(&bp->hwrm_cmd_lock);
3540         for (i = 0; i < bp->cp_nr_rings; i++) {
3541                 req.ring_id = cpu_to_le16(bp->grp_info[i].cp_fw_ring_id);
3542
3543                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3544                                         HWRM_CMD_TIMEOUT);
3545                 if (rc)
3546                         break;
3547         }
3548         mutex_unlock(&bp->hwrm_cmd_lock);
3549         return rc;
3550 }
3551
3552 static int bnxt_hwrm_stat_ctx_free(struct bnxt *bp)
3553 {
3554         int rc = 0, i;
3555         struct hwrm_stat_ctx_free_input req = {0};
3556
3557         if (!bp->bnapi)
3558                 return 0;
3559
3560         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_FREE, -1, -1);
3561
3562         mutex_lock(&bp->hwrm_cmd_lock);
3563         for (i = 0; i < bp->cp_nr_rings; i++) {
3564                 struct bnxt_napi *bnapi = bp->bnapi[i];
3565                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3566
3567                 if (cpr->hw_stats_ctx_id != INVALID_STATS_CTX_ID) {
3568                         req.stat_ctx_id = cpu_to_le32(cpr->hw_stats_ctx_id);
3569
3570                         rc = _hwrm_send_message(bp, &req, sizeof(req),
3571                                                 HWRM_CMD_TIMEOUT);
3572                         if (rc)
3573                                 break;
3574
3575                         cpr->hw_stats_ctx_id = INVALID_STATS_CTX_ID;
3576                 }
3577         }
3578         mutex_unlock(&bp->hwrm_cmd_lock);
3579         return rc;
3580 }
3581
3582 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt *bp)
3583 {
3584         int rc = 0, i;
3585         struct hwrm_stat_ctx_alloc_input req = {0};
3586         struct hwrm_stat_ctx_alloc_output *resp = bp->hwrm_cmd_resp_addr;
3587
3588         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_STAT_CTX_ALLOC, -1, -1);
3589
3590         req.update_period_ms = cpu_to_le32(1000);
3591
3592         mutex_lock(&bp->hwrm_cmd_lock);
3593         for (i = 0; i < bp->cp_nr_rings; i++) {
3594                 struct bnxt_napi *bnapi = bp->bnapi[i];
3595                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
3596
3597                 req.stats_dma_addr = cpu_to_le64(cpr->hw_stats_map);
3598
3599                 rc = _hwrm_send_message(bp, &req, sizeof(req),
3600                                         HWRM_CMD_TIMEOUT);
3601                 if (rc)
3602                         break;
3603
3604                 cpr->hw_stats_ctx_id = le32_to_cpu(resp->stat_ctx_id);
3605
3606                 bp->grp_info[i].fw_stats_ctx = cpr->hw_stats_ctx_id;
3607         }
3608         mutex_unlock(&bp->hwrm_cmd_lock);
3609         return 0;
3610 }
3611
3612 int bnxt_hwrm_func_qcaps(struct bnxt *bp)
3613 {
3614         int rc = 0;
3615         struct hwrm_func_qcaps_input req = {0};
3616         struct hwrm_func_qcaps_output *resp = bp->hwrm_cmd_resp_addr;
3617
3618         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_QCAPS, -1, -1);
3619         req.fid = cpu_to_le16(0xffff);
3620
3621         mutex_lock(&bp->hwrm_cmd_lock);
3622         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3623         if (rc)
3624                 goto hwrm_func_qcaps_exit;
3625
3626         if (BNXT_PF(bp)) {
3627                 struct bnxt_pf_info *pf = &bp->pf;
3628
3629                 pf->fw_fid = le16_to_cpu(resp->fid);
3630                 pf->port_id = le16_to_cpu(resp->port_id);
3631                 memcpy(pf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3632                 memcpy(bp->dev->dev_addr, pf->mac_addr, ETH_ALEN);
3633                 pf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3634                 pf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3635                 pf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3636                 pf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3637                 pf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3638                 if (!pf->max_hw_ring_grps)
3639                         pf->max_hw_ring_grps = pf->max_tx_rings;
3640                 pf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3641                 pf->max_vnics = le16_to_cpu(resp->max_vnics);
3642                 pf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3643                 pf->first_vf_id = le16_to_cpu(resp->first_vf_id);
3644                 pf->max_vfs = le16_to_cpu(resp->max_vfs);
3645                 pf->max_encap_records = le32_to_cpu(resp->max_encap_records);
3646                 pf->max_decap_records = le32_to_cpu(resp->max_decap_records);
3647                 pf->max_tx_em_flows = le32_to_cpu(resp->max_tx_em_flows);
3648                 pf->max_tx_wm_flows = le32_to_cpu(resp->max_tx_wm_flows);
3649                 pf->max_rx_em_flows = le32_to_cpu(resp->max_rx_em_flows);
3650                 pf->max_rx_wm_flows = le32_to_cpu(resp->max_rx_wm_flows);
3651         } else {
3652 #ifdef CONFIG_BNXT_SRIOV
3653                 struct bnxt_vf_info *vf = &bp->vf;
3654
3655                 vf->fw_fid = le16_to_cpu(resp->fid);
3656                 memcpy(vf->mac_addr, resp->perm_mac_address, ETH_ALEN);
3657                 if (is_valid_ether_addr(vf->mac_addr))
3658                         /* overwrite netdev dev_adr with admin VF MAC */
3659                         memcpy(bp->dev->dev_addr, vf->mac_addr, ETH_ALEN);
3660                 else
3661                         random_ether_addr(bp->dev->dev_addr);
3662
3663                 vf->max_rsscos_ctxs = le16_to_cpu(resp->max_rsscos_ctx);
3664                 vf->max_cp_rings = le16_to_cpu(resp->max_cmpl_rings);
3665                 vf->max_tx_rings = le16_to_cpu(resp->max_tx_rings);
3666                 vf->max_rx_rings = le16_to_cpu(resp->max_rx_rings);
3667                 vf->max_hw_ring_grps = le32_to_cpu(resp->max_hw_ring_grps);
3668                 if (!vf->max_hw_ring_grps)
3669                         vf->max_hw_ring_grps = vf->max_tx_rings;
3670                 vf->max_l2_ctxs = le16_to_cpu(resp->max_l2_ctxs);
3671                 vf->max_vnics = le16_to_cpu(resp->max_vnics);
3672                 vf->max_stat_ctxs = le16_to_cpu(resp->max_stat_ctx);
3673 #endif
3674         }
3675
3676         bp->tx_push_thresh = 0;
3677         if (resp->flags &
3678             cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED))
3679                 bp->tx_push_thresh = BNXT_TX_PUSH_THRESH;
3680
3681 hwrm_func_qcaps_exit:
3682         mutex_unlock(&bp->hwrm_cmd_lock);
3683         return rc;
3684 }
3685
3686 static int bnxt_hwrm_func_reset(struct bnxt *bp)
3687 {
3688         struct hwrm_func_reset_input req = {0};
3689
3690         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_RESET, -1, -1);
3691         req.enables = 0;
3692
3693         return hwrm_send_message(bp, &req, sizeof(req), HWRM_RESET_TIMEOUT);
3694 }
3695
3696 static int bnxt_hwrm_queue_qportcfg(struct bnxt *bp)
3697 {
3698         int rc = 0;
3699         struct hwrm_queue_qportcfg_input req = {0};
3700         struct hwrm_queue_qportcfg_output *resp = bp->hwrm_cmd_resp_addr;
3701         u8 i, *qptr;
3702
3703         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_QUEUE_QPORTCFG, -1, -1);
3704
3705         mutex_lock(&bp->hwrm_cmd_lock);
3706         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3707         if (rc)
3708                 goto qportcfg_exit;
3709
3710         if (!resp->max_configurable_queues) {
3711                 rc = -EINVAL;
3712                 goto qportcfg_exit;
3713         }
3714         bp->max_tc = resp->max_configurable_queues;
3715         if (bp->max_tc > BNXT_MAX_QUEUE)
3716                 bp->max_tc = BNXT_MAX_QUEUE;
3717
3718         qptr = &resp->queue_id0;
3719         for (i = 0; i < bp->max_tc; i++) {
3720                 bp->q_info[i].queue_id = *qptr++;
3721                 bp->q_info[i].queue_profile = *qptr++;
3722         }
3723
3724 qportcfg_exit:
3725         mutex_unlock(&bp->hwrm_cmd_lock);
3726         return rc;
3727 }
3728
3729 static int bnxt_hwrm_ver_get(struct bnxt *bp)
3730 {
3731         int rc;
3732         struct hwrm_ver_get_input req = {0};
3733         struct hwrm_ver_get_output *resp = bp->hwrm_cmd_resp_addr;
3734
3735         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_VER_GET, -1, -1);
3736         req.hwrm_intf_maj = HWRM_VERSION_MAJOR;
3737         req.hwrm_intf_min = HWRM_VERSION_MINOR;
3738         req.hwrm_intf_upd = HWRM_VERSION_UPDATE;
3739         mutex_lock(&bp->hwrm_cmd_lock);
3740         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
3741         if (rc)
3742                 goto hwrm_ver_get_exit;
3743
3744         memcpy(&bp->ver_resp, resp, sizeof(struct hwrm_ver_get_output));
3745
3746         if (resp->hwrm_intf_maj < 1) {
3747                 netdev_warn(bp->dev, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3748                             resp->hwrm_intf_maj, resp->hwrm_intf_min,
3749                             resp->hwrm_intf_upd);
3750                 netdev_warn(bp->dev, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3751         }
3752         snprintf(bp->fw_ver_str, BC_HWRM_STR_LEN, "bc %d.%d.%d rm %d.%d.%d",
3753                  resp->hwrm_fw_maj, resp->hwrm_fw_min, resp->hwrm_fw_bld,
3754                  resp->hwrm_intf_maj, resp->hwrm_intf_min, resp->hwrm_intf_upd);
3755
3756 hwrm_ver_get_exit:
3757         mutex_unlock(&bp->hwrm_cmd_lock);
3758         return rc;
3759 }
3760
3761 static void bnxt_hwrm_free_tunnel_ports(struct bnxt *bp)
3762 {
3763         if (bp->vxlan_port_cnt) {
3764                 bnxt_hwrm_tunnel_dst_port_free(
3765                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
3766         }
3767         bp->vxlan_port_cnt = 0;
3768         if (bp->nge_port_cnt) {
3769                 bnxt_hwrm_tunnel_dst_port_free(
3770                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE);
3771         }
3772         bp->nge_port_cnt = 0;
3773 }
3774
3775 static int bnxt_set_tpa(struct bnxt *bp, bool set_tpa)
3776 {
3777         int rc, i;
3778         u32 tpa_flags = 0;
3779
3780         if (set_tpa)
3781                 tpa_flags = bp->flags & BNXT_FLAG_TPA;
3782         for (i = 0; i < bp->nr_vnics; i++) {
3783                 rc = bnxt_hwrm_vnic_set_tpa(bp, i, tpa_flags);
3784                 if (rc) {
3785                         netdev_err(bp->dev, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3786                                    rc, i);
3787                         return rc;
3788                 }
3789         }
3790         return 0;
3791 }
3792
3793 static void bnxt_hwrm_clear_vnic_rss(struct bnxt *bp)
3794 {
3795         int i;
3796
3797         for (i = 0; i < bp->nr_vnics; i++)
3798                 bnxt_hwrm_vnic_set_rss(bp, i, false);
3799 }
3800
3801 static void bnxt_hwrm_resource_free(struct bnxt *bp, bool close_path,
3802                                     bool irq_re_init)
3803 {
3804         if (bp->vnic_info) {
3805                 bnxt_hwrm_clear_vnic_filter(bp);
3806                 /* clear all RSS setting before free vnic ctx */
3807                 bnxt_hwrm_clear_vnic_rss(bp);
3808                 bnxt_hwrm_vnic_ctx_free(bp);
3809                 /* before free the vnic, undo the vnic tpa settings */
3810                 if (bp->flags & BNXT_FLAG_TPA)
3811                         bnxt_set_tpa(bp, false);
3812                 bnxt_hwrm_vnic_free(bp);
3813         }
3814         bnxt_hwrm_ring_free(bp, close_path);
3815         bnxt_hwrm_ring_grp_free(bp);
3816         if (irq_re_init) {
3817                 bnxt_hwrm_stat_ctx_free(bp);
3818                 bnxt_hwrm_free_tunnel_ports(bp);
3819         }
3820 }
3821
3822 static int bnxt_setup_vnic(struct bnxt *bp, u16 vnic_id)
3823 {
3824         int rc;
3825
3826         /* allocate context for vnic */
3827         rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic_id);
3828         if (rc) {
3829                 netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3830                            vnic_id, rc);
3831                 goto vnic_setup_err;
3832         }
3833         bp->rsscos_nr_ctxs++;
3834
3835         /* configure default vnic, ring grp */
3836         rc = bnxt_hwrm_vnic_cfg(bp, vnic_id);
3837         if (rc) {
3838                 netdev_err(bp->dev, "hwrm vnic %d cfg failure rc: %x\n",
3839                            vnic_id, rc);
3840                 goto vnic_setup_err;
3841         }
3842
3843         /* Enable RSS hashing on vnic */
3844         rc = bnxt_hwrm_vnic_set_rss(bp, vnic_id, true);
3845         if (rc) {
3846                 netdev_err(bp->dev, "hwrm vnic %d set rss failure rc: %x\n",
3847                            vnic_id, rc);
3848                 goto vnic_setup_err;
3849         }
3850
3851         if (bp->flags & BNXT_FLAG_AGG_RINGS) {
3852                 rc = bnxt_hwrm_vnic_set_hds(bp, vnic_id);
3853                 if (rc) {
3854                         netdev_err(bp->dev, "hwrm vnic %d set hds failure rc: %x\n",
3855                                    vnic_id, rc);
3856                 }
3857         }
3858
3859 vnic_setup_err:
3860         return rc;
3861 }
3862
3863 static int bnxt_alloc_rfs_vnics(struct bnxt *bp)
3864 {
3865 #ifdef CONFIG_RFS_ACCEL
3866         int i, rc = 0;
3867
3868         for (i = 0; i < bp->rx_nr_rings; i++) {
3869                 u16 vnic_id = i + 1;
3870                 u16 ring_id = i;
3871
3872                 if (vnic_id >= bp->nr_vnics)
3873                         break;
3874
3875                 bp->vnic_info[vnic_id].flags |= BNXT_VNIC_RFS_FLAG;
3876                 rc = bnxt_hwrm_vnic_alloc(bp, vnic_id, ring_id, 1);
3877                 if (rc) {
3878                         netdev_err(bp->dev, "hwrm vnic %d alloc failure rc: %x\n",
3879                                    vnic_id, rc);
3880                         break;
3881                 }
3882                 rc = bnxt_setup_vnic(bp, vnic_id);
3883                 if (rc)
3884                         break;
3885         }
3886         return rc;
3887 #else
3888         return 0;
3889 #endif
3890 }
3891
3892 static int bnxt_cfg_rx_mode(struct bnxt *);
3893
3894 static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
3895 {
3896         int rc = 0;
3897
3898         if (irq_re_init) {
3899                 rc = bnxt_hwrm_stat_ctx_alloc(bp);
3900                 if (rc) {
3901                         netdev_err(bp->dev, "hwrm stat ctx alloc failure rc: %x\n",
3902                                    rc);
3903                         goto err_out;
3904                 }
3905         }
3906
3907         rc = bnxt_hwrm_ring_alloc(bp);
3908         if (rc) {
3909                 netdev_err(bp->dev, "hwrm ring alloc failure rc: %x\n", rc);
3910                 goto err_out;
3911         }
3912
3913         rc = bnxt_hwrm_ring_grp_alloc(bp);
3914         if (rc) {
3915                 netdev_err(bp->dev, "hwrm_ring_grp alloc failure: %x\n", rc);
3916                 goto err_out;
3917         }
3918
3919         /* default vnic 0 */
3920         rc = bnxt_hwrm_vnic_alloc(bp, 0, 0, bp->rx_nr_rings);
3921         if (rc) {
3922                 netdev_err(bp->dev, "hwrm vnic alloc failure rc: %x\n", rc);
3923                 goto err_out;
3924         }
3925
3926         rc = bnxt_setup_vnic(bp, 0);
3927         if (rc)
3928                 goto err_out;
3929
3930         if (bp->flags & BNXT_FLAG_RFS) {
3931                 rc = bnxt_alloc_rfs_vnics(bp);
3932                 if (rc)
3933                         goto err_out;
3934         }
3935
3936         if (bp->flags & BNXT_FLAG_TPA) {
3937                 rc = bnxt_set_tpa(bp, true);
3938                 if (rc)
3939                         goto err_out;
3940         }
3941
3942         if (BNXT_VF(bp))
3943                 bnxt_update_vf_mac(bp);
3944
3945         /* Filter for default vnic 0 */
3946         rc = bnxt_hwrm_set_vnic_filter(bp, 0, 0, bp->dev->dev_addr);
3947         if (rc) {
3948                 netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n", rc);
3949                 goto err_out;
3950         }
3951         bp->vnic_info[0].uc_filter_count = 1;
3952
3953         bp->vnic_info[0].rx_mask = CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
3954
3955         if ((bp->dev->flags & IFF_PROMISC) && BNXT_PF(bp))
3956                 bp->vnic_info[0].rx_mask |=
3957                                 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
3958
3959         rc = bnxt_cfg_rx_mode(bp);
3960         if (rc)
3961                 goto err_out;
3962
3963         rc = bnxt_hwrm_set_coal(bp);
3964         if (rc)
3965                 netdev_warn(bp->dev, "HWRM set coalescing failure rc: %x\n",
3966                             rc);
3967
3968         return 0;
3969
3970 err_out:
3971         bnxt_hwrm_resource_free(bp, 0, true);
3972
3973         return rc;
3974 }
3975
3976 static int bnxt_shutdown_nic(struct bnxt *bp, bool irq_re_init)
3977 {
3978         bnxt_hwrm_resource_free(bp, 1, irq_re_init);
3979         return 0;
3980 }
3981
3982 static int bnxt_init_nic(struct bnxt *bp, bool irq_re_init)
3983 {
3984         bnxt_init_rx_rings(bp);
3985         bnxt_init_tx_rings(bp);
3986         bnxt_init_ring_grps(bp, irq_re_init);
3987         bnxt_init_vnics(bp);
3988
3989         return bnxt_init_chip(bp, irq_re_init);
3990 }
3991
3992 static void bnxt_disable_int(struct bnxt *bp)
3993 {
3994         int i;
3995
3996         if (!bp->bnapi)
3997                 return;
3998
3999         for (i = 0; i < bp->cp_nr_rings; i++) {
4000                 struct bnxt_napi *bnapi = bp->bnapi[i];
4001                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4002
4003                 BNXT_CP_DB(cpr->cp_doorbell, cpr->cp_raw_cons);
4004         }
4005 }
4006
4007 static void bnxt_enable_int(struct bnxt *bp)
4008 {
4009         int i;
4010
4011         atomic_set(&bp->intr_sem, 0);
4012         for (i = 0; i < bp->cp_nr_rings; i++) {
4013                 struct bnxt_napi *bnapi = bp->bnapi[i];
4014                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4015
4016                 BNXT_CP_DB_REARM(cpr->cp_doorbell, cpr->cp_raw_cons);
4017         }
4018 }
4019
4020 static int bnxt_set_real_num_queues(struct bnxt *bp)
4021 {
4022         int rc;
4023         struct net_device *dev = bp->dev;
4024
4025         rc = netif_set_real_num_tx_queues(dev, bp->tx_nr_rings);
4026         if (rc)
4027                 return rc;
4028
4029         rc = netif_set_real_num_rx_queues(dev, bp->rx_nr_rings);
4030         if (rc)
4031                 return rc;
4032
4033 #ifdef CONFIG_RFS_ACCEL
4034         if (bp->flags & BNXT_FLAG_RFS)
4035                 dev->rx_cpu_rmap = alloc_irq_cpu_rmap(bp->rx_nr_rings);
4036 #endif
4037
4038         return rc;
4039 }
4040
4041 static int bnxt_trim_rings(struct bnxt *bp, int *rx, int *tx, int max,
4042                            bool shared)
4043 {
4044         int _rx = *rx, _tx = *tx;
4045
4046         if (shared) {
4047                 *rx = min_t(int, _rx, max);
4048                 *tx = min_t(int, _tx, max);
4049         } else {
4050                 if (max < 2)
4051                         return -ENOMEM;
4052
4053                 while (_rx + _tx > max) {
4054                         if (_rx > _tx && _rx > 1)
4055                                 _rx--;
4056                         else if (_tx > 1)
4057                                 _tx--;
4058                 }
4059                 *rx = _rx;
4060                 *tx = _tx;
4061         }
4062         return 0;
4063 }
4064
4065 static int bnxt_setup_msix(struct bnxt *bp)
4066 {
4067         struct msix_entry *msix_ent;
4068         struct net_device *dev = bp->dev;
4069         int i, total_vecs, rc = 0;
4070         const int len = sizeof(bp->irq_tbl[0].name);
4071
4072         bp->flags &= ~BNXT_FLAG_USING_MSIX;
4073         total_vecs = bp->cp_nr_rings;
4074
4075         msix_ent = kcalloc(total_vecs, sizeof(struct msix_entry), GFP_KERNEL);
4076         if (!msix_ent)
4077                 return -ENOMEM;
4078
4079         for (i = 0; i < total_vecs; i++) {
4080                 msix_ent[i].entry = i;
4081                 msix_ent[i].vector = 0;
4082         }
4083
4084         total_vecs = pci_enable_msix_range(bp->pdev, msix_ent, 1, total_vecs);
4085         if (total_vecs < 0) {
4086                 rc = -ENODEV;
4087                 goto msix_setup_exit;
4088         }
4089
4090         bp->irq_tbl = kcalloc(total_vecs, sizeof(struct bnxt_irq), GFP_KERNEL);
4091         if (bp->irq_tbl) {
4092                 int tcs;
4093
4094                 /* Trim rings based upon num of vectors allocated */
4095                 rc = bnxt_trim_rings(bp, &bp->rx_nr_rings, &bp->tx_nr_rings,
4096                                      total_vecs, true);
4097                 if (rc)
4098                         goto msix_setup_exit;
4099
4100                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4101                 tcs = netdev_get_num_tc(dev);
4102                 if (tcs > 1) {
4103                         bp->tx_nr_rings_per_tc = bp->tx_nr_rings / tcs;
4104                         if (bp->tx_nr_rings_per_tc == 0) {
4105                                 netdev_reset_tc(dev);
4106                                 bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4107                         } else {
4108                                 int i, off, count;
4109
4110                                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tcs;
4111                                 for (i = 0; i < tcs; i++) {
4112                                         count = bp->tx_nr_rings_per_tc;
4113                                         off = i * count;
4114                                         netdev_set_tc_queue(dev, i, count, off);
4115                                 }
4116                         }
4117                 }
4118                 bp->cp_nr_rings = max_t(int, bp->rx_nr_rings, bp->tx_nr_rings);
4119
4120                 for (i = 0; i < bp->cp_nr_rings; i++) {
4121                         bp->irq_tbl[i].vector = msix_ent[i].vector;
4122                         snprintf(bp->irq_tbl[i].name, len,
4123                                  "%s-%s-%d", dev->name, "TxRx", i);
4124                         bp->irq_tbl[i].handler = bnxt_msix;
4125                 }
4126                 rc = bnxt_set_real_num_queues(bp);
4127                 if (rc)
4128                         goto msix_setup_exit;
4129         } else {
4130                 rc = -ENOMEM;
4131                 goto msix_setup_exit;
4132         }
4133         bp->flags |= BNXT_FLAG_USING_MSIX;
4134         kfree(msix_ent);
4135         return 0;
4136
4137 msix_setup_exit:
4138         netdev_err(bp->dev, "bnxt_setup_msix err: %x\n", rc);
4139         pci_disable_msix(bp->pdev);
4140         kfree(msix_ent);
4141         return rc;
4142 }
4143
4144 static int bnxt_setup_inta(struct bnxt *bp)
4145 {
4146         int rc;
4147         const int len = sizeof(bp->irq_tbl[0].name);
4148
4149         if (netdev_get_num_tc(bp->dev))
4150                 netdev_reset_tc(bp->dev);
4151
4152         bp->irq_tbl = kcalloc(1, sizeof(struct bnxt_irq), GFP_KERNEL);
4153         if (!bp->irq_tbl) {
4154                 rc = -ENOMEM;
4155                 return rc;
4156         }
4157         bp->rx_nr_rings = 1;
4158         bp->tx_nr_rings = 1;
4159         bp->cp_nr_rings = 1;
4160         bp->tx_nr_rings_per_tc = bp->tx_nr_rings;
4161         bp->irq_tbl[0].vector = bp->pdev->irq;
4162         snprintf(bp->irq_tbl[0].name, len,
4163                  "%s-%s-%d", bp->dev->name, "TxRx", 0);
4164         bp->irq_tbl[0].handler = bnxt_inta;
4165         rc = bnxt_set_real_num_queues(bp);
4166         return rc;
4167 }
4168
4169 static int bnxt_setup_int_mode(struct bnxt *bp)
4170 {
4171         int rc = 0;
4172
4173         if (bp->flags & BNXT_FLAG_MSIX_CAP)
4174                 rc = bnxt_setup_msix(bp);
4175
4176         if (!(bp->flags & BNXT_FLAG_USING_MSIX)) {
4177                 /* fallback to INTA */
4178                 rc = bnxt_setup_inta(bp);
4179         }
4180         return rc;
4181 }
4182
4183 static void bnxt_free_irq(struct bnxt *bp)
4184 {
4185         struct bnxt_irq *irq;
4186         int i;
4187
4188 #ifdef CONFIG_RFS_ACCEL
4189         free_irq_cpu_rmap(bp->dev->rx_cpu_rmap);
4190         bp->dev->rx_cpu_rmap = NULL;
4191 #endif
4192         if (!bp->irq_tbl)
4193                 return;
4194
4195         for (i = 0; i < bp->cp_nr_rings; i++) {
4196                 irq = &bp->irq_tbl[i];
4197                 if (irq->requested)
4198                         free_irq(irq->vector, bp->bnapi[i]);
4199                 irq->requested = 0;
4200         }
4201         if (bp->flags & BNXT_FLAG_USING_MSIX)
4202                 pci_disable_msix(bp->pdev);
4203         kfree(bp->irq_tbl);
4204         bp->irq_tbl = NULL;
4205 }
4206
4207 static int bnxt_request_irq(struct bnxt *bp)
4208 {
4209         int i, j, rc = 0;
4210         unsigned long flags = 0;
4211 #ifdef CONFIG_RFS_ACCEL
4212         struct cpu_rmap *rmap = bp->dev->rx_cpu_rmap;
4213 #endif
4214
4215         if (!(bp->flags & BNXT_FLAG_USING_MSIX))
4216                 flags = IRQF_SHARED;
4217
4218         for (i = 0, j = 0; i < bp->cp_nr_rings; i++) {
4219                 struct bnxt_irq *irq = &bp->irq_tbl[i];
4220 #ifdef CONFIG_RFS_ACCEL
4221                 if (rmap && bp->bnapi[i]->rx_ring) {
4222                         rc = irq_cpu_rmap_add(rmap, irq->vector);
4223                         if (rc)
4224                                 netdev_warn(bp->dev, "failed adding irq rmap for ring %d\n",
4225                                             j);
4226                         j++;
4227                 }
4228 #endif
4229                 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
4230                                  bp->bnapi[i]);
4231                 if (rc)
4232                         break;
4233
4234                 irq->requested = 1;
4235         }
4236         return rc;
4237 }
4238
4239 static void bnxt_del_napi(struct bnxt *bp)
4240 {
4241         int i;
4242
4243         if (!bp->bnapi)
4244                 return;
4245
4246         for (i = 0; i < bp->cp_nr_rings; i++) {
4247                 struct bnxt_napi *bnapi = bp->bnapi[i];
4248
4249                 napi_hash_del(&bnapi->napi);
4250                 netif_napi_del(&bnapi->napi);
4251         }
4252 }
4253
4254 static void bnxt_init_napi(struct bnxt *bp)
4255 {
4256         int i;
4257         struct bnxt_napi *bnapi;
4258
4259         if (bp->flags & BNXT_FLAG_USING_MSIX) {
4260                 for (i = 0; i < bp->cp_nr_rings; i++) {
4261                         bnapi = bp->bnapi[i];
4262                         netif_napi_add(bp->dev, &bnapi->napi,
4263                                        bnxt_poll, 64);
4264                 }
4265         } else {
4266                 bnapi = bp->bnapi[0];
4267                 netif_napi_add(bp->dev, &bnapi->napi, bnxt_poll, 64);
4268         }
4269 }
4270
4271 static void bnxt_disable_napi(struct bnxt *bp)
4272 {
4273         int i;
4274
4275         if (!bp->bnapi)
4276                 return;
4277
4278         for (i = 0; i < bp->cp_nr_rings; i++) {
4279                 napi_disable(&bp->bnapi[i]->napi);
4280                 bnxt_disable_poll(bp->bnapi[i]);
4281         }
4282 }
4283
4284 static void bnxt_enable_napi(struct bnxt *bp)
4285 {
4286         int i;
4287
4288         for (i = 0; i < bp->cp_nr_rings; i++) {
4289                 bnxt_enable_poll(bp->bnapi[i]);
4290                 napi_enable(&bp->bnapi[i]->napi);
4291         }
4292 }
4293
4294 static void bnxt_tx_disable(struct bnxt *bp)
4295 {
4296         int i;
4297         struct bnxt_tx_ring_info *txr;
4298         struct netdev_queue *txq;
4299
4300         if (bp->tx_ring) {
4301                 for (i = 0; i < bp->tx_nr_rings; i++) {
4302                         txr = &bp->tx_ring[i];
4303                         txq = netdev_get_tx_queue(bp->dev, i);
4304                         __netif_tx_lock(txq, smp_processor_id());
4305                         txr->dev_state = BNXT_DEV_STATE_CLOSING;
4306                         __netif_tx_unlock(txq);
4307                 }
4308         }
4309         /* Stop all TX queues */
4310         netif_tx_disable(bp->dev);
4311         netif_carrier_off(bp->dev);
4312 }
4313
4314 static void bnxt_tx_enable(struct bnxt *bp)
4315 {
4316         int i;
4317         struct bnxt_tx_ring_info *txr;
4318         struct netdev_queue *txq;
4319
4320         for (i = 0; i < bp->tx_nr_rings; i++) {
4321                 txr = &bp->tx_ring[i];
4322                 txq = netdev_get_tx_queue(bp->dev, i);
4323                 txr->dev_state = 0;
4324         }
4325         netif_tx_wake_all_queues(bp->dev);
4326         if (bp->link_info.link_up)
4327                 netif_carrier_on(bp->dev);
4328 }
4329
4330 static void bnxt_report_link(struct bnxt *bp)
4331 {
4332         if (bp->link_info.link_up) {
4333                 const char *duplex;
4334                 const char *flow_ctrl;
4335                 u16 speed;
4336
4337                 netif_carrier_on(bp->dev);
4338                 if (bp->link_info.duplex == BNXT_LINK_DUPLEX_FULL)
4339                         duplex = "full";
4340                 else
4341                         duplex = "half";
4342                 if (bp->link_info.pause == BNXT_LINK_PAUSE_BOTH)
4343                         flow_ctrl = "ON - receive & transmit";
4344                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_TX)
4345                         flow_ctrl = "ON - transmit";
4346                 else if (bp->link_info.pause == BNXT_LINK_PAUSE_RX)
4347                         flow_ctrl = "ON - receive";
4348                 else
4349                         flow_ctrl = "none";
4350                 speed = bnxt_fw_to_ethtool_speed(bp->link_info.link_speed);
4351                 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4352                             speed, duplex, flow_ctrl);
4353         } else {
4354                 netif_carrier_off(bp->dev);
4355                 netdev_err(bp->dev, "NIC Link is Down\n");
4356         }
4357 }
4358
4359 static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)
4360 {
4361         int rc = 0;
4362         struct bnxt_link_info *link_info = &bp->link_info;
4363         struct hwrm_port_phy_qcfg_input req = {0};
4364         struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;
4365         u8 link_up = link_info->link_up;
4366
4367         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
4368
4369         mutex_lock(&bp->hwrm_cmd_lock);
4370         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4371         if (rc) {
4372                 mutex_unlock(&bp->hwrm_cmd_lock);
4373                 return rc;
4374         }
4375
4376         memcpy(&link_info->phy_qcfg_resp, resp, sizeof(*resp));
4377         link_info->phy_link_status = resp->link;
4378         link_info->duplex =  resp->duplex;
4379         link_info->pause = resp->pause;
4380         link_info->auto_mode = resp->auto_mode;
4381         link_info->auto_pause_setting = resp->auto_pause;
4382         link_info->force_pause_setting = resp->force_pause;
4383         link_info->duplex_setting = resp->duplex;
4384         if (link_info->phy_link_status == BNXT_LINK_LINK)
4385                 link_info->link_speed = le16_to_cpu(resp->link_speed);
4386         else
4387                 link_info->link_speed = 0;
4388         link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);
4389         link_info->auto_link_speed = le16_to_cpu(resp->auto_link_speed);
4390         link_info->support_speeds = le16_to_cpu(resp->support_speeds);
4391         link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);
4392         link_info->preemphasis = le32_to_cpu(resp->preemphasis);
4393         link_info->phy_ver[0] = resp->phy_maj;
4394         link_info->phy_ver[1] = resp->phy_min;
4395         link_info->phy_ver[2] = resp->phy_bld;
4396         link_info->media_type = resp->media_type;
4397         link_info->transceiver = resp->transceiver_type;
4398         link_info->phy_addr = resp->phy_addr;
4399
4400         /* TODO: need to add more logic to report VF link */
4401         if (chng_link_state) {
4402                 if (link_info->phy_link_status == BNXT_LINK_LINK)
4403                         link_info->link_up = 1;
4404                 else
4405                         link_info->link_up = 0;
4406                 if (link_up != link_info->link_up)
4407                         bnxt_report_link(bp);
4408         } else {
4409                 /* alwasy link down if not require to update link state */
4410                 link_info->link_up = 0;
4411         }
4412         mutex_unlock(&bp->hwrm_cmd_lock);
4413         return 0;
4414 }
4415
4416 static void
4417 bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)
4418 {
4419         if (bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) {
4420                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4421                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4422                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4423                         req->auto_pause |= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX;
4424                 req->enables |=
4425                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE);
4426         } else {
4427                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_RX)
4428                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX;
4429                 if (bp->link_info.req_flow_ctrl & BNXT_LINK_PAUSE_TX)
4430                         req->force_pause |= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX;
4431                 req->enables |=
4432                         cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE);
4433         }
4434 }
4435
4436 static void bnxt_hwrm_set_link_common(struct bnxt *bp,
4437                                       struct hwrm_port_phy_cfg_input *req)
4438 {
4439         u8 autoneg = bp->link_info.autoneg;
4440         u16 fw_link_speed = bp->link_info.req_link_speed;
4441         u32 advertising = bp->link_info.advertising;
4442
4443         if (autoneg & BNXT_AUTONEG_SPEED) {
4444                 req->auto_mode |=
4445                         PORT_PHY_CFG_REQ_AUTO_MODE_MASK;
4446
4447                 req->enables |= cpu_to_le32(
4448                         PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);
4449                 req->auto_link_speed_mask = cpu_to_le16(advertising);
4450
4451                 req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);
4452                 req->flags |=
4453                         cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);
4454         } else {
4455                 req->force_link_speed = cpu_to_le16(fw_link_speed);
4456                 req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);
4457         }
4458
4459         /* currently don't support half duplex */
4460         req->auto_duplex = PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL;
4461         req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX);
4462         /* tell chimp that the setting takes effect immediately */
4463         req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY);
4464 }
4465
4466 int bnxt_hwrm_set_pause(struct bnxt *bp)
4467 {
4468         struct hwrm_port_phy_cfg_input req = {0};
4469         int rc;
4470
4471         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4472         bnxt_hwrm_set_pause_common(bp, &req);
4473
4474         if ((bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL) ||
4475             bp->link_info.force_link_chng)
4476                 bnxt_hwrm_set_link_common(bp, &req);
4477
4478         mutex_lock(&bp->hwrm_cmd_lock);
4479         rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4480         if (!rc && !(bp->link_info.autoneg & BNXT_AUTONEG_FLOW_CTRL)) {
4481                 /* since changing of pause setting doesn't trigger any link
4482                  * change event, the driver needs to update the current pause
4483                  * result upon successfully return of the phy_cfg command
4484                  */
4485                 bp->link_info.pause =
4486                 bp->link_info.force_pause_setting = bp->link_info.req_flow_ctrl;
4487                 bp->link_info.auto_pause_setting = 0;
4488                 if (!bp->link_info.force_link_chng)
4489                         bnxt_report_link(bp);
4490         }
4491         bp->link_info.force_link_chng = false;
4492         mutex_unlock(&bp->hwrm_cmd_lock);
4493         return rc;
4494 }
4495
4496 int bnxt_hwrm_set_link_setting(struct bnxt *bp, bool set_pause)
4497 {
4498         struct hwrm_port_phy_cfg_input req = {0};
4499
4500         bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_CFG, -1, -1);
4501         if (set_pause)
4502                 bnxt_hwrm_set_pause_common(bp, &req);
4503
4504         bnxt_hwrm_set_link_common(bp, &req);
4505         return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT);
4506 }
4507
4508 static int bnxt_update_phy_setting(struct bnxt *bp)
4509 {
4510         int rc;
4511         bool update_link = false;
4512         bool update_pause = false;
4513         struct bnxt_link_info *link_info = &bp->link_info;
4514
4515         rc = bnxt_update_link(bp, true);
4516         if (rc) {
4517                 netdev_err(bp->dev, "failed to update link (rc: %x)\n",
4518                            rc);
4519                 return rc;
4520         }
4521         if ((link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4522             link_info->auto_pause_setting != link_info->req_flow_ctrl)
4523                 update_pause = true;
4524         if (!(link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL) &&
4525             link_info->force_pause_setting != link_info->req_flow_ctrl)
4526                 update_pause = true;
4527         if (link_info->req_duplex != link_info->duplex_setting)
4528                 update_link = true;
4529         if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {
4530                 if (BNXT_AUTO_MODE(link_info->auto_mode))
4531                         update_link = true;
4532                 if (link_info->req_link_speed != link_info->force_link_speed)
4533                         update_link = true;
4534         } else {
4535                 if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)
4536                         update_link = true;
4537                 if (link_info->advertising != link_info->auto_link_speeds)
4538                         update_link = true;
4539                 if (link_info->req_link_speed != link_info->auto_link_speed)
4540                         update_link = true;
4541         }
4542
4543         if (update_link)
4544                 rc = bnxt_hwrm_set_link_setting(bp, update_pause);
4545         else if (update_pause)
4546                 rc = bnxt_hwrm_set_pause(bp);
4547         if (rc) {
4548                 netdev_err(bp->dev, "failed to update phy setting (rc: %x)\n",
4549                            rc);
4550                 return rc;
4551         }
4552
4553         return rc;
4554 }
4555
4556 /* Common routine to pre-map certain register block to different GRC window.
4557  * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4558  * in PF and 3 windows in VF that can be customized to map in different
4559  * register blocks.
4560  */
4561 static void bnxt_preset_reg_win(struct bnxt *bp)
4562 {
4563         if (BNXT_PF(bp)) {
4564                 /* CAG registers map to GRC window #4 */
4565                 writel(BNXT_CAG_REG_BASE,
4566                        bp->bar0 + BNXT_GRCPF_REG_WINDOW_BASE_OUT + 12);
4567         }
4568 }
4569
4570 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4571 {
4572         int rc = 0;
4573
4574         bnxt_preset_reg_win(bp);
4575         netif_carrier_off(bp->dev);
4576         if (irq_re_init) {
4577                 rc = bnxt_setup_int_mode(bp);
4578                 if (rc) {
4579                         netdev_err(bp->dev, "bnxt_setup_int_mode err: %x\n",
4580                                    rc);
4581                         return rc;
4582                 }
4583         }
4584         if ((bp->flags & BNXT_FLAG_RFS) &&
4585             !(bp->flags & BNXT_FLAG_USING_MSIX)) {
4586                 /* disable RFS if falling back to INTA */
4587                 bp->dev->hw_features &= ~NETIF_F_NTUPLE;
4588                 bp->flags &= ~BNXT_FLAG_RFS;
4589         }
4590
4591         rc = bnxt_alloc_mem(bp, irq_re_init);
4592         if (rc) {
4593                 netdev_err(bp->dev, "bnxt_alloc_mem err: %x\n", rc);
4594                 goto open_err_free_mem;
4595         }
4596
4597         if (irq_re_init) {
4598                 bnxt_init_napi(bp);
4599                 rc = bnxt_request_irq(bp);
4600                 if (rc) {
4601                         netdev_err(bp->dev, "bnxt_request_irq err: %x\n", rc);
4602                         goto open_err;
4603                 }
4604         }
4605
4606         bnxt_enable_napi(bp);
4607
4608         rc = bnxt_init_nic(bp, irq_re_init);
4609         if (rc) {
4610                 netdev_err(bp->dev, "bnxt_init_nic err: %x\n", rc);
4611                 goto open_err;
4612         }
4613
4614         if (link_re_init) {
4615                 rc = bnxt_update_phy_setting(bp);
4616                 if (rc)
4617                         goto open_err;
4618         }
4619
4620         if (irq_re_init) {
4621 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4622                 vxlan_get_rx_port(bp->dev);
4623 #endif
4624                 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4625                                 bp, htons(0x17c1),
4626                                 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE))
4627                         bp->nge_port_cnt = 1;
4628         }
4629
4630         set_bit(BNXT_STATE_OPEN, &bp->state);
4631         bnxt_enable_int(bp);
4632         /* Enable TX queues */
4633         bnxt_tx_enable(bp);
4634         mod_timer(&bp->timer, jiffies + bp->current_interval);
4635
4636         return 0;
4637
4638 open_err:
4639         bnxt_disable_napi(bp);
4640         bnxt_del_napi(bp);
4641
4642 open_err_free_mem:
4643         bnxt_free_skbs(bp);
4644         bnxt_free_irq(bp);
4645         bnxt_free_mem(bp, true);
4646         return rc;
4647 }
4648
4649 /* rtnl_lock held */
4650 int bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4651 {
4652         int rc = 0;
4653
4654         rc = __bnxt_open_nic(bp, irq_re_init, link_re_init);
4655         if (rc) {
4656                 netdev_err(bp->dev, "nic open fail (rc: %x)\n", rc);
4657                 dev_close(bp->dev);
4658         }
4659         return rc;
4660 }
4661
4662 static int bnxt_open(struct net_device *dev)
4663 {
4664         struct bnxt *bp = netdev_priv(dev);
4665         int rc = 0;
4666
4667         rc = bnxt_hwrm_func_reset(bp);
4668         if (rc) {
4669                 netdev_err(bp->dev, "hwrm chip reset failure rc: %x\n",
4670                            rc);
4671                 rc = -1;
4672                 return rc;
4673         }
4674         return __bnxt_open_nic(bp, true, true);
4675 }
4676
4677 static void bnxt_disable_int_sync(struct bnxt *bp)
4678 {
4679         int i;
4680
4681         atomic_inc(&bp->intr_sem);
4682         if (!netif_running(bp->dev))
4683                 return;
4684
4685         bnxt_disable_int(bp);
4686         for (i = 0; i < bp->cp_nr_rings; i++)
4687                 synchronize_irq(bp->irq_tbl[i].vector);
4688 }
4689
4690 int bnxt_close_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init)
4691 {
4692         int rc = 0;
4693
4694 #ifdef CONFIG_BNXT_SRIOV
4695         if (bp->sriov_cfg) {
4696                 rc = wait_event_interruptible_timeout(bp->sriov_cfg_wait,
4697                                                       !bp->sriov_cfg,
4698                                                       BNXT_SRIOV_CFG_WAIT_TMO);
4699                 if (rc)
4700                         netdev_warn(bp->dev, "timeout waiting for SRIOV config operation to complete!\n");
4701         }
4702 #endif
4703         /* Change device state to avoid TX queue wake up's */
4704         bnxt_tx_disable(bp);
4705
4706         clear_bit(BNXT_STATE_OPEN, &bp->state);
4707         smp_mb__after_atomic();
4708         while (test_bit(BNXT_STATE_IN_SP_TASK, &bp->state))
4709                 msleep(20);
4710
4711         /* Flush rings before disabling interrupts */
4712         bnxt_shutdown_nic(bp, irq_re_init);
4713
4714         /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4715
4716         bnxt_disable_napi(bp);
4717         bnxt_disable_int_sync(bp);
4718         del_timer_sync(&bp->timer);
4719         bnxt_free_skbs(bp);
4720
4721         if (irq_re_init) {
4722                 bnxt_free_irq(bp);
4723                 bnxt_del_napi(bp);
4724         }
4725         bnxt_free_mem(bp, irq_re_init);
4726         return rc;
4727 }
4728
4729 static int bnxt_close(struct net_device *dev)
4730 {
4731         struct bnxt *bp = netdev_priv(dev);
4732
4733         bnxt_close_nic(bp, true, true);
4734         return 0;
4735 }
4736
4737 /* rtnl_lock held */
4738 static int bnxt_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4739 {
4740         switch (cmd) {
4741         case SIOCGMIIPHY:
4742                 /* fallthru */
4743         case SIOCGMIIREG: {
4744                 if (!netif_running(dev))
4745                         return -EAGAIN;
4746
4747                 return 0;
4748         }
4749
4750         case SIOCSMIIREG:
4751                 if (!netif_running(dev))
4752                         return -EAGAIN;
4753
4754                 return 0;
4755
4756         default:
4757                 /* do nothing */
4758                 break;
4759         }
4760         return -EOPNOTSUPP;
4761 }
4762
4763 static struct rtnl_link_stats64 *
4764 bnxt_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
4765 {
4766         u32 i;
4767         struct bnxt *bp = netdev_priv(dev);
4768
4769         memset(stats, 0, sizeof(struct rtnl_link_stats64));
4770
4771         if (!bp->bnapi)
4772                 return stats;
4773
4774         /* TODO check if we need to synchronize with bnxt_close path */
4775         for (i = 0; i < bp->cp_nr_rings; i++) {
4776                 struct bnxt_napi *bnapi = bp->bnapi[i];
4777                 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
4778                 struct ctx_hw_stats *hw_stats = cpr->hw_stats;
4779
4780                 stats->rx_packets += le64_to_cpu(hw_stats->rx_ucast_pkts);
4781                 stats->rx_packets += le64_to_cpu(hw_stats->rx_mcast_pkts);
4782                 stats->rx_packets += le64_to_cpu(hw_stats->rx_bcast_pkts);
4783
4784                 stats->tx_packets += le64_to_cpu(hw_stats->tx_ucast_pkts);
4785                 stats->tx_packets += le64_to_cpu(hw_stats->tx_mcast_pkts);
4786                 stats->tx_packets += le64_to_cpu(hw_stats->tx_bcast_pkts);
4787
4788                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_ucast_bytes);
4789                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_mcast_bytes);
4790                 stats->rx_bytes += le64_to_cpu(hw_stats->rx_bcast_bytes);
4791
4792                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_ucast_bytes);
4793                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_mcast_bytes);
4794                 stats->tx_bytes += le64_to_cpu(hw_stats->tx_bcast_bytes);
4795
4796                 stats->rx_missed_errors +=
4797                         le64_to_cpu(hw_stats->rx_discard_pkts);
4798
4799                 stats->multicast += le64_to_cpu(hw_stats->rx_mcast_pkts);
4800
4801                 stats->rx_dropped += le64_to_cpu(hw_stats->rx_drop_pkts);
4802
4803                 stats->tx_dropped += le64_to_cpu(hw_stats->tx_drop_pkts);
4804         }
4805
4806         return stats;
4807 }
4808
4809 static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
4810 {
4811         struct net_device *dev = bp->dev;
4812         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4813         struct netdev_hw_addr *ha;
4814         u8 *haddr;
4815         int mc_count = 0;
4816         bool update = false;
4817         int off = 0;
4818
4819         netdev_for_each_mc_addr(ha, dev) {
4820                 if (mc_count >= BNXT_MAX_MC_ADDRS) {
4821                         *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4822                         vnic->mc_list_count = 0;
4823                         return false;
4824                 }
4825                 haddr = ha->addr;
4826                 if (!ether_addr_equal(haddr, vnic->mc_list + off)) {
4827                         memcpy(vnic->mc_list + off, haddr, ETH_ALEN);
4828                         update = true;
4829                 }
4830                 off += ETH_ALEN;
4831                 mc_count++;
4832         }
4833         if (mc_count)
4834                 *rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST;
4835
4836         if (mc_count != vnic->mc_list_count) {
4837                 vnic->mc_list_count = mc_count;
4838                 update = true;
4839         }
4840         return update;
4841 }
4842
4843 static bool bnxt_uc_list_updated(struct bnxt *bp)
4844 {
4845         struct net_device *dev = bp->dev;
4846         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4847         struct netdev_hw_addr *ha;
4848         int off = 0;
4849
4850         if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
4851                 return true;
4852
4853         netdev_for_each_uc_addr(ha, dev) {
4854                 if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
4855                         return true;
4856
4857                 off += ETH_ALEN;
4858         }
4859         return false;
4860 }
4861
4862 static void bnxt_set_rx_mode(struct net_device *dev)
4863 {
4864         struct bnxt *bp = netdev_priv(dev);
4865         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4866         u32 mask = vnic->rx_mask;
4867         bool mc_update = false;
4868         bool uc_update;
4869
4870         if (!netif_running(dev))
4871                 return;
4872
4873         mask &= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS |
4874                   CFA_L2_SET_RX_MASK_REQ_MASK_MCAST |
4875                   CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST);
4876
4877         /* Only allow PF to be in promiscuous mode */
4878         if ((dev->flags & IFF_PROMISC) && BNXT_PF(bp))
4879                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4880
4881         uc_update = bnxt_uc_list_updated(bp);
4882
4883         if (dev->flags & IFF_ALLMULTI) {
4884                 mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
4885                 vnic->mc_list_count = 0;
4886         } else {
4887                 mc_update = bnxt_mc_list_updated(bp, &mask);
4888         }
4889
4890         if (mask != vnic->rx_mask || uc_update || mc_update) {
4891                 vnic->rx_mask = mask;
4892
4893                 set_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event);
4894                 schedule_work(&bp->sp_task);
4895         }
4896 }
4897
4898 static int bnxt_cfg_rx_mode(struct bnxt *bp)
4899 {
4900         struct net_device *dev = bp->dev;
4901         struct bnxt_vnic_info *vnic = &bp->vnic_info[0];
4902         struct netdev_hw_addr *ha;
4903         int i, off = 0, rc;
4904         bool uc_update;
4905
4906         netif_addr_lock_bh(dev);
4907         uc_update = bnxt_uc_list_updated(bp);
4908         netif_addr_unlock_bh(dev);
4909
4910         if (!uc_update)
4911                 goto skip_uc;
4912
4913         mutex_lock(&bp->hwrm_cmd_lock);
4914         for (i = 1; i < vnic->uc_filter_count; i++) {
4915                 struct hwrm_cfa_l2_filter_free_input req = {0};
4916
4917                 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_CFA_L2_FILTER_FREE, -1,
4918                                        -1);
4919
4920                 req.l2_filter_id = vnic->fw_l2_filter_id[i];
4921
4922                 rc = _hwrm_send_message(bp, &req, sizeof(req),
4923                                         HWRM_CMD_TIMEOUT);
4924         }
4925         mutex_unlock(&bp->hwrm_cmd_lock);
4926
4927         vnic->uc_filter_count = 1;
4928
4929         netif_addr_lock_bh(dev);
4930         if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
4931                 vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
4932         } else {
4933                 netdev_for_each_uc_addr(ha, dev) {
4934                         memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
4935                         off += ETH_ALEN;
4936                         vnic->uc_filter_count++;
4937                 }
4938         }
4939         netif_addr_unlock_bh(dev);
4940
4941         for (i = 1, off = 0; i < vnic->uc_filter_count; i++, off += ETH_ALEN) {
4942                 rc = bnxt_hwrm_set_vnic_filter(bp, 0, i, vnic->uc_list + off);
4943                 if (rc) {
4944                         netdev_err(bp->dev, "HWRM vnic filter failure rc: %x\n",
4945                                    rc);
4946                         vnic->uc_filter_count = i;
4947                         return rc;
4948                 }
4949         }
4950
4951 skip_uc:
4952         rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, 0);
4953         if (rc)
4954                 netdev_err(bp->dev, "HWRM cfa l2 rx mask failure rc: %x\n",
4955                            rc);
4956
4957         return rc;
4958 }
4959
4960 static bool bnxt_rfs_capable(struct bnxt *bp)
4961 {
4962 #ifdef CONFIG_RFS_ACCEL
4963         struct bnxt_pf_info *pf = &bp->pf;
4964         int vnics;
4965
4966         if (BNXT_VF(bp) || !(bp->flags & BNXT_FLAG_MSIX_CAP))
4967                 return false;
4968
4969         vnics = 1 + bp->rx_nr_rings;
4970         if (vnics > pf->max_rsscos_ctxs || vnics > pf->max_vnics)
4971                 return false;
4972
4973         return true;
4974 #else
4975         return false;
4976 #endif
4977 }
4978
4979 static netdev_features_t bnxt_fix_features(struct net_device *dev,
4980                                            netdev_features_t features)
4981 {
4982         struct bnxt *bp = netdev_priv(dev);
4983
4984         if (!bnxt_rfs_capable(bp))
4985                 features &= ~NETIF_F_NTUPLE;
4986         return features;
4987 }
4988
4989 static int bnxt_set_features(struct net_device *dev, netdev_features_t features)
4990 {
4991         struct bnxt *bp = netdev_priv(dev);
4992         u32 flags = bp->flags;
4993         u32 changes;
4994         int rc = 0;
4995         bool re_init = false;
4996         bool update_tpa = false;
4997
4998         flags &= ~BNXT_FLAG_ALL_CONFIG_FEATS;
4999         if ((features & NETIF_F_GRO) && (bp->pdev->revision > 0))
5000                 flags |= BNXT_FLAG_GRO;
5001         if (features & NETIF_F_LRO)
5002                 flags |= BNXT_FLAG_LRO;
5003
5004         if (features & NETIF_F_HW_VLAN_CTAG_RX)
5005                 flags |= BNXT_FLAG_STRIP_VLAN;
5006
5007         if (features & NETIF_F_NTUPLE)
5008                 flags |= BNXT_FLAG_RFS;
5009
5010         changes = flags ^ bp->flags;
5011         if (changes & BNXT_FLAG_TPA) {
5012                 update_tpa = true;
5013                 if ((bp->flags & BNXT_FLAG_TPA) == 0 ||
5014                     (flags & BNXT_FLAG_TPA) == 0)
5015                         re_init = true;
5016         }
5017
5018         if (changes & ~BNXT_FLAG_TPA)
5019                 re_init = true;
5020
5021         if (flags != bp->flags) {
5022                 u32 old_flags = bp->flags;
5023
5024                 bp->flags = flags;
5025
5026                 if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5027                         if (update_tpa)
5028                                 bnxt_set_ring_params(bp);
5029                         return rc;
5030                 }
5031
5032                 if (re_init) {
5033                         bnxt_close_nic(bp, false, false);
5034                         if (update_tpa)
5035                                 bnxt_set_ring_params(bp);
5036
5037                         return bnxt_open_nic(bp, false, false);
5038                 }
5039                 if (update_tpa) {
5040                         rc = bnxt_set_tpa(bp,
5041                                           (flags & BNXT_FLAG_TPA) ?
5042                                           true : false);
5043                         if (rc)
5044                                 bp->flags = old_flags;
5045                 }
5046         }
5047         return rc;
5048 }
5049
5050 static void bnxt_dump_tx_sw_state(struct bnxt_napi *bnapi)
5051 {
5052         struct bnxt_tx_ring_info *txr = bnapi->tx_ring;
5053         int i = bnapi->index;
5054
5055         if (!txr)
5056                 return;
5057
5058         netdev_info(bnapi->bp->dev, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5059                     i, txr->tx_ring_struct.fw_ring_id, txr->tx_prod,
5060                     txr->tx_cons);
5061 }
5062
5063 static void bnxt_dump_rx_sw_state(struct bnxt_napi *bnapi)
5064 {
5065         struct bnxt_rx_ring_info *rxr = bnapi->rx_ring;
5066         int i = bnapi->index;
5067
5068         if (!rxr)
5069                 return;
5070
5071         netdev_info(bnapi->bp->dev, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5072                     i, rxr->rx_ring_struct.fw_ring_id, rxr->rx_prod,
5073                     rxr->rx_agg_ring_struct.fw_ring_id, rxr->rx_agg_prod,
5074                     rxr->rx_sw_agg_prod);
5075 }
5076
5077 static void bnxt_dump_cp_sw_state(struct bnxt_napi *bnapi)
5078 {
5079         struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring;
5080         int i = bnapi->index;
5081
5082         netdev_info(bnapi->bp->dev, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5083                     i, cpr->cp_ring_struct.fw_ring_id, cpr->cp_raw_cons);
5084 }
5085
5086 static void bnxt_dbg_dump_states(struct bnxt *bp)
5087 {
5088         int i;
5089         struct bnxt_napi *bnapi;
5090
5091         for (i = 0; i < bp->cp_nr_rings; i++) {
5092                 bnapi = bp->bnapi[i];
5093                 if (netif_msg_drv(bp)) {
5094                         bnxt_dump_tx_sw_state(bnapi);
5095                         bnxt_dump_rx_sw_state(bnapi);
5096                         bnxt_dump_cp_sw_state(bnapi);
5097                 }
5098         }
5099 }
5100
5101 static void bnxt_reset_task(struct bnxt *bp)
5102 {
5103         bnxt_dbg_dump_states(bp);
5104         if (netif_running(bp->dev)) {
5105                 bnxt_close_nic(bp, false, false);
5106                 bnxt_open_nic(bp, false, false);
5107         }
5108 }
5109
5110 static void bnxt_tx_timeout(struct net_device *dev)
5111 {
5112         struct bnxt *bp = netdev_priv(dev);
5113
5114         netdev_err(bp->dev,  "TX timeout detected, starting reset task!\n");
5115         set_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event);
5116         schedule_work(&bp->sp_task);
5117 }
5118
5119 #ifdef CONFIG_NET_POLL_CONTROLLER
5120 static void bnxt_poll_controller(struct net_device *dev)
5121 {
5122         struct bnxt *bp = netdev_priv(dev);
5123         int i;
5124
5125         for (i = 0; i < bp->cp_nr_rings; i++) {
5126                 struct bnxt_irq *irq = &bp->irq_tbl[i];
5127
5128                 disable_irq(irq->vector);
5129                 irq->handler(irq->vector, bp->bnapi[i]);
5130                 enable_irq(irq->vector);
5131         }
5132 }
5133 #endif
5134
5135 static void bnxt_timer(unsigned long data)
5136 {
5137         struct bnxt *bp = (struct bnxt *)data;
5138         struct net_device *dev = bp->dev;
5139
5140         if (!netif_running(dev))
5141                 return;
5142
5143         if (atomic_read(&bp->intr_sem) != 0)
5144                 goto bnxt_restart_timer;
5145
5146 bnxt_restart_timer:
5147         mod_timer(&bp->timer, jiffies + bp->current_interval);
5148 }
5149
5150 static void bnxt_cfg_ntp_filters(struct bnxt *);
5151
5152 static void bnxt_sp_task(struct work_struct *work)
5153 {
5154         struct bnxt *bp = container_of(work, struct bnxt, sp_task);
5155         int rc;
5156
5157         set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5158         smp_mb__after_atomic();
5159         if (!test_bit(BNXT_STATE_OPEN, &bp->state)) {
5160                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5161                 return;
5162         }
5163
5164         if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
5165                 bnxt_cfg_rx_mode(bp);
5166
5167         if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
5168                 bnxt_cfg_ntp_filters(bp);
5169         if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT, &bp->sp_event)) {
5170                 rc = bnxt_update_link(bp, true);
5171                 if (rc)
5172                         netdev_err(bp->dev, "SP task can't update link (rc: %x)\n",
5173                                    rc);
5174         }
5175         if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
5176                 bnxt_hwrm_exec_fwd_req(bp);
5177         if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event)) {
5178                 bnxt_hwrm_tunnel_dst_port_alloc(
5179                         bp, bp->vxlan_port,
5180                         TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5181         }
5182         if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event)) {
5183                 bnxt_hwrm_tunnel_dst_port_free(
5184                         bp, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN);
5185         }
5186         if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event)) {
5187                 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5188                  * for BNXT_STATE_IN_SP_TASK to clear.
5189                  */
5190                 clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5191                 rtnl_lock();
5192                 bnxt_reset_task(bp);
5193                 set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5194                 rtnl_unlock();
5195         }
5196
5197         smp_mb__before_atomic();
5198         clear_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
5199 }
5200
5201 static int bnxt_init_board(struct pci_dev *pdev, struct net_device *dev)
5202 {
5203         int rc;
5204         struct bnxt *bp = netdev_priv(dev);
5205
5206         SET_NETDEV_DEV(dev, &pdev->dev);
5207
5208         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5209         rc = pci_enable_device(pdev);
5210         if (rc) {
5211                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
5212                 goto init_err;
5213         }
5214
5215         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5216                 dev_err(&pdev->dev,
5217                         "Cannot find PCI device base address, aborting\n");
5218                 rc = -ENODEV;
5219                 goto init_err_disable;
5220         }
5221
5222         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5223         if (rc) {
5224                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
5225                 goto init_err_disable;
5226         }
5227
5228         if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) != 0 &&
5229             dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
5230                 dev_err(&pdev->dev, "System does not support DMA, aborting\n");
5231                 goto init_err_disable;
5232         }
5233
5234         pci_set_master(pdev);
5235
5236         bp->dev = dev;
5237         bp->pdev = pdev;
5238
5239         bp->bar0 = pci_ioremap_bar(pdev, 0);
5240         if (!bp->bar0) {
5241                 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
5242                 rc = -ENOMEM;
5243                 goto init_err_release;
5244         }
5245
5246         bp->bar1 = pci_ioremap_bar(pdev, 2);
5247         if (!bp->bar1) {
5248                 dev_err(&pdev->dev, "Cannot map doorbell registers, aborting\n");
5249                 rc = -ENOMEM;
5250                 goto init_err_release;
5251         }
5252
5253         bp->bar2 = pci_ioremap_bar(pdev, 4);
5254         if (!bp->bar2) {
5255                 dev_err(&pdev->dev, "Cannot map bar4 registers, aborting\n");
5256                 rc = -ENOMEM;
5257                 goto init_err_release;
5258         }
5259
5260         INIT_WORK(&bp->sp_task, bnxt_sp_task);
5261
5262         spin_lock_init(&bp->ntp_fltr_lock);
5263
5264         bp->rx_ring_size = BNXT_DEFAULT_RX_RING_SIZE;
5265         bp->tx_ring_size = BNXT_DEFAULT_TX_RING_SIZE;
5266
5267         bp->coal_ticks = BNXT_USEC_TO_COAL_TIMER(4);
5268         bp->coal_bufs = 20;
5269         bp->coal_ticks_irq = BNXT_USEC_TO_COAL_TIMER(1);
5270         bp->coal_bufs_irq = 2;
5271
5272         init_timer(&bp->timer);
5273         bp->timer.data = (unsigned long)bp;
5274         bp->timer.function = bnxt_timer;
5275         bp->current_interval = BNXT_TIMER_INTERVAL;
5276
5277         clear_bit(BNXT_STATE_OPEN, &bp->state);
5278
5279         return 0;
5280
5281 init_err_release:
5282         if (bp->bar2) {
5283                 pci_iounmap(pdev, bp->bar2);
5284                 bp->bar2 = NULL;
5285         }
5286
5287         if (bp->bar1) {
5288                 pci_iounmap(pdev, bp->bar1);
5289                 bp->bar1 = NULL;
5290         }
5291
5292         if (bp->bar0) {
5293                 pci_iounmap(pdev, bp->bar0);
5294                 bp->bar0 = NULL;
5295         }
5296
5297         pci_release_regions(pdev);
5298
5299 init_err_disable:
5300         pci_disable_device(pdev);
5301
5302 init_err:
5303         return rc;
5304 }
5305
5306 /* rtnl_lock held */
5307 static int bnxt_change_mac_addr(struct net_device *dev, void *p)
5308 {
5309         struct sockaddr *addr = p;
5310         struct bnxt *bp = netdev_priv(dev);
5311         int rc = 0;
5312
5313         if (!is_valid_ether_addr(addr->sa_data))
5314                 return -EADDRNOTAVAIL;
5315
5316 #ifdef CONFIG_BNXT_SRIOV
5317         if (BNXT_VF(bp) && is_valid_ether_addr(bp->vf.mac_addr))
5318                 return -EADDRNOTAVAIL;
5319 #endif
5320
5321         if (ether_addr_equal(addr->sa_data, dev->dev_addr))
5322                 return 0;
5323
5324         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5325         if (netif_running(dev)) {
5326                 bnxt_close_nic(bp, false, false);
5327                 rc = bnxt_open_nic(bp, false, false);
5328         }
5329
5330         return rc;
5331 }
5332
5333 /* rtnl_lock held */
5334 static int bnxt_change_mtu(struct net_device *dev, int new_mtu)
5335 {
5336         struct bnxt *bp = netdev_priv(dev);
5337
5338         if (new_mtu < 60 || new_mtu > 9000)
5339                 return -EINVAL;
5340
5341         if (netif_running(dev))
5342                 bnxt_close_nic(bp, false, false);
5343
5344         dev->mtu = new_mtu;
5345         bnxt_set_ring_params(bp);
5346
5347         if (netif_running(dev))
5348                 return bnxt_open_nic(bp, false, false);
5349
5350         return 0;
5351 }
5352
5353 static int bnxt_setup_tc(struct net_device *dev, u8 tc)
5354 {
5355         struct bnxt *bp = netdev_priv(dev);
5356
5357         if (tc > bp->max_tc) {
5358                 netdev_err(dev, "too many traffic classes requested: %d Max supported is %d\n",
5359                            tc, bp->max_tc);
5360                 return -EINVAL;
5361         }
5362
5363         if (netdev_get_num_tc(dev) == tc)
5364                 return 0;
5365
5366         if (tc) {
5367                 int max_rx_rings, max_tx_rings, rc;
5368
5369                 rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, true);
5370                 if (rc || bp->tx_nr_rings_per_tc * tc > max_tx_rings)
5371                         return -ENOMEM;
5372         }
5373
5374         /* Needs to close the device and do hw resource re-allocations */
5375         if (netif_running(bp->dev))
5376                 bnxt_close_nic(bp, true, false);
5377
5378         if (tc) {
5379                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc * tc;
5380                 netdev_set_num_tc(dev, tc);
5381         } else {
5382                 bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5383                 netdev_reset_tc(dev);
5384         }
5385         bp->cp_nr_rings = max_t(int, bp->tx_nr_rings, bp->rx_nr_rings);
5386         bp->num_stat_ctxs = bp->cp_nr_rings;
5387
5388         if (netif_running(bp->dev))
5389                 return bnxt_open_nic(bp, true, false);
5390
5391         return 0;
5392 }
5393
5394 #ifdef CONFIG_RFS_ACCEL
5395 static bool bnxt_fltr_match(struct bnxt_ntuple_filter *f1,
5396                             struct bnxt_ntuple_filter *f2)
5397 {
5398         struct flow_keys *keys1 = &f1->fkeys;
5399         struct flow_keys *keys2 = &f2->fkeys;
5400
5401         if (keys1->addrs.v4addrs.src == keys2->addrs.v4addrs.src &&
5402             keys1->addrs.v4addrs.dst == keys2->addrs.v4addrs.dst &&
5403             keys1->ports.ports == keys2->ports.ports &&
5404             keys1->basic.ip_proto == keys2->basic.ip_proto &&
5405             keys1->basic.n_proto == keys2->basic.n_proto &&
5406             ether_addr_equal(f1->src_mac_addr, f2->src_mac_addr))
5407                 return true;
5408
5409         return false;
5410 }
5411
5412 static int bnxt_rx_flow_steer(struct net_device *dev, const struct sk_buff *skb,
5413                               u16 rxq_index, u32 flow_id)
5414 {
5415         struct bnxt *bp = netdev_priv(dev);
5416         struct bnxt_ntuple_filter *fltr, *new_fltr;
5417         struct flow_keys *fkeys;
5418         struct ethhdr *eth = (struct ethhdr *)skb_mac_header(skb);
5419         int rc = 0, idx, bit_id;
5420         struct hlist_head *head;
5421
5422         if (skb->encapsulation)
5423                 return -EPROTONOSUPPORT;
5424
5425         new_fltr = kzalloc(sizeof(*new_fltr), GFP_ATOMIC);
5426         if (!new_fltr)
5427                 return -ENOMEM;
5428
5429         fkeys = &new_fltr->fkeys;
5430         if (!skb_flow_dissect_flow_keys(skb, fkeys, 0)) {
5431                 rc = -EPROTONOSUPPORT;
5432                 goto err_free;
5433         }
5434
5435         if ((fkeys->basic.n_proto != htons(ETH_P_IP)) ||
5436             ((fkeys->basic.ip_proto != IPPROTO_TCP) &&
5437              (fkeys->basic.ip_proto != IPPROTO_UDP))) {
5438                 rc = -EPROTONOSUPPORT;
5439                 goto err_free;
5440         }
5441
5442         memcpy(new_fltr->src_mac_addr, eth->h_source, ETH_ALEN);
5443
5444         idx = skb_get_hash_raw(skb) & BNXT_NTP_FLTR_HASH_MASK;
5445         head = &bp->ntp_fltr_hash_tbl[idx];
5446         rcu_read_lock();
5447         hlist_for_each_entry_rcu(fltr, head, hash) {
5448                 if (bnxt_fltr_match(fltr, new_fltr)) {
5449                         rcu_read_unlock();
5450                         rc = 0;
5451                         goto err_free;
5452                 }
5453         }
5454         rcu_read_unlock();
5455
5456         spin_lock_bh(&bp->ntp_fltr_lock);
5457         bit_id = bitmap_find_free_region(bp->ntp_fltr_bmap,
5458                                          BNXT_NTP_FLTR_MAX_FLTR, 0);
5459         if (bit_id < 0) {
5460                 spin_unlock_bh(&bp->ntp_fltr_lock);
5461                 rc = -ENOMEM;
5462                 goto err_free;
5463         }
5464
5465         new_fltr->sw_id = (u16)bit_id;
5466         new_fltr->flow_id = flow_id;
5467         new_fltr->rxq = rxq_index;
5468         hlist_add_head_rcu(&new_fltr->hash, head);
5469         bp->ntp_fltr_count++;
5470         spin_unlock_bh(&bp->ntp_fltr_lock);
5471
5472         set_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event);
5473         schedule_work(&bp->sp_task);
5474
5475         return new_fltr->sw_id;
5476
5477 err_free:
5478         kfree(new_fltr);
5479         return rc;
5480 }
5481
5482 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5483 {
5484         int i;
5485
5486         for (i = 0; i < BNXT_NTP_FLTR_HASH_SIZE; i++) {
5487                 struct hlist_head *head;
5488                 struct hlist_node *tmp;
5489                 struct bnxt_ntuple_filter *fltr;
5490                 int rc;
5491
5492                 head = &bp->ntp_fltr_hash_tbl[i];
5493                 hlist_for_each_entry_safe(fltr, tmp, head, hash) {
5494                         bool del = false;
5495
5496                         if (test_bit(BNXT_FLTR_VALID, &fltr->state)) {
5497                                 if (rps_may_expire_flow(bp->dev, fltr->rxq,
5498                                                         fltr->flow_id,
5499                                                         fltr->sw_id)) {
5500                                         bnxt_hwrm_cfa_ntuple_filter_free(bp,
5501                                                                          fltr);
5502                                         del = true;
5503                                 }
5504                         } else {
5505                                 rc = bnxt_hwrm_cfa_ntuple_filter_alloc(bp,
5506                                                                        fltr);
5507                                 if (rc)
5508                                         del = true;
5509                                 else
5510                                         set_bit(BNXT_FLTR_VALID, &fltr->state);
5511                         }
5512
5513                         if (del) {
5514                                 spin_lock_bh(&bp->ntp_fltr_lock);
5515                                 hlist_del_rcu(&fltr->hash);
5516                                 bp->ntp_fltr_count--;
5517                                 spin_unlock_bh(&bp->ntp_fltr_lock);
5518                                 synchronize_rcu();
5519                                 clear_bit(fltr->sw_id, bp->ntp_fltr_bmap);
5520                                 kfree(fltr);
5521                         }
5522                 }
5523         }
5524 }
5525
5526 #else
5527
5528 static void bnxt_cfg_ntp_filters(struct bnxt *bp)
5529 {
5530 }
5531
5532 #endif /* CONFIG_RFS_ACCEL */
5533
5534 static void bnxt_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5535                                 __be16 port)
5536 {
5537         struct bnxt *bp = netdev_priv(dev);
5538
5539         if (!netif_running(dev))
5540                 return;
5541
5542         if (sa_family != AF_INET6 && sa_family != AF_INET)
5543                 return;
5544
5545         if (bp->vxlan_port_cnt && bp->vxlan_port != port)
5546                 return;
5547
5548         bp->vxlan_port_cnt++;
5549         if (bp->vxlan_port_cnt == 1) {
5550                 bp->vxlan_port = port;
5551                 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT, &bp->sp_event);
5552                 schedule_work(&bp->sp_task);
5553         }
5554 }
5555
5556 static void bnxt_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
5557                                 __be16 port)
5558 {
5559         struct bnxt *bp = netdev_priv(dev);
5560
5561         if (!netif_running(dev))
5562                 return;
5563
5564         if (sa_family != AF_INET6 && sa_family != AF_INET)
5565                 return;
5566
5567         if (bp->vxlan_port_cnt && bp->vxlan_port == port) {
5568                 bp->vxlan_port_cnt--;
5569
5570                 if (bp->vxlan_port_cnt == 0) {
5571                         set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT, &bp->sp_event);
5572                         schedule_work(&bp->sp_task);
5573                 }
5574         }
5575 }
5576
5577 static const struct net_device_ops bnxt_netdev_ops = {
5578         .ndo_open               = bnxt_open,
5579         .ndo_start_xmit         = bnxt_start_xmit,
5580         .ndo_stop               = bnxt_close,
5581         .ndo_get_stats64        = bnxt_get_stats64,
5582         .ndo_set_rx_mode        = bnxt_set_rx_mode,
5583         .ndo_do_ioctl           = bnxt_ioctl,
5584         .ndo_validate_addr      = eth_validate_addr,
5585         .ndo_set_mac_address    = bnxt_change_mac_addr,
5586         .ndo_change_mtu         = bnxt_change_mtu,
5587         .ndo_fix_features       = bnxt_fix_features,
5588         .ndo_set_features       = bnxt_set_features,
5589         .ndo_tx_timeout         = bnxt_tx_timeout,
5590 #ifdef CONFIG_BNXT_SRIOV
5591         .ndo_get_vf_config      = bnxt_get_vf_config,
5592         .ndo_set_vf_mac         = bnxt_set_vf_mac,
5593         .ndo_set_vf_vlan        = bnxt_set_vf_vlan,
5594         .ndo_set_vf_rate        = bnxt_set_vf_bw,
5595         .ndo_set_vf_link_state  = bnxt_set_vf_link_state,
5596         .ndo_set_vf_spoofchk    = bnxt_set_vf_spoofchk,
5597 #endif
5598 #ifdef CONFIG_NET_POLL_CONTROLLER
5599         .ndo_poll_controller    = bnxt_poll_controller,
5600 #endif
5601         .ndo_setup_tc           = bnxt_setup_tc,
5602 #ifdef CONFIG_RFS_ACCEL
5603         .ndo_rx_flow_steer      = bnxt_rx_flow_steer,
5604 #endif
5605         .ndo_add_vxlan_port     = bnxt_add_vxlan_port,
5606         .ndo_del_vxlan_port     = bnxt_del_vxlan_port,
5607 #ifdef CONFIG_NET_RX_BUSY_POLL
5608         .ndo_busy_poll          = bnxt_busy_poll,
5609 #endif
5610 };
5611
5612 static void bnxt_remove_one(struct pci_dev *pdev)
5613 {
5614         struct net_device *dev = pci_get_drvdata(pdev);
5615         struct bnxt *bp = netdev_priv(dev);
5616
5617         if (BNXT_PF(bp))
5618                 bnxt_sriov_disable(bp);
5619
5620         unregister_netdev(dev);
5621         cancel_work_sync(&bp->sp_task);
5622         bp->sp_event = 0;
5623
5624         bnxt_hwrm_func_drv_unrgtr(bp);
5625         bnxt_free_hwrm_resources(bp);
5626         pci_iounmap(pdev, bp->bar2);
5627         pci_iounmap(pdev, bp->bar1);
5628         pci_iounmap(pdev, bp->bar0);
5629         free_netdev(dev);
5630
5631         pci_release_regions(pdev);
5632         pci_disable_device(pdev);
5633 }
5634
5635 static int bnxt_probe_phy(struct bnxt *bp)
5636 {
5637         int rc = 0;
5638         struct bnxt_link_info *link_info = &bp->link_info;
5639         char phy_ver[PHY_VER_STR_LEN];
5640
5641         rc = bnxt_update_link(bp, false);
5642         if (rc) {
5643                 netdev_err(bp->dev, "Probe phy can't update link (rc: %x)\n",
5644                            rc);
5645                 return rc;
5646         }
5647
5648         /*initialize the ethool setting copy with NVM settings */
5649         if (BNXT_AUTO_MODE(link_info->auto_mode))
5650                 link_info->autoneg |= BNXT_AUTONEG_SPEED;
5651
5652         if (link_info->auto_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5653                 if (link_info->auto_pause_setting == BNXT_LINK_PAUSE_BOTH)
5654                         link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;
5655                 link_info->req_flow_ctrl = link_info->auto_pause_setting;
5656         } else if (link_info->force_pause_setting & BNXT_LINK_PAUSE_BOTH) {
5657                 link_info->req_flow_ctrl = link_info->force_pause_setting;
5658         }
5659         link_info->req_duplex = link_info->duplex_setting;
5660         if (link_info->autoneg & BNXT_AUTONEG_SPEED)
5661                 link_info->req_link_speed = link_info->auto_link_speed;
5662         else
5663                 link_info->req_link_speed = link_info->force_link_speed;
5664         link_info->advertising = link_info->auto_link_speeds;
5665         snprintf(phy_ver, PHY_VER_STR_LEN, " ph %d.%d.%d",
5666                  link_info->phy_ver[0],
5667                  link_info->phy_ver[1],
5668                  link_info->phy_ver[2]);
5669         strcat(bp->fw_ver_str, phy_ver);
5670         return rc;
5671 }
5672
5673 static int bnxt_get_max_irq(struct pci_dev *pdev)
5674 {
5675         u16 ctrl;
5676
5677         if (!pdev->msix_cap)
5678                 return 1;
5679
5680         pci_read_config_word(pdev, pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
5681         return (ctrl & PCI_MSIX_FLAGS_QSIZE) + 1;
5682 }
5683
5684 static void _bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx,
5685                                 int *max_cp)
5686 {
5687         int max_ring_grps = 0;
5688
5689         if (BNXT_PF(bp)) {
5690                 *max_tx = bp->pf.max_tx_rings;
5691                 *max_rx = bp->pf.max_rx_rings;
5692                 *max_cp = min_t(int, bp->pf.max_irqs, bp->pf.max_cp_rings);
5693                 *max_cp = min_t(int, *max_cp, bp->pf.max_stat_ctxs);
5694                 max_ring_grps = bp->pf.max_hw_ring_grps;
5695         } else {
5696 #ifdef CONFIG_BNXT_SRIOV
5697                 *max_tx = bp->vf.max_tx_rings;
5698                 *max_rx = bp->vf.max_rx_rings;
5699                 *max_cp = min_t(int, bp->vf.max_irqs, bp->vf.max_cp_rings);
5700                 *max_cp = min_t(int, *max_cp, bp->vf.max_stat_ctxs);
5701                 max_ring_grps = bp->vf.max_hw_ring_grps;
5702 #endif
5703         }
5704         if (bp->flags & BNXT_FLAG_AGG_RINGS)
5705                 *max_rx >>= 1;
5706         *max_rx = min_t(int, *max_rx, max_ring_grps);
5707 }
5708
5709 int bnxt_get_max_rings(struct bnxt *bp, int *max_rx, int *max_tx, bool shared)
5710 {
5711         int rx, tx, cp;
5712
5713         _bnxt_get_max_rings(bp, &rx, &tx, &cp);
5714         if (!rx || !tx || !cp)
5715                 return -ENOMEM;
5716
5717         *max_rx = rx;
5718         *max_tx = tx;
5719         return bnxt_trim_rings(bp, max_rx, max_tx, cp, shared);
5720 }
5721
5722 static int bnxt_set_dflt_rings(struct bnxt *bp)
5723 {
5724         int dflt_rings, max_rx_rings, max_tx_rings, rc;
5725         bool sh = true;
5726
5727         if (sh)
5728                 bp->flags |= BNXT_FLAG_SHARED_RINGS;
5729         dflt_rings = netif_get_num_default_rss_queues();
5730         rc = bnxt_get_max_rings(bp, &max_rx_rings, &max_tx_rings, sh);
5731         if (rc)
5732                 return rc;
5733         bp->rx_nr_rings = min_t(int, dflt_rings, max_rx_rings);
5734         bp->tx_nr_rings_per_tc = min_t(int, dflt_rings, max_tx_rings);
5735         bp->tx_nr_rings = bp->tx_nr_rings_per_tc;
5736         bp->cp_nr_rings = sh ? max_t(int, bp->tx_nr_rings, bp->rx_nr_rings) :
5737                                bp->tx_nr_rings + bp->rx_nr_rings;
5738         bp->num_stat_ctxs = bp->cp_nr_rings;
5739         return rc;
5740 }
5741
5742 static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5743 {
5744         static int version_printed;
5745         struct net_device *dev;
5746         struct bnxt *bp;
5747         int rc, max_irqs;
5748
5749         if (version_printed++ == 0)
5750                 pr_info("%s", version);
5751
5752         max_irqs = bnxt_get_max_irq(pdev);
5753         dev = alloc_etherdev_mq(sizeof(*bp), max_irqs);
5754         if (!dev)
5755                 return -ENOMEM;
5756
5757         bp = netdev_priv(dev);
5758
5759         if (bnxt_vf_pciid(ent->driver_data))
5760                 bp->flags |= BNXT_FLAG_VF;
5761
5762         if (pdev->msix_cap)
5763                 bp->flags |= BNXT_FLAG_MSIX_CAP;
5764
5765         rc = bnxt_init_board(pdev, dev);
5766         if (rc < 0)
5767                 goto init_err_free;
5768
5769         dev->netdev_ops = &bnxt_netdev_ops;
5770         dev->watchdog_timeo = BNXT_TX_TIMEOUT;
5771         dev->ethtool_ops = &bnxt_ethtool_ops;
5772
5773         pci_set_drvdata(pdev, dev);
5774
5775         dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5776                            NETIF_F_TSO | NETIF_F_TSO6 |
5777                            NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5778                            NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT |
5779                            NETIF_F_RXHASH |
5780                            NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO;
5781
5782         dev->hw_enc_features =
5783                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
5784                         NETIF_F_TSO | NETIF_F_TSO6 |
5785                         NETIF_F_GSO_UDP_TUNNEL | NETIF_F_GSO_GRE |
5786                         NETIF_F_GSO_IPIP | NETIF_F_GSO_SIT;
5787         dev->vlan_features = dev->hw_features | NETIF_F_HIGHDMA;
5788         dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX |
5789                             NETIF_F_HW_VLAN_STAG_RX | NETIF_F_HW_VLAN_STAG_TX;
5790         dev->features |= dev->hw_features | NETIF_F_HIGHDMA;
5791         dev->priv_flags |= IFF_UNICAST_FLT;
5792
5793 #ifdef CONFIG_BNXT_SRIOV
5794         init_waitqueue_head(&bp->sriov_cfg_wait);
5795 #endif
5796         rc = bnxt_alloc_hwrm_resources(bp);
5797         if (rc)
5798                 goto init_err;
5799
5800         mutex_init(&bp->hwrm_cmd_lock);
5801         bnxt_hwrm_ver_get(bp);
5802
5803         rc = bnxt_hwrm_func_drv_rgtr(bp);
5804         if (rc)
5805                 goto init_err;
5806
5807         /* Get the MAX capabilities for this function */
5808         rc = bnxt_hwrm_func_qcaps(bp);
5809         if (rc) {
5810                 netdev_err(bp->dev, "hwrm query capability failure rc: %x\n",
5811                            rc);
5812                 rc = -1;
5813                 goto init_err;
5814         }
5815
5816         rc = bnxt_hwrm_queue_qportcfg(bp);
5817         if (rc) {
5818                 netdev_err(bp->dev, "hwrm query qportcfg failure rc: %x\n",
5819                            rc);
5820                 rc = -1;
5821                 goto init_err;
5822         }
5823
5824         bnxt_set_tpa_flags(bp);
5825         bnxt_set_ring_params(bp);
5826         if (BNXT_PF(bp))
5827                 bp->pf.max_irqs = max_irqs;
5828 #if defined(CONFIG_BNXT_SRIOV)
5829         else
5830                 bp->vf.max_irqs = max_irqs;
5831 #endif
5832         bnxt_set_dflt_rings(bp);
5833
5834         if (BNXT_PF(bp)) {
5835                 dev->hw_features |= NETIF_F_NTUPLE;
5836                 if (bnxt_rfs_capable(bp)) {
5837                         bp->flags |= BNXT_FLAG_RFS;
5838                         dev->features |= NETIF_F_NTUPLE;
5839                 }
5840         }
5841
5842         if (dev->hw_features & NETIF_F_HW_VLAN_CTAG_RX)
5843                 bp->flags |= BNXT_FLAG_STRIP_VLAN;
5844
5845         rc = bnxt_probe_phy(bp);
5846         if (rc)
5847                 goto init_err;
5848
5849         rc = register_netdev(dev);
5850         if (rc)
5851                 goto init_err;
5852
5853         netdev_info(dev, "%s found at mem %lx, node addr %pM\n",
5854                     board_info[ent->driver_data].name,
5855                     (long)pci_resource_start(pdev, 0), dev->dev_addr);
5856
5857         return 0;
5858
5859 init_err:
5860         pci_iounmap(pdev, bp->bar0);
5861         pci_release_regions(pdev);
5862         pci_disable_device(pdev);
5863
5864 init_err_free:
5865         free_netdev(dev);
5866         return rc;
5867 }
5868
5869 static struct pci_driver bnxt_pci_driver = {
5870         .name           = DRV_MODULE_NAME,
5871         .id_table       = bnxt_pci_tbl,
5872         .probe          = bnxt_init_one,
5873         .remove         = bnxt_remove_one,
5874 #if defined(CONFIG_BNXT_SRIOV)
5875         .sriov_configure = bnxt_sriov_configure,
5876 #endif
5877 };
5878
5879 module_pci_driver(bnxt_pci_driver);