1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2016 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
13 #define DRV_MODULE_NAME "bnxt_en"
14 #define DRV_MODULE_VERSION "1.3.0"
21 __le32 tx_bd_len_flags_type;
22 #define TX_BD_TYPE (0x3f << 0)
23 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
24 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
25 #define TX_BD_FLAGS_PACKET_END (1 << 6)
26 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
27 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
28 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
29 #define TX_BD_FLAGS_LHINT (3 << 13)
30 #define TX_BD_FLAGS_LHINT_SHIFT 13
31 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
32 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
33 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
34 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
35 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
36 #define TX_BD_LEN (0xffff << 16)
37 #define TX_BD_LEN_SHIFT 16
44 __le32 tx_bd_hsize_lflags;
45 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
46 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
47 #define TX_BD_FLAGS_NO_CRC (1 << 2)
48 #define TX_BD_FLAGS_STAMP (1 << 3)
49 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
50 #define TX_BD_FLAGS_LSO (1 << 5)
51 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
52 #define TX_BD_FLAGS_T_IPID (1 << 7)
53 #define TX_BD_HSIZE (0xff << 16)
54 #define TX_BD_HSIZE_SHIFT 16
57 __le32 tx_bd_cfa_action;
58 #define TX_BD_CFA_ACTION (0xffff << 16)
59 #define TX_BD_CFA_ACTION_SHIFT 16
61 __le32 tx_bd_cfa_meta;
62 #define TX_BD_CFA_META_MASK 0xfffffff
63 #define TX_BD_CFA_META_VID_MASK 0xfff
64 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
65 #define TX_BD_CFA_META_PRI_SHIFT 12
66 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
67 #define TX_BD_CFA_META_TPID_SHIFT 16
68 #define TX_BD_CFA_META_KEY (0xf << 28)
69 #define TX_BD_CFA_META_KEY_SHIFT 28
70 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
74 __le32 rx_bd_len_flags_type;
75 #define RX_BD_TYPE (0x3f << 0)
76 #define RX_BD_TYPE_RX_PACKET_BD 0x4
77 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
78 #define RX_BD_TYPE_RX_AGG_BD 0x6
79 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
80 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
81 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
82 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
83 #define RX_BD_FLAGS_SOP (1 << 6)
84 #define RX_BD_FLAGS_EOP (1 << 7)
85 #define RX_BD_FLAGS_BUFFERS (3 << 8)
86 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
87 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
88 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
89 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
90 #define RX_BD_LEN (0xffff << 16)
91 #define RX_BD_LEN_SHIFT 16
98 __le32 tx_cmp_flags_type;
99 #define CMP_TYPE (0x3f << 0)
100 #define CMP_TYPE_TX_L2_CMP 0
101 #define CMP_TYPE_RX_L2_CMP 17
102 #define CMP_TYPE_RX_AGG_CMP 18
103 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
104 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
105 #define CMP_TYPE_STATUS_CMP 32
106 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
107 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
108 #define CMP_TYPE_ERROR_STATUS 48
109 #define CMPL_BASE_TYPE_STAT_EJECT (0x1aUL << 0)
110 #define CMPL_BASE_TYPE_HWRM_DONE (0x20UL << 0)
111 #define CMPL_BASE_TYPE_HWRM_FWD_REQ (0x22UL << 0)
112 #define CMPL_BASE_TYPE_HWRM_FWD_RESP (0x24UL << 0)
113 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT (0x2eUL << 0)
115 #define TX_CMP_FLAGS_ERROR (1 << 6)
116 #define TX_CMP_FLAGS_PUSH (1 << 7)
119 __le32 tx_cmp_errors_v;
120 #define TX_CMP_V (1 << 0)
121 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
122 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
123 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
124 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
125 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
126 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
127 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
128 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
129 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
131 __le32 tx_cmp_unsed_3;
135 __le32 rx_cmp_len_flags_type;
136 #define RX_CMP_CMP_TYPE (0x3f << 0)
137 #define RX_CMP_FLAGS_ERROR (1 << 6)
138 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
139 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
140 #define RX_CMP_FLAGS_UNUSED (1 << 11)
141 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
142 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
143 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
144 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
145 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
146 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
147 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
148 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
149 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
150 #define RX_CMP_LEN (0xffff << 16)
151 #define RX_CMP_LEN_SHIFT 16
154 __le32 rx_cmp_misc_v1;
155 #define RX_CMP_V1 (1 << 0)
156 #define RX_CMP_AGG_BUFS (0x1f << 1)
157 #define RX_CMP_AGG_BUFS_SHIFT 1
158 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
159 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
160 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
161 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
163 __le32 rx_cmp_rss_hash;
166 #define RX_CMP_HASH_VALID(rxcmp) \
167 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
169 #define RSS_PROFILE_ID_MASK 0x1f
171 #define RX_CMP_HASH_TYPE(rxcmp) \
172 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
173 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
176 __le32 rx_cmp_flags2;
177 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
178 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
179 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
180 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
181 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
182 __le32 rx_cmp_meta_data;
183 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
184 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
185 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
186 __le32 rx_cmp_cfa_code_errors_v2;
187 #define RX_CMP_V (1 << 0)
188 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
189 #define RX_CMPL_ERRORS_SFT 1
190 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
191 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
192 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
193 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
194 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
195 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
196 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
197 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
198 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
199 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
200 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
201 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
202 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
203 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
204 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
205 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
206 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
207 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
208 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
209 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
210 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
211 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
212 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
213 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
214 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
215 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
216 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
217 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
219 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
220 #define RX_CMPL_CFA_CODE_SFT 16
222 __le32 rx_cmp_unused3;
225 #define RX_CMP_L2_ERRORS \
226 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
228 #define RX_CMP_L4_CS_BITS \
229 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
231 #define RX_CMP_L4_CS_ERR_BITS \
232 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
234 #define RX_CMP_L4_CS_OK(rxcmp1) \
235 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
236 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
238 #define RX_CMP_ENCAP(rxcmp1) \
239 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
240 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
243 __le32 rx_agg_cmp_len_flags_type;
244 #define RX_AGG_CMP_TYPE (0x3f << 0)
245 #define RX_AGG_CMP_LEN (0xffff << 16)
246 #define RX_AGG_CMP_LEN_SHIFT 16
247 u32 rx_agg_cmp_opaque;
249 #define RX_AGG_CMP_V (1 << 0)
250 __le32 rx_agg_cmp_unused;
253 struct rx_tpa_start_cmp {
254 __le32 rx_tpa_start_cmp_len_flags_type;
255 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
256 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
257 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
258 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
259 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
260 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
261 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
262 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
263 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
264 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
265 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
266 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
267 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
268 #define RX_TPA_START_CMP_LEN (0xffff << 16)
269 #define RX_TPA_START_CMP_LEN_SHIFT 16
271 u32 rx_tpa_start_cmp_opaque;
272 __le32 rx_tpa_start_cmp_misc_v1;
273 #define RX_TPA_START_CMP_V1 (0x1 << 0)
274 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
275 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
276 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
277 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
279 __le32 rx_tpa_start_cmp_rss_hash;
282 #define TPA_START_HASH_VALID(rx_tpa_start) \
283 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
284 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
286 #define TPA_START_HASH_TYPE(rx_tpa_start) \
287 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
288 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
289 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
291 #define TPA_START_AGG_ID(rx_tpa_start) \
292 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
293 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
295 struct rx_tpa_start_cmp_ext {
296 __le32 rx_tpa_start_cmp_flags2;
297 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
298 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
299 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
300 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
301 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
303 __le32 rx_tpa_start_cmp_metadata;
304 __le32 rx_tpa_start_cmp_cfa_code_v2;
305 #define RX_TPA_START_CMP_V2 (0x1 << 0)
306 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
307 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
308 __le32 rx_tpa_start_cmp_hdr_info;
311 struct rx_tpa_end_cmp {
312 __le32 rx_tpa_end_cmp_len_flags_type;
313 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
314 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
315 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
316 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
317 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
318 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
319 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
320 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
321 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
322 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
323 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
324 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
325 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
326 #define RX_TPA_END_CMP_LEN (0xffff << 16)
327 #define RX_TPA_END_CMP_LEN_SHIFT 16
329 u32 rx_tpa_end_cmp_opaque;
330 __le32 rx_tpa_end_cmp_misc_v1;
331 #define RX_TPA_END_CMP_V1 (0x1 << 0)
332 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
333 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
334 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
335 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
336 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
337 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
338 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
339 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
341 __le32 rx_tpa_end_cmp_tsdelta;
342 #define RX_TPA_END_GRO_TS (0x1 << 31)
345 #define TPA_END_AGG_ID(rx_tpa_end) \
346 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
347 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
349 #define TPA_END_TPA_SEGS(rx_tpa_end) \
350 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
351 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
353 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
354 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
355 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
357 #define TPA_END_GRO(rx_tpa_end) \
358 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
359 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
361 #define TPA_END_GRO_TS(rx_tpa_end) \
362 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
363 cpu_to_le32(RX_TPA_END_GRO_TS)))
365 struct rx_tpa_end_cmp_ext {
366 __le32 rx_tpa_end_cmp_dup_acks;
367 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
369 __le32 rx_tpa_end_cmp_seg_len;
370 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
372 __le32 rx_tpa_end_cmp_errors_v2;
373 #define RX_TPA_END_CMP_V2 (0x1 << 0)
374 #define RX_TPA_END_CMP_ERRORS (0x7fff << 1)
375 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
377 u32 rx_tpa_end_cmp_start_opaque;
380 #define DB_IDX_MASK 0xffffff
381 #define DB_IDX_VALID (0x1 << 26)
382 #define DB_IRQ_DIS (0x1 << 27)
383 #define DB_KEY_TX (0x0 << 28)
384 #define DB_KEY_RX (0x1 << 28)
385 #define DB_KEY_CP (0x2 << 28)
386 #define DB_KEY_ST (0x3 << 28)
387 #define DB_KEY_TX_PUSH (0x4 << 28)
388 #define DB_LONG_TX_PUSH (0x2 << 24)
390 #define INVALID_HW_RING_ID ((u16)-1)
392 #define BNXT_RSS_HASH_TYPE_FLAG_IPV4 0x01
393 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4 0x02
394 #define BNXT_RSS_HASH_TYPE_FLAG_IPV6 0x04
395 #define BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6 0x08
397 /* The hardware supports certain page sizes. Use the supported page sizes
398 * to allocate the rings.
400 #if (PAGE_SHIFT < 12)
401 #define BNXT_PAGE_SHIFT 12
402 #elif (PAGE_SHIFT <= 13)
403 #define BNXT_PAGE_SHIFT PAGE_SHIFT
404 #elif (PAGE_SHIFT < 16)
405 #define BNXT_PAGE_SHIFT 13
407 #define BNXT_PAGE_SHIFT 16
410 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
412 /* The RXBD length is 16-bit so we can only support page sizes < 64K */
413 #if (PAGE_SHIFT > 15)
414 #define BNXT_RX_PAGE_SHIFT 15
416 #define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
419 #define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
421 #define BNXT_MIN_PKT_SIZE 45
423 #define BNXT_NUM_TESTS(bp) 0
425 #define BNXT_DEFAULT_RX_RING_SIZE 511
426 #define BNXT_DEFAULT_TX_RING_SIZE 511
430 #if (BNXT_PAGE_SHIFT == 16)
431 #define MAX_RX_PAGES 1
432 #define MAX_RX_AGG_PAGES 4
433 #define MAX_TX_PAGES 1
434 #define MAX_CP_PAGES 8
436 #define MAX_RX_PAGES 8
437 #define MAX_RX_AGG_PAGES 32
438 #define MAX_TX_PAGES 8
439 #define MAX_CP_PAGES 64
442 #define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
443 #define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
444 #define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
446 #define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
447 #define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
449 #define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
451 #define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
452 #define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
454 #define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
456 #define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
457 #define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
458 #define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
460 #define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
461 #define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
463 #define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
464 #define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
466 #define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
467 #define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
469 #define TX_CMP_VALID(txcmp, raw_cons) \
470 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
471 !((raw_cons) & bp->cp_bit))
473 #define RX_CMP_VALID(rxcmp1, raw_cons) \
474 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
475 !((raw_cons) & bp->cp_bit))
477 #define RX_AGG_CMP_VALID(agg, raw_cons) \
478 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
479 !((raw_cons) & bp->cp_bit))
481 #define TX_CMP_TYPE(txcmp) \
482 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
484 #define RX_CMP_TYPE(rxcmp) \
485 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
487 #define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
489 #define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
491 #define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
493 #define ADV_RAW_CMP(idx, n) ((idx) + (n))
494 #define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
495 #define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
496 #define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
498 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
499 #define DFLT_HWRM_CMD_TIMEOUT 500
500 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
501 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
502 #define HWRM_RESP_ERR_CODE_MASK 0xffff
503 #define HWRM_RESP_LEN_OFFSET 4
504 #define HWRM_RESP_LEN_MASK 0xffff0000
505 #define HWRM_RESP_LEN_SFT 16
506 #define HWRM_RESP_VALID_MASK 0xff000000
507 #define HWRM_SEQ_ID_INVALID -1
508 #define BNXT_HWRM_REQ_MAX_SIZE 128
509 #define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
510 BNXT_HWRM_REQ_MAX_SIZE)
512 struct bnxt_sw_tx_bd {
514 DEFINE_DMA_UNMAP_ADDR(mapping);
517 unsigned short nr_frags;
520 struct bnxt_sw_rx_bd {
522 DEFINE_DMA_UNMAP_ADDR(mapping);
525 struct bnxt_sw_rx_agg_bd {
531 struct bnxt_ring_struct {
538 dma_addr_t pg_tbl_map;
543 u16 fw_ring_id; /* Ring id filled by Chimp FW */
549 __le32 tx_bd_len_flags_type;
551 struct tx_bd_ext txbd2;
554 struct tx_push_buffer {
555 struct tx_push_bd push_bd;
559 struct bnxt_tx_ring_info {
560 struct bnxt_napi *bnapi;
563 void __iomem *tx_doorbell;
565 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
566 struct bnxt_sw_tx_bd *tx_buf_ring;
568 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
570 struct tx_push_buffer *tx_push;
571 dma_addr_t tx_push_mapping;
574 #define BNXT_DEV_STATE_CLOSING 0x1
577 struct bnxt_ring_struct tx_ring_struct;
580 struct bnxt_tpa_info {
584 unsigned short gso_type;
587 enum pkt_hash_types hash_type;
591 #define BNXT_TPA_L4_SIZE(hdr_info) \
592 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
594 #define BNXT_TPA_INNER_L3_OFF(hdr_info) \
595 (((hdr_info) >> 18) & 0x1ff)
597 #define BNXT_TPA_INNER_L2_OFF(hdr_info) \
598 (((hdr_info) >> 9) & 0x1ff)
600 #define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
604 struct bnxt_rx_ring_info {
605 struct bnxt_napi *bnapi;
610 void __iomem *rx_doorbell;
611 void __iomem *rx_agg_doorbell;
613 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
614 struct bnxt_sw_rx_bd *rx_buf_ring;
616 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
617 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
619 unsigned long *rx_agg_bmap;
620 u16 rx_agg_bmap_size;
622 struct page *rx_page;
623 unsigned int rx_page_offset;
625 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
626 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
628 struct bnxt_tpa_info *rx_tpa;
630 struct bnxt_ring_struct rx_ring_struct;
631 struct bnxt_ring_struct rx_agg_ring_struct;
634 struct bnxt_cp_ring_info {
636 void __iomem *cp_doorbell;
638 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
640 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
642 struct ctx_hw_stats *hw_stats;
643 dma_addr_t hw_stats_map;
645 u64 rx_l4_csum_errors;
647 struct bnxt_ring_struct cp_ring_struct;
651 struct napi_struct napi;
655 struct bnxt_cp_ring_info cp_ring;
656 struct bnxt_rx_ring_info *rx_ring;
657 struct bnxt_tx_ring_info *tx_ring;
659 #ifdef CONFIG_NET_RX_BUSY_POLL
665 #ifdef CONFIG_NET_RX_BUSY_POLL
666 enum bnxt_poll_state_t {
675 irq_handler_t handler;
678 char name[IFNAMSIZ + 2];
681 #define HWRM_RING_ALLOC_TX 0x1
682 #define HWRM_RING_ALLOC_RX 0x2
683 #define HWRM_RING_ALLOC_AGG 0x4
684 #define HWRM_RING_ALLOC_CMPL 0x8
686 #define INVALID_STATS_CTX_ID -1
688 struct bnxt_ring_grp_info {
696 struct bnxt_vnic_info {
697 u16 fw_vnic_id; /* returned by Chimp during alloc */
698 #define BNXT_MAX_CTX_PER_VNIC 2
699 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
701 #define BNXT_MAX_UC_ADDRS 4
702 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
703 /* index 0 always dev_addr */
709 dma_addr_t rss_table_dma_addr;
711 dma_addr_t rss_hash_key_dma_addr;
718 dma_addr_t mc_list_mapping;
719 #define BNXT_MAX_MC_ADDRS 16
722 #define BNXT_VNIC_RSS_FLAG 1
723 #define BNXT_VNIC_RFS_FLAG 2
724 #define BNXT_VNIC_MCAST_FLAG 4
725 #define BNXT_VNIC_UCAST_FLAG 8
728 #if defined(CONFIG_BNXT_SRIOV)
729 struct bnxt_vf_info {
731 u8 mac_addr[ETH_ALEN];
736 u16 max_hw_ring_grps;
743 #define BNXT_VF_QOS 0x1
744 #define BNXT_VF_SPOOFCHK 0x2
745 #define BNXT_VF_LINK_FORCED 0x4
746 #define BNXT_VF_LINK_UP 0x8
747 u32 func_flags; /* func cfg flags */
750 void *hwrm_cmd_req_addr;
751 dma_addr_t hwrm_cmd_req_dma_addr;
755 struct bnxt_pf_info {
756 #define BNXT_FIRST_PF_FID 1
757 #define BNXT_FIRST_VF_FID 128
760 u8 mac_addr[ETH_ALEN];
763 u16 max_tx_rings; /* HW assigned max tx rings for this PF */
764 u16 max_rx_rings; /* HW assigned max rx rings for this PF */
765 u16 max_hw_ring_grps;
773 u32 max_encap_records;
774 u32 max_decap_records;
779 unsigned long *vf_event_bmap;
780 u16 hwrm_cmd_req_pages;
781 void *hwrm_cmd_req_addr[4];
782 dma_addr_t hwrm_cmd_req_dma_addr[4];
783 struct bnxt_vf_info *vf;
786 struct bnxt_ntuple_filter {
787 struct hlist_node hash;
788 u8 dst_mac_addr[ETH_ALEN];
789 u8 src_mac_addr[ETH_ALEN];
790 struct flow_keys fkeys;
797 #define BNXT_FLTR_VALID 0
798 #define BNXT_FLTR_UPDATE 1
801 struct bnxt_link_info {
807 #define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
808 #define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
809 #define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
814 #define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_HALF
815 #define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_FULL
817 #define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
818 #define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
819 #define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
820 PORT_PHY_QCFG_RESP_PAUSE_TX)
822 u8 auto_pause_setting;
823 u8 force_pause_setting;
826 #define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
827 (mode) <= BNXT_LINK_AUTO_MSK)
828 #define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
829 #define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
830 #define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
831 #define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
832 #define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
833 #define PHY_VER_LEN 3
834 u8 phy_ver[PHY_VER_LEN];
836 #define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
837 #define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
838 #define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
839 #define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
840 #define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
841 #define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
842 #define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
843 #define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
844 #define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
846 u16 auto_link_speeds;
847 #define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
848 #define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
849 #define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
850 #define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
851 #define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
852 #define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
853 #define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
854 #define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
855 #define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
856 u16 support_auto_speeds;
857 u16 lp_auto_link_speeds;
858 u16 force_link_speed;
862 /* copy of requested setting from ethtool cmd */
864 #define BNXT_AUTONEG_SPEED 1
865 #define BNXT_AUTONEG_FLOW_CTRL 2
870 bool force_link_chng;
872 /* a copy of phy_qcfg output used to report link
875 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
878 #define BNXT_MAX_QUEUE 8
880 struct bnxt_queue_info {
885 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
886 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
887 #define BNXT_CAG_REG_BASE 0x300000
896 #define CHIP_NUM_57301 0x16c8
897 #define CHIP_NUM_57302 0x16c9
898 #define CHIP_NUM_57304 0x16ca
899 #define CHIP_NUM_58700 0x16cd
900 #define CHIP_NUM_57402 0x16d0
901 #define CHIP_NUM_57404 0x16d1
902 #define CHIP_NUM_57406 0x16d2
904 #define CHIP_NUM_57311 0x16ce
905 #define CHIP_NUM_57312 0x16cf
906 #define CHIP_NUM_57314 0x16df
907 #define CHIP_NUM_57412 0x16d6
908 #define CHIP_NUM_57414 0x16d7
909 #define CHIP_NUM_57416 0x16d8
910 #define CHIP_NUM_57417 0x16d9
912 #define BNXT_CHIP_NUM_5730X(chip_num) \
913 ((chip_num) >= CHIP_NUM_57301 && \
914 (chip_num) <= CHIP_NUM_57304)
916 #define BNXT_CHIP_NUM_5740X(chip_num) \
917 ((chip_num) >= CHIP_NUM_57402 && \
918 (chip_num) <= CHIP_NUM_57406)
920 #define BNXT_CHIP_NUM_5731X(chip_num) \
921 ((chip_num) == CHIP_NUM_57311 || \
922 (chip_num) == CHIP_NUM_57312 || \
923 (chip_num) == CHIP_NUM_57314)
925 #define BNXT_CHIP_NUM_5741X(chip_num) \
926 ((chip_num) >= CHIP_NUM_57412 && \
927 (chip_num) <= CHIP_NUM_57417)
929 #define BNXT_CHIP_NUM_57X0X(chip_num) \
930 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
932 #define BNXT_CHIP_NUM_57X1X(chip_num) \
933 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
935 struct net_device *dev;
936 struct pci_dev *pdev;
941 #define BNXT_FLAG_DCB_ENABLED 0x1
942 #define BNXT_FLAG_VF 0x2
943 #define BNXT_FLAG_LRO 0x4
945 #define BNXT_FLAG_GRO 0x8
947 /* Cannot support hardware GRO if CONFIG_INET is not set */
948 #define BNXT_FLAG_GRO 0x0
950 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
951 #define BNXT_FLAG_JUMBO 0x10
952 #define BNXT_FLAG_STRIP_VLAN 0x20
953 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
955 #define BNXT_FLAG_USING_MSIX 0x40
956 #define BNXT_FLAG_MSIX_CAP 0x80
957 #define BNXT_FLAG_RFS 0x100
958 #define BNXT_FLAG_SHARED_RINGS 0x200
959 #define BNXT_FLAG_PORT_STATS 0x400
960 #define BNXT_FLAG_EEE_CAP 0x1000
961 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
963 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
965 BNXT_FLAG_STRIP_VLAN)
967 #define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
968 #define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
969 #define BNXT_NPAR(bp) ((bp)->port_partition_type)
970 #define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp))
971 #define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
973 struct bnxt_napi **bnapi;
975 struct bnxt_rx_ring_info *rx_ring;
976 struct bnxt_tx_ring_info *tx_ring;
978 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
982 u32 rx_buf_use_size; /* useable size */
984 u32 rx_agg_ring_size;
987 u32 rx_agg_ring_mask;
997 int tx_nr_rings_per_tc;
1011 /* grp_info indexed by completion ring index */
1012 struct bnxt_ring_grp_info *grp_info;
1013 struct bnxt_vnic_info *vnic_info;
1017 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1019 unsigned int current_interval;
1020 #define BNXT_TIMER_INTERVAL HZ
1022 struct timer_list timer;
1024 unsigned long state;
1025 #define BNXT_STATE_OPEN 0
1026 #define BNXT_STATE_IN_SP_TASK 1
1027 #define BNXT_STATE_FN_RST_DONE 2
1029 struct bnxt_irq *irq_tbl;
1030 u8 mac_addr[ETH_ALEN];
1036 u32 hwrm_intr_seq_id;
1037 void *hwrm_cmd_resp_addr;
1038 dma_addr_t hwrm_cmd_resp_dma_addr;
1039 void *hwrm_dbg_resp_addr;
1040 dma_addr_t hwrm_dbg_resp_dma_addr;
1041 #define HWRM_DBG_REG_BUF_SIZE 128
1043 struct rx_port_stats *hw_rx_port_stats;
1044 struct tx_port_stats *hw_tx_port_stats;
1045 dma_addr_t hw_rx_port_stats_map;
1046 dma_addr_t hw_tx_port_stats_map;
1047 int hw_port_stats_size;
1049 u16 hwrm_max_req_len;
1050 int hwrm_cmd_timeout;
1051 struct mutex hwrm_cmd_lock; /* serialize hwrm messages */
1052 struct hwrm_ver_get_output ver_resp;
1053 #define FW_VER_STR_LEN 32
1054 #define BC_HWRM_STR_LEN 21
1055 #define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1056 char fw_ver_str[FW_VER_STR_LEN];
1059 __le16 vxlan_fw_dst_port_id;
1062 __le16 nge_fw_dst_port_id;
1063 u8 port_partition_type;
1066 u16 rx_coal_ticks_irq;
1068 u16 rx_coal_bufs_irq;
1070 u16 tx_coal_ticks_irq;
1072 u16 tx_coal_bufs_irq;
1074 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
1076 u32 stats_coal_ticks;
1077 #define BNXT_DEF_STATS_COAL_TICKS 1000000
1078 #define BNXT_MIN_STATS_COAL_TICKS 250000
1079 #define BNXT_MAX_STATS_COAL_TICKS 1000000
1081 struct work_struct sp_task;
1082 unsigned long sp_event;
1083 #define BNXT_RX_MASK_SP_EVENT 0
1084 #define BNXT_RX_NTP_FLTR_SP_EVENT 1
1085 #define BNXT_LINK_CHNG_SP_EVENT 2
1086 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1087 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1088 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1089 #define BNXT_RESET_TASK_SP_EVENT 6
1090 #define BNXT_RST_RING_SP_EVENT 7
1091 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1092 #define BNXT_PERIODIC_STATS_SP_EVENT 9
1093 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1094 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1095 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1096 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1098 struct bnxt_pf_info pf;
1099 #ifdef CONFIG_BNXT_SRIOV
1101 struct bnxt_vf_info vf;
1102 wait_queue_head_t sriov_cfg_wait;
1104 #define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1107 #define BNXT_NTP_FLTR_MAX_FLTR 4096
1108 #define BNXT_NTP_FLTR_HASH_SIZE 512
1109 #define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1110 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1111 spinlock_t ntp_fltr_lock; /* for hash table add, del */
1113 unsigned long *ntp_fltr_bmap;
1116 struct bnxt_link_info link_info;
1117 struct ethtool_eee eee;
1122 #ifdef CONFIG_NET_RX_BUSY_POLL
1123 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1125 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1128 /* called from the NAPI poll routine to get ownership of a bnapi */
1129 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1131 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1134 return rc == BNXT_STATE_IDLE;
1137 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1139 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1142 /* called from the busy poll routine to get ownership of a bnapi */
1143 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1145 int rc = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1148 return rc == BNXT_STATE_IDLE;
1151 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1153 atomic_set(&bnapi->poll_state, BNXT_STATE_IDLE);
1156 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1158 return atomic_read(&bnapi->poll_state) == BNXT_STATE_POLL;
1161 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1166 old = atomic_cmpxchg(&bnapi->poll_state, BNXT_STATE_IDLE,
1167 BNXT_STATE_DISABLE);
1168 if (old == BNXT_STATE_IDLE)
1170 usleep_range(500, 5000);
1176 static inline void bnxt_enable_poll(struct bnxt_napi *bnapi)
1180 static inline bool bnxt_lock_napi(struct bnxt_napi *bnapi)
1185 static inline void bnxt_unlock_napi(struct bnxt_napi *bnapi)
1189 static inline bool bnxt_lock_poll(struct bnxt_napi *bnapi)
1194 static inline void bnxt_unlock_poll(struct bnxt_napi *bnapi)
1198 static inline bool bnxt_busy_polling(struct bnxt_napi *bnapi)
1203 static inline void bnxt_disable_poll(struct bnxt_napi *bnapi)
1209 #define I2C_DEV_ADDR_A0 0xa0
1210 #define I2C_DEV_ADDR_A2 0xa2
1211 #define SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
1212 #define SFP_EEPROM_SFF_8472_COMP_SIZE 1
1213 #define SFF_MODULE_ID_SFP 0x3
1214 #define SFF_MODULE_ID_QSFP 0xc
1215 #define SFF_MODULE_ID_QSFP_PLUS 0xd
1216 #define SFF_MODULE_ID_QSFP28 0x11
1217 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1219 void bnxt_set_ring_params(struct bnxt *);
1220 void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1221 int _hwrm_send_message(struct bnxt *, void *, u32, int);
1222 int hwrm_send_message(struct bnxt *, void *, u32, int);
1223 int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1224 int bnxt_hwrm_set_coal(struct bnxt *);
1225 int bnxt_hwrm_func_qcaps(struct bnxt *);
1226 int bnxt_hwrm_set_pause(struct bnxt *);
1227 int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1228 int bnxt_open_nic(struct bnxt *, bool, bool);
1229 int bnxt_close_nic(struct bnxt *, bool, bool);
1230 int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);