2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 5000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 usleep_range(10, 40);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6237 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 ns = timespec_to_ns(ts);
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6248 tg3_full_unlock(tp);
6253 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6302 tg3_full_unlock(tp);
6312 static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6328 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6336 /* tp->lock must be held */
6337 static void tg3_ptp_init(struct tg3 *tp)
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6345 tp->ptp_info = tg3_ptp_caps;
6348 /* tp->lock must be held */
6349 static void tg3_ptp_resume(struct tg3 *tp)
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6358 static void tg3_ptp_fini(struct tg3 *tp)
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6363 ptp_clock_unregister(tp->ptp_clock);
6364 tp->ptp_clock = NULL;
6368 static inline int tg3_irq_sync(struct tg3 *tp)
6370 return tp->irq_sync;
6373 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6382 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6404 if (tg3_flag(tp, SUPPORT_MSIX))
6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6416 if (!tg3_flag(tp, 5705_PLUS)) {
6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6428 if (tg3_flag(tp, NVRAM))
6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6432 static void tg3_dump_state(struct tg3 *tp)
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6441 if (tg3_flag(tp, PCI_EXPRESS)) {
6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6446 tg3_dump_legacy_regs(tp, regs);
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6463 /* SW status block */
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6488 /* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6494 static void tg3_tx_recover(struct tg3 *tp)
6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6508 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6510 /* Tell compiler to fetch tx indices from memory. */
6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6516 /* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6520 static void tg3_tx(struct tg3_napi *tnapi)
6522 struct tg3 *tp = tnapi->tp;
6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6524 u32 sw_idx = tnapi->tx_cons;
6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
6527 unsigned int pkts_compl = 0, bytes_compl = 0;
6529 if (tg3_flag(tp, ENABLE_TSS))
6532 txq = netdev_get_tx_queue(tp->dev, index);
6534 while (sw_idx != hw_idx) {
6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6536 struct sk_buff *skb = ri->skb;
6539 if (unlikely(skb == NULL)) {
6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6549 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6551 skb_tstamp_tx(skb, ×tamp);
6554 pci_unmap_single(tp->pdev,
6555 dma_unmap_addr(ri, mapping),
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6567 sw_idx = NEXT_TX(sw_idx);
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6570 ri = &tnapi->tx_buffers[sw_idx];
6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6574 pci_unmap_page(tp->pdev,
6575 dma_unmap_addr(ri, mapping),
6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6585 sw_idx = NEXT_TX(sw_idx);
6589 bytes_compl += skb->len;
6591 dev_kfree_skb_any(skb);
6593 if (unlikely(tx_bug)) {
6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6601 tnapi->tx_cons = sw_idx;
6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6610 if (unlikely(netif_tx_queue_stopped(txq) &&
6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
6620 static void tg3_frag_free(bool is_frag, void *data)
6623 put_page(virt_to_head_page(data));
6628 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6637 map_sz, PCI_DMA_FROMDEVICE);
6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6643 /* Returns size of skb allocated or < 0 on error.
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6654 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
6658 struct tg3_rx_buffer_desc *desc;
6659 struct ring_info *map;
6662 int skb_size, data_size, dest_idx;
6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
6669 data_size = tp->rx_pkt_map_sz;
6672 case RXD_OPAQUE_RING_JUMBO:
6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6674 desc = &tpr->rx_jmb[dest_idx].std;
6675 map = &tpr->rx_jmb_buffers[dest_idx];
6676 data_size = TG3_RX_JMB_MAP_SZ;
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6704 PCI_DMA_FROMDEVICE);
6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6711 dma_unmap_addr_set(map, mapping, mapping);
6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6719 /* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
6721 * tg3_alloc_rx_data for full details.
6723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
6728 struct tg3 *tp = tnapi->tp;
6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
6743 case RXD_OPAQUE_RING_JUMBO:
6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
6755 dest_map->data = src_map->data;
6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6766 src_map->data = NULL;
6769 /* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6795 struct tg3 *tp = tnapi->tp;
6796 u32 work_mask, rx_std_posted = 0;
6797 u32 std_prod_idx, jmb_prod_idx;
6798 u32 sw_idx = tnapi->rx_rcb_ptr;
6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6813 while (sw_idx != hw_idx && budget > 0) {
6814 struct ring_info *ri;
6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6827 dma_addr = dma_unmap_addr(ri, mapping);
6829 post_ptr = &std_prod_idx;
6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6833 dma_addr = dma_unmap_addr(ri, mapping);
6835 post_ptr = &jmb_prod_idx;
6837 goto next_pkt_nopost;
6839 work_mask |= opaque_key;
6841 if (desc->err_vlan & RXD_ERR_MASK) {
6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
6844 desc_idx, *post_ptr);
6846 /* Other statistics kept track of by card. */
6851 prefetch(data + TG3_RX_OFFSET(tp));
6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6863 if (len > TG3_RX_COPY_THRESH(tp)) {
6865 unsigned int frag_size;
6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6868 *post_ptr, &frag_size);
6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6873 PCI_DMA_FROMDEVICE);
6875 /* Ensure that the update to the data happens
6876 * after the usage of the old DMA mapping.
6882 skb = build_skb(data, frag_size);
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
6890 desc_idx, *post_ptr);
6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6895 goto drop_it_no_recycle;
6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6900 data + TG3_RX_OFFSET(tp),
6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6916 skb_checksum_none_assert(skb);
6918 skb->protocol = eth_type_trans(skb, tp->dev);
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q) &&
6922 skb->protocol != htons(ETH_P_8021AD)) {
6923 dev_kfree_skb_any(skb);
6924 goto drop_it_no_recycle;
6927 if (desc->type_flags & RXD_FLAG_VLAN &&
6928 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6930 desc->err_vlan & RXD_VLAN_MASK);
6932 napi_gro_receive(&tnapi->napi, skb);
6940 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6941 tpr->rx_std_prod_idx = std_prod_idx &
6942 tp->rx_std_ring_mask;
6943 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6944 tpr->rx_std_prod_idx);
6945 work_mask &= ~RXD_OPAQUE_RING_STD;
6950 sw_idx &= tp->rx_ret_ring_mask;
6952 /* Refresh hw_idx to see if there is new work */
6953 if (sw_idx == hw_idx) {
6954 hw_idx = *(tnapi->rx_rcb_prod_idx);
6959 /* ACK the status ring. */
6960 tnapi->rx_rcb_ptr = sw_idx;
6961 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6963 /* Refill RX ring(s). */
6964 if (!tg3_flag(tp, ENABLE_RSS)) {
6965 /* Sync BD data before updating mailbox */
6968 if (work_mask & RXD_OPAQUE_RING_STD) {
6969 tpr->rx_std_prod_idx = std_prod_idx &
6970 tp->rx_std_ring_mask;
6971 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6972 tpr->rx_std_prod_idx);
6974 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6975 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6976 tp->rx_jmb_ring_mask;
6977 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6978 tpr->rx_jmb_prod_idx);
6981 } else if (work_mask) {
6982 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6983 * updated before the producer indices can be updated.
6987 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6990 if (tnapi != &tp->napi[1]) {
6991 tp->rx_refill = true;
6992 napi_schedule(&tp->napi[1].napi);
6999 static void tg3_poll_link(struct tg3 *tp)
7001 /* handle link change and other phy events */
7002 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7003 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7005 if (sblk->status & SD_STATUS_LINK_CHG) {
7006 sblk->status = SD_STATUS_UPDATED |
7007 (sblk->status & ~SD_STATUS_LINK_CHG);
7008 spin_lock(&tp->lock);
7009 if (tg3_flag(tp, USE_PHYLIB)) {
7011 (MAC_STATUS_SYNC_CHANGED |
7012 MAC_STATUS_CFG_CHANGED |
7013 MAC_STATUS_MI_COMPLETION |
7014 MAC_STATUS_LNKSTATE_CHANGED));
7017 tg3_setup_phy(tp, false);
7018 spin_unlock(&tp->lock);
7023 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7024 struct tg3_rx_prodring_set *dpr,
7025 struct tg3_rx_prodring_set *spr)
7027 u32 si, di, cpycnt, src_prod_idx;
7031 src_prod_idx = spr->rx_std_prod_idx;
7033 /* Make sure updates to the rx_std_buffers[] entries and the
7034 * standard producer index are seen in the correct order.
7038 if (spr->rx_std_cons_idx == src_prod_idx)
7041 if (spr->rx_std_cons_idx < src_prod_idx)
7042 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7044 cpycnt = tp->rx_std_ring_mask + 1 -
7045 spr->rx_std_cons_idx;
7047 cpycnt = min(cpycnt,
7048 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7050 si = spr->rx_std_cons_idx;
7051 di = dpr->rx_std_prod_idx;
7053 for (i = di; i < di + cpycnt; i++) {
7054 if (dpr->rx_std_buffers[i].data) {
7064 /* Ensure that updates to the rx_std_buffers ring and the
7065 * shadowed hardware producer ring from tg3_recycle_skb() are
7066 * ordered correctly WRT the skb check above.
7070 memcpy(&dpr->rx_std_buffers[di],
7071 &spr->rx_std_buffers[si],
7072 cpycnt * sizeof(struct ring_info));
7074 for (i = 0; i < cpycnt; i++, di++, si++) {
7075 struct tg3_rx_buffer_desc *sbd, *dbd;
7076 sbd = &spr->rx_std[si];
7077 dbd = &dpr->rx_std[di];
7078 dbd->addr_hi = sbd->addr_hi;
7079 dbd->addr_lo = sbd->addr_lo;
7082 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7084 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7085 tp->rx_std_ring_mask;
7089 src_prod_idx = spr->rx_jmb_prod_idx;
7091 /* Make sure updates to the rx_jmb_buffers[] entries and
7092 * the jumbo producer index are seen in the correct order.
7096 if (spr->rx_jmb_cons_idx == src_prod_idx)
7099 if (spr->rx_jmb_cons_idx < src_prod_idx)
7100 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7102 cpycnt = tp->rx_jmb_ring_mask + 1 -
7103 spr->rx_jmb_cons_idx;
7105 cpycnt = min(cpycnt,
7106 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7108 si = spr->rx_jmb_cons_idx;
7109 di = dpr->rx_jmb_prod_idx;
7111 for (i = di; i < di + cpycnt; i++) {
7112 if (dpr->rx_jmb_buffers[i].data) {
7122 /* Ensure that updates to the rx_jmb_buffers ring and the
7123 * shadowed hardware producer ring from tg3_recycle_skb() are
7124 * ordered correctly WRT the skb check above.
7128 memcpy(&dpr->rx_jmb_buffers[di],
7129 &spr->rx_jmb_buffers[si],
7130 cpycnt * sizeof(struct ring_info));
7132 for (i = 0; i < cpycnt; i++, di++, si++) {
7133 struct tg3_rx_buffer_desc *sbd, *dbd;
7134 sbd = &spr->rx_jmb[si].std;
7135 dbd = &dpr->rx_jmb[di].std;
7136 dbd->addr_hi = sbd->addr_hi;
7137 dbd->addr_lo = sbd->addr_lo;
7140 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7142 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7143 tp->rx_jmb_ring_mask;
7149 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7151 struct tg3 *tp = tnapi->tp;
7153 /* run TX completion thread */
7154 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7156 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7160 if (!tnapi->rx_rcb_prod_idx)
7163 /* run RX thread, within the bounds set by NAPI.
7164 * All RX "locking" is done by ensuring outside
7165 * code synchronizes with tg3->napi.poll()
7167 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7168 work_done += tg3_rx(tnapi, budget - work_done);
7170 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7171 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7173 u32 std_prod_idx = dpr->rx_std_prod_idx;
7174 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7176 tp->rx_refill = false;
7177 for (i = 1; i <= tp->rxq_cnt; i++)
7178 err |= tg3_rx_prodring_xfer(tp, dpr,
7179 &tp->napi[i].prodring);
7183 if (std_prod_idx != dpr->rx_std_prod_idx)
7184 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7185 dpr->rx_std_prod_idx);
7187 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7188 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7189 dpr->rx_jmb_prod_idx);
7194 tw32_f(HOSTCC_MODE, tp->coal_now);
7200 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7202 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7203 schedule_work(&tp->reset_task);
7206 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7208 cancel_work_sync(&tp->reset_task);
7209 tg3_flag_clear(tp, RESET_TASK_PENDING);
7210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7213 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7215 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7216 struct tg3 *tp = tnapi->tp;
7218 struct tg3_hw_status *sblk = tnapi->hw_status;
7221 work_done = tg3_poll_work(tnapi, work_done, budget);
7223 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7226 if (unlikely(work_done >= budget))
7229 /* tp->last_tag is used in tg3_int_reenable() below
7230 * to tell the hw how much work has been processed,
7231 * so we must read it before checking for more work.
7233 tnapi->last_tag = sblk->status_tag;
7234 tnapi->last_irq_tag = tnapi->last_tag;
7237 /* check for RX/TX work to do */
7238 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7239 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7241 /* This test here is not race free, but will reduce
7242 * the number of interrupts by looping again.
7244 if (tnapi == &tp->napi[1] && tp->rx_refill)
7247 napi_complete_done(napi, work_done);
7248 /* Reenable interrupts. */
7249 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7251 /* This test here is synchronized by napi_schedule()
7252 * and napi_complete() to close the race condition.
7254 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7255 tw32(HOSTCC_MODE, tp->coalesce_mode |
7256 HOSTCC_MODE_ENABLE |
7267 /* work_done is guaranteed to be less than budget. */
7268 napi_complete(napi);
7269 tg3_reset_task_schedule(tp);
7273 static void tg3_process_error(struct tg3 *tp)
7276 bool real_error = false;
7278 if (tg3_flag(tp, ERROR_PROCESSED))
7281 /* Check Flow Attention register */
7282 val = tr32(HOSTCC_FLOW_ATTN);
7283 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7284 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7288 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7289 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7293 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7294 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7303 tg3_flag_set(tp, ERROR_PROCESSED);
7304 tg3_reset_task_schedule(tp);
7307 static int tg3_poll(struct napi_struct *napi, int budget)
7309 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7310 struct tg3 *tp = tnapi->tp;
7312 struct tg3_hw_status *sblk = tnapi->hw_status;
7315 if (sblk->status & SD_STATUS_ERROR)
7316 tg3_process_error(tp);
7320 work_done = tg3_poll_work(tnapi, work_done, budget);
7322 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7325 if (unlikely(work_done >= budget))
7328 if (tg3_flag(tp, TAGGED_STATUS)) {
7329 /* tp->last_tag is used in tg3_int_reenable() below
7330 * to tell the hw how much work has been processed,
7331 * so we must read it before checking for more work.
7333 tnapi->last_tag = sblk->status_tag;
7334 tnapi->last_irq_tag = tnapi->last_tag;
7337 sblk->status &= ~SD_STATUS_UPDATED;
7339 if (likely(!tg3_has_work(tnapi))) {
7340 napi_complete_done(napi, work_done);
7341 tg3_int_reenable(tnapi);
7349 /* work_done is guaranteed to be less than budget. */
7350 napi_complete(napi);
7351 tg3_reset_task_schedule(tp);
7355 static void tg3_napi_disable(struct tg3 *tp)
7359 for (i = tp->irq_cnt - 1; i >= 0; i--)
7360 napi_disable(&tp->napi[i].napi);
7363 static void tg3_napi_enable(struct tg3 *tp)
7367 for (i = 0; i < tp->irq_cnt; i++)
7368 napi_enable(&tp->napi[i].napi);
7371 static void tg3_napi_init(struct tg3 *tp)
7375 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7376 for (i = 1; i < tp->irq_cnt; i++)
7377 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7380 static void tg3_napi_fini(struct tg3 *tp)
7384 for (i = 0; i < tp->irq_cnt; i++)
7385 netif_napi_del(&tp->napi[i].napi);
7388 static inline void tg3_netif_stop(struct tg3 *tp)
7390 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7391 tg3_napi_disable(tp);
7392 netif_carrier_off(tp->dev);
7393 netif_tx_disable(tp->dev);
7396 /* tp->lock must be held */
7397 static inline void tg3_netif_start(struct tg3 *tp)
7401 /* NOTE: unconditional netif_tx_wake_all_queues is only
7402 * appropriate so long as all callers are assured to
7403 * have free tx slots (such as after tg3_init_hw)
7405 netif_tx_wake_all_queues(tp->dev);
7408 netif_carrier_on(tp->dev);
7410 tg3_napi_enable(tp);
7411 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7412 tg3_enable_ints(tp);
7415 static void tg3_irq_quiesce(struct tg3 *tp)
7416 __releases(tp->lock)
7417 __acquires(tp->lock)
7421 BUG_ON(tp->irq_sync);
7426 spin_unlock_bh(&tp->lock);
7428 for (i = 0; i < tp->irq_cnt; i++)
7429 synchronize_irq(tp->napi[i].irq_vec);
7431 spin_lock_bh(&tp->lock);
7434 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7435 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7436 * with as well. Most of the time, this is not necessary except when
7437 * shutting down the device.
7439 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7441 spin_lock_bh(&tp->lock);
7443 tg3_irq_quiesce(tp);
7446 static inline void tg3_full_unlock(struct tg3 *tp)
7448 spin_unlock_bh(&tp->lock);
7451 /* One-shot MSI handler - Chip automatically disables interrupt
7452 * after sending MSI so driver doesn't have to do it.
7454 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7456 struct tg3_napi *tnapi = dev_id;
7457 struct tg3 *tp = tnapi->tp;
7459 prefetch(tnapi->hw_status);
7461 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7463 if (likely(!tg3_irq_sync(tp)))
7464 napi_schedule(&tnapi->napi);
7469 /* MSI ISR - No need to check for interrupt sharing and no need to
7470 * flush status block and interrupt mailbox. PCI ordering rules
7471 * guarantee that MSI will arrive after the status block.
7473 static irqreturn_t tg3_msi(int irq, void *dev_id)
7475 struct tg3_napi *tnapi = dev_id;
7476 struct tg3 *tp = tnapi->tp;
7478 prefetch(tnapi->hw_status);
7480 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7482 * Writing any value to intr-mbox-0 clears PCI INTA# and
7483 * chip-internal interrupt pending events.
7484 * Writing non-zero to intr-mbox-0 additional tells the
7485 * NIC to stop sending us irqs, engaging "in-intr-handler"
7488 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7489 if (likely(!tg3_irq_sync(tp)))
7490 napi_schedule(&tnapi->napi);
7492 return IRQ_RETVAL(1);
7495 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7497 struct tg3_napi *tnapi = dev_id;
7498 struct tg3 *tp = tnapi->tp;
7499 struct tg3_hw_status *sblk = tnapi->hw_status;
7500 unsigned int handled = 1;
7502 /* In INTx mode, it is possible for the interrupt to arrive at
7503 * the CPU before the status block posted prior to the interrupt.
7504 * Reading the PCI State register will confirm whether the
7505 * interrupt is ours and will flush the status block.
7507 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7508 if (tg3_flag(tp, CHIP_RESETTING) ||
7509 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7516 * Writing any value to intr-mbox-0 clears PCI INTA# and
7517 * chip-internal interrupt pending events.
7518 * Writing non-zero to intr-mbox-0 additional tells the
7519 * NIC to stop sending us irqs, engaging "in-intr-handler"
7522 * Flush the mailbox to de-assert the IRQ immediately to prevent
7523 * spurious interrupts. The flush impacts performance but
7524 * excessive spurious interrupts can be worse in some cases.
7526 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7527 if (tg3_irq_sync(tp))
7529 sblk->status &= ~SD_STATUS_UPDATED;
7530 if (likely(tg3_has_work(tnapi))) {
7531 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7532 napi_schedule(&tnapi->napi);
7534 /* No work, shared interrupt perhaps? re-enable
7535 * interrupts, and flush that PCI write
7537 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7541 return IRQ_RETVAL(handled);
7544 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7546 struct tg3_napi *tnapi = dev_id;
7547 struct tg3 *tp = tnapi->tp;
7548 struct tg3_hw_status *sblk = tnapi->hw_status;
7549 unsigned int handled = 1;
7551 /* In INTx mode, it is possible for the interrupt to arrive at
7552 * the CPU before the status block posted prior to the interrupt.
7553 * Reading the PCI State register will confirm whether the
7554 * interrupt is ours and will flush the status block.
7556 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7557 if (tg3_flag(tp, CHIP_RESETTING) ||
7558 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7565 * writing any value to intr-mbox-0 clears PCI INTA# and
7566 * chip-internal interrupt pending events.
7567 * writing non-zero to intr-mbox-0 additional tells the
7568 * NIC to stop sending us irqs, engaging "in-intr-handler"
7571 * Flush the mailbox to de-assert the IRQ immediately to prevent
7572 * spurious interrupts. The flush impacts performance but
7573 * excessive spurious interrupts can be worse in some cases.
7575 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7578 * In a shared interrupt configuration, sometimes other devices'
7579 * interrupts will scream. We record the current status tag here
7580 * so that the above check can report that the screaming interrupts
7581 * are unhandled. Eventually they will be silenced.
7583 tnapi->last_irq_tag = sblk->status_tag;
7585 if (tg3_irq_sync(tp))
7588 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7590 napi_schedule(&tnapi->napi);
7593 return IRQ_RETVAL(handled);
7596 /* ISR for interrupt test */
7597 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7599 struct tg3_napi *tnapi = dev_id;
7600 struct tg3 *tp = tnapi->tp;
7601 struct tg3_hw_status *sblk = tnapi->hw_status;
7603 if ((sblk->status & SD_STATUS_UPDATED) ||
7604 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7605 tg3_disable_ints(tp);
7606 return IRQ_RETVAL(1);
7608 return IRQ_RETVAL(0);
7611 #ifdef CONFIG_NET_POLL_CONTROLLER
7612 static void tg3_poll_controller(struct net_device *dev)
7615 struct tg3 *tp = netdev_priv(dev);
7617 if (tg3_irq_sync(tp))
7620 for (i = 0; i < tp->irq_cnt; i++)
7621 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7625 static void tg3_tx_timeout(struct net_device *dev)
7627 struct tg3 *tp = netdev_priv(dev);
7629 if (netif_msg_tx_err(tp)) {
7630 netdev_err(dev, "transmit timed out, resetting\n");
7634 tg3_reset_task_schedule(tp);
7637 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7638 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7640 u32 base = (u32) mapping & 0xffffffff;
7642 return base + len + 8 < base;
7645 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7646 * of any 4GB boundaries: 4G, 8G, etc
7648 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7651 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7652 u32 base = (u32) mapping & 0xffffffff;
7654 return ((base + len + (mss & 0x3fff)) < base);
7659 /* Test for DMA addresses > 40-bit */
7660 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7663 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7664 if (tg3_flag(tp, 40BIT_DMA_BUG))
7665 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7672 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7673 dma_addr_t mapping, u32 len, u32 flags,
7676 txbd->addr_hi = ((u64) mapping >> 32);
7677 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7678 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7679 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7682 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7683 dma_addr_t map, u32 len, u32 flags,
7686 struct tg3 *tp = tnapi->tp;
7689 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7692 if (tg3_4g_overflow_test(map, len))
7695 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7698 if (tg3_40bit_overflow_test(tp, map, len))
7701 if (tp->dma_limit) {
7702 u32 prvidx = *entry;
7703 u32 tmp_flag = flags & ~TXD_FLAG_END;
7704 while (len > tp->dma_limit && *budget) {
7705 u32 frag_len = tp->dma_limit;
7706 len -= tp->dma_limit;
7708 /* Avoid the 8byte DMA problem */
7710 len += tp->dma_limit / 2;
7711 frag_len = tp->dma_limit / 2;
7714 tnapi->tx_buffers[*entry].fragmented = true;
7716 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7717 frag_len, tmp_flag, mss, vlan);
7720 *entry = NEXT_TX(*entry);
7727 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7728 len, flags, mss, vlan);
7730 *entry = NEXT_TX(*entry);
7733 tnapi->tx_buffers[prvidx].fragmented = false;
7737 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7738 len, flags, mss, vlan);
7739 *entry = NEXT_TX(*entry);
7745 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7748 struct sk_buff *skb;
7749 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7754 pci_unmap_single(tnapi->tp->pdev,
7755 dma_unmap_addr(txb, mapping),
7759 while (txb->fragmented) {
7760 txb->fragmented = false;
7761 entry = NEXT_TX(entry);
7762 txb = &tnapi->tx_buffers[entry];
7765 for (i = 0; i <= last; i++) {
7766 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7768 entry = NEXT_TX(entry);
7769 txb = &tnapi->tx_buffers[entry];
7771 pci_unmap_page(tnapi->tp->pdev,
7772 dma_unmap_addr(txb, mapping),
7773 skb_frag_size(frag), PCI_DMA_TODEVICE);
7775 while (txb->fragmented) {
7776 txb->fragmented = false;
7777 entry = NEXT_TX(entry);
7778 txb = &tnapi->tx_buffers[entry];
7783 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7784 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7785 struct sk_buff **pskb,
7786 u32 *entry, u32 *budget,
7787 u32 base_flags, u32 mss, u32 vlan)
7789 struct tg3 *tp = tnapi->tp;
7790 struct sk_buff *new_skb, *skb = *pskb;
7791 dma_addr_t new_addr = 0;
7794 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7795 new_skb = skb_copy(skb, GFP_ATOMIC);
7797 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7799 new_skb = skb_copy_expand(skb,
7800 skb_headroom(skb) + more_headroom,
7801 skb_tailroom(skb), GFP_ATOMIC);
7807 /* New SKB is guaranteed to be linear. */
7808 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7810 /* Make sure the mapping succeeded */
7811 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7812 dev_kfree_skb_any(new_skb);
7815 u32 save_entry = *entry;
7817 base_flags |= TXD_FLAG_END;
7819 tnapi->tx_buffers[*entry].skb = new_skb;
7820 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7823 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7824 new_skb->len, base_flags,
7826 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7827 dev_kfree_skb_any(new_skb);
7833 dev_kfree_skb_any(skb);
7838 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7840 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7841 * indicated in tg3_tx_frag_set()
7843 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7844 struct netdev_queue *txq, struct sk_buff *skb)
7846 struct sk_buff *segs, *nskb;
7847 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7849 /* Estimate the number of fragments in the worst case */
7850 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7851 netif_tx_stop_queue(txq);
7853 /* netif_tx_stop_queue() must be done before checking
7854 * checking tx index in tg3_tx_avail() below, because in
7855 * tg3_tx(), we update tx index before checking for
7856 * netif_tx_queue_stopped().
7859 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7860 return NETDEV_TX_BUSY;
7862 netif_tx_wake_queue(txq);
7865 segs = skb_gso_segment(skb, tp->dev->features &
7866 ~(NETIF_F_TSO | NETIF_F_TSO6));
7867 if (IS_ERR(segs) || !segs)
7868 goto tg3_tso_bug_end;
7874 tg3_start_xmit(nskb, tp->dev);
7878 dev_kfree_skb_any(skb);
7880 return NETDEV_TX_OK;
7883 /* hard_start_xmit for all devices */
7884 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7886 struct tg3 *tp = netdev_priv(dev);
7887 u32 len, entry, base_flags, mss, vlan = 0;
7889 int i = -1, would_hit_hwbug;
7891 struct tg3_napi *tnapi;
7892 struct netdev_queue *txq;
7894 struct iphdr *iph = NULL;
7895 struct tcphdr *tcph = NULL;
7896 __sum16 tcp_csum = 0, ip_csum = 0;
7897 __be16 ip_tot_len = 0;
7899 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7900 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7901 if (tg3_flag(tp, ENABLE_TSS))
7904 budget = tg3_tx_avail(tnapi);
7906 /* We are running in BH disabled context with netif_tx_lock
7907 * and TX reclaim runs via tp->napi.poll inside of a software
7908 * interrupt. Furthermore, IRQ processing runs lockless so we have
7909 * no IRQ context deadlocks to worry about either. Rejoice!
7911 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7912 if (!netif_tx_queue_stopped(txq)) {
7913 netif_tx_stop_queue(txq);
7915 /* This is a hard error, log it. */
7917 "BUG! Tx Ring full when queue awake!\n");
7919 return NETDEV_TX_BUSY;
7922 entry = tnapi->tx_prod;
7925 mss = skb_shinfo(skb)->gso_size;
7927 u32 tcp_opt_len, hdr_len;
7929 if (skb_cow_head(skb, 0))
7933 tcp_opt_len = tcp_optlen(skb);
7935 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7937 /* HW/FW can not correctly segment packets that have been
7938 * vlan encapsulated.
7940 if (skb->protocol == htons(ETH_P_8021Q) ||
7941 skb->protocol == htons(ETH_P_8021AD))
7942 return tg3_tso_bug(tp, tnapi, txq, skb);
7944 if (!skb_is_gso_v6(skb)) {
7945 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7946 tg3_flag(tp, TSO_BUG))
7947 return tg3_tso_bug(tp, tnapi, txq, skb);
7949 ip_csum = iph->check;
7950 ip_tot_len = iph->tot_len;
7952 iph->tot_len = htons(mss + hdr_len);
7955 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7956 TXD_FLAG_CPU_POST_DMA);
7958 tcph = tcp_hdr(skb);
7959 tcp_csum = tcph->check;
7961 if (tg3_flag(tp, HW_TSO_1) ||
7962 tg3_flag(tp, HW_TSO_2) ||
7963 tg3_flag(tp, HW_TSO_3)) {
7965 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7967 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7971 if (tg3_flag(tp, HW_TSO_3)) {
7972 mss |= (hdr_len & 0xc) << 12;
7974 base_flags |= 0x00000010;
7975 base_flags |= (hdr_len & 0x3e0) << 5;
7976 } else if (tg3_flag(tp, HW_TSO_2))
7977 mss |= hdr_len << 9;
7978 else if (tg3_flag(tp, HW_TSO_1) ||
7979 tg3_asic_rev(tp) == ASIC_REV_5705) {
7980 if (tcp_opt_len || iph->ihl > 5) {
7983 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7984 mss |= (tsflags << 11);
7987 if (tcp_opt_len || iph->ihl > 5) {
7990 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7991 base_flags |= tsflags << 12;
7994 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7995 /* HW/FW can not correctly checksum packets that have been
7996 * vlan encapsulated.
7998 if (skb->protocol == htons(ETH_P_8021Q) ||
7999 skb->protocol == htons(ETH_P_8021AD)) {
8000 if (skb_checksum_help(skb))
8003 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8007 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8008 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8009 base_flags |= TXD_FLAG_JMB_PKT;
8011 if (skb_vlan_tag_present(skb)) {
8012 base_flags |= TXD_FLAG_VLAN;
8013 vlan = skb_vlan_tag_get(skb);
8016 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8017 tg3_flag(tp, TX_TSTAMP_EN)) {
8018 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8019 base_flags |= TXD_FLAG_HWTSTAMP;
8022 len = skb_headlen(skb);
8024 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8025 if (pci_dma_mapping_error(tp->pdev, mapping))
8029 tnapi->tx_buffers[entry].skb = skb;
8030 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8032 would_hit_hwbug = 0;
8034 if (tg3_flag(tp, 5701_DMA_BUG))
8035 would_hit_hwbug = 1;
8037 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8038 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8040 would_hit_hwbug = 1;
8041 } else if (skb_shinfo(skb)->nr_frags > 0) {
8044 if (!tg3_flag(tp, HW_TSO_1) &&
8045 !tg3_flag(tp, HW_TSO_2) &&
8046 !tg3_flag(tp, HW_TSO_3))
8049 /* Now loop through additional data
8050 * fragments, and queue them.
8052 last = skb_shinfo(skb)->nr_frags - 1;
8053 for (i = 0; i <= last; i++) {
8054 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8056 len = skb_frag_size(frag);
8057 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8058 len, DMA_TO_DEVICE);
8060 tnapi->tx_buffers[entry].skb = NULL;
8061 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8063 if (dma_mapping_error(&tp->pdev->dev, mapping))
8067 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8069 ((i == last) ? TXD_FLAG_END : 0),
8071 would_hit_hwbug = 1;
8077 if (would_hit_hwbug) {
8078 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8081 /* If it's a TSO packet, do GSO instead of
8082 * allocating and copying to a large linear SKB
8085 iph->check = ip_csum;
8086 iph->tot_len = ip_tot_len;
8088 tcph->check = tcp_csum;
8089 return tg3_tso_bug(tp, tnapi, txq, skb);
8092 /* If the workaround fails due to memory/mapping
8093 * failure, silently drop this packet.
8095 entry = tnapi->tx_prod;
8096 budget = tg3_tx_avail(tnapi);
8097 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8098 base_flags, mss, vlan))
8102 skb_tx_timestamp(skb);
8103 netdev_tx_sent_queue(txq, skb->len);
8105 /* Sync BD data before updating mailbox */
8108 tnapi->tx_prod = entry;
8109 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8110 netif_tx_stop_queue(txq);
8112 /* netif_tx_stop_queue() must be done before checking
8113 * checking tx index in tg3_tx_avail() below, because in
8114 * tg3_tx(), we update tx index before checking for
8115 * netif_tx_queue_stopped().
8118 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8119 netif_tx_wake_queue(txq);
8122 if (!skb->xmit_more || netif_xmit_stopped(txq)) {
8123 /* Packets are ready, update Tx producer idx on card. */
8124 tw32_tx_mbox(tnapi->prodmbox, entry);
8128 return NETDEV_TX_OK;
8131 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8132 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8134 dev_kfree_skb_any(skb);
8137 return NETDEV_TX_OK;
8140 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8143 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8144 MAC_MODE_PORT_MODE_MASK);
8146 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8148 if (!tg3_flag(tp, 5705_PLUS))
8149 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8151 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8152 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8154 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8156 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8158 if (tg3_flag(tp, 5705_PLUS) ||
8159 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8160 tg3_asic_rev(tp) == ASIC_REV_5700)
8161 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8164 tw32(MAC_MODE, tp->mac_mode);
8168 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8170 u32 val, bmcr, mac_mode, ptest = 0;
8172 tg3_phy_toggle_apd(tp, false);
8173 tg3_phy_toggle_automdix(tp, false);
8175 if (extlpbk && tg3_phy_set_extloopbk(tp))
8178 bmcr = BMCR_FULLDPLX;
8183 bmcr |= BMCR_SPEED100;
8187 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8189 bmcr |= BMCR_SPEED100;
8192 bmcr |= BMCR_SPEED1000;
8197 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8198 tg3_readphy(tp, MII_CTRL1000, &val);
8199 val |= CTL1000_AS_MASTER |
8200 CTL1000_ENABLE_MASTER;
8201 tg3_writephy(tp, MII_CTRL1000, val);
8203 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8204 MII_TG3_FET_PTEST_TRIM_2;
8205 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8208 bmcr |= BMCR_LOOPBACK;
8210 tg3_writephy(tp, MII_BMCR, bmcr);
8212 /* The write needs to be flushed for the FETs */
8213 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8214 tg3_readphy(tp, MII_BMCR, &bmcr);
8218 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8219 tg3_asic_rev(tp) == ASIC_REV_5785) {
8220 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8221 MII_TG3_FET_PTEST_FRC_TX_LINK |
8222 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8224 /* The write needs to be flushed for the AC131 */
8225 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8228 /* Reset to prevent losing 1st rx packet intermittently */
8229 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8230 tg3_flag(tp, 5780_CLASS)) {
8231 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8233 tw32_f(MAC_RX_MODE, tp->rx_mode);
8236 mac_mode = tp->mac_mode &
8237 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8238 if (speed == SPEED_1000)
8239 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8241 mac_mode |= MAC_MODE_PORT_MODE_MII;
8243 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8244 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8246 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8247 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8248 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8249 mac_mode |= MAC_MODE_LINK_POLARITY;
8251 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8252 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8255 tw32(MAC_MODE, mac_mode);
8261 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8263 struct tg3 *tp = netdev_priv(dev);
8265 if (features & NETIF_F_LOOPBACK) {
8266 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8269 spin_lock_bh(&tp->lock);
8270 tg3_mac_loopback(tp, true);
8271 netif_carrier_on(tp->dev);
8272 spin_unlock_bh(&tp->lock);
8273 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8275 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8278 spin_lock_bh(&tp->lock);
8279 tg3_mac_loopback(tp, false);
8280 /* Force link status check */
8281 tg3_setup_phy(tp, true);
8282 spin_unlock_bh(&tp->lock);
8283 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8287 static netdev_features_t tg3_fix_features(struct net_device *dev,
8288 netdev_features_t features)
8290 struct tg3 *tp = netdev_priv(dev);
8292 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8293 features &= ~NETIF_F_ALL_TSO;
8298 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8300 netdev_features_t changed = dev->features ^ features;
8302 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8303 tg3_set_loopback(dev, features);
8308 static void tg3_rx_prodring_free(struct tg3 *tp,
8309 struct tg3_rx_prodring_set *tpr)
8313 if (tpr != &tp->napi[0].prodring) {
8314 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8315 i = (i + 1) & tp->rx_std_ring_mask)
8316 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8319 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8320 for (i = tpr->rx_jmb_cons_idx;
8321 i != tpr->rx_jmb_prod_idx;
8322 i = (i + 1) & tp->rx_jmb_ring_mask) {
8323 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8331 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8332 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8335 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8336 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8337 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8342 /* Initialize rx rings for packet processing.
8344 * The chip has been shut down and the driver detached from
8345 * the networking, so no interrupts or new tx packets will
8346 * end up in the driver. tp->{tx,}lock are held and thus
8349 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8350 struct tg3_rx_prodring_set *tpr)
8352 u32 i, rx_pkt_dma_sz;
8354 tpr->rx_std_cons_idx = 0;
8355 tpr->rx_std_prod_idx = 0;
8356 tpr->rx_jmb_cons_idx = 0;
8357 tpr->rx_jmb_prod_idx = 0;
8359 if (tpr != &tp->napi[0].prodring) {
8360 memset(&tpr->rx_std_buffers[0], 0,
8361 TG3_RX_STD_BUFF_RING_SIZE(tp));
8362 if (tpr->rx_jmb_buffers)
8363 memset(&tpr->rx_jmb_buffers[0], 0,
8364 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8368 /* Zero out all descriptors. */
8369 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8371 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8372 if (tg3_flag(tp, 5780_CLASS) &&
8373 tp->dev->mtu > ETH_DATA_LEN)
8374 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8375 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8377 /* Initialize invariants of the rings, we only set this
8378 * stuff once. This works because the card does not
8379 * write into the rx buffer posting rings.
8381 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8382 struct tg3_rx_buffer_desc *rxd;
8384 rxd = &tpr->rx_std[i];
8385 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8386 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8387 rxd->opaque = (RXD_OPAQUE_RING_STD |
8388 (i << RXD_OPAQUE_INDEX_SHIFT));
8391 /* Now allocate fresh SKBs for each rx ring. */
8392 for (i = 0; i < tp->rx_pending; i++) {
8393 unsigned int frag_size;
8395 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8397 netdev_warn(tp->dev,
8398 "Using a smaller RX standard ring. Only "
8399 "%d out of %d buffers were allocated "
8400 "successfully\n", i, tp->rx_pending);
8408 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8411 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8413 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8416 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8417 struct tg3_rx_buffer_desc *rxd;
8419 rxd = &tpr->rx_jmb[i].std;
8420 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8421 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8423 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8424 (i << RXD_OPAQUE_INDEX_SHIFT));
8427 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8428 unsigned int frag_size;
8430 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8432 netdev_warn(tp->dev,
8433 "Using a smaller RX jumbo ring. Only %d "
8434 "out of %d buffers were allocated "
8435 "successfully\n", i, tp->rx_jumbo_pending);
8438 tp->rx_jumbo_pending = i;
8447 tg3_rx_prodring_free(tp, tpr);
8451 static void tg3_rx_prodring_fini(struct tg3 *tp,
8452 struct tg3_rx_prodring_set *tpr)
8454 kfree(tpr->rx_std_buffers);
8455 tpr->rx_std_buffers = NULL;
8456 kfree(tpr->rx_jmb_buffers);
8457 tpr->rx_jmb_buffers = NULL;
8459 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8460 tpr->rx_std, tpr->rx_std_mapping);
8464 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8465 tpr->rx_jmb, tpr->rx_jmb_mapping);
8470 static int tg3_rx_prodring_init(struct tg3 *tp,
8471 struct tg3_rx_prodring_set *tpr)
8473 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8475 if (!tpr->rx_std_buffers)
8478 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8479 TG3_RX_STD_RING_BYTES(tp),
8480 &tpr->rx_std_mapping,
8485 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8486 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8488 if (!tpr->rx_jmb_buffers)
8491 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8492 TG3_RX_JMB_RING_BYTES(tp),
8493 &tpr->rx_jmb_mapping,
8502 tg3_rx_prodring_fini(tp, tpr);
8506 /* Free up pending packets in all rx/tx rings.
8508 * The chip has been shut down and the driver detached from
8509 * the networking, so no interrupts or new tx packets will
8510 * end up in the driver. tp->{tx,}lock is not held and we are not
8511 * in an interrupt context and thus may sleep.
8513 static void tg3_free_rings(struct tg3 *tp)
8517 for (j = 0; j < tp->irq_cnt; j++) {
8518 struct tg3_napi *tnapi = &tp->napi[j];
8520 tg3_rx_prodring_free(tp, &tnapi->prodring);
8522 if (!tnapi->tx_buffers)
8525 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8526 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8531 tg3_tx_skb_unmap(tnapi, i,
8532 skb_shinfo(skb)->nr_frags - 1);
8534 dev_kfree_skb_any(skb);
8536 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8540 /* Initialize tx/rx rings for packet processing.
8542 * The chip has been shut down and the driver detached from
8543 * the networking, so no interrupts or new tx packets will
8544 * end up in the driver. tp->{tx,}lock are held and thus
8547 static int tg3_init_rings(struct tg3 *tp)
8551 /* Free up all the SKBs. */
8554 for (i = 0; i < tp->irq_cnt; i++) {
8555 struct tg3_napi *tnapi = &tp->napi[i];
8557 tnapi->last_tag = 0;
8558 tnapi->last_irq_tag = 0;
8559 tnapi->hw_status->status = 0;
8560 tnapi->hw_status->status_tag = 0;
8561 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8566 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8568 tnapi->rx_rcb_ptr = 0;
8570 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8572 if (tnapi->prodring.rx_std &&
8573 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8582 static void tg3_mem_tx_release(struct tg3 *tp)
8586 for (i = 0; i < tp->irq_max; i++) {
8587 struct tg3_napi *tnapi = &tp->napi[i];
8589 if (tnapi->tx_ring) {
8590 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8591 tnapi->tx_ring, tnapi->tx_desc_mapping);
8592 tnapi->tx_ring = NULL;
8595 kfree(tnapi->tx_buffers);
8596 tnapi->tx_buffers = NULL;
8600 static int tg3_mem_tx_acquire(struct tg3 *tp)
8603 struct tg3_napi *tnapi = &tp->napi[0];
8605 /* If multivector TSS is enabled, vector 0 does not handle
8606 * tx interrupts. Don't allocate any resources for it.
8608 if (tg3_flag(tp, ENABLE_TSS))
8611 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8612 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8613 TG3_TX_RING_SIZE, GFP_KERNEL);
8614 if (!tnapi->tx_buffers)
8617 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8619 &tnapi->tx_desc_mapping,
8621 if (!tnapi->tx_ring)
8628 tg3_mem_tx_release(tp);
8632 static void tg3_mem_rx_release(struct tg3 *tp)
8636 for (i = 0; i < tp->irq_max; i++) {
8637 struct tg3_napi *tnapi = &tp->napi[i];
8639 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8644 dma_free_coherent(&tp->pdev->dev,
8645 TG3_RX_RCB_RING_BYTES(tp),
8647 tnapi->rx_rcb_mapping);
8648 tnapi->rx_rcb = NULL;
8652 static int tg3_mem_rx_acquire(struct tg3 *tp)
8654 unsigned int i, limit;
8656 limit = tp->rxq_cnt;
8658 /* If RSS is enabled, we need a (dummy) producer ring
8659 * set on vector zero. This is the true hw prodring.
8661 if (tg3_flag(tp, ENABLE_RSS))
8664 for (i = 0; i < limit; i++) {
8665 struct tg3_napi *tnapi = &tp->napi[i];
8667 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8670 /* If multivector RSS is enabled, vector 0
8671 * does not handle rx or tx interrupts.
8672 * Don't allocate any resources for it.
8674 if (!i && tg3_flag(tp, ENABLE_RSS))
8677 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8678 TG3_RX_RCB_RING_BYTES(tp),
8679 &tnapi->rx_rcb_mapping,
8688 tg3_mem_rx_release(tp);
8693 * Must not be invoked with interrupt sources disabled and
8694 * the hardware shutdown down.
8696 static void tg3_free_consistent(struct tg3 *tp)
8700 for (i = 0; i < tp->irq_cnt; i++) {
8701 struct tg3_napi *tnapi = &tp->napi[i];
8703 if (tnapi->hw_status) {
8704 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8706 tnapi->status_mapping);
8707 tnapi->hw_status = NULL;
8711 tg3_mem_rx_release(tp);
8712 tg3_mem_tx_release(tp);
8715 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8716 tp->hw_stats, tp->stats_mapping);
8717 tp->hw_stats = NULL;
8722 * Must not be invoked with interrupt sources disabled and
8723 * the hardware shutdown down. Can sleep.
8725 static int tg3_alloc_consistent(struct tg3 *tp)
8729 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8730 sizeof(struct tg3_hw_stats),
8731 &tp->stats_mapping, GFP_KERNEL);
8735 for (i = 0; i < tp->irq_cnt; i++) {
8736 struct tg3_napi *tnapi = &tp->napi[i];
8737 struct tg3_hw_status *sblk;
8739 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8741 &tnapi->status_mapping,
8743 if (!tnapi->hw_status)
8746 sblk = tnapi->hw_status;
8748 if (tg3_flag(tp, ENABLE_RSS)) {
8749 u16 *prodptr = NULL;
8752 * When RSS is enabled, the status block format changes
8753 * slightly. The "rx_jumbo_consumer", "reserved",
8754 * and "rx_mini_consumer" members get mapped to the
8755 * other three rx return ring producer indexes.
8759 prodptr = &sblk->idx[0].rx_producer;
8762 prodptr = &sblk->rx_jumbo_consumer;
8765 prodptr = &sblk->reserved;
8768 prodptr = &sblk->rx_mini_consumer;
8771 tnapi->rx_rcb_prod_idx = prodptr;
8773 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8777 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8783 tg3_free_consistent(tp);
8787 #define MAX_WAIT_CNT 1000
8789 /* To stop a block, clear the enable bit and poll till it
8790 * clears. tp->lock is held.
8792 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8797 if (tg3_flag(tp, 5705_PLUS)) {
8804 /* We can't enable/disable these bits of the
8805 * 5705/5750, just say success.
8818 for (i = 0; i < MAX_WAIT_CNT; i++) {
8819 if (pci_channel_offline(tp->pdev)) {
8820 dev_err(&tp->pdev->dev,
8821 "tg3_stop_block device offline, "
8822 "ofs=%lx enable_bit=%x\n",
8829 if ((val & enable_bit) == 0)
8833 if (i == MAX_WAIT_CNT && !silent) {
8834 dev_err(&tp->pdev->dev,
8835 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8843 /* tp->lock is held. */
8844 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8848 tg3_disable_ints(tp);
8850 if (pci_channel_offline(tp->pdev)) {
8851 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8852 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8857 tp->rx_mode &= ~RX_MODE_ENABLE;
8858 tw32_f(MAC_RX_MODE, tp->rx_mode);
8861 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8866 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8868 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8869 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8870 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8871 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8872 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8873 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8874 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8876 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8877 tw32_f(MAC_MODE, tp->mac_mode);
8880 tp->tx_mode &= ~TX_MODE_ENABLE;
8881 tw32_f(MAC_TX_MODE, tp->tx_mode);
8883 for (i = 0; i < MAX_WAIT_CNT; i++) {
8885 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8888 if (i >= MAX_WAIT_CNT) {
8889 dev_err(&tp->pdev->dev,
8890 "%s timed out, TX_MODE_ENABLE will not clear "
8891 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8895 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8896 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8897 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8899 tw32(FTQ_RESET, 0xffffffff);
8900 tw32(FTQ_RESET, 0x00000000);
8902 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8903 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8906 for (i = 0; i < tp->irq_cnt; i++) {
8907 struct tg3_napi *tnapi = &tp->napi[i];
8908 if (tnapi->hw_status)
8909 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8915 /* Save PCI command register before chip reset */
8916 static void tg3_save_pci_state(struct tg3 *tp)
8918 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8921 /* Restore PCI state after chip reset */
8922 static void tg3_restore_pci_state(struct tg3 *tp)
8926 /* Re-enable indirect register accesses. */
8927 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8928 tp->misc_host_ctrl);
8930 /* Set MAX PCI retry to zero. */
8931 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8932 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8933 tg3_flag(tp, PCIX_MODE))
8934 val |= PCISTATE_RETRY_SAME_DMA;
8935 /* Allow reads and writes to the APE register and memory space. */
8936 if (tg3_flag(tp, ENABLE_APE))
8937 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8938 PCISTATE_ALLOW_APE_SHMEM_WR |
8939 PCISTATE_ALLOW_APE_PSPACE_WR;
8940 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8942 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8944 if (!tg3_flag(tp, PCI_EXPRESS)) {
8945 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8946 tp->pci_cacheline_sz);
8947 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8951 /* Make sure PCI-X relaxed ordering bit is clear. */
8952 if (tg3_flag(tp, PCIX_MODE)) {
8955 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8957 pcix_cmd &= ~PCI_X_CMD_ERO;
8958 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8962 if (tg3_flag(tp, 5780_CLASS)) {
8964 /* Chip reset on 5780 will reset MSI enable bit,
8965 * so need to restore it.
8967 if (tg3_flag(tp, USING_MSI)) {
8970 pci_read_config_word(tp->pdev,
8971 tp->msi_cap + PCI_MSI_FLAGS,
8973 pci_write_config_word(tp->pdev,
8974 tp->msi_cap + PCI_MSI_FLAGS,
8975 ctrl | PCI_MSI_FLAGS_ENABLE);
8976 val = tr32(MSGINT_MODE);
8977 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8982 static void tg3_override_clk(struct tg3 *tp)
8986 switch (tg3_asic_rev(tp)) {
8988 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8989 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8990 TG3_CPMU_MAC_ORIDE_ENABLE);
8995 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9003 static void tg3_restore_clk(struct tg3 *tp)
9007 switch (tg3_asic_rev(tp)) {
9009 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9010 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9011 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9016 val = tr32(TG3_CPMU_CLCK_ORIDE);
9017 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9025 /* tp->lock is held. */
9026 static int tg3_chip_reset(struct tg3 *tp)
9027 __releases(tp->lock)
9028 __acquires(tp->lock)
9031 void (*write_op)(struct tg3 *, u32, u32);
9034 if (!pci_device_is_present(tp->pdev))
9039 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9041 /* No matching tg3_nvram_unlock() after this because
9042 * chip reset below will undo the nvram lock.
9044 tp->nvram_lock_cnt = 0;
9046 /* GRC_MISC_CFG core clock reset will clear the memory
9047 * enable bit in PCI register 4 and the MSI enable bit
9048 * on some chips, so we save relevant registers here.
9050 tg3_save_pci_state(tp);
9052 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9053 tg3_flag(tp, 5755_PLUS))
9054 tw32(GRC_FASTBOOT_PC, 0);
9057 * We must avoid the readl() that normally takes place.
9058 * It locks machines, causes machine checks, and other
9059 * fun things. So, temporarily disable the 5701
9060 * hardware workaround, while we do the reset.
9062 write_op = tp->write32;
9063 if (write_op == tg3_write_flush_reg32)
9064 tp->write32 = tg3_write32;
9066 /* Prevent the irq handler from reading or writing PCI registers
9067 * during chip reset when the memory enable bit in the PCI command
9068 * register may be cleared. The chip does not generate interrupt
9069 * at this time, but the irq handler may still be called due to irq
9070 * sharing or irqpoll.
9072 tg3_flag_set(tp, CHIP_RESETTING);
9073 for (i = 0; i < tp->irq_cnt; i++) {
9074 struct tg3_napi *tnapi = &tp->napi[i];
9075 if (tnapi->hw_status) {
9076 tnapi->hw_status->status = 0;
9077 tnapi->hw_status->status_tag = 0;
9079 tnapi->last_tag = 0;
9080 tnapi->last_irq_tag = 0;
9084 tg3_full_unlock(tp);
9086 for (i = 0; i < tp->irq_cnt; i++)
9087 synchronize_irq(tp->napi[i].irq_vec);
9089 tg3_full_lock(tp, 0);
9091 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9092 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9093 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9097 val = GRC_MISC_CFG_CORECLK_RESET;
9099 if (tg3_flag(tp, PCI_EXPRESS)) {
9100 /* Force PCIe 1.0a mode */
9101 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9102 !tg3_flag(tp, 57765_PLUS) &&
9103 tr32(TG3_PCIE_PHY_TSTCTL) ==
9104 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9105 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9107 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9108 tw32(GRC_MISC_CFG, (1 << 29));
9113 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9114 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9115 tw32(GRC_VCPU_EXT_CTRL,
9116 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9119 /* Set the clock to the highest frequency to avoid timeouts. With link
9120 * aware mode, the clock speed could be slow and bootcode does not
9121 * complete within the expected time. Override the clock to allow the
9122 * bootcode to finish sooner and then restore it.
9124 tg3_override_clk(tp);
9126 /* Manage gphy power for all CPMU absent PCIe devices. */
9127 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9128 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9130 tw32(GRC_MISC_CFG, val);
9132 /* restore 5701 hardware bug workaround write method */
9133 tp->write32 = write_op;
9135 /* Unfortunately, we have to delay before the PCI read back.
9136 * Some 575X chips even will not respond to a PCI cfg access
9137 * when the reset command is given to the chip.
9139 * How do these hardware designers expect things to work
9140 * properly if the PCI write is posted for a long period
9141 * of time? It is always necessary to have some method by
9142 * which a register read back can occur to push the write
9143 * out which does the reset.
9145 * For most tg3 variants the trick below was working.
9150 /* Flush PCI posted writes. The normal MMIO registers
9151 * are inaccessible at this time so this is the only
9152 * way to make this reliably (actually, this is no longer
9153 * the case, see above). I tried to use indirect
9154 * register read/write but this upset some 5701 variants.
9156 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9160 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9163 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9167 /* Wait for link training to complete. */
9168 for (j = 0; j < 5000; j++)
9171 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9172 pci_write_config_dword(tp->pdev, 0xc4,
9173 cfg_val | (1 << 15));
9176 /* Clear the "no snoop" and "relaxed ordering" bits. */
9177 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9179 * Older PCIe devices only support the 128 byte
9180 * MPS setting. Enforce the restriction.
9182 if (!tg3_flag(tp, CPMU_PRESENT))
9183 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9184 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9186 /* Clear error status */
9187 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9188 PCI_EXP_DEVSTA_CED |
9189 PCI_EXP_DEVSTA_NFED |
9190 PCI_EXP_DEVSTA_FED |
9191 PCI_EXP_DEVSTA_URD);
9194 tg3_restore_pci_state(tp);
9196 tg3_flag_clear(tp, CHIP_RESETTING);
9197 tg3_flag_clear(tp, ERROR_PROCESSED);
9200 if (tg3_flag(tp, 5780_CLASS))
9201 val = tr32(MEMARB_MODE);
9202 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9204 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9206 tw32(0x5000, 0x400);
9209 if (tg3_flag(tp, IS_SSB_CORE)) {
9211 * BCM4785: In order to avoid repercussions from using
9212 * potentially defective internal ROM, stop the Rx RISC CPU,
9213 * which is not required.
9216 tg3_halt_cpu(tp, RX_CPU_BASE);
9219 err = tg3_poll_fw(tp);
9223 tw32(GRC_MODE, tp->grc_mode);
9225 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9228 tw32(0xc4, val | (1 << 15));
9231 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9232 tg3_asic_rev(tp) == ASIC_REV_5705) {
9233 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9234 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9235 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9236 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9239 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9240 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9242 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9243 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9248 tw32_f(MAC_MODE, val);
9251 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9255 if (tg3_flag(tp, PCI_EXPRESS) &&
9256 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9257 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9258 !tg3_flag(tp, 57765_PLUS)) {
9261 tw32(0x7c00, val | (1 << 25));
9264 tg3_restore_clk(tp);
9266 /* Reprobe ASF enable state. */
9267 tg3_flag_clear(tp, ENABLE_ASF);
9268 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9269 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9271 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9272 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9273 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9276 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9277 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9278 tg3_flag_set(tp, ENABLE_ASF);
9279 tp->last_event_jiffies = jiffies;
9280 if (tg3_flag(tp, 5750_PLUS))
9281 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9283 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9284 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9285 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9286 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9287 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9294 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9295 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9296 static void __tg3_set_rx_mode(struct net_device *);
9298 /* tp->lock is held. */
9299 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9305 tg3_write_sig_pre_reset(tp, kind);
9307 tg3_abort_hw(tp, silent);
9308 err = tg3_chip_reset(tp);
9310 __tg3_set_mac_addr(tp, false);
9312 tg3_write_sig_legacy(tp, kind);
9313 tg3_write_sig_post_reset(tp, kind);
9316 /* Save the stats across chip resets... */
9317 tg3_get_nstats(tp, &tp->net_stats_prev);
9318 tg3_get_estats(tp, &tp->estats_prev);
9320 /* And make sure the next sample is new data */
9321 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9327 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9329 struct tg3 *tp = netdev_priv(dev);
9330 struct sockaddr *addr = p;
9332 bool skip_mac_1 = false;
9334 if (!is_valid_ether_addr(addr->sa_data))
9335 return -EADDRNOTAVAIL;
9337 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9339 if (!netif_running(dev))
9342 if (tg3_flag(tp, ENABLE_ASF)) {
9343 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9345 addr0_high = tr32(MAC_ADDR_0_HIGH);
9346 addr0_low = tr32(MAC_ADDR_0_LOW);
9347 addr1_high = tr32(MAC_ADDR_1_HIGH);
9348 addr1_low = tr32(MAC_ADDR_1_LOW);
9350 /* Skip MAC addr 1 if ASF is using it. */
9351 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9352 !(addr1_high == 0 && addr1_low == 0))
9355 spin_lock_bh(&tp->lock);
9356 __tg3_set_mac_addr(tp, skip_mac_1);
9357 __tg3_set_rx_mode(dev);
9358 spin_unlock_bh(&tp->lock);
9363 /* tp->lock is held. */
9364 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9365 dma_addr_t mapping, u32 maxlen_flags,
9369 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9370 ((u64) mapping >> 32));
9372 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9373 ((u64) mapping & 0xffffffff));
9375 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9378 if (!tg3_flag(tp, 5705_PLUS))
9380 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9385 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9389 if (!tg3_flag(tp, ENABLE_TSS)) {
9390 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9391 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9392 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9394 tw32(HOSTCC_TXCOL_TICKS, 0);
9395 tw32(HOSTCC_TXMAX_FRAMES, 0);
9396 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9398 for (; i < tp->txq_cnt; i++) {
9401 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9402 tw32(reg, ec->tx_coalesce_usecs);
9403 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9404 tw32(reg, ec->tx_max_coalesced_frames);
9405 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9406 tw32(reg, ec->tx_max_coalesced_frames_irq);
9410 for (; i < tp->irq_max - 1; i++) {
9411 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9412 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9413 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9417 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9420 u32 limit = tp->rxq_cnt;
9422 if (!tg3_flag(tp, ENABLE_RSS)) {
9423 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9424 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9425 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9428 tw32(HOSTCC_RXCOL_TICKS, 0);
9429 tw32(HOSTCC_RXMAX_FRAMES, 0);
9430 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9433 for (; i < limit; i++) {
9436 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9437 tw32(reg, ec->rx_coalesce_usecs);
9438 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9439 tw32(reg, ec->rx_max_coalesced_frames);
9440 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9441 tw32(reg, ec->rx_max_coalesced_frames_irq);
9444 for (; i < tp->irq_max - 1; i++) {
9445 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9446 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9447 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9451 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9453 tg3_coal_tx_init(tp, ec);
9454 tg3_coal_rx_init(tp, ec);
9456 if (!tg3_flag(tp, 5705_PLUS)) {
9457 u32 val = ec->stats_block_coalesce_usecs;
9459 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9460 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9465 tw32(HOSTCC_STAT_COAL_TICKS, val);
9469 /* tp->lock is held. */
9470 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9474 /* Disable all transmit rings but the first. */
9475 if (!tg3_flag(tp, 5705_PLUS))
9476 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9477 else if (tg3_flag(tp, 5717_PLUS))
9478 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9479 else if (tg3_flag(tp, 57765_CLASS) ||
9480 tg3_asic_rev(tp) == ASIC_REV_5762)
9481 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9483 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9485 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9486 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9487 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9488 BDINFO_FLAGS_DISABLED);
9491 /* tp->lock is held. */
9492 static void tg3_tx_rcbs_init(struct tg3 *tp)
9495 u32 txrcb = NIC_SRAM_SEND_RCB;
9497 if (tg3_flag(tp, ENABLE_TSS))
9500 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9501 struct tg3_napi *tnapi = &tp->napi[i];
9503 if (!tnapi->tx_ring)
9506 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9507 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9508 NIC_SRAM_TX_BUFFER_DESC);
9512 /* tp->lock is held. */
9513 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9517 /* Disable all receive return rings but the first. */
9518 if (tg3_flag(tp, 5717_PLUS))
9519 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9520 else if (!tg3_flag(tp, 5705_PLUS))
9521 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9522 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9523 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9524 tg3_flag(tp, 57765_CLASS))
9525 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9527 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9529 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9530 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9531 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9532 BDINFO_FLAGS_DISABLED);
9535 /* tp->lock is held. */
9536 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9539 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9541 if (tg3_flag(tp, ENABLE_RSS))
9544 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9545 struct tg3_napi *tnapi = &tp->napi[i];
9550 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9551 (tp->rx_ret_ring_mask + 1) <<
9552 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9556 /* tp->lock is held. */
9557 static void tg3_rings_reset(struct tg3 *tp)
9561 struct tg3_napi *tnapi = &tp->napi[0];
9563 tg3_tx_rcbs_disable(tp);
9565 tg3_rx_ret_rcbs_disable(tp);
9567 /* Disable interrupts */
9568 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9569 tp->napi[0].chk_msi_cnt = 0;
9570 tp->napi[0].last_rx_cons = 0;
9571 tp->napi[0].last_tx_cons = 0;
9573 /* Zero mailbox registers. */
9574 if (tg3_flag(tp, SUPPORT_MSIX)) {
9575 for (i = 1; i < tp->irq_max; i++) {
9576 tp->napi[i].tx_prod = 0;
9577 tp->napi[i].tx_cons = 0;
9578 if (tg3_flag(tp, ENABLE_TSS))
9579 tw32_mailbox(tp->napi[i].prodmbox, 0);
9580 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9581 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9582 tp->napi[i].chk_msi_cnt = 0;
9583 tp->napi[i].last_rx_cons = 0;
9584 tp->napi[i].last_tx_cons = 0;
9586 if (!tg3_flag(tp, ENABLE_TSS))
9587 tw32_mailbox(tp->napi[0].prodmbox, 0);
9589 tp->napi[0].tx_prod = 0;
9590 tp->napi[0].tx_cons = 0;
9591 tw32_mailbox(tp->napi[0].prodmbox, 0);
9592 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9595 /* Make sure the NIC-based send BD rings are disabled. */
9596 if (!tg3_flag(tp, 5705_PLUS)) {
9597 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9598 for (i = 0; i < 16; i++)
9599 tw32_tx_mbox(mbox + i * 8, 0);
9602 /* Clear status block in ram. */
9603 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9605 /* Set status block DMA address */
9606 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9607 ((u64) tnapi->status_mapping >> 32));
9608 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9609 ((u64) tnapi->status_mapping & 0xffffffff));
9611 stblk = HOSTCC_STATBLCK_RING1;
9613 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9614 u64 mapping = (u64)tnapi->status_mapping;
9615 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9616 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9619 /* Clear status block in ram. */
9620 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9623 tg3_tx_rcbs_init(tp);
9624 tg3_rx_ret_rcbs_init(tp);
9627 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9629 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9631 if (!tg3_flag(tp, 5750_PLUS) ||
9632 tg3_flag(tp, 5780_CLASS) ||
9633 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9634 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9635 tg3_flag(tp, 57765_PLUS))
9636 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9637 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9638 tg3_asic_rev(tp) == ASIC_REV_5787)
9639 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9641 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9643 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9644 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9646 val = min(nic_rep_thresh, host_rep_thresh);
9647 tw32(RCVBDI_STD_THRESH, val);
9649 if (tg3_flag(tp, 57765_PLUS))
9650 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9652 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9655 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9657 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9659 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9660 tw32(RCVBDI_JUMBO_THRESH, val);
9662 if (tg3_flag(tp, 57765_PLUS))
9663 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9666 static inline u32 calc_crc(unsigned char *buf, int len)
9674 for (j = 0; j < len; j++) {
9677 for (k = 0; k < 8; k++) {
9690 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9692 /* accept or reject all multicast frames */
9693 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9694 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9695 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9696 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9699 static void __tg3_set_rx_mode(struct net_device *dev)
9701 struct tg3 *tp = netdev_priv(dev);
9704 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9705 RX_MODE_KEEP_VLAN_TAG);
9707 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9708 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9711 if (!tg3_flag(tp, ENABLE_ASF))
9712 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9715 if (dev->flags & IFF_PROMISC) {
9716 /* Promiscuous mode. */
9717 rx_mode |= RX_MODE_PROMISC;
9718 } else if (dev->flags & IFF_ALLMULTI) {
9719 /* Accept all multicast. */
9720 tg3_set_multi(tp, 1);
9721 } else if (netdev_mc_empty(dev)) {
9722 /* Reject all multicast. */
9723 tg3_set_multi(tp, 0);
9725 /* Accept one or more multicast(s). */
9726 struct netdev_hw_addr *ha;
9727 u32 mc_filter[4] = { 0, };
9732 netdev_for_each_mc_addr(ha, dev) {
9733 crc = calc_crc(ha->addr, ETH_ALEN);
9735 regidx = (bit & 0x60) >> 5;
9737 mc_filter[regidx] |= (1 << bit);
9740 tw32(MAC_HASH_REG_0, mc_filter[0]);
9741 tw32(MAC_HASH_REG_1, mc_filter[1]);
9742 tw32(MAC_HASH_REG_2, mc_filter[2]);
9743 tw32(MAC_HASH_REG_3, mc_filter[3]);
9746 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9747 rx_mode |= RX_MODE_PROMISC;
9748 } else if (!(dev->flags & IFF_PROMISC)) {
9749 /* Add all entries into to the mac addr filter list */
9751 struct netdev_hw_addr *ha;
9753 netdev_for_each_uc_addr(ha, dev) {
9754 __tg3_set_one_mac_addr(tp, ha->addr,
9755 i + TG3_UCAST_ADDR_IDX(tp));
9760 if (rx_mode != tp->rx_mode) {
9761 tp->rx_mode = rx_mode;
9762 tw32_f(MAC_RX_MODE, rx_mode);
9767 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9771 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9772 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9775 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9779 if (!tg3_flag(tp, SUPPORT_MSIX))
9782 if (tp->rxq_cnt == 1) {
9783 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9787 /* Validate table against current IRQ count */
9788 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9789 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9793 if (i != TG3_RSS_INDIR_TBL_SIZE)
9794 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9797 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9800 u32 reg = MAC_RSS_INDIR_TBL_0;
9802 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9803 u32 val = tp->rss_ind_tbl[i];
9805 for (; i % 8; i++) {
9807 val |= tp->rss_ind_tbl[i];
9814 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9816 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9817 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9819 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9822 /* tp->lock is held. */
9823 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9825 u32 val, rdmac_mode;
9827 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9829 tg3_disable_ints(tp);
9833 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9835 if (tg3_flag(tp, INIT_COMPLETE))
9836 tg3_abort_hw(tp, 1);
9838 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9839 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9840 tg3_phy_pull_config(tp);
9841 tg3_eee_pull_config(tp, NULL);
9842 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9845 /* Enable MAC control of LPI */
9846 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9852 err = tg3_chip_reset(tp);
9856 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9858 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9859 val = tr32(TG3_CPMU_CTRL);
9860 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9861 tw32(TG3_CPMU_CTRL, val);
9863 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9864 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9865 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9866 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9868 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9869 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9870 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9871 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9873 val = tr32(TG3_CPMU_HST_ACC);
9874 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9875 val |= CPMU_HST_ACC_MACCLK_6_25;
9876 tw32(TG3_CPMU_HST_ACC, val);
9879 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9880 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9881 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9882 PCIE_PWR_MGMT_L1_THRESH_4MS;
9883 tw32(PCIE_PWR_MGMT_THRESH, val);
9885 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9886 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9888 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9890 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9891 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9894 if (tg3_flag(tp, L1PLLPD_EN)) {
9895 u32 grc_mode = tr32(GRC_MODE);
9897 /* Access the lower 1K of PL PCIE block registers. */
9898 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9899 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9901 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9902 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9903 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9905 tw32(GRC_MODE, grc_mode);
9908 if (tg3_flag(tp, 57765_CLASS)) {
9909 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9910 u32 grc_mode = tr32(GRC_MODE);
9912 /* Access the lower 1K of PL PCIE block registers. */
9913 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9914 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9916 val = tr32(TG3_PCIE_TLDLPL_PORT +
9917 TG3_PCIE_PL_LO_PHYCTL5);
9918 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9919 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9921 tw32(GRC_MODE, grc_mode);
9924 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9927 /* Fix transmit hangs */
9928 val = tr32(TG3_CPMU_PADRNG_CTL);
9929 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9930 tw32(TG3_CPMU_PADRNG_CTL, val);
9932 grc_mode = tr32(GRC_MODE);
9934 /* Access the lower 1K of DL PCIE block registers. */
9935 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9936 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9938 val = tr32(TG3_PCIE_TLDLPL_PORT +
9939 TG3_PCIE_DL_LO_FTSMAX);
9940 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9941 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9942 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9944 tw32(GRC_MODE, grc_mode);
9947 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9948 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9949 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9950 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9953 /* This works around an issue with Athlon chipsets on
9954 * B3 tigon3 silicon. This bit has no effect on any
9955 * other revision. But do not set this on PCI Express
9956 * chips and don't even touch the clocks if the CPMU is present.
9958 if (!tg3_flag(tp, CPMU_PRESENT)) {
9959 if (!tg3_flag(tp, PCI_EXPRESS))
9960 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9961 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9964 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9965 tg3_flag(tp, PCIX_MODE)) {
9966 val = tr32(TG3PCI_PCISTATE);
9967 val |= PCISTATE_RETRY_SAME_DMA;
9968 tw32(TG3PCI_PCISTATE, val);
9971 if (tg3_flag(tp, ENABLE_APE)) {
9972 /* Allow reads and writes to the
9973 * APE register and memory space.
9975 val = tr32(TG3PCI_PCISTATE);
9976 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9977 PCISTATE_ALLOW_APE_SHMEM_WR |
9978 PCISTATE_ALLOW_APE_PSPACE_WR;
9979 tw32(TG3PCI_PCISTATE, val);
9982 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9983 /* Enable some hw fixes. */
9984 val = tr32(TG3PCI_MSI_DATA);
9985 val |= (1 << 26) | (1 << 28) | (1 << 29);
9986 tw32(TG3PCI_MSI_DATA, val);
9989 /* Descriptor ring init may make accesses to the
9990 * NIC SRAM area to setup the TX descriptors, so we
9991 * can only do this after the hardware has been
9992 * successfully reset.
9994 err = tg3_init_rings(tp);
9998 if (tg3_flag(tp, 57765_PLUS)) {
9999 val = tr32(TG3PCI_DMA_RW_CTRL) &
10000 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
10001 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
10002 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
10003 if (!tg3_flag(tp, 57765_CLASS) &&
10004 tg3_asic_rev(tp) != ASIC_REV_5717 &&
10005 tg3_asic_rev(tp) != ASIC_REV_5762)
10006 val |= DMA_RWCTRL_TAGGED_STAT_WA;
10007 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
10008 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
10009 tg3_asic_rev(tp) != ASIC_REV_5761) {
10010 /* This value is determined during the probe time DMA
10011 * engine test, tg3_test_dma.
10013 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10016 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10017 GRC_MODE_4X_NIC_SEND_RINGS |
10018 GRC_MODE_NO_TX_PHDR_CSUM |
10019 GRC_MODE_NO_RX_PHDR_CSUM);
10020 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10022 /* Pseudo-header checksum is done by hardware logic and not
10023 * the offload processers, so make the chip do the pseudo-
10024 * header checksums on receive. For transmit it is more
10025 * convenient to do the pseudo-header checksum in software
10026 * as Linux does that on transmit for us in all cases.
10028 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10030 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10032 tw32(TG3_RX_PTP_CTL,
10033 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10035 if (tg3_flag(tp, PTP_CAPABLE))
10036 val |= GRC_MODE_TIME_SYNC_ENABLE;
10038 tw32(GRC_MODE, tp->grc_mode | val);
10040 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10041 val = tr32(GRC_MISC_CFG);
10043 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10044 tw32(GRC_MISC_CFG, val);
10046 /* Initialize MBUF/DESC pool. */
10047 if (tg3_flag(tp, 5750_PLUS)) {
10049 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10050 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10051 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10052 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10054 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10055 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10056 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10057 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10060 fw_len = tp->fw_len;
10061 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10062 tw32(BUFMGR_MB_POOL_ADDR,
10063 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10064 tw32(BUFMGR_MB_POOL_SIZE,
10065 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10068 if (tp->dev->mtu <= ETH_DATA_LEN) {
10069 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10070 tp->bufmgr_config.mbuf_read_dma_low_water);
10071 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10072 tp->bufmgr_config.mbuf_mac_rx_low_water);
10073 tw32(BUFMGR_MB_HIGH_WATER,
10074 tp->bufmgr_config.mbuf_high_water);
10076 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10077 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10078 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10079 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10080 tw32(BUFMGR_MB_HIGH_WATER,
10081 tp->bufmgr_config.mbuf_high_water_jumbo);
10083 tw32(BUFMGR_DMA_LOW_WATER,
10084 tp->bufmgr_config.dma_low_water);
10085 tw32(BUFMGR_DMA_HIGH_WATER,
10086 tp->bufmgr_config.dma_high_water);
10088 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10089 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10090 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10091 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10092 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10093 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10094 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10095 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10096 tw32(BUFMGR_MODE, val);
10097 for (i = 0; i < 2000; i++) {
10098 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10103 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10107 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10108 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10110 tg3_setup_rxbd_thresholds(tp);
10112 /* Initialize TG3_BDINFO's at:
10113 * RCVDBDI_STD_BD: standard eth size rx ring
10114 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10115 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10118 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10119 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10120 * ring attribute flags
10121 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10123 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10124 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10126 * The size of each ring is fixed in the firmware, but the location is
10129 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10130 ((u64) tpr->rx_std_mapping >> 32));
10131 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10132 ((u64) tpr->rx_std_mapping & 0xffffffff));
10133 if (!tg3_flag(tp, 5717_PLUS))
10134 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10135 NIC_SRAM_RX_BUFFER_DESC);
10137 /* Disable the mini ring */
10138 if (!tg3_flag(tp, 5705_PLUS))
10139 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10140 BDINFO_FLAGS_DISABLED);
10142 /* Program the jumbo buffer descriptor ring control
10143 * blocks on those devices that have them.
10145 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10146 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10148 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10149 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10150 ((u64) tpr->rx_jmb_mapping >> 32));
10151 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10152 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10153 val = TG3_RX_JMB_RING_SIZE(tp) <<
10154 BDINFO_FLAGS_MAXLEN_SHIFT;
10155 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10156 val | BDINFO_FLAGS_USE_EXT_RECV);
10157 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10158 tg3_flag(tp, 57765_CLASS) ||
10159 tg3_asic_rev(tp) == ASIC_REV_5762)
10160 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10161 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10163 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10164 BDINFO_FLAGS_DISABLED);
10167 if (tg3_flag(tp, 57765_PLUS)) {
10168 val = TG3_RX_STD_RING_SIZE(tp);
10169 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10170 val |= (TG3_RX_STD_DMA_SZ << 2);
10172 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10174 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10176 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10178 tpr->rx_std_prod_idx = tp->rx_pending;
10179 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10181 tpr->rx_jmb_prod_idx =
10182 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10183 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10185 tg3_rings_reset(tp);
10187 /* Initialize MAC address and backoff seed. */
10188 __tg3_set_mac_addr(tp, false);
10190 /* MTU + ethernet header + FCS + optional VLAN tag */
10191 tw32(MAC_RX_MTU_SIZE,
10192 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10194 /* The slot time is changed by tg3_setup_phy if we
10195 * run at gigabit with half duplex.
10197 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10198 (6 << TX_LENGTHS_IPG_SHIFT) |
10199 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10201 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10202 tg3_asic_rev(tp) == ASIC_REV_5762)
10203 val |= tr32(MAC_TX_LENGTHS) &
10204 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10205 TX_LENGTHS_CNT_DWN_VAL_MSK);
10207 tw32(MAC_TX_LENGTHS, val);
10209 /* Receive rules. */
10210 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10211 tw32(RCVLPC_CONFIG, 0x0181);
10213 /* Calculate RDMAC_MODE setting early, we need it to determine
10214 * the RCVLPC_STATE_ENABLE mask.
10216 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10217 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10218 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10219 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10220 RDMAC_MODE_LNGREAD_ENAB);
10222 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10223 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10225 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10226 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10227 tg3_asic_rev(tp) == ASIC_REV_57780)
10228 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10229 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10230 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10232 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10233 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10234 if (tg3_flag(tp, TSO_CAPABLE) &&
10235 tg3_asic_rev(tp) == ASIC_REV_5705) {
10236 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10237 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10238 !tg3_flag(tp, IS_5788)) {
10239 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10243 if (tg3_flag(tp, PCI_EXPRESS))
10244 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10246 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10248 if (tp->dev->mtu <= ETH_DATA_LEN) {
10249 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10250 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10254 if (tg3_flag(tp, HW_TSO_1) ||
10255 tg3_flag(tp, HW_TSO_2) ||
10256 tg3_flag(tp, HW_TSO_3))
10257 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10259 if (tg3_flag(tp, 57765_PLUS) ||
10260 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10261 tg3_asic_rev(tp) == ASIC_REV_57780)
10262 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10264 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10265 tg3_asic_rev(tp) == ASIC_REV_5762)
10266 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10268 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10269 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10270 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10271 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10272 tg3_flag(tp, 57765_PLUS)) {
10275 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10276 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10278 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10280 val = tr32(tgtreg);
10281 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10282 tg3_asic_rev(tp) == ASIC_REV_5762) {
10283 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10284 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10285 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10286 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10287 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10288 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10290 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10293 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10294 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10295 tg3_asic_rev(tp) == ASIC_REV_5762) {
10298 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10299 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10301 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10303 val = tr32(tgtreg);
10305 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10306 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10309 /* Receive/send statistics. */
10310 if (tg3_flag(tp, 5750_PLUS)) {
10311 val = tr32(RCVLPC_STATS_ENABLE);
10312 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10313 tw32(RCVLPC_STATS_ENABLE, val);
10314 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10315 tg3_flag(tp, TSO_CAPABLE)) {
10316 val = tr32(RCVLPC_STATS_ENABLE);
10317 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10318 tw32(RCVLPC_STATS_ENABLE, val);
10320 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10322 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10323 tw32(SNDDATAI_STATSENAB, 0xffffff);
10324 tw32(SNDDATAI_STATSCTRL,
10325 (SNDDATAI_SCTRL_ENABLE |
10326 SNDDATAI_SCTRL_FASTUPD));
10328 /* Setup host coalescing engine. */
10329 tw32(HOSTCC_MODE, 0);
10330 for (i = 0; i < 2000; i++) {
10331 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10336 __tg3_set_coalesce(tp, &tp->coal);
10338 if (!tg3_flag(tp, 5705_PLUS)) {
10339 /* Status/statistics block address. See tg3_timer,
10340 * the tg3_periodic_fetch_stats call there, and
10341 * tg3_get_stats to see how this works for 5705/5750 chips.
10343 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10344 ((u64) tp->stats_mapping >> 32));
10345 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10346 ((u64) tp->stats_mapping & 0xffffffff));
10347 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10349 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10351 /* Clear statistics and status block memory areas */
10352 for (i = NIC_SRAM_STATS_BLK;
10353 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10354 i += sizeof(u32)) {
10355 tg3_write_mem(tp, i, 0);
10360 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10362 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10363 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10364 if (!tg3_flag(tp, 5705_PLUS))
10365 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10367 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10368 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10369 /* reset to prevent losing 1st rx packet intermittently */
10370 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10374 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10375 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10376 MAC_MODE_FHDE_ENABLE;
10377 if (tg3_flag(tp, ENABLE_APE))
10378 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10379 if (!tg3_flag(tp, 5705_PLUS) &&
10380 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10381 tg3_asic_rev(tp) != ASIC_REV_5700)
10382 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10383 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10386 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10387 * If TG3_FLAG_IS_NIC is zero, we should read the
10388 * register to preserve the GPIO settings for LOMs. The GPIOs,
10389 * whether used as inputs or outputs, are set by boot code after
10392 if (!tg3_flag(tp, IS_NIC)) {
10395 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10396 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10397 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10399 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10400 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10401 GRC_LCLCTRL_GPIO_OUTPUT3;
10403 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10404 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10406 tp->grc_local_ctrl &= ~gpio_mask;
10407 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10409 /* GPIO1 must be driven high for eeprom write protect */
10410 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10411 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10412 GRC_LCLCTRL_GPIO_OUTPUT1);
10414 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10417 if (tg3_flag(tp, USING_MSIX)) {
10418 val = tr32(MSGINT_MODE);
10419 val |= MSGINT_MODE_ENABLE;
10420 if (tp->irq_cnt > 1)
10421 val |= MSGINT_MODE_MULTIVEC_EN;
10422 if (!tg3_flag(tp, 1SHOT_MSI))
10423 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10424 tw32(MSGINT_MODE, val);
10427 if (!tg3_flag(tp, 5705_PLUS)) {
10428 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10432 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10433 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10434 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10435 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10436 WDMAC_MODE_LNGREAD_ENAB);
10438 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10439 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10440 if (tg3_flag(tp, TSO_CAPABLE) &&
10441 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10442 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10444 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10445 !tg3_flag(tp, IS_5788)) {
10446 val |= WDMAC_MODE_RX_ACCEL;
10450 /* Enable host coalescing bug fix */
10451 if (tg3_flag(tp, 5755_PLUS))
10452 val |= WDMAC_MODE_STATUS_TAG_FIX;
10454 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10455 val |= WDMAC_MODE_BURST_ALL_DATA;
10457 tw32_f(WDMAC_MODE, val);
10460 if (tg3_flag(tp, PCIX_MODE)) {
10463 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10465 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10466 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10467 pcix_cmd |= PCI_X_CMD_READ_2K;
10468 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10469 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10470 pcix_cmd |= PCI_X_CMD_READ_2K;
10472 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10476 tw32_f(RDMAC_MODE, rdmac_mode);
10479 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10480 tg3_asic_rev(tp) == ASIC_REV_5720) {
10481 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10482 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10485 if (i < TG3_NUM_RDMA_CHANNELS) {
10486 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10487 val |= tg3_lso_rd_dma_workaround_bit(tp);
10488 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10489 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10493 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10494 if (!tg3_flag(tp, 5705_PLUS))
10495 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10497 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10498 tw32(SNDDATAC_MODE,
10499 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10501 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10503 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10504 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10505 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10506 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10507 val |= RCVDBDI_MODE_LRG_RING_SZ;
10508 tw32(RCVDBDI_MODE, val);
10509 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10510 if (tg3_flag(tp, HW_TSO_1) ||
10511 tg3_flag(tp, HW_TSO_2) ||
10512 tg3_flag(tp, HW_TSO_3))
10513 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10514 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10515 if (tg3_flag(tp, ENABLE_TSS))
10516 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10517 tw32(SNDBDI_MODE, val);
10518 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10520 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10521 err = tg3_load_5701_a0_firmware_fix(tp);
10526 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10527 /* Ignore any errors for the firmware download. If download
10528 * fails, the device will operate with EEE disabled
10530 tg3_load_57766_firmware(tp);
10533 if (tg3_flag(tp, TSO_CAPABLE)) {
10534 err = tg3_load_tso_firmware(tp);
10539 tp->tx_mode = TX_MODE_ENABLE;
10541 if (tg3_flag(tp, 5755_PLUS) ||
10542 tg3_asic_rev(tp) == ASIC_REV_5906)
10543 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10545 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10546 tg3_asic_rev(tp) == ASIC_REV_5762) {
10547 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10548 tp->tx_mode &= ~val;
10549 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10552 tw32_f(MAC_TX_MODE, tp->tx_mode);
10555 if (tg3_flag(tp, ENABLE_RSS)) {
10558 tg3_rss_write_indir_tbl(tp);
10560 netdev_rss_key_fill(rss_key, 10 * sizeof(u32));
10562 for (i = 0; i < 10 ; i++)
10563 tw32(MAC_RSS_HASH_KEY_0 + i*4, rss_key[i]);
10566 tp->rx_mode = RX_MODE_ENABLE;
10567 if (tg3_flag(tp, 5755_PLUS))
10568 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10570 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10571 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10573 if (tg3_flag(tp, ENABLE_RSS))
10574 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10575 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10576 RX_MODE_RSS_IPV6_HASH_EN |
10577 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10578 RX_MODE_RSS_IPV4_HASH_EN |
10579 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10581 tw32_f(MAC_RX_MODE, tp->rx_mode);
10584 tw32(MAC_LED_CTRL, tp->led_ctrl);
10586 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10587 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10588 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10591 tw32_f(MAC_RX_MODE, tp->rx_mode);
10594 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10595 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10596 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10597 /* Set drive transmission level to 1.2V */
10598 /* only if the signal pre-emphasis bit is not set */
10599 val = tr32(MAC_SERDES_CFG);
10602 tw32(MAC_SERDES_CFG, val);
10604 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10605 tw32(MAC_SERDES_CFG, 0x616000);
10608 /* Prevent chip from dropping frames when flow control
10611 if (tg3_flag(tp, 57765_CLASS))
10615 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10617 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10618 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10619 /* Use hardware link auto-negotiation */
10620 tg3_flag_set(tp, HW_AUTONEG);
10623 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10624 tg3_asic_rev(tp) == ASIC_REV_5714) {
10627 tmp = tr32(SERDES_RX_CTRL);
10628 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10629 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10630 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10631 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10634 if (!tg3_flag(tp, USE_PHYLIB)) {
10635 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10636 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10638 err = tg3_setup_phy(tp, false);
10642 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10643 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10646 /* Clear CRC stats. */
10647 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10648 tg3_writephy(tp, MII_TG3_TEST1,
10649 tmp | MII_TG3_TEST1_CRC_EN);
10650 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10655 __tg3_set_rx_mode(tp->dev);
10657 /* Initialize receive rules. */
10658 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10659 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10660 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10661 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10663 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10667 if (tg3_flag(tp, ENABLE_ASF))
10671 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10673 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10675 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10677 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10679 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10681 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10683 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10685 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10687 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10689 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10691 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10693 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10695 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10697 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10705 if (tg3_flag(tp, ENABLE_APE))
10706 /* Write our heartbeat update interval to APE. */
10707 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10708 APE_HOST_HEARTBEAT_INT_DISABLE);
10710 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10715 /* Called at device open time to get the chip ready for
10716 * packet processing. Invoked with tp->lock held.
10718 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10720 /* Chip may have been just powered on. If so, the boot code may still
10721 * be running initialization. Wait for it to finish to avoid races in
10722 * accessing the hardware.
10724 tg3_enable_register_access(tp);
10727 tg3_switch_clocks(tp);
10729 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10731 return tg3_reset_hw(tp, reset_phy);
10734 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10738 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10739 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10741 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10744 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10745 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10746 memset(ocir, 0, TG3_OCIR_LEN);
10750 /* sysfs attributes for hwmon */
10751 static ssize_t tg3_show_temp(struct device *dev,
10752 struct device_attribute *devattr, char *buf)
10754 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10755 struct tg3 *tp = dev_get_drvdata(dev);
10758 spin_lock_bh(&tp->lock);
10759 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10760 sizeof(temperature));
10761 spin_unlock_bh(&tp->lock);
10762 return sprintf(buf, "%u\n", temperature);
10766 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10767 TG3_TEMP_SENSOR_OFFSET);
10768 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10769 TG3_TEMP_CAUTION_OFFSET);
10770 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10771 TG3_TEMP_MAX_OFFSET);
10773 static struct attribute *tg3_attrs[] = {
10774 &sensor_dev_attr_temp1_input.dev_attr.attr,
10775 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10776 &sensor_dev_attr_temp1_max.dev_attr.attr,
10779 ATTRIBUTE_GROUPS(tg3);
10781 static void tg3_hwmon_close(struct tg3 *tp)
10783 if (tp->hwmon_dev) {
10784 hwmon_device_unregister(tp->hwmon_dev);
10785 tp->hwmon_dev = NULL;
10789 static void tg3_hwmon_open(struct tg3 *tp)
10793 struct pci_dev *pdev = tp->pdev;
10794 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10796 tg3_sd_scan_scratchpad(tp, ocirs);
10798 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10799 if (!ocirs[i].src_data_length)
10802 size += ocirs[i].src_hdr_length;
10803 size += ocirs[i].src_data_length;
10809 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10811 if (IS_ERR(tp->hwmon_dev)) {
10812 tp->hwmon_dev = NULL;
10813 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10818 #define TG3_STAT_ADD32(PSTAT, REG) \
10819 do { u32 __val = tr32(REG); \
10820 (PSTAT)->low += __val; \
10821 if ((PSTAT)->low < __val) \
10822 (PSTAT)->high += 1; \
10825 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10827 struct tg3_hw_stats *sp = tp->hw_stats;
10832 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10833 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10834 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10835 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10836 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10837 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10838 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10839 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10840 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10841 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10842 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10843 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10844 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10845 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10846 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10847 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10850 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10851 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10852 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10853 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10856 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10857 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10858 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10859 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10860 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10861 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10862 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10863 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10864 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10865 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10866 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10867 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10868 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10869 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10871 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10872 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10873 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10874 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10875 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10876 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10878 u32 val = tr32(HOSTCC_FLOW_ATTN);
10879 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10881 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10882 sp->rx_discards.low += val;
10883 if (sp->rx_discards.low < val)
10884 sp->rx_discards.high += 1;
10886 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10888 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10891 static void tg3_chk_missed_msi(struct tg3 *tp)
10895 for (i = 0; i < tp->irq_cnt; i++) {
10896 struct tg3_napi *tnapi = &tp->napi[i];
10898 if (tg3_has_work(tnapi)) {
10899 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10900 tnapi->last_tx_cons == tnapi->tx_cons) {
10901 if (tnapi->chk_msi_cnt < 1) {
10902 tnapi->chk_msi_cnt++;
10908 tnapi->chk_msi_cnt = 0;
10909 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10910 tnapi->last_tx_cons = tnapi->tx_cons;
10914 static void tg3_timer(unsigned long __opaque)
10916 struct tg3 *tp = (struct tg3 *) __opaque;
10918 spin_lock(&tp->lock);
10920 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) {
10921 spin_unlock(&tp->lock);
10922 goto restart_timer;
10925 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10926 tg3_flag(tp, 57765_CLASS))
10927 tg3_chk_missed_msi(tp);
10929 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10930 /* BCM4785: Flush posted writes from GbE to host memory. */
10934 if (!tg3_flag(tp, TAGGED_STATUS)) {
10935 /* All of this garbage is because when using non-tagged
10936 * IRQ status the mailbox/status_block protocol the chip
10937 * uses with the cpu is race prone.
10939 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10940 tw32(GRC_LOCAL_CTRL,
10941 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10943 tw32(HOSTCC_MODE, tp->coalesce_mode |
10944 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10947 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10948 spin_unlock(&tp->lock);
10949 tg3_reset_task_schedule(tp);
10950 goto restart_timer;
10954 /* This part only runs once per second. */
10955 if (!--tp->timer_counter) {
10956 if (tg3_flag(tp, 5705_PLUS))
10957 tg3_periodic_fetch_stats(tp);
10959 if (tp->setlpicnt && !--tp->setlpicnt)
10960 tg3_phy_eee_enable(tp);
10962 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10966 mac_stat = tr32(MAC_STATUS);
10969 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10970 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10972 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10976 tg3_setup_phy(tp, false);
10977 } else if (tg3_flag(tp, POLL_SERDES)) {
10978 u32 mac_stat = tr32(MAC_STATUS);
10979 int need_setup = 0;
10982 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10985 if (!tp->link_up &&
10986 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10987 MAC_STATUS_SIGNAL_DET))) {
10991 if (!tp->serdes_counter) {
10994 ~MAC_MODE_PORT_MODE_MASK));
10996 tw32_f(MAC_MODE, tp->mac_mode);
10999 tg3_setup_phy(tp, false);
11001 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
11002 tg3_flag(tp, 5780_CLASS)) {
11003 tg3_serdes_parallel_detect(tp);
11004 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
11005 u32 cpmu = tr32(TG3_CPMU_STATUS);
11006 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
11007 TG3_CPMU_STATUS_LINK_MASK);
11009 if (link_up != tp->link_up)
11010 tg3_setup_phy(tp, false);
11013 tp->timer_counter = tp->timer_multiplier;
11016 /* Heartbeat is only sent once every 2 seconds.
11018 * The heartbeat is to tell the ASF firmware that the host
11019 * driver is still alive. In the event that the OS crashes,
11020 * ASF needs to reset the hardware to free up the FIFO space
11021 * that may be filled with rx packets destined for the host.
11022 * If the FIFO is full, ASF will no longer function properly.
11024 * Unintended resets have been reported on real time kernels
11025 * where the timer doesn't run on time. Netpoll will also have
11028 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11029 * to check the ring condition when the heartbeat is expiring
11030 * before doing the reset. This will prevent most unintended
11033 if (!--tp->asf_counter) {
11034 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11035 tg3_wait_for_event_ack(tp);
11037 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11038 FWCMD_NICDRV_ALIVE3);
11039 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11040 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11041 TG3_FW_UPDATE_TIMEOUT_SEC);
11043 tg3_generate_fw_event(tp);
11045 tp->asf_counter = tp->asf_multiplier;
11048 spin_unlock(&tp->lock);
11051 tp->timer.expires = jiffies + tp->timer_offset;
11052 add_timer(&tp->timer);
11055 static void tg3_timer_init(struct tg3 *tp)
11057 if (tg3_flag(tp, TAGGED_STATUS) &&
11058 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11059 !tg3_flag(tp, 57765_CLASS))
11060 tp->timer_offset = HZ;
11062 tp->timer_offset = HZ / 10;
11064 BUG_ON(tp->timer_offset > HZ);
11066 tp->timer_multiplier = (HZ / tp->timer_offset);
11067 tp->asf_multiplier = (HZ / tp->timer_offset) *
11068 TG3_FW_UPDATE_FREQ_SEC;
11070 init_timer(&tp->timer);
11071 tp->timer.data = (unsigned long) tp;
11072 tp->timer.function = tg3_timer;
11075 static void tg3_timer_start(struct tg3 *tp)
11077 tp->asf_counter = tp->asf_multiplier;
11078 tp->timer_counter = tp->timer_multiplier;
11080 tp->timer.expires = jiffies + tp->timer_offset;
11081 add_timer(&tp->timer);
11084 static void tg3_timer_stop(struct tg3 *tp)
11086 del_timer_sync(&tp->timer);
11089 /* Restart hardware after configuration changes, self-test, etc.
11090 * Invoked with tp->lock held.
11092 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11093 __releases(tp->lock)
11094 __acquires(tp->lock)
11098 err = tg3_init_hw(tp, reset_phy);
11100 netdev_err(tp->dev,
11101 "Failed to re-initialize device, aborting\n");
11102 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11103 tg3_full_unlock(tp);
11104 tg3_timer_stop(tp);
11106 tg3_napi_enable(tp);
11107 dev_close(tp->dev);
11108 tg3_full_lock(tp, 0);
11113 static void tg3_reset_task(struct work_struct *work)
11115 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11119 tg3_full_lock(tp, 0);
11121 if (!netif_running(tp->dev)) {
11122 tg3_flag_clear(tp, RESET_TASK_PENDING);
11123 tg3_full_unlock(tp);
11128 tg3_full_unlock(tp);
11132 tg3_netif_stop(tp);
11134 tg3_full_lock(tp, 1);
11136 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11137 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11138 tp->write32_rx_mbox = tg3_write_flush_reg32;
11139 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11140 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11143 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11144 err = tg3_init_hw(tp, true);
11148 tg3_netif_start(tp);
11151 tg3_full_unlock(tp);
11156 tg3_flag_clear(tp, RESET_TASK_PENDING);
11160 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11163 unsigned long flags;
11165 struct tg3_napi *tnapi = &tp->napi[irq_num];
11167 if (tp->irq_cnt == 1)
11168 name = tp->dev->name;
11170 name = &tnapi->irq_lbl[0];
11171 if (tnapi->tx_buffers && tnapi->rx_rcb)
11172 snprintf(name, IFNAMSIZ,
11173 "%s-txrx-%d", tp->dev->name, irq_num);
11174 else if (tnapi->tx_buffers)
11175 snprintf(name, IFNAMSIZ,
11176 "%s-tx-%d", tp->dev->name, irq_num);
11177 else if (tnapi->rx_rcb)
11178 snprintf(name, IFNAMSIZ,
11179 "%s-rx-%d", tp->dev->name, irq_num);
11181 snprintf(name, IFNAMSIZ,
11182 "%s-%d", tp->dev->name, irq_num);
11183 name[IFNAMSIZ-1] = 0;
11186 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11188 if (tg3_flag(tp, 1SHOT_MSI))
11189 fn = tg3_msi_1shot;
11192 fn = tg3_interrupt;
11193 if (tg3_flag(tp, TAGGED_STATUS))
11194 fn = tg3_interrupt_tagged;
11195 flags = IRQF_SHARED;
11198 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11201 static int tg3_test_interrupt(struct tg3 *tp)
11203 struct tg3_napi *tnapi = &tp->napi[0];
11204 struct net_device *dev = tp->dev;
11205 int err, i, intr_ok = 0;
11208 if (!netif_running(dev))
11211 tg3_disable_ints(tp);
11213 free_irq(tnapi->irq_vec, tnapi);
11216 * Turn off MSI one shot mode. Otherwise this test has no
11217 * observable way to know whether the interrupt was delivered.
11219 if (tg3_flag(tp, 57765_PLUS)) {
11220 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11221 tw32(MSGINT_MODE, val);
11224 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11225 IRQF_SHARED, dev->name, tnapi);
11229 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11230 tg3_enable_ints(tp);
11232 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11235 for (i = 0; i < 5; i++) {
11236 u32 int_mbox, misc_host_ctrl;
11238 int_mbox = tr32_mailbox(tnapi->int_mbox);
11239 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11241 if ((int_mbox != 0) ||
11242 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11247 if (tg3_flag(tp, 57765_PLUS) &&
11248 tnapi->hw_status->status_tag != tnapi->last_tag)
11249 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11254 tg3_disable_ints(tp);
11256 free_irq(tnapi->irq_vec, tnapi);
11258 err = tg3_request_irq(tp, 0);
11264 /* Reenable MSI one shot mode. */
11265 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11266 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11267 tw32(MSGINT_MODE, val);
11275 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11276 * successfully restored
11278 static int tg3_test_msi(struct tg3 *tp)
11283 if (!tg3_flag(tp, USING_MSI))
11286 /* Turn off SERR reporting in case MSI terminates with Master
11289 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11290 pci_write_config_word(tp->pdev, PCI_COMMAND,
11291 pci_cmd & ~PCI_COMMAND_SERR);
11293 err = tg3_test_interrupt(tp);
11295 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11300 /* other failures */
11304 /* MSI test failed, go back to INTx mode */
11305 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11306 "to INTx mode. Please report this failure to the PCI "
11307 "maintainer and include system chipset information\n");
11309 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11311 pci_disable_msi(tp->pdev);
11313 tg3_flag_clear(tp, USING_MSI);
11314 tp->napi[0].irq_vec = tp->pdev->irq;
11316 err = tg3_request_irq(tp, 0);
11320 /* Need to reset the chip because the MSI cycle may have terminated
11321 * with Master Abort.
11323 tg3_full_lock(tp, 1);
11325 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11326 err = tg3_init_hw(tp, true);
11328 tg3_full_unlock(tp);
11331 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11336 static int tg3_request_firmware(struct tg3 *tp)
11338 const struct tg3_firmware_hdr *fw_hdr;
11340 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11341 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11346 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11348 /* Firmware blob starts with version numbers, followed by
11349 * start address and _full_ length including BSS sections
11350 * (which must be longer than the actual data, of course
11353 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11354 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11355 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11356 tp->fw_len, tp->fw_needed);
11357 release_firmware(tp->fw);
11362 /* We no longer need firmware; we have it. */
11363 tp->fw_needed = NULL;
11367 static u32 tg3_irq_count(struct tg3 *tp)
11369 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11372 /* We want as many rx rings enabled as there are cpus.
11373 * In multiqueue MSI-X mode, the first MSI-X vector
11374 * only deals with link interrupts, etc, so we add
11375 * one to the number of vectors we are requesting.
11377 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11383 static bool tg3_enable_msix(struct tg3 *tp)
11386 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11388 tp->txq_cnt = tp->txq_req;
11389 tp->rxq_cnt = tp->rxq_req;
11391 tp->rxq_cnt = netif_get_num_default_rss_queues();
11392 if (tp->rxq_cnt > tp->rxq_max)
11393 tp->rxq_cnt = tp->rxq_max;
11395 /* Disable multiple TX rings by default. Simple round-robin hardware
11396 * scheduling of the TX rings can cause starvation of rings with
11397 * small packets when other rings have TSO or jumbo packets.
11402 tp->irq_cnt = tg3_irq_count(tp);
11404 for (i = 0; i < tp->irq_max; i++) {
11405 msix_ent[i].entry = i;
11406 msix_ent[i].vector = 0;
11409 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11412 } else if (rc < tp->irq_cnt) {
11413 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11416 tp->rxq_cnt = max(rc - 1, 1);
11418 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11421 for (i = 0; i < tp->irq_max; i++)
11422 tp->napi[i].irq_vec = msix_ent[i].vector;
11424 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11425 pci_disable_msix(tp->pdev);
11429 if (tp->irq_cnt == 1)
11432 tg3_flag_set(tp, ENABLE_RSS);
11434 if (tp->txq_cnt > 1)
11435 tg3_flag_set(tp, ENABLE_TSS);
11437 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11442 static void tg3_ints_init(struct tg3 *tp)
11444 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11445 !tg3_flag(tp, TAGGED_STATUS)) {
11446 /* All MSI supporting chips should support tagged
11447 * status. Assert that this is the case.
11449 netdev_warn(tp->dev,
11450 "MSI without TAGGED_STATUS? Not using MSI\n");
11454 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11455 tg3_flag_set(tp, USING_MSIX);
11456 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11457 tg3_flag_set(tp, USING_MSI);
11459 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11460 u32 msi_mode = tr32(MSGINT_MODE);
11461 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11462 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11463 if (!tg3_flag(tp, 1SHOT_MSI))
11464 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11465 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11468 if (!tg3_flag(tp, USING_MSIX)) {
11470 tp->napi[0].irq_vec = tp->pdev->irq;
11473 if (tp->irq_cnt == 1) {
11476 netif_set_real_num_tx_queues(tp->dev, 1);
11477 netif_set_real_num_rx_queues(tp->dev, 1);
11481 static void tg3_ints_fini(struct tg3 *tp)
11483 if (tg3_flag(tp, USING_MSIX))
11484 pci_disable_msix(tp->pdev);
11485 else if (tg3_flag(tp, USING_MSI))
11486 pci_disable_msi(tp->pdev);
11487 tg3_flag_clear(tp, USING_MSI);
11488 tg3_flag_clear(tp, USING_MSIX);
11489 tg3_flag_clear(tp, ENABLE_RSS);
11490 tg3_flag_clear(tp, ENABLE_TSS);
11493 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11496 struct net_device *dev = tp->dev;
11500 * Setup interrupts first so we know how
11501 * many NAPI resources to allocate
11505 tg3_rss_check_indir_tbl(tp);
11507 /* The placement of this call is tied
11508 * to the setup and use of Host TX descriptors.
11510 err = tg3_alloc_consistent(tp);
11512 goto out_ints_fini;
11516 tg3_napi_enable(tp);
11518 for (i = 0; i < tp->irq_cnt; i++) {
11519 struct tg3_napi *tnapi = &tp->napi[i];
11520 err = tg3_request_irq(tp, i);
11522 for (i--; i >= 0; i--) {
11523 tnapi = &tp->napi[i];
11524 free_irq(tnapi->irq_vec, tnapi);
11526 goto out_napi_fini;
11530 tg3_full_lock(tp, 0);
11533 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11535 err = tg3_init_hw(tp, reset_phy);
11537 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11538 tg3_free_rings(tp);
11541 tg3_full_unlock(tp);
11546 if (test_irq && tg3_flag(tp, USING_MSI)) {
11547 err = tg3_test_msi(tp);
11550 tg3_full_lock(tp, 0);
11551 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11552 tg3_free_rings(tp);
11553 tg3_full_unlock(tp);
11555 goto out_napi_fini;
11558 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11559 u32 val = tr32(PCIE_TRANSACTION_CFG);
11561 tw32(PCIE_TRANSACTION_CFG,
11562 val | PCIE_TRANS_CFG_1SHOT_MSI);
11568 tg3_hwmon_open(tp);
11570 tg3_full_lock(tp, 0);
11572 tg3_timer_start(tp);
11573 tg3_flag_set(tp, INIT_COMPLETE);
11574 tg3_enable_ints(tp);
11576 tg3_ptp_resume(tp);
11578 tg3_full_unlock(tp);
11580 netif_tx_start_all_queues(dev);
11583 * Reset loopback feature if it was turned on while the device was down
11584 * make sure that it's installed properly now.
11586 if (dev->features & NETIF_F_LOOPBACK)
11587 tg3_set_loopback(dev, dev->features);
11592 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11593 struct tg3_napi *tnapi = &tp->napi[i];
11594 free_irq(tnapi->irq_vec, tnapi);
11598 tg3_napi_disable(tp);
11600 tg3_free_consistent(tp);
11608 static void tg3_stop(struct tg3 *tp)
11612 tg3_reset_task_cancel(tp);
11613 tg3_netif_stop(tp);
11615 tg3_timer_stop(tp);
11617 tg3_hwmon_close(tp);
11621 tg3_full_lock(tp, 1);
11623 tg3_disable_ints(tp);
11625 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11626 tg3_free_rings(tp);
11627 tg3_flag_clear(tp, INIT_COMPLETE);
11629 tg3_full_unlock(tp);
11631 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11632 struct tg3_napi *tnapi = &tp->napi[i];
11633 free_irq(tnapi->irq_vec, tnapi);
11640 tg3_free_consistent(tp);
11643 static int tg3_open(struct net_device *dev)
11645 struct tg3 *tp = netdev_priv(dev);
11648 if (tp->pcierr_recovery) {
11649 netdev_err(dev, "Failed to open device. PCI error recovery "
11654 if (tp->fw_needed) {
11655 err = tg3_request_firmware(tp);
11656 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11658 netdev_warn(tp->dev, "EEE capability disabled\n");
11659 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11660 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11661 netdev_warn(tp->dev, "EEE capability restored\n");
11662 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11664 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11668 netdev_warn(tp->dev, "TSO capability disabled\n");
11669 tg3_flag_clear(tp, TSO_CAPABLE);
11670 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11671 netdev_notice(tp->dev, "TSO capability restored\n");
11672 tg3_flag_set(tp, TSO_CAPABLE);
11676 tg3_carrier_off(tp);
11678 err = tg3_power_up(tp);
11682 tg3_full_lock(tp, 0);
11684 tg3_disable_ints(tp);
11685 tg3_flag_clear(tp, INIT_COMPLETE);
11687 tg3_full_unlock(tp);
11689 err = tg3_start(tp,
11690 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11693 tg3_frob_aux_power(tp, false);
11694 pci_set_power_state(tp->pdev, PCI_D3hot);
11700 static int tg3_close(struct net_device *dev)
11702 struct tg3 *tp = netdev_priv(dev);
11704 if (tp->pcierr_recovery) {
11705 netdev_err(dev, "Failed to close device. PCI error recovery "
11712 /* Clear stats across close / open calls */
11713 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11714 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11716 if (pci_device_is_present(tp->pdev)) {
11717 tg3_power_down_prepare(tp);
11719 tg3_carrier_off(tp);
11724 static inline u64 get_stat64(tg3_stat64_t *val)
11726 return ((u64)val->high << 32) | ((u64)val->low);
11729 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11731 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11733 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11734 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11735 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11738 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11739 tg3_writephy(tp, MII_TG3_TEST1,
11740 val | MII_TG3_TEST1_CRC_EN);
11741 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11745 tp->phy_crc_errors += val;
11747 return tp->phy_crc_errors;
11750 return get_stat64(&hw_stats->rx_fcs_errors);
11753 #define ESTAT_ADD(member) \
11754 estats->member = old_estats->member + \
11755 get_stat64(&hw_stats->member)
11757 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11759 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11760 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11762 ESTAT_ADD(rx_octets);
11763 ESTAT_ADD(rx_fragments);
11764 ESTAT_ADD(rx_ucast_packets);
11765 ESTAT_ADD(rx_mcast_packets);
11766 ESTAT_ADD(rx_bcast_packets);
11767 ESTAT_ADD(rx_fcs_errors);
11768 ESTAT_ADD(rx_align_errors);
11769 ESTAT_ADD(rx_xon_pause_rcvd);
11770 ESTAT_ADD(rx_xoff_pause_rcvd);
11771 ESTAT_ADD(rx_mac_ctrl_rcvd);
11772 ESTAT_ADD(rx_xoff_entered);
11773 ESTAT_ADD(rx_frame_too_long_errors);
11774 ESTAT_ADD(rx_jabbers);
11775 ESTAT_ADD(rx_undersize_packets);
11776 ESTAT_ADD(rx_in_length_errors);
11777 ESTAT_ADD(rx_out_length_errors);
11778 ESTAT_ADD(rx_64_or_less_octet_packets);
11779 ESTAT_ADD(rx_65_to_127_octet_packets);
11780 ESTAT_ADD(rx_128_to_255_octet_packets);
11781 ESTAT_ADD(rx_256_to_511_octet_packets);
11782 ESTAT_ADD(rx_512_to_1023_octet_packets);
11783 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11784 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11785 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11786 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11787 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11789 ESTAT_ADD(tx_octets);
11790 ESTAT_ADD(tx_collisions);
11791 ESTAT_ADD(tx_xon_sent);
11792 ESTAT_ADD(tx_xoff_sent);
11793 ESTAT_ADD(tx_flow_control);
11794 ESTAT_ADD(tx_mac_errors);
11795 ESTAT_ADD(tx_single_collisions);
11796 ESTAT_ADD(tx_mult_collisions);
11797 ESTAT_ADD(tx_deferred);
11798 ESTAT_ADD(tx_excessive_collisions);
11799 ESTAT_ADD(tx_late_collisions);
11800 ESTAT_ADD(tx_collide_2times);
11801 ESTAT_ADD(tx_collide_3times);
11802 ESTAT_ADD(tx_collide_4times);
11803 ESTAT_ADD(tx_collide_5times);
11804 ESTAT_ADD(tx_collide_6times);
11805 ESTAT_ADD(tx_collide_7times);
11806 ESTAT_ADD(tx_collide_8times);
11807 ESTAT_ADD(tx_collide_9times);
11808 ESTAT_ADD(tx_collide_10times);
11809 ESTAT_ADD(tx_collide_11times);
11810 ESTAT_ADD(tx_collide_12times);
11811 ESTAT_ADD(tx_collide_13times);
11812 ESTAT_ADD(tx_collide_14times);
11813 ESTAT_ADD(tx_collide_15times);
11814 ESTAT_ADD(tx_ucast_packets);
11815 ESTAT_ADD(tx_mcast_packets);
11816 ESTAT_ADD(tx_bcast_packets);
11817 ESTAT_ADD(tx_carrier_sense_errors);
11818 ESTAT_ADD(tx_discards);
11819 ESTAT_ADD(tx_errors);
11821 ESTAT_ADD(dma_writeq_full);
11822 ESTAT_ADD(dma_write_prioq_full);
11823 ESTAT_ADD(rxbds_empty);
11824 ESTAT_ADD(rx_discards);
11825 ESTAT_ADD(rx_errors);
11826 ESTAT_ADD(rx_threshold_hit);
11828 ESTAT_ADD(dma_readq_full);
11829 ESTAT_ADD(dma_read_prioq_full);
11830 ESTAT_ADD(tx_comp_queue_full);
11832 ESTAT_ADD(ring_set_send_prod_index);
11833 ESTAT_ADD(ring_status_update);
11834 ESTAT_ADD(nic_irqs);
11835 ESTAT_ADD(nic_avoided_irqs);
11836 ESTAT_ADD(nic_tx_threshold_hit);
11838 ESTAT_ADD(mbuf_lwm_thresh_hit);
11841 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11843 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11844 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11846 stats->rx_packets = old_stats->rx_packets +
11847 get_stat64(&hw_stats->rx_ucast_packets) +
11848 get_stat64(&hw_stats->rx_mcast_packets) +
11849 get_stat64(&hw_stats->rx_bcast_packets);
11851 stats->tx_packets = old_stats->tx_packets +
11852 get_stat64(&hw_stats->tx_ucast_packets) +
11853 get_stat64(&hw_stats->tx_mcast_packets) +
11854 get_stat64(&hw_stats->tx_bcast_packets);
11856 stats->rx_bytes = old_stats->rx_bytes +
11857 get_stat64(&hw_stats->rx_octets);
11858 stats->tx_bytes = old_stats->tx_bytes +
11859 get_stat64(&hw_stats->tx_octets);
11861 stats->rx_errors = old_stats->rx_errors +
11862 get_stat64(&hw_stats->rx_errors);
11863 stats->tx_errors = old_stats->tx_errors +
11864 get_stat64(&hw_stats->tx_errors) +
11865 get_stat64(&hw_stats->tx_mac_errors) +
11866 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11867 get_stat64(&hw_stats->tx_discards);
11869 stats->multicast = old_stats->multicast +
11870 get_stat64(&hw_stats->rx_mcast_packets);
11871 stats->collisions = old_stats->collisions +
11872 get_stat64(&hw_stats->tx_collisions);
11874 stats->rx_length_errors = old_stats->rx_length_errors +
11875 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11876 get_stat64(&hw_stats->rx_undersize_packets);
11878 stats->rx_frame_errors = old_stats->rx_frame_errors +
11879 get_stat64(&hw_stats->rx_align_errors);
11880 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11881 get_stat64(&hw_stats->tx_discards);
11882 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11883 get_stat64(&hw_stats->tx_carrier_sense_errors);
11885 stats->rx_crc_errors = old_stats->rx_crc_errors +
11886 tg3_calc_crc_errors(tp);
11888 stats->rx_missed_errors = old_stats->rx_missed_errors +
11889 get_stat64(&hw_stats->rx_discards);
11891 stats->rx_dropped = tp->rx_dropped;
11892 stats->tx_dropped = tp->tx_dropped;
11895 static int tg3_get_regs_len(struct net_device *dev)
11897 return TG3_REG_BLK_SIZE;
11900 static void tg3_get_regs(struct net_device *dev,
11901 struct ethtool_regs *regs, void *_p)
11903 struct tg3 *tp = netdev_priv(dev);
11907 memset(_p, 0, TG3_REG_BLK_SIZE);
11909 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11912 tg3_full_lock(tp, 0);
11914 tg3_dump_legacy_regs(tp, (u32 *)_p);
11916 tg3_full_unlock(tp);
11919 static int tg3_get_eeprom_len(struct net_device *dev)
11921 struct tg3 *tp = netdev_priv(dev);
11923 return tp->nvram_size;
11926 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11928 struct tg3 *tp = netdev_priv(dev);
11929 int ret, cpmu_restore = 0;
11931 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11934 if (tg3_flag(tp, NO_NVRAM))
11937 offset = eeprom->offset;
11941 eeprom->magic = TG3_EEPROM_MAGIC;
11943 /* Override clock, link aware and link idle modes */
11944 if (tg3_flag(tp, CPMU_PRESENT)) {
11945 cpmu_val = tr32(TG3_CPMU_CTRL);
11946 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11947 CPMU_CTRL_LINK_IDLE_MODE)) {
11948 tw32(TG3_CPMU_CTRL, cpmu_val &
11949 ~(CPMU_CTRL_LINK_AWARE_MODE |
11950 CPMU_CTRL_LINK_IDLE_MODE));
11954 tg3_override_clk(tp);
11957 /* adjustments to start on required 4 byte boundary */
11958 b_offset = offset & 3;
11959 b_count = 4 - b_offset;
11960 if (b_count > len) {
11961 /* i.e. offset=1 len=2 */
11964 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11967 memcpy(data, ((char *)&val) + b_offset, b_count);
11970 eeprom->len += b_count;
11973 /* read bytes up to the last 4 byte boundary */
11974 pd = &data[eeprom->len];
11975 for (i = 0; i < (len - (len & 3)); i += 4) {
11976 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11983 memcpy(pd + i, &val, 4);
11984 if (need_resched()) {
11985 if (signal_pending(current)) {
11996 /* read last bytes not ending on 4 byte boundary */
11997 pd = &data[eeprom->len];
11999 b_offset = offset + len - b_count;
12000 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12003 memcpy(pd, &val, b_count);
12004 eeprom->len += b_count;
12009 /* Restore clock, link aware and link idle modes */
12010 tg3_restore_clk(tp);
12012 tw32(TG3_CPMU_CTRL, cpmu_val);
12017 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12019 struct tg3 *tp = netdev_priv(dev);
12021 u32 offset, len, b_offset, odd_len;
12025 if (tg3_flag(tp, NO_NVRAM) ||
12026 eeprom->magic != TG3_EEPROM_MAGIC)
12029 offset = eeprom->offset;
12032 if ((b_offset = (offset & 3))) {
12033 /* adjustments to start on required 4 byte boundary */
12034 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12045 /* adjustments to end on required 4 byte boundary */
12047 len = (len + 3) & ~3;
12048 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12054 if (b_offset || odd_len) {
12055 buf = kmalloc(len, GFP_KERNEL);
12059 memcpy(buf, &start, 4);
12061 memcpy(buf+len-4, &end, 4);
12062 memcpy(buf + b_offset, data, eeprom->len);
12065 ret = tg3_nvram_write_block(tp, offset, len, buf);
12073 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12075 struct tg3 *tp = netdev_priv(dev);
12077 if (tg3_flag(tp, USE_PHYLIB)) {
12078 struct phy_device *phydev;
12079 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12081 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12082 return phy_ethtool_gset(phydev, cmd);
12085 cmd->supported = (SUPPORTED_Autoneg);
12087 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12088 cmd->supported |= (SUPPORTED_1000baseT_Half |
12089 SUPPORTED_1000baseT_Full);
12091 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12092 cmd->supported |= (SUPPORTED_100baseT_Half |
12093 SUPPORTED_100baseT_Full |
12094 SUPPORTED_10baseT_Half |
12095 SUPPORTED_10baseT_Full |
12097 cmd->port = PORT_TP;
12099 cmd->supported |= SUPPORTED_FIBRE;
12100 cmd->port = PORT_FIBRE;
12103 cmd->advertising = tp->link_config.advertising;
12104 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12105 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12106 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12107 cmd->advertising |= ADVERTISED_Pause;
12109 cmd->advertising |= ADVERTISED_Pause |
12110 ADVERTISED_Asym_Pause;
12112 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12113 cmd->advertising |= ADVERTISED_Asym_Pause;
12116 if (netif_running(dev) && tp->link_up) {
12117 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12118 cmd->duplex = tp->link_config.active_duplex;
12119 cmd->lp_advertising = tp->link_config.rmt_adv;
12120 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12121 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12122 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12124 cmd->eth_tp_mdix = ETH_TP_MDI;
12127 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12128 cmd->duplex = DUPLEX_UNKNOWN;
12129 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12131 cmd->phy_address = tp->phy_addr;
12132 cmd->transceiver = XCVR_INTERNAL;
12133 cmd->autoneg = tp->link_config.autoneg;
12139 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12141 struct tg3 *tp = netdev_priv(dev);
12142 u32 speed = ethtool_cmd_speed(cmd);
12144 if (tg3_flag(tp, USE_PHYLIB)) {
12145 struct phy_device *phydev;
12146 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12148 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12149 return phy_ethtool_sset(phydev, cmd);
12152 if (cmd->autoneg != AUTONEG_ENABLE &&
12153 cmd->autoneg != AUTONEG_DISABLE)
12156 if (cmd->autoneg == AUTONEG_DISABLE &&
12157 cmd->duplex != DUPLEX_FULL &&
12158 cmd->duplex != DUPLEX_HALF)
12161 if (cmd->autoneg == AUTONEG_ENABLE) {
12162 u32 mask = ADVERTISED_Autoneg |
12164 ADVERTISED_Asym_Pause;
12166 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12167 mask |= ADVERTISED_1000baseT_Half |
12168 ADVERTISED_1000baseT_Full;
12170 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12171 mask |= ADVERTISED_100baseT_Half |
12172 ADVERTISED_100baseT_Full |
12173 ADVERTISED_10baseT_Half |
12174 ADVERTISED_10baseT_Full |
12177 mask |= ADVERTISED_FIBRE;
12179 if (cmd->advertising & ~mask)
12182 mask &= (ADVERTISED_1000baseT_Half |
12183 ADVERTISED_1000baseT_Full |
12184 ADVERTISED_100baseT_Half |
12185 ADVERTISED_100baseT_Full |
12186 ADVERTISED_10baseT_Half |
12187 ADVERTISED_10baseT_Full);
12189 cmd->advertising &= mask;
12191 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12192 if (speed != SPEED_1000)
12195 if (cmd->duplex != DUPLEX_FULL)
12198 if (speed != SPEED_100 &&
12204 tg3_full_lock(tp, 0);
12206 tp->link_config.autoneg = cmd->autoneg;
12207 if (cmd->autoneg == AUTONEG_ENABLE) {
12208 tp->link_config.advertising = (cmd->advertising |
12209 ADVERTISED_Autoneg);
12210 tp->link_config.speed = SPEED_UNKNOWN;
12211 tp->link_config.duplex = DUPLEX_UNKNOWN;
12213 tp->link_config.advertising = 0;
12214 tp->link_config.speed = speed;
12215 tp->link_config.duplex = cmd->duplex;
12218 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12220 tg3_warn_mgmt_link_flap(tp);
12222 if (netif_running(dev))
12223 tg3_setup_phy(tp, true);
12225 tg3_full_unlock(tp);
12230 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12232 struct tg3 *tp = netdev_priv(dev);
12234 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12235 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12236 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12237 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12240 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12242 struct tg3 *tp = netdev_priv(dev);
12244 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12245 wol->supported = WAKE_MAGIC;
12247 wol->supported = 0;
12249 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12250 wol->wolopts = WAKE_MAGIC;
12251 memset(&wol->sopass, 0, sizeof(wol->sopass));
12254 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12256 struct tg3 *tp = netdev_priv(dev);
12257 struct device *dp = &tp->pdev->dev;
12259 if (wol->wolopts & ~WAKE_MAGIC)
12261 if ((wol->wolopts & WAKE_MAGIC) &&
12262 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12265 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12267 if (device_may_wakeup(dp))
12268 tg3_flag_set(tp, WOL_ENABLE);
12270 tg3_flag_clear(tp, WOL_ENABLE);
12275 static u32 tg3_get_msglevel(struct net_device *dev)
12277 struct tg3 *tp = netdev_priv(dev);
12278 return tp->msg_enable;
12281 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12283 struct tg3 *tp = netdev_priv(dev);
12284 tp->msg_enable = value;
12287 static int tg3_nway_reset(struct net_device *dev)
12289 struct tg3 *tp = netdev_priv(dev);
12292 if (!netif_running(dev))
12295 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12298 tg3_warn_mgmt_link_flap(tp);
12300 if (tg3_flag(tp, USE_PHYLIB)) {
12301 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12303 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12307 spin_lock_bh(&tp->lock);
12309 tg3_readphy(tp, MII_BMCR, &bmcr);
12310 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12311 ((bmcr & BMCR_ANENABLE) ||
12312 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12313 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12317 spin_unlock_bh(&tp->lock);
12323 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12325 struct tg3 *tp = netdev_priv(dev);
12327 ering->rx_max_pending = tp->rx_std_ring_mask;
12328 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12329 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12331 ering->rx_jumbo_max_pending = 0;
12333 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12335 ering->rx_pending = tp->rx_pending;
12336 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12337 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12339 ering->rx_jumbo_pending = 0;
12341 ering->tx_pending = tp->napi[0].tx_pending;
12344 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12346 struct tg3 *tp = netdev_priv(dev);
12347 int i, irq_sync = 0, err = 0;
12349 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12350 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12351 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12352 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12353 (tg3_flag(tp, TSO_BUG) &&
12354 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12357 if (netif_running(dev)) {
12359 tg3_netif_stop(tp);
12363 tg3_full_lock(tp, irq_sync);
12365 tp->rx_pending = ering->rx_pending;
12367 if (tg3_flag(tp, MAX_RXPEND_64) &&
12368 tp->rx_pending > 63)
12369 tp->rx_pending = 63;
12371 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12372 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12374 for (i = 0; i < tp->irq_max; i++)
12375 tp->napi[i].tx_pending = ering->tx_pending;
12377 if (netif_running(dev)) {
12378 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12379 err = tg3_restart_hw(tp, false);
12381 tg3_netif_start(tp);
12384 tg3_full_unlock(tp);
12386 if (irq_sync && !err)
12392 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12394 struct tg3 *tp = netdev_priv(dev);
12396 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12398 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12399 epause->rx_pause = 1;
12401 epause->rx_pause = 0;
12403 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12404 epause->tx_pause = 1;
12406 epause->tx_pause = 0;
12409 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12411 struct tg3 *tp = netdev_priv(dev);
12414 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12415 tg3_warn_mgmt_link_flap(tp);
12417 if (tg3_flag(tp, USE_PHYLIB)) {
12419 struct phy_device *phydev;
12421 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12423 if (!(phydev->supported & SUPPORTED_Pause) ||
12424 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12425 (epause->rx_pause != epause->tx_pause)))
12428 tp->link_config.flowctrl = 0;
12429 if (epause->rx_pause) {
12430 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12432 if (epause->tx_pause) {
12433 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12434 newadv = ADVERTISED_Pause;
12436 newadv = ADVERTISED_Pause |
12437 ADVERTISED_Asym_Pause;
12438 } else if (epause->tx_pause) {
12439 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12440 newadv = ADVERTISED_Asym_Pause;
12444 if (epause->autoneg)
12445 tg3_flag_set(tp, PAUSE_AUTONEG);
12447 tg3_flag_clear(tp, PAUSE_AUTONEG);
12449 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12450 u32 oldadv = phydev->advertising &
12451 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12452 if (oldadv != newadv) {
12453 phydev->advertising &=
12454 ~(ADVERTISED_Pause |
12455 ADVERTISED_Asym_Pause);
12456 phydev->advertising |= newadv;
12457 if (phydev->autoneg) {
12459 * Always renegotiate the link to
12460 * inform our link partner of our
12461 * flow control settings, even if the
12462 * flow control is forced. Let
12463 * tg3_adjust_link() do the final
12464 * flow control setup.
12466 return phy_start_aneg(phydev);
12470 if (!epause->autoneg)
12471 tg3_setup_flow_control(tp, 0, 0);
12473 tp->link_config.advertising &=
12474 ~(ADVERTISED_Pause |
12475 ADVERTISED_Asym_Pause);
12476 tp->link_config.advertising |= newadv;
12481 if (netif_running(dev)) {
12482 tg3_netif_stop(tp);
12486 tg3_full_lock(tp, irq_sync);
12488 if (epause->autoneg)
12489 tg3_flag_set(tp, PAUSE_AUTONEG);
12491 tg3_flag_clear(tp, PAUSE_AUTONEG);
12492 if (epause->rx_pause)
12493 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12495 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12496 if (epause->tx_pause)
12497 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12499 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12501 if (netif_running(dev)) {
12502 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12503 err = tg3_restart_hw(tp, false);
12505 tg3_netif_start(tp);
12508 tg3_full_unlock(tp);
12511 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12516 static int tg3_get_sset_count(struct net_device *dev, int sset)
12520 return TG3_NUM_TEST;
12522 return TG3_NUM_STATS;
12524 return -EOPNOTSUPP;
12528 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12529 u32 *rules __always_unused)
12531 struct tg3 *tp = netdev_priv(dev);
12533 if (!tg3_flag(tp, SUPPORT_MSIX))
12534 return -EOPNOTSUPP;
12536 switch (info->cmd) {
12537 case ETHTOOL_GRXRINGS:
12538 if (netif_running(tp->dev))
12539 info->data = tp->rxq_cnt;
12541 info->data = num_online_cpus();
12542 if (info->data > TG3_RSS_MAX_NUM_QS)
12543 info->data = TG3_RSS_MAX_NUM_QS;
12546 /* The first interrupt vector only
12547 * handles link interrupts.
12553 return -EOPNOTSUPP;
12557 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12560 struct tg3 *tp = netdev_priv(dev);
12562 if (tg3_flag(tp, SUPPORT_MSIX))
12563 size = TG3_RSS_INDIR_TBL_SIZE;
12568 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, u8 *hfunc)
12570 struct tg3 *tp = netdev_priv(dev);
12574 *hfunc = ETH_RSS_HASH_TOP;
12578 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12579 indir[i] = tp->rss_ind_tbl[i];
12584 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key,
12587 struct tg3 *tp = netdev_priv(dev);
12590 /* We require at least one supported parameter to be changed and no
12591 * change in any of the unsupported parameters
12594 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
12595 return -EOPNOTSUPP;
12600 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12601 tp->rss_ind_tbl[i] = indir[i];
12603 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12606 /* It is legal to write the indirection
12607 * table while the device is running.
12609 tg3_full_lock(tp, 0);
12610 tg3_rss_write_indir_tbl(tp);
12611 tg3_full_unlock(tp);
12616 static void tg3_get_channels(struct net_device *dev,
12617 struct ethtool_channels *channel)
12619 struct tg3 *tp = netdev_priv(dev);
12620 u32 deflt_qs = netif_get_num_default_rss_queues();
12622 channel->max_rx = tp->rxq_max;
12623 channel->max_tx = tp->txq_max;
12625 if (netif_running(dev)) {
12626 channel->rx_count = tp->rxq_cnt;
12627 channel->tx_count = tp->txq_cnt;
12630 channel->rx_count = tp->rxq_req;
12632 channel->rx_count = min(deflt_qs, tp->rxq_max);
12635 channel->tx_count = tp->txq_req;
12637 channel->tx_count = min(deflt_qs, tp->txq_max);
12641 static int tg3_set_channels(struct net_device *dev,
12642 struct ethtool_channels *channel)
12644 struct tg3 *tp = netdev_priv(dev);
12646 if (!tg3_flag(tp, SUPPORT_MSIX))
12647 return -EOPNOTSUPP;
12649 if (channel->rx_count > tp->rxq_max ||
12650 channel->tx_count > tp->txq_max)
12653 tp->rxq_req = channel->rx_count;
12654 tp->txq_req = channel->tx_count;
12656 if (!netif_running(dev))
12661 tg3_carrier_off(tp);
12663 tg3_start(tp, true, false, false);
12668 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12670 switch (stringset) {
12672 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12675 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12678 WARN_ON(1); /* we need a WARN() */
12683 static int tg3_set_phys_id(struct net_device *dev,
12684 enum ethtool_phys_id_state state)
12686 struct tg3 *tp = netdev_priv(dev);
12688 if (!netif_running(tp->dev))
12692 case ETHTOOL_ID_ACTIVE:
12693 return 1; /* cycle on/off once per second */
12695 case ETHTOOL_ID_ON:
12696 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12697 LED_CTRL_1000MBPS_ON |
12698 LED_CTRL_100MBPS_ON |
12699 LED_CTRL_10MBPS_ON |
12700 LED_CTRL_TRAFFIC_OVERRIDE |
12701 LED_CTRL_TRAFFIC_BLINK |
12702 LED_CTRL_TRAFFIC_LED);
12705 case ETHTOOL_ID_OFF:
12706 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12707 LED_CTRL_TRAFFIC_OVERRIDE);
12710 case ETHTOOL_ID_INACTIVE:
12711 tw32(MAC_LED_CTRL, tp->led_ctrl);
12718 static void tg3_get_ethtool_stats(struct net_device *dev,
12719 struct ethtool_stats *estats, u64 *tmp_stats)
12721 struct tg3 *tp = netdev_priv(dev);
12724 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12726 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12729 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12733 u32 offset = 0, len = 0;
12736 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12739 if (magic == TG3_EEPROM_MAGIC) {
12740 for (offset = TG3_NVM_DIR_START;
12741 offset < TG3_NVM_DIR_END;
12742 offset += TG3_NVM_DIRENT_SIZE) {
12743 if (tg3_nvram_read(tp, offset, &val))
12746 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12747 TG3_NVM_DIRTYPE_EXTVPD)
12751 if (offset != TG3_NVM_DIR_END) {
12752 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12753 if (tg3_nvram_read(tp, offset + 4, &offset))
12756 offset = tg3_nvram_logical_addr(tp, offset);
12760 if (!offset || !len) {
12761 offset = TG3_NVM_VPD_OFF;
12762 len = TG3_NVM_VPD_LEN;
12765 buf = kmalloc(len, GFP_KERNEL);
12769 if (magic == TG3_EEPROM_MAGIC) {
12770 for (i = 0; i < len; i += 4) {
12771 /* The data is in little-endian format in NVRAM.
12772 * Use the big-endian read routines to preserve
12773 * the byte order as it exists in NVRAM.
12775 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12781 unsigned int pos = 0;
12783 ptr = (u8 *)&buf[0];
12784 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12785 cnt = pci_read_vpd(tp->pdev, pos,
12787 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12805 #define NVRAM_TEST_SIZE 0x100
12806 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12807 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12808 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12809 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12810 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12811 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12812 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12813 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12815 static int tg3_test_nvram(struct tg3 *tp)
12817 u32 csum, magic, len;
12819 int i, j, k, err = 0, size;
12821 if (tg3_flag(tp, NO_NVRAM))
12824 if (tg3_nvram_read(tp, 0, &magic) != 0)
12827 if (magic == TG3_EEPROM_MAGIC)
12828 size = NVRAM_TEST_SIZE;
12829 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12830 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12831 TG3_EEPROM_SB_FORMAT_1) {
12832 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12833 case TG3_EEPROM_SB_REVISION_0:
12834 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12836 case TG3_EEPROM_SB_REVISION_2:
12837 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12839 case TG3_EEPROM_SB_REVISION_3:
12840 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12842 case TG3_EEPROM_SB_REVISION_4:
12843 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12845 case TG3_EEPROM_SB_REVISION_5:
12846 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12848 case TG3_EEPROM_SB_REVISION_6:
12849 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12856 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12857 size = NVRAM_SELFBOOT_HW_SIZE;
12861 buf = kmalloc(size, GFP_KERNEL);
12866 for (i = 0, j = 0; i < size; i += 4, j++) {
12867 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12874 /* Selfboot format */
12875 magic = be32_to_cpu(buf[0]);
12876 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12877 TG3_EEPROM_MAGIC_FW) {
12878 u8 *buf8 = (u8 *) buf, csum8 = 0;
12880 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12881 TG3_EEPROM_SB_REVISION_2) {
12882 /* For rev 2, the csum doesn't include the MBA. */
12883 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12885 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12888 for (i = 0; i < size; i++)
12901 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12902 TG3_EEPROM_MAGIC_HW) {
12903 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12904 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12905 u8 *buf8 = (u8 *) buf;
12907 /* Separate the parity bits and the data bytes. */
12908 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12909 if ((i == 0) || (i == 8)) {
12913 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12914 parity[k++] = buf8[i] & msk;
12916 } else if (i == 16) {
12920 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12921 parity[k++] = buf8[i] & msk;
12924 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12925 parity[k++] = buf8[i] & msk;
12928 data[j++] = buf8[i];
12932 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12933 u8 hw8 = hweight8(data[i]);
12935 if ((hw8 & 0x1) && parity[i])
12937 else if (!(hw8 & 0x1) && !parity[i])
12946 /* Bootstrap checksum at offset 0x10 */
12947 csum = calc_crc((unsigned char *) buf, 0x10);
12948 if (csum != le32_to_cpu(buf[0x10/4]))
12951 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12952 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12953 if (csum != le32_to_cpu(buf[0xfc/4]))
12958 buf = tg3_vpd_readblock(tp, &len);
12962 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12964 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12968 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12971 i += PCI_VPD_LRDT_TAG_SIZE;
12972 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12973 PCI_VPD_RO_KEYWORD_CHKSUM);
12977 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12979 for (i = 0; i <= j; i++)
12980 csum8 += ((u8 *)buf)[i];
12994 #define TG3_SERDES_TIMEOUT_SEC 2
12995 #define TG3_COPPER_TIMEOUT_SEC 6
12997 static int tg3_test_link(struct tg3 *tp)
13001 if (!netif_running(tp->dev))
13004 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
13005 max = TG3_SERDES_TIMEOUT_SEC;
13007 max = TG3_COPPER_TIMEOUT_SEC;
13009 for (i = 0; i < max; i++) {
13013 if (msleep_interruptible(1000))
13020 /* Only test the commonly used registers */
13021 static int tg3_test_registers(struct tg3 *tp)
13023 int i, is_5705, is_5750;
13024 u32 offset, read_mask, write_mask, val, save_val, read_val;
13028 #define TG3_FL_5705 0x1
13029 #define TG3_FL_NOT_5705 0x2
13030 #define TG3_FL_NOT_5788 0x4
13031 #define TG3_FL_NOT_5750 0x8
13035 /* MAC Control Registers */
13036 { MAC_MODE, TG3_FL_NOT_5705,
13037 0x00000000, 0x00ef6f8c },
13038 { MAC_MODE, TG3_FL_5705,
13039 0x00000000, 0x01ef6b8c },
13040 { MAC_STATUS, TG3_FL_NOT_5705,
13041 0x03800107, 0x00000000 },
13042 { MAC_STATUS, TG3_FL_5705,
13043 0x03800100, 0x00000000 },
13044 { MAC_ADDR_0_HIGH, 0x0000,
13045 0x00000000, 0x0000ffff },
13046 { MAC_ADDR_0_LOW, 0x0000,
13047 0x00000000, 0xffffffff },
13048 { MAC_RX_MTU_SIZE, 0x0000,
13049 0x00000000, 0x0000ffff },
13050 { MAC_TX_MODE, 0x0000,
13051 0x00000000, 0x00000070 },
13052 { MAC_TX_LENGTHS, 0x0000,
13053 0x00000000, 0x00003fff },
13054 { MAC_RX_MODE, TG3_FL_NOT_5705,
13055 0x00000000, 0x000007fc },
13056 { MAC_RX_MODE, TG3_FL_5705,
13057 0x00000000, 0x000007dc },
13058 { MAC_HASH_REG_0, 0x0000,
13059 0x00000000, 0xffffffff },
13060 { MAC_HASH_REG_1, 0x0000,
13061 0x00000000, 0xffffffff },
13062 { MAC_HASH_REG_2, 0x0000,
13063 0x00000000, 0xffffffff },
13064 { MAC_HASH_REG_3, 0x0000,
13065 0x00000000, 0xffffffff },
13067 /* Receive Data and Receive BD Initiator Control Registers. */
13068 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13069 0x00000000, 0xffffffff },
13070 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13071 0x00000000, 0xffffffff },
13072 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13073 0x00000000, 0x00000003 },
13074 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13075 0x00000000, 0xffffffff },
13076 { RCVDBDI_STD_BD+0, 0x0000,
13077 0x00000000, 0xffffffff },
13078 { RCVDBDI_STD_BD+4, 0x0000,
13079 0x00000000, 0xffffffff },
13080 { RCVDBDI_STD_BD+8, 0x0000,
13081 0x00000000, 0xffff0002 },
13082 { RCVDBDI_STD_BD+0xc, 0x0000,
13083 0x00000000, 0xffffffff },
13085 /* Receive BD Initiator Control Registers. */
13086 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13087 0x00000000, 0xffffffff },
13088 { RCVBDI_STD_THRESH, TG3_FL_5705,
13089 0x00000000, 0x000003ff },
13090 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13091 0x00000000, 0xffffffff },
13093 /* Host Coalescing Control Registers. */
13094 { HOSTCC_MODE, TG3_FL_NOT_5705,
13095 0x00000000, 0x00000004 },
13096 { HOSTCC_MODE, TG3_FL_5705,
13097 0x00000000, 0x000000f6 },
13098 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13099 0x00000000, 0xffffffff },
13100 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13101 0x00000000, 0x000003ff },
13102 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13103 0x00000000, 0xffffffff },
13104 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13105 0x00000000, 0x000003ff },
13106 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13107 0x00000000, 0xffffffff },
13108 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13109 0x00000000, 0x000000ff },
13110 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13111 0x00000000, 0xffffffff },
13112 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13113 0x00000000, 0x000000ff },
13114 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13115 0x00000000, 0xffffffff },
13116 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13117 0x00000000, 0xffffffff },
13118 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13119 0x00000000, 0xffffffff },
13120 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13121 0x00000000, 0x000000ff },
13122 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13123 0x00000000, 0xffffffff },
13124 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13125 0x00000000, 0x000000ff },
13126 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13127 0x00000000, 0xffffffff },
13128 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13129 0x00000000, 0xffffffff },
13130 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13131 0x00000000, 0xffffffff },
13132 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13133 0x00000000, 0xffffffff },
13134 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13135 0x00000000, 0xffffffff },
13136 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13137 0xffffffff, 0x00000000 },
13138 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13139 0xffffffff, 0x00000000 },
13141 /* Buffer Manager Control Registers. */
13142 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13143 0x00000000, 0x007fff80 },
13144 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13145 0x00000000, 0x007fffff },
13146 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13147 0x00000000, 0x0000003f },
13148 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13149 0x00000000, 0x000001ff },
13150 { BUFMGR_MB_HIGH_WATER, 0x0000,
13151 0x00000000, 0x000001ff },
13152 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13153 0xffffffff, 0x00000000 },
13154 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13155 0xffffffff, 0x00000000 },
13157 /* Mailbox Registers */
13158 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13159 0x00000000, 0x000001ff },
13160 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13161 0x00000000, 0x000001ff },
13162 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13163 0x00000000, 0x000007ff },
13164 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13165 0x00000000, 0x000001ff },
13167 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13170 is_5705 = is_5750 = 0;
13171 if (tg3_flag(tp, 5705_PLUS)) {
13173 if (tg3_flag(tp, 5750_PLUS))
13177 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13178 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13181 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13184 if (tg3_flag(tp, IS_5788) &&
13185 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13188 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13191 offset = (u32) reg_tbl[i].offset;
13192 read_mask = reg_tbl[i].read_mask;
13193 write_mask = reg_tbl[i].write_mask;
13195 /* Save the original register content */
13196 save_val = tr32(offset);
13198 /* Determine the read-only value. */
13199 read_val = save_val & read_mask;
13201 /* Write zero to the register, then make sure the read-only bits
13202 * are not changed and the read/write bits are all zeros.
13206 val = tr32(offset);
13208 /* Test the read-only and read/write bits. */
13209 if (((val & read_mask) != read_val) || (val & write_mask))
13212 /* Write ones to all the bits defined by RdMask and WrMask, then
13213 * make sure the read-only bits are not changed and the
13214 * read/write bits are all ones.
13216 tw32(offset, read_mask | write_mask);
13218 val = tr32(offset);
13220 /* Test the read-only bits. */
13221 if ((val & read_mask) != read_val)
13224 /* Test the read/write bits. */
13225 if ((val & write_mask) != write_mask)
13228 tw32(offset, save_val);
13234 if (netif_msg_hw(tp))
13235 netdev_err(tp->dev,
13236 "Register test failed at offset %x\n", offset);
13237 tw32(offset, save_val);
13241 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13243 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13247 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13248 for (j = 0; j < len; j += 4) {
13251 tg3_write_mem(tp, offset + j, test_pattern[i]);
13252 tg3_read_mem(tp, offset + j, &val);
13253 if (val != test_pattern[i])
13260 static int tg3_test_memory(struct tg3 *tp)
13262 static struct mem_entry {
13265 } mem_tbl_570x[] = {
13266 { 0x00000000, 0x00b50},
13267 { 0x00002000, 0x1c000},
13268 { 0xffffffff, 0x00000}
13269 }, mem_tbl_5705[] = {
13270 { 0x00000100, 0x0000c},
13271 { 0x00000200, 0x00008},
13272 { 0x00004000, 0x00800},
13273 { 0x00006000, 0x01000},
13274 { 0x00008000, 0x02000},
13275 { 0x00010000, 0x0e000},
13276 { 0xffffffff, 0x00000}
13277 }, mem_tbl_5755[] = {
13278 { 0x00000200, 0x00008},
13279 { 0x00004000, 0x00800},
13280 { 0x00006000, 0x00800},
13281 { 0x00008000, 0x02000},
13282 { 0x00010000, 0x0c000},
13283 { 0xffffffff, 0x00000}
13284 }, mem_tbl_5906[] = {
13285 { 0x00000200, 0x00008},
13286 { 0x00004000, 0x00400},
13287 { 0x00006000, 0x00400},
13288 { 0x00008000, 0x01000},
13289 { 0x00010000, 0x01000},
13290 { 0xffffffff, 0x00000}
13291 }, mem_tbl_5717[] = {
13292 { 0x00000200, 0x00008},
13293 { 0x00010000, 0x0a000},
13294 { 0x00020000, 0x13c00},
13295 { 0xffffffff, 0x00000}
13296 }, mem_tbl_57765[] = {
13297 { 0x00000200, 0x00008},
13298 { 0x00004000, 0x00800},
13299 { 0x00006000, 0x09800},
13300 { 0x00010000, 0x0a000},
13301 { 0xffffffff, 0x00000}
13303 struct mem_entry *mem_tbl;
13307 if (tg3_flag(tp, 5717_PLUS))
13308 mem_tbl = mem_tbl_5717;
13309 else if (tg3_flag(tp, 57765_CLASS) ||
13310 tg3_asic_rev(tp) == ASIC_REV_5762)
13311 mem_tbl = mem_tbl_57765;
13312 else if (tg3_flag(tp, 5755_PLUS))
13313 mem_tbl = mem_tbl_5755;
13314 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13315 mem_tbl = mem_tbl_5906;
13316 else if (tg3_flag(tp, 5705_PLUS))
13317 mem_tbl = mem_tbl_5705;
13319 mem_tbl = mem_tbl_570x;
13321 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13322 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13330 #define TG3_TSO_MSS 500
13332 #define TG3_TSO_IP_HDR_LEN 20
13333 #define TG3_TSO_TCP_HDR_LEN 20
13334 #define TG3_TSO_TCP_OPT_LEN 12
13336 static const u8 tg3_tso_header[] = {
13338 0x45, 0x00, 0x00, 0x00,
13339 0x00, 0x00, 0x40, 0x00,
13340 0x40, 0x06, 0x00, 0x00,
13341 0x0a, 0x00, 0x00, 0x01,
13342 0x0a, 0x00, 0x00, 0x02,
13343 0x0d, 0x00, 0xe0, 0x00,
13344 0x00, 0x00, 0x01, 0x00,
13345 0x00, 0x00, 0x02, 0x00,
13346 0x80, 0x10, 0x10, 0x00,
13347 0x14, 0x09, 0x00, 0x00,
13348 0x01, 0x01, 0x08, 0x0a,
13349 0x11, 0x11, 0x11, 0x11,
13350 0x11, 0x11, 0x11, 0x11,
13353 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13355 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13356 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13358 struct sk_buff *skb;
13359 u8 *tx_data, *rx_data;
13361 int num_pkts, tx_len, rx_len, i, err;
13362 struct tg3_rx_buffer_desc *desc;
13363 struct tg3_napi *tnapi, *rnapi;
13364 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13366 tnapi = &tp->napi[0];
13367 rnapi = &tp->napi[0];
13368 if (tp->irq_cnt > 1) {
13369 if (tg3_flag(tp, ENABLE_RSS))
13370 rnapi = &tp->napi[1];
13371 if (tg3_flag(tp, ENABLE_TSS))
13372 tnapi = &tp->napi[1];
13374 coal_now = tnapi->coal_now | rnapi->coal_now;
13379 skb = netdev_alloc_skb(tp->dev, tx_len);
13383 tx_data = skb_put(skb, tx_len);
13384 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13385 memset(tx_data + ETH_ALEN, 0x0, 8);
13387 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13389 if (tso_loopback) {
13390 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13392 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13393 TG3_TSO_TCP_OPT_LEN;
13395 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13396 sizeof(tg3_tso_header));
13399 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13400 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13402 /* Set the total length field in the IP header */
13403 iph->tot_len = htons((u16)(mss + hdr_len));
13405 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13406 TXD_FLAG_CPU_POST_DMA);
13408 if (tg3_flag(tp, HW_TSO_1) ||
13409 tg3_flag(tp, HW_TSO_2) ||
13410 tg3_flag(tp, HW_TSO_3)) {
13412 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13413 th = (struct tcphdr *)&tx_data[val];
13416 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13418 if (tg3_flag(tp, HW_TSO_3)) {
13419 mss |= (hdr_len & 0xc) << 12;
13420 if (hdr_len & 0x10)
13421 base_flags |= 0x00000010;
13422 base_flags |= (hdr_len & 0x3e0) << 5;
13423 } else if (tg3_flag(tp, HW_TSO_2))
13424 mss |= hdr_len << 9;
13425 else if (tg3_flag(tp, HW_TSO_1) ||
13426 tg3_asic_rev(tp) == ASIC_REV_5705) {
13427 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13429 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13432 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13435 data_off = ETH_HLEN;
13437 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13438 tx_len > VLAN_ETH_FRAME_LEN)
13439 base_flags |= TXD_FLAG_JMB_PKT;
13442 for (i = data_off; i < tx_len; i++)
13443 tx_data[i] = (u8) (i & 0xff);
13445 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13446 if (pci_dma_mapping_error(tp->pdev, map)) {
13447 dev_kfree_skb(skb);
13451 val = tnapi->tx_prod;
13452 tnapi->tx_buffers[val].skb = skb;
13453 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13455 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13460 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13462 budget = tg3_tx_avail(tnapi);
13463 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13464 base_flags | TXD_FLAG_END, mss, 0)) {
13465 tnapi->tx_buffers[val].skb = NULL;
13466 dev_kfree_skb(skb);
13472 /* Sync BD data before updating mailbox */
13475 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13476 tr32_mailbox(tnapi->prodmbox);
13480 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13481 for (i = 0; i < 35; i++) {
13482 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13487 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13488 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13489 if ((tx_idx == tnapi->tx_prod) &&
13490 (rx_idx == (rx_start_idx + num_pkts)))
13494 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13495 dev_kfree_skb(skb);
13497 if (tx_idx != tnapi->tx_prod)
13500 if (rx_idx != rx_start_idx + num_pkts)
13504 while (rx_idx != rx_start_idx) {
13505 desc = &rnapi->rx_rcb[rx_start_idx++];
13506 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13507 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13509 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13510 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13513 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13516 if (!tso_loopback) {
13517 if (rx_len != tx_len)
13520 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13521 if (opaque_key != RXD_OPAQUE_RING_STD)
13524 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13527 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13528 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13529 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13533 if (opaque_key == RXD_OPAQUE_RING_STD) {
13534 rx_data = tpr->rx_std_buffers[desc_idx].data;
13535 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13537 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13538 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13539 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13544 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13545 PCI_DMA_FROMDEVICE);
13547 rx_data += TG3_RX_OFFSET(tp);
13548 for (i = data_off; i < rx_len; i++, val++) {
13549 if (*(rx_data + i) != (u8) (val & 0xff))
13556 /* tg3_free_rings will unmap and free the rx_data */
13561 #define TG3_STD_LOOPBACK_FAILED 1
13562 #define TG3_JMB_LOOPBACK_FAILED 2
13563 #define TG3_TSO_LOOPBACK_FAILED 4
13564 #define TG3_LOOPBACK_FAILED \
13565 (TG3_STD_LOOPBACK_FAILED | \
13566 TG3_JMB_LOOPBACK_FAILED | \
13567 TG3_TSO_LOOPBACK_FAILED)
13569 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13573 u32 jmb_pkt_sz = 9000;
13576 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13578 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13579 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13581 if (!netif_running(tp->dev)) {
13582 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13583 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13585 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13589 err = tg3_reset_hw(tp, true);
13591 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13592 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13594 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13598 if (tg3_flag(tp, ENABLE_RSS)) {
13601 /* Reroute all rx packets to the 1st queue */
13602 for (i = MAC_RSS_INDIR_TBL_0;
13603 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13607 /* HW errata - mac loopback fails in some cases on 5780.
13608 * Normal traffic and PHY loopback are not affected by
13609 * errata. Also, the MAC loopback test is deprecated for
13610 * all newer ASIC revisions.
13612 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13613 !tg3_flag(tp, CPMU_PRESENT)) {
13614 tg3_mac_loopback(tp, true);
13616 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13617 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13619 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13620 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13621 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13623 tg3_mac_loopback(tp, false);
13626 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13627 !tg3_flag(tp, USE_PHYLIB)) {
13630 tg3_phy_lpbk_set(tp, 0, false);
13632 /* Wait for link */
13633 for (i = 0; i < 100; i++) {
13634 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13639 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13640 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13641 if (tg3_flag(tp, TSO_CAPABLE) &&
13642 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13643 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13644 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13645 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13646 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13649 tg3_phy_lpbk_set(tp, 0, true);
13651 /* All link indications report up, but the hardware
13652 * isn't really ready for about 20 msec. Double it
13657 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13658 data[TG3_EXT_LOOPB_TEST] |=
13659 TG3_STD_LOOPBACK_FAILED;
13660 if (tg3_flag(tp, TSO_CAPABLE) &&
13661 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13662 data[TG3_EXT_LOOPB_TEST] |=
13663 TG3_TSO_LOOPBACK_FAILED;
13664 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13665 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13666 data[TG3_EXT_LOOPB_TEST] |=
13667 TG3_JMB_LOOPBACK_FAILED;
13670 /* Re-enable gphy autopowerdown. */
13671 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13672 tg3_phy_toggle_apd(tp, true);
13675 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13676 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13679 tp->phy_flags |= eee_cap;
13684 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13687 struct tg3 *tp = netdev_priv(dev);
13688 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13690 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13691 if (tg3_power_up(tp)) {
13692 etest->flags |= ETH_TEST_FL_FAILED;
13693 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13696 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13699 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13701 if (tg3_test_nvram(tp) != 0) {
13702 etest->flags |= ETH_TEST_FL_FAILED;
13703 data[TG3_NVRAM_TEST] = 1;
13705 if (!doextlpbk && tg3_test_link(tp)) {
13706 etest->flags |= ETH_TEST_FL_FAILED;
13707 data[TG3_LINK_TEST] = 1;
13709 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13710 int err, err2 = 0, irq_sync = 0;
13712 if (netif_running(dev)) {
13714 tg3_netif_stop(tp);
13718 tg3_full_lock(tp, irq_sync);
13719 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13720 err = tg3_nvram_lock(tp);
13721 tg3_halt_cpu(tp, RX_CPU_BASE);
13722 if (!tg3_flag(tp, 5705_PLUS))
13723 tg3_halt_cpu(tp, TX_CPU_BASE);
13725 tg3_nvram_unlock(tp);
13727 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13730 if (tg3_test_registers(tp) != 0) {
13731 etest->flags |= ETH_TEST_FL_FAILED;
13732 data[TG3_REGISTER_TEST] = 1;
13735 if (tg3_test_memory(tp) != 0) {
13736 etest->flags |= ETH_TEST_FL_FAILED;
13737 data[TG3_MEMORY_TEST] = 1;
13741 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13743 if (tg3_test_loopback(tp, data, doextlpbk))
13744 etest->flags |= ETH_TEST_FL_FAILED;
13746 tg3_full_unlock(tp);
13748 if (tg3_test_interrupt(tp) != 0) {
13749 etest->flags |= ETH_TEST_FL_FAILED;
13750 data[TG3_INTERRUPT_TEST] = 1;
13753 tg3_full_lock(tp, 0);
13755 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13756 if (netif_running(dev)) {
13757 tg3_flag_set(tp, INIT_COMPLETE);
13758 err2 = tg3_restart_hw(tp, true);
13760 tg3_netif_start(tp);
13763 tg3_full_unlock(tp);
13765 if (irq_sync && !err2)
13768 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13769 tg3_power_down_prepare(tp);
13773 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13775 struct tg3 *tp = netdev_priv(dev);
13776 struct hwtstamp_config stmpconf;
13778 if (!tg3_flag(tp, PTP_CAPABLE))
13779 return -EOPNOTSUPP;
13781 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13784 if (stmpconf.flags)
13787 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13788 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13791 switch (stmpconf.rx_filter) {
13792 case HWTSTAMP_FILTER_NONE:
13795 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13796 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13797 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13799 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13800 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13801 TG3_RX_PTP_CTL_SYNC_EVNT;
13803 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13804 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13805 TG3_RX_PTP_CTL_DELAY_REQ;
13807 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13808 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13809 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13811 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13812 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13813 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13815 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13816 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13817 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13819 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13820 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13821 TG3_RX_PTP_CTL_SYNC_EVNT;
13823 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13824 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13825 TG3_RX_PTP_CTL_SYNC_EVNT;
13827 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13828 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13829 TG3_RX_PTP_CTL_SYNC_EVNT;
13831 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13832 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13833 TG3_RX_PTP_CTL_DELAY_REQ;
13835 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13836 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13837 TG3_RX_PTP_CTL_DELAY_REQ;
13839 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13840 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13841 TG3_RX_PTP_CTL_DELAY_REQ;
13847 if (netif_running(dev) && tp->rxptpctl)
13848 tw32(TG3_RX_PTP_CTL,
13849 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13851 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13852 tg3_flag_set(tp, TX_TSTAMP_EN);
13854 tg3_flag_clear(tp, TX_TSTAMP_EN);
13856 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13860 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13862 struct tg3 *tp = netdev_priv(dev);
13863 struct hwtstamp_config stmpconf;
13865 if (!tg3_flag(tp, PTP_CAPABLE))
13866 return -EOPNOTSUPP;
13868 stmpconf.flags = 0;
13869 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13870 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13872 switch (tp->rxptpctl) {
13874 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13876 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13877 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13879 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13880 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13882 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13883 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13885 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13886 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13888 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13889 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13891 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13892 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13894 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13895 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13897 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13898 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13900 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13901 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13903 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13904 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13906 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13907 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13909 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13910 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13917 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13921 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13923 struct mii_ioctl_data *data = if_mii(ifr);
13924 struct tg3 *tp = netdev_priv(dev);
13927 if (tg3_flag(tp, USE_PHYLIB)) {
13928 struct phy_device *phydev;
13929 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13931 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13932 return phy_mii_ioctl(phydev, ifr, cmd);
13937 data->phy_id = tp->phy_addr;
13940 case SIOCGMIIREG: {
13943 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13944 break; /* We have no PHY */
13946 if (!netif_running(dev))
13949 spin_lock_bh(&tp->lock);
13950 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13951 data->reg_num & 0x1f, &mii_regval);
13952 spin_unlock_bh(&tp->lock);
13954 data->val_out = mii_regval;
13960 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13961 break; /* We have no PHY */
13963 if (!netif_running(dev))
13966 spin_lock_bh(&tp->lock);
13967 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13968 data->reg_num & 0x1f, data->val_in);
13969 spin_unlock_bh(&tp->lock);
13973 case SIOCSHWTSTAMP:
13974 return tg3_hwtstamp_set(dev, ifr);
13976 case SIOCGHWTSTAMP:
13977 return tg3_hwtstamp_get(dev, ifr);
13983 return -EOPNOTSUPP;
13986 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13988 struct tg3 *tp = netdev_priv(dev);
13990 memcpy(ec, &tp->coal, sizeof(*ec));
13994 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13996 struct tg3 *tp = netdev_priv(dev);
13997 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13998 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
14000 if (!tg3_flag(tp, 5705_PLUS)) {
14001 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
14002 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
14003 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
14004 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
14007 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
14008 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
14009 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
14010 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
14011 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
14012 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
14013 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
14014 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
14015 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
14016 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14019 /* No rx interrupts will be generated if both are zero */
14020 if ((ec->rx_coalesce_usecs == 0) &&
14021 (ec->rx_max_coalesced_frames == 0))
14024 /* No tx interrupts will be generated if both are zero */
14025 if ((ec->tx_coalesce_usecs == 0) &&
14026 (ec->tx_max_coalesced_frames == 0))
14029 /* Only copy relevant parameters, ignore all others. */
14030 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14031 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14032 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14033 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14034 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14035 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14036 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14037 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14038 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14040 if (netif_running(dev)) {
14041 tg3_full_lock(tp, 0);
14042 __tg3_set_coalesce(tp, &tp->coal);
14043 tg3_full_unlock(tp);
14048 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14050 struct tg3 *tp = netdev_priv(dev);
14052 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14053 netdev_warn(tp->dev, "Board does not support EEE!\n");
14054 return -EOPNOTSUPP;
14057 if (edata->advertised != tp->eee.advertised) {
14058 netdev_warn(tp->dev,
14059 "Direct manipulation of EEE advertisement is not supported\n");
14063 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14064 netdev_warn(tp->dev,
14065 "Maximal Tx Lpi timer supported is %#x(u)\n",
14066 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14072 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14073 tg3_warn_mgmt_link_flap(tp);
14075 if (netif_running(tp->dev)) {
14076 tg3_full_lock(tp, 0);
14079 tg3_full_unlock(tp);
14085 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14087 struct tg3 *tp = netdev_priv(dev);
14089 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14090 netdev_warn(tp->dev,
14091 "Board does not support EEE!\n");
14092 return -EOPNOTSUPP;
14099 static const struct ethtool_ops tg3_ethtool_ops = {
14100 .get_settings = tg3_get_settings,
14101 .set_settings = tg3_set_settings,
14102 .get_drvinfo = tg3_get_drvinfo,
14103 .get_regs_len = tg3_get_regs_len,
14104 .get_regs = tg3_get_regs,
14105 .get_wol = tg3_get_wol,
14106 .set_wol = tg3_set_wol,
14107 .get_msglevel = tg3_get_msglevel,
14108 .set_msglevel = tg3_set_msglevel,
14109 .nway_reset = tg3_nway_reset,
14110 .get_link = ethtool_op_get_link,
14111 .get_eeprom_len = tg3_get_eeprom_len,
14112 .get_eeprom = tg3_get_eeprom,
14113 .set_eeprom = tg3_set_eeprom,
14114 .get_ringparam = tg3_get_ringparam,
14115 .set_ringparam = tg3_set_ringparam,
14116 .get_pauseparam = tg3_get_pauseparam,
14117 .set_pauseparam = tg3_set_pauseparam,
14118 .self_test = tg3_self_test,
14119 .get_strings = tg3_get_strings,
14120 .set_phys_id = tg3_set_phys_id,
14121 .get_ethtool_stats = tg3_get_ethtool_stats,
14122 .get_coalesce = tg3_get_coalesce,
14123 .set_coalesce = tg3_set_coalesce,
14124 .get_sset_count = tg3_get_sset_count,
14125 .get_rxnfc = tg3_get_rxnfc,
14126 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14127 .get_rxfh = tg3_get_rxfh,
14128 .set_rxfh = tg3_set_rxfh,
14129 .get_channels = tg3_get_channels,
14130 .set_channels = tg3_set_channels,
14131 .get_ts_info = tg3_get_ts_info,
14132 .get_eee = tg3_get_eee,
14133 .set_eee = tg3_set_eee,
14136 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14137 struct rtnl_link_stats64 *stats)
14139 struct tg3 *tp = netdev_priv(dev);
14141 spin_lock_bh(&tp->lock);
14142 if (!tp->hw_stats) {
14143 *stats = tp->net_stats_prev;
14144 spin_unlock_bh(&tp->lock);
14148 tg3_get_nstats(tp, stats);
14149 spin_unlock_bh(&tp->lock);
14154 static void tg3_set_rx_mode(struct net_device *dev)
14156 struct tg3 *tp = netdev_priv(dev);
14158 if (!netif_running(dev))
14161 tg3_full_lock(tp, 0);
14162 __tg3_set_rx_mode(dev);
14163 tg3_full_unlock(tp);
14166 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14169 dev->mtu = new_mtu;
14171 if (new_mtu > ETH_DATA_LEN) {
14172 if (tg3_flag(tp, 5780_CLASS)) {
14173 netdev_update_features(dev);
14174 tg3_flag_clear(tp, TSO_CAPABLE);
14176 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14179 if (tg3_flag(tp, 5780_CLASS)) {
14180 tg3_flag_set(tp, TSO_CAPABLE);
14181 netdev_update_features(dev);
14183 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14187 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14189 struct tg3 *tp = netdev_priv(dev);
14191 bool reset_phy = false;
14193 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14196 if (!netif_running(dev)) {
14197 /* We'll just catch it later when the
14200 tg3_set_mtu(dev, tp, new_mtu);
14206 tg3_netif_stop(tp);
14208 tg3_set_mtu(dev, tp, new_mtu);
14210 tg3_full_lock(tp, 1);
14212 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14214 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14215 * breaks all requests to 256 bytes.
14217 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14220 err = tg3_restart_hw(tp, reset_phy);
14223 tg3_netif_start(tp);
14225 tg3_full_unlock(tp);
14233 static const struct net_device_ops tg3_netdev_ops = {
14234 .ndo_open = tg3_open,
14235 .ndo_stop = tg3_close,
14236 .ndo_start_xmit = tg3_start_xmit,
14237 .ndo_get_stats64 = tg3_get_stats64,
14238 .ndo_validate_addr = eth_validate_addr,
14239 .ndo_set_rx_mode = tg3_set_rx_mode,
14240 .ndo_set_mac_address = tg3_set_mac_addr,
14241 .ndo_do_ioctl = tg3_ioctl,
14242 .ndo_tx_timeout = tg3_tx_timeout,
14243 .ndo_change_mtu = tg3_change_mtu,
14244 .ndo_fix_features = tg3_fix_features,
14245 .ndo_set_features = tg3_set_features,
14246 #ifdef CONFIG_NET_POLL_CONTROLLER
14247 .ndo_poll_controller = tg3_poll_controller,
14251 static void tg3_get_eeprom_size(struct tg3 *tp)
14253 u32 cursize, val, magic;
14255 tp->nvram_size = EEPROM_CHIP_SIZE;
14257 if (tg3_nvram_read(tp, 0, &magic) != 0)
14260 if ((magic != TG3_EEPROM_MAGIC) &&
14261 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14262 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14266 * Size the chip by reading offsets at increasing powers of two.
14267 * When we encounter our validation signature, we know the addressing
14268 * has wrapped around, and thus have our chip size.
14272 while (cursize < tp->nvram_size) {
14273 if (tg3_nvram_read(tp, cursize, &val) != 0)
14282 tp->nvram_size = cursize;
14285 static void tg3_get_nvram_size(struct tg3 *tp)
14289 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14292 /* Selfboot format */
14293 if (val != TG3_EEPROM_MAGIC) {
14294 tg3_get_eeprom_size(tp);
14298 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14300 /* This is confusing. We want to operate on the
14301 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14302 * call will read from NVRAM and byteswap the data
14303 * according to the byteswapping settings for all
14304 * other register accesses. This ensures the data we
14305 * want will always reside in the lower 16-bits.
14306 * However, the data in NVRAM is in LE format, which
14307 * means the data from the NVRAM read will always be
14308 * opposite the endianness of the CPU. The 16-bit
14309 * byteswap then brings the data to CPU endianness.
14311 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14315 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14318 static void tg3_get_nvram_info(struct tg3 *tp)
14322 nvcfg1 = tr32(NVRAM_CFG1);
14323 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14324 tg3_flag_set(tp, FLASH);
14326 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14327 tw32(NVRAM_CFG1, nvcfg1);
14330 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14331 tg3_flag(tp, 5780_CLASS)) {
14332 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14333 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14334 tp->nvram_jedecnum = JEDEC_ATMEL;
14335 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14336 tg3_flag_set(tp, NVRAM_BUFFERED);
14338 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14339 tp->nvram_jedecnum = JEDEC_ATMEL;
14340 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14342 case FLASH_VENDOR_ATMEL_EEPROM:
14343 tp->nvram_jedecnum = JEDEC_ATMEL;
14344 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14345 tg3_flag_set(tp, NVRAM_BUFFERED);
14347 case FLASH_VENDOR_ST:
14348 tp->nvram_jedecnum = JEDEC_ST;
14349 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14350 tg3_flag_set(tp, NVRAM_BUFFERED);
14352 case FLASH_VENDOR_SAIFUN:
14353 tp->nvram_jedecnum = JEDEC_SAIFUN;
14354 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14356 case FLASH_VENDOR_SST_SMALL:
14357 case FLASH_VENDOR_SST_LARGE:
14358 tp->nvram_jedecnum = JEDEC_SST;
14359 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14363 tp->nvram_jedecnum = JEDEC_ATMEL;
14364 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14365 tg3_flag_set(tp, NVRAM_BUFFERED);
14369 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14371 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14372 case FLASH_5752PAGE_SIZE_256:
14373 tp->nvram_pagesize = 256;
14375 case FLASH_5752PAGE_SIZE_512:
14376 tp->nvram_pagesize = 512;
14378 case FLASH_5752PAGE_SIZE_1K:
14379 tp->nvram_pagesize = 1024;
14381 case FLASH_5752PAGE_SIZE_2K:
14382 tp->nvram_pagesize = 2048;
14384 case FLASH_5752PAGE_SIZE_4K:
14385 tp->nvram_pagesize = 4096;
14387 case FLASH_5752PAGE_SIZE_264:
14388 tp->nvram_pagesize = 264;
14390 case FLASH_5752PAGE_SIZE_528:
14391 tp->nvram_pagesize = 528;
14396 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14400 nvcfg1 = tr32(NVRAM_CFG1);
14402 /* NVRAM protection for TPM */
14403 if (nvcfg1 & (1 << 27))
14404 tg3_flag_set(tp, PROTECTED_NVRAM);
14406 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14407 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14408 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14409 tp->nvram_jedecnum = JEDEC_ATMEL;
14410 tg3_flag_set(tp, NVRAM_BUFFERED);
14412 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14413 tp->nvram_jedecnum = JEDEC_ATMEL;
14414 tg3_flag_set(tp, NVRAM_BUFFERED);
14415 tg3_flag_set(tp, FLASH);
14417 case FLASH_5752VENDOR_ST_M45PE10:
14418 case FLASH_5752VENDOR_ST_M45PE20:
14419 case FLASH_5752VENDOR_ST_M45PE40:
14420 tp->nvram_jedecnum = JEDEC_ST;
14421 tg3_flag_set(tp, NVRAM_BUFFERED);
14422 tg3_flag_set(tp, FLASH);
14426 if (tg3_flag(tp, FLASH)) {
14427 tg3_nvram_get_pagesize(tp, nvcfg1);
14429 /* For eeprom, set pagesize to maximum eeprom size */
14430 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14432 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14433 tw32(NVRAM_CFG1, nvcfg1);
14437 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14439 u32 nvcfg1, protect = 0;
14441 nvcfg1 = tr32(NVRAM_CFG1);
14443 /* NVRAM protection for TPM */
14444 if (nvcfg1 & (1 << 27)) {
14445 tg3_flag_set(tp, PROTECTED_NVRAM);
14449 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14451 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14452 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14453 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14454 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14455 tp->nvram_jedecnum = JEDEC_ATMEL;
14456 tg3_flag_set(tp, NVRAM_BUFFERED);
14457 tg3_flag_set(tp, FLASH);
14458 tp->nvram_pagesize = 264;
14459 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14460 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14461 tp->nvram_size = (protect ? 0x3e200 :
14462 TG3_NVRAM_SIZE_512KB);
14463 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14464 tp->nvram_size = (protect ? 0x1f200 :
14465 TG3_NVRAM_SIZE_256KB);
14467 tp->nvram_size = (protect ? 0x1f200 :
14468 TG3_NVRAM_SIZE_128KB);
14470 case FLASH_5752VENDOR_ST_M45PE10:
14471 case FLASH_5752VENDOR_ST_M45PE20:
14472 case FLASH_5752VENDOR_ST_M45PE40:
14473 tp->nvram_jedecnum = JEDEC_ST;
14474 tg3_flag_set(tp, NVRAM_BUFFERED);
14475 tg3_flag_set(tp, FLASH);
14476 tp->nvram_pagesize = 256;
14477 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14478 tp->nvram_size = (protect ?
14479 TG3_NVRAM_SIZE_64KB :
14480 TG3_NVRAM_SIZE_128KB);
14481 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14482 tp->nvram_size = (protect ?
14483 TG3_NVRAM_SIZE_64KB :
14484 TG3_NVRAM_SIZE_256KB);
14486 tp->nvram_size = (protect ?
14487 TG3_NVRAM_SIZE_128KB :
14488 TG3_NVRAM_SIZE_512KB);
14493 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14497 nvcfg1 = tr32(NVRAM_CFG1);
14499 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14500 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14501 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14502 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14503 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14504 tp->nvram_jedecnum = JEDEC_ATMEL;
14505 tg3_flag_set(tp, NVRAM_BUFFERED);
14506 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14508 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14509 tw32(NVRAM_CFG1, nvcfg1);
14511 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14512 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14513 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14514 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14515 tp->nvram_jedecnum = JEDEC_ATMEL;
14516 tg3_flag_set(tp, NVRAM_BUFFERED);
14517 tg3_flag_set(tp, FLASH);
14518 tp->nvram_pagesize = 264;
14520 case FLASH_5752VENDOR_ST_M45PE10:
14521 case FLASH_5752VENDOR_ST_M45PE20:
14522 case FLASH_5752VENDOR_ST_M45PE40:
14523 tp->nvram_jedecnum = JEDEC_ST;
14524 tg3_flag_set(tp, NVRAM_BUFFERED);
14525 tg3_flag_set(tp, FLASH);
14526 tp->nvram_pagesize = 256;
14531 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14533 u32 nvcfg1, protect = 0;
14535 nvcfg1 = tr32(NVRAM_CFG1);
14537 /* NVRAM protection for TPM */
14538 if (nvcfg1 & (1 << 27)) {
14539 tg3_flag_set(tp, PROTECTED_NVRAM);
14543 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14545 case FLASH_5761VENDOR_ATMEL_ADB021D:
14546 case FLASH_5761VENDOR_ATMEL_ADB041D:
14547 case FLASH_5761VENDOR_ATMEL_ADB081D:
14548 case FLASH_5761VENDOR_ATMEL_ADB161D:
14549 case FLASH_5761VENDOR_ATMEL_MDB021D:
14550 case FLASH_5761VENDOR_ATMEL_MDB041D:
14551 case FLASH_5761VENDOR_ATMEL_MDB081D:
14552 case FLASH_5761VENDOR_ATMEL_MDB161D:
14553 tp->nvram_jedecnum = JEDEC_ATMEL;
14554 tg3_flag_set(tp, NVRAM_BUFFERED);
14555 tg3_flag_set(tp, FLASH);
14556 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14557 tp->nvram_pagesize = 256;
14559 case FLASH_5761VENDOR_ST_A_M45PE20:
14560 case FLASH_5761VENDOR_ST_A_M45PE40:
14561 case FLASH_5761VENDOR_ST_A_M45PE80:
14562 case FLASH_5761VENDOR_ST_A_M45PE16:
14563 case FLASH_5761VENDOR_ST_M_M45PE20:
14564 case FLASH_5761VENDOR_ST_M_M45PE40:
14565 case FLASH_5761VENDOR_ST_M_M45PE80:
14566 case FLASH_5761VENDOR_ST_M_M45PE16:
14567 tp->nvram_jedecnum = JEDEC_ST;
14568 tg3_flag_set(tp, NVRAM_BUFFERED);
14569 tg3_flag_set(tp, FLASH);
14570 tp->nvram_pagesize = 256;
14575 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14578 case FLASH_5761VENDOR_ATMEL_ADB161D:
14579 case FLASH_5761VENDOR_ATMEL_MDB161D:
14580 case FLASH_5761VENDOR_ST_A_M45PE16:
14581 case FLASH_5761VENDOR_ST_M_M45PE16:
14582 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14584 case FLASH_5761VENDOR_ATMEL_ADB081D:
14585 case FLASH_5761VENDOR_ATMEL_MDB081D:
14586 case FLASH_5761VENDOR_ST_A_M45PE80:
14587 case FLASH_5761VENDOR_ST_M_M45PE80:
14588 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14590 case FLASH_5761VENDOR_ATMEL_ADB041D:
14591 case FLASH_5761VENDOR_ATMEL_MDB041D:
14592 case FLASH_5761VENDOR_ST_A_M45PE40:
14593 case FLASH_5761VENDOR_ST_M_M45PE40:
14594 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14596 case FLASH_5761VENDOR_ATMEL_ADB021D:
14597 case FLASH_5761VENDOR_ATMEL_MDB021D:
14598 case FLASH_5761VENDOR_ST_A_M45PE20:
14599 case FLASH_5761VENDOR_ST_M_M45PE20:
14600 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14606 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14608 tp->nvram_jedecnum = JEDEC_ATMEL;
14609 tg3_flag_set(tp, NVRAM_BUFFERED);
14610 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14613 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14617 nvcfg1 = tr32(NVRAM_CFG1);
14619 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14620 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14621 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14622 tp->nvram_jedecnum = JEDEC_ATMEL;
14623 tg3_flag_set(tp, NVRAM_BUFFERED);
14624 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14626 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14627 tw32(NVRAM_CFG1, nvcfg1);
14629 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14630 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14631 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14632 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14633 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14634 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14635 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14636 tp->nvram_jedecnum = JEDEC_ATMEL;
14637 tg3_flag_set(tp, NVRAM_BUFFERED);
14638 tg3_flag_set(tp, FLASH);
14640 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14641 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14642 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14643 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14644 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14646 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14647 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14648 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14650 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14651 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14652 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14656 case FLASH_5752VENDOR_ST_M45PE10:
14657 case FLASH_5752VENDOR_ST_M45PE20:
14658 case FLASH_5752VENDOR_ST_M45PE40:
14659 tp->nvram_jedecnum = JEDEC_ST;
14660 tg3_flag_set(tp, NVRAM_BUFFERED);
14661 tg3_flag_set(tp, FLASH);
14663 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14664 case FLASH_5752VENDOR_ST_M45PE10:
14665 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14667 case FLASH_5752VENDOR_ST_M45PE20:
14668 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14670 case FLASH_5752VENDOR_ST_M45PE40:
14671 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14676 tg3_flag_set(tp, NO_NVRAM);
14680 tg3_nvram_get_pagesize(tp, nvcfg1);
14681 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14682 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14686 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14690 nvcfg1 = tr32(NVRAM_CFG1);
14692 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14693 case FLASH_5717VENDOR_ATMEL_EEPROM:
14694 case FLASH_5717VENDOR_MICRO_EEPROM:
14695 tp->nvram_jedecnum = JEDEC_ATMEL;
14696 tg3_flag_set(tp, NVRAM_BUFFERED);
14697 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14699 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14700 tw32(NVRAM_CFG1, nvcfg1);
14702 case FLASH_5717VENDOR_ATMEL_MDB011D:
14703 case FLASH_5717VENDOR_ATMEL_ADB011B:
14704 case FLASH_5717VENDOR_ATMEL_ADB011D:
14705 case FLASH_5717VENDOR_ATMEL_MDB021D:
14706 case FLASH_5717VENDOR_ATMEL_ADB021B:
14707 case FLASH_5717VENDOR_ATMEL_ADB021D:
14708 case FLASH_5717VENDOR_ATMEL_45USPT:
14709 tp->nvram_jedecnum = JEDEC_ATMEL;
14710 tg3_flag_set(tp, NVRAM_BUFFERED);
14711 tg3_flag_set(tp, FLASH);
14713 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14714 case FLASH_5717VENDOR_ATMEL_MDB021D:
14715 /* Detect size with tg3_nvram_get_size() */
14717 case FLASH_5717VENDOR_ATMEL_ADB021B:
14718 case FLASH_5717VENDOR_ATMEL_ADB021D:
14719 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14722 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14726 case FLASH_5717VENDOR_ST_M_M25PE10:
14727 case FLASH_5717VENDOR_ST_A_M25PE10:
14728 case FLASH_5717VENDOR_ST_M_M45PE10:
14729 case FLASH_5717VENDOR_ST_A_M45PE10:
14730 case FLASH_5717VENDOR_ST_M_M25PE20:
14731 case FLASH_5717VENDOR_ST_A_M25PE20:
14732 case FLASH_5717VENDOR_ST_M_M45PE20:
14733 case FLASH_5717VENDOR_ST_A_M45PE20:
14734 case FLASH_5717VENDOR_ST_25USPT:
14735 case FLASH_5717VENDOR_ST_45USPT:
14736 tp->nvram_jedecnum = JEDEC_ST;
14737 tg3_flag_set(tp, NVRAM_BUFFERED);
14738 tg3_flag_set(tp, FLASH);
14740 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14741 case FLASH_5717VENDOR_ST_M_M25PE20:
14742 case FLASH_5717VENDOR_ST_M_M45PE20:
14743 /* Detect size with tg3_nvram_get_size() */
14745 case FLASH_5717VENDOR_ST_A_M25PE20:
14746 case FLASH_5717VENDOR_ST_A_M45PE20:
14747 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14750 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14755 tg3_flag_set(tp, NO_NVRAM);
14759 tg3_nvram_get_pagesize(tp, nvcfg1);
14760 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14761 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14764 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14766 u32 nvcfg1, nvmpinstrp;
14768 nvcfg1 = tr32(NVRAM_CFG1);
14769 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14771 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14772 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14773 tg3_flag_set(tp, NO_NVRAM);
14777 switch (nvmpinstrp) {
14778 case FLASH_5762_EEPROM_HD:
14779 nvmpinstrp = FLASH_5720_EEPROM_HD;
14781 case FLASH_5762_EEPROM_LD:
14782 nvmpinstrp = FLASH_5720_EEPROM_LD;
14784 case FLASH_5720VENDOR_M_ST_M45PE20:
14785 /* This pinstrap supports multiple sizes, so force it
14786 * to read the actual size from location 0xf0.
14788 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14793 switch (nvmpinstrp) {
14794 case FLASH_5720_EEPROM_HD:
14795 case FLASH_5720_EEPROM_LD:
14796 tp->nvram_jedecnum = JEDEC_ATMEL;
14797 tg3_flag_set(tp, NVRAM_BUFFERED);
14799 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14800 tw32(NVRAM_CFG1, nvcfg1);
14801 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14802 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14804 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14806 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14807 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14808 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14809 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14810 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14811 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14812 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14813 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14814 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14815 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14816 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14817 case FLASH_5720VENDOR_ATMEL_45USPT:
14818 tp->nvram_jedecnum = JEDEC_ATMEL;
14819 tg3_flag_set(tp, NVRAM_BUFFERED);
14820 tg3_flag_set(tp, FLASH);
14822 switch (nvmpinstrp) {
14823 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14824 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14825 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14826 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14828 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14829 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14830 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14831 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14833 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14834 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14835 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14838 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14839 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14843 case FLASH_5720VENDOR_M_ST_M25PE10:
14844 case FLASH_5720VENDOR_M_ST_M45PE10:
14845 case FLASH_5720VENDOR_A_ST_M25PE10:
14846 case FLASH_5720VENDOR_A_ST_M45PE10:
14847 case FLASH_5720VENDOR_M_ST_M25PE20:
14848 case FLASH_5720VENDOR_M_ST_M45PE20:
14849 case FLASH_5720VENDOR_A_ST_M25PE20:
14850 case FLASH_5720VENDOR_A_ST_M45PE20:
14851 case FLASH_5720VENDOR_M_ST_M25PE40:
14852 case FLASH_5720VENDOR_M_ST_M45PE40:
14853 case FLASH_5720VENDOR_A_ST_M25PE40:
14854 case FLASH_5720VENDOR_A_ST_M45PE40:
14855 case FLASH_5720VENDOR_M_ST_M25PE80:
14856 case FLASH_5720VENDOR_M_ST_M45PE80:
14857 case FLASH_5720VENDOR_A_ST_M25PE80:
14858 case FLASH_5720VENDOR_A_ST_M45PE80:
14859 case FLASH_5720VENDOR_ST_25USPT:
14860 case FLASH_5720VENDOR_ST_45USPT:
14861 tp->nvram_jedecnum = JEDEC_ST;
14862 tg3_flag_set(tp, NVRAM_BUFFERED);
14863 tg3_flag_set(tp, FLASH);
14865 switch (nvmpinstrp) {
14866 case FLASH_5720VENDOR_M_ST_M25PE20:
14867 case FLASH_5720VENDOR_M_ST_M45PE20:
14868 case FLASH_5720VENDOR_A_ST_M25PE20:
14869 case FLASH_5720VENDOR_A_ST_M45PE20:
14870 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14872 case FLASH_5720VENDOR_M_ST_M25PE40:
14873 case FLASH_5720VENDOR_M_ST_M45PE40:
14874 case FLASH_5720VENDOR_A_ST_M25PE40:
14875 case FLASH_5720VENDOR_A_ST_M45PE40:
14876 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14878 case FLASH_5720VENDOR_M_ST_M25PE80:
14879 case FLASH_5720VENDOR_M_ST_M45PE80:
14880 case FLASH_5720VENDOR_A_ST_M25PE80:
14881 case FLASH_5720VENDOR_A_ST_M45PE80:
14882 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14885 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14886 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14891 tg3_flag_set(tp, NO_NVRAM);
14895 tg3_nvram_get_pagesize(tp, nvcfg1);
14896 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14897 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14899 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14902 if (tg3_nvram_read(tp, 0, &val))
14905 if (val != TG3_EEPROM_MAGIC &&
14906 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14907 tg3_flag_set(tp, NO_NVRAM);
14911 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14912 static void tg3_nvram_init(struct tg3 *tp)
14914 if (tg3_flag(tp, IS_SSB_CORE)) {
14915 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14916 tg3_flag_clear(tp, NVRAM);
14917 tg3_flag_clear(tp, NVRAM_BUFFERED);
14918 tg3_flag_set(tp, NO_NVRAM);
14922 tw32_f(GRC_EEPROM_ADDR,
14923 (EEPROM_ADDR_FSM_RESET |
14924 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14925 EEPROM_ADDR_CLKPERD_SHIFT)));
14929 /* Enable seeprom accesses. */
14930 tw32_f(GRC_LOCAL_CTRL,
14931 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14934 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14935 tg3_asic_rev(tp) != ASIC_REV_5701) {
14936 tg3_flag_set(tp, NVRAM);
14938 if (tg3_nvram_lock(tp)) {
14939 netdev_warn(tp->dev,
14940 "Cannot get nvram lock, %s failed\n",
14944 tg3_enable_nvram_access(tp);
14946 tp->nvram_size = 0;
14948 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14949 tg3_get_5752_nvram_info(tp);
14950 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14951 tg3_get_5755_nvram_info(tp);
14952 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14953 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14954 tg3_asic_rev(tp) == ASIC_REV_5785)
14955 tg3_get_5787_nvram_info(tp);
14956 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14957 tg3_get_5761_nvram_info(tp);
14958 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14959 tg3_get_5906_nvram_info(tp);
14960 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14961 tg3_flag(tp, 57765_CLASS))
14962 tg3_get_57780_nvram_info(tp);
14963 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14964 tg3_asic_rev(tp) == ASIC_REV_5719)
14965 tg3_get_5717_nvram_info(tp);
14966 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14967 tg3_asic_rev(tp) == ASIC_REV_5762)
14968 tg3_get_5720_nvram_info(tp);
14970 tg3_get_nvram_info(tp);
14972 if (tp->nvram_size == 0)
14973 tg3_get_nvram_size(tp);
14975 tg3_disable_nvram_access(tp);
14976 tg3_nvram_unlock(tp);
14979 tg3_flag_clear(tp, NVRAM);
14980 tg3_flag_clear(tp, NVRAM_BUFFERED);
14982 tg3_get_eeprom_size(tp);
14986 struct subsys_tbl_ent {
14987 u16 subsys_vendor, subsys_devid;
14991 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14992 /* Broadcom boards. */
14993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14994 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14996 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14997 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14998 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14999 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15000 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
15001 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15002 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
15003 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15004 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
15005 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15006 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
15007 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15008 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
15009 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15010 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
15011 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15012 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
15013 { TG3PCI_SUBVENDOR_ID_BROADCOM,
15014 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
15017 { TG3PCI_SUBVENDOR_ID_3COM,
15018 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15019 { TG3PCI_SUBVENDOR_ID_3COM,
15020 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15021 { TG3PCI_SUBVENDOR_ID_3COM,
15022 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15023 { TG3PCI_SUBVENDOR_ID_3COM,
15024 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15025 { TG3PCI_SUBVENDOR_ID_3COM,
15026 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15029 { TG3PCI_SUBVENDOR_ID_DELL,
15030 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15031 { TG3PCI_SUBVENDOR_ID_DELL,
15032 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15033 { TG3PCI_SUBVENDOR_ID_DELL,
15034 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15035 { TG3PCI_SUBVENDOR_ID_DELL,
15036 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15038 /* Compaq boards. */
15039 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15040 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15041 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15042 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15043 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15044 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15045 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15046 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15047 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15048 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15051 { TG3PCI_SUBVENDOR_ID_IBM,
15052 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15055 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15059 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15060 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15061 tp->pdev->subsystem_vendor) &&
15062 (subsys_id_to_phy_id[i].subsys_devid ==
15063 tp->pdev->subsystem_device))
15064 return &subsys_id_to_phy_id[i];
15069 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15073 tp->phy_id = TG3_PHY_ID_INVALID;
15074 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15076 /* Assume an onboard device and WOL capable by default. */
15077 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15078 tg3_flag_set(tp, WOL_CAP);
15080 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15081 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15082 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15083 tg3_flag_set(tp, IS_NIC);
15085 val = tr32(VCPU_CFGSHDW);
15086 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15087 tg3_flag_set(tp, ASPM_WORKAROUND);
15088 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15089 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15090 tg3_flag_set(tp, WOL_ENABLE);
15091 device_set_wakeup_enable(&tp->pdev->dev, true);
15096 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15097 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15098 u32 nic_cfg, led_cfg;
15099 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15100 u32 nic_phy_id, ver, eeprom_phy_id;
15101 int eeprom_phy_serdes = 0;
15103 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15104 tp->nic_sram_data_cfg = nic_cfg;
15106 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15107 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15108 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15109 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15110 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15111 (ver > 0) && (ver < 0x100))
15112 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15114 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15115 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15117 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15118 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15119 tg3_asic_rev(tp) == ASIC_REV_5720)
15120 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15122 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15123 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15124 eeprom_phy_serdes = 1;
15126 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15127 if (nic_phy_id != 0) {
15128 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15129 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15131 eeprom_phy_id = (id1 >> 16) << 10;
15132 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15133 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15137 tp->phy_id = eeprom_phy_id;
15138 if (eeprom_phy_serdes) {
15139 if (!tg3_flag(tp, 5705_PLUS))
15140 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15142 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15145 if (tg3_flag(tp, 5750_PLUS))
15146 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15147 SHASTA_EXT_LED_MODE_MASK);
15149 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15153 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15154 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15157 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15158 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15161 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15162 tp->led_ctrl = LED_CTRL_MODE_MAC;
15164 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15165 * read on some older 5700/5701 bootcode.
15167 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15168 tg3_asic_rev(tp) == ASIC_REV_5701)
15169 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15173 case SHASTA_EXT_LED_SHARED:
15174 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15175 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15176 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15177 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15178 LED_CTRL_MODE_PHY_2);
15180 if (tg3_flag(tp, 5717_PLUS) ||
15181 tg3_asic_rev(tp) == ASIC_REV_5762)
15182 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15183 LED_CTRL_BLINK_RATE_MASK;
15187 case SHASTA_EXT_LED_MAC:
15188 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15191 case SHASTA_EXT_LED_COMBO:
15192 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15193 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15194 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15195 LED_CTRL_MODE_PHY_2);
15200 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15201 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15202 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15203 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15205 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15206 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15208 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15209 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15210 if ((tp->pdev->subsystem_vendor ==
15211 PCI_VENDOR_ID_ARIMA) &&
15212 (tp->pdev->subsystem_device == 0x205a ||
15213 tp->pdev->subsystem_device == 0x2063))
15214 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15216 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15217 tg3_flag_set(tp, IS_NIC);
15220 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15221 tg3_flag_set(tp, ENABLE_ASF);
15222 if (tg3_flag(tp, 5750_PLUS))
15223 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15226 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15227 tg3_flag(tp, 5750_PLUS))
15228 tg3_flag_set(tp, ENABLE_APE);
15230 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15231 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15232 tg3_flag_clear(tp, WOL_CAP);
15234 if (tg3_flag(tp, WOL_CAP) &&
15235 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15236 tg3_flag_set(tp, WOL_ENABLE);
15237 device_set_wakeup_enable(&tp->pdev->dev, true);
15240 if (cfg2 & (1 << 17))
15241 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15243 /* serdes signal pre-emphasis in register 0x590 set by */
15244 /* bootcode if bit 18 is set */
15245 if (cfg2 & (1 << 18))
15246 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15248 if ((tg3_flag(tp, 57765_PLUS) ||
15249 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15250 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15251 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15252 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15254 if (tg3_flag(tp, PCI_EXPRESS)) {
15257 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15258 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15259 !tg3_flag(tp, 57765_PLUS) &&
15260 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15261 tg3_flag_set(tp, ASPM_WORKAROUND);
15262 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15263 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15264 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15265 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15268 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15269 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15270 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15271 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15272 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15273 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15275 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15276 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15279 if (tg3_flag(tp, WOL_CAP))
15280 device_set_wakeup_enable(&tp->pdev->dev,
15281 tg3_flag(tp, WOL_ENABLE));
15283 device_set_wakeup_capable(&tp->pdev->dev, false);
15286 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15289 u32 val2, off = offset * 8;
15291 err = tg3_nvram_lock(tp);
15295 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15296 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15297 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15298 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15301 for (i = 0; i < 100; i++) {
15302 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15303 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15304 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15310 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15312 tg3_nvram_unlock(tp);
15313 if (val2 & APE_OTP_STATUS_CMD_DONE)
15319 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15324 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15325 tw32(OTP_CTRL, cmd);
15327 /* Wait for up to 1 ms for command to execute. */
15328 for (i = 0; i < 100; i++) {
15329 val = tr32(OTP_STATUS);
15330 if (val & OTP_STATUS_CMD_DONE)
15335 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15338 /* Read the gphy configuration from the OTP region of the chip. The gphy
15339 * configuration is a 32-bit value that straddles the alignment boundary.
15340 * We do two 32-bit reads and then shift and merge the results.
15342 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15344 u32 bhalf_otp, thalf_otp;
15346 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15348 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15351 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15353 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15356 thalf_otp = tr32(OTP_READ_DATA);
15358 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15360 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15363 bhalf_otp = tr32(OTP_READ_DATA);
15365 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15368 static void tg3_phy_init_link_config(struct tg3 *tp)
15370 u32 adv = ADVERTISED_Autoneg;
15372 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15373 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15374 adv |= ADVERTISED_1000baseT_Half;
15375 adv |= ADVERTISED_1000baseT_Full;
15378 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15379 adv |= ADVERTISED_100baseT_Half |
15380 ADVERTISED_100baseT_Full |
15381 ADVERTISED_10baseT_Half |
15382 ADVERTISED_10baseT_Full |
15385 adv |= ADVERTISED_FIBRE;
15387 tp->link_config.advertising = adv;
15388 tp->link_config.speed = SPEED_UNKNOWN;
15389 tp->link_config.duplex = DUPLEX_UNKNOWN;
15390 tp->link_config.autoneg = AUTONEG_ENABLE;
15391 tp->link_config.active_speed = SPEED_UNKNOWN;
15392 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15397 static int tg3_phy_probe(struct tg3 *tp)
15399 u32 hw_phy_id_1, hw_phy_id_2;
15400 u32 hw_phy_id, hw_phy_id_masked;
15403 /* flow control autonegotiation is default behavior */
15404 tg3_flag_set(tp, PAUSE_AUTONEG);
15405 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15407 if (tg3_flag(tp, ENABLE_APE)) {
15408 switch (tp->pci_fn) {
15410 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15413 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15416 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15419 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15424 if (!tg3_flag(tp, ENABLE_ASF) &&
15425 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15426 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15427 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15428 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15430 if (tg3_flag(tp, USE_PHYLIB))
15431 return tg3_phy_init(tp);
15433 /* Reading the PHY ID register can conflict with ASF
15434 * firmware access to the PHY hardware.
15437 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15438 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15440 /* Now read the physical PHY_ID from the chip and verify
15441 * that it is sane. If it doesn't look good, we fall back
15442 * to either the hard-coded table based PHY_ID and failing
15443 * that the value found in the eeprom area.
15445 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15446 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15448 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15449 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15450 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15452 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15455 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15456 tp->phy_id = hw_phy_id;
15457 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15458 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15460 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15462 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15463 /* Do nothing, phy ID already set up in
15464 * tg3_get_eeprom_hw_cfg().
15467 struct subsys_tbl_ent *p;
15469 /* No eeprom signature? Try the hardcoded
15470 * subsys device table.
15472 p = tg3_lookup_by_subsys(tp);
15474 tp->phy_id = p->phy_id;
15475 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15476 /* For now we saw the IDs 0xbc050cd0,
15477 * 0xbc050f80 and 0xbc050c30 on devices
15478 * connected to an BCM4785 and there are
15479 * probably more. Just assume that the phy is
15480 * supported when it is connected to a SSB core
15487 tp->phy_id == TG3_PHY_ID_BCM8002)
15488 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15492 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15493 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15494 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15495 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15496 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15497 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15498 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15499 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15500 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15501 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15503 tp->eee.supported = SUPPORTED_100baseT_Full |
15504 SUPPORTED_1000baseT_Full;
15505 tp->eee.advertised = ADVERTISED_100baseT_Full |
15506 ADVERTISED_1000baseT_Full;
15507 tp->eee.eee_enabled = 1;
15508 tp->eee.tx_lpi_enabled = 1;
15509 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15512 tg3_phy_init_link_config(tp);
15514 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15515 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15516 !tg3_flag(tp, ENABLE_APE) &&
15517 !tg3_flag(tp, ENABLE_ASF)) {
15520 tg3_readphy(tp, MII_BMSR, &bmsr);
15521 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15522 (bmsr & BMSR_LSTATUS))
15523 goto skip_phy_reset;
15525 err = tg3_phy_reset(tp);
15529 tg3_phy_set_wirespeed(tp);
15531 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15532 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15533 tp->link_config.flowctrl);
15535 tg3_writephy(tp, MII_BMCR,
15536 BMCR_ANENABLE | BMCR_ANRESTART);
15541 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15542 err = tg3_init_5401phy_dsp(tp);
15546 err = tg3_init_5401phy_dsp(tp);
15552 static void tg3_read_vpd(struct tg3 *tp)
15555 unsigned int block_end, rosize, len;
15559 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15563 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15565 goto out_not_found;
15567 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15568 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15569 i += PCI_VPD_LRDT_TAG_SIZE;
15571 if (block_end > vpdlen)
15572 goto out_not_found;
15574 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15575 PCI_VPD_RO_KEYWORD_MFR_ID);
15577 len = pci_vpd_info_field_size(&vpd_data[j]);
15579 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15580 if (j + len > block_end || len != 4 ||
15581 memcmp(&vpd_data[j], "1028", 4))
15584 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15585 PCI_VPD_RO_KEYWORD_VENDOR0);
15589 len = pci_vpd_info_field_size(&vpd_data[j]);
15591 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15592 if (j + len > block_end)
15595 if (len >= sizeof(tp->fw_ver))
15596 len = sizeof(tp->fw_ver) - 1;
15597 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15598 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15603 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15604 PCI_VPD_RO_KEYWORD_PARTNO);
15606 goto out_not_found;
15608 len = pci_vpd_info_field_size(&vpd_data[i]);
15610 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15611 if (len > TG3_BPN_SIZE ||
15612 (len + i) > vpdlen)
15613 goto out_not_found;
15615 memcpy(tp->board_part_number, &vpd_data[i], len);
15619 if (tp->board_part_number[0])
15623 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15624 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15625 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15626 strcpy(tp->board_part_number, "BCM5717");
15627 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15628 strcpy(tp->board_part_number, "BCM5718");
15631 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15632 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15633 strcpy(tp->board_part_number, "BCM57780");
15634 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15635 strcpy(tp->board_part_number, "BCM57760");
15636 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15637 strcpy(tp->board_part_number, "BCM57790");
15638 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15639 strcpy(tp->board_part_number, "BCM57788");
15642 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15643 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15644 strcpy(tp->board_part_number, "BCM57761");
15645 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15646 strcpy(tp->board_part_number, "BCM57765");
15647 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15648 strcpy(tp->board_part_number, "BCM57781");
15649 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15650 strcpy(tp->board_part_number, "BCM57785");
15651 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15652 strcpy(tp->board_part_number, "BCM57791");
15653 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15654 strcpy(tp->board_part_number, "BCM57795");
15657 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15658 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15659 strcpy(tp->board_part_number, "BCM57762");
15660 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15661 strcpy(tp->board_part_number, "BCM57766");
15662 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15663 strcpy(tp->board_part_number, "BCM57782");
15664 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15665 strcpy(tp->board_part_number, "BCM57786");
15668 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15669 strcpy(tp->board_part_number, "BCM95906");
15672 strcpy(tp->board_part_number, "none");
15676 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15680 if (tg3_nvram_read(tp, offset, &val) ||
15681 (val & 0xfc000000) != 0x0c000000 ||
15682 tg3_nvram_read(tp, offset + 4, &val) ||
15689 static void tg3_read_bc_ver(struct tg3 *tp)
15691 u32 val, offset, start, ver_offset;
15693 bool newver = false;
15695 if (tg3_nvram_read(tp, 0xc, &offset) ||
15696 tg3_nvram_read(tp, 0x4, &start))
15699 offset = tg3_nvram_logical_addr(tp, offset);
15701 if (tg3_nvram_read(tp, offset, &val))
15704 if ((val & 0xfc000000) == 0x0c000000) {
15705 if (tg3_nvram_read(tp, offset + 4, &val))
15712 dst_off = strlen(tp->fw_ver);
15715 if (TG3_VER_SIZE - dst_off < 16 ||
15716 tg3_nvram_read(tp, offset + 8, &ver_offset))
15719 offset = offset + ver_offset - start;
15720 for (i = 0; i < 16; i += 4) {
15722 if (tg3_nvram_read_be32(tp, offset + i, &v))
15725 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15730 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15733 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15734 TG3_NVM_BCVER_MAJSFT;
15735 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15736 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15737 "v%d.%02d", major, minor);
15741 static void tg3_read_hwsb_ver(struct tg3 *tp)
15743 u32 val, major, minor;
15745 /* Use native endian representation */
15746 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15749 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15750 TG3_NVM_HWSB_CFG1_MAJSFT;
15751 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15752 TG3_NVM_HWSB_CFG1_MINSFT;
15754 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15757 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15759 u32 offset, major, minor, build;
15761 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15763 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15766 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15767 case TG3_EEPROM_SB_REVISION_0:
15768 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15770 case TG3_EEPROM_SB_REVISION_2:
15771 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15773 case TG3_EEPROM_SB_REVISION_3:
15774 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15776 case TG3_EEPROM_SB_REVISION_4:
15777 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15779 case TG3_EEPROM_SB_REVISION_5:
15780 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15782 case TG3_EEPROM_SB_REVISION_6:
15783 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15789 if (tg3_nvram_read(tp, offset, &val))
15792 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15793 TG3_EEPROM_SB_EDH_BLD_SHFT;
15794 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15795 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15796 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15798 if (minor > 99 || build > 26)
15801 offset = strlen(tp->fw_ver);
15802 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15803 " v%d.%02d", major, minor);
15806 offset = strlen(tp->fw_ver);
15807 if (offset < TG3_VER_SIZE - 1)
15808 tp->fw_ver[offset] = 'a' + build - 1;
15812 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15814 u32 val, offset, start;
15817 for (offset = TG3_NVM_DIR_START;
15818 offset < TG3_NVM_DIR_END;
15819 offset += TG3_NVM_DIRENT_SIZE) {
15820 if (tg3_nvram_read(tp, offset, &val))
15823 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15827 if (offset == TG3_NVM_DIR_END)
15830 if (!tg3_flag(tp, 5705_PLUS))
15831 start = 0x08000000;
15832 else if (tg3_nvram_read(tp, offset - 4, &start))
15835 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15836 !tg3_fw_img_is_valid(tp, offset) ||
15837 tg3_nvram_read(tp, offset + 8, &val))
15840 offset += val - start;
15842 vlen = strlen(tp->fw_ver);
15844 tp->fw_ver[vlen++] = ',';
15845 tp->fw_ver[vlen++] = ' ';
15847 for (i = 0; i < 4; i++) {
15849 if (tg3_nvram_read_be32(tp, offset, &v))
15852 offset += sizeof(v);
15854 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15855 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15859 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15864 static void tg3_probe_ncsi(struct tg3 *tp)
15868 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15869 if (apedata != APE_SEG_SIG_MAGIC)
15872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15873 if (!(apedata & APE_FW_STATUS_READY))
15876 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15877 tg3_flag_set(tp, APE_HAS_NCSI);
15880 static void tg3_read_dash_ver(struct tg3 *tp)
15886 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15888 if (tg3_flag(tp, APE_HAS_NCSI))
15890 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15895 vlen = strlen(tp->fw_ver);
15897 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15899 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15900 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15901 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15902 (apedata & APE_FW_VERSION_BLDMSK));
15905 static void tg3_read_otp_ver(struct tg3 *tp)
15909 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15912 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15913 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15914 TG3_OTP_MAGIC0_VALID(val)) {
15915 u64 val64 = (u64) val << 32 | val2;
15919 for (i = 0; i < 7; i++) {
15920 if ((val64 & 0xff) == 0)
15922 ver = val64 & 0xff;
15925 vlen = strlen(tp->fw_ver);
15926 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15930 static void tg3_read_fw_ver(struct tg3 *tp)
15933 bool vpd_vers = false;
15935 if (tp->fw_ver[0] != 0)
15938 if (tg3_flag(tp, NO_NVRAM)) {
15939 strcat(tp->fw_ver, "sb");
15940 tg3_read_otp_ver(tp);
15944 if (tg3_nvram_read(tp, 0, &val))
15947 if (val == TG3_EEPROM_MAGIC)
15948 tg3_read_bc_ver(tp);
15949 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15950 tg3_read_sb_ver(tp, val);
15951 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15952 tg3_read_hwsb_ver(tp);
15954 if (tg3_flag(tp, ENABLE_ASF)) {
15955 if (tg3_flag(tp, ENABLE_APE)) {
15956 tg3_probe_ncsi(tp);
15958 tg3_read_dash_ver(tp);
15959 } else if (!vpd_vers) {
15960 tg3_read_mgmtfw_ver(tp);
15964 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15967 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15969 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15970 return TG3_RX_RET_MAX_SIZE_5717;
15971 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15972 return TG3_RX_RET_MAX_SIZE_5700;
15974 return TG3_RX_RET_MAX_SIZE_5705;
15977 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15978 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15979 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15980 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15984 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15986 struct pci_dev *peer;
15987 unsigned int func, devnr = tp->pdev->devfn & ~7;
15989 for (func = 0; func < 8; func++) {
15990 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15991 if (peer && peer != tp->pdev)
15995 /* 5704 can be configured in single-port mode, set peer to
15996 * tp->pdev in that case.
16004 * We don't need to keep the refcount elevated; there's no way
16005 * to remove one half of this device without removing the other
16012 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
16014 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
16015 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16018 /* All devices that use the alternate
16019 * ASIC REV location have a CPMU.
16021 tg3_flag_set(tp, CPMU_PRESENT);
16023 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16027 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16028 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16029 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16030 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16031 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16032 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16033 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16034 reg = TG3PCI_GEN2_PRODID_ASICREV;
16035 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16036 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16037 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16038 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16039 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16040 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16041 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16042 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16043 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16044 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16045 reg = TG3PCI_GEN15_PRODID_ASICREV;
16047 reg = TG3PCI_PRODID_ASICREV;
16049 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16052 /* Wrong chip ID in 5752 A0. This code can be removed later
16053 * as A0 is not in production.
16055 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16056 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16058 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16059 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16061 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16062 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16063 tg3_asic_rev(tp) == ASIC_REV_5720)
16064 tg3_flag_set(tp, 5717_PLUS);
16066 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16067 tg3_asic_rev(tp) == ASIC_REV_57766)
16068 tg3_flag_set(tp, 57765_CLASS);
16070 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16071 tg3_asic_rev(tp) == ASIC_REV_5762)
16072 tg3_flag_set(tp, 57765_PLUS);
16074 /* Intentionally exclude ASIC_REV_5906 */
16075 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16076 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16077 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16078 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16079 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16080 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16081 tg3_flag(tp, 57765_PLUS))
16082 tg3_flag_set(tp, 5755_PLUS);
16084 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16085 tg3_asic_rev(tp) == ASIC_REV_5714)
16086 tg3_flag_set(tp, 5780_CLASS);
16088 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16089 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16090 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16091 tg3_flag(tp, 5755_PLUS) ||
16092 tg3_flag(tp, 5780_CLASS))
16093 tg3_flag_set(tp, 5750_PLUS);
16095 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16096 tg3_flag(tp, 5750_PLUS))
16097 tg3_flag_set(tp, 5705_PLUS);
16100 static bool tg3_10_100_only_device(struct tg3 *tp,
16101 const struct pci_device_id *ent)
16103 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16105 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16106 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16107 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16110 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16111 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16112 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16122 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16125 u32 pci_state_reg, grc_misc_cfg;
16130 /* Force memory write invalidate off. If we leave it on,
16131 * then on 5700_BX chips we have to enable a workaround.
16132 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16133 * to match the cacheline size. The Broadcom driver have this
16134 * workaround but turns MWI off all the times so never uses
16135 * it. This seems to suggest that the workaround is insufficient.
16137 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16138 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16139 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16141 /* Important! -- Make sure register accesses are byteswapped
16142 * correctly. Also, for those chips that require it, make
16143 * sure that indirect register accesses are enabled before
16144 * the first operation.
16146 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16148 tp->misc_host_ctrl |= (misc_ctrl_reg &
16149 MISC_HOST_CTRL_CHIPREV);
16150 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16151 tp->misc_host_ctrl);
16153 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16155 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16156 * we need to disable memory and use config. cycles
16157 * only to access all registers. The 5702/03 chips
16158 * can mistakenly decode the special cycles from the
16159 * ICH chipsets as memory write cycles, causing corruption
16160 * of register and memory space. Only certain ICH bridges
16161 * will drive special cycles with non-zero data during the
16162 * address phase which can fall within the 5703's address
16163 * range. This is not an ICH bug as the PCI spec allows
16164 * non-zero address during special cycles. However, only
16165 * these ICH bridges are known to drive non-zero addresses
16166 * during special cycles.
16168 * Since special cycles do not cross PCI bridges, we only
16169 * enable this workaround if the 5703 is on the secondary
16170 * bus of these ICH bridges.
16172 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16173 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16174 static struct tg3_dev_id {
16178 } ich_chipsets[] = {
16179 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16181 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16183 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16185 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16189 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16190 struct pci_dev *bridge = NULL;
16192 while (pci_id->vendor != 0) {
16193 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16199 if (pci_id->rev != PCI_ANY_ID) {
16200 if (bridge->revision > pci_id->rev)
16203 if (bridge->subordinate &&
16204 (bridge->subordinate->number ==
16205 tp->pdev->bus->number)) {
16206 tg3_flag_set(tp, ICH_WORKAROUND);
16207 pci_dev_put(bridge);
16213 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16214 static struct tg3_dev_id {
16217 } bridge_chipsets[] = {
16218 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16219 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16222 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16223 struct pci_dev *bridge = NULL;
16225 while (pci_id->vendor != 0) {
16226 bridge = pci_get_device(pci_id->vendor,
16233 if (bridge->subordinate &&
16234 (bridge->subordinate->number <=
16235 tp->pdev->bus->number) &&
16236 (bridge->subordinate->busn_res.end >=
16237 tp->pdev->bus->number)) {
16238 tg3_flag_set(tp, 5701_DMA_BUG);
16239 pci_dev_put(bridge);
16245 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16246 * DMA addresses > 40-bit. This bridge may have other additional
16247 * 57xx devices behind it in some 4-port NIC designs for example.
16248 * Any tg3 device found behind the bridge will also need the 40-bit
16251 if (tg3_flag(tp, 5780_CLASS)) {
16252 tg3_flag_set(tp, 40BIT_DMA_BUG);
16253 tp->msi_cap = tp->pdev->msi_cap;
16255 struct pci_dev *bridge = NULL;
16258 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16259 PCI_DEVICE_ID_SERVERWORKS_EPB,
16261 if (bridge && bridge->subordinate &&
16262 (bridge->subordinate->number <=
16263 tp->pdev->bus->number) &&
16264 (bridge->subordinate->busn_res.end >=
16265 tp->pdev->bus->number)) {
16266 tg3_flag_set(tp, 40BIT_DMA_BUG);
16267 pci_dev_put(bridge);
16273 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16274 tg3_asic_rev(tp) == ASIC_REV_5714)
16275 tp->pdev_peer = tg3_find_peer(tp);
16277 /* Determine TSO capabilities */
16278 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16279 ; /* Do nothing. HW bug. */
16280 else if (tg3_flag(tp, 57765_PLUS))
16281 tg3_flag_set(tp, HW_TSO_3);
16282 else if (tg3_flag(tp, 5755_PLUS) ||
16283 tg3_asic_rev(tp) == ASIC_REV_5906)
16284 tg3_flag_set(tp, HW_TSO_2);
16285 else if (tg3_flag(tp, 5750_PLUS)) {
16286 tg3_flag_set(tp, HW_TSO_1);
16287 tg3_flag_set(tp, TSO_BUG);
16288 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16289 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16290 tg3_flag_clear(tp, TSO_BUG);
16291 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16292 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16293 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16294 tg3_flag_set(tp, FW_TSO);
16295 tg3_flag_set(tp, TSO_BUG);
16296 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16297 tp->fw_needed = FIRMWARE_TG3TSO5;
16299 tp->fw_needed = FIRMWARE_TG3TSO;
16302 /* Selectively allow TSO based on operating conditions */
16303 if (tg3_flag(tp, HW_TSO_1) ||
16304 tg3_flag(tp, HW_TSO_2) ||
16305 tg3_flag(tp, HW_TSO_3) ||
16306 tg3_flag(tp, FW_TSO)) {
16307 /* For firmware TSO, assume ASF is disabled.
16308 * We'll disable TSO later if we discover ASF
16309 * is enabled in tg3_get_eeprom_hw_cfg().
16311 tg3_flag_set(tp, TSO_CAPABLE);
16313 tg3_flag_clear(tp, TSO_CAPABLE);
16314 tg3_flag_clear(tp, TSO_BUG);
16315 tp->fw_needed = NULL;
16318 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16319 tp->fw_needed = FIRMWARE_TG3;
16321 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16322 tp->fw_needed = FIRMWARE_TG357766;
16326 if (tg3_flag(tp, 5750_PLUS)) {
16327 tg3_flag_set(tp, SUPPORT_MSI);
16328 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16329 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16330 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16331 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16332 tp->pdev_peer == tp->pdev))
16333 tg3_flag_clear(tp, SUPPORT_MSI);
16335 if (tg3_flag(tp, 5755_PLUS) ||
16336 tg3_asic_rev(tp) == ASIC_REV_5906) {
16337 tg3_flag_set(tp, 1SHOT_MSI);
16340 if (tg3_flag(tp, 57765_PLUS)) {
16341 tg3_flag_set(tp, SUPPORT_MSIX);
16342 tp->irq_max = TG3_IRQ_MAX_VECS;
16348 if (tp->irq_max > 1) {
16349 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16350 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16352 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16353 tg3_asic_rev(tp) == ASIC_REV_5720)
16354 tp->txq_max = tp->irq_max - 1;
16357 if (tg3_flag(tp, 5755_PLUS) ||
16358 tg3_asic_rev(tp) == ASIC_REV_5906)
16359 tg3_flag_set(tp, SHORT_DMA_BUG);
16361 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16362 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16364 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16365 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16366 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16367 tg3_asic_rev(tp) == ASIC_REV_5762)
16368 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16370 if (tg3_flag(tp, 57765_PLUS) &&
16371 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16372 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16374 if (!tg3_flag(tp, 5705_PLUS) ||
16375 tg3_flag(tp, 5780_CLASS) ||
16376 tg3_flag(tp, USE_JUMBO_BDFLAG))
16377 tg3_flag_set(tp, JUMBO_CAPABLE);
16379 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16382 if (pci_is_pcie(tp->pdev)) {
16385 tg3_flag_set(tp, PCI_EXPRESS);
16387 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16388 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16389 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16390 tg3_flag_clear(tp, HW_TSO_2);
16391 tg3_flag_clear(tp, TSO_CAPABLE);
16393 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16394 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16395 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16396 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16397 tg3_flag_set(tp, CLKREQ_BUG);
16398 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16399 tg3_flag_set(tp, L1PLLPD_EN);
16401 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16402 /* BCM5785 devices are effectively PCIe devices, and should
16403 * follow PCIe codepaths, but do not have a PCIe capabilities
16406 tg3_flag_set(tp, PCI_EXPRESS);
16407 } else if (!tg3_flag(tp, 5705_PLUS) ||
16408 tg3_flag(tp, 5780_CLASS)) {
16409 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16410 if (!tp->pcix_cap) {
16411 dev_err(&tp->pdev->dev,
16412 "Cannot find PCI-X capability, aborting\n");
16416 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16417 tg3_flag_set(tp, PCIX_MODE);
16420 /* If we have an AMD 762 or VIA K8T800 chipset, write
16421 * reordering to the mailbox registers done by the host
16422 * controller can cause major troubles. We read back from
16423 * every mailbox register write to force the writes to be
16424 * posted to the chip in order.
16426 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16427 !tg3_flag(tp, PCI_EXPRESS))
16428 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16430 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16431 &tp->pci_cacheline_sz);
16432 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16433 &tp->pci_lat_timer);
16434 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16435 tp->pci_lat_timer < 64) {
16436 tp->pci_lat_timer = 64;
16437 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16438 tp->pci_lat_timer);
16441 /* Important! -- It is critical that the PCI-X hw workaround
16442 * situation is decided before the first MMIO register access.
16444 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16445 /* 5700 BX chips need to have their TX producer index
16446 * mailboxes written twice to workaround a bug.
16448 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16450 /* If we are in PCI-X mode, enable register write workaround.
16452 * The workaround is to use indirect register accesses
16453 * for all chip writes not to mailbox registers.
16455 if (tg3_flag(tp, PCIX_MODE)) {
16458 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16460 /* The chip can have it's power management PCI config
16461 * space registers clobbered due to this bug.
16462 * So explicitly force the chip into D0 here.
16464 pci_read_config_dword(tp->pdev,
16465 tp->pdev->pm_cap + PCI_PM_CTRL,
16467 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16468 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16469 pci_write_config_dword(tp->pdev,
16470 tp->pdev->pm_cap + PCI_PM_CTRL,
16473 /* Also, force SERR#/PERR# in PCI command. */
16474 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16475 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16476 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16480 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16481 tg3_flag_set(tp, PCI_HIGH_SPEED);
16482 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16483 tg3_flag_set(tp, PCI_32BIT);
16485 /* Chip-specific fixup from Broadcom driver */
16486 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16487 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16488 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16489 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16492 /* Default fast path register access methods */
16493 tp->read32 = tg3_read32;
16494 tp->write32 = tg3_write32;
16495 tp->read32_mbox = tg3_read32;
16496 tp->write32_mbox = tg3_write32;
16497 tp->write32_tx_mbox = tg3_write32;
16498 tp->write32_rx_mbox = tg3_write32;
16500 /* Various workaround register access methods */
16501 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16502 tp->write32 = tg3_write_indirect_reg32;
16503 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16504 (tg3_flag(tp, PCI_EXPRESS) &&
16505 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16507 * Back to back register writes can cause problems on these
16508 * chips, the workaround is to read back all reg writes
16509 * except those to mailbox regs.
16511 * See tg3_write_indirect_reg32().
16513 tp->write32 = tg3_write_flush_reg32;
16516 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16517 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16518 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16519 tp->write32_rx_mbox = tg3_write_flush_reg32;
16522 if (tg3_flag(tp, ICH_WORKAROUND)) {
16523 tp->read32 = tg3_read_indirect_reg32;
16524 tp->write32 = tg3_write_indirect_reg32;
16525 tp->read32_mbox = tg3_read_indirect_mbox;
16526 tp->write32_mbox = tg3_write_indirect_mbox;
16527 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16528 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16533 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16534 pci_cmd &= ~PCI_COMMAND_MEMORY;
16535 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16537 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16538 tp->read32_mbox = tg3_read32_mbox_5906;
16539 tp->write32_mbox = tg3_write32_mbox_5906;
16540 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16541 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16544 if (tp->write32 == tg3_write_indirect_reg32 ||
16545 (tg3_flag(tp, PCIX_MODE) &&
16546 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16547 tg3_asic_rev(tp) == ASIC_REV_5701)))
16548 tg3_flag_set(tp, SRAM_USE_CONFIG);
16550 /* The memory arbiter has to be enabled in order for SRAM accesses
16551 * to succeed. Normally on powerup the tg3 chip firmware will make
16552 * sure it is enabled, but other entities such as system netboot
16553 * code might disable it.
16555 val = tr32(MEMARB_MODE);
16556 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16558 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16559 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16560 tg3_flag(tp, 5780_CLASS)) {
16561 if (tg3_flag(tp, PCIX_MODE)) {
16562 pci_read_config_dword(tp->pdev,
16563 tp->pcix_cap + PCI_X_STATUS,
16565 tp->pci_fn = val & 0x7;
16567 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16568 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16569 tg3_asic_rev(tp) == ASIC_REV_5720) {
16570 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16571 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16572 val = tr32(TG3_CPMU_STATUS);
16574 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16575 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16577 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16578 TG3_CPMU_STATUS_FSHFT_5719;
16581 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16582 tp->write32_tx_mbox = tg3_write_flush_reg32;
16583 tp->write32_rx_mbox = tg3_write_flush_reg32;
16586 /* Get eeprom hw config before calling tg3_set_power_state().
16587 * In particular, the TG3_FLAG_IS_NIC flag must be
16588 * determined before calling tg3_set_power_state() so that
16589 * we know whether or not to switch out of Vaux power.
16590 * When the flag is set, it means that GPIO1 is used for eeprom
16591 * write protect and also implies that it is a LOM where GPIOs
16592 * are not used to switch power.
16594 tg3_get_eeprom_hw_cfg(tp);
16596 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16597 tg3_flag_clear(tp, TSO_CAPABLE);
16598 tg3_flag_clear(tp, TSO_BUG);
16599 tp->fw_needed = NULL;
16602 if (tg3_flag(tp, ENABLE_APE)) {
16603 /* Allow reads and writes to the
16604 * APE register and memory space.
16606 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16607 PCISTATE_ALLOW_APE_SHMEM_WR |
16608 PCISTATE_ALLOW_APE_PSPACE_WR;
16609 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16612 tg3_ape_lock_init(tp);
16615 /* Set up tp->grc_local_ctrl before calling
16616 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16617 * will bring 5700's external PHY out of reset.
16618 * It is also used as eeprom write protect on LOMs.
16620 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16621 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16622 tg3_flag(tp, EEPROM_WRITE_PROT))
16623 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16624 GRC_LCLCTRL_GPIO_OUTPUT1);
16625 /* Unused GPIO3 must be driven as output on 5752 because there
16626 * are no pull-up resistors on unused GPIO pins.
16628 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16629 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16631 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16632 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16633 tg3_flag(tp, 57765_CLASS))
16634 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16636 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16637 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16638 /* Turn off the debug UART. */
16639 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16640 if (tg3_flag(tp, IS_NIC))
16641 /* Keep VMain power. */
16642 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16643 GRC_LCLCTRL_GPIO_OUTPUT0;
16646 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16647 tp->grc_local_ctrl |=
16648 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16650 /* Switch out of Vaux if it is a NIC */
16651 tg3_pwrsrc_switch_to_vmain(tp);
16653 /* Derive initial jumbo mode from MTU assigned in
16654 * ether_setup() via the alloc_etherdev() call
16656 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16657 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16659 /* Determine WakeOnLan speed to use. */
16660 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16661 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16662 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16663 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16664 tg3_flag_clear(tp, WOL_SPEED_100MB);
16666 tg3_flag_set(tp, WOL_SPEED_100MB);
16669 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16670 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16672 /* A few boards don't want Ethernet@WireSpeed phy feature */
16673 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16674 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16675 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16676 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16677 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16678 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16679 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16681 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16682 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16683 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16684 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16685 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16687 if (tg3_flag(tp, 5705_PLUS) &&
16688 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16689 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16690 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16691 !tg3_flag(tp, 57765_PLUS)) {
16692 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16693 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16694 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16695 tg3_asic_rev(tp) == ASIC_REV_5761) {
16696 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16697 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16698 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16699 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16700 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16702 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16705 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16706 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16707 tp->phy_otp = tg3_read_otp_phycfg(tp);
16708 if (tp->phy_otp == 0)
16709 tp->phy_otp = TG3_OTP_DEFAULT;
16712 if (tg3_flag(tp, CPMU_PRESENT))
16713 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16715 tp->mi_mode = MAC_MI_MODE_BASE;
16717 tp->coalesce_mode = 0;
16718 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16719 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16720 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16722 /* Set these bits to enable statistics workaround. */
16723 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16724 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16725 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16726 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16727 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16728 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16731 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16732 tg3_asic_rev(tp) == ASIC_REV_57780)
16733 tg3_flag_set(tp, USE_PHYLIB);
16735 err = tg3_mdio_init(tp);
16739 /* Initialize data/descriptor byte/word swapping. */
16740 val = tr32(GRC_MODE);
16741 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16742 tg3_asic_rev(tp) == ASIC_REV_5762)
16743 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16744 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16745 GRC_MODE_B2HRX_ENABLE |
16746 GRC_MODE_HTX2B_ENABLE |
16747 GRC_MODE_HOST_STACKUP);
16749 val &= GRC_MODE_HOST_STACKUP;
16751 tw32(GRC_MODE, val | tp->grc_mode);
16753 tg3_switch_clocks(tp);
16755 /* Clear this out for sanity. */
16756 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16758 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16759 tw32(TG3PCI_REG_BASE_ADDR, 0);
16761 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16763 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16764 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16766 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16767 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16768 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16769 void __iomem *sram_base;
16771 /* Write some dummy words into the SRAM status block
16772 * area, see if it reads back correctly. If the return
16773 * value is bad, force enable the PCIX workaround.
16775 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16777 writel(0x00000000, sram_base);
16778 writel(0x00000000, sram_base + 4);
16779 writel(0xffffffff, sram_base + 4);
16780 if (readl(sram_base) != 0x00000000)
16781 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16786 tg3_nvram_init(tp);
16788 /* If the device has an NVRAM, no need to load patch firmware */
16789 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16790 !tg3_flag(tp, NO_NVRAM))
16791 tp->fw_needed = NULL;
16793 grc_misc_cfg = tr32(GRC_MISC_CFG);
16794 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16796 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16797 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16798 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16799 tg3_flag_set(tp, IS_5788);
16801 if (!tg3_flag(tp, IS_5788) &&
16802 tg3_asic_rev(tp) != ASIC_REV_5700)
16803 tg3_flag_set(tp, TAGGED_STATUS);
16804 if (tg3_flag(tp, TAGGED_STATUS)) {
16805 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16806 HOSTCC_MODE_CLRTICK_TXBD);
16808 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16809 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16810 tp->misc_host_ctrl);
16813 /* Preserve the APE MAC_MODE bits */
16814 if (tg3_flag(tp, ENABLE_APE))
16815 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16819 if (tg3_10_100_only_device(tp, ent))
16820 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16822 err = tg3_phy_probe(tp);
16824 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16825 /* ... but do not return immediately ... */
16830 tg3_read_fw_ver(tp);
16832 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16833 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16835 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16836 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16838 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16841 /* 5700 {AX,BX} chips have a broken status block link
16842 * change bit implementation, so we must use the
16843 * status register in those cases.
16845 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16846 tg3_flag_set(tp, USE_LINKCHG_REG);
16848 tg3_flag_clear(tp, USE_LINKCHG_REG);
16850 /* The led_ctrl is set during tg3_phy_probe, here we might
16851 * have to force the link status polling mechanism based
16852 * upon subsystem IDs.
16854 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16855 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16856 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16857 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16858 tg3_flag_set(tp, USE_LINKCHG_REG);
16861 /* For all SERDES we poll the MAC status register. */
16862 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16863 tg3_flag_set(tp, POLL_SERDES);
16865 tg3_flag_clear(tp, POLL_SERDES);
16867 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16868 tg3_flag_set(tp, POLL_CPMU_LINK);
16870 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16871 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16872 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16873 tg3_flag(tp, PCIX_MODE)) {
16874 tp->rx_offset = NET_SKB_PAD;
16875 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16876 tp->rx_copy_thresh = ~(u16)0;
16880 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16881 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16882 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16884 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16886 /* Increment the rx prod index on the rx std ring by at most
16887 * 8 for these chips to workaround hw errata.
16889 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16890 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16891 tg3_asic_rev(tp) == ASIC_REV_5755)
16892 tp->rx_std_max_post = 8;
16894 if (tg3_flag(tp, ASPM_WORKAROUND))
16895 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16896 PCIE_PWR_MGMT_L1_THRESH_MSK;
16901 #ifdef CONFIG_SPARC
16902 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16904 struct net_device *dev = tp->dev;
16905 struct pci_dev *pdev = tp->pdev;
16906 struct device_node *dp = pci_device_to_OF_node(pdev);
16907 const unsigned char *addr;
16910 addr = of_get_property(dp, "local-mac-address", &len);
16911 if (addr && len == ETH_ALEN) {
16912 memcpy(dev->dev_addr, addr, ETH_ALEN);
16918 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16920 struct net_device *dev = tp->dev;
16922 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16927 static int tg3_get_device_address(struct tg3 *tp)
16929 struct net_device *dev = tp->dev;
16930 u32 hi, lo, mac_offset;
16934 #ifdef CONFIG_SPARC
16935 if (!tg3_get_macaddr_sparc(tp))
16939 if (tg3_flag(tp, IS_SSB_CORE)) {
16940 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16941 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16946 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16947 tg3_flag(tp, 5780_CLASS)) {
16948 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16950 if (tg3_nvram_lock(tp))
16951 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16953 tg3_nvram_unlock(tp);
16954 } else if (tg3_flag(tp, 5717_PLUS)) {
16955 if (tp->pci_fn & 1)
16957 if (tp->pci_fn > 1)
16958 mac_offset += 0x18c;
16959 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16962 /* First try to get it from MAC address mailbox. */
16963 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16964 if ((hi >> 16) == 0x484b) {
16965 dev->dev_addr[0] = (hi >> 8) & 0xff;
16966 dev->dev_addr[1] = (hi >> 0) & 0xff;
16968 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16969 dev->dev_addr[2] = (lo >> 24) & 0xff;
16970 dev->dev_addr[3] = (lo >> 16) & 0xff;
16971 dev->dev_addr[4] = (lo >> 8) & 0xff;
16972 dev->dev_addr[5] = (lo >> 0) & 0xff;
16974 /* Some old bootcode may report a 0 MAC address in SRAM */
16975 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16978 /* Next, try NVRAM. */
16979 if (!tg3_flag(tp, NO_NVRAM) &&
16980 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16981 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16982 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16983 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16985 /* Finally just fetch it out of the MAC control regs. */
16987 hi = tr32(MAC_ADDR_0_HIGH);
16988 lo = tr32(MAC_ADDR_0_LOW);
16990 dev->dev_addr[5] = lo & 0xff;
16991 dev->dev_addr[4] = (lo >> 8) & 0xff;
16992 dev->dev_addr[3] = (lo >> 16) & 0xff;
16993 dev->dev_addr[2] = (lo >> 24) & 0xff;
16994 dev->dev_addr[1] = hi & 0xff;
16995 dev->dev_addr[0] = (hi >> 8) & 0xff;
16999 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
17000 #ifdef CONFIG_SPARC
17001 if (!tg3_get_default_macaddr_sparc(tp))
17009 #define BOUNDARY_SINGLE_CACHELINE 1
17010 #define BOUNDARY_MULTI_CACHELINE 2
17012 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
17014 int cacheline_size;
17018 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17020 cacheline_size = 1024;
17022 cacheline_size = (int) byte * 4;
17024 /* On 5703 and later chips, the boundary bits have no
17027 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17028 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17029 !tg3_flag(tp, PCI_EXPRESS))
17032 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17033 goal = BOUNDARY_MULTI_CACHELINE;
17035 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17036 goal = BOUNDARY_SINGLE_CACHELINE;
17042 if (tg3_flag(tp, 57765_PLUS)) {
17043 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17050 /* PCI controllers on most RISC systems tend to disconnect
17051 * when a device tries to burst across a cache-line boundary.
17052 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17054 * Unfortunately, for PCI-E there are only limited
17055 * write-side controls for this, and thus for reads
17056 * we will still get the disconnects. We'll also waste
17057 * these PCI cycles for both read and write for chips
17058 * other than 5700 and 5701 which do not implement the
17061 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17062 switch (cacheline_size) {
17067 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17068 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17069 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17071 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17072 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17077 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17078 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17082 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17083 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17086 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17087 switch (cacheline_size) {
17091 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17092 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17093 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17099 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17100 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17104 switch (cacheline_size) {
17106 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17107 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17108 DMA_RWCTRL_WRITE_BNDRY_16);
17113 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17114 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17115 DMA_RWCTRL_WRITE_BNDRY_32);
17120 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17121 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17122 DMA_RWCTRL_WRITE_BNDRY_64);
17127 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17128 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17129 DMA_RWCTRL_WRITE_BNDRY_128);
17134 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17135 DMA_RWCTRL_WRITE_BNDRY_256);
17138 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17139 DMA_RWCTRL_WRITE_BNDRY_512);
17143 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17144 DMA_RWCTRL_WRITE_BNDRY_1024);
17153 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17154 int size, bool to_device)
17156 struct tg3_internal_buffer_desc test_desc;
17157 u32 sram_dma_descs;
17160 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17162 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17163 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17164 tw32(RDMAC_STATUS, 0);
17165 tw32(WDMAC_STATUS, 0);
17167 tw32(BUFMGR_MODE, 0);
17168 tw32(FTQ_RESET, 0);
17170 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17171 test_desc.addr_lo = buf_dma & 0xffffffff;
17172 test_desc.nic_mbuf = 0x00002100;
17173 test_desc.len = size;
17176 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17177 * the *second* time the tg3 driver was getting loaded after an
17180 * Broadcom tells me:
17181 * ...the DMA engine is connected to the GRC block and a DMA
17182 * reset may affect the GRC block in some unpredictable way...
17183 * The behavior of resets to individual blocks has not been tested.
17185 * Broadcom noted the GRC reset will also reset all sub-components.
17188 test_desc.cqid_sqid = (13 << 8) | 2;
17190 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17193 test_desc.cqid_sqid = (16 << 8) | 7;
17195 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17198 test_desc.flags = 0x00000005;
17200 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17203 val = *(((u32 *)&test_desc) + i);
17204 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17205 sram_dma_descs + (i * sizeof(u32)));
17206 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17208 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17211 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17213 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17216 for (i = 0; i < 40; i++) {
17220 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17222 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17223 if ((val & 0xffff) == sram_dma_descs) {
17234 #define TEST_BUFFER_SIZE 0x2000
17236 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17237 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17241 static int tg3_test_dma(struct tg3 *tp)
17243 dma_addr_t buf_dma;
17244 u32 *buf, saved_dma_rwctrl;
17247 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17248 &buf_dma, GFP_KERNEL);
17254 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17255 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17257 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17259 if (tg3_flag(tp, 57765_PLUS))
17262 if (tg3_flag(tp, PCI_EXPRESS)) {
17263 /* DMA read watermark not used on PCIE */
17264 tp->dma_rwctrl |= 0x00180000;
17265 } else if (!tg3_flag(tp, PCIX_MODE)) {
17266 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17267 tg3_asic_rev(tp) == ASIC_REV_5750)
17268 tp->dma_rwctrl |= 0x003f0000;
17270 tp->dma_rwctrl |= 0x003f000f;
17272 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17273 tg3_asic_rev(tp) == ASIC_REV_5704) {
17274 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17275 u32 read_water = 0x7;
17277 /* If the 5704 is behind the EPB bridge, we can
17278 * do the less restrictive ONE_DMA workaround for
17279 * better performance.
17281 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17282 tg3_asic_rev(tp) == ASIC_REV_5704)
17283 tp->dma_rwctrl |= 0x8000;
17284 else if (ccval == 0x6 || ccval == 0x7)
17285 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17287 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17289 /* Set bit 23 to enable PCIX hw bug fix */
17291 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17292 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17294 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17295 /* 5780 always in PCIX mode */
17296 tp->dma_rwctrl |= 0x00144000;
17297 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17298 /* 5714 always in PCIX mode */
17299 tp->dma_rwctrl |= 0x00148000;
17301 tp->dma_rwctrl |= 0x001b000f;
17304 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17305 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17307 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17308 tg3_asic_rev(tp) == ASIC_REV_5704)
17309 tp->dma_rwctrl &= 0xfffffff0;
17311 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17312 tg3_asic_rev(tp) == ASIC_REV_5701) {
17313 /* Remove this if it causes problems for some boards. */
17314 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17316 /* On 5700/5701 chips, we need to set this bit.
17317 * Otherwise the chip will issue cacheline transactions
17318 * to streamable DMA memory with not all the byte
17319 * enables turned on. This is an error on several
17320 * RISC PCI controllers, in particular sparc64.
17322 * On 5703/5704 chips, this bit has been reassigned
17323 * a different meaning. In particular, it is used
17324 * on those chips to enable a PCI-X workaround.
17326 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17329 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17332 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17333 tg3_asic_rev(tp) != ASIC_REV_5701)
17336 /* It is best to perform DMA test with maximum write burst size
17337 * to expose the 5700/5701 write DMA bug.
17339 saved_dma_rwctrl = tp->dma_rwctrl;
17340 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17341 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17346 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17349 /* Send the buffer to the chip. */
17350 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17352 dev_err(&tp->pdev->dev,
17353 "%s: Buffer write failed. err = %d\n",
17358 /* Now read it back. */
17359 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17361 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17362 "err = %d\n", __func__, ret);
17367 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17371 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17372 DMA_RWCTRL_WRITE_BNDRY_16) {
17373 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17374 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17375 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17378 dev_err(&tp->pdev->dev,
17379 "%s: Buffer corrupted on read back! "
17380 "(%d != %d)\n", __func__, p[i], i);
17386 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17392 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17393 DMA_RWCTRL_WRITE_BNDRY_16) {
17394 /* DMA test passed without adjusting DMA boundary,
17395 * now look for chipsets that are known to expose the
17396 * DMA bug without failing the test.
17398 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17399 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17400 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17402 /* Safe to use the calculated DMA boundary. */
17403 tp->dma_rwctrl = saved_dma_rwctrl;
17406 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17410 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17415 static void tg3_init_bufmgr_config(struct tg3 *tp)
17417 if (tg3_flag(tp, 57765_PLUS)) {
17418 tp->bufmgr_config.mbuf_read_dma_low_water =
17419 DEFAULT_MB_RDMA_LOW_WATER_5705;
17420 tp->bufmgr_config.mbuf_mac_rx_low_water =
17421 DEFAULT_MB_MACRX_LOW_WATER_57765;
17422 tp->bufmgr_config.mbuf_high_water =
17423 DEFAULT_MB_HIGH_WATER_57765;
17425 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17426 DEFAULT_MB_RDMA_LOW_WATER_5705;
17427 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17428 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17429 tp->bufmgr_config.mbuf_high_water_jumbo =
17430 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17431 } else if (tg3_flag(tp, 5705_PLUS)) {
17432 tp->bufmgr_config.mbuf_read_dma_low_water =
17433 DEFAULT_MB_RDMA_LOW_WATER_5705;
17434 tp->bufmgr_config.mbuf_mac_rx_low_water =
17435 DEFAULT_MB_MACRX_LOW_WATER_5705;
17436 tp->bufmgr_config.mbuf_high_water =
17437 DEFAULT_MB_HIGH_WATER_5705;
17438 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17439 tp->bufmgr_config.mbuf_mac_rx_low_water =
17440 DEFAULT_MB_MACRX_LOW_WATER_5906;
17441 tp->bufmgr_config.mbuf_high_water =
17442 DEFAULT_MB_HIGH_WATER_5906;
17445 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17446 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17447 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17448 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17449 tp->bufmgr_config.mbuf_high_water_jumbo =
17450 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17452 tp->bufmgr_config.mbuf_read_dma_low_water =
17453 DEFAULT_MB_RDMA_LOW_WATER;
17454 tp->bufmgr_config.mbuf_mac_rx_low_water =
17455 DEFAULT_MB_MACRX_LOW_WATER;
17456 tp->bufmgr_config.mbuf_high_water =
17457 DEFAULT_MB_HIGH_WATER;
17459 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17460 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17461 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17462 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17463 tp->bufmgr_config.mbuf_high_water_jumbo =
17464 DEFAULT_MB_HIGH_WATER_JUMBO;
17467 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17468 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17471 static char *tg3_phy_string(struct tg3 *tp)
17473 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17474 case TG3_PHY_ID_BCM5400: return "5400";
17475 case TG3_PHY_ID_BCM5401: return "5401";
17476 case TG3_PHY_ID_BCM5411: return "5411";
17477 case TG3_PHY_ID_BCM5701: return "5701";
17478 case TG3_PHY_ID_BCM5703: return "5703";
17479 case TG3_PHY_ID_BCM5704: return "5704";
17480 case TG3_PHY_ID_BCM5705: return "5705";
17481 case TG3_PHY_ID_BCM5750: return "5750";
17482 case TG3_PHY_ID_BCM5752: return "5752";
17483 case TG3_PHY_ID_BCM5714: return "5714";
17484 case TG3_PHY_ID_BCM5780: return "5780";
17485 case TG3_PHY_ID_BCM5755: return "5755";
17486 case TG3_PHY_ID_BCM5787: return "5787";
17487 case TG3_PHY_ID_BCM5784: return "5784";
17488 case TG3_PHY_ID_BCM5756: return "5722/5756";
17489 case TG3_PHY_ID_BCM5906: return "5906";
17490 case TG3_PHY_ID_BCM5761: return "5761";
17491 case TG3_PHY_ID_BCM5718C: return "5718C";
17492 case TG3_PHY_ID_BCM5718S: return "5718S";
17493 case TG3_PHY_ID_BCM57765: return "57765";
17494 case TG3_PHY_ID_BCM5719C: return "5719C";
17495 case TG3_PHY_ID_BCM5720C: return "5720C";
17496 case TG3_PHY_ID_BCM5762: return "5762C";
17497 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17498 case 0: return "serdes";
17499 default: return "unknown";
17503 static char *tg3_bus_string(struct tg3 *tp, char *str)
17505 if (tg3_flag(tp, PCI_EXPRESS)) {
17506 strcpy(str, "PCI Express");
17508 } else if (tg3_flag(tp, PCIX_MODE)) {
17509 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17511 strcpy(str, "PCIX:");
17513 if ((clock_ctrl == 7) ||
17514 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17515 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17516 strcat(str, "133MHz");
17517 else if (clock_ctrl == 0)
17518 strcat(str, "33MHz");
17519 else if (clock_ctrl == 2)
17520 strcat(str, "50MHz");
17521 else if (clock_ctrl == 4)
17522 strcat(str, "66MHz");
17523 else if (clock_ctrl == 6)
17524 strcat(str, "100MHz");
17526 strcpy(str, "PCI:");
17527 if (tg3_flag(tp, PCI_HIGH_SPEED))
17528 strcat(str, "66MHz");
17530 strcat(str, "33MHz");
17532 if (tg3_flag(tp, PCI_32BIT))
17533 strcat(str, ":32-bit");
17535 strcat(str, ":64-bit");
17539 static void tg3_init_coal(struct tg3 *tp)
17541 struct ethtool_coalesce *ec = &tp->coal;
17543 memset(ec, 0, sizeof(*ec));
17544 ec->cmd = ETHTOOL_GCOALESCE;
17545 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17546 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17547 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17548 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17549 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17550 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17551 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17552 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17553 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17555 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17556 HOSTCC_MODE_CLRTICK_TXBD)) {
17557 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17558 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17559 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17560 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17563 if (tg3_flag(tp, 5705_PLUS)) {
17564 ec->rx_coalesce_usecs_irq = 0;
17565 ec->tx_coalesce_usecs_irq = 0;
17566 ec->stats_block_coalesce_usecs = 0;
17570 static int tg3_init_one(struct pci_dev *pdev,
17571 const struct pci_device_id *ent)
17573 struct net_device *dev;
17576 u32 sndmbx, rcvmbx, intmbx;
17578 u64 dma_mask, persist_dma_mask;
17579 netdev_features_t features = 0;
17581 printk_once(KERN_INFO "%s\n", version);
17583 err = pci_enable_device(pdev);
17585 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17589 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17591 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17592 goto err_out_disable_pdev;
17595 pci_set_master(pdev);
17597 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17600 goto err_out_free_res;
17603 SET_NETDEV_DEV(dev, &pdev->dev);
17605 tp = netdev_priv(dev);
17608 tp->rx_mode = TG3_DEF_RX_MODE;
17609 tp->tx_mode = TG3_DEF_TX_MODE;
17611 tp->pcierr_recovery = false;
17614 tp->msg_enable = tg3_debug;
17616 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17618 if (pdev_is_ssb_gige_core(pdev)) {
17619 tg3_flag_set(tp, IS_SSB_CORE);
17620 if (ssb_gige_must_flush_posted_writes(pdev))
17621 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17622 if (ssb_gige_one_dma_at_once(pdev))
17623 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17624 if (ssb_gige_have_roboswitch(pdev)) {
17625 tg3_flag_set(tp, USE_PHYLIB);
17626 tg3_flag_set(tp, ROBOSWITCH);
17628 if (ssb_gige_is_rgmii(pdev))
17629 tg3_flag_set(tp, RGMII_MODE);
17632 /* The word/byte swap controls here control register access byte
17633 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17636 tp->misc_host_ctrl =
17637 MISC_HOST_CTRL_MASK_PCI_INT |
17638 MISC_HOST_CTRL_WORD_SWAP |
17639 MISC_HOST_CTRL_INDIR_ACCESS |
17640 MISC_HOST_CTRL_PCISTATE_RW;
17642 /* The NONFRM (non-frame) byte/word swap controls take effect
17643 * on descriptor entries, anything which isn't packet data.
17645 * The StrongARM chips on the board (one for tx, one for rx)
17646 * are running in big-endian mode.
17648 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17649 GRC_MODE_WSWAP_NONFRM_DATA);
17650 #ifdef __BIG_ENDIAN
17651 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17653 spin_lock_init(&tp->lock);
17654 spin_lock_init(&tp->indirect_lock);
17655 INIT_WORK(&tp->reset_task, tg3_reset_task);
17657 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17659 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17661 goto err_out_free_dev;
17664 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17665 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17666 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17667 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17668 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17669 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17670 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17671 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17674 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17675 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17676 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17677 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17678 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17679 tg3_flag_set(tp, ENABLE_APE);
17680 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17681 if (!tp->aperegs) {
17682 dev_err(&pdev->dev,
17683 "Cannot map APE registers, aborting\n");
17685 goto err_out_iounmap;
17689 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17690 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17692 dev->ethtool_ops = &tg3_ethtool_ops;
17693 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17694 dev->netdev_ops = &tg3_netdev_ops;
17695 dev->irq = pdev->irq;
17697 err = tg3_get_invariants(tp, ent);
17699 dev_err(&pdev->dev,
17700 "Problem fetching invariants of chip, aborting\n");
17701 goto err_out_apeunmap;
17704 /* The EPB bridge inside 5714, 5715, and 5780 and any
17705 * device behind the EPB cannot support DMA addresses > 40-bit.
17706 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17707 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17708 * do DMA address check in tg3_start_xmit().
17710 if (tg3_flag(tp, IS_5788))
17711 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17712 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17713 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17714 #ifdef CONFIG_HIGHMEM
17715 dma_mask = DMA_BIT_MASK(64);
17718 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17720 /* Configure DMA attributes. */
17721 if (dma_mask > DMA_BIT_MASK(32)) {
17722 err = pci_set_dma_mask(pdev, dma_mask);
17724 features |= NETIF_F_HIGHDMA;
17725 err = pci_set_consistent_dma_mask(pdev,
17728 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17729 "DMA for consistent allocations\n");
17730 goto err_out_apeunmap;
17734 if (err || dma_mask == DMA_BIT_MASK(32)) {
17735 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17737 dev_err(&pdev->dev,
17738 "No usable DMA configuration, aborting\n");
17739 goto err_out_apeunmap;
17743 tg3_init_bufmgr_config(tp);
17745 /* 5700 B0 chips do not support checksumming correctly due
17746 * to hardware bugs.
17748 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17749 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17751 if (tg3_flag(tp, 5755_PLUS))
17752 features |= NETIF_F_IPV6_CSUM;
17755 /* TSO is on by default on chips that support hardware TSO.
17756 * Firmware TSO on older chips gives lower performance, so it
17757 * is off by default, but can be enabled using ethtool.
17759 if ((tg3_flag(tp, HW_TSO_1) ||
17760 tg3_flag(tp, HW_TSO_2) ||
17761 tg3_flag(tp, HW_TSO_3)) &&
17762 (features & NETIF_F_IP_CSUM))
17763 features |= NETIF_F_TSO;
17764 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17765 if (features & NETIF_F_IPV6_CSUM)
17766 features |= NETIF_F_TSO6;
17767 if (tg3_flag(tp, HW_TSO_3) ||
17768 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17769 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17770 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17771 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17772 tg3_asic_rev(tp) == ASIC_REV_57780)
17773 features |= NETIF_F_TSO_ECN;
17776 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17777 NETIF_F_HW_VLAN_CTAG_RX;
17778 dev->vlan_features |= features;
17781 * Add loopback capability only for a subset of devices that support
17782 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17783 * loopback for the remaining devices.
17785 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17786 !tg3_flag(tp, CPMU_PRESENT))
17787 /* Add the loopback capability */
17788 features |= NETIF_F_LOOPBACK;
17790 dev->hw_features |= features;
17791 dev->priv_flags |= IFF_UNICAST_FLT;
17793 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17794 !tg3_flag(tp, TSO_CAPABLE) &&
17795 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17796 tg3_flag_set(tp, MAX_RXPEND_64);
17797 tp->rx_pending = 63;
17800 err = tg3_get_device_address(tp);
17802 dev_err(&pdev->dev,
17803 "Could not obtain valid ethernet address, aborting\n");
17804 goto err_out_apeunmap;
17807 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17808 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17809 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17810 for (i = 0; i < tp->irq_max; i++) {
17811 struct tg3_napi *tnapi = &tp->napi[i];
17814 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17816 tnapi->int_mbox = intmbx;
17822 tnapi->consmbox = rcvmbx;
17823 tnapi->prodmbox = sndmbx;
17826 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17828 tnapi->coal_now = HOSTCC_MODE_NOW;
17830 if (!tg3_flag(tp, SUPPORT_MSIX))
17834 * If we support MSIX, we'll be using RSS. If we're using
17835 * RSS, the first vector only handles link interrupts and the
17836 * remaining vectors handle rx and tx interrupts. Reuse the
17837 * mailbox values for the next iteration. The values we setup
17838 * above are still useful for the single vectored mode.
17852 * Reset chip in case UNDI or EFI driver did not shutdown
17853 * DMA self test will enable WDMAC and we'll see (spurious)
17854 * pending DMA on the PCI bus at that point.
17856 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17857 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17858 tg3_full_lock(tp, 0);
17859 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17860 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17861 tg3_full_unlock(tp);
17864 err = tg3_test_dma(tp);
17866 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17867 goto err_out_apeunmap;
17872 pci_set_drvdata(pdev, dev);
17874 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17875 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17876 tg3_asic_rev(tp) == ASIC_REV_5762)
17877 tg3_flag_set(tp, PTP_CAPABLE);
17879 tg3_timer_init(tp);
17881 tg3_carrier_off(tp);
17883 err = register_netdev(dev);
17885 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17886 goto err_out_apeunmap;
17889 if (tg3_flag(tp, PTP_CAPABLE)) {
17891 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
17893 if (IS_ERR(tp->ptp_clock))
17894 tp->ptp_clock = NULL;
17897 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17898 tp->board_part_number,
17899 tg3_chip_rev_id(tp),
17900 tg3_bus_string(tp, str),
17903 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17904 struct phy_device *phydev;
17905 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17907 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17908 phydev->drv->name, dev_name(&phydev->dev));
17912 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17913 ethtype = "10/100Base-TX";
17914 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17915 ethtype = "1000Base-SX";
17917 ethtype = "10/100/1000Base-T";
17919 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17920 "(WireSpeed[%d], EEE[%d])\n",
17921 tg3_phy_string(tp), ethtype,
17922 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17923 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17926 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17927 (dev->features & NETIF_F_RXCSUM) != 0,
17928 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17929 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17930 tg3_flag(tp, ENABLE_ASF) != 0,
17931 tg3_flag(tp, TSO_CAPABLE) != 0);
17932 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17934 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17935 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17937 pci_save_state(pdev);
17943 iounmap(tp->aperegs);
17944 tp->aperegs = NULL;
17957 pci_release_regions(pdev);
17959 err_out_disable_pdev:
17960 if (pci_is_enabled(pdev))
17961 pci_disable_device(pdev);
17965 static void tg3_remove_one(struct pci_dev *pdev)
17967 struct net_device *dev = pci_get_drvdata(pdev);
17970 struct tg3 *tp = netdev_priv(dev);
17974 release_firmware(tp->fw);
17976 tg3_reset_task_cancel(tp);
17978 if (tg3_flag(tp, USE_PHYLIB)) {
17983 unregister_netdev(dev);
17985 iounmap(tp->aperegs);
17986 tp->aperegs = NULL;
17993 pci_release_regions(pdev);
17994 pci_disable_device(pdev);
17998 #ifdef CONFIG_PM_SLEEP
17999 static int tg3_suspend(struct device *device)
18001 struct pci_dev *pdev = to_pci_dev(device);
18002 struct net_device *dev = pci_get_drvdata(pdev);
18003 struct tg3 *tp = netdev_priv(dev);
18008 if (!netif_running(dev))
18011 tg3_reset_task_cancel(tp);
18013 tg3_netif_stop(tp);
18015 tg3_timer_stop(tp);
18017 tg3_full_lock(tp, 1);
18018 tg3_disable_ints(tp);
18019 tg3_full_unlock(tp);
18021 netif_device_detach(dev);
18023 tg3_full_lock(tp, 0);
18024 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
18025 tg3_flag_clear(tp, INIT_COMPLETE);
18026 tg3_full_unlock(tp);
18028 err = tg3_power_down_prepare(tp);
18032 tg3_full_lock(tp, 0);
18034 tg3_flag_set(tp, INIT_COMPLETE);
18035 err2 = tg3_restart_hw(tp, true);
18039 tg3_timer_start(tp);
18041 netif_device_attach(dev);
18042 tg3_netif_start(tp);
18045 tg3_full_unlock(tp);
18056 static int tg3_resume(struct device *device)
18058 struct pci_dev *pdev = to_pci_dev(device);
18059 struct net_device *dev = pci_get_drvdata(pdev);
18060 struct tg3 *tp = netdev_priv(dev);
18065 if (!netif_running(dev))
18068 netif_device_attach(dev);
18070 tg3_full_lock(tp, 0);
18072 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18074 tg3_flag_set(tp, INIT_COMPLETE);
18075 err = tg3_restart_hw(tp,
18076 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18080 tg3_timer_start(tp);
18082 tg3_netif_start(tp);
18085 tg3_full_unlock(tp);
18094 #endif /* CONFIG_PM_SLEEP */
18096 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18098 static void tg3_shutdown(struct pci_dev *pdev)
18100 struct net_device *dev = pci_get_drvdata(pdev);
18101 struct tg3 *tp = netdev_priv(dev);
18104 netif_device_detach(dev);
18106 if (netif_running(dev))
18109 if (system_state == SYSTEM_POWER_OFF)
18110 tg3_power_down(tp);
18116 * tg3_io_error_detected - called when PCI error is detected
18117 * @pdev: Pointer to PCI device
18118 * @state: The current pci connection state
18120 * This function is called after a PCI bus error affecting
18121 * this device has been detected.
18123 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18124 pci_channel_state_t state)
18126 struct net_device *netdev = pci_get_drvdata(pdev);
18127 struct tg3 *tp = netdev_priv(netdev);
18128 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18130 netdev_info(netdev, "PCI I/O error detected\n");
18134 tp->pcierr_recovery = true;
18136 /* We probably don't have netdev yet */
18137 if (!netdev || !netif_running(netdev))
18142 tg3_netif_stop(tp);
18144 tg3_timer_stop(tp);
18146 /* Want to make sure that the reset task doesn't run */
18147 tg3_reset_task_cancel(tp);
18149 netif_device_detach(netdev);
18151 /* Clean up software state, even if MMIO is blocked */
18152 tg3_full_lock(tp, 0);
18153 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18154 tg3_full_unlock(tp);
18157 if (state == pci_channel_io_perm_failure) {
18159 tg3_napi_enable(tp);
18162 err = PCI_ERS_RESULT_DISCONNECT;
18164 pci_disable_device(pdev);
18173 * tg3_io_slot_reset - called after the pci bus has been reset.
18174 * @pdev: Pointer to PCI device
18176 * Restart the card from scratch, as if from a cold-boot.
18177 * At this point, the card has exprienced a hard reset,
18178 * followed by fixups by BIOS, and has its config space
18179 * set up identically to what it was at cold boot.
18181 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18183 struct net_device *netdev = pci_get_drvdata(pdev);
18184 struct tg3 *tp = netdev_priv(netdev);
18185 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18190 if (pci_enable_device(pdev)) {
18191 dev_err(&pdev->dev,
18192 "Cannot re-enable PCI device after reset.\n");
18196 pci_set_master(pdev);
18197 pci_restore_state(pdev);
18198 pci_save_state(pdev);
18200 if (!netdev || !netif_running(netdev)) {
18201 rc = PCI_ERS_RESULT_RECOVERED;
18205 err = tg3_power_up(tp);
18209 rc = PCI_ERS_RESULT_RECOVERED;
18212 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18213 tg3_napi_enable(tp);
18222 * tg3_io_resume - called when traffic can start flowing again.
18223 * @pdev: Pointer to PCI device
18225 * This callback is called when the error recovery driver tells
18226 * us that its OK to resume normal operation.
18228 static void tg3_io_resume(struct pci_dev *pdev)
18230 struct net_device *netdev = pci_get_drvdata(pdev);
18231 struct tg3 *tp = netdev_priv(netdev);
18236 if (!netif_running(netdev))
18239 tg3_full_lock(tp, 0);
18240 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18241 tg3_flag_set(tp, INIT_COMPLETE);
18242 err = tg3_restart_hw(tp, true);
18244 tg3_full_unlock(tp);
18245 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18249 netif_device_attach(netdev);
18251 tg3_timer_start(tp);
18253 tg3_netif_start(tp);
18255 tg3_full_unlock(tp);
18260 tp->pcierr_recovery = false;
18264 static const struct pci_error_handlers tg3_err_handler = {
18265 .error_detected = tg3_io_error_detected,
18266 .slot_reset = tg3_io_slot_reset,
18267 .resume = tg3_io_resume
18270 static struct pci_driver tg3_driver = {
18271 .name = DRV_MODULE_NAME,
18272 .id_table = tg3_pci_tbl,
18273 .probe = tg3_init_one,
18274 .remove = tg3_remove_one,
18275 .err_handler = &tg3_err_handler,
18276 .driver.pm = &tg3_pm_ops,
18277 .shutdown = tg3_shutdown,
18280 module_pci_driver(tg3_driver);