2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2014 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/ioport.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/ethtool.h>
35 #include <linux/mdio.h>
36 #include <linux/mii.h>
37 #include <linux/phy.h>
38 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
75 return test_bit(flag, bits);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
85 clear_bit(flag, bits);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 137
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "May 11, 2014"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3)
212 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1)
214 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
215 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
217 #define FIRMWARE_TG3 "tigon/tg3.bin"
218 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
219 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
220 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
222 static char version[] =
223 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")";
225 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
226 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
227 MODULE_LICENSE("GPL");
228 MODULE_VERSION(DRV_MODULE_VERSION);
229 MODULE_FIRMWARE(FIRMWARE_TG3);
230 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
231 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
234 module_param(tg3_debug, int, 0);
235 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
240 static const struct pci_device_id tg3_pci_tbl[] = {
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
257 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
258 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901),
260 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
261 TG3_DRV_DATA_FLAG_5705_10_100},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2),
263 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
264 TG3_DRV_DATA_FLAG_5705_10_100},
265 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F),
267 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY |
268 TG3_DRV_DATA_FLAG_5705_10_100},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
272 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F),
275 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
278 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F),
281 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
286 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
287 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
288 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
289 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5787M,
290 PCI_VENDOR_ID_LENOVO,
291 TG3PCI_SUBDEVICE_ID_LENOVO_5787M),
292 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F),
295 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
311 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
312 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
313 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
315 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_A),
316 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
317 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780,
318 PCI_VENDOR_ID_AI, TG3PCI_SUBDEVICE_ID_ACER_57780_B),
319 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
320 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790),
323 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717_C)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57781)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57785)},
330 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57761)},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57765)},
332 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57791),
333 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57795),
335 .driver_data = TG3_DRV_DATA_FLAG_10_100_ONLY},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5719)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5720)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57762)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57766)},
340 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5762)},
341 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5725)},
342 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5727)},
343 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57764)},
344 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57767)},
345 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57787)},
346 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57782)},
347 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57786)},
348 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
349 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
350 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
351 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
352 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
353 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
354 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
359 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
361 static const struct {
362 const char string[ETH_GSTRING_LEN];
363 } ethtool_stats_keys[] = {
366 { "rx_ucast_packets" },
367 { "rx_mcast_packets" },
368 { "rx_bcast_packets" },
370 { "rx_align_errors" },
371 { "rx_xon_pause_rcvd" },
372 { "rx_xoff_pause_rcvd" },
373 { "rx_mac_ctrl_rcvd" },
374 { "rx_xoff_entered" },
375 { "rx_frame_too_long_errors" },
377 { "rx_undersize_packets" },
378 { "rx_in_length_errors" },
379 { "rx_out_length_errors" },
380 { "rx_64_or_less_octet_packets" },
381 { "rx_65_to_127_octet_packets" },
382 { "rx_128_to_255_octet_packets" },
383 { "rx_256_to_511_octet_packets" },
384 { "rx_512_to_1023_octet_packets" },
385 { "rx_1024_to_1522_octet_packets" },
386 { "rx_1523_to_2047_octet_packets" },
387 { "rx_2048_to_4095_octet_packets" },
388 { "rx_4096_to_8191_octet_packets" },
389 { "rx_8192_to_9022_octet_packets" },
396 { "tx_flow_control" },
398 { "tx_single_collisions" },
399 { "tx_mult_collisions" },
401 { "tx_excessive_collisions" },
402 { "tx_late_collisions" },
403 { "tx_collide_2times" },
404 { "tx_collide_3times" },
405 { "tx_collide_4times" },
406 { "tx_collide_5times" },
407 { "tx_collide_6times" },
408 { "tx_collide_7times" },
409 { "tx_collide_8times" },
410 { "tx_collide_9times" },
411 { "tx_collide_10times" },
412 { "tx_collide_11times" },
413 { "tx_collide_12times" },
414 { "tx_collide_13times" },
415 { "tx_collide_14times" },
416 { "tx_collide_15times" },
417 { "tx_ucast_packets" },
418 { "tx_mcast_packets" },
419 { "tx_bcast_packets" },
420 { "tx_carrier_sense_errors" },
424 { "dma_writeq_full" },
425 { "dma_write_prioq_full" },
429 { "rx_threshold_hit" },
431 { "dma_readq_full" },
432 { "dma_read_prioq_full" },
433 { "tx_comp_queue_full" },
435 { "ring_set_send_prod_index" },
436 { "ring_status_update" },
438 { "nic_avoided_irqs" },
439 { "nic_tx_threshold_hit" },
441 { "mbuf_lwm_thresh_hit" },
444 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
445 #define TG3_NVRAM_TEST 0
446 #define TG3_LINK_TEST 1
447 #define TG3_REGISTER_TEST 2
448 #define TG3_MEMORY_TEST 3
449 #define TG3_MAC_LOOPB_TEST 4
450 #define TG3_PHY_LOOPB_TEST 5
451 #define TG3_EXT_LOOPB_TEST 6
452 #define TG3_INTERRUPT_TEST 7
455 static const struct {
456 const char string[ETH_GSTRING_LEN];
457 } ethtool_test_keys[] = {
458 [TG3_NVRAM_TEST] = { "nvram test (online) " },
459 [TG3_LINK_TEST] = { "link test (online) " },
460 [TG3_REGISTER_TEST] = { "register test (offline)" },
461 [TG3_MEMORY_TEST] = { "memory test (offline)" },
462 [TG3_MAC_LOOPB_TEST] = { "mac loopback test (offline)" },
463 [TG3_PHY_LOOPB_TEST] = { "phy loopback test (offline)" },
464 [TG3_EXT_LOOPB_TEST] = { "ext loopback test (offline)" },
465 [TG3_INTERRUPT_TEST] = { "interrupt test (offline)" },
468 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
473 writel(val, tp->regs + off);
476 static u32 tg3_read32(struct tg3 *tp, u32 off)
478 return readl(tp->regs + off);
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
483 writel(val, tp->aperegs + off);
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
488 return readl(tp->aperegs + off);
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
495 spin_lock_irqsave(&tp->indirect_lock, flags);
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
503 writel(val, tp->regs + off);
504 readl(tp->regs + off);
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
512 spin_lock_irqsave(&tp->indirect_lock, flags);
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
515 spin_unlock_irqrestore(&tp->indirect_lock, flags);
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
523 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
525 TG3_64BIT_REG_LOW, val);
528 if (off == TG3_RX_STD_PROD_IDX_REG) {
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
530 TG3_64BIT_REG_LOW, val);
534 spin_lock_irqsave(&tp->indirect_lock, flags);
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
537 spin_unlock_irqrestore(&tp->indirect_lock, flags);
539 /* In indirect mode when disabling interrupts, we also need
540 * to clear the interrupt bit in the GRC local ctrl register.
542 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
554 spin_lock_irqsave(&tp->indirect_lock, flags);
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
557 spin_unlock_irqrestore(&tp->indirect_lock, flags);
561 /* usec_wait specifies the wait time in usec when writing to certain registers
562 * where it is unsafe to read back the register without some delay.
563 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
564 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND))
569 /* Non-posted methods */
570 tp->write32(tp, off, val);
573 tg3_write32(tp, off, val);
578 /* Wait again after the read for the posted method to guarantee that
579 * the wait time is met.
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
587 tp->write32_mbox(tp, off, val);
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) ||
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) &&
590 !tg3_flag(tp, ICH_WORKAROUND)))
591 tp->read32_mbox(tp, off);
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
596 void __iomem *mbox = tp->regs + off;
598 if (tg3_flag(tp, TXD_MBOX_HWBUG))
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) ||
601 tg3_flag(tp, FLUSH_POSTED_WRITES))
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
607 return readl(tp->regs + off + GRCMBOX_BASE);
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
612 writel(val, tp->regs + off + GRCMBOX_BASE);
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
631 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
634 spin_lock_irqsave(&tp->indirect_lock, flags);
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
639 /* Always leave this as zero. */
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
642 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 tw32_f(TG3PCI_MEM_WIN_DATA, val);
645 /* Always leave this as zero. */
646 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
648 spin_unlock_irqrestore(&tp->indirect_lock, flags);
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 &&
656 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
661 spin_lock_irqsave(&tp->indirect_lock, flags);
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) {
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
666 /* Always leave this as zero. */
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
670 *val = tr32(TG3PCI_MEM_WIN_DATA);
672 /* Always leave this as zero. */
673 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
675 spin_unlock_irqrestore(&tp->indirect_lock, flags);
678 static void tg3_ape_lock_init(struct tg3 *tp)
683 if (tg3_asic_rev(tp) == ASIC_REV_5761)
684 regbase = TG3_APE_LOCK_GRANT;
686 regbase = TG3_APE_PER_LOCK_GRANT;
688 /* Make sure the driver hasn't any stale locks. */
689 for (i = TG3_APE_LOCK_PHY0; i <= TG3_APE_LOCK_GPIO; i++) {
691 case TG3_APE_LOCK_PHY0:
692 case TG3_APE_LOCK_PHY1:
693 case TG3_APE_LOCK_PHY2:
694 case TG3_APE_LOCK_PHY3:
695 bit = APE_LOCK_GRANT_DRIVER;
699 bit = APE_LOCK_GRANT_DRIVER;
701 bit = 1 << tp->pci_fn;
703 tg3_ape_write32(tp, regbase + 4 * i, bit);
708 static int tg3_ape_lock(struct tg3 *tp, int locknum)
712 u32 status, req, gnt, bit;
714 if (!tg3_flag(tp, ENABLE_APE))
718 case TG3_APE_LOCK_GPIO:
719 if (tg3_asic_rev(tp) == ASIC_REV_5761)
721 case TG3_APE_LOCK_GRC:
722 case TG3_APE_LOCK_MEM:
724 bit = APE_LOCK_REQ_DRIVER;
726 bit = 1 << tp->pci_fn;
728 case TG3_APE_LOCK_PHY0:
729 case TG3_APE_LOCK_PHY1:
730 case TG3_APE_LOCK_PHY2:
731 case TG3_APE_LOCK_PHY3:
732 bit = APE_LOCK_REQ_DRIVER;
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) {
739 req = TG3_APE_LOCK_REQ;
740 gnt = TG3_APE_LOCK_GRANT;
742 req = TG3_APE_PER_LOCK_REQ;
743 gnt = TG3_APE_PER_LOCK_GRANT;
748 tg3_ape_write32(tp, req + off, bit);
750 /* Wait for up to 1 millisecond to acquire lock. */
751 for (i = 0; i < 100; i++) {
752 status = tg3_ape_read32(tp, gnt + off);
755 if (pci_channel_offline(tp->pdev))
762 /* Revoke the lock request. */
763 tg3_ape_write32(tp, gnt + off, bit);
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
774 if (!tg3_flag(tp, ENABLE_APE))
778 case TG3_APE_LOCK_GPIO:
779 if (tg3_asic_rev(tp) == ASIC_REV_5761)
781 case TG3_APE_LOCK_GRC:
782 case TG3_APE_LOCK_MEM:
784 bit = APE_LOCK_GRANT_DRIVER;
786 bit = 1 << tp->pci_fn;
788 case TG3_APE_LOCK_PHY0:
789 case TG3_APE_LOCK_PHY1:
790 case TG3_APE_LOCK_PHY2:
791 case TG3_APE_LOCK_PHY3:
792 bit = APE_LOCK_GRANT_DRIVER;
798 if (tg3_asic_rev(tp) == ASIC_REV_5761)
799 gnt = TG3_APE_LOCK_GRANT;
801 gnt = TG3_APE_PER_LOCK_GRANT;
803 tg3_ape_write32(tp, gnt + 4 * locknum, bit);
806 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us)
811 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
814 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
815 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
818 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
821 timeout_us -= (timeout_us > 10) ? 10 : timeout_us;
824 return timeout_us ? 0 : -EBUSY;
827 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us)
831 for (i = 0; i < timeout_us / 10; i++) {
832 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
834 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
840 return i == timeout_us / 10;
843 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off,
847 u32 i, bufoff, msgoff, maxlen, apedata;
849 if (!tg3_flag(tp, APE_HAS_NCSI))
852 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
853 if (apedata != APE_SEG_SIG_MAGIC)
856 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
857 if (!(apedata & APE_FW_STATUS_READY))
860 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) +
862 msgoff = bufoff + 2 * sizeof(u32);
863 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN);
868 /* Cap xfer sizes to scratchpad limits. */
869 length = (len > maxlen) ? maxlen : len;
872 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
873 if (!(apedata & APE_FW_STATUS_READY))
876 /* Wait for up to 1 msec for APE to service previous event. */
877 err = tg3_ape_event_lock(tp, 1000);
881 apedata = APE_EVENT_STATUS_DRIVER_EVNT |
882 APE_EVENT_STATUS_SCRTCHPD_READ |
883 APE_EVENT_STATUS_EVENT_PENDING;
884 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata);
886 tg3_ape_write32(tp, bufoff, base_off);
887 tg3_ape_write32(tp, bufoff + sizeof(u32), length);
889 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
890 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
894 if (tg3_ape_wait_for_event(tp, 30000))
897 for (i = 0; length; i += 4, length -= 4) {
898 u32 val = tg3_ape_read32(tp, msgoff + i);
899 memcpy(data, &val, sizeof(u32));
907 static int tg3_ape_send_event(struct tg3 *tp, u32 event)
912 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
913 if (apedata != APE_SEG_SIG_MAGIC)
916 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
917 if (!(apedata & APE_FW_STATUS_READY))
920 /* Wait for up to 1 millisecond for APE to service previous event. */
921 err = tg3_ape_event_lock(tp, 1000);
925 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
926 event | APE_EVENT_STATUS_EVENT_PENDING);
928 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
929 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
934 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
939 if (!tg3_flag(tp, ENABLE_APE))
943 case RESET_KIND_INIT:
944 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
945 APE_HOST_SEG_SIG_MAGIC);
946 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
947 APE_HOST_SEG_LEN_MAGIC);
948 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
949 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
950 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
951 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM, TG3_MIN_NUM));
952 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
953 APE_HOST_BEHAV_NO_PHYLOCK);
954 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE,
955 TG3_APE_HOST_DRVR_STATE_START);
957 event = APE_EVENT_STATUS_STATE_START;
959 case RESET_KIND_SHUTDOWN:
960 /* With the interface we are currently using,
961 * APE does not track driver state. Wiping
962 * out the HOST SEGMENT SIGNATURE forces
963 * the APE to assume OS absent status.
965 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
967 if (device_may_wakeup(&tp->pdev->dev) &&
968 tg3_flag(tp, WOL_ENABLE)) {
969 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED,
970 TG3_APE_HOST_WOL_SPEED_AUTO);
971 apedata = TG3_APE_HOST_DRVR_STATE_WOL;
973 apedata = TG3_APE_HOST_DRVR_STATE_UNLOAD;
975 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata);
977 event = APE_EVENT_STATUS_STATE_UNLOAD;
983 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
985 tg3_ape_send_event(tp, event);
988 static void tg3_disable_ints(struct tg3 *tp)
992 tw32(TG3PCI_MISC_HOST_CTRL,
993 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
994 for (i = 0; i < tp->irq_max; i++)
995 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
998 static void tg3_enable_ints(struct tg3 *tp)
1005 tw32(TG3PCI_MISC_HOST_CTRL,
1006 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
1008 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE;
1009 for (i = 0; i < tp->irq_cnt; i++) {
1010 struct tg3_napi *tnapi = &tp->napi[i];
1012 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1013 if (tg3_flag(tp, 1SHOT_MSI))
1014 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
1016 tp->coal_now |= tnapi->coal_now;
1019 /* Force an initial interrupt */
1020 if (!tg3_flag(tp, TAGGED_STATUS) &&
1021 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
1022 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
1024 tw32(HOSTCC_MODE, tp->coal_now);
1026 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now);
1029 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
1031 struct tg3 *tp = tnapi->tp;
1032 struct tg3_hw_status *sblk = tnapi->hw_status;
1033 unsigned int work_exists = 0;
1035 /* check for phy events */
1036 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
1037 if (sblk->status & SD_STATUS_LINK_CHG)
1041 /* check for TX work to do */
1042 if (sblk->idx[0].tx_consumer != tnapi->tx_cons)
1045 /* check for RX work to do */
1046 if (tnapi->rx_rcb_prod_idx &&
1047 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
1054 * similar to tg3_enable_ints, but it accurately determines whether there
1055 * is new work pending and can return without flushing the PIO write
1056 * which reenables interrupts
1058 static void tg3_int_reenable(struct tg3_napi *tnapi)
1060 struct tg3 *tp = tnapi->tp;
1062 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
1065 /* When doing tagged status, this work check is unnecessary.
1066 * The last_tag we write above tells the chip which piece of
1067 * work we've completed.
1069 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi))
1070 tw32(HOSTCC_MODE, tp->coalesce_mode |
1071 HOSTCC_MODE_ENABLE | tnapi->coal_now);
1074 static void tg3_switch_clocks(struct tg3 *tp)
1077 u32 orig_clock_ctrl;
1079 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS))
1082 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
1084 orig_clock_ctrl = clock_ctrl;
1085 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
1086 CLOCK_CTRL_CLKRUN_OENABLE |
1088 tp->pci_clock_ctrl = clock_ctrl;
1090 if (tg3_flag(tp, 5705_PLUS)) {
1091 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1093 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
1095 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1098 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
1100 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1101 clock_ctrl | (CLOCK_CTRL_ALTCLK),
1104 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
1107 #define PHY_BUSY_LOOPS 5000
1109 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg,
1116 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1118 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1122 tg3_ape_lock(tp, tp->phy_ape_lock);
1126 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1127 MI_COM_PHY_ADDR_MASK);
1128 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1129 MI_COM_REG_ADDR_MASK);
1130 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
1132 tw32_f(MAC_MI_COM, frame_val);
1134 loops = PHY_BUSY_LOOPS;
1135 while (loops != 0) {
1137 frame_val = tr32(MAC_MI_COM);
1139 if ((frame_val & MI_COM_BUSY) == 0) {
1141 frame_val = tr32(MAC_MI_COM);
1149 *val = frame_val & MI_COM_DATA_MASK;
1153 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1154 tw32_f(MAC_MI_MODE, tp->mi_mode);
1158 tg3_ape_unlock(tp, tp->phy_ape_lock);
1163 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
1165 return __tg3_readphy(tp, tp->phy_addr, reg, val);
1168 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg,
1175 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
1176 (reg == MII_CTRL1000 || reg == MII_TG3_AUX_CTRL))
1179 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1181 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1185 tg3_ape_lock(tp, tp->phy_ape_lock);
1187 frame_val = ((phy_addr << MI_COM_PHY_ADDR_SHIFT) &
1188 MI_COM_PHY_ADDR_MASK);
1189 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
1190 MI_COM_REG_ADDR_MASK);
1191 frame_val |= (val & MI_COM_DATA_MASK);
1192 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
1194 tw32_f(MAC_MI_COM, frame_val);
1196 loops = PHY_BUSY_LOOPS;
1197 while (loops != 0) {
1199 frame_val = tr32(MAC_MI_COM);
1200 if ((frame_val & MI_COM_BUSY) == 0) {
1202 frame_val = tr32(MAC_MI_COM);
1212 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1213 tw32_f(MAC_MI_MODE, tp->mi_mode);
1217 tg3_ape_unlock(tp, tp->phy_ape_lock);
1222 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
1224 return __tg3_writephy(tp, tp->phy_addr, reg, val);
1227 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1231 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1235 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1240 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1250 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1254 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1258 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1263 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1267 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1273 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1277 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1279 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1284 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1288 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1290 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1295 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
1299 err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
1300 (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
1301 MII_TG3_AUXCTL_SHDWSEL_MISC);
1303 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
1308 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
1310 if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
1311 set |= MII_TG3_AUXCTL_MISC_WREN;
1313 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
1316 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable)
1321 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
1327 val |= MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1329 val &= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA;
1331 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
1332 val | MII_TG3_AUXCTL_ACTL_TX_6DB);
1337 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val)
1339 return tg3_writephy(tp, MII_TG3_MISC_SHDW,
1340 reg | val | MII_TG3_MISC_SHDW_WREN);
1343 static int tg3_bmcr_reset(struct tg3 *tp)
1348 /* OK, reset it, and poll the BMCR_RESET bit until it
1349 * clears or we time out.
1351 phy_control = BMCR_RESET;
1352 err = tg3_writephy(tp, MII_BMCR, phy_control);
1358 err = tg3_readphy(tp, MII_BMCR, &phy_control);
1362 if ((phy_control & BMCR_RESET) == 0) {
1374 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
1376 struct tg3 *tp = bp->priv;
1379 spin_lock_bh(&tp->lock);
1381 if (__tg3_readphy(tp, mii_id, reg, &val))
1384 spin_unlock_bh(&tp->lock);
1389 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
1391 struct tg3 *tp = bp->priv;
1394 spin_lock_bh(&tp->lock);
1396 if (__tg3_writephy(tp, mii_id, reg, val))
1399 spin_unlock_bh(&tp->lock);
1404 static void tg3_mdio_config_5785(struct tg3 *tp)
1407 struct phy_device *phydev;
1409 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1410 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1411 case PHY_ID_BCM50610:
1412 case PHY_ID_BCM50610M:
1413 val = MAC_PHYCFG2_50610_LED_MODES;
1415 case PHY_ID_BCMAC131:
1416 val = MAC_PHYCFG2_AC131_LED_MODES;
1418 case PHY_ID_RTL8211C:
1419 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
1421 case PHY_ID_RTL8201E:
1422 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
1428 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
1429 tw32(MAC_PHYCFG2, val);
1431 val = tr32(MAC_PHYCFG1);
1432 val &= ~(MAC_PHYCFG1_RGMII_INT |
1433 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
1434 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
1435 tw32(MAC_PHYCFG1, val);
1440 if (!tg3_flag(tp, RGMII_INBAND_DISABLE))
1441 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
1442 MAC_PHYCFG2_FMODE_MASK_MASK |
1443 MAC_PHYCFG2_GMODE_MASK_MASK |
1444 MAC_PHYCFG2_ACT_MASK_MASK |
1445 MAC_PHYCFG2_QUAL_MASK_MASK |
1446 MAC_PHYCFG2_INBAND_ENABLE;
1448 tw32(MAC_PHYCFG2, val);
1450 val = tr32(MAC_PHYCFG1);
1451 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
1452 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
1453 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1454 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1455 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
1456 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1457 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
1459 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1460 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1461 tw32(MAC_PHYCFG1, val);
1463 val = tr32(MAC_EXT_RGMII_MODE);
1464 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1465 MAC_RGMII_MODE_RX_QUALITY |
1466 MAC_RGMII_MODE_RX_ACTIVITY |
1467 MAC_RGMII_MODE_RX_ENG_DET |
1468 MAC_RGMII_MODE_TX_ENABLE |
1469 MAC_RGMII_MODE_TX_LOWPWR |
1470 MAC_RGMII_MODE_TX_RESET);
1471 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) {
1472 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1473 val |= MAC_RGMII_MODE_RX_INT_B |
1474 MAC_RGMII_MODE_RX_QUALITY |
1475 MAC_RGMII_MODE_RX_ACTIVITY |
1476 MAC_RGMII_MODE_RX_ENG_DET;
1477 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1478 val |= MAC_RGMII_MODE_TX_ENABLE |
1479 MAC_RGMII_MODE_TX_LOWPWR |
1480 MAC_RGMII_MODE_TX_RESET;
1482 tw32(MAC_EXT_RGMII_MODE, val);
1485 static void tg3_mdio_start(struct tg3 *tp)
1487 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1488 tw32_f(MAC_MI_MODE, tp->mi_mode);
1491 if (tg3_flag(tp, MDIOBUS_INITED) &&
1492 tg3_asic_rev(tp) == ASIC_REV_5785)
1493 tg3_mdio_config_5785(tp);
1496 static int tg3_mdio_init(struct tg3 *tp)
1500 struct phy_device *phydev;
1502 if (tg3_flag(tp, 5717_PLUS)) {
1505 tp->phy_addr = tp->pci_fn + 1;
1507 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0)
1508 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1510 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1511 TG3_CPMU_PHY_STRAP_IS_SERDES;
1514 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) {
1517 addr = ssb_gige_get_phyaddr(tp->pdev);
1520 tp->phy_addr = addr;
1522 tp->phy_addr = TG3_PHY_MII_ADDR;
1526 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED))
1529 tp->mdio_bus = mdiobus_alloc();
1530 if (tp->mdio_bus == NULL)
1533 tp->mdio_bus->name = "tg3 mdio bus";
1534 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1535 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1536 tp->mdio_bus->priv = tp;
1537 tp->mdio_bus->parent = &tp->pdev->dev;
1538 tp->mdio_bus->read = &tg3_mdio_read;
1539 tp->mdio_bus->write = &tg3_mdio_write;
1540 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr);
1541 tp->mdio_bus->irq = &tp->mdio_irq[0];
1543 for (i = 0; i < PHY_MAX_ADDR; i++)
1544 tp->mdio_bus->irq[i] = PHY_POLL;
1546 /* The bus registration will look for all the PHYs on the mdio bus.
1547 * Unfortunately, it does not ensure the PHY is powered up before
1548 * accessing the PHY ID registers. A chip reset is the
1549 * quickest way to bring the device back to an operational state..
1551 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1554 i = mdiobus_register(tp->mdio_bus);
1556 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i);
1557 mdiobus_free(tp->mdio_bus);
1561 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
1563 if (!phydev || !phydev->drv) {
1564 dev_warn(&tp->pdev->dev, "No PHY devices\n");
1565 mdiobus_unregister(tp->mdio_bus);
1566 mdiobus_free(tp->mdio_bus);
1570 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1571 case PHY_ID_BCM57780:
1572 phydev->interface = PHY_INTERFACE_MODE_GMII;
1573 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1575 case PHY_ID_BCM50610:
1576 case PHY_ID_BCM50610M:
1577 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1578 PHY_BRCM_RX_REFCLK_UNUSED |
1579 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1580 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1581 if (tg3_flag(tp, RGMII_INBAND_DISABLE))
1582 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1583 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN))
1584 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1585 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN))
1586 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1588 case PHY_ID_RTL8211C:
1589 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1591 case PHY_ID_RTL8201E:
1592 case PHY_ID_BCMAC131:
1593 phydev->interface = PHY_INTERFACE_MODE_MII;
1594 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1595 tp->phy_flags |= TG3_PHYFLG_IS_FET;
1599 tg3_flag_set(tp, MDIOBUS_INITED);
1601 if (tg3_asic_rev(tp) == ASIC_REV_5785)
1602 tg3_mdio_config_5785(tp);
1607 static void tg3_mdio_fini(struct tg3 *tp)
1609 if (tg3_flag(tp, MDIOBUS_INITED)) {
1610 tg3_flag_clear(tp, MDIOBUS_INITED);
1611 mdiobus_unregister(tp->mdio_bus);
1612 mdiobus_free(tp->mdio_bus);
1616 /* tp->lock is held. */
1617 static inline void tg3_generate_fw_event(struct tg3 *tp)
1621 val = tr32(GRC_RX_CPU_EVENT);
1622 val |= GRC_RX_CPU_DRIVER_EVENT;
1623 tw32_f(GRC_RX_CPU_EVENT, val);
1625 tp->last_event_jiffies = jiffies;
1628 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1630 /* tp->lock is held. */
1631 static void tg3_wait_for_event_ack(struct tg3 *tp)
1634 unsigned int delay_cnt;
1637 /* If enough time has passed, no wait is necessary. */
1638 time_remain = (long)(tp->last_event_jiffies + 1 +
1639 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1641 if (time_remain < 0)
1644 /* Check if we can shorten the wait time. */
1645 delay_cnt = jiffies_to_usecs(time_remain);
1646 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1647 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1648 delay_cnt = (delay_cnt >> 3) + 1;
1650 for (i = 0; i < delay_cnt; i++) {
1651 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1653 if (pci_channel_offline(tp->pdev))
1660 /* tp->lock is held. */
1661 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data)
1666 if (!tg3_readphy(tp, MII_BMCR, ®))
1668 if (!tg3_readphy(tp, MII_BMSR, ®))
1669 val |= (reg & 0xffff);
1673 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1675 if (!tg3_readphy(tp, MII_LPA, ®))
1676 val |= (reg & 0xffff);
1680 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1681 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1683 if (!tg3_readphy(tp, MII_STAT1000, ®))
1684 val |= (reg & 0xffff);
1688 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1695 /* tp->lock is held. */
1696 static void tg3_ump_link_report(struct tg3 *tp)
1700 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1703 tg3_phy_gather_ump_data(tp, data);
1705 tg3_wait_for_event_ack(tp);
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]);
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]);
1711 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]);
1712 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]);
1714 tg3_generate_fw_event(tp);
1717 /* tp->lock is held. */
1718 static void tg3_stop_fw(struct tg3 *tp)
1720 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
1721 /* Wait for RX cpu to ACK the previous event. */
1722 tg3_wait_for_event_ack(tp);
1724 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1726 tg3_generate_fw_event(tp);
1728 /* Wait for RX cpu to ACK this event. */
1729 tg3_wait_for_event_ack(tp);
1733 /* tp->lock is held. */
1734 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
1736 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
1737 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1739 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1741 case RESET_KIND_INIT:
1742 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1746 case RESET_KIND_SHUTDOWN:
1747 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1751 case RESET_KIND_SUSPEND:
1752 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1762 /* tp->lock is held. */
1763 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
1765 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) {
1767 case RESET_KIND_INIT:
1768 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1769 DRV_STATE_START_DONE);
1772 case RESET_KIND_SHUTDOWN:
1773 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1774 DRV_STATE_UNLOAD_DONE);
1783 /* tp->lock is held. */
1784 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
1786 if (tg3_flag(tp, ENABLE_ASF)) {
1788 case RESET_KIND_INIT:
1789 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1793 case RESET_KIND_SHUTDOWN:
1794 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1798 case RESET_KIND_SUSPEND:
1799 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
1809 static int tg3_poll_fw(struct tg3 *tp)
1814 if (tg3_flag(tp, NO_FWARE_REPORTED))
1817 if (tg3_flag(tp, IS_SSB_CORE)) {
1818 /* We don't use firmware. */
1822 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
1823 /* Wait up to 20ms for init done. */
1824 for (i = 0; i < 200; i++) {
1825 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
1827 if (pci_channel_offline(tp->pdev))
1835 /* Wait for firmware initialization to complete. */
1836 for (i = 0; i < 100000; i++) {
1837 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
1838 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1840 if (pci_channel_offline(tp->pdev)) {
1841 if (!tg3_flag(tp, NO_FWARE_REPORTED)) {
1842 tg3_flag_set(tp, NO_FWARE_REPORTED);
1843 netdev_info(tp->dev, "No firmware running\n");
1852 /* Chip might not be fitted with firmware. Some Sun onboard
1853 * parts are configured like that. So don't signal the timeout
1854 * of the above loop as an error, but do report the lack of
1855 * running firmware once.
1857 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) {
1858 tg3_flag_set(tp, NO_FWARE_REPORTED);
1860 netdev_info(tp->dev, "No firmware running\n");
1863 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
1864 /* The 57765 A0 needs a little more
1865 * time to do some important work.
1873 static void tg3_link_report(struct tg3 *tp)
1875 if (!netif_carrier_ok(tp->dev)) {
1876 netif_info(tp, link, tp->dev, "Link is down\n");
1877 tg3_ump_link_report(tp);
1878 } else if (netif_msg_link(tp)) {
1879 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1880 (tp->link_config.active_speed == SPEED_1000 ?
1882 (tp->link_config.active_speed == SPEED_100 ?
1884 (tp->link_config.active_duplex == DUPLEX_FULL ?
1887 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n",
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1890 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1893 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1894 netdev_info(tp->dev, "EEE is %s\n",
1895 tp->setlpicnt ? "enabled" : "disabled");
1897 tg3_ump_link_report(tp);
1900 tp->link_up = netif_carrier_ok(tp->dev);
1903 static u32 tg3_decode_flowctrl_1000T(u32 adv)
1907 if (adv & ADVERTISE_PAUSE_CAP) {
1908 flowctrl |= FLOW_CTRL_RX;
1909 if (!(adv & ADVERTISE_PAUSE_ASYM))
1910 flowctrl |= FLOW_CTRL_TX;
1911 } else if (adv & ADVERTISE_PAUSE_ASYM)
1912 flowctrl |= FLOW_CTRL_TX;
1917 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1921 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1922 miireg = ADVERTISE_1000XPAUSE;
1923 else if (flow_ctrl & FLOW_CTRL_TX)
1924 miireg = ADVERTISE_1000XPSE_ASYM;
1925 else if (flow_ctrl & FLOW_CTRL_RX)
1926 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1933 static u32 tg3_decode_flowctrl_1000X(u32 adv)
1937 if (adv & ADVERTISE_1000XPAUSE) {
1938 flowctrl |= FLOW_CTRL_RX;
1939 if (!(adv & ADVERTISE_1000XPSE_ASYM))
1940 flowctrl |= FLOW_CTRL_TX;
1941 } else if (adv & ADVERTISE_1000XPSE_ASYM)
1942 flowctrl |= FLOW_CTRL_TX;
1947 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1951 if (lcladv & rmtadv & ADVERTISE_1000XPAUSE) {
1952 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1953 } else if (lcladv & rmtadv & ADVERTISE_1000XPSE_ASYM) {
1954 if (lcladv & ADVERTISE_1000XPAUSE)
1956 if (rmtadv & ADVERTISE_1000XPAUSE)
1963 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1967 u32 old_rx_mode = tp->rx_mode;
1968 u32 old_tx_mode = tp->tx_mode;
1970 if (tg3_flag(tp, USE_PHYLIB))
1971 autoneg = tp->mdio_bus->phy_map[tp->phy_addr]->autoneg;
1973 autoneg = tp->link_config.autoneg;
1975 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) {
1976 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1977 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1979 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1981 flowctrl = tp->link_config.flowctrl;
1983 tp->link_config.active_flowctrl = flowctrl;
1985 if (flowctrl & FLOW_CTRL_RX)
1986 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1988 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1990 if (old_rx_mode != tp->rx_mode)
1991 tw32_f(MAC_RX_MODE, tp->rx_mode);
1993 if (flowctrl & FLOW_CTRL_TX)
1994 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1996 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1998 if (old_tx_mode != tp->tx_mode)
1999 tw32_f(MAC_TX_MODE, tp->tx_mode);
2002 static void tg3_adjust_link(struct net_device *dev)
2004 u8 oldflowctrl, linkmesg = 0;
2005 u32 mac_mode, lcl_adv, rmt_adv;
2006 struct tg3 *tp = netdev_priv(dev);
2007 struct phy_device *phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2009 spin_lock_bh(&tp->lock);
2011 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
2012 MAC_MODE_HALF_DUPLEX);
2014 oldflowctrl = tp->link_config.active_flowctrl;
2020 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
2021 mac_mode |= MAC_MODE_PORT_MODE_MII;
2022 else if (phydev->speed == SPEED_1000 ||
2023 tg3_asic_rev(tp) != ASIC_REV_5785)
2024 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2026 mac_mode |= MAC_MODE_PORT_MODE_MII;
2028 if (phydev->duplex == DUPLEX_HALF)
2029 mac_mode |= MAC_MODE_HALF_DUPLEX;
2031 lcl_adv = mii_advertise_flowctrl(
2032 tp->link_config.flowctrl);
2035 rmt_adv = LPA_PAUSE_CAP;
2036 if (phydev->asym_pause)
2037 rmt_adv |= LPA_PAUSE_ASYM;
2040 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
2042 mac_mode |= MAC_MODE_PORT_MODE_GMII;
2044 if (mac_mode != tp->mac_mode) {
2045 tp->mac_mode = mac_mode;
2046 tw32_f(MAC_MODE, tp->mac_mode);
2050 if (tg3_asic_rev(tp) == ASIC_REV_5785) {
2051 if (phydev->speed == SPEED_10)
2053 MAC_MI_STAT_10MBPS_MODE |
2054 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2056 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2059 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
2060 tw32(MAC_TX_LENGTHS,
2061 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2062 (6 << TX_LENGTHS_IPG_SHIFT) |
2063 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2065 tw32(MAC_TX_LENGTHS,
2066 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2067 (6 << TX_LENGTHS_IPG_SHIFT) |
2068 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2070 if (phydev->link != tp->old_link ||
2071 phydev->speed != tp->link_config.active_speed ||
2072 phydev->duplex != tp->link_config.active_duplex ||
2073 oldflowctrl != tp->link_config.active_flowctrl)
2076 tp->old_link = phydev->link;
2077 tp->link_config.active_speed = phydev->speed;
2078 tp->link_config.active_duplex = phydev->duplex;
2080 spin_unlock_bh(&tp->lock);
2083 tg3_link_report(tp);
2086 static int tg3_phy_init(struct tg3 *tp)
2088 struct phy_device *phydev;
2090 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)
2093 /* Bring the PHY back to a known state. */
2096 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2098 /* Attach the MAC to the PHY. */
2099 phydev = phy_connect(tp->dev, dev_name(&phydev->dev),
2100 tg3_adjust_link, phydev->interface);
2101 if (IS_ERR(phydev)) {
2102 dev_err(&tp->pdev->dev, "Could not attach to PHY\n");
2103 return PTR_ERR(phydev);
2106 /* Mask with MAC supported features. */
2107 switch (phydev->interface) {
2108 case PHY_INTERFACE_MODE_GMII:
2109 case PHY_INTERFACE_MODE_RGMII:
2110 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
2111 phydev->supported &= (PHY_GBIT_FEATURES |
2113 SUPPORTED_Asym_Pause);
2117 case PHY_INTERFACE_MODE_MII:
2118 phydev->supported &= (PHY_BASIC_FEATURES |
2120 SUPPORTED_Asym_Pause);
2123 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2127 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED;
2129 phydev->advertising = phydev->supported;
2134 static void tg3_phy_start(struct tg3 *tp)
2136 struct phy_device *phydev;
2138 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2141 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
2143 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
2144 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
2145 phydev->speed = tp->link_config.speed;
2146 phydev->duplex = tp->link_config.duplex;
2147 phydev->autoneg = tp->link_config.autoneg;
2148 phydev->advertising = tp->link_config.advertising;
2153 phy_start_aneg(phydev);
2156 static void tg3_phy_stop(struct tg3 *tp)
2158 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
2161 phy_stop(tp->mdio_bus->phy_map[tp->phy_addr]);
2164 static void tg3_phy_fini(struct tg3 *tp)
2166 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
2167 phy_disconnect(tp->mdio_bus->phy_map[tp->phy_addr]);
2168 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED;
2172 static int tg3_phy_set_extloopbk(struct tg3 *tp)
2177 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
2180 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2181 /* Cannot do read-modify-write on 5401 */
2182 err = tg3_phy_auxctl_write(tp,
2183 MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2184 MII_TG3_AUXCTL_ACTL_EXTLOOPBK |
2189 err = tg3_phy_auxctl_read(tp,
2190 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2194 val |= MII_TG3_AUXCTL_ACTL_EXTLOOPBK;
2195 err = tg3_phy_auxctl_write(tp,
2196 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, val);
2202 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
2206 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2209 tg3_writephy(tp, MII_TG3_FET_TEST,
2210 phytest | MII_TG3_FET_SHADOW_EN);
2211 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
2213 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
2215 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
2216 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
2218 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2222 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
2226 if (!tg3_flag(tp, 5705_PLUS) ||
2227 (tg3_flag(tp, 5717_PLUS) &&
2228 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)))
2231 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2232 tg3_phy_fet_toggle_apd(tp, enable);
2236 reg = MII_TG3_MISC_SHDW_SCR5_LPED |
2237 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
2238 MII_TG3_MISC_SHDW_SCR5_SDTL |
2239 MII_TG3_MISC_SHDW_SCR5_C125OE;
2240 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable)
2241 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
2243 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg);
2246 reg = MII_TG3_MISC_SHDW_APD_WKTM_84MS;
2248 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
2250 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg);
2253 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable)
2257 if (!tg3_flag(tp, 5705_PLUS) ||
2258 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
2261 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
2264 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
2265 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
2267 tg3_writephy(tp, MII_TG3_FET_TEST,
2268 ephy | MII_TG3_FET_SHADOW_EN);
2269 if (!tg3_readphy(tp, reg, &phy)) {
2271 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2273 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
2274 tg3_writephy(tp, reg, phy);
2276 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
2281 ret = tg3_phy_auxctl_read(tp,
2282 MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
2285 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2287 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
2288 tg3_phy_auxctl_write(tp,
2289 MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
2294 static void tg3_phy_set_wirespeed(struct tg3 *tp)
2299 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
2302 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
2304 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
2305 val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
2308 static void tg3_phy_apply_otp(struct tg3 *tp)
2317 if (tg3_phy_toggle_auxctl_smdsp(tp, true))
2320 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
2321 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
2322 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
2324 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
2325 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
2328 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
2329 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
2330 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
2332 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
2335 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
2338 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
2339 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
2340 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
2342 tg3_phy_toggle_auxctl_smdsp(tp, false);
2345 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee)
2348 struct ethtool_eee *dest = &tp->eee;
2350 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2356 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val))
2359 /* Pull eee_active */
2360 if (val == TG3_CL45_D7_EEERES_STAT_LP_1000T ||
2361 val == TG3_CL45_D7_EEERES_STAT_LP_100TX) {
2362 dest->eee_active = 1;
2364 dest->eee_active = 0;
2366 /* Pull lp advertised settings */
2367 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val))
2369 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2371 /* Pull advertised and eee_enabled settings */
2372 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val))
2374 dest->eee_enabled = !!val;
2375 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
2377 /* Pull tx_lpi_enabled */
2378 val = tr32(TG3_CPMU_EEE_MODE);
2379 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX);
2381 /* Pull lpi timer value */
2382 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff;
2385 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up)
2389 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
2394 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2396 tp->link_config.active_duplex == DUPLEX_FULL &&
2397 (tp->link_config.active_speed == SPEED_100 ||
2398 tp->link_config.active_speed == SPEED_1000)) {
2401 if (tp->link_config.active_speed == SPEED_1000)
2402 eeectl = TG3_CPMU_EEE_CTRL_EXIT_16_5_US;
2404 eeectl = TG3_CPMU_EEE_CTRL_EXIT_36_US;
2406 tw32(TG3_CPMU_EEE_CTRL, eeectl);
2408 tg3_eee_pull_config(tp, NULL);
2409 if (tp->eee.eee_active)
2413 if (!tp->setlpicnt) {
2414 if (current_link_up &&
2415 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2416 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);
2417 tg3_phy_toggle_auxctl_smdsp(tp, false);
2420 val = tr32(TG3_CPMU_EEE_MODE);
2421 tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE);
2425 static void tg3_phy_eee_enable(struct tg3 *tp)
2429 if (tp->link_config.active_speed == SPEED_1000 &&
2430 (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2431 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2432 tg3_flag(tp, 57765_CLASS)) &&
2433 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2434 val = MII_TG3_DSP_TAP26_ALNOKO |
2435 MII_TG3_DSP_TAP26_RMRXSTO;
2436 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
2437 tg3_phy_toggle_auxctl_smdsp(tp, false);
2440 val = tr32(TG3_CPMU_EEE_MODE);
2441 tw32(TG3_CPMU_EEE_MODE, val | TG3_CPMU_EEEMD_LPI_ENABLE);
2444 static int tg3_wait_macro_done(struct tg3 *tp)
2451 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
2452 if ((tmp32 & 0x1000) == 0)
2462 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
2464 static const u32 test_pat[4][6] = {
2465 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2466 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2467 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2468 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2472 for (chan = 0; chan < 4; chan++) {
2475 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2476 (chan * 0x2000) | 0x0200);
2477 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2479 for (i = 0; i < 6; i++)
2480 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
2483 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2484 if (tg3_wait_macro_done(tp)) {
2489 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2490 (chan * 0x2000) | 0x0200);
2491 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
2492 if (tg3_wait_macro_done(tp)) {
2497 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
2498 if (tg3_wait_macro_done(tp)) {
2503 for (i = 0; i < 6; i += 2) {
2506 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
2507 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
2508 tg3_wait_macro_done(tp)) {
2514 if (low != test_pat[chan][i] ||
2515 high != test_pat[chan][i+1]) {
2516 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
2517 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
2518 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
2528 static int tg3_phy_reset_chanpat(struct tg3 *tp)
2532 for (chan = 0; chan < 4; chan++) {
2535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
2536 (chan * 0x2000) | 0x0200);
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
2538 for (i = 0; i < 6; i++)
2539 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
2540 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
2541 if (tg3_wait_macro_done(tp))
2548 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
2550 u32 reg32, phy9_orig;
2551 int retries, do_phy_reset, err;
2557 err = tg3_bmcr_reset(tp);
2563 /* Disable transmitter and interrupt. */
2564 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
2568 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2570 /* Set full-duplex, 1000 mbps. */
2571 tg3_writephy(tp, MII_BMCR,
2572 BMCR_FULLDPLX | BMCR_SPEED1000);
2574 /* Set to master mode. */
2575 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig))
2578 tg3_writephy(tp, MII_CTRL1000,
2579 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
2581 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
2585 /* Block the PHY control access. */
2586 tg3_phydsp_write(tp, 0x8005, 0x0800);
2588 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
2591 } while (--retries);
2593 err = tg3_phy_reset_chanpat(tp);
2597 tg3_phydsp_write(tp, 0x8005, 0x0000);
2599 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
2600 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
2602 tg3_phy_toggle_auxctl_smdsp(tp, false);
2604 tg3_writephy(tp, MII_CTRL1000, phy9_orig);
2606 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32);
2611 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
2616 static void tg3_carrier_off(struct tg3 *tp)
2618 netif_carrier_off(tp->dev);
2619 tp->link_up = false;
2622 static void tg3_warn_mgmt_link_flap(struct tg3 *tp)
2624 if (tg3_flag(tp, ENABLE_ASF))
2625 netdev_warn(tp->dev,
2626 "Management side-band traffic will be interrupted during phy settings change\n");
2629 /* This will reset the tigon3 PHY if there is no valid
2630 * link unless the FORCE argument is non-zero.
2632 static int tg3_phy_reset(struct tg3 *tp)
2637 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2638 val = tr32(GRC_MISC_CFG);
2639 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2642 err = tg3_readphy(tp, MII_BMSR, &val);
2643 err |= tg3_readphy(tp, MII_BMSR, &val);
2647 if (netif_running(tp->dev) && tp->link_up) {
2648 netif_carrier_off(tp->dev);
2649 tg3_link_report(tp);
2652 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
2653 tg3_asic_rev(tp) == ASIC_REV_5704 ||
2654 tg3_asic_rev(tp) == ASIC_REV_5705) {
2655 err = tg3_phy_reset_5703_4_5(tp);
2662 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
2663 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
2664 cpmuctrl = tr32(TG3_CPMU_CTRL);
2665 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
2667 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
2670 err = tg3_bmcr_reset(tp);
2674 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
2675 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
2676 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
2678 tw32(TG3_CPMU_CTRL, cpmuctrl);
2681 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
2682 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
2683 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2684 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
2685 CPMU_LSPD_1000MB_MACCLK_12_5) {
2686 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2688 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2692 if (tg3_flag(tp, 5717_PLUS) &&
2693 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
2696 tg3_phy_apply_otp(tp);
2698 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
2699 tg3_phy_toggle_apd(tp, true);
2701 tg3_phy_toggle_apd(tp, false);
2704 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
2705 !tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2706 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
2707 tg3_phydsp_write(tp, 0x000a, 0x0323);
2708 tg3_phy_toggle_auxctl_smdsp(tp, false);
2711 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
2712 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2713 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
2716 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
2717 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2718 tg3_phydsp_write(tp, 0x000a, 0x310b);
2719 tg3_phydsp_write(tp, 0x201f, 0x9506);
2720 tg3_phydsp_write(tp, 0x401f, 0x14e2);
2721 tg3_phy_toggle_auxctl_smdsp(tp, false);
2723 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
2724 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) {
2725 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
2726 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
2728 tg3_writephy(tp, MII_TG3_TEST1,
2729 MII_TG3_TEST1_TRIM_EN | 0x4);
2731 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
2733 tg3_phy_toggle_auxctl_smdsp(tp, false);
2737 /* Set Extended packet length bit (bit 14) on all chips that */
2738 /* support jumbo frames */
2739 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
2740 /* Cannot do read-modify-write on 5401 */
2741 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
2742 } else if (tg3_flag(tp, JUMBO_CAPABLE)) {
2743 /* Set bit 14 with read-modify-write to preserve other bits */
2744 err = tg3_phy_auxctl_read(tp,
2745 MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val);
2747 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL,
2748 val | MII_TG3_AUXCTL_ACTL_EXTPKTLEN);
2751 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2752 * jumbo frames transmission.
2754 if (tg3_flag(tp, JUMBO_CAPABLE)) {
2755 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val))
2756 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2757 val | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2760 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
2761 /* adjust output voltage */
2762 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2765 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0)
2766 tg3_phydsp_write(tp, 0xffb, 0x4000);
2768 tg3_phy_toggle_automdix(tp, true);
2769 tg3_phy_set_wirespeed(tp);
2773 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2774 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2775 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2776 TG3_GPIO_MSG_NEED_VAUX)
2777 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2778 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2779 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2780 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2781 (TG3_GPIO_MSG_DRVR_PRES << 12))
2783 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2784 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2785 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2786 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2787 (TG3_GPIO_MSG_NEED_VAUX << 12))
2789 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat)
2793 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2794 tg3_asic_rev(tp) == ASIC_REV_5719)
2795 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG);
2797 status = tr32(TG3_CPMU_DRV_STATUS);
2799 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn;
2800 status &= ~(TG3_GPIO_MSG_MASK << shift);
2801 status |= (newstat << shift);
2803 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2804 tg3_asic_rev(tp) == ASIC_REV_5719)
2805 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status);
2807 tw32(TG3_CPMU_DRV_STATUS, status);
2809 return status >> TG3_APE_GPIO_MSG_SHIFT;
2812 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp)
2814 if (!tg3_flag(tp, IS_NIC))
2817 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2818 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2819 tg3_asic_rev(tp) == ASIC_REV_5720) {
2820 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2823 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES);
2825 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2826 TG3_GRC_LCLCTL_PWRSW_DELAY);
2828 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2830 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY);
2837 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp)
2841 if (!tg3_flag(tp, IS_NIC) ||
2842 tg3_asic_rev(tp) == ASIC_REV_5700 ||
2843 tg3_asic_rev(tp) == ASIC_REV_5701)
2846 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1;
2848 tw32_wait_f(GRC_LOCAL_CTRL,
2849 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2850 TG3_GRC_LCLCTL_PWRSW_DELAY);
2852 tw32_wait_f(GRC_LOCAL_CTRL,
2854 TG3_GRC_LCLCTL_PWRSW_DELAY);
2856 tw32_wait_f(GRC_LOCAL_CTRL,
2857 grc_local_ctrl | GRC_LCLCTRL_GPIO_OUTPUT1,
2858 TG3_GRC_LCLCTL_PWRSW_DELAY);
2861 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp)
2863 if (!tg3_flag(tp, IS_NIC))
2866 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
2867 tg3_asic_rev(tp) == ASIC_REV_5701) {
2868 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2869 (GRC_LCLCTRL_GPIO_OE0 |
2870 GRC_LCLCTRL_GPIO_OE1 |
2871 GRC_LCLCTRL_GPIO_OE2 |
2872 GRC_LCLCTRL_GPIO_OUTPUT0 |
2873 GRC_LCLCTRL_GPIO_OUTPUT1),
2874 TG3_GRC_LCLCTL_PWRSW_DELAY);
2875 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2876 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2877 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2878 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2879 GRC_LCLCTRL_GPIO_OE1 |
2880 GRC_LCLCTRL_GPIO_OE2 |
2881 GRC_LCLCTRL_GPIO_OUTPUT0 |
2882 GRC_LCLCTRL_GPIO_OUTPUT1 |
2884 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2885 TG3_GRC_LCLCTL_PWRSW_DELAY);
2887 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2888 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2889 TG3_GRC_LCLCTL_PWRSW_DELAY);
2891 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2892 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl,
2893 TG3_GRC_LCLCTL_PWRSW_DELAY);
2896 u32 grc_local_ctrl = 0;
2898 /* Workaround to prevent overdrawing Amps. */
2899 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
2900 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2901 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2903 TG3_GRC_LCLCTL_PWRSW_DELAY);
2906 /* On 5753 and variants, GPIO2 cannot be used. */
2907 no_gpio2 = tp->nic_sram_data_cfg &
2908 NIC_SRAM_DATA_CFG_NO_GPIO2;
2910 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2911 GRC_LCLCTRL_GPIO_OE1 |
2912 GRC_LCLCTRL_GPIO_OE2 |
2913 GRC_LCLCTRL_GPIO_OUTPUT1 |
2914 GRC_LCLCTRL_GPIO_OUTPUT2;
2916 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2917 GRC_LCLCTRL_GPIO_OUTPUT2);
2919 tw32_wait_f(GRC_LOCAL_CTRL,
2920 tp->grc_local_ctrl | grc_local_ctrl,
2921 TG3_GRC_LCLCTL_PWRSW_DELAY);
2923 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2925 tw32_wait_f(GRC_LOCAL_CTRL,
2926 tp->grc_local_ctrl | grc_local_ctrl,
2927 TG3_GRC_LCLCTL_PWRSW_DELAY);
2930 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2931 tw32_wait_f(GRC_LOCAL_CTRL,
2932 tp->grc_local_ctrl | grc_local_ctrl,
2933 TG3_GRC_LCLCTL_PWRSW_DELAY);
2938 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable)
2942 /* Serialize power state transitions */
2943 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO))
2946 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable)
2947 msg = TG3_GPIO_MSG_NEED_VAUX;
2949 msg = tg3_set_function_status(tp, msg);
2951 if (msg & TG3_GPIO_MSG_ALL_DRVR_PRES_MASK)
2954 if (msg & TG3_GPIO_MSG_ALL_NEED_VAUX_MASK)
2955 tg3_pwrsrc_switch_to_vaux(tp);
2957 tg3_pwrsrc_die_with_vmain(tp);
2960 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO);
2963 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol)
2965 bool need_vaux = false;
2967 /* The GPIOs do something completely different on 57765. */
2968 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS))
2971 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
2972 tg3_asic_rev(tp) == ASIC_REV_5719 ||
2973 tg3_asic_rev(tp) == ASIC_REV_5720) {
2974 tg3_frob_aux_power_5717(tp, include_wol ?
2975 tg3_flag(tp, WOL_ENABLE) != 0 : 0);
2979 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) {
2980 struct net_device *dev_peer;
2982 dev_peer = pci_get_drvdata(tp->pdev_peer);
2984 /* remove_one() may have been run on the peer. */
2986 struct tg3 *tp_peer = netdev_priv(dev_peer);
2988 if (tg3_flag(tp_peer, INIT_COMPLETE))
2991 if ((include_wol && tg3_flag(tp_peer, WOL_ENABLE)) ||
2992 tg3_flag(tp_peer, ENABLE_ASF))
2997 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) ||
2998 tg3_flag(tp, ENABLE_ASF))
3002 tg3_pwrsrc_switch_to_vaux(tp);
3004 tg3_pwrsrc_die_with_vmain(tp);
3007 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
3009 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
3011 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
3012 if (speed != SPEED_10)
3014 } else if (speed == SPEED_10)
3020 static bool tg3_phy_power_bug(struct tg3 *tp)
3022 switch (tg3_asic_rev(tp)) {
3027 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
3036 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
3045 static bool tg3_phy_led_bug(struct tg3 *tp)
3047 switch (tg3_asic_rev(tp)) {
3050 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
3059 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
3063 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)
3066 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
3067 if (tg3_asic_rev(tp) == ASIC_REV_5704) {
3068 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3069 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
3072 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
3073 tw32(SG_DIG_CTRL, sg_dig_ctrl);
3074 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
3079 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3081 val = tr32(GRC_MISC_CFG);
3082 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3085 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
3087 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
3090 tg3_writephy(tp, MII_ADVERTISE, 0);
3091 tg3_writephy(tp, MII_BMCR,
3092 BMCR_ANENABLE | BMCR_ANRESTART);
3094 tg3_writephy(tp, MII_TG3_FET_TEST,
3095 phytest | MII_TG3_FET_SHADOW_EN);
3096 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
3097 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
3099 MII_TG3_FET_SHDW_AUXMODE4,
3102 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
3105 } else if (do_low_power) {
3106 if (!tg3_phy_led_bug(tp))
3107 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3108 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
3110 val = MII_TG3_AUXCTL_PCTL_100TX_LPWR |
3111 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
3112 MII_TG3_AUXCTL_PCTL_VREG_11V;
3113 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val);
3116 /* The PHY should not be powered down on some chips because
3119 if (tg3_phy_power_bug(tp))
3122 if (tg3_chip_rev(tp) == CHIPREV_5784_AX ||
3123 tg3_chip_rev(tp) == CHIPREV_5761_AX) {
3124 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
3125 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
3126 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
3127 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3130 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
3133 /* tp->lock is held. */
3134 static int tg3_nvram_lock(struct tg3 *tp)
3136 if (tg3_flag(tp, NVRAM)) {
3139 if (tp->nvram_lock_cnt == 0) {
3140 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
3141 for (i = 0; i < 8000; i++) {
3142 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
3147 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
3151 tp->nvram_lock_cnt++;
3156 /* tp->lock is held. */
3157 static void tg3_nvram_unlock(struct tg3 *tp)
3159 if (tg3_flag(tp, NVRAM)) {
3160 if (tp->nvram_lock_cnt > 0)
3161 tp->nvram_lock_cnt--;
3162 if (tp->nvram_lock_cnt == 0)
3163 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3167 /* tp->lock is held. */
3168 static void tg3_enable_nvram_access(struct tg3 *tp)
3170 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3171 u32 nvaccess = tr32(NVRAM_ACCESS);
3173 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
3177 /* tp->lock is held. */
3178 static void tg3_disable_nvram_access(struct tg3 *tp)
3180 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) {
3181 u32 nvaccess = tr32(NVRAM_ACCESS);
3183 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
3187 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
3188 u32 offset, u32 *val)
3193 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
3196 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
3197 EEPROM_ADDR_DEVID_MASK |
3199 tw32(GRC_EEPROM_ADDR,
3201 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3202 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
3203 EEPROM_ADDR_ADDR_MASK) |
3204 EEPROM_ADDR_READ | EEPROM_ADDR_START);
3206 for (i = 0; i < 1000; i++) {
3207 tmp = tr32(GRC_EEPROM_ADDR);
3209 if (tmp & EEPROM_ADDR_COMPLETE)
3213 if (!(tmp & EEPROM_ADDR_COMPLETE))
3216 tmp = tr32(GRC_EEPROM_DATA);
3219 * The data will always be opposite the native endian
3220 * format. Perform a blind byteswap to compensate.
3227 #define NVRAM_CMD_TIMEOUT 5000
3229 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
3233 tw32(NVRAM_CMD, nvram_cmd);
3234 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
3235 usleep_range(10, 40);
3236 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
3242 if (i == NVRAM_CMD_TIMEOUT)
3248 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
3250 if (tg3_flag(tp, NVRAM) &&
3251 tg3_flag(tp, NVRAM_BUFFERED) &&
3252 tg3_flag(tp, FLASH) &&
3253 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3254 (tp->nvram_jedecnum == JEDEC_ATMEL))
3256 addr = ((addr / tp->nvram_pagesize) <<
3257 ATMEL_AT45DB0X1B_PAGE_POS) +
3258 (addr % tp->nvram_pagesize);
3263 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
3265 if (tg3_flag(tp, NVRAM) &&
3266 tg3_flag(tp, NVRAM_BUFFERED) &&
3267 tg3_flag(tp, FLASH) &&
3268 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) &&
3269 (tp->nvram_jedecnum == JEDEC_ATMEL))
3271 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
3272 tp->nvram_pagesize) +
3273 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
3278 /* NOTE: Data read in from NVRAM is byteswapped according to
3279 * the byteswapping settings for all other register accesses.
3280 * tg3 devices are BE devices, so on a BE machine, the data
3281 * returned will be exactly as it is seen in NVRAM. On a LE
3282 * machine, the 32-bit value will be byteswapped.
3284 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
3288 if (!tg3_flag(tp, NVRAM))
3289 return tg3_nvram_read_using_eeprom(tp, offset, val);
3291 offset = tg3_nvram_phys_addr(tp, offset);
3293 if (offset > NVRAM_ADDR_MSK)
3296 ret = tg3_nvram_lock(tp);
3300 tg3_enable_nvram_access(tp);
3302 tw32(NVRAM_ADDR, offset);
3303 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
3304 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
3307 *val = tr32(NVRAM_RDDATA);
3309 tg3_disable_nvram_access(tp);
3311 tg3_nvram_unlock(tp);
3316 /* Ensures NVRAM data is in bytestream format. */
3317 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
3320 int res = tg3_nvram_read(tp, offset, &v);
3322 *val = cpu_to_be32(v);
3326 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
3327 u32 offset, u32 len, u8 *buf)
3332 for (i = 0; i < len; i += 4) {
3338 memcpy(&data, buf + i, 4);
3341 * The SEEPROM interface expects the data to always be opposite
3342 * the native endian format. We accomplish this by reversing
3343 * all the operations that would have been performed on the
3344 * data from a call to tg3_nvram_read_be32().
3346 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
3348 val = tr32(GRC_EEPROM_ADDR);
3349 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
3351 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
3353 tw32(GRC_EEPROM_ADDR, val |
3354 (0 << EEPROM_ADDR_DEVID_SHIFT) |
3355 (addr & EEPROM_ADDR_ADDR_MASK) |
3359 for (j = 0; j < 1000; j++) {
3360 val = tr32(GRC_EEPROM_ADDR);
3362 if (val & EEPROM_ADDR_COMPLETE)
3366 if (!(val & EEPROM_ADDR_COMPLETE)) {
3375 /* offset and length are dword aligned */
3376 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
3380 u32 pagesize = tp->nvram_pagesize;
3381 u32 pagemask = pagesize - 1;
3385 tmp = kmalloc(pagesize, GFP_KERNEL);
3391 u32 phy_addr, page_off, size;
3393 phy_addr = offset & ~pagemask;
3395 for (j = 0; j < pagesize; j += 4) {
3396 ret = tg3_nvram_read_be32(tp, phy_addr + j,
3397 (__be32 *) (tmp + j));
3404 page_off = offset & pagemask;
3411 memcpy(tmp + page_off, buf, size);
3413 offset = offset + (pagesize - page_off);
3415 tg3_enable_nvram_access(tp);
3418 * Before we can erase the flash page, we need
3419 * to issue a special "write enable" command.
3421 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3423 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3426 /* Erase the target page */
3427 tw32(NVRAM_ADDR, phy_addr);
3429 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
3430 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
3432 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3435 /* Issue another write enable to start the write. */
3436 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3438 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
3441 for (j = 0; j < pagesize; j += 4) {
3444 data = *((__be32 *) (tmp + j));
3446 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3448 tw32(NVRAM_ADDR, phy_addr + j);
3450 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
3454 nvram_cmd |= NVRAM_CMD_FIRST;
3455 else if (j == (pagesize - 4))
3456 nvram_cmd |= NVRAM_CMD_LAST;
3458 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3466 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3467 tg3_nvram_exec_cmd(tp, nvram_cmd);
3474 /* offset and length are dword aligned */
3475 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
3480 for (i = 0; i < len; i += 4, offset += 4) {
3481 u32 page_off, phy_addr, nvram_cmd;
3484 memcpy(&data, buf + i, 4);
3485 tw32(NVRAM_WRDATA, be32_to_cpu(data));
3487 page_off = offset % tp->nvram_pagesize;
3489 phy_addr = tg3_nvram_phys_addr(tp, offset);
3491 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
3493 if (page_off == 0 || i == 0)
3494 nvram_cmd |= NVRAM_CMD_FIRST;
3495 if (page_off == (tp->nvram_pagesize - 4))
3496 nvram_cmd |= NVRAM_CMD_LAST;
3499 nvram_cmd |= NVRAM_CMD_LAST;
3501 if ((nvram_cmd & NVRAM_CMD_FIRST) ||
3502 !tg3_flag(tp, FLASH) ||
3503 !tg3_flag(tp, 57765_PLUS))
3504 tw32(NVRAM_ADDR, phy_addr);
3506 if (tg3_asic_rev(tp) != ASIC_REV_5752 &&
3507 !tg3_flag(tp, 5755_PLUS) &&
3508 (tp->nvram_jedecnum == JEDEC_ST) &&
3509 (nvram_cmd & NVRAM_CMD_FIRST)) {
3512 cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
3513 ret = tg3_nvram_exec_cmd(tp, cmd);
3517 if (!tg3_flag(tp, FLASH)) {
3518 /* We always do complete word writes to eeprom. */
3519 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
3522 ret = tg3_nvram_exec_cmd(tp, nvram_cmd);
3529 /* offset and length are dword aligned */
3530 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
3534 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3535 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3536 ~GRC_LCLCTRL_GPIO_OUTPUT1);
3540 if (!tg3_flag(tp, NVRAM)) {
3541 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
3545 ret = tg3_nvram_lock(tp);
3549 tg3_enable_nvram_access(tp);
3550 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM))
3551 tw32(NVRAM_WRITE1, 0x406);
3553 grc_mode = tr32(GRC_MODE);
3554 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
3556 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) {
3557 ret = tg3_nvram_write_block_buffered(tp, offset, len,
3560 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
3564 grc_mode = tr32(GRC_MODE);
3565 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
3567 tg3_disable_nvram_access(tp);
3568 tg3_nvram_unlock(tp);
3571 if (tg3_flag(tp, EEPROM_WRITE_PROT)) {
3572 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3579 #define RX_CPU_SCRATCH_BASE 0x30000
3580 #define RX_CPU_SCRATCH_SIZE 0x04000
3581 #define TX_CPU_SCRATCH_BASE 0x34000
3582 #define TX_CPU_SCRATCH_SIZE 0x04000
3584 /* tp->lock is held. */
3585 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)
3588 const int iters = 10000;
3590 for (i = 0; i < iters; i++) {
3591 tw32(cpu_base + CPU_STATE, 0xffffffff);
3592 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3593 if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)
3595 if (pci_channel_offline(tp->pdev))
3599 return (i == iters) ? -EBUSY : 0;
3602 /* tp->lock is held. */
3603 static int tg3_rxcpu_pause(struct tg3 *tp)
3605 int rc = tg3_pause_cpu(tp, RX_CPU_BASE);
3607 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
3608 tw32_f(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
3614 /* tp->lock is held. */
3615 static int tg3_txcpu_pause(struct tg3 *tp)
3617 return tg3_pause_cpu(tp, TX_CPU_BASE);
3620 /* tp->lock is held. */
3621 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)
3623 tw32(cpu_base + CPU_STATE, 0xffffffff);
3624 tw32_f(cpu_base + CPU_MODE, 0x00000000);
3627 /* tp->lock is held. */
3628 static void tg3_rxcpu_resume(struct tg3 *tp)
3630 tg3_resume_cpu(tp, RX_CPU_BASE);
3633 /* tp->lock is held. */
3634 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)
3638 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));
3640 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
3641 u32 val = tr32(GRC_VCPU_EXT_CTRL);
3643 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
3646 if (cpu_base == RX_CPU_BASE) {
3647 rc = tg3_rxcpu_pause(tp);
3650 * There is only an Rx CPU for the 5750 derivative in the
3653 if (tg3_flag(tp, IS_SSB_CORE))
3656 rc = tg3_txcpu_pause(tp);
3660 netdev_err(tp->dev, "%s timed out, %s CPU\n",
3661 __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");
3665 /* Clear firmware's nvram arbitration. */
3666 if (tg3_flag(tp, NVRAM))
3667 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
3671 static int tg3_fw_data_len(struct tg3 *tp,
3672 const struct tg3_firmware_hdr *fw_hdr)
3676 /* Non fragmented firmware have one firmware header followed by a
3677 * contiguous chunk of data to be written. The length field in that
3678 * header is not the length of data to be written but the complete
3679 * length of the bss. The data length is determined based on
3680 * tp->fw->size minus headers.
3682 * Fragmented firmware have a main header followed by multiple
3683 * fragments. Each fragment is identical to non fragmented firmware
3684 * with a firmware header followed by a contiguous chunk of data. In
3685 * the main header, the length field is unused and set to 0xffffffff.
3686 * In each fragment header the length is the entire size of that
3687 * fragment i.e. fragment data + header length. Data length is
3688 * therefore length field in the header minus TG3_FW_HDR_LEN.
3690 if (tp->fw_len == 0xffffffff)
3691 fw_len = be32_to_cpu(fw_hdr->len);
3693 fw_len = tp->fw->size;
3695 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32);
3698 /* tp->lock is held. */
3699 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base,
3700 u32 cpu_scratch_base, int cpu_scratch_size,
3701 const struct tg3_firmware_hdr *fw_hdr)
3704 void (*write_op)(struct tg3 *, u32, u32);
3705 int total_len = tp->fw->size;
3707 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) {
3709 "%s: Trying to load TX cpu firmware which is 5705\n",
3714 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766)
3715 write_op = tg3_write_mem;
3717 write_op = tg3_write_indirect_reg32;
3719 if (tg3_asic_rev(tp) != ASIC_REV_57766) {
3720 /* It is possible that bootcode is still loading at this point.
3721 * Get the nvram lock first before halting the cpu.
3723 int lock_err = tg3_nvram_lock(tp);
3724 err = tg3_halt_cpu(tp, cpu_base);
3726 tg3_nvram_unlock(tp);
3730 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
3731 write_op(tp, cpu_scratch_base + i, 0);
3732 tw32(cpu_base + CPU_STATE, 0xffffffff);
3733 tw32(cpu_base + CPU_MODE,
3734 tr32(cpu_base + CPU_MODE) | CPU_MODE_HALT);
3736 /* Subtract additional main header for fragmented firmware and
3737 * advance to the first fragment
3739 total_len -= TG3_FW_HDR_LEN;
3744 u32 *fw_data = (u32 *)(fw_hdr + 1);
3745 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++)
3746 write_op(tp, cpu_scratch_base +
3747 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) +
3749 be32_to_cpu(fw_data[i]));
3751 total_len -= be32_to_cpu(fw_hdr->len);
3753 /* Advance to next fragment */
3754 fw_hdr = (struct tg3_firmware_hdr *)
3755 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len));
3756 } while (total_len > 0);
3764 /* tp->lock is held. */
3765 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc)
3768 const int iters = 5;
3770 tw32(cpu_base + CPU_STATE, 0xffffffff);
3771 tw32_f(cpu_base + CPU_PC, pc);
3773 for (i = 0; i < iters; i++) {
3774 if (tr32(cpu_base + CPU_PC) == pc)
3776 tw32(cpu_base + CPU_STATE, 0xffffffff);
3777 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
3778 tw32_f(cpu_base + CPU_PC, pc);
3782 return (i == iters) ? -EBUSY : 0;
3785 /* tp->lock is held. */
3786 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
3788 const struct tg3_firmware_hdr *fw_hdr;
3791 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3793 /* Firmware blob starts with version numbers, followed by
3794 start address and length. We are setting complete length.
3795 length = end_address_of_bss - start_address_of_text.
3796 Remainder is the blob to be loaded contiguously
3797 from start address. */
3799 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
3800 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
3805 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
3806 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
3811 /* Now startup only the RX cpu. */
3812 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE,
3813 be32_to_cpu(fw_hdr->base_addr));
3815 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x "
3816 "should be %08x\n", __func__,
3817 tr32(RX_CPU_BASE + CPU_PC),
3818 be32_to_cpu(fw_hdr->base_addr));
3822 tg3_rxcpu_resume(tp);
3827 static int tg3_validate_rxcpu_state(struct tg3 *tp)
3829 const int iters = 1000;
3833 /* Wait for boot code to complete initialization and enter service
3834 * loop. It is then safe to download service patches
3836 for (i = 0; i < iters; i++) {
3837 if (tr32(RX_CPU_HWBKPT) == TG3_SBROM_IN_SERVICE_LOOP)
3844 netdev_err(tp->dev, "Boot code not ready for service patches\n");
3848 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE);
3850 netdev_warn(tp->dev,
3851 "Other patches exist. Not downloading EEE patch\n");
3858 /* tp->lock is held. */
3859 static void tg3_load_57766_firmware(struct tg3 *tp)
3861 struct tg3_firmware_hdr *fw_hdr;
3863 if (!tg3_flag(tp, NO_NVRAM))
3866 if (tg3_validate_rxcpu_state(tp))
3872 /* This firmware blob has a different format than older firmware
3873 * releases as given below. The main difference is we have fragmented
3874 * data to be written to non-contiguous locations.
3876 * In the beginning we have a firmware header identical to other
3877 * firmware which consists of version, base addr and length. The length
3878 * here is unused and set to 0xffffffff.
3880 * This is followed by a series of firmware fragments which are
3881 * individually identical to previous firmware. i.e. they have the
3882 * firmware header and followed by data for that fragment. The version
3883 * field of the individual fragment header is unused.
3886 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3887 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR)
3890 if (tg3_rxcpu_pause(tp))
3893 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3894 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr);
3896 tg3_rxcpu_resume(tp);
3899 /* tp->lock is held. */
3900 static int tg3_load_tso_firmware(struct tg3 *tp)
3902 const struct tg3_firmware_hdr *fw_hdr;
3903 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
3906 if (!tg3_flag(tp, FW_TSO))
3909 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
3911 /* Firmware blob starts with version numbers, followed by
3912 start address and length. We are setting complete length.
3913 length = end_address_of_bss - start_address_of_text.
3914 Remainder is the blob to be loaded contiguously
3915 from start address. */
3917 cpu_scratch_size = tp->fw_len;
3919 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
3920 cpu_base = RX_CPU_BASE;
3921 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
3923 cpu_base = TX_CPU_BASE;
3924 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
3925 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
3928 err = tg3_load_firmware_cpu(tp, cpu_base,
3929 cpu_scratch_base, cpu_scratch_size,
3934 /* Now startup the cpu. */
3935 err = tg3_pause_cpu_and_set_pc(tp, cpu_base,
3936 be32_to_cpu(fw_hdr->base_addr));
3939 "%s fails to set CPU PC, is %08x should be %08x\n",
3940 __func__, tr32(cpu_base + CPU_PC),
3941 be32_to_cpu(fw_hdr->base_addr));
3945 tg3_resume_cpu(tp, cpu_base);
3949 /* tp->lock is held. */
3950 static void __tg3_set_one_mac_addr(struct tg3 *tp, u8 *mac_addr, int index)
3952 u32 addr_high, addr_low;
3954 addr_high = ((mac_addr[0] << 8) | mac_addr[1]);
3955 addr_low = ((mac_addr[2] << 24) | (mac_addr[3] << 16) |
3956 (mac_addr[4] << 8) | mac_addr[5]);
3959 tw32(MAC_ADDR_0_HIGH + (index * 8), addr_high);
3960 tw32(MAC_ADDR_0_LOW + (index * 8), addr_low);
3963 tw32(MAC_EXTADDR_0_HIGH + (index * 8), addr_high);
3964 tw32(MAC_EXTADDR_0_LOW + (index * 8), addr_low);
3968 /* tp->lock is held. */
3969 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1)
3974 for (i = 0; i < 4; i++) {
3975 if (i == 1 && skip_mac_1)
3977 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3980 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
3981 tg3_asic_rev(tp) == ASIC_REV_5704) {
3982 for (i = 4; i < 16; i++)
3983 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i);
3986 addr_high = (tp->dev->dev_addr[0] +
3987 tp->dev->dev_addr[1] +
3988 tp->dev->dev_addr[2] +
3989 tp->dev->dev_addr[3] +
3990 tp->dev->dev_addr[4] +
3991 tp->dev->dev_addr[5]) &
3992 TX_BACKOFF_SEED_MASK;
3993 tw32(MAC_TX_BACKOFF_SEED, addr_high);
3996 static void tg3_enable_register_access(struct tg3 *tp)
3999 * Make sure register accesses (indirect or otherwise) will function
4002 pci_write_config_dword(tp->pdev,
4003 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
4006 static int tg3_power_up(struct tg3 *tp)
4010 tg3_enable_register_access(tp);
4012 err = pci_set_power_state(tp->pdev, PCI_D0);
4014 /* Switch out of Vaux if it is a NIC */
4015 tg3_pwrsrc_switch_to_vmain(tp);
4017 netdev_err(tp->dev, "Transition to D0 failed\n");
4023 static int tg3_setup_phy(struct tg3 *, bool);
4025 static int tg3_power_down_prepare(struct tg3 *tp)
4028 bool device_should_wake, do_low_power;
4030 tg3_enable_register_access(tp);
4032 /* Restore the CLKREQ setting. */
4033 if (tg3_flag(tp, CLKREQ_BUG))
4034 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
4035 PCI_EXP_LNKCTL_CLKREQ_EN);
4037 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
4038 tw32(TG3PCI_MISC_HOST_CTRL,
4039 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
4041 device_should_wake = device_may_wakeup(&tp->pdev->dev) &&
4042 tg3_flag(tp, WOL_ENABLE);
4044 if (tg3_flag(tp, USE_PHYLIB)) {
4045 do_low_power = false;
4046 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) &&
4047 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4048 struct phy_device *phydev;
4049 u32 phyid, advertising;
4051 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
4053 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4055 tp->link_config.speed = phydev->speed;
4056 tp->link_config.duplex = phydev->duplex;
4057 tp->link_config.autoneg = phydev->autoneg;
4058 tp->link_config.advertising = phydev->advertising;
4060 advertising = ADVERTISED_TP |
4062 ADVERTISED_Autoneg |
4063 ADVERTISED_10baseT_Half;
4065 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) {
4066 if (tg3_flag(tp, WOL_SPEED_100MB))
4068 ADVERTISED_100baseT_Half |
4069 ADVERTISED_100baseT_Full |
4070 ADVERTISED_10baseT_Full;
4072 advertising |= ADVERTISED_10baseT_Full;
4075 phydev->advertising = advertising;
4077 phy_start_aneg(phydev);
4079 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
4080 if (phyid != PHY_ID_BCMAC131) {
4081 phyid &= PHY_BCM_OUI_MASK;
4082 if (phyid == PHY_BCM_OUI_1 ||
4083 phyid == PHY_BCM_OUI_2 ||
4084 phyid == PHY_BCM_OUI_3)
4085 do_low_power = true;
4089 do_low_power = true;
4091 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER))
4092 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER;
4094 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
4095 tg3_setup_phy(tp, false);
4098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
4101 val = tr32(GRC_VCPU_EXT_CTRL);
4102 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
4103 } else if (!tg3_flag(tp, ENABLE_ASF)) {
4107 for (i = 0; i < 200; i++) {
4108 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
4109 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4114 if (tg3_flag(tp, WOL_CAP))
4115 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
4116 WOL_DRV_STATE_SHUTDOWN |
4120 if (device_should_wake) {
4123 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
4125 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
4126 tg3_phy_auxctl_write(tp,
4127 MII_TG3_AUXCTL_SHDWSEL_PWRCTL,
4128 MII_TG3_AUXCTL_PCTL_WOL_EN |
4129 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
4130 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC);
4134 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4135 mac_mode = MAC_MODE_PORT_MODE_GMII;
4136 else if (tp->phy_flags &
4137 TG3_PHYFLG_KEEP_LINK_ON_PWRDN) {
4138 if (tp->link_config.active_speed == SPEED_1000)
4139 mac_mode = MAC_MODE_PORT_MODE_GMII;
4141 mac_mode = MAC_MODE_PORT_MODE_MII;
4143 mac_mode = MAC_MODE_PORT_MODE_MII;
4145 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
4146 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
4147 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ?
4148 SPEED_100 : SPEED_10;
4149 if (tg3_5700_link_polarity(tp, speed))
4150 mac_mode |= MAC_MODE_LINK_POLARITY;
4152 mac_mode &= ~MAC_MODE_LINK_POLARITY;
4155 mac_mode = MAC_MODE_PORT_MODE_TBI;
4158 if (!tg3_flag(tp, 5750_PLUS))
4159 tw32(MAC_LED_CTRL, tp->led_ctrl);
4161 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
4162 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) &&
4163 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)))
4164 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
4166 if (tg3_flag(tp, ENABLE_APE))
4167 mac_mode |= MAC_MODE_APE_TX_EN |
4168 MAC_MODE_APE_RX_EN |
4169 MAC_MODE_TDE_ENABLE;
4171 tw32_f(MAC_MODE, mac_mode);
4174 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4178 if (!tg3_flag(tp, WOL_SPEED_100MB) &&
4179 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4180 tg3_asic_rev(tp) == ASIC_REV_5701)) {
4183 base_val = tp->pci_clock_ctrl;
4184 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
4185 CLOCK_CTRL_TXCLK_DISABLE);
4187 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
4188 CLOCK_CTRL_PWRDOWN_PLL133, 40);
4189 } else if (tg3_flag(tp, 5780_CLASS) ||
4190 tg3_flag(tp, CPMU_PRESENT) ||
4191 tg3_asic_rev(tp) == ASIC_REV_5906) {
4193 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) {
4194 u32 newbits1, newbits2;
4196 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4197 tg3_asic_rev(tp) == ASIC_REV_5701) {
4198 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
4199 CLOCK_CTRL_TXCLK_DISABLE |
4201 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4202 } else if (tg3_flag(tp, 5705_PLUS)) {
4203 newbits1 = CLOCK_CTRL_625_CORE;
4204 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
4206 newbits1 = CLOCK_CTRL_ALTCLK;
4207 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
4210 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
4213 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
4216 if (!tg3_flag(tp, 5705_PLUS)) {
4219 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4220 tg3_asic_rev(tp) == ASIC_REV_5701) {
4221 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
4222 CLOCK_CTRL_TXCLK_DISABLE |
4223 CLOCK_CTRL_44MHZ_CORE);
4225 newbits3 = CLOCK_CTRL_44MHZ_CORE;
4228 tw32_wait_f(TG3PCI_CLOCK_CTRL,
4229 tp->pci_clock_ctrl | newbits3, 40);
4233 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF))
4234 tg3_power_down_phy(tp, do_low_power);
4236 tg3_frob_aux_power(tp, true);
4238 /* Workaround for unstable PLL clock */
4239 if ((!tg3_flag(tp, IS_SSB_CORE)) &&
4240 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) ||
4241 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) {
4242 u32 val = tr32(0x7d00);
4244 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4246 if (!tg3_flag(tp, ENABLE_ASF)) {
4249 err = tg3_nvram_lock(tp);
4250 tg3_halt_cpu(tp, RX_CPU_BASE);
4252 tg3_nvram_unlock(tp);
4256 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
4258 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN);
4263 static void tg3_power_down(struct tg3 *tp)
4265 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE));
4266 pci_set_power_state(tp->pdev, PCI_D3hot);
4269 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
4271 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
4272 case MII_TG3_AUX_STAT_10HALF:
4274 *duplex = DUPLEX_HALF;
4277 case MII_TG3_AUX_STAT_10FULL:
4279 *duplex = DUPLEX_FULL;
4282 case MII_TG3_AUX_STAT_100HALF:
4284 *duplex = DUPLEX_HALF;
4287 case MII_TG3_AUX_STAT_100FULL:
4289 *duplex = DUPLEX_FULL;
4292 case MII_TG3_AUX_STAT_1000HALF:
4293 *speed = SPEED_1000;
4294 *duplex = DUPLEX_HALF;
4297 case MII_TG3_AUX_STAT_1000FULL:
4298 *speed = SPEED_1000;
4299 *duplex = DUPLEX_FULL;
4303 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4304 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
4306 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
4310 *speed = SPEED_UNKNOWN;
4311 *duplex = DUPLEX_UNKNOWN;
4316 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
4321 new_adv = ADVERTISE_CSMA;
4322 new_adv |= ethtool_adv_to_mii_adv_t(advertise) & ADVERTISE_ALL;
4323 new_adv |= mii_advertise_flowctrl(flowctrl);
4325 err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
4329 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4330 new_adv = ethtool_adv_to_mii_ctrl1000_t(advertise);
4332 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4333 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)
4334 new_adv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4336 err = tg3_writephy(tp, MII_CTRL1000, new_adv);
4341 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4344 tw32(TG3_CPMU_EEE_MODE,
4345 tr32(TG3_CPMU_EEE_MODE) & ~TG3_CPMU_EEEMD_LPI_ENABLE);
4347 err = tg3_phy_toggle_auxctl_smdsp(tp, true);
4352 /* Advertise 100-BaseTX EEE ability */
4353 if (advertise & ADVERTISED_100baseT_Full)
4354 val |= MDIO_AN_EEE_ADV_100TX;
4355 /* Advertise 1000-BaseT EEE ability */
4356 if (advertise & ADVERTISED_1000baseT_Full)
4357 val |= MDIO_AN_EEE_ADV_1000T;
4359 if (!tp->eee.eee_enabled) {
4361 tp->eee.advertised = 0;
4363 tp->eee.advertised = advertise &
4364 (ADVERTISED_100baseT_Full |
4365 ADVERTISED_1000baseT_Full);
4368 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4372 switch (tg3_asic_rev(tp)) {
4374 case ASIC_REV_57765:
4375 case ASIC_REV_57766:
4377 /* If we advertised any eee advertisements above... */
4379 val = MII_TG3_DSP_TAP26_ALNOKO |
4380 MII_TG3_DSP_TAP26_RMRXSTO |
4381 MII_TG3_DSP_TAP26_OPCSINPT;
4382 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);
4386 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val))
4387 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |
4388 MII_TG3_DSP_CH34TP2_HIBW01);
4391 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false);
4400 static void tg3_phy_copper_begin(struct tg3 *tp)
4402 if (tp->link_config.autoneg == AUTONEG_ENABLE ||
4403 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4406 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4407 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4408 adv = ADVERTISED_10baseT_Half |
4409 ADVERTISED_10baseT_Full;
4410 if (tg3_flag(tp, WOL_SPEED_100MB))
4411 adv |= ADVERTISED_100baseT_Half |
4412 ADVERTISED_100baseT_Full;
4413 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) {
4414 if (!(tp->phy_flags &
4415 TG3_PHYFLG_DISABLE_1G_HD_ADV))
4416 adv |= ADVERTISED_1000baseT_Half;
4417 adv |= ADVERTISED_1000baseT_Full;
4420 fc = FLOW_CTRL_TX | FLOW_CTRL_RX;
4422 adv = tp->link_config.advertising;
4423 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
4424 adv &= ~(ADVERTISED_1000baseT_Half |
4425 ADVERTISED_1000baseT_Full);
4427 fc = tp->link_config.flowctrl;
4430 tg3_phy_autoneg_cfg(tp, adv, fc);
4432 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) &&
4433 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) {
4434 /* Normally during power down we want to autonegotiate
4435 * the lowest possible speed for WOL. However, to avoid
4436 * link flap, we leave it untouched.
4441 tg3_writephy(tp, MII_BMCR,
4442 BMCR_ANENABLE | BMCR_ANRESTART);
4445 u32 bmcr, orig_bmcr;
4447 tp->link_config.active_speed = tp->link_config.speed;
4448 tp->link_config.active_duplex = tp->link_config.duplex;
4450 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
4451 /* With autoneg disabled, 5715 only links up when the
4452 * advertisement register has the configured speed
4455 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL);
4459 switch (tp->link_config.speed) {
4465 bmcr |= BMCR_SPEED100;
4469 bmcr |= BMCR_SPEED1000;
4473 if (tp->link_config.duplex == DUPLEX_FULL)
4474 bmcr |= BMCR_FULLDPLX;
4476 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
4477 (bmcr != orig_bmcr)) {
4478 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
4479 for (i = 0; i < 1500; i++) {
4483 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
4484 tg3_readphy(tp, MII_BMSR, &tmp))
4486 if (!(tmp & BMSR_LSTATUS)) {
4491 tg3_writephy(tp, MII_BMCR, bmcr);
4497 static int tg3_phy_pull_config(struct tg3 *tp)
4502 err = tg3_readphy(tp, MII_BMCR, &val);
4506 if (!(val & BMCR_ANENABLE)) {
4507 tp->link_config.autoneg = AUTONEG_DISABLE;
4508 tp->link_config.advertising = 0;
4509 tg3_flag_clear(tp, PAUSE_AUTONEG);
4513 switch (val & (BMCR_SPEED1000 | BMCR_SPEED100)) {
4515 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4518 tp->link_config.speed = SPEED_10;
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
4524 tp->link_config.speed = SPEED_100;
4526 case BMCR_SPEED1000:
4527 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4528 tp->link_config.speed = SPEED_1000;
4536 if (val & BMCR_FULLDPLX)
4537 tp->link_config.duplex = DUPLEX_FULL;
4539 tp->link_config.duplex = DUPLEX_HALF;
4541 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
4547 tp->link_config.autoneg = AUTONEG_ENABLE;
4548 tp->link_config.advertising = ADVERTISED_Autoneg;
4549 tg3_flag_set(tp, PAUSE_AUTONEG);
4551 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4554 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4558 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL);
4559 tp->link_config.advertising |= adv | ADVERTISED_TP;
4561 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val);
4563 tp->link_config.advertising |= ADVERTISED_FIBRE;
4566 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4569 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
4570 err = tg3_readphy(tp, MII_CTRL1000, &val);
4574 adv = mii_ctrl1000_to_ethtool_adv_t(val);
4576 err = tg3_readphy(tp, MII_ADVERTISE, &val);
4580 adv = tg3_decode_flowctrl_1000X(val);
4581 tp->link_config.flowctrl = adv;
4583 val &= (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL);
4584 adv = mii_adv_to_ethtool_adv_x(val);
4587 tp->link_config.advertising |= adv;
4594 static int tg3_init_5401phy_dsp(struct tg3 *tp)
4598 /* Turn off tap power management. */
4599 /* Set Extended packet length bit */
4600 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
4602 err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
4603 err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
4604 err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
4605 err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
4606 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
4613 static bool tg3_phy_eee_config_ok(struct tg3 *tp)
4615 struct ethtool_eee eee;
4617 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
4620 tg3_eee_pull_config(tp, &eee);
4622 if (tp->eee.eee_enabled) {
4623 if (tp->eee.advertised != eee.advertised ||
4624 tp->eee.tx_lpi_timer != eee.tx_lpi_timer ||
4625 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled)
4628 /* EEE is disabled but we're advertising */
4636 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv)
4638 u32 advmsk, tgtadv, advertising;
4640 advertising = tp->link_config.advertising;
4641 tgtadv = ethtool_adv_to_mii_adv_t(advertising) & ADVERTISE_ALL;
4643 advmsk = ADVERTISE_ALL;
4644 if (tp->link_config.active_duplex == DUPLEX_FULL) {
4645 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl);
4646 advmsk |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4649 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
4652 if ((*lcladv & advmsk) != tgtadv)
4655 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4658 tgtadv = ethtool_adv_to_mii_ctrl1000_t(advertising);
4660 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl))
4664 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4665 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) {
4666 tgtadv |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
4667 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL |
4668 CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER);
4670 tg3_ctrl &= (ADVERTISE_1000HALF | ADVERTISE_1000FULL);
4673 if (tg3_ctrl != tgtadv)
4680 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv)
4684 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
4687 if (tg3_readphy(tp, MII_STAT1000, &val))
4690 lpeth = mii_stat1000_to_ethtool_lpa_t(val);
4693 if (tg3_readphy(tp, MII_LPA, rmtadv))
4696 lpeth |= mii_lpa_to_ethtool_lpa_t(*rmtadv);
4697 tp->link_config.rmt_adv = lpeth;
4702 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up)
4704 if (curr_link_up != tp->link_up) {
4706 netif_carrier_on(tp->dev);
4708 netif_carrier_off(tp->dev);
4709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
4710 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
4713 tg3_link_report(tp);
4720 static void tg3_clear_mac_status(struct tg3 *tp)
4725 MAC_STATUS_SYNC_CHANGED |
4726 MAC_STATUS_CFG_CHANGED |
4727 MAC_STATUS_MI_COMPLETION |
4728 MAC_STATUS_LNKSTATE_CHANGED);
4732 static void tg3_setup_eee(struct tg3 *tp)
4736 val = TG3_CPMU_EEE_LNKIDL_PCIE_NL0 |
4737 TG3_CPMU_EEE_LNKIDL_UART_IDL;
4738 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
4739 val |= TG3_CPMU_EEE_LNKIDL_APE_TX_MT;
4741 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4743 tw32_f(TG3_CPMU_EEE_CTRL,
4744 TG3_CPMU_EEE_CTRL_EXIT_20_1_US);
4746 val = TG3_CPMU_EEEMD_ERLY_L1_XIT_DET |
4747 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) |
4748 TG3_CPMU_EEEMD_LPI_IN_RX |
4749 TG3_CPMU_EEEMD_EEE_ENABLE;
4751 if (tg3_asic_rev(tp) != ASIC_REV_5717)
4752 val |= TG3_CPMU_EEEMD_SND_IDX_DET_EN;
4754 if (tg3_flag(tp, ENABLE_APE))
4755 val |= TG3_CPMU_EEEMD_APE_TX_DET_EN;
4757 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4759 tw32_f(TG3_CPMU_EEE_DBTMR1,
4760 TG3_CPMU_DBTMR1_PCIEXIT_2047US |
4761 (tp->eee.tx_lpi_timer & 0xffff));
4763 tw32_f(TG3_CPMU_EEE_DBTMR2,
4764 TG3_CPMU_DBTMR2_APE_TX_2047US |
4765 TG3_CPMU_DBTMR2_TXIDXEQ_2047US);
4768 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset)
4770 bool current_link_up;
4772 u32 lcl_adv, rmt_adv;
4777 tg3_clear_mac_status(tp);
4779 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
4781 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
4785 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
4787 /* Some third-party PHYs need to be reset on link going
4790 if ((tg3_asic_rev(tp) == ASIC_REV_5703 ||
4791 tg3_asic_rev(tp) == ASIC_REV_5704 ||
4792 tg3_asic_rev(tp) == ASIC_REV_5705) &&
4794 tg3_readphy(tp, MII_BMSR, &bmsr);
4795 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4796 !(bmsr & BMSR_LSTATUS))
4802 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
4803 tg3_readphy(tp, MII_BMSR, &bmsr);
4804 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
4805 !tg3_flag(tp, INIT_COMPLETE))
4808 if (!(bmsr & BMSR_LSTATUS)) {
4809 err = tg3_init_5401phy_dsp(tp);
4813 tg3_readphy(tp, MII_BMSR, &bmsr);
4814 for (i = 0; i < 1000; i++) {
4816 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4817 (bmsr & BMSR_LSTATUS)) {
4823 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
4824 TG3_PHY_REV_BCM5401_B0 &&
4825 !(bmsr & BMSR_LSTATUS) &&
4826 tp->link_config.active_speed == SPEED_1000) {
4827 err = tg3_phy_reset(tp);
4829 err = tg3_init_5401phy_dsp(tp);
4834 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
4835 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) {
4836 /* 5701 {A0,B0} CRC bug workaround */
4837 tg3_writephy(tp, 0x15, 0x0a75);
4838 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4839 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
4840 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
4843 /* Clear pending interrupts... */
4844 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4845 tg3_readphy(tp, MII_TG3_ISTAT, &val);
4847 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
4848 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
4849 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
4850 tg3_writephy(tp, MII_TG3_IMASK, ~0);
4852 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
4853 tg3_asic_rev(tp) == ASIC_REV_5701) {
4854 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
4855 tg3_writephy(tp, MII_TG3_EXT_CTRL,
4856 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
4858 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
4861 current_link_up = false;
4862 current_speed = SPEED_UNKNOWN;
4863 current_duplex = DUPLEX_UNKNOWN;
4864 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE;
4865 tp->link_config.rmt_adv = 0;
4867 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
4868 err = tg3_phy_auxctl_read(tp,
4869 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4871 if (!err && !(val & (1 << 10))) {
4872 tg3_phy_auxctl_write(tp,
4873 MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
4880 for (i = 0; i < 100; i++) {
4881 tg3_readphy(tp, MII_BMSR, &bmsr);
4882 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
4883 (bmsr & BMSR_LSTATUS))
4888 if (bmsr & BMSR_LSTATUS) {
4891 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
4892 for (i = 0; i < 2000; i++) {
4894 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
4899 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
4904 for (i = 0; i < 200; i++) {
4905 tg3_readphy(tp, MII_BMCR, &bmcr);
4906 if (tg3_readphy(tp, MII_BMCR, &bmcr))
4908 if (bmcr && bmcr != 0x7fff)
4916 tp->link_config.active_speed = current_speed;
4917 tp->link_config.active_duplex = current_duplex;
4919 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4920 bool eee_config_ok = tg3_phy_eee_config_ok(tp);
4922 if ((bmcr & BMCR_ANENABLE) &&
4924 tg3_phy_copper_an_config_ok(tp, &lcl_adv) &&
4925 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv))
4926 current_link_up = true;
4928 /* EEE settings changes take effect only after a phy
4929 * reset. If we have skipped a reset due to Link Flap
4930 * Avoidance being enabled, do it now.
4932 if (!eee_config_ok &&
4933 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
4939 if (!(bmcr & BMCR_ANENABLE) &&
4940 tp->link_config.speed == current_speed &&
4941 tp->link_config.duplex == current_duplex) {
4942 current_link_up = true;
4946 if (current_link_up &&
4947 tp->link_config.active_duplex == DUPLEX_FULL) {
4950 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
4951 reg = MII_TG3_FET_GEN_STAT;
4952 bit = MII_TG3_FET_GEN_STAT_MDIXSTAT;
4954 reg = MII_TG3_EXT_STAT;
4955 bit = MII_TG3_EXT_STAT_MDIX;
4958 if (!tg3_readphy(tp, reg, &val) && (val & bit))
4959 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE;
4961 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
4966 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) {
4967 tg3_phy_copper_begin(tp);
4969 if (tg3_flag(tp, ROBOSWITCH)) {
4970 current_link_up = true;
4971 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4972 current_speed = SPEED_1000;
4973 current_duplex = DUPLEX_FULL;
4974 tp->link_config.active_speed = current_speed;
4975 tp->link_config.active_duplex = current_duplex;
4978 tg3_readphy(tp, MII_BMSR, &bmsr);
4979 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
4980 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
4981 current_link_up = true;
4984 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
4985 if (current_link_up) {
4986 if (tp->link_config.active_speed == SPEED_100 ||
4987 tp->link_config.active_speed == SPEED_10)
4988 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4990 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4991 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
4992 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4996 /* In order for the 5750 core in BCM4785 chip to work properly
4997 * in RGMII mode, the Led Control Register must be set up.
4999 if (tg3_flag(tp, RGMII_MODE)) {
5000 u32 led_ctrl = tr32(MAC_LED_CTRL);
5001 led_ctrl &= ~(LED_CTRL_1000MBPS_ON | LED_CTRL_100MBPS_ON);
5003 if (tp->link_config.active_speed == SPEED_10)
5004 led_ctrl |= LED_CTRL_LNKLED_OVERRIDE;
5005 else if (tp->link_config.active_speed == SPEED_100)
5006 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5007 LED_CTRL_100MBPS_ON);
5008 else if (tp->link_config.active_speed == SPEED_1000)
5009 led_ctrl |= (LED_CTRL_LNKLED_OVERRIDE |
5010 LED_CTRL_1000MBPS_ON);
5012 tw32(MAC_LED_CTRL, led_ctrl);
5016 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5017 if (tp->link_config.active_duplex == DUPLEX_HALF)
5018 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5020 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
5021 if (current_link_up &&
5022 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
5023 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
5025 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
5028 /* ??? Without this setting Netgear GA302T PHY does not
5029 * ??? send/receive packets...
5031 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
5032 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) {
5033 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
5034 tw32_f(MAC_MI_MODE, tp->mi_mode);
5038 tw32_f(MAC_MODE, tp->mac_mode);
5041 tg3_phy_eee_adjust(tp, current_link_up);
5043 if (tg3_flag(tp, USE_LINKCHG_REG)) {
5044 /* Polled via timer. */
5045 tw32_f(MAC_EVENT, 0);
5047 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5051 if (tg3_asic_rev(tp) == ASIC_REV_5700 &&
5053 tp->link_config.active_speed == SPEED_1000 &&
5054 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
5057 (MAC_STATUS_SYNC_CHANGED |
5058 MAC_STATUS_CFG_CHANGED));
5061 NIC_SRAM_FIRMWARE_MBOX,
5062 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
5065 /* Prevent send BD corruption. */
5066 if (tg3_flag(tp, CLKREQ_BUG)) {
5067 if (tp->link_config.active_speed == SPEED_100 ||
5068 tp->link_config.active_speed == SPEED_10)
5069 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL,
5070 PCI_EXP_LNKCTL_CLKREQ_EN);
5072 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL,
5073 PCI_EXP_LNKCTL_CLKREQ_EN);
5076 tg3_test_and_report_link_chg(tp, current_link_up);
5081 struct tg3_fiber_aneginfo {
5083 #define ANEG_STATE_UNKNOWN 0
5084 #define ANEG_STATE_AN_ENABLE 1
5085 #define ANEG_STATE_RESTART_INIT 2
5086 #define ANEG_STATE_RESTART 3
5087 #define ANEG_STATE_DISABLE_LINK_OK 4
5088 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5089 #define ANEG_STATE_ABILITY_DETECT 6
5090 #define ANEG_STATE_ACK_DETECT_INIT 7
5091 #define ANEG_STATE_ACK_DETECT 8
5092 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5093 #define ANEG_STATE_COMPLETE_ACK 10
5094 #define ANEG_STATE_IDLE_DETECT_INIT 11
5095 #define ANEG_STATE_IDLE_DETECT 12
5096 #define ANEG_STATE_LINK_OK 13
5097 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5098 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5101 #define MR_AN_ENABLE 0x00000001
5102 #define MR_RESTART_AN 0x00000002
5103 #define MR_AN_COMPLETE 0x00000004
5104 #define MR_PAGE_RX 0x00000008
5105 #define MR_NP_LOADED 0x00000010
5106 #define MR_TOGGLE_TX 0x00000020
5107 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5108 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5109 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5110 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5111 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5112 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5113 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5114 #define MR_TOGGLE_RX 0x00002000
5115 #define MR_NP_RX 0x00004000
5117 #define MR_LINK_OK 0x80000000
5119 unsigned long link_time, cur_time;
5121 u32 ability_match_cfg;
5122 int ability_match_count;
5124 char ability_match, idle_match, ack_match;
5126 u32 txconfig, rxconfig;
5127 #define ANEG_CFG_NP 0x00000080
5128 #define ANEG_CFG_ACK 0x00000040
5129 #define ANEG_CFG_RF2 0x00000020
5130 #define ANEG_CFG_RF1 0x00000010
5131 #define ANEG_CFG_PS2 0x00000001
5132 #define ANEG_CFG_PS1 0x00008000
5133 #define ANEG_CFG_HD 0x00004000
5134 #define ANEG_CFG_FD 0x00002000
5135 #define ANEG_CFG_INVAL 0x00001f06
5140 #define ANEG_TIMER_ENAB 2
5141 #define ANEG_FAILED -1
5143 #define ANEG_STATE_SETTLE_TIME 10000
5145 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
5146 struct tg3_fiber_aneginfo *ap)
5149 unsigned long delta;
5153 if (ap->state == ANEG_STATE_UNKNOWN) {
5157 ap->ability_match_cfg = 0;
5158 ap->ability_match_count = 0;
5159 ap->ability_match = 0;
5165 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
5166 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
5168 if (rx_cfg_reg != ap->ability_match_cfg) {
5169 ap->ability_match_cfg = rx_cfg_reg;
5170 ap->ability_match = 0;
5171 ap->ability_match_count = 0;
5173 if (++ap->ability_match_count > 1) {
5174 ap->ability_match = 1;
5175 ap->ability_match_cfg = rx_cfg_reg;
5178 if (rx_cfg_reg & ANEG_CFG_ACK)
5186 ap->ability_match_cfg = 0;
5187 ap->ability_match_count = 0;
5188 ap->ability_match = 0;
5194 ap->rxconfig = rx_cfg_reg;
5197 switch (ap->state) {
5198 case ANEG_STATE_UNKNOWN:
5199 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
5200 ap->state = ANEG_STATE_AN_ENABLE;
5203 case ANEG_STATE_AN_ENABLE:
5204 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
5205 if (ap->flags & MR_AN_ENABLE) {
5208 ap->ability_match_cfg = 0;
5209 ap->ability_match_count = 0;
5210 ap->ability_match = 0;
5214 ap->state = ANEG_STATE_RESTART_INIT;
5216 ap->state = ANEG_STATE_DISABLE_LINK_OK;
5220 case ANEG_STATE_RESTART_INIT:
5221 ap->link_time = ap->cur_time;
5222 ap->flags &= ~(MR_NP_LOADED);
5224 tw32(MAC_TX_AUTO_NEG, 0);
5225 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5226 tw32_f(MAC_MODE, tp->mac_mode);
5229 ret = ANEG_TIMER_ENAB;
5230 ap->state = ANEG_STATE_RESTART;
5233 case ANEG_STATE_RESTART:
5234 delta = ap->cur_time - ap->link_time;
5235 if (delta > ANEG_STATE_SETTLE_TIME)
5236 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
5238 ret = ANEG_TIMER_ENAB;
5241 case ANEG_STATE_DISABLE_LINK_OK:
5245 case ANEG_STATE_ABILITY_DETECT_INIT:
5246 ap->flags &= ~(MR_TOGGLE_TX);
5247 ap->txconfig = ANEG_CFG_FD;
5248 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5249 if (flowctrl & ADVERTISE_1000XPAUSE)
5250 ap->txconfig |= ANEG_CFG_PS1;
5251 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5252 ap->txconfig |= ANEG_CFG_PS2;
5253 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5254 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5255 tw32_f(MAC_MODE, tp->mac_mode);
5258 ap->state = ANEG_STATE_ABILITY_DETECT;
5261 case ANEG_STATE_ABILITY_DETECT:
5262 if (ap->ability_match != 0 && ap->rxconfig != 0)
5263 ap->state = ANEG_STATE_ACK_DETECT_INIT;
5266 case ANEG_STATE_ACK_DETECT_INIT:
5267 ap->txconfig |= ANEG_CFG_ACK;
5268 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
5269 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
5270 tw32_f(MAC_MODE, tp->mac_mode);
5273 ap->state = ANEG_STATE_ACK_DETECT;
5276 case ANEG_STATE_ACK_DETECT:
5277 if (ap->ack_match != 0) {
5278 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
5279 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
5280 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
5282 ap->state = ANEG_STATE_AN_ENABLE;
5284 } else if (ap->ability_match != 0 &&
5285 ap->rxconfig == 0) {
5286 ap->state = ANEG_STATE_AN_ENABLE;
5290 case ANEG_STATE_COMPLETE_ACK_INIT:
5291 if (ap->rxconfig & ANEG_CFG_INVAL) {
5295 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
5296 MR_LP_ADV_HALF_DUPLEX |
5297 MR_LP_ADV_SYM_PAUSE |
5298 MR_LP_ADV_ASYM_PAUSE |
5299 MR_LP_ADV_REMOTE_FAULT1 |
5300 MR_LP_ADV_REMOTE_FAULT2 |
5301 MR_LP_ADV_NEXT_PAGE |
5304 if (ap->rxconfig & ANEG_CFG_FD)
5305 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
5306 if (ap->rxconfig & ANEG_CFG_HD)
5307 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
5308 if (ap->rxconfig & ANEG_CFG_PS1)
5309 ap->flags |= MR_LP_ADV_SYM_PAUSE;
5310 if (ap->rxconfig & ANEG_CFG_PS2)
5311 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
5312 if (ap->rxconfig & ANEG_CFG_RF1)
5313 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
5314 if (ap->rxconfig & ANEG_CFG_RF2)
5315 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
5316 if (ap->rxconfig & ANEG_CFG_NP)
5317 ap->flags |= MR_LP_ADV_NEXT_PAGE;
5319 ap->link_time = ap->cur_time;
5321 ap->flags ^= (MR_TOGGLE_TX);
5322 if (ap->rxconfig & 0x0008)
5323 ap->flags |= MR_TOGGLE_RX;
5324 if (ap->rxconfig & ANEG_CFG_NP)
5325 ap->flags |= MR_NP_RX;
5326 ap->flags |= MR_PAGE_RX;
5328 ap->state = ANEG_STATE_COMPLETE_ACK;
5329 ret = ANEG_TIMER_ENAB;
5332 case ANEG_STATE_COMPLETE_ACK:
5333 if (ap->ability_match != 0 &&
5334 ap->rxconfig == 0) {
5335 ap->state = ANEG_STATE_AN_ENABLE;
5338 delta = ap->cur_time - ap->link_time;
5339 if (delta > ANEG_STATE_SETTLE_TIME) {
5340 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
5341 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5343 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
5344 !(ap->flags & MR_NP_RX)) {
5345 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
5353 case ANEG_STATE_IDLE_DETECT_INIT:
5354 ap->link_time = ap->cur_time;
5355 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5356 tw32_f(MAC_MODE, tp->mac_mode);
5359 ap->state = ANEG_STATE_IDLE_DETECT;
5360 ret = ANEG_TIMER_ENAB;
5363 case ANEG_STATE_IDLE_DETECT:
5364 if (ap->ability_match != 0 &&
5365 ap->rxconfig == 0) {
5366 ap->state = ANEG_STATE_AN_ENABLE;
5369 delta = ap->cur_time - ap->link_time;
5370 if (delta > ANEG_STATE_SETTLE_TIME) {
5371 /* XXX another gem from the Broadcom driver :( */
5372 ap->state = ANEG_STATE_LINK_OK;
5376 case ANEG_STATE_LINK_OK:
5377 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
5381 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
5382 /* ??? unimplemented */
5385 case ANEG_STATE_NEXT_PAGE_WAIT:
5386 /* ??? unimplemented */
5397 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
5400 struct tg3_fiber_aneginfo aninfo;
5401 int status = ANEG_FAILED;
5405 tw32_f(MAC_TX_AUTO_NEG, 0);
5407 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
5408 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5411 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5414 memset(&aninfo, 0, sizeof(aninfo));
5415 aninfo.flags |= MR_AN_ENABLE;
5416 aninfo.state = ANEG_STATE_UNKNOWN;
5417 aninfo.cur_time = 0;
5419 while (++tick < 195000) {
5420 status = tg3_fiber_aneg_smachine(tp, &aninfo);
5421 if (status == ANEG_DONE || status == ANEG_FAILED)
5427 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
5428 tw32_f(MAC_MODE, tp->mac_mode);
5431 *txflags = aninfo.txconfig;
5432 *rxflags = aninfo.flags;
5434 if (status == ANEG_DONE &&
5435 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
5436 MR_LP_ADV_FULL_DUPLEX)))
5442 static void tg3_init_bcm8002(struct tg3 *tp)
5444 u32 mac_status = tr32(MAC_STATUS);
5447 /* Reset when initting first time or we have a link. */
5448 if (tg3_flag(tp, INIT_COMPLETE) &&
5449 !(mac_status & MAC_STATUS_PCS_SYNCED))
5452 /* Set PLL lock range. */
5453 tg3_writephy(tp, 0x16, 0x8007);
5456 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
5458 /* Wait for reset to complete. */
5459 /* XXX schedule_timeout() ... */
5460 for (i = 0; i < 500; i++)
5463 /* Config mode; select PMA/Ch 1 regs. */
5464 tg3_writephy(tp, 0x10, 0x8411);
5466 /* Enable auto-lock and comdet, select txclk for tx. */
5467 tg3_writephy(tp, 0x11, 0x0a10);
5469 tg3_writephy(tp, 0x18, 0x00a0);
5470 tg3_writephy(tp, 0x16, 0x41ff);
5472 /* Assert and deassert POR. */
5473 tg3_writephy(tp, 0x13, 0x0400);
5475 tg3_writephy(tp, 0x13, 0x0000);
5477 tg3_writephy(tp, 0x11, 0x0a50);
5479 tg3_writephy(tp, 0x11, 0x0a10);
5481 /* Wait for signal to stabilize */
5482 /* XXX schedule_timeout() ... */
5483 for (i = 0; i < 15000; i++)
5486 /* Deselect the channel register so we can read the PHYID
5489 tg3_writephy(tp, 0x10, 0x8011);
5492 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
5495 bool current_link_up;
5496 u32 sg_dig_ctrl, sg_dig_status;
5497 u32 serdes_cfg, expected_sg_dig_ctrl;
5498 int workaround, port_a;
5501 expected_sg_dig_ctrl = 0;
5504 current_link_up = false;
5506 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 &&
5507 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) {
5509 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
5512 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5513 /* preserve bits 20-23 for voltage regulator */
5514 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
5517 sg_dig_ctrl = tr32(SG_DIG_CTRL);
5519 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
5520 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
5522 u32 val = serdes_cfg;
5528 tw32_f(MAC_SERDES_CFG, val);
5531 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5533 if (mac_status & MAC_STATUS_PCS_SYNCED) {
5534 tg3_setup_flow_control(tp, 0, 0);
5535 current_link_up = true;
5540 /* Want auto-negotiation. */
5541 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
5543 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5544 if (flowctrl & ADVERTISE_1000XPAUSE)
5545 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
5546 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
5547 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
5549 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
5550 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) &&
5551 tp->serdes_counter &&
5552 ((mac_status & (MAC_STATUS_PCS_SYNCED |
5553 MAC_STATUS_RCVD_CFG)) ==
5554 MAC_STATUS_PCS_SYNCED)) {
5555 tp->serdes_counter--;
5556 current_link_up = true;
5561 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5562 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5564 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5566 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5567 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5568 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
5569 MAC_STATUS_SIGNAL_DET)) {
5570 sg_dig_status = tr32(SG_DIG_STATUS);
5571 mac_status = tr32(MAC_STATUS);
5573 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
5574 (mac_status & MAC_STATUS_PCS_SYNCED)) {
5575 u32 local_adv = 0, remote_adv = 0;
5577 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
5578 local_adv |= ADVERTISE_1000XPAUSE;
5579 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
5580 local_adv |= ADVERTISE_1000XPSE_ASYM;
5582 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
5583 remote_adv |= LPA_1000XPAUSE;
5584 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
5585 remote_adv |= LPA_1000XPAUSE_ASYM;
5587 tp->link_config.rmt_adv =
5588 mii_adv_to_ethtool_adv_x(remote_adv);
5590 tg3_setup_flow_control(tp, local_adv, remote_adv);
5591 current_link_up = true;
5592 tp->serdes_counter = 0;
5593 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5594 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
5595 if (tp->serdes_counter)
5596 tp->serdes_counter--;
5599 u32 val = serdes_cfg;
5606 tw32_f(MAC_SERDES_CFG, val);
5609 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5612 /* Link parallel detection - link is up */
5613 /* only if we have PCS_SYNC and not */
5614 /* receiving config code words */
5615 mac_status = tr32(MAC_STATUS);
5616 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
5617 !(mac_status & MAC_STATUS_RCVD_CFG)) {
5618 tg3_setup_flow_control(tp, 0, 0);
5619 current_link_up = true;
5621 TG3_PHYFLG_PARALLEL_DETECT;
5622 tp->serdes_counter =
5623 SERDES_PARALLEL_DET_TIMEOUT;
5625 goto restart_autoneg;
5629 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
5630 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5634 return current_link_up;
5637 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
5639 bool current_link_up = false;
5641 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
5644 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5645 u32 txflags, rxflags;
5648 if (fiber_autoneg(tp, &txflags, &rxflags)) {
5649 u32 local_adv = 0, remote_adv = 0;
5651 if (txflags & ANEG_CFG_PS1)
5652 local_adv |= ADVERTISE_1000XPAUSE;
5653 if (txflags & ANEG_CFG_PS2)
5654 local_adv |= ADVERTISE_1000XPSE_ASYM;
5656 if (rxflags & MR_LP_ADV_SYM_PAUSE)
5657 remote_adv |= LPA_1000XPAUSE;
5658 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
5659 remote_adv |= LPA_1000XPAUSE_ASYM;
5661 tp->link_config.rmt_adv =
5662 mii_adv_to_ethtool_adv_x(remote_adv);
5664 tg3_setup_flow_control(tp, local_adv, remote_adv);
5666 current_link_up = true;
5668 for (i = 0; i < 30; i++) {
5671 (MAC_STATUS_SYNC_CHANGED |
5672 MAC_STATUS_CFG_CHANGED));
5674 if ((tr32(MAC_STATUS) &
5675 (MAC_STATUS_SYNC_CHANGED |
5676 MAC_STATUS_CFG_CHANGED)) == 0)
5680 mac_status = tr32(MAC_STATUS);
5681 if (!current_link_up &&
5682 (mac_status & MAC_STATUS_PCS_SYNCED) &&
5683 !(mac_status & MAC_STATUS_RCVD_CFG))
5684 current_link_up = true;
5686 tg3_setup_flow_control(tp, 0, 0);
5688 /* Forcing 1000FD link up. */
5689 current_link_up = true;
5691 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5694 tw32_f(MAC_MODE, tp->mac_mode);
5699 return current_link_up;
5702 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset)
5705 u16 orig_active_speed;
5706 u8 orig_active_duplex;
5708 bool current_link_up;
5711 orig_pause_cfg = tp->link_config.active_flowctrl;
5712 orig_active_speed = tp->link_config.active_speed;
5713 orig_active_duplex = tp->link_config.active_duplex;
5715 if (!tg3_flag(tp, HW_AUTONEG) &&
5717 tg3_flag(tp, INIT_COMPLETE)) {
5718 mac_status = tr32(MAC_STATUS);
5719 mac_status &= (MAC_STATUS_PCS_SYNCED |
5720 MAC_STATUS_SIGNAL_DET |
5721 MAC_STATUS_CFG_CHANGED |
5722 MAC_STATUS_RCVD_CFG);
5723 if (mac_status == (MAC_STATUS_PCS_SYNCED |
5724 MAC_STATUS_SIGNAL_DET)) {
5725 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5726 MAC_STATUS_CFG_CHANGED));
5731 tw32_f(MAC_TX_AUTO_NEG, 0);
5733 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
5734 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
5735 tw32_f(MAC_MODE, tp->mac_mode);
5738 if (tp->phy_id == TG3_PHY_ID_BCM8002)
5739 tg3_init_bcm8002(tp);
5741 /* Enable link change event even when serdes polling. */
5742 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5745 current_link_up = false;
5746 tp->link_config.rmt_adv = 0;
5747 mac_status = tr32(MAC_STATUS);
5749 if (tg3_flag(tp, HW_AUTONEG))
5750 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
5752 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
5754 tp->napi[0].hw_status->status =
5755 (SD_STATUS_UPDATED |
5756 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
5758 for (i = 0; i < 100; i++) {
5759 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5760 MAC_STATUS_CFG_CHANGED));
5762 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
5763 MAC_STATUS_CFG_CHANGED |
5764 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
5768 mac_status = tr32(MAC_STATUS);
5769 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
5770 current_link_up = false;
5771 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
5772 tp->serdes_counter == 0) {
5773 tw32_f(MAC_MODE, (tp->mac_mode |
5774 MAC_MODE_SEND_CONFIGS));
5776 tw32_f(MAC_MODE, tp->mac_mode);
5780 if (current_link_up) {
5781 tp->link_config.active_speed = SPEED_1000;
5782 tp->link_config.active_duplex = DUPLEX_FULL;
5783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5784 LED_CTRL_LNKLED_OVERRIDE |
5785 LED_CTRL_1000MBPS_ON));
5787 tp->link_config.active_speed = SPEED_UNKNOWN;
5788 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
5789 tw32(MAC_LED_CTRL, (tp->led_ctrl |
5790 LED_CTRL_LNKLED_OVERRIDE |
5791 LED_CTRL_TRAFFIC_OVERRIDE));
5794 if (!tg3_test_and_report_link_chg(tp, current_link_up)) {
5795 u32 now_pause_cfg = tp->link_config.active_flowctrl;
5796 if (orig_pause_cfg != now_pause_cfg ||
5797 orig_active_speed != tp->link_config.active_speed ||
5798 orig_active_duplex != tp->link_config.active_duplex)
5799 tg3_link_report(tp);
5805 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset)
5809 u16 current_speed = SPEED_UNKNOWN;
5810 u8 current_duplex = DUPLEX_UNKNOWN;
5811 bool current_link_up = false;
5812 u32 local_adv, remote_adv, sgsr;
5814 if ((tg3_asic_rev(tp) == ASIC_REV_5719 ||
5815 tg3_asic_rev(tp) == ASIC_REV_5720) &&
5816 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) &&
5817 (sgsr & SERDES_TG3_SGMII_MODE)) {
5822 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
5824 if (!(sgsr & SERDES_TG3_LINK_UP)) {
5825 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5827 current_link_up = true;
5828 if (sgsr & SERDES_TG3_SPEED_1000) {
5829 current_speed = SPEED_1000;
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5831 } else if (sgsr & SERDES_TG3_SPEED_100) {
5832 current_speed = SPEED_100;
5833 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5835 current_speed = SPEED_10;
5836 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
5839 if (sgsr & SERDES_TG3_FULL_DUPLEX)
5840 current_duplex = DUPLEX_FULL;
5842 current_duplex = DUPLEX_HALF;
5845 tw32_f(MAC_MODE, tp->mac_mode);
5848 tg3_clear_mac_status(tp);
5850 goto fiber_setup_done;
5853 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
5854 tw32_f(MAC_MODE, tp->mac_mode);
5857 tg3_clear_mac_status(tp);
5862 tp->link_config.rmt_adv = 0;
5864 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5865 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5866 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5867 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5868 bmsr |= BMSR_LSTATUS;
5870 bmsr &= ~BMSR_LSTATUS;
5873 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
5875 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
5876 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
5877 /* do nothing, just check for link up at the end */
5878 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
5881 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5882 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
5883 ADVERTISE_1000XPAUSE |
5884 ADVERTISE_1000XPSE_ASYM |
5887 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
5888 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising);
5890 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) {
5891 tg3_writephy(tp, MII_ADVERTISE, newadv);
5892 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
5893 tg3_writephy(tp, MII_BMCR, bmcr);
5895 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5896 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
5897 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5904 bmcr &= ~BMCR_SPEED1000;
5905 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
5907 if (tp->link_config.duplex == DUPLEX_FULL)
5908 new_bmcr |= BMCR_FULLDPLX;
5910 if (new_bmcr != bmcr) {
5911 /* BMCR_SPEED1000 is a reserved bit that needs
5912 * to be set on write.
5914 new_bmcr |= BMCR_SPEED1000;
5916 /* Force a linkdown */
5920 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
5921 adv &= ~(ADVERTISE_1000XFULL |
5922 ADVERTISE_1000XHALF |
5924 tg3_writephy(tp, MII_ADVERTISE, adv);
5925 tg3_writephy(tp, MII_BMCR, bmcr |
5929 tg3_carrier_off(tp);
5931 tg3_writephy(tp, MII_BMCR, new_bmcr);
5933 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5934 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
5935 if (tg3_asic_rev(tp) == ASIC_REV_5714) {
5936 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
5937 bmsr |= BMSR_LSTATUS;
5939 bmsr &= ~BMSR_LSTATUS;
5941 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
5945 if (bmsr & BMSR_LSTATUS) {
5946 current_speed = SPEED_1000;
5947 current_link_up = true;
5948 if (bmcr & BMCR_FULLDPLX)
5949 current_duplex = DUPLEX_FULL;
5951 current_duplex = DUPLEX_HALF;
5956 if (bmcr & BMCR_ANENABLE) {
5959 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
5960 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
5961 common = local_adv & remote_adv;
5962 if (common & (ADVERTISE_1000XHALF |
5963 ADVERTISE_1000XFULL)) {
5964 if (common & ADVERTISE_1000XFULL)
5965 current_duplex = DUPLEX_FULL;
5967 current_duplex = DUPLEX_HALF;
5969 tp->link_config.rmt_adv =
5970 mii_adv_to_ethtool_adv_x(remote_adv);
5971 } else if (!tg3_flag(tp, 5780_CLASS)) {
5972 /* Link is up via parallel detect */
5974 current_link_up = false;
5980 if (current_link_up && current_duplex == DUPLEX_FULL)
5981 tg3_setup_flow_control(tp, local_adv, remote_adv);
5983 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
5984 if (tp->link_config.active_duplex == DUPLEX_HALF)
5985 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
5987 tw32_f(MAC_MODE, tp->mac_mode);
5990 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 tp->link_config.active_speed = current_speed;
5993 tp->link_config.active_duplex = current_duplex;
5995 tg3_test_and_report_link_chg(tp, current_link_up);
5999 static void tg3_serdes_parallel_detect(struct tg3 *tp)
6001 if (tp->serdes_counter) {
6002 /* Give autoneg time to complete. */
6003 tp->serdes_counter--;
6008 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
6011 tg3_readphy(tp, MII_BMCR, &bmcr);
6012 if (bmcr & BMCR_ANENABLE) {
6015 /* Select shadow register 0x1f */
6016 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00);
6017 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1);
6019 /* Select expansion interrupt status register */
6020 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6021 MII_TG3_DSP_EXP1_INT_STAT);
6022 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6023 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6025 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
6026 /* We have signal detect and not receiving
6027 * config code words, link is up by parallel
6031 bmcr &= ~BMCR_ANENABLE;
6032 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
6033 tg3_writephy(tp, MII_BMCR, bmcr);
6034 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT;
6037 } else if (tp->link_up &&
6038 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
6039 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) {
6042 /* Select expansion interrupt status register */
6043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
6044 MII_TG3_DSP_EXP1_INT_STAT);
6045 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2);
6049 /* Config code words received, turn on autoneg. */
6050 tg3_readphy(tp, MII_BMCR, &bmcr);
6051 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
6053 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
6059 static int tg3_setup_phy(struct tg3 *tp, bool force_reset)
6064 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
6065 err = tg3_setup_fiber_phy(tp, force_reset);
6066 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
6067 err = tg3_setup_fiber_mii_phy(tp, force_reset);
6069 err = tg3_setup_copper_phy(tp, force_reset);
6071 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
6074 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
6075 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
6077 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
6082 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
6083 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
6084 tw32(GRC_MISC_CFG, val);
6087 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6088 (6 << TX_LENGTHS_IPG_SHIFT);
6089 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
6090 tg3_asic_rev(tp) == ASIC_REV_5762)
6091 val |= tr32(MAC_TX_LENGTHS) &
6092 (TX_LENGTHS_JMB_FRM_LEN_MSK |
6093 TX_LENGTHS_CNT_DWN_VAL_MSK);
6095 if (tp->link_config.active_speed == SPEED_1000 &&
6096 tp->link_config.active_duplex == DUPLEX_HALF)
6097 tw32(MAC_TX_LENGTHS, val |
6098 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
6100 tw32(MAC_TX_LENGTHS, val |
6101 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6103 if (!tg3_flag(tp, 5705_PLUS)) {
6105 tw32(HOSTCC_STAT_COAL_TICKS,
6106 tp->coal.stats_block_coalesce_usecs);
6108 tw32(HOSTCC_STAT_COAL_TICKS, 0);
6112 if (tg3_flag(tp, ASPM_WORKAROUND)) {
6113 val = tr32(PCIE_PWR_MGMT_THRESH);
6115 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
6118 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
6119 tw32(PCIE_PWR_MGMT_THRESH, val);
6125 /* tp->lock must be held */
6126 static u64 tg3_refclk_read(struct tg3 *tp)
6128 u64 stamp = tr32(TG3_EAV_REF_CLCK_LSB);
6129 return stamp | (u64)tr32(TG3_EAV_REF_CLCK_MSB) << 32;
6132 /* tp->lock must be held */
6133 static void tg3_refclk_write(struct tg3 *tp, u64 newval)
6135 u32 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6137 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_STOP);
6138 tw32(TG3_EAV_REF_CLCK_LSB, newval & 0xffffffff);
6139 tw32(TG3_EAV_REF_CLCK_MSB, newval >> 32);
6140 tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
6143 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6144 static inline void tg3_full_unlock(struct tg3 *tp);
6145 static int tg3_get_ts_info(struct net_device *dev, struct ethtool_ts_info *info)
6147 struct tg3 *tp = netdev_priv(dev);
6149 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
6150 SOF_TIMESTAMPING_RX_SOFTWARE |
6151 SOF_TIMESTAMPING_SOFTWARE;
6153 if (tg3_flag(tp, PTP_CAPABLE)) {
6154 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE |
6155 SOF_TIMESTAMPING_RX_HARDWARE |
6156 SOF_TIMESTAMPING_RAW_HARDWARE;
6160 info->phc_index = ptp_clock_index(tp->ptp_clock);
6162 info->phc_index = -1;
6164 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
6166 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
6167 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
6168 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
6169 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT);
6173 static int tg3_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
6175 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6176 bool neg_adj = false;
6184 /* Frequency adjustment is performed using hardware with a 24 bit
6185 * accumulator and a programmable correction value. On each clk, the
6186 * correction value gets added to the accumulator and when it
6187 * overflows, the time counter is incremented/decremented.
6189 * So conversion from ppb to correction value is
6190 * ppb * (1 << 24) / 1000000000
6192 correction = div_u64((u64)ppb * (1 << 24), 1000000000ULL) &
6193 TG3_EAV_REF_CLK_CORRECT_MASK;
6195 tg3_full_lock(tp, 0);
6198 tw32(TG3_EAV_REF_CLK_CORRECT_CTL,
6199 TG3_EAV_REF_CLK_CORRECT_EN |
6200 (neg_adj ? TG3_EAV_REF_CLK_CORRECT_NEG : 0) | correction);
6202 tw32(TG3_EAV_REF_CLK_CORRECT_CTL, 0);
6204 tg3_full_unlock(tp);
6209 static int tg3_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
6211 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6213 tg3_full_lock(tp, 0);
6214 tp->ptp_adjust += delta;
6215 tg3_full_unlock(tp);
6220 static int tg3_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
6224 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6226 tg3_full_lock(tp, 0);
6227 ns = tg3_refclk_read(tp);
6228 ns += tp->ptp_adjust;
6229 tg3_full_unlock(tp);
6231 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
6232 ts->tv_nsec = remainder;
6237 static int tg3_ptp_settime(struct ptp_clock_info *ptp,
6238 const struct timespec *ts)
6241 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6243 ns = timespec_to_ns(ts);
6245 tg3_full_lock(tp, 0);
6246 tg3_refclk_write(tp, ns);
6248 tg3_full_unlock(tp);
6253 static int tg3_ptp_enable(struct ptp_clock_info *ptp,
6254 struct ptp_clock_request *rq, int on)
6256 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info);
6261 case PTP_CLK_REQ_PEROUT:
6262 if (rq->perout.index != 0)
6265 tg3_full_lock(tp, 0);
6266 clock_ctl = tr32(TG3_EAV_REF_CLCK_CTL);
6267 clock_ctl &= ~TG3_EAV_CTL_TSYNC_GPIO_MASK;
6272 nsec = rq->perout.start.sec * 1000000000ULL +
6273 rq->perout.start.nsec;
6275 if (rq->perout.period.sec || rq->perout.period.nsec) {
6276 netdev_warn(tp->dev,
6277 "Device supports only a one-shot timesync output, period must be 0\n");
6282 if (nsec & (1ULL << 63)) {
6283 netdev_warn(tp->dev,
6284 "Start value (nsec) is over limit. Maximum size of start is only 63 bits\n");
6289 tw32(TG3_EAV_WATCHDOG0_LSB, (nsec & 0xffffffff));
6290 tw32(TG3_EAV_WATCHDOG0_MSB,
6291 TG3_EAV_WATCHDOG0_EN |
6292 ((nsec >> 32) & TG3_EAV_WATCHDOG_MSB_MASK));
6294 tw32(TG3_EAV_REF_CLCK_CTL,
6295 clock_ctl | TG3_EAV_CTL_TSYNC_WDOG0);
6297 tw32(TG3_EAV_WATCHDOG0_MSB, 0);
6298 tw32(TG3_EAV_REF_CLCK_CTL, clock_ctl);
6302 tg3_full_unlock(tp);
6312 static const struct ptp_clock_info tg3_ptp_caps = {
6313 .owner = THIS_MODULE,
6314 .name = "tg3 clock",
6315 .max_adj = 250000000,
6321 .adjfreq = tg3_ptp_adjfreq,
6322 .adjtime = tg3_ptp_adjtime,
6323 .gettime = tg3_ptp_gettime,
6324 .settime = tg3_ptp_settime,
6325 .enable = tg3_ptp_enable,
6328 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock,
6329 struct skb_shared_hwtstamps *timestamp)
6331 memset(timestamp, 0, sizeof(struct skb_shared_hwtstamps));
6332 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) +
6336 /* tp->lock must be held */
6337 static void tg3_ptp_init(struct tg3 *tp)
6339 if (!tg3_flag(tp, PTP_CAPABLE))
6342 /* Initialize the hardware clock to the system time. */
6343 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()));
6345 tp->ptp_info = tg3_ptp_caps;
6348 /* tp->lock must be held */
6349 static void tg3_ptp_resume(struct tg3 *tp)
6351 if (!tg3_flag(tp, PTP_CAPABLE))
6354 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust);
6358 static void tg3_ptp_fini(struct tg3 *tp)
6360 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock)
6363 ptp_clock_unregister(tp->ptp_clock);
6364 tp->ptp_clock = NULL;
6368 static inline int tg3_irq_sync(struct tg3 *tp)
6370 return tp->irq_sync;
6373 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len)
6377 dst = (u32 *)((u8 *)dst + off);
6378 for (i = 0; i < len; i += sizeof(u32))
6379 *dst++ = tr32(off + i);
6382 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs)
6384 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0);
6385 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200);
6386 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0);
6387 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0);
6388 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04);
6389 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80);
6390 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48);
6391 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04);
6392 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20);
6393 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c);
6394 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c);
6395 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c);
6396 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44);
6397 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04);
6398 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20);
6399 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14);
6400 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08);
6401 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08);
6402 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100);
6404 if (tg3_flag(tp, SUPPORT_MSIX))
6405 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180);
6407 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10);
6408 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58);
6409 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08);
6410 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08);
6411 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04);
6412 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04);
6413 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04);
6414 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04);
6416 if (!tg3_flag(tp, 5705_PLUS)) {
6417 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04);
6418 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04);
6419 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04);
6422 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110);
6423 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120);
6424 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c);
6425 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04);
6426 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c);
6428 if (tg3_flag(tp, NVRAM))
6429 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24);
6432 static void tg3_dump_state(struct tg3 *tp)
6437 regs = kzalloc(TG3_REG_BLK_SIZE, GFP_ATOMIC);
6441 if (tg3_flag(tp, PCI_EXPRESS)) {
6442 /* Read up to but not including private PCI registers */
6443 for (i = 0; i < TG3_PCIE_TLDLPL_PORT; i += sizeof(u32))
6444 regs[i / sizeof(u32)] = tr32(i);
6446 tg3_dump_legacy_regs(tp, regs);
6448 for (i = 0; i < TG3_REG_BLK_SIZE / sizeof(u32); i += 4) {
6449 if (!regs[i + 0] && !regs[i + 1] &&
6450 !regs[i + 2] && !regs[i + 3])
6453 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6455 regs[i + 0], regs[i + 1], regs[i + 2], regs[i + 3]);
6460 for (i = 0; i < tp->irq_cnt; i++) {
6461 struct tg3_napi *tnapi = &tp->napi[i];
6463 /* SW status block */
6465 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6467 tnapi->hw_status->status,
6468 tnapi->hw_status->status_tag,
6469 tnapi->hw_status->rx_jumbo_consumer,
6470 tnapi->hw_status->rx_consumer,
6471 tnapi->hw_status->rx_mini_consumer,
6472 tnapi->hw_status->idx[0].rx_producer,
6473 tnapi->hw_status->idx[0].tx_consumer);
6476 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6478 tnapi->last_tag, tnapi->last_irq_tag,
6479 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending,
6481 tnapi->prodring.rx_std_prod_idx,
6482 tnapi->prodring.rx_std_cons_idx,
6483 tnapi->prodring.rx_jmb_prod_idx,
6484 tnapi->prodring.rx_jmb_cons_idx);
6488 /* This is called whenever we suspect that the system chipset is re-
6489 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6490 * is bogus tx completions. We try to recover by setting the
6491 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6494 static void tg3_tx_recover(struct tg3 *tp)
6496 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) ||
6497 tp->write32_tx_mbox == tg3_write_indirect_mbox);
6499 netdev_warn(tp->dev,
6500 "The system may be re-ordering memory-mapped I/O "
6501 "cycles to the network device, attempting to recover. "
6502 "Please report the problem to the driver maintainer "
6503 "and include system chipset information.\n");
6505 tg3_flag_set(tp, TX_RECOVERY_PENDING);
6508 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
6510 /* Tell compiler to fetch tx indices from memory. */
6512 return tnapi->tx_pending -
6513 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
6516 /* Tigon3 never reports partial packet sends. So we do not
6517 * need special logic to handle SKBs that have not had all
6518 * of their frags sent yet, like SunGEM does.
6520 static void tg3_tx(struct tg3_napi *tnapi)
6522 struct tg3 *tp = tnapi->tp;
6523 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
6524 u32 sw_idx = tnapi->tx_cons;
6525 struct netdev_queue *txq;
6526 int index = tnapi - tp->napi;
6527 unsigned int pkts_compl = 0, bytes_compl = 0;
6529 if (tg3_flag(tp, ENABLE_TSS))
6532 txq = netdev_get_tx_queue(tp->dev, index);
6534 while (sw_idx != hw_idx) {
6535 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx];
6536 struct sk_buff *skb = ri->skb;
6539 if (unlikely(skb == NULL)) {
6544 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) {
6545 struct skb_shared_hwtstamps timestamp;
6546 u64 hwclock = tr32(TG3_TX_TSTAMP_LSB);
6547 hwclock |= (u64)tr32(TG3_TX_TSTAMP_MSB) << 32;
6549 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp);
6551 skb_tstamp_tx(skb, ×tamp);
6554 pci_unmap_single(tp->pdev,
6555 dma_unmap_addr(ri, mapping),
6561 while (ri->fragmented) {
6562 ri->fragmented = false;
6563 sw_idx = NEXT_TX(sw_idx);
6564 ri = &tnapi->tx_buffers[sw_idx];
6567 sw_idx = NEXT_TX(sw_idx);
6569 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
6570 ri = &tnapi->tx_buffers[sw_idx];
6571 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
6574 pci_unmap_page(tp->pdev,
6575 dma_unmap_addr(ri, mapping),
6576 skb_frag_size(&skb_shinfo(skb)->frags[i]),
6579 while (ri->fragmented) {
6580 ri->fragmented = false;
6581 sw_idx = NEXT_TX(sw_idx);
6582 ri = &tnapi->tx_buffers[sw_idx];
6585 sw_idx = NEXT_TX(sw_idx);
6589 bytes_compl += skb->len;
6591 dev_kfree_skb_any(skb);
6593 if (unlikely(tx_bug)) {
6599 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
6601 tnapi->tx_cons = sw_idx;
6603 /* Need to make the tx_cons update visible to tg3_start_xmit()
6604 * before checking for netif_queue_stopped(). Without the
6605 * memory barrier, there is a small possibility that tg3_start_xmit()
6606 * will miss it and cause the queue to be stopped forever.
6610 if (unlikely(netif_tx_queue_stopped(txq) &&
6611 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
6612 __netif_tx_lock(txq, smp_processor_id());
6613 if (netif_tx_queue_stopped(txq) &&
6614 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
6615 netif_tx_wake_queue(txq);
6616 __netif_tx_unlock(txq);
6620 static void tg3_frag_free(bool is_frag, void *data)
6623 put_page(virt_to_head_page(data));
6628 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
6630 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) +
6631 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6636 pci_unmap_single(tp->pdev, dma_unmap_addr(ri, mapping),
6637 map_sz, PCI_DMA_FROMDEVICE);
6638 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data);
6643 /* Returns size of skb allocated or < 0 on error.
6645 * We only need to fill in the address because the other members
6646 * of the RX descriptor are invariant, see tg3_init_rings.
6648 * Note the purposeful assymetry of cpu vs. chip accesses. For
6649 * posting buffers we only dirty the first cache line of the RX
6650 * descriptor (containing the address). Whereas for the RX status
6651 * buffers the cpu only reads the last cacheline of the RX descriptor
6652 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6654 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
6655 u32 opaque_key, u32 dest_idx_unmasked,
6656 unsigned int *frag_size)
6658 struct tg3_rx_buffer_desc *desc;
6659 struct ring_info *map;
6662 int skb_size, data_size, dest_idx;
6664 switch (opaque_key) {
6665 case RXD_OPAQUE_RING_STD:
6666 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6667 desc = &tpr->rx_std[dest_idx];
6668 map = &tpr->rx_std_buffers[dest_idx];
6669 data_size = tp->rx_pkt_map_sz;
6672 case RXD_OPAQUE_RING_JUMBO:
6673 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6674 desc = &tpr->rx_jmb[dest_idx].std;
6675 map = &tpr->rx_jmb_buffers[dest_idx];
6676 data_size = TG3_RX_JMB_MAP_SZ;
6683 /* Do not overwrite any of the map or rp information
6684 * until we are sure we can commit to a new buffer.
6686 * Callers depend upon this behavior and assume that
6687 * we leave everything unchanged if we fail.
6689 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) +
6690 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
6691 if (skb_size <= PAGE_SIZE) {
6692 data = netdev_alloc_frag(skb_size);
6693 *frag_size = skb_size;
6695 data = kmalloc(skb_size, GFP_ATOMIC);
6701 mapping = pci_map_single(tp->pdev,
6702 data + TG3_RX_OFFSET(tp),
6704 PCI_DMA_FROMDEVICE);
6705 if (unlikely(pci_dma_mapping_error(tp->pdev, mapping))) {
6706 tg3_frag_free(skb_size <= PAGE_SIZE, data);
6711 dma_unmap_addr_set(map, mapping, mapping);
6713 desc->addr_hi = ((u64)mapping >> 32);
6714 desc->addr_lo = ((u64)mapping & 0xffffffff);
6719 /* We only need to move over in the address because the other
6720 * members of the RX descriptor are invariant. See notes above
6721 * tg3_alloc_rx_data for full details.
6723 static void tg3_recycle_rx(struct tg3_napi *tnapi,
6724 struct tg3_rx_prodring_set *dpr,
6725 u32 opaque_key, int src_idx,
6726 u32 dest_idx_unmasked)
6728 struct tg3 *tp = tnapi->tp;
6729 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
6730 struct ring_info *src_map, *dest_map;
6731 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring;
6734 switch (opaque_key) {
6735 case RXD_OPAQUE_RING_STD:
6736 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask;
6737 dest_desc = &dpr->rx_std[dest_idx];
6738 dest_map = &dpr->rx_std_buffers[dest_idx];
6739 src_desc = &spr->rx_std[src_idx];
6740 src_map = &spr->rx_std_buffers[src_idx];
6743 case RXD_OPAQUE_RING_JUMBO:
6744 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask;
6745 dest_desc = &dpr->rx_jmb[dest_idx].std;
6746 dest_map = &dpr->rx_jmb_buffers[dest_idx];
6747 src_desc = &spr->rx_jmb[src_idx].std;
6748 src_map = &spr->rx_jmb_buffers[src_idx];
6755 dest_map->data = src_map->data;
6756 dma_unmap_addr_set(dest_map, mapping,
6757 dma_unmap_addr(src_map, mapping));
6758 dest_desc->addr_hi = src_desc->addr_hi;
6759 dest_desc->addr_lo = src_desc->addr_lo;
6761 /* Ensure that the update to the skb happens after the physical
6762 * addresses have been transferred to the new BD location.
6766 src_map->data = NULL;
6769 /* The RX ring scheme is composed of multiple rings which post fresh
6770 * buffers to the chip, and one special ring the chip uses to report
6771 * status back to the host.
6773 * The special ring reports the status of received packets to the
6774 * host. The chip does not write into the original descriptor the
6775 * RX buffer was obtained from. The chip simply takes the original
6776 * descriptor as provided by the host, updates the status and length
6777 * field, then writes this into the next status ring entry.
6779 * Each ring the host uses to post buffers to the chip is described
6780 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6781 * it is first placed into the on-chip ram. When the packet's length
6782 * is known, it walks down the TG3_BDINFO entries to select the ring.
6783 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6784 * which is within the range of the new packet's length is chosen.
6786 * The "separate ring for rx status" scheme may sound queer, but it makes
6787 * sense from a cache coherency perspective. If only the host writes
6788 * to the buffer post rings, and only the chip writes to the rx status
6789 * rings, then cache lines never move beyond shared-modified state.
6790 * If both the host and chip were to write into the same ring, cache line
6791 * eviction could occur since both entities want it in an exclusive state.
6793 static int tg3_rx(struct tg3_napi *tnapi, int budget)
6795 struct tg3 *tp = tnapi->tp;
6796 u32 work_mask, rx_std_posted = 0;
6797 u32 std_prod_idx, jmb_prod_idx;
6798 u32 sw_idx = tnapi->rx_rcb_ptr;
6801 struct tg3_rx_prodring_set *tpr = &tnapi->prodring;
6803 hw_idx = *(tnapi->rx_rcb_prod_idx);
6805 * We need to order the read of hw_idx and the read of
6806 * the opaque cookie.
6811 std_prod_idx = tpr->rx_std_prod_idx;
6812 jmb_prod_idx = tpr->rx_jmb_prod_idx;
6813 while (sw_idx != hw_idx && budget > 0) {
6814 struct ring_info *ri;
6815 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
6817 struct sk_buff *skb;
6818 dma_addr_t dma_addr;
6819 u32 opaque_key, desc_idx, *post_ptr;
6823 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
6824 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
6825 if (opaque_key == RXD_OPAQUE_RING_STD) {
6826 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx];
6827 dma_addr = dma_unmap_addr(ri, mapping);
6829 post_ptr = &std_prod_idx;
6831 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
6832 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx];
6833 dma_addr = dma_unmap_addr(ri, mapping);
6835 post_ptr = &jmb_prod_idx;
6837 goto next_pkt_nopost;
6839 work_mask |= opaque_key;
6841 if (desc->err_vlan & RXD_ERR_MASK) {
6843 tg3_recycle_rx(tnapi, tpr, opaque_key,
6844 desc_idx, *post_ptr);
6846 /* Other statistics kept track of by card. */
6851 prefetch(data + TG3_RX_OFFSET(tp));
6852 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
6855 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6856 RXD_FLAG_PTPSTAT_PTPV1 ||
6857 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) ==
6858 RXD_FLAG_PTPSTAT_PTPV2) {
6859 tstamp = tr32(TG3_RX_TSTAMP_LSB);
6860 tstamp |= (u64)tr32(TG3_RX_TSTAMP_MSB) << 32;
6863 if (len > TG3_RX_COPY_THRESH(tp)) {
6865 unsigned int frag_size;
6867 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key,
6868 *post_ptr, &frag_size);
6872 pci_unmap_single(tp->pdev, dma_addr, skb_size,
6873 PCI_DMA_FROMDEVICE);
6875 /* Ensure that the update to the data happens
6876 * after the usage of the old DMA mapping.
6882 skb = build_skb(data, frag_size);
6884 tg3_frag_free(frag_size != 0, data);
6885 goto drop_it_no_recycle;
6887 skb_reserve(skb, TG3_RX_OFFSET(tp));
6889 tg3_recycle_rx(tnapi, tpr, opaque_key,
6890 desc_idx, *post_ptr);
6892 skb = netdev_alloc_skb(tp->dev,
6893 len + TG3_RAW_IP_ALIGN);
6895 goto drop_it_no_recycle;
6897 skb_reserve(skb, TG3_RAW_IP_ALIGN);
6898 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6900 data + TG3_RX_OFFSET(tp),
6902 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
6907 tg3_hwclock_to_timestamp(tp, tstamp,
6908 skb_hwtstamps(skb));
6910 if ((tp->dev->features & NETIF_F_RXCSUM) &&
6911 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
6912 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
6913 >> RXD_TCPCSUM_SHIFT) == 0xffff))
6914 skb->ip_summed = CHECKSUM_UNNECESSARY;
6916 skb_checksum_none_assert(skb);
6918 skb->protocol = eth_type_trans(skb, tp->dev);
6920 if (len > (tp->dev->mtu + ETH_HLEN) &&
6921 skb->protocol != htons(ETH_P_8021Q) &&
6922 skb->protocol != htons(ETH_P_8021AD)) {
6923 dev_kfree_skb_any(skb);
6924 goto drop_it_no_recycle;
6927 if (desc->type_flags & RXD_FLAG_VLAN &&
6928 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG))
6929 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
6930 desc->err_vlan & RXD_VLAN_MASK);
6932 napi_gro_receive(&tnapi->napi, skb);
6940 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
6941 tpr->rx_std_prod_idx = std_prod_idx &
6942 tp->rx_std_ring_mask;
6943 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6944 tpr->rx_std_prod_idx);
6945 work_mask &= ~RXD_OPAQUE_RING_STD;
6950 sw_idx &= tp->rx_ret_ring_mask;
6952 /* Refresh hw_idx to see if there is new work */
6953 if (sw_idx == hw_idx) {
6954 hw_idx = *(tnapi->rx_rcb_prod_idx);
6959 /* ACK the status ring. */
6960 tnapi->rx_rcb_ptr = sw_idx;
6961 tw32_rx_mbox(tnapi->consmbox, sw_idx);
6963 /* Refill RX ring(s). */
6964 if (!tg3_flag(tp, ENABLE_RSS)) {
6965 /* Sync BD data before updating mailbox */
6968 if (work_mask & RXD_OPAQUE_RING_STD) {
6969 tpr->rx_std_prod_idx = std_prod_idx &
6970 tp->rx_std_ring_mask;
6971 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
6972 tpr->rx_std_prod_idx);
6974 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
6975 tpr->rx_jmb_prod_idx = jmb_prod_idx &
6976 tp->rx_jmb_ring_mask;
6977 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
6978 tpr->rx_jmb_prod_idx);
6981 } else if (work_mask) {
6982 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6983 * updated before the producer indices can be updated.
6987 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask;
6988 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask;
6990 if (tnapi != &tp->napi[1]) {
6991 tp->rx_refill = true;
6992 napi_schedule(&tp->napi[1].napi);
6999 static void tg3_poll_link(struct tg3 *tp)
7001 /* handle link change and other phy events */
7002 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) {
7003 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
7005 if (sblk->status & SD_STATUS_LINK_CHG) {
7006 sblk->status = SD_STATUS_UPDATED |
7007 (sblk->status & ~SD_STATUS_LINK_CHG);
7008 spin_lock(&tp->lock);
7009 if (tg3_flag(tp, USE_PHYLIB)) {
7011 (MAC_STATUS_SYNC_CHANGED |
7012 MAC_STATUS_CFG_CHANGED |
7013 MAC_STATUS_MI_COMPLETION |
7014 MAC_STATUS_LNKSTATE_CHANGED));
7017 tg3_setup_phy(tp, false);
7018 spin_unlock(&tp->lock);
7023 static int tg3_rx_prodring_xfer(struct tg3 *tp,
7024 struct tg3_rx_prodring_set *dpr,
7025 struct tg3_rx_prodring_set *spr)
7027 u32 si, di, cpycnt, src_prod_idx;
7031 src_prod_idx = spr->rx_std_prod_idx;
7033 /* Make sure updates to the rx_std_buffers[] entries and the
7034 * standard producer index are seen in the correct order.
7038 if (spr->rx_std_cons_idx == src_prod_idx)
7041 if (spr->rx_std_cons_idx < src_prod_idx)
7042 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
7044 cpycnt = tp->rx_std_ring_mask + 1 -
7045 spr->rx_std_cons_idx;
7047 cpycnt = min(cpycnt,
7048 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx);
7050 si = spr->rx_std_cons_idx;
7051 di = dpr->rx_std_prod_idx;
7053 for (i = di; i < di + cpycnt; i++) {
7054 if (dpr->rx_std_buffers[i].data) {
7064 /* Ensure that updates to the rx_std_buffers ring and the
7065 * shadowed hardware producer ring from tg3_recycle_skb() are
7066 * ordered correctly WRT the skb check above.
7070 memcpy(&dpr->rx_std_buffers[di],
7071 &spr->rx_std_buffers[si],
7072 cpycnt * sizeof(struct ring_info));
7074 for (i = 0; i < cpycnt; i++, di++, si++) {
7075 struct tg3_rx_buffer_desc *sbd, *dbd;
7076 sbd = &spr->rx_std[si];
7077 dbd = &dpr->rx_std[di];
7078 dbd->addr_hi = sbd->addr_hi;
7079 dbd->addr_lo = sbd->addr_lo;
7082 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) &
7083 tp->rx_std_ring_mask;
7084 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) &
7085 tp->rx_std_ring_mask;
7089 src_prod_idx = spr->rx_jmb_prod_idx;
7091 /* Make sure updates to the rx_jmb_buffers[] entries and
7092 * the jumbo producer index are seen in the correct order.
7096 if (spr->rx_jmb_cons_idx == src_prod_idx)
7099 if (spr->rx_jmb_cons_idx < src_prod_idx)
7100 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
7102 cpycnt = tp->rx_jmb_ring_mask + 1 -
7103 spr->rx_jmb_cons_idx;
7105 cpycnt = min(cpycnt,
7106 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx);
7108 si = spr->rx_jmb_cons_idx;
7109 di = dpr->rx_jmb_prod_idx;
7111 for (i = di; i < di + cpycnt; i++) {
7112 if (dpr->rx_jmb_buffers[i].data) {
7122 /* Ensure that updates to the rx_jmb_buffers ring and the
7123 * shadowed hardware producer ring from tg3_recycle_skb() are
7124 * ordered correctly WRT the skb check above.
7128 memcpy(&dpr->rx_jmb_buffers[di],
7129 &spr->rx_jmb_buffers[si],
7130 cpycnt * sizeof(struct ring_info));
7132 for (i = 0; i < cpycnt; i++, di++, si++) {
7133 struct tg3_rx_buffer_desc *sbd, *dbd;
7134 sbd = &spr->rx_jmb[si].std;
7135 dbd = &dpr->rx_jmb[di].std;
7136 dbd->addr_hi = sbd->addr_hi;
7137 dbd->addr_lo = sbd->addr_lo;
7140 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) &
7141 tp->rx_jmb_ring_mask;
7142 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) &
7143 tp->rx_jmb_ring_mask;
7149 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
7151 struct tg3 *tp = tnapi->tp;
7153 /* run TX completion thread */
7154 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
7156 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7160 if (!tnapi->rx_rcb_prod_idx)
7163 /* run RX thread, within the bounds set by NAPI.
7164 * All RX "locking" is done by ensuring outside
7165 * code synchronizes with tg3->napi.poll()
7167 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
7168 work_done += tg3_rx(tnapi, budget - work_done);
7170 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) {
7171 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring;
7173 u32 std_prod_idx = dpr->rx_std_prod_idx;
7174 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx;
7176 tp->rx_refill = false;
7177 for (i = 1; i <= tp->rxq_cnt; i++)
7178 err |= tg3_rx_prodring_xfer(tp, dpr,
7179 &tp->napi[i].prodring);
7183 if (std_prod_idx != dpr->rx_std_prod_idx)
7184 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
7185 dpr->rx_std_prod_idx);
7187 if (jmb_prod_idx != dpr->rx_jmb_prod_idx)
7188 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
7189 dpr->rx_jmb_prod_idx);
7194 tw32_f(HOSTCC_MODE, tp->coal_now);
7200 static inline void tg3_reset_task_schedule(struct tg3 *tp)
7202 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags))
7203 schedule_work(&tp->reset_task);
7206 static inline void tg3_reset_task_cancel(struct tg3 *tp)
7208 cancel_work_sync(&tp->reset_task);
7209 tg3_flag_clear(tp, RESET_TASK_PENDING);
7210 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
7213 static int tg3_poll_msix(struct napi_struct *napi, int budget)
7215 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7216 struct tg3 *tp = tnapi->tp;
7218 struct tg3_hw_status *sblk = tnapi->hw_status;
7221 work_done = tg3_poll_work(tnapi, work_done, budget);
7223 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7226 if (unlikely(work_done >= budget))
7229 /* tp->last_tag is used in tg3_int_reenable() below
7230 * to tell the hw how much work has been processed,
7231 * so we must read it before checking for more work.
7233 tnapi->last_tag = sblk->status_tag;
7234 tnapi->last_irq_tag = tnapi->last_tag;
7237 /* check for RX/TX work to do */
7238 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons &&
7239 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) {
7241 /* This test here is not race free, but will reduce
7242 * the number of interrupts by looping again.
7244 if (tnapi == &tp->napi[1] && tp->rx_refill)
7247 napi_complete(napi);
7248 /* Reenable interrupts. */
7249 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
7251 /* This test here is synchronized by napi_schedule()
7252 * and napi_complete() to close the race condition.
7254 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) {
7255 tw32(HOSTCC_MODE, tp->coalesce_mode |
7256 HOSTCC_MODE_ENABLE |
7267 /* work_done is guaranteed to be less than budget. */
7268 napi_complete(napi);
7269 tg3_reset_task_schedule(tp);
7273 static void tg3_process_error(struct tg3 *tp)
7276 bool real_error = false;
7278 if (tg3_flag(tp, ERROR_PROCESSED))
7281 /* Check Flow Attention register */
7282 val = tr32(HOSTCC_FLOW_ATTN);
7283 if (val & ~HOSTCC_FLOW_ATTN_MBUF_LWM) {
7284 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n");
7288 if (tr32(MSGINT_STATUS) & ~MSGINT_STATUS_MSI_REQ) {
7289 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n");
7293 if (tr32(RDMAC_STATUS) || tr32(WDMAC_STATUS)) {
7294 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n");
7303 tg3_flag_set(tp, ERROR_PROCESSED);
7304 tg3_reset_task_schedule(tp);
7307 static int tg3_poll(struct napi_struct *napi, int budget)
7309 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
7310 struct tg3 *tp = tnapi->tp;
7312 struct tg3_hw_status *sblk = tnapi->hw_status;
7315 if (sblk->status & SD_STATUS_ERROR)
7316 tg3_process_error(tp);
7320 work_done = tg3_poll_work(tnapi, work_done, budget);
7322 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING)))
7325 if (unlikely(work_done >= budget))
7328 if (tg3_flag(tp, TAGGED_STATUS)) {
7329 /* tp->last_tag is used in tg3_int_reenable() below
7330 * to tell the hw how much work has been processed,
7331 * so we must read it before checking for more work.
7333 tnapi->last_tag = sblk->status_tag;
7334 tnapi->last_irq_tag = tnapi->last_tag;
7337 sblk->status &= ~SD_STATUS_UPDATED;
7339 if (likely(!tg3_has_work(tnapi))) {
7340 napi_complete(napi);
7341 tg3_int_reenable(tnapi);
7349 /* work_done is guaranteed to be less than budget. */
7350 napi_complete(napi);
7351 tg3_reset_task_schedule(tp);
7355 static void tg3_napi_disable(struct tg3 *tp)
7359 for (i = tp->irq_cnt - 1; i >= 0; i--)
7360 napi_disable(&tp->napi[i].napi);
7363 static void tg3_napi_enable(struct tg3 *tp)
7367 for (i = 0; i < tp->irq_cnt; i++)
7368 napi_enable(&tp->napi[i].napi);
7371 static void tg3_napi_init(struct tg3 *tp)
7375 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll, 64);
7376 for (i = 1; i < tp->irq_cnt; i++)
7377 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix, 64);
7380 static void tg3_napi_fini(struct tg3 *tp)
7384 for (i = 0; i < tp->irq_cnt; i++)
7385 netif_napi_del(&tp->napi[i].napi);
7388 static inline void tg3_netif_stop(struct tg3 *tp)
7390 tp->dev->trans_start = jiffies; /* prevent tx timeout */
7391 tg3_napi_disable(tp);
7392 netif_carrier_off(tp->dev);
7393 netif_tx_disable(tp->dev);
7396 /* tp->lock must be held */
7397 static inline void tg3_netif_start(struct tg3 *tp)
7401 /* NOTE: unconditional netif_tx_wake_all_queues is only
7402 * appropriate so long as all callers are assured to
7403 * have free tx slots (such as after tg3_init_hw)
7405 netif_tx_wake_all_queues(tp->dev);
7408 netif_carrier_on(tp->dev);
7410 tg3_napi_enable(tp);
7411 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
7412 tg3_enable_ints(tp);
7415 static void tg3_irq_quiesce(struct tg3 *tp)
7419 BUG_ON(tp->irq_sync);
7424 for (i = 0; i < tp->irq_cnt; i++)
7425 synchronize_irq(tp->napi[i].irq_vec);
7428 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7429 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7430 * with as well. Most of the time, this is not necessary except when
7431 * shutting down the device.
7433 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
7435 spin_lock_bh(&tp->lock);
7437 tg3_irq_quiesce(tp);
7440 static inline void tg3_full_unlock(struct tg3 *tp)
7442 spin_unlock_bh(&tp->lock);
7445 /* One-shot MSI handler - Chip automatically disables interrupt
7446 * after sending MSI so driver doesn't have to do it.
7448 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
7450 struct tg3_napi *tnapi = dev_id;
7451 struct tg3 *tp = tnapi->tp;
7453 prefetch(tnapi->hw_status);
7455 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7457 if (likely(!tg3_irq_sync(tp)))
7458 napi_schedule(&tnapi->napi);
7463 /* MSI ISR - No need to check for interrupt sharing and no need to
7464 * flush status block and interrupt mailbox. PCI ordering rules
7465 * guarantee that MSI will arrive after the status block.
7467 static irqreturn_t tg3_msi(int irq, void *dev_id)
7469 struct tg3_napi *tnapi = dev_id;
7470 struct tg3 *tp = tnapi->tp;
7472 prefetch(tnapi->hw_status);
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7476 * Writing any value to intr-mbox-0 clears PCI INTA# and
7477 * chip-internal interrupt pending events.
7478 * Writing non-zero to intr-mbox-0 additional tells the
7479 * NIC to stop sending us irqs, engaging "in-intr-handler"
7482 tw32_mailbox(tnapi->int_mbox, 0x00000001);
7483 if (likely(!tg3_irq_sync(tp)))
7484 napi_schedule(&tnapi->napi);
7486 return IRQ_RETVAL(1);
7489 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
7491 struct tg3_napi *tnapi = dev_id;
7492 struct tg3 *tp = tnapi->tp;
7493 struct tg3_hw_status *sblk = tnapi->hw_status;
7494 unsigned int handled = 1;
7496 /* In INTx mode, it is possible for the interrupt to arrive at
7497 * the CPU before the status block posted prior to the interrupt.
7498 * Reading the PCI State register will confirm whether the
7499 * interrupt is ours and will flush the status block.
7501 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
7502 if (tg3_flag(tp, CHIP_RESETTING) ||
7503 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7510 * Writing any value to intr-mbox-0 clears PCI INTA# and
7511 * chip-internal interrupt pending events.
7512 * Writing non-zero to intr-mbox-0 additional tells the
7513 * NIC to stop sending us irqs, engaging "in-intr-handler"
7516 * Flush the mailbox to de-assert the IRQ immediately to prevent
7517 * spurious interrupts. The flush impacts performance but
7518 * excessive spurious interrupts can be worse in some cases.
7520 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7521 if (tg3_irq_sync(tp))
7523 sblk->status &= ~SD_STATUS_UPDATED;
7524 if (likely(tg3_has_work(tnapi))) {
7525 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7526 napi_schedule(&tnapi->napi);
7528 /* No work, shared interrupt perhaps? re-enable
7529 * interrupts, and flush that PCI write
7531 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
7535 return IRQ_RETVAL(handled);
7538 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
7540 struct tg3_napi *tnapi = dev_id;
7541 struct tg3 *tp = tnapi->tp;
7542 struct tg3_hw_status *sblk = tnapi->hw_status;
7543 unsigned int handled = 1;
7545 /* In INTx mode, it is possible for the interrupt to arrive at
7546 * the CPU before the status block posted prior to the interrupt.
7547 * Reading the PCI State register will confirm whether the
7548 * interrupt is ours and will flush the status block.
7550 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
7551 if (tg3_flag(tp, CHIP_RESETTING) ||
7552 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7559 * writing any value to intr-mbox-0 clears PCI INTA# and
7560 * chip-internal interrupt pending events.
7561 * writing non-zero to intr-mbox-0 additional tells the
7562 * NIC to stop sending us irqs, engaging "in-intr-handler"
7565 * Flush the mailbox to de-assert the IRQ immediately to prevent
7566 * spurious interrupts. The flush impacts performance but
7567 * excessive spurious interrupts can be worse in some cases.
7569 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
7572 * In a shared interrupt configuration, sometimes other devices'
7573 * interrupts will scream. We record the current status tag here
7574 * so that the above check can report that the screaming interrupts
7575 * are unhandled. Eventually they will be silenced.
7577 tnapi->last_irq_tag = sblk->status_tag;
7579 if (tg3_irq_sync(tp))
7582 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
7584 napi_schedule(&tnapi->napi);
7587 return IRQ_RETVAL(handled);
7590 /* ISR for interrupt test */
7591 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
7593 struct tg3_napi *tnapi = dev_id;
7594 struct tg3 *tp = tnapi->tp;
7595 struct tg3_hw_status *sblk = tnapi->hw_status;
7597 if ((sblk->status & SD_STATUS_UPDATED) ||
7598 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
7599 tg3_disable_ints(tp);
7600 return IRQ_RETVAL(1);
7602 return IRQ_RETVAL(0);
7605 #ifdef CONFIG_NET_POLL_CONTROLLER
7606 static void tg3_poll_controller(struct net_device *dev)
7609 struct tg3 *tp = netdev_priv(dev);
7611 if (tg3_irq_sync(tp))
7614 for (i = 0; i < tp->irq_cnt; i++)
7615 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]);
7619 static void tg3_tx_timeout(struct net_device *dev)
7621 struct tg3 *tp = netdev_priv(dev);
7623 if (netif_msg_tx_err(tp)) {
7624 netdev_err(dev, "transmit timed out, resetting\n");
7628 tg3_reset_task_schedule(tp);
7631 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7632 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
7634 u32 base = (u32) mapping & 0xffffffff;
7636 return base + len + 8 < base;
7639 /* Test for TSO DMA buffers that cross into regions which are within MSS bytes
7640 * of any 4GB boundaries: 4G, 8G, etc
7642 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7645 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) {
7646 u32 base = (u32) mapping & 0xffffffff;
7648 return ((base + len + (mss & 0x3fff)) < base);
7653 /* Test for DMA addresses > 40-bit */
7654 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
7657 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7658 if (tg3_flag(tp, 40BIT_DMA_BUG))
7659 return ((u64) mapping + len) > DMA_BIT_MASK(40);
7666 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc *txbd,
7667 dma_addr_t mapping, u32 len, u32 flags,
7670 txbd->addr_hi = ((u64) mapping >> 32);
7671 txbd->addr_lo = ((u64) mapping & 0xffffffff);
7672 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff);
7673 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT);
7676 static bool tg3_tx_frag_set(struct tg3_napi *tnapi, u32 *entry, u32 *budget,
7677 dma_addr_t map, u32 len, u32 flags,
7680 struct tg3 *tp = tnapi->tp;
7683 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8)
7686 if (tg3_4g_overflow_test(map, len))
7689 if (tg3_4g_tso_overflow_test(tp, map, len, mss))
7692 if (tg3_40bit_overflow_test(tp, map, len))
7695 if (tp->dma_limit) {
7696 u32 prvidx = *entry;
7697 u32 tmp_flag = flags & ~TXD_FLAG_END;
7698 while (len > tp->dma_limit && *budget) {
7699 u32 frag_len = tp->dma_limit;
7700 len -= tp->dma_limit;
7702 /* Avoid the 8byte DMA problem */
7704 len += tp->dma_limit / 2;
7705 frag_len = tp->dma_limit / 2;
7708 tnapi->tx_buffers[*entry].fragmented = true;
7710 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7711 frag_len, tmp_flag, mss, vlan);
7714 *entry = NEXT_TX(*entry);
7721 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7722 len, flags, mss, vlan);
7724 *entry = NEXT_TX(*entry);
7727 tnapi->tx_buffers[prvidx].fragmented = false;
7731 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map,
7732 len, flags, mss, vlan);
7733 *entry = NEXT_TX(*entry);
7739 static void tg3_tx_skb_unmap(struct tg3_napi *tnapi, u32 entry, int last)
7742 struct sk_buff *skb;
7743 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry];
7748 pci_unmap_single(tnapi->tp->pdev,
7749 dma_unmap_addr(txb, mapping),
7753 while (txb->fragmented) {
7754 txb->fragmented = false;
7755 entry = NEXT_TX(entry);
7756 txb = &tnapi->tx_buffers[entry];
7759 for (i = 0; i <= last; i++) {
7760 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
7762 entry = NEXT_TX(entry);
7763 txb = &tnapi->tx_buffers[entry];
7765 pci_unmap_page(tnapi->tp->pdev,
7766 dma_unmap_addr(txb, mapping),
7767 skb_frag_size(frag), PCI_DMA_TODEVICE);
7769 while (txb->fragmented) {
7770 txb->fragmented = false;
7771 entry = NEXT_TX(entry);
7772 txb = &tnapi->tx_buffers[entry];
7777 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7778 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
7779 struct sk_buff **pskb,
7780 u32 *entry, u32 *budget,
7781 u32 base_flags, u32 mss, u32 vlan)
7783 struct tg3 *tp = tnapi->tp;
7784 struct sk_buff *new_skb, *skb = *pskb;
7785 dma_addr_t new_addr = 0;
7788 if (tg3_asic_rev(tp) != ASIC_REV_5701)
7789 new_skb = skb_copy(skb, GFP_ATOMIC);
7791 int more_headroom = 4 - ((unsigned long)skb->data & 3);
7793 new_skb = skb_copy_expand(skb,
7794 skb_headroom(skb) + more_headroom,
7795 skb_tailroom(skb), GFP_ATOMIC);
7801 /* New SKB is guaranteed to be linear. */
7802 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
7804 /* Make sure the mapping succeeded */
7805 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
7806 dev_kfree_skb_any(new_skb);
7809 u32 save_entry = *entry;
7811 base_flags |= TXD_FLAG_END;
7813 tnapi->tx_buffers[*entry].skb = new_skb;
7814 dma_unmap_addr_set(&tnapi->tx_buffers[*entry],
7817 if (tg3_tx_frag_set(tnapi, entry, budget, new_addr,
7818 new_skb->len, base_flags,
7820 tg3_tx_skb_unmap(tnapi, save_entry, -1);
7821 dev_kfree_skb_any(new_skb);
7827 dev_kfree_skb_any(skb);
7832 static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
7834 /* Use GSO to workaround all TSO packets that meet HW bug conditions
7835 * indicated in tg3_tx_frag_set()
7837 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi,
7838 struct netdev_queue *txq, struct sk_buff *skb)
7840 struct sk_buff *segs, *nskb;
7841 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
7843 /* Estimate the number of fragments in the worst case */
7844 if (unlikely(tg3_tx_avail(tnapi) <= frag_cnt_est)) {
7845 netif_tx_stop_queue(txq);
7847 /* netif_tx_stop_queue() must be done before checking
7848 * checking tx index in tg3_tx_avail() below, because in
7849 * tg3_tx(), we update tx index before checking for
7850 * netif_tx_queue_stopped().
7853 if (tg3_tx_avail(tnapi) <= frag_cnt_est)
7854 return NETDEV_TX_BUSY;
7856 netif_tx_wake_queue(txq);
7859 segs = skb_gso_segment(skb, tp->dev->features &
7860 ~(NETIF_F_TSO | NETIF_F_TSO6));
7861 if (IS_ERR(segs) || !segs)
7862 goto tg3_tso_bug_end;
7868 tg3_start_xmit(nskb, tp->dev);
7872 dev_kfree_skb_any(skb);
7874 return NETDEV_TX_OK;
7877 /* hard_start_xmit for all devices */
7878 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
7880 struct tg3 *tp = netdev_priv(dev);
7881 u32 len, entry, base_flags, mss, vlan = 0;
7883 int i = -1, would_hit_hwbug;
7885 struct tg3_napi *tnapi;
7886 struct netdev_queue *txq;
7888 struct iphdr *iph = NULL;
7889 struct tcphdr *tcph = NULL;
7890 __sum16 tcp_csum = 0, ip_csum = 0;
7891 __be16 ip_tot_len = 0;
7893 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
7894 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
7895 if (tg3_flag(tp, ENABLE_TSS))
7898 budget = tg3_tx_avail(tnapi);
7900 /* We are running in BH disabled context with netif_tx_lock
7901 * and TX reclaim runs via tp->napi.poll inside of a software
7902 * interrupt. Furthermore, IRQ processing runs lockless so we have
7903 * no IRQ context deadlocks to worry about either. Rejoice!
7905 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) {
7906 if (!netif_tx_queue_stopped(txq)) {
7907 netif_tx_stop_queue(txq);
7909 /* This is a hard error, log it. */
7911 "BUG! Tx Ring full when queue awake!\n");
7913 return NETDEV_TX_BUSY;
7916 entry = tnapi->tx_prod;
7919 mss = skb_shinfo(skb)->gso_size;
7921 u32 tcp_opt_len, hdr_len;
7923 if (skb_cow_head(skb, 0))
7927 tcp_opt_len = tcp_optlen(skb);
7929 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb) - ETH_HLEN;
7931 /* HW/FW can not correctly segment packets that have been
7932 * vlan encapsulated.
7934 if (skb->protocol == htons(ETH_P_8021Q) ||
7935 skb->protocol == htons(ETH_P_8021AD))
7936 return tg3_tso_bug(tp, tnapi, txq, skb);
7938 if (!skb_is_gso_v6(skb)) {
7939 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
7940 tg3_flag(tp, TSO_BUG))
7941 return tg3_tso_bug(tp, tnapi, txq, skb);
7943 ip_csum = iph->check;
7944 ip_tot_len = iph->tot_len;
7946 iph->tot_len = htons(mss + hdr_len);
7949 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
7950 TXD_FLAG_CPU_POST_DMA);
7952 tcph = tcp_hdr(skb);
7953 tcp_csum = tcph->check;
7955 if (tg3_flag(tp, HW_TSO_1) ||
7956 tg3_flag(tp, HW_TSO_2) ||
7957 tg3_flag(tp, HW_TSO_3)) {
7959 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
7961 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr,
7965 if (tg3_flag(tp, HW_TSO_3)) {
7966 mss |= (hdr_len & 0xc) << 12;
7968 base_flags |= 0x00000010;
7969 base_flags |= (hdr_len & 0x3e0) << 5;
7970 } else if (tg3_flag(tp, HW_TSO_2))
7971 mss |= hdr_len << 9;
7972 else if (tg3_flag(tp, HW_TSO_1) ||
7973 tg3_asic_rev(tp) == ASIC_REV_5705) {
7974 if (tcp_opt_len || iph->ihl > 5) {
7977 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7978 mss |= (tsflags << 11);
7981 if (tcp_opt_len || iph->ihl > 5) {
7984 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
7985 base_flags |= tsflags << 12;
7988 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
7989 /* HW/FW can not correctly checksum packets that have been
7990 * vlan encapsulated.
7992 if (skb->protocol == htons(ETH_P_8021Q) ||
7993 skb->protocol == htons(ETH_P_8021AD)) {
7994 if (skb_checksum_help(skb))
7997 base_flags |= TXD_FLAG_TCPUDP_CSUM;
8001 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
8002 !mss && skb->len > VLAN_ETH_FRAME_LEN)
8003 base_flags |= TXD_FLAG_JMB_PKT;
8005 if (vlan_tx_tag_present(skb)) {
8006 base_flags |= TXD_FLAG_VLAN;
8007 vlan = vlan_tx_tag_get(skb);
8010 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) &&
8011 tg3_flag(tp, TX_TSTAMP_EN)) {
8012 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8013 base_flags |= TXD_FLAG_HWTSTAMP;
8016 len = skb_headlen(skb);
8018 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
8019 if (pci_dma_mapping_error(tp->pdev, mapping))
8023 tnapi->tx_buffers[entry].skb = skb;
8024 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
8026 would_hit_hwbug = 0;
8028 if (tg3_flag(tp, 5701_DMA_BUG))
8029 would_hit_hwbug = 1;
8031 if (tg3_tx_frag_set(tnapi, &entry, &budget, mapping, len, base_flags |
8032 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0),
8034 would_hit_hwbug = 1;
8035 } else if (skb_shinfo(skb)->nr_frags > 0) {
8038 if (!tg3_flag(tp, HW_TSO_1) &&
8039 !tg3_flag(tp, HW_TSO_2) &&
8040 !tg3_flag(tp, HW_TSO_3))
8043 /* Now loop through additional data
8044 * fragments, and queue them.
8046 last = skb_shinfo(skb)->nr_frags - 1;
8047 for (i = 0; i <= last; i++) {
8048 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
8050 len = skb_frag_size(frag);
8051 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0,
8052 len, DMA_TO_DEVICE);
8054 tnapi->tx_buffers[entry].skb = NULL;
8055 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
8057 if (dma_mapping_error(&tp->pdev->dev, mapping))
8061 tg3_tx_frag_set(tnapi, &entry, &budget, mapping,
8063 ((i == last) ? TXD_FLAG_END : 0),
8065 would_hit_hwbug = 1;
8071 if (would_hit_hwbug) {
8072 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i);
8075 /* If it's a TSO packet, do GSO instead of
8076 * allocating and copying to a large linear SKB
8079 iph->check = ip_csum;
8080 iph->tot_len = ip_tot_len;
8082 tcph->check = tcp_csum;
8083 return tg3_tso_bug(tp, tnapi, txq, skb);
8086 /* If the workaround fails due to memory/mapping
8087 * failure, silently drop this packet.
8089 entry = tnapi->tx_prod;
8090 budget = tg3_tx_avail(tnapi);
8091 if (tigon3_dma_hwbug_workaround(tnapi, &skb, &entry, &budget,
8092 base_flags, mss, vlan))
8096 skb_tx_timestamp(skb);
8097 netdev_tx_sent_queue(txq, skb->len);
8099 /* Sync BD data before updating mailbox */
8102 /* Packets are ready, update Tx producer idx local and on card. */
8103 tw32_tx_mbox(tnapi->prodmbox, entry);
8105 tnapi->tx_prod = entry;
8106 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
8107 netif_tx_stop_queue(txq);
8109 /* netif_tx_stop_queue() must be done before checking
8110 * checking tx index in tg3_tx_avail() below, because in
8111 * tg3_tx(), we update tx index before checking for
8112 * netif_tx_queue_stopped().
8115 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
8116 netif_tx_wake_queue(txq);
8120 return NETDEV_TX_OK;
8123 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i);
8124 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL;
8126 dev_kfree_skb_any(skb);
8129 return NETDEV_TX_OK;
8132 static void tg3_mac_loopback(struct tg3 *tp, bool enable)
8135 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX |
8136 MAC_MODE_PORT_MODE_MASK);
8138 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK;
8140 if (!tg3_flag(tp, 5705_PLUS))
8141 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
8143 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
8144 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
8146 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
8148 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK;
8150 if (tg3_flag(tp, 5705_PLUS) ||
8151 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) ||
8152 tg3_asic_rev(tp) == ASIC_REV_5700)
8153 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
8156 tw32(MAC_MODE, tp->mac_mode);
8160 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk)
8162 u32 val, bmcr, mac_mode, ptest = 0;
8164 tg3_phy_toggle_apd(tp, false);
8165 tg3_phy_toggle_automdix(tp, false);
8167 if (extlpbk && tg3_phy_set_extloopbk(tp))
8170 bmcr = BMCR_FULLDPLX;
8175 bmcr |= BMCR_SPEED100;
8179 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
8181 bmcr |= BMCR_SPEED100;
8184 bmcr |= BMCR_SPEED1000;
8189 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
8190 tg3_readphy(tp, MII_CTRL1000, &val);
8191 val |= CTL1000_AS_MASTER |
8192 CTL1000_ENABLE_MASTER;
8193 tg3_writephy(tp, MII_CTRL1000, val);
8195 ptest = MII_TG3_FET_PTEST_TRIM_SEL |
8196 MII_TG3_FET_PTEST_TRIM_2;
8197 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest);
8200 bmcr |= BMCR_LOOPBACK;
8202 tg3_writephy(tp, MII_BMCR, bmcr);
8204 /* The write needs to be flushed for the FETs */
8205 if (tp->phy_flags & TG3_PHYFLG_IS_FET)
8206 tg3_readphy(tp, MII_BMCR, &bmcr);
8210 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
8211 tg3_asic_rev(tp) == ASIC_REV_5785) {
8212 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest |
8213 MII_TG3_FET_PTEST_FRC_TX_LINK |
8214 MII_TG3_FET_PTEST_FRC_TX_LOCK);
8216 /* The write needs to be flushed for the AC131 */
8217 tg3_readphy(tp, MII_TG3_FET_PTEST, &val);
8220 /* Reset to prevent losing 1st rx packet intermittently */
8221 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
8222 tg3_flag(tp, 5780_CLASS)) {
8223 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8225 tw32_f(MAC_RX_MODE, tp->rx_mode);
8228 mac_mode = tp->mac_mode &
8229 ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
8230 if (speed == SPEED_1000)
8231 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8233 mac_mode |= MAC_MODE_PORT_MODE_MII;
8235 if (tg3_asic_rev(tp) == ASIC_REV_5700) {
8236 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK;
8238 if (masked_phy_id == TG3_PHY_ID_BCM5401)
8239 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8240 else if (masked_phy_id == TG3_PHY_ID_BCM5411)
8241 mac_mode |= MAC_MODE_LINK_POLARITY;
8243 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8244 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8247 tw32(MAC_MODE, mac_mode);
8253 static void tg3_set_loopback(struct net_device *dev, netdev_features_t features)
8255 struct tg3 *tp = netdev_priv(dev);
8257 if (features & NETIF_F_LOOPBACK) {
8258 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)
8261 spin_lock_bh(&tp->lock);
8262 tg3_mac_loopback(tp, true);
8263 netif_carrier_on(tp->dev);
8264 spin_unlock_bh(&tp->lock);
8265 netdev_info(dev, "Internal MAC loopback mode enabled.\n");
8267 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
8270 spin_lock_bh(&tp->lock);
8271 tg3_mac_loopback(tp, false);
8272 /* Force link status check */
8273 tg3_setup_phy(tp, true);
8274 spin_unlock_bh(&tp->lock);
8275 netdev_info(dev, "Internal MAC loopback mode disabled.\n");
8279 static netdev_features_t tg3_fix_features(struct net_device *dev,
8280 netdev_features_t features)
8282 struct tg3 *tp = netdev_priv(dev);
8284 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS))
8285 features &= ~NETIF_F_ALL_TSO;
8290 static int tg3_set_features(struct net_device *dev, netdev_features_t features)
8292 netdev_features_t changed = dev->features ^ features;
8294 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev))
8295 tg3_set_loopback(dev, features);
8300 static void tg3_rx_prodring_free(struct tg3 *tp,
8301 struct tg3_rx_prodring_set *tpr)
8305 if (tpr != &tp->napi[0].prodring) {
8306 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
8307 i = (i + 1) & tp->rx_std_ring_mask)
8308 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8311 if (tg3_flag(tp, JUMBO_CAPABLE)) {
8312 for (i = tpr->rx_jmb_cons_idx;
8313 i != tpr->rx_jmb_prod_idx;
8314 i = (i + 1) & tp->rx_jmb_ring_mask) {
8315 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8323 for (i = 0; i <= tp->rx_std_ring_mask; i++)
8324 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i],
8327 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8328 for (i = 0; i <= tp->rx_jmb_ring_mask; i++)
8329 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i],
8334 /* Initialize rx rings for packet processing.
8336 * The chip has been shut down and the driver detached from
8337 * the networking, so no interrupts or new tx packets will
8338 * end up in the driver. tp->{tx,}lock are held and thus
8341 static int tg3_rx_prodring_alloc(struct tg3 *tp,
8342 struct tg3_rx_prodring_set *tpr)
8344 u32 i, rx_pkt_dma_sz;
8346 tpr->rx_std_cons_idx = 0;
8347 tpr->rx_std_prod_idx = 0;
8348 tpr->rx_jmb_cons_idx = 0;
8349 tpr->rx_jmb_prod_idx = 0;
8351 if (tpr != &tp->napi[0].prodring) {
8352 memset(&tpr->rx_std_buffers[0], 0,
8353 TG3_RX_STD_BUFF_RING_SIZE(tp));
8354 if (tpr->rx_jmb_buffers)
8355 memset(&tpr->rx_jmb_buffers[0], 0,
8356 TG3_RX_JMB_BUFF_RING_SIZE(tp));
8360 /* Zero out all descriptors. */
8361 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp));
8363 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
8364 if (tg3_flag(tp, 5780_CLASS) &&
8365 tp->dev->mtu > ETH_DATA_LEN)
8366 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
8367 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
8369 /* Initialize invariants of the rings, we only set this
8370 * stuff once. This works because the card does not
8371 * write into the rx buffer posting rings.
8373 for (i = 0; i <= tp->rx_std_ring_mask; i++) {
8374 struct tg3_rx_buffer_desc *rxd;
8376 rxd = &tpr->rx_std[i];
8377 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
8378 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
8379 rxd->opaque = (RXD_OPAQUE_RING_STD |
8380 (i << RXD_OPAQUE_INDEX_SHIFT));
8383 /* Now allocate fresh SKBs for each rx ring. */
8384 for (i = 0; i < tp->rx_pending; i++) {
8385 unsigned int frag_size;
8387 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i,
8389 netdev_warn(tp->dev,
8390 "Using a smaller RX standard ring. Only "
8391 "%d out of %d buffers were allocated "
8392 "successfully\n", i, tp->rx_pending);
8400 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
8403 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp));
8405 if (!tg3_flag(tp, JUMBO_RING_ENABLE))
8408 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) {
8409 struct tg3_rx_buffer_desc *rxd;
8411 rxd = &tpr->rx_jmb[i].std;
8412 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
8413 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
8415 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
8416 (i << RXD_OPAQUE_INDEX_SHIFT));
8419 for (i = 0; i < tp->rx_jumbo_pending; i++) {
8420 unsigned int frag_size;
8422 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i,
8424 netdev_warn(tp->dev,
8425 "Using a smaller RX jumbo ring. Only %d "
8426 "out of %d buffers were allocated "
8427 "successfully\n", i, tp->rx_jumbo_pending);
8430 tp->rx_jumbo_pending = i;
8439 tg3_rx_prodring_free(tp, tpr);
8443 static void tg3_rx_prodring_fini(struct tg3 *tp,
8444 struct tg3_rx_prodring_set *tpr)
8446 kfree(tpr->rx_std_buffers);
8447 tpr->rx_std_buffers = NULL;
8448 kfree(tpr->rx_jmb_buffers);
8449 tpr->rx_jmb_buffers = NULL;
8451 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp),
8452 tpr->rx_std, tpr->rx_std_mapping);
8456 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp),
8457 tpr->rx_jmb, tpr->rx_jmb_mapping);
8462 static int tg3_rx_prodring_init(struct tg3 *tp,
8463 struct tg3_rx_prodring_set *tpr)
8465 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp),
8467 if (!tpr->rx_std_buffers)
8470 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev,
8471 TG3_RX_STD_RING_BYTES(tp),
8472 &tpr->rx_std_mapping,
8477 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) {
8478 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp),
8480 if (!tpr->rx_jmb_buffers)
8483 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev,
8484 TG3_RX_JMB_RING_BYTES(tp),
8485 &tpr->rx_jmb_mapping,
8494 tg3_rx_prodring_fini(tp, tpr);
8498 /* Free up pending packets in all rx/tx rings.
8500 * The chip has been shut down and the driver detached from
8501 * the networking, so no interrupts or new tx packets will
8502 * end up in the driver. tp->{tx,}lock is not held and we are not
8503 * in an interrupt context and thus may sleep.
8505 static void tg3_free_rings(struct tg3 *tp)
8509 for (j = 0; j < tp->irq_cnt; j++) {
8510 struct tg3_napi *tnapi = &tp->napi[j];
8512 tg3_rx_prodring_free(tp, &tnapi->prodring);
8514 if (!tnapi->tx_buffers)
8517 for (i = 0; i < TG3_TX_RING_SIZE; i++) {
8518 struct sk_buff *skb = tnapi->tx_buffers[i].skb;
8523 tg3_tx_skb_unmap(tnapi, i,
8524 skb_shinfo(skb)->nr_frags - 1);
8526 dev_kfree_skb_any(skb);
8528 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j));
8532 /* Initialize tx/rx rings for packet processing.
8534 * The chip has been shut down and the driver detached from
8535 * the networking, so no interrupts or new tx packets will
8536 * end up in the driver. tp->{tx,}lock are held and thus
8539 static int tg3_init_rings(struct tg3 *tp)
8543 /* Free up all the SKBs. */
8546 for (i = 0; i < tp->irq_cnt; i++) {
8547 struct tg3_napi *tnapi = &tp->napi[i];
8549 tnapi->last_tag = 0;
8550 tnapi->last_irq_tag = 0;
8551 tnapi->hw_status->status = 0;
8552 tnapi->hw_status->status_tag = 0;
8553 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8558 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
8560 tnapi->rx_rcb_ptr = 0;
8562 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
8564 if (tg3_rx_prodring_alloc(tp, &tnapi->prodring)) {
8573 static void tg3_mem_tx_release(struct tg3 *tp)
8577 for (i = 0; i < tp->irq_max; i++) {
8578 struct tg3_napi *tnapi = &tp->napi[i];
8580 if (tnapi->tx_ring) {
8581 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES,
8582 tnapi->tx_ring, tnapi->tx_desc_mapping);
8583 tnapi->tx_ring = NULL;
8586 kfree(tnapi->tx_buffers);
8587 tnapi->tx_buffers = NULL;
8591 static int tg3_mem_tx_acquire(struct tg3 *tp)
8594 struct tg3_napi *tnapi = &tp->napi[0];
8596 /* If multivector TSS is enabled, vector 0 does not handle
8597 * tx interrupts. Don't allocate any resources for it.
8599 if (tg3_flag(tp, ENABLE_TSS))
8602 for (i = 0; i < tp->txq_cnt; i++, tnapi++) {
8603 tnapi->tx_buffers = kzalloc(sizeof(struct tg3_tx_ring_info) *
8604 TG3_TX_RING_SIZE, GFP_KERNEL);
8605 if (!tnapi->tx_buffers)
8608 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev,
8610 &tnapi->tx_desc_mapping,
8612 if (!tnapi->tx_ring)
8619 tg3_mem_tx_release(tp);
8623 static void tg3_mem_rx_release(struct tg3 *tp)
8627 for (i = 0; i < tp->irq_max; i++) {
8628 struct tg3_napi *tnapi = &tp->napi[i];
8630 tg3_rx_prodring_fini(tp, &tnapi->prodring);
8635 dma_free_coherent(&tp->pdev->dev,
8636 TG3_RX_RCB_RING_BYTES(tp),
8638 tnapi->rx_rcb_mapping);
8639 tnapi->rx_rcb = NULL;
8643 static int tg3_mem_rx_acquire(struct tg3 *tp)
8645 unsigned int i, limit;
8647 limit = tp->rxq_cnt;
8649 /* If RSS is enabled, we need a (dummy) producer ring
8650 * set on vector zero. This is the true hw prodring.
8652 if (tg3_flag(tp, ENABLE_RSS))
8655 for (i = 0; i < limit; i++) {
8656 struct tg3_napi *tnapi = &tp->napi[i];
8658 if (tg3_rx_prodring_init(tp, &tnapi->prodring))
8661 /* If multivector RSS is enabled, vector 0
8662 * does not handle rx or tx interrupts.
8663 * Don't allocate any resources for it.
8665 if (!i && tg3_flag(tp, ENABLE_RSS))
8668 tnapi->rx_rcb = dma_zalloc_coherent(&tp->pdev->dev,
8669 TG3_RX_RCB_RING_BYTES(tp),
8670 &tnapi->rx_rcb_mapping,
8679 tg3_mem_rx_release(tp);
8684 * Must not be invoked with interrupt sources disabled and
8685 * the hardware shutdown down.
8687 static void tg3_free_consistent(struct tg3 *tp)
8691 for (i = 0; i < tp->irq_cnt; i++) {
8692 struct tg3_napi *tnapi = &tp->napi[i];
8694 if (tnapi->hw_status) {
8695 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE,
8697 tnapi->status_mapping);
8698 tnapi->hw_status = NULL;
8702 tg3_mem_rx_release(tp);
8703 tg3_mem_tx_release(tp);
8706 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats),
8707 tp->hw_stats, tp->stats_mapping);
8708 tp->hw_stats = NULL;
8713 * Must not be invoked with interrupt sources disabled and
8714 * the hardware shutdown down. Can sleep.
8716 static int tg3_alloc_consistent(struct tg3 *tp)
8720 tp->hw_stats = dma_zalloc_coherent(&tp->pdev->dev,
8721 sizeof(struct tg3_hw_stats),
8722 &tp->stats_mapping, GFP_KERNEL);
8726 for (i = 0; i < tp->irq_cnt; i++) {
8727 struct tg3_napi *tnapi = &tp->napi[i];
8728 struct tg3_hw_status *sblk;
8730 tnapi->hw_status = dma_zalloc_coherent(&tp->pdev->dev,
8732 &tnapi->status_mapping,
8734 if (!tnapi->hw_status)
8737 sblk = tnapi->hw_status;
8739 if (tg3_flag(tp, ENABLE_RSS)) {
8740 u16 *prodptr = NULL;
8743 * When RSS is enabled, the status block format changes
8744 * slightly. The "rx_jumbo_consumer", "reserved",
8745 * and "rx_mini_consumer" members get mapped to the
8746 * other three rx return ring producer indexes.
8750 prodptr = &sblk->idx[0].rx_producer;
8753 prodptr = &sblk->rx_jumbo_consumer;
8756 prodptr = &sblk->reserved;
8759 prodptr = &sblk->rx_mini_consumer;
8762 tnapi->rx_rcb_prod_idx = prodptr;
8764 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
8768 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp))
8774 tg3_free_consistent(tp);
8778 #define MAX_WAIT_CNT 1000
8780 /* To stop a block, clear the enable bit and poll till it
8781 * clears. tp->lock is held.
8783 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent)
8788 if (tg3_flag(tp, 5705_PLUS)) {
8795 /* We can't enable/disable these bits of the
8796 * 5705/5750, just say success.
8809 for (i = 0; i < MAX_WAIT_CNT; i++) {
8810 if (pci_channel_offline(tp->pdev)) {
8811 dev_err(&tp->pdev->dev,
8812 "tg3_stop_block device offline, "
8813 "ofs=%lx enable_bit=%x\n",
8820 if ((val & enable_bit) == 0)
8824 if (i == MAX_WAIT_CNT && !silent) {
8825 dev_err(&tp->pdev->dev,
8826 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8834 /* tp->lock is held. */
8835 static int tg3_abort_hw(struct tg3 *tp, bool silent)
8839 tg3_disable_ints(tp);
8841 if (pci_channel_offline(tp->pdev)) {
8842 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE);
8843 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8848 tp->rx_mode &= ~RX_MODE_ENABLE;
8849 tw32_f(MAC_RX_MODE, tp->rx_mode);
8852 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
8853 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
8854 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
8855 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
8856 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
8857 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
8859 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
8860 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
8861 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
8862 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
8863 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
8864 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
8865 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
8867 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
8868 tw32_f(MAC_MODE, tp->mac_mode);
8871 tp->tx_mode &= ~TX_MODE_ENABLE;
8872 tw32_f(MAC_TX_MODE, tp->tx_mode);
8874 for (i = 0; i < MAX_WAIT_CNT; i++) {
8876 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
8879 if (i >= MAX_WAIT_CNT) {
8880 dev_err(&tp->pdev->dev,
8881 "%s timed out, TX_MODE_ENABLE will not clear "
8882 "MAC_TX_MODE=%08x\n", __func__, tr32(MAC_TX_MODE));
8886 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
8887 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
8888 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
8890 tw32(FTQ_RESET, 0xffffffff);
8891 tw32(FTQ_RESET, 0x00000000);
8893 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
8894 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
8897 for (i = 0; i < tp->irq_cnt; i++) {
8898 struct tg3_napi *tnapi = &tp->napi[i];
8899 if (tnapi->hw_status)
8900 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
8906 /* Save PCI command register before chip reset */
8907 static void tg3_save_pci_state(struct tg3 *tp)
8909 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
8912 /* Restore PCI state after chip reset */
8913 static void tg3_restore_pci_state(struct tg3 *tp)
8917 /* Re-enable indirect register accesses. */
8918 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
8919 tp->misc_host_ctrl);
8921 /* Set MAX PCI retry to zero. */
8922 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
8923 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
8924 tg3_flag(tp, PCIX_MODE))
8925 val |= PCISTATE_RETRY_SAME_DMA;
8926 /* Allow reads and writes to the APE register and memory space. */
8927 if (tg3_flag(tp, ENABLE_APE))
8928 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
8929 PCISTATE_ALLOW_APE_SHMEM_WR |
8930 PCISTATE_ALLOW_APE_PSPACE_WR;
8931 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
8933 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
8935 if (!tg3_flag(tp, PCI_EXPRESS)) {
8936 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
8937 tp->pci_cacheline_sz);
8938 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
8942 /* Make sure PCI-X relaxed ordering bit is clear. */
8943 if (tg3_flag(tp, PCIX_MODE)) {
8946 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8948 pcix_cmd &= ~PCI_X_CMD_ERO;
8949 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8953 if (tg3_flag(tp, 5780_CLASS)) {
8955 /* Chip reset on 5780 will reset MSI enable bit,
8956 * so need to restore it.
8958 if (tg3_flag(tp, USING_MSI)) {
8961 pci_read_config_word(tp->pdev,
8962 tp->msi_cap + PCI_MSI_FLAGS,
8964 pci_write_config_word(tp->pdev,
8965 tp->msi_cap + PCI_MSI_FLAGS,
8966 ctrl | PCI_MSI_FLAGS_ENABLE);
8967 val = tr32(MSGINT_MODE);
8968 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
8973 static void tg3_override_clk(struct tg3 *tp)
8977 switch (tg3_asic_rev(tp)) {
8979 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
8980 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE, val |
8981 TG3_CPMU_MAC_ORIDE_ENABLE);
8986 tw32(TG3_CPMU_CLCK_ORIDE, CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
8994 static void tg3_restore_clk(struct tg3 *tp)
8998 switch (tg3_asic_rev(tp)) {
9000 val = tr32(TG3_CPMU_CLCK_ORIDE_ENABLE);
9001 tw32(TG3_CPMU_CLCK_ORIDE_ENABLE,
9002 val & ~TG3_CPMU_MAC_ORIDE_ENABLE);
9007 val = tr32(TG3_CPMU_CLCK_ORIDE);
9008 tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
9016 /* tp->lock is held. */
9017 static int tg3_chip_reset(struct tg3 *tp)
9020 void (*write_op)(struct tg3 *, u32, u32);
9023 if (!pci_device_is_present(tp->pdev))
9028 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
9030 /* No matching tg3_nvram_unlock() after this because
9031 * chip reset below will undo the nvram lock.
9033 tp->nvram_lock_cnt = 0;
9035 /* GRC_MISC_CFG core clock reset will clear the memory
9036 * enable bit in PCI register 4 and the MSI enable bit
9037 * on some chips, so we save relevant registers here.
9039 tg3_save_pci_state(tp);
9041 if (tg3_asic_rev(tp) == ASIC_REV_5752 ||
9042 tg3_flag(tp, 5755_PLUS))
9043 tw32(GRC_FASTBOOT_PC, 0);
9046 * We must avoid the readl() that normally takes place.
9047 * It locks machines, causes machine checks, and other
9048 * fun things. So, temporarily disable the 5701
9049 * hardware workaround, while we do the reset.
9051 write_op = tp->write32;
9052 if (write_op == tg3_write_flush_reg32)
9053 tp->write32 = tg3_write32;
9055 /* Prevent the irq handler from reading or writing PCI registers
9056 * during chip reset when the memory enable bit in the PCI command
9057 * register may be cleared. The chip does not generate interrupt
9058 * at this time, but the irq handler may still be called due to irq
9059 * sharing or irqpoll.
9061 tg3_flag_set(tp, CHIP_RESETTING);
9062 for (i = 0; i < tp->irq_cnt; i++) {
9063 struct tg3_napi *tnapi = &tp->napi[i];
9064 if (tnapi->hw_status) {
9065 tnapi->hw_status->status = 0;
9066 tnapi->hw_status->status_tag = 0;
9068 tnapi->last_tag = 0;
9069 tnapi->last_irq_tag = 0;
9073 for (i = 0; i < tp->irq_cnt; i++)
9074 synchronize_irq(tp->napi[i].irq_vec);
9076 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9077 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9078 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9082 val = GRC_MISC_CFG_CORECLK_RESET;
9084 if (tg3_flag(tp, PCI_EXPRESS)) {
9085 /* Force PCIe 1.0a mode */
9086 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
9087 !tg3_flag(tp, 57765_PLUS) &&
9088 tr32(TG3_PCIE_PHY_TSTCTL) ==
9089 (TG3_PCIE_PHY_TSTCTL_PCIE10 | TG3_PCIE_PHY_TSTCTL_PSCRAM))
9090 tw32(TG3_PCIE_PHY_TSTCTL, TG3_PCIE_PHY_TSTCTL_PSCRAM);
9092 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) {
9093 tw32(GRC_MISC_CFG, (1 << 29));
9098 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
9099 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
9100 tw32(GRC_VCPU_EXT_CTRL,
9101 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
9104 /* Set the clock to the highest frequency to avoid timeouts. With link
9105 * aware mode, the clock speed could be slow and bootcode does not
9106 * complete within the expected time. Override the clock to allow the
9107 * bootcode to finish sooner and then restore it.
9109 tg3_override_clk(tp);
9111 /* Manage gphy power for all CPMU absent PCIe devices. */
9112 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT))
9113 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
9115 tw32(GRC_MISC_CFG, val);
9117 /* restore 5701 hardware bug workaround write method */
9118 tp->write32 = write_op;
9120 /* Unfortunately, we have to delay before the PCI read back.
9121 * Some 575X chips even will not respond to a PCI cfg access
9122 * when the reset command is given to the chip.
9124 * How do these hardware designers expect things to work
9125 * properly if the PCI write is posted for a long period
9126 * of time? It is always necessary to have some method by
9127 * which a register read back can occur to push the write
9128 * out which does the reset.
9130 * For most tg3 variants the trick below was working.
9135 /* Flush PCI posted writes. The normal MMIO registers
9136 * are inaccessible at this time so this is the only
9137 * way to make this reliably (actually, this is no longer
9138 * the case, see above). I tried to use indirect
9139 * register read/write but this upset some 5701 variants.
9141 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
9145 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) {
9148 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) {
9152 /* Wait for link training to complete. */
9153 for (j = 0; j < 5000; j++)
9156 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
9157 pci_write_config_dword(tp->pdev, 0xc4,
9158 cfg_val | (1 << 15));
9161 /* Clear the "no snoop" and "relaxed ordering" bits. */
9162 val16 = PCI_EXP_DEVCTL_RELAX_EN | PCI_EXP_DEVCTL_NOSNOOP_EN;
9164 * Older PCIe devices only support the 128 byte
9165 * MPS setting. Enforce the restriction.
9167 if (!tg3_flag(tp, CPMU_PRESENT))
9168 val16 |= PCI_EXP_DEVCTL_PAYLOAD;
9169 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16);
9171 /* Clear error status */
9172 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA,
9173 PCI_EXP_DEVSTA_CED |
9174 PCI_EXP_DEVSTA_NFED |
9175 PCI_EXP_DEVSTA_FED |
9176 PCI_EXP_DEVSTA_URD);
9179 tg3_restore_pci_state(tp);
9181 tg3_flag_clear(tp, CHIP_RESETTING);
9182 tg3_flag_clear(tp, ERROR_PROCESSED);
9185 if (tg3_flag(tp, 5780_CLASS))
9186 val = tr32(MEMARB_MODE);
9187 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9189 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) {
9191 tw32(0x5000, 0x400);
9194 if (tg3_flag(tp, IS_SSB_CORE)) {
9196 * BCM4785: In order to avoid repercussions from using
9197 * potentially defective internal ROM, stop the Rx RISC CPU,
9198 * which is not required.
9201 tg3_halt_cpu(tp, RX_CPU_BASE);
9204 err = tg3_poll_fw(tp);
9208 tw32(GRC_MODE, tp->grc_mode);
9210 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) {
9213 tw32(0xc4, val | (1 << 15));
9216 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
9217 tg3_asic_rev(tp) == ASIC_REV_5705) {
9218 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
9219 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0)
9220 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
9221 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9224 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
9225 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
9227 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
9228 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
9233 tw32_f(MAC_MODE, val);
9236 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
9240 if (tg3_flag(tp, PCI_EXPRESS) &&
9241 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
9242 tg3_asic_rev(tp) != ASIC_REV_5785 &&
9243 !tg3_flag(tp, 57765_PLUS)) {
9246 tw32(0x7c00, val | (1 << 25));
9249 tg3_restore_clk(tp);
9251 /* Reprobe ASF enable state. */
9252 tg3_flag_clear(tp, ENABLE_ASF);
9253 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
9254 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
9256 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE);
9257 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9258 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9261 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9262 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9263 tg3_flag_set(tp, ENABLE_ASF);
9264 tp->last_event_jiffies = jiffies;
9265 if (tg3_flag(tp, 5750_PLUS))
9266 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
9268 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg);
9269 if (nic_cfg & NIC_SRAM_1G_ON_VAUX_OK)
9270 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
9271 if (nic_cfg & NIC_SRAM_LNK_FLAP_AVOID)
9272 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
9279 static void tg3_get_nstats(struct tg3 *, struct rtnl_link_stats64 *);
9280 static void tg3_get_estats(struct tg3 *, struct tg3_ethtool_stats *);
9281 static void __tg3_set_rx_mode(struct net_device *);
9283 /* tp->lock is held. */
9284 static int tg3_halt(struct tg3 *tp, int kind, bool silent)
9290 tg3_write_sig_pre_reset(tp, kind);
9292 tg3_abort_hw(tp, silent);
9293 err = tg3_chip_reset(tp);
9295 __tg3_set_mac_addr(tp, false);
9297 tg3_write_sig_legacy(tp, kind);
9298 tg3_write_sig_post_reset(tp, kind);
9301 /* Save the stats across chip resets... */
9302 tg3_get_nstats(tp, &tp->net_stats_prev);
9303 tg3_get_estats(tp, &tp->estats_prev);
9305 /* And make sure the next sample is new data */
9306 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
9312 static int tg3_set_mac_addr(struct net_device *dev, void *p)
9314 struct tg3 *tp = netdev_priv(dev);
9315 struct sockaddr *addr = p;
9317 bool skip_mac_1 = false;
9319 if (!is_valid_ether_addr(addr->sa_data))
9320 return -EADDRNOTAVAIL;
9322 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
9324 if (!netif_running(dev))
9327 if (tg3_flag(tp, ENABLE_ASF)) {
9328 u32 addr0_high, addr0_low, addr1_high, addr1_low;
9330 addr0_high = tr32(MAC_ADDR_0_HIGH);
9331 addr0_low = tr32(MAC_ADDR_0_LOW);
9332 addr1_high = tr32(MAC_ADDR_1_HIGH);
9333 addr1_low = tr32(MAC_ADDR_1_LOW);
9335 /* Skip MAC addr 1 if ASF is using it. */
9336 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
9337 !(addr1_high == 0 && addr1_low == 0))
9340 spin_lock_bh(&tp->lock);
9341 __tg3_set_mac_addr(tp, skip_mac_1);
9342 __tg3_set_rx_mode(dev);
9343 spin_unlock_bh(&tp->lock);
9348 /* tp->lock is held. */
9349 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
9350 dma_addr_t mapping, u32 maxlen_flags,
9354 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
9355 ((u64) mapping >> 32));
9357 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
9358 ((u64) mapping & 0xffffffff));
9360 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
9363 if (!tg3_flag(tp, 5705_PLUS))
9365 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
9370 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9374 if (!tg3_flag(tp, ENABLE_TSS)) {
9375 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
9376 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
9377 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
9379 tw32(HOSTCC_TXCOL_TICKS, 0);
9380 tw32(HOSTCC_TXMAX_FRAMES, 0);
9381 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
9383 for (; i < tp->txq_cnt; i++) {
9386 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
9387 tw32(reg, ec->tx_coalesce_usecs);
9388 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
9389 tw32(reg, ec->tx_max_coalesced_frames);
9390 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
9391 tw32(reg, ec->tx_max_coalesced_frames_irq);
9395 for (; i < tp->irq_max - 1; i++) {
9396 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
9397 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
9398 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9402 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec)
9405 u32 limit = tp->rxq_cnt;
9407 if (!tg3_flag(tp, ENABLE_RSS)) {
9408 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
9409 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
9410 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
9413 tw32(HOSTCC_RXCOL_TICKS, 0);
9414 tw32(HOSTCC_RXMAX_FRAMES, 0);
9415 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
9418 for (; i < limit; i++) {
9421 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
9422 tw32(reg, ec->rx_coalesce_usecs);
9423 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
9424 tw32(reg, ec->rx_max_coalesced_frames);
9425 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
9426 tw32(reg, ec->rx_max_coalesced_frames_irq);
9429 for (; i < tp->irq_max - 1; i++) {
9430 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
9431 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
9432 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
9436 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
9438 tg3_coal_tx_init(tp, ec);
9439 tg3_coal_rx_init(tp, ec);
9441 if (!tg3_flag(tp, 5705_PLUS)) {
9442 u32 val = ec->stats_block_coalesce_usecs;
9444 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
9445 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
9450 tw32(HOSTCC_STAT_COAL_TICKS, val);
9454 /* tp->lock is held. */
9455 static void tg3_tx_rcbs_disable(struct tg3 *tp)
9459 /* Disable all transmit rings but the first. */
9460 if (!tg3_flag(tp, 5705_PLUS))
9461 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
9462 else if (tg3_flag(tp, 5717_PLUS))
9463 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4;
9464 else if (tg3_flag(tp, 57765_CLASS) ||
9465 tg3_asic_rev(tp) == ASIC_REV_5762)
9466 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
9468 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9470 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
9471 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
9472 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
9473 BDINFO_FLAGS_DISABLED);
9476 /* tp->lock is held. */
9477 static void tg3_tx_rcbs_init(struct tg3 *tp)
9480 u32 txrcb = NIC_SRAM_SEND_RCB;
9482 if (tg3_flag(tp, ENABLE_TSS))
9485 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) {
9486 struct tg3_napi *tnapi = &tp->napi[i];
9488 if (!tnapi->tx_ring)
9491 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
9492 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
9493 NIC_SRAM_TX_BUFFER_DESC);
9497 /* tp->lock is held. */
9498 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp)
9502 /* Disable all receive return rings but the first. */
9503 if (tg3_flag(tp, 5717_PLUS))
9504 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
9505 else if (!tg3_flag(tp, 5705_PLUS))
9506 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
9507 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9508 tg3_asic_rev(tp) == ASIC_REV_5762 ||
9509 tg3_flag(tp, 57765_CLASS))
9510 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
9512 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9514 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
9515 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
9516 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
9517 BDINFO_FLAGS_DISABLED);
9520 /* tp->lock is held. */
9521 static void tg3_rx_ret_rcbs_init(struct tg3 *tp)
9524 u32 rxrcb = NIC_SRAM_RCV_RET_RCB;
9526 if (tg3_flag(tp, ENABLE_RSS))
9529 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) {
9530 struct tg3_napi *tnapi = &tp->napi[i];
9535 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
9536 (tp->rx_ret_ring_mask + 1) <<
9537 BDINFO_FLAGS_MAXLEN_SHIFT, 0);
9541 /* tp->lock is held. */
9542 static void tg3_rings_reset(struct tg3 *tp)
9546 struct tg3_napi *tnapi = &tp->napi[0];
9548 tg3_tx_rcbs_disable(tp);
9550 tg3_rx_ret_rcbs_disable(tp);
9552 /* Disable interrupts */
9553 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
9554 tp->napi[0].chk_msi_cnt = 0;
9555 tp->napi[0].last_rx_cons = 0;
9556 tp->napi[0].last_tx_cons = 0;
9558 /* Zero mailbox registers. */
9559 if (tg3_flag(tp, SUPPORT_MSIX)) {
9560 for (i = 1; i < tp->irq_max; i++) {
9561 tp->napi[i].tx_prod = 0;
9562 tp->napi[i].tx_cons = 0;
9563 if (tg3_flag(tp, ENABLE_TSS))
9564 tw32_mailbox(tp->napi[i].prodmbox, 0);
9565 tw32_rx_mbox(tp->napi[i].consmbox, 0);
9566 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
9567 tp->napi[i].chk_msi_cnt = 0;
9568 tp->napi[i].last_rx_cons = 0;
9569 tp->napi[i].last_tx_cons = 0;
9571 if (!tg3_flag(tp, ENABLE_TSS))
9572 tw32_mailbox(tp->napi[0].prodmbox, 0);
9574 tp->napi[0].tx_prod = 0;
9575 tp->napi[0].tx_cons = 0;
9576 tw32_mailbox(tp->napi[0].prodmbox, 0);
9577 tw32_rx_mbox(tp->napi[0].consmbox, 0);
9580 /* Make sure the NIC-based send BD rings are disabled. */
9581 if (!tg3_flag(tp, 5705_PLUS)) {
9582 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
9583 for (i = 0; i < 16; i++)
9584 tw32_tx_mbox(mbox + i * 8, 0);
9587 /* Clear status block in ram. */
9588 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9590 /* Set status block DMA address */
9591 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
9592 ((u64) tnapi->status_mapping >> 32));
9593 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
9594 ((u64) tnapi->status_mapping & 0xffffffff));
9596 stblk = HOSTCC_STATBLCK_RING1;
9598 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
9599 u64 mapping = (u64)tnapi->status_mapping;
9600 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
9601 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
9604 /* Clear status block in ram. */
9605 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
9608 tg3_tx_rcbs_init(tp);
9609 tg3_rx_ret_rcbs_init(tp);
9612 static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
9614 u32 val, bdcache_maxcnt, host_rep_thresh, nic_rep_thresh;
9616 if (!tg3_flag(tp, 5750_PLUS) ||
9617 tg3_flag(tp, 5780_CLASS) ||
9618 tg3_asic_rev(tp) == ASIC_REV_5750 ||
9619 tg3_asic_rev(tp) == ASIC_REV_5752 ||
9620 tg3_flag(tp, 57765_PLUS))
9621 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5700;
9622 else if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
9623 tg3_asic_rev(tp) == ASIC_REV_5787)
9624 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5755;
9626 bdcache_maxcnt = TG3_SRAM_RX_STD_BDCACHE_SIZE_5906;
9628 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post);
9629 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1);
9631 val = min(nic_rep_thresh, host_rep_thresh);
9632 tw32(RCVBDI_STD_THRESH, val);
9634 if (tg3_flag(tp, 57765_PLUS))
9635 tw32(STD_REPLENISH_LWM, bdcache_maxcnt);
9637 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS))
9640 bdcache_maxcnt = TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700;
9642 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1);
9644 val = min(bdcache_maxcnt / 2, host_rep_thresh);
9645 tw32(RCVBDI_JUMBO_THRESH, val);
9647 if (tg3_flag(tp, 57765_PLUS))
9648 tw32(JMB_REPLENISH_LWM, bdcache_maxcnt);
9651 static inline u32 calc_crc(unsigned char *buf, int len)
9659 for (j = 0; j < len; j++) {
9662 for (k = 0; k < 8; k++) {
9675 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9677 /* accept or reject all multicast frames */
9678 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9679 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9680 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9681 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9684 static void __tg3_set_rx_mode(struct net_device *dev)
9686 struct tg3 *tp = netdev_priv(dev);
9689 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9690 RX_MODE_KEEP_VLAN_TAG);
9692 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9693 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9696 if (!tg3_flag(tp, ENABLE_ASF))
9697 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9700 if (dev->flags & IFF_PROMISC) {
9701 /* Promiscuous mode. */
9702 rx_mode |= RX_MODE_PROMISC;
9703 } else if (dev->flags & IFF_ALLMULTI) {
9704 /* Accept all multicast. */
9705 tg3_set_multi(tp, 1);
9706 } else if (netdev_mc_empty(dev)) {
9707 /* Reject all multicast. */
9708 tg3_set_multi(tp, 0);
9710 /* Accept one or more multicast(s). */
9711 struct netdev_hw_addr *ha;
9712 u32 mc_filter[4] = { 0, };
9717 netdev_for_each_mc_addr(ha, dev) {
9718 crc = calc_crc(ha->addr, ETH_ALEN);
9720 regidx = (bit & 0x60) >> 5;
9722 mc_filter[regidx] |= (1 << bit);
9725 tw32(MAC_HASH_REG_0, mc_filter[0]);
9726 tw32(MAC_HASH_REG_1, mc_filter[1]);
9727 tw32(MAC_HASH_REG_2, mc_filter[2]);
9728 tw32(MAC_HASH_REG_3, mc_filter[3]);
9731 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) {
9732 rx_mode |= RX_MODE_PROMISC;
9733 } else if (!(dev->flags & IFF_PROMISC)) {
9734 /* Add all entries into to the mac addr filter list */
9736 struct netdev_hw_addr *ha;
9738 netdev_for_each_uc_addr(ha, dev) {
9739 __tg3_set_one_mac_addr(tp, ha->addr,
9740 i + TG3_UCAST_ADDR_IDX(tp));
9745 if (rx_mode != tp->rx_mode) {
9746 tp->rx_mode = rx_mode;
9747 tw32_f(MAC_RX_MODE, rx_mode);
9752 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt)
9756 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
9757 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt);
9760 static void tg3_rss_check_indir_tbl(struct tg3 *tp)
9764 if (!tg3_flag(tp, SUPPORT_MSIX))
9767 if (tp->rxq_cnt == 1) {
9768 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl));
9772 /* Validate table against current IRQ count */
9773 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
9774 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt)
9778 if (i != TG3_RSS_INDIR_TBL_SIZE)
9779 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt);
9782 static void tg3_rss_write_indir_tbl(struct tg3 *tp)
9785 u32 reg = MAC_RSS_INDIR_TBL_0;
9787 while (i < TG3_RSS_INDIR_TBL_SIZE) {
9788 u32 val = tp->rss_ind_tbl[i];
9790 for (; i % 8; i++) {
9792 val |= tp->rss_ind_tbl[i];
9799 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
9801 if (tg3_asic_rev(tp) == ASIC_REV_5719)
9802 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
9804 return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
9807 /* tp->lock is held. */
9808 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
9810 u32 val, rdmac_mode;
9812 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
9814 tg3_disable_ints(tp);
9818 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
9820 if (tg3_flag(tp, INIT_COMPLETE))
9821 tg3_abort_hw(tp, 1);
9823 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
9824 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) {
9825 tg3_phy_pull_config(tp);
9826 tg3_eee_pull_config(tp, NULL);
9827 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
9830 /* Enable MAC control of LPI */
9831 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
9837 err = tg3_chip_reset(tp);
9841 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
9843 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) {
9844 val = tr32(TG3_CPMU_CTRL);
9845 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
9846 tw32(TG3_CPMU_CTRL, val);
9848 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9849 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9850 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9851 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9853 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
9854 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
9855 val |= CPMU_LNK_AWARE_MACCLK_6_25;
9856 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
9858 val = tr32(TG3_CPMU_HST_ACC);
9859 val &= ~CPMU_HST_ACC_MACCLK_MASK;
9860 val |= CPMU_HST_ACC_MACCLK_6_25;
9861 tw32(TG3_CPMU_HST_ACC, val);
9864 if (tg3_asic_rev(tp) == ASIC_REV_57780) {
9865 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
9866 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
9867 PCIE_PWR_MGMT_L1_THRESH_4MS;
9868 tw32(PCIE_PWR_MGMT_THRESH, val);
9870 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
9871 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
9873 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
9875 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
9876 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
9879 if (tg3_flag(tp, L1PLLPD_EN)) {
9880 u32 grc_mode = tr32(GRC_MODE);
9882 /* Access the lower 1K of PL PCIE block registers. */
9883 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9884 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9886 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
9887 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
9888 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
9890 tw32(GRC_MODE, grc_mode);
9893 if (tg3_flag(tp, 57765_CLASS)) {
9894 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) {
9895 u32 grc_mode = tr32(GRC_MODE);
9897 /* Access the lower 1K of PL PCIE block registers. */
9898 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9899 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
9901 val = tr32(TG3_PCIE_TLDLPL_PORT +
9902 TG3_PCIE_PL_LO_PHYCTL5);
9903 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5,
9904 val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ);
9906 tw32(GRC_MODE, grc_mode);
9909 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) {
9912 /* Fix transmit hangs */
9913 val = tr32(TG3_CPMU_PADRNG_CTL);
9914 val |= TG3_CPMU_PADRNG_CTL_RDIV2;
9915 tw32(TG3_CPMU_PADRNG_CTL, val);
9917 grc_mode = tr32(GRC_MODE);
9919 /* Access the lower 1K of DL PCIE block registers. */
9920 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
9921 tw32(GRC_MODE, val | GRC_MODE_PCIE_DL_SEL);
9923 val = tr32(TG3_PCIE_TLDLPL_PORT +
9924 TG3_PCIE_DL_LO_FTSMAX);
9925 val &= ~TG3_PCIE_DL_LO_FTSMAX_MSK;
9926 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_DL_LO_FTSMAX,
9927 val | TG3_PCIE_DL_LO_FTSMAX_VAL);
9929 tw32(GRC_MODE, grc_mode);
9932 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
9933 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
9934 val |= CPMU_LSPD_10MB_MACCLK_6_25;
9935 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
9938 /* This works around an issue with Athlon chipsets on
9939 * B3 tigon3 silicon. This bit has no effect on any
9940 * other revision. But do not set this on PCI Express
9941 * chips and don't even touch the clocks if the CPMU is present.
9943 if (!tg3_flag(tp, CPMU_PRESENT)) {
9944 if (!tg3_flag(tp, PCI_EXPRESS))
9945 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
9946 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
9949 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 &&
9950 tg3_flag(tp, PCIX_MODE)) {
9951 val = tr32(TG3PCI_PCISTATE);
9952 val |= PCISTATE_RETRY_SAME_DMA;
9953 tw32(TG3PCI_PCISTATE, val);
9956 if (tg3_flag(tp, ENABLE_APE)) {
9957 /* Allow reads and writes to the
9958 * APE register and memory space.
9960 val = tr32(TG3PCI_PCISTATE);
9961 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
9962 PCISTATE_ALLOW_APE_SHMEM_WR |
9963 PCISTATE_ALLOW_APE_PSPACE_WR;
9964 tw32(TG3PCI_PCISTATE, val);
9967 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) {
9968 /* Enable some hw fixes. */
9969 val = tr32(TG3PCI_MSI_DATA);
9970 val |= (1 << 26) | (1 << 28) | (1 << 29);
9971 tw32(TG3PCI_MSI_DATA, val);
9974 /* Descriptor ring init may make accesses to the
9975 * NIC SRAM area to setup the TX descriptors, so we
9976 * can only do this after the hardware has been
9977 * successfully reset.
9979 err = tg3_init_rings(tp);
9983 if (tg3_flag(tp, 57765_PLUS)) {
9984 val = tr32(TG3PCI_DMA_RW_CTRL) &
9985 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
9986 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0)
9987 val &= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK;
9988 if (!tg3_flag(tp, 57765_CLASS) &&
9989 tg3_asic_rev(tp) != ASIC_REV_5717 &&
9990 tg3_asic_rev(tp) != ASIC_REV_5762)
9991 val |= DMA_RWCTRL_TAGGED_STAT_WA;
9992 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
9993 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 &&
9994 tg3_asic_rev(tp) != ASIC_REV_5761) {
9995 /* This value is determined during the probe time DMA
9996 * engine test, tg3_test_dma.
9998 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10001 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
10002 GRC_MODE_4X_NIC_SEND_RINGS |
10003 GRC_MODE_NO_TX_PHDR_CSUM |
10004 GRC_MODE_NO_RX_PHDR_CSUM);
10005 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
10007 /* Pseudo-header checksum is done by hardware logic and not
10008 * the offload processers, so make the chip do the pseudo-
10009 * header checksums on receive. For transmit it is more
10010 * convenient to do the pseudo-header checksum in software
10011 * as Linux does that on transmit for us in all cases.
10013 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
10015 val = GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP;
10017 tw32(TG3_RX_PTP_CTL,
10018 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
10020 if (tg3_flag(tp, PTP_CAPABLE))
10021 val |= GRC_MODE_TIME_SYNC_ENABLE;
10023 tw32(GRC_MODE, tp->grc_mode | val);
10025 /* Setup the timer prescalar register. Clock is always 66Mhz. */
10026 val = tr32(GRC_MISC_CFG);
10028 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
10029 tw32(GRC_MISC_CFG, val);
10031 /* Initialize MBUF/DESC pool. */
10032 if (tg3_flag(tp, 5750_PLUS)) {
10034 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) {
10035 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
10036 if (tg3_asic_rev(tp) == ASIC_REV_5704)
10037 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
10039 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
10040 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
10041 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
10042 } else if (tg3_flag(tp, TSO_CAPABLE)) {
10045 fw_len = tp->fw_len;
10046 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
10047 tw32(BUFMGR_MB_POOL_ADDR,
10048 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
10049 tw32(BUFMGR_MB_POOL_SIZE,
10050 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
10053 if (tp->dev->mtu <= ETH_DATA_LEN) {
10054 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10055 tp->bufmgr_config.mbuf_read_dma_low_water);
10056 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10057 tp->bufmgr_config.mbuf_mac_rx_low_water);
10058 tw32(BUFMGR_MB_HIGH_WATER,
10059 tp->bufmgr_config.mbuf_high_water);
10061 tw32(BUFMGR_MB_RDMA_LOW_WATER,
10062 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
10063 tw32(BUFMGR_MB_MACRX_LOW_WATER,
10064 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
10065 tw32(BUFMGR_MB_HIGH_WATER,
10066 tp->bufmgr_config.mbuf_high_water_jumbo);
10068 tw32(BUFMGR_DMA_LOW_WATER,
10069 tp->bufmgr_config.dma_low_water);
10070 tw32(BUFMGR_DMA_HIGH_WATER,
10071 tp->bufmgr_config.dma_high_water);
10073 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
10074 if (tg3_asic_rev(tp) == ASIC_REV_5719)
10075 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
10076 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10077 tg3_asic_rev(tp) == ASIC_REV_5762 ||
10078 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10079 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0)
10080 val |= BUFMGR_MODE_MBLOW_ATTN_ENAB;
10081 tw32(BUFMGR_MODE, val);
10082 for (i = 0; i < 2000; i++) {
10083 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
10088 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__);
10092 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1)
10093 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
10095 tg3_setup_rxbd_thresholds(tp);
10097 /* Initialize TG3_BDINFO's at:
10098 * RCVDBDI_STD_BD: standard eth size rx ring
10099 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
10100 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
10103 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
10104 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
10105 * ring attribute flags
10106 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
10108 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
10109 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
10111 * The size of each ring is fixed in the firmware, but the location is
10114 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10115 ((u64) tpr->rx_std_mapping >> 32));
10116 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10117 ((u64) tpr->rx_std_mapping & 0xffffffff));
10118 if (!tg3_flag(tp, 5717_PLUS))
10119 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
10120 NIC_SRAM_RX_BUFFER_DESC);
10122 /* Disable the mini ring */
10123 if (!tg3_flag(tp, 5705_PLUS))
10124 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
10125 BDINFO_FLAGS_DISABLED);
10127 /* Program the jumbo buffer descriptor ring control
10128 * blocks on those devices that have them.
10130 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10131 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) {
10133 if (tg3_flag(tp, JUMBO_RING_ENABLE)) {
10134 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
10135 ((u64) tpr->rx_jmb_mapping >> 32));
10136 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
10137 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
10138 val = TG3_RX_JMB_RING_SIZE(tp) <<
10139 BDINFO_FLAGS_MAXLEN_SHIFT;
10140 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10141 val | BDINFO_FLAGS_USE_EXT_RECV);
10142 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) ||
10143 tg3_flag(tp, 57765_CLASS) ||
10144 tg3_asic_rev(tp) == ASIC_REV_5762)
10145 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
10146 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
10148 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
10149 BDINFO_FLAGS_DISABLED);
10152 if (tg3_flag(tp, 57765_PLUS)) {
10153 val = TG3_RX_STD_RING_SIZE(tp);
10154 val <<= BDINFO_FLAGS_MAXLEN_SHIFT;
10155 val |= (TG3_RX_STD_DMA_SZ << 2);
10157 val = TG3_RX_STD_DMA_SZ << BDINFO_FLAGS_MAXLEN_SHIFT;
10159 val = TG3_RX_STD_MAX_SIZE_5700 << BDINFO_FLAGS_MAXLEN_SHIFT;
10161 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
10163 tpr->rx_std_prod_idx = tp->rx_pending;
10164 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
10166 tpr->rx_jmb_prod_idx =
10167 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0;
10168 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
10170 tg3_rings_reset(tp);
10172 /* Initialize MAC address and backoff seed. */
10173 __tg3_set_mac_addr(tp, false);
10175 /* MTU + ethernet header + FCS + optional VLAN tag */
10176 tw32(MAC_RX_MTU_SIZE,
10177 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
10179 /* The slot time is changed by tg3_setup_phy if we
10180 * run at gigabit with half duplex.
10182 val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
10183 (6 << TX_LENGTHS_IPG_SHIFT) |
10184 (32 << TX_LENGTHS_SLOT_TIME_SHIFT);
10186 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10187 tg3_asic_rev(tp) == ASIC_REV_5762)
10188 val |= tr32(MAC_TX_LENGTHS) &
10189 (TX_LENGTHS_JMB_FRM_LEN_MSK |
10190 TX_LENGTHS_CNT_DWN_VAL_MSK);
10192 tw32(MAC_TX_LENGTHS, val);
10194 /* Receive rules. */
10195 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
10196 tw32(RCVLPC_CONFIG, 0x0181);
10198 /* Calculate RDMAC_MODE setting early, we need it to determine
10199 * the RCVLPC_STATE_ENABLE mask.
10201 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
10202 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
10203 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
10204 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
10205 RDMAC_MODE_LNGREAD_ENAB);
10207 if (tg3_asic_rev(tp) == ASIC_REV_5717)
10208 rdmac_mode |= RDMAC_MODE_MULT_DMA_RD_DIS;
10210 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
10211 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10212 tg3_asic_rev(tp) == ASIC_REV_57780)
10213 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
10214 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
10215 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
10217 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10218 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10219 if (tg3_flag(tp, TSO_CAPABLE) &&
10220 tg3_asic_rev(tp) == ASIC_REV_5705) {
10221 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
10222 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10223 !tg3_flag(tp, IS_5788)) {
10224 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10228 if (tg3_flag(tp, PCI_EXPRESS))
10229 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
10231 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10233 if (tp->dev->mtu <= ETH_DATA_LEN) {
10234 rdmac_mode |= RDMAC_MODE_JMB_2K_MMRR;
10235 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K;
10239 if (tg3_flag(tp, HW_TSO_1) ||
10240 tg3_flag(tp, HW_TSO_2) ||
10241 tg3_flag(tp, HW_TSO_3))
10242 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
10244 if (tg3_flag(tp, 57765_PLUS) ||
10245 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10246 tg3_asic_rev(tp) == ASIC_REV_57780)
10247 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
10249 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10250 tg3_asic_rev(tp) == ASIC_REV_5762)
10251 rdmac_mode |= tr32(RDMAC_MODE) & RDMAC_MODE_H2BNC_VLAN_DET;
10253 if (tg3_asic_rev(tp) == ASIC_REV_5761 ||
10254 tg3_asic_rev(tp) == ASIC_REV_5784 ||
10255 tg3_asic_rev(tp) == ASIC_REV_5785 ||
10256 tg3_asic_rev(tp) == ASIC_REV_57780 ||
10257 tg3_flag(tp, 57765_PLUS)) {
10260 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10261 tgtreg = TG3_RDMA_RSRVCTRL_REG2;
10263 tgtreg = TG3_RDMA_RSRVCTRL_REG;
10265 val = tr32(tgtreg);
10266 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
10267 tg3_asic_rev(tp) == ASIC_REV_5762) {
10268 val &= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK |
10269 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK |
10270 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK);
10271 val |= TG3_RDMA_RSRVCTRL_TXMRGN_320B |
10272 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
10273 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K;
10275 tw32(tgtreg, val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
10278 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10279 tg3_asic_rev(tp) == ASIC_REV_5720 ||
10280 tg3_asic_rev(tp) == ASIC_REV_5762) {
10283 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10284 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL2;
10286 tgtreg = TG3_LSO_RD_DMA_CRPTEN_CTRL;
10288 val = tr32(tgtreg);
10290 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
10291 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
10294 /* Receive/send statistics. */
10295 if (tg3_flag(tp, 5750_PLUS)) {
10296 val = tr32(RCVLPC_STATS_ENABLE);
10297 val &= ~RCVLPC_STATSENAB_DACK_FIX;
10298 tw32(RCVLPC_STATS_ENABLE, val);
10299 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
10300 tg3_flag(tp, TSO_CAPABLE)) {
10301 val = tr32(RCVLPC_STATS_ENABLE);
10302 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
10303 tw32(RCVLPC_STATS_ENABLE, val);
10305 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
10307 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
10308 tw32(SNDDATAI_STATSENAB, 0xffffff);
10309 tw32(SNDDATAI_STATSCTRL,
10310 (SNDDATAI_SCTRL_ENABLE |
10311 SNDDATAI_SCTRL_FASTUPD));
10313 /* Setup host coalescing engine. */
10314 tw32(HOSTCC_MODE, 0);
10315 for (i = 0; i < 2000; i++) {
10316 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
10321 __tg3_set_coalesce(tp, &tp->coal);
10323 if (!tg3_flag(tp, 5705_PLUS)) {
10324 /* Status/statistics block address. See tg3_timer,
10325 * the tg3_periodic_fetch_stats call there, and
10326 * tg3_get_stats to see how this works for 5705/5750 chips.
10328 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
10329 ((u64) tp->stats_mapping >> 32));
10330 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
10331 ((u64) tp->stats_mapping & 0xffffffff));
10332 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
10334 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
10336 /* Clear statistics and status block memory areas */
10337 for (i = NIC_SRAM_STATS_BLK;
10338 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
10339 i += sizeof(u32)) {
10340 tg3_write_mem(tp, i, 0);
10345 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
10347 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
10348 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
10349 if (!tg3_flag(tp, 5705_PLUS))
10350 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
10352 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) {
10353 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT;
10354 /* reset to prevent losing 1st rx packet intermittently */
10355 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10359 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
10360 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE |
10361 MAC_MODE_FHDE_ENABLE;
10362 if (tg3_flag(tp, ENABLE_APE))
10363 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
10364 if (!tg3_flag(tp, 5705_PLUS) &&
10365 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10366 tg3_asic_rev(tp) != ASIC_REV_5700)
10367 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
10368 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10371 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10372 * If TG3_FLAG_IS_NIC is zero, we should read the
10373 * register to preserve the GPIO settings for LOMs. The GPIOs,
10374 * whether used as inputs or outputs, are set by boot code after
10377 if (!tg3_flag(tp, IS_NIC)) {
10380 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
10381 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
10382 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
10384 if (tg3_asic_rev(tp) == ASIC_REV_5752)
10385 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
10386 GRC_LCLCTRL_GPIO_OUTPUT3;
10388 if (tg3_asic_rev(tp) == ASIC_REV_5755)
10389 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
10391 tp->grc_local_ctrl &= ~gpio_mask;
10392 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
10394 /* GPIO1 must be driven high for eeprom write protect */
10395 if (tg3_flag(tp, EEPROM_WRITE_PROT))
10396 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10397 GRC_LCLCTRL_GPIO_OUTPUT1);
10399 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10402 if (tg3_flag(tp, USING_MSIX)) {
10403 val = tr32(MSGINT_MODE);
10404 val |= MSGINT_MODE_ENABLE;
10405 if (tp->irq_cnt > 1)
10406 val |= MSGINT_MODE_MULTIVEC_EN;
10407 if (!tg3_flag(tp, 1SHOT_MSI))
10408 val |= MSGINT_MODE_ONE_SHOT_DISABLE;
10409 tw32(MSGINT_MODE, val);
10412 if (!tg3_flag(tp, 5705_PLUS)) {
10413 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10417 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
10418 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
10419 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
10420 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
10421 WDMAC_MODE_LNGREAD_ENAB);
10423 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
10424 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
10425 if (tg3_flag(tp, TSO_CAPABLE) &&
10426 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 ||
10427 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) {
10429 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
10430 !tg3_flag(tp, IS_5788)) {
10431 val |= WDMAC_MODE_RX_ACCEL;
10435 /* Enable host coalescing bug fix */
10436 if (tg3_flag(tp, 5755_PLUS))
10437 val |= WDMAC_MODE_STATUS_TAG_FIX;
10439 if (tg3_asic_rev(tp) == ASIC_REV_5785)
10440 val |= WDMAC_MODE_BURST_ALL_DATA;
10442 tw32_f(WDMAC_MODE, val);
10445 if (tg3_flag(tp, PCIX_MODE)) {
10448 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10450 if (tg3_asic_rev(tp) == ASIC_REV_5703) {
10451 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
10452 pcix_cmd |= PCI_X_CMD_READ_2K;
10453 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) {
10454 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
10455 pcix_cmd |= PCI_X_CMD_READ_2K;
10457 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
10461 tw32_f(RDMAC_MODE, rdmac_mode);
10464 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
10465 tg3_asic_rev(tp) == ASIC_REV_5720) {
10466 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
10467 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
10470 if (i < TG3_NUM_RDMA_CHANNELS) {
10471 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10472 val |= tg3_lso_rd_dma_workaround_bit(tp);
10473 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10474 tg3_flag_set(tp, 5719_5720_RDMA_BUG);
10478 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
10479 if (!tg3_flag(tp, 5705_PLUS))
10480 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
10482 if (tg3_asic_rev(tp) == ASIC_REV_5761)
10483 tw32(SNDDATAC_MODE,
10484 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
10486 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
10488 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
10489 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
10490 val = RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ;
10491 if (tg3_flag(tp, LRG_PROD_RING_CAP))
10492 val |= RCVDBDI_MODE_LRG_RING_SZ;
10493 tw32(RCVDBDI_MODE, val);
10494 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
10495 if (tg3_flag(tp, HW_TSO_1) ||
10496 tg3_flag(tp, HW_TSO_2) ||
10497 tg3_flag(tp, HW_TSO_3))
10498 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
10499 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
10500 if (tg3_flag(tp, ENABLE_TSS))
10501 val |= SNDBDI_MODE_MULTI_TXQ_EN;
10502 tw32(SNDBDI_MODE, val);
10503 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
10505 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
10506 err = tg3_load_5701_a0_firmware_fix(tp);
10511 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
10512 /* Ignore any errors for the firmware download. If download
10513 * fails, the device will operate with EEE disabled
10515 tg3_load_57766_firmware(tp);
10518 if (tg3_flag(tp, TSO_CAPABLE)) {
10519 err = tg3_load_tso_firmware(tp);
10524 tp->tx_mode = TX_MODE_ENABLE;
10526 if (tg3_flag(tp, 5755_PLUS) ||
10527 tg3_asic_rev(tp) == ASIC_REV_5906)
10528 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX;
10530 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
10531 tg3_asic_rev(tp) == ASIC_REV_5762) {
10532 val = TX_MODE_JMB_FRM_LEN | TX_MODE_CNT_DN_MODE;
10533 tp->tx_mode &= ~val;
10534 tp->tx_mode |= tr32(MAC_TX_MODE) & val;
10537 tw32_f(MAC_TX_MODE, tp->tx_mode);
10540 if (tg3_flag(tp, ENABLE_RSS)) {
10541 tg3_rss_write_indir_tbl(tp);
10543 /* Setup the "secret" hash key. */
10544 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
10545 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
10546 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
10547 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
10548 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
10549 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
10550 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
10551 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
10552 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
10553 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
10556 tp->rx_mode = RX_MODE_ENABLE;
10557 if (tg3_flag(tp, 5755_PLUS))
10558 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
10560 if (tg3_asic_rev(tp) == ASIC_REV_5762)
10561 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX;
10563 if (tg3_flag(tp, ENABLE_RSS))
10564 tp->rx_mode |= RX_MODE_RSS_ENABLE |
10565 RX_MODE_RSS_ITBL_HASH_BITS_7 |
10566 RX_MODE_RSS_IPV6_HASH_EN |
10567 RX_MODE_RSS_TCP_IPV6_HASH_EN |
10568 RX_MODE_RSS_IPV4_HASH_EN |
10569 RX_MODE_RSS_TCP_IPV4_HASH_EN;
10571 tw32_f(MAC_RX_MODE, tp->rx_mode);
10574 tw32(MAC_LED_CTRL, tp->led_ctrl);
10576 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
10577 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10578 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10581 tw32_f(MAC_RX_MODE, tp->rx_mode);
10584 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
10585 if ((tg3_asic_rev(tp) == ASIC_REV_5704) &&
10586 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) {
10587 /* Set drive transmission level to 1.2V */
10588 /* only if the signal pre-emphasis bit is not set */
10589 val = tr32(MAC_SERDES_CFG);
10592 tw32(MAC_SERDES_CFG, val);
10594 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1)
10595 tw32(MAC_SERDES_CFG, 0x616000);
10598 /* Prevent chip from dropping frames when flow control
10601 if (tg3_flag(tp, 57765_CLASS))
10605 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
10607 if (tg3_asic_rev(tp) == ASIC_REV_5704 &&
10608 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
10609 /* Use hardware link auto-negotiation */
10610 tg3_flag_set(tp, HW_AUTONEG);
10613 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10614 tg3_asic_rev(tp) == ASIC_REV_5714) {
10617 tmp = tr32(SERDES_RX_CTRL);
10618 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
10619 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
10620 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
10621 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10624 if (!tg3_flag(tp, USE_PHYLIB)) {
10625 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
10626 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER;
10628 err = tg3_setup_phy(tp, false);
10632 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
10633 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) {
10636 /* Clear CRC stats. */
10637 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
10638 tg3_writephy(tp, MII_TG3_TEST1,
10639 tmp | MII_TG3_TEST1_CRC_EN);
10640 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp);
10645 __tg3_set_rx_mode(tp->dev);
10647 /* Initialize receive rules. */
10648 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
10649 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
10650 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
10651 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
10653 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS))
10657 if (tg3_flag(tp, ENABLE_ASF))
10661 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
10663 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
10665 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
10667 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
10669 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
10671 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
10673 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
10675 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
10677 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
10679 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
10681 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
10683 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
10685 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10687 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10695 if (tg3_flag(tp, ENABLE_APE))
10696 /* Write our heartbeat update interval to APE. */
10697 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
10698 APE_HOST_HEARTBEAT_INT_DISABLE);
10700 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
10705 /* Called at device open time to get the chip ready for
10706 * packet processing. Invoked with tp->lock held.
10708 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
10710 /* Chip may have been just powered on. If so, the boot code may still
10711 * be running initialization. Wait for it to finish to avoid races in
10712 * accessing the hardware.
10714 tg3_enable_register_access(tp);
10717 tg3_switch_clocks(tp);
10719 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10721 return tg3_reset_hw(tp, reset_phy);
10724 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir)
10728 for (i = 0; i < TG3_SD_NUM_RECS; i++, ocir++) {
10729 u32 off = i * TG3_OCIR_LEN, len = TG3_OCIR_LEN;
10731 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len);
10734 if (ocir->signature != TG3_OCIR_SIG_MAGIC ||
10735 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE))
10736 memset(ocir, 0, TG3_OCIR_LEN);
10740 /* sysfs attributes for hwmon */
10741 static ssize_t tg3_show_temp(struct device *dev,
10742 struct device_attribute *devattr, char *buf)
10744 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
10745 struct tg3 *tp = dev_get_drvdata(dev);
10748 spin_lock_bh(&tp->lock);
10749 tg3_ape_scratchpad_read(tp, &temperature, attr->index,
10750 sizeof(temperature));
10751 spin_unlock_bh(&tp->lock);
10752 return sprintf(buf, "%u\n", temperature);
10756 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, tg3_show_temp, NULL,
10757 TG3_TEMP_SENSOR_OFFSET);
10758 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, tg3_show_temp, NULL,
10759 TG3_TEMP_CAUTION_OFFSET);
10760 static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, tg3_show_temp, NULL,
10761 TG3_TEMP_MAX_OFFSET);
10763 static struct attribute *tg3_attrs[] = {
10764 &sensor_dev_attr_temp1_input.dev_attr.attr,
10765 &sensor_dev_attr_temp1_crit.dev_attr.attr,
10766 &sensor_dev_attr_temp1_max.dev_attr.attr,
10769 ATTRIBUTE_GROUPS(tg3);
10771 static void tg3_hwmon_close(struct tg3 *tp)
10773 if (tp->hwmon_dev) {
10774 hwmon_device_unregister(tp->hwmon_dev);
10775 tp->hwmon_dev = NULL;
10779 static void tg3_hwmon_open(struct tg3 *tp)
10783 struct pci_dev *pdev = tp->pdev;
10784 struct tg3_ocir ocirs[TG3_SD_NUM_RECS];
10786 tg3_sd_scan_scratchpad(tp, ocirs);
10788 for (i = 0; i < TG3_SD_NUM_RECS; i++) {
10789 if (!ocirs[i].src_data_length)
10792 size += ocirs[i].src_hdr_length;
10793 size += ocirs[i].src_data_length;
10799 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3",
10801 if (IS_ERR(tp->hwmon_dev)) {
10802 tp->hwmon_dev = NULL;
10803 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n");
10808 #define TG3_STAT_ADD32(PSTAT, REG) \
10809 do { u32 __val = tr32(REG); \
10810 (PSTAT)->low += __val; \
10811 if ((PSTAT)->low < __val) \
10812 (PSTAT)->high += 1; \
10815 static void tg3_periodic_fetch_stats(struct tg3 *tp)
10817 struct tg3_hw_stats *sp = tp->hw_stats;
10822 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
10823 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
10824 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
10825 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
10826 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
10827 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
10828 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
10829 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
10830 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
10831 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
10832 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
10833 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
10834 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
10835 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
10836 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
10837 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
10840 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
10841 val &= ~tg3_lso_rd_dma_workaround_bit(tp);
10842 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
10843 tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
10846 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
10847 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
10848 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
10849 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
10850 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
10851 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
10852 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
10853 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
10854 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
10855 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
10856 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
10857 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
10858 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
10859 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
10861 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
10862 if (tg3_asic_rev(tp) != ASIC_REV_5717 &&
10863 tg3_asic_rev(tp) != ASIC_REV_5762 &&
10864 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 &&
10865 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) {
10866 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
10868 u32 val = tr32(HOSTCC_FLOW_ATTN);
10869 val = (val & HOSTCC_FLOW_ATTN_MBUF_LWM) ? 1 : 0;
10871 tw32(HOSTCC_FLOW_ATTN, HOSTCC_FLOW_ATTN_MBUF_LWM);
10872 sp->rx_discards.low += val;
10873 if (sp->rx_discards.low < val)
10874 sp->rx_discards.high += 1;
10876 sp->mbuf_lwm_thresh_hit = sp->rx_discards;
10878 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
10881 static void tg3_chk_missed_msi(struct tg3 *tp)
10885 for (i = 0; i < tp->irq_cnt; i++) {
10886 struct tg3_napi *tnapi = &tp->napi[i];
10888 if (tg3_has_work(tnapi)) {
10889 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr &&
10890 tnapi->last_tx_cons == tnapi->tx_cons) {
10891 if (tnapi->chk_msi_cnt < 1) {
10892 tnapi->chk_msi_cnt++;
10898 tnapi->chk_msi_cnt = 0;
10899 tnapi->last_rx_cons = tnapi->rx_rcb_ptr;
10900 tnapi->last_tx_cons = tnapi->tx_cons;
10904 static void tg3_timer(unsigned long __opaque)
10906 struct tg3 *tp = (struct tg3 *) __opaque;
10908 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING))
10909 goto restart_timer;
10911 spin_lock(&tp->lock);
10913 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
10914 tg3_flag(tp, 57765_CLASS))
10915 tg3_chk_missed_msi(tp);
10917 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
10918 /* BCM4785: Flush posted writes from GbE to host memory. */
10922 if (!tg3_flag(tp, TAGGED_STATUS)) {
10923 /* All of this garbage is because when using non-tagged
10924 * IRQ status the mailbox/status_block protocol the chip
10925 * uses with the cpu is race prone.
10927 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
10928 tw32(GRC_LOCAL_CTRL,
10929 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
10931 tw32(HOSTCC_MODE, tp->coalesce_mode |
10932 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
10935 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10936 spin_unlock(&tp->lock);
10937 tg3_reset_task_schedule(tp);
10938 goto restart_timer;
10942 /* This part only runs once per second. */
10943 if (!--tp->timer_counter) {
10944 if (tg3_flag(tp, 5705_PLUS))
10945 tg3_periodic_fetch_stats(tp);
10947 if (tp->setlpicnt && !--tp->setlpicnt)
10948 tg3_phy_eee_enable(tp);
10950 if (tg3_flag(tp, USE_LINKCHG_REG)) {
10954 mac_stat = tr32(MAC_STATUS);
10957 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) {
10958 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
10960 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
10964 tg3_setup_phy(tp, false);
10965 } else if (tg3_flag(tp, POLL_SERDES)) {
10966 u32 mac_stat = tr32(MAC_STATUS);
10967 int need_setup = 0;
10970 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
10973 if (!tp->link_up &&
10974 (mac_stat & (MAC_STATUS_PCS_SYNCED |
10975 MAC_STATUS_SIGNAL_DET))) {
10979 if (!tp->serdes_counter) {
10982 ~MAC_MODE_PORT_MODE_MASK));
10984 tw32_f(MAC_MODE, tp->mac_mode);
10987 tg3_setup_phy(tp, false);
10989 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) &&
10990 tg3_flag(tp, 5780_CLASS)) {
10991 tg3_serdes_parallel_detect(tp);
10992 } else if (tg3_flag(tp, POLL_CPMU_LINK)) {
10993 u32 cpmu = tr32(TG3_CPMU_STATUS);
10994 bool link_up = !((cpmu & TG3_CPMU_STATUS_LINK_MASK) ==
10995 TG3_CPMU_STATUS_LINK_MASK);
10997 if (link_up != tp->link_up)
10998 tg3_setup_phy(tp, false);
11001 tp->timer_counter = tp->timer_multiplier;
11004 /* Heartbeat is only sent once every 2 seconds.
11006 * The heartbeat is to tell the ASF firmware that the host
11007 * driver is still alive. In the event that the OS crashes,
11008 * ASF needs to reset the hardware to free up the FIFO space
11009 * that may be filled with rx packets destined for the host.
11010 * If the FIFO is full, ASF will no longer function properly.
11012 * Unintended resets have been reported on real time kernels
11013 * where the timer doesn't run on time. Netpoll will also have
11016 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
11017 * to check the ring condition when the heartbeat is expiring
11018 * before doing the reset. This will prevent most unintended
11021 if (!--tp->asf_counter) {
11022 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) {
11023 tg3_wait_for_event_ack(tp);
11025 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
11026 FWCMD_NICDRV_ALIVE3);
11027 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
11028 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX,
11029 TG3_FW_UPDATE_TIMEOUT_SEC);
11031 tg3_generate_fw_event(tp);
11033 tp->asf_counter = tp->asf_multiplier;
11036 spin_unlock(&tp->lock);
11039 tp->timer.expires = jiffies + tp->timer_offset;
11040 add_timer(&tp->timer);
11043 static void tg3_timer_init(struct tg3 *tp)
11045 if (tg3_flag(tp, TAGGED_STATUS) &&
11046 tg3_asic_rev(tp) != ASIC_REV_5717 &&
11047 !tg3_flag(tp, 57765_CLASS))
11048 tp->timer_offset = HZ;
11050 tp->timer_offset = HZ / 10;
11052 BUG_ON(tp->timer_offset > HZ);
11054 tp->timer_multiplier = (HZ / tp->timer_offset);
11055 tp->asf_multiplier = (HZ / tp->timer_offset) *
11056 TG3_FW_UPDATE_FREQ_SEC;
11058 init_timer(&tp->timer);
11059 tp->timer.data = (unsigned long) tp;
11060 tp->timer.function = tg3_timer;
11063 static void tg3_timer_start(struct tg3 *tp)
11065 tp->asf_counter = tp->asf_multiplier;
11066 tp->timer_counter = tp->timer_multiplier;
11068 tp->timer.expires = jiffies + tp->timer_offset;
11069 add_timer(&tp->timer);
11072 static void tg3_timer_stop(struct tg3 *tp)
11074 del_timer_sync(&tp->timer);
11077 /* Restart hardware after configuration changes, self-test, etc.
11078 * Invoked with tp->lock held.
11080 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy)
11081 __releases(tp->lock)
11082 __acquires(tp->lock)
11086 err = tg3_init_hw(tp, reset_phy);
11088 netdev_err(tp->dev,
11089 "Failed to re-initialize device, aborting\n");
11090 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11091 tg3_full_unlock(tp);
11092 tg3_timer_stop(tp);
11094 tg3_napi_enable(tp);
11095 dev_close(tp->dev);
11096 tg3_full_lock(tp, 0);
11101 static void tg3_reset_task(struct work_struct *work)
11103 struct tg3 *tp = container_of(work, struct tg3, reset_task);
11106 tg3_full_lock(tp, 0);
11108 if (!netif_running(tp->dev)) {
11109 tg3_flag_clear(tp, RESET_TASK_PENDING);
11110 tg3_full_unlock(tp);
11114 tg3_full_unlock(tp);
11118 tg3_netif_stop(tp);
11120 tg3_full_lock(tp, 1);
11122 if (tg3_flag(tp, TX_RECOVERY_PENDING)) {
11123 tp->write32_tx_mbox = tg3_write32_tx_mbox;
11124 tp->write32_rx_mbox = tg3_write_flush_reg32;
11125 tg3_flag_set(tp, MBOX_WRITE_REORDER);
11126 tg3_flag_clear(tp, TX_RECOVERY_PENDING);
11129 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
11130 err = tg3_init_hw(tp, true);
11134 tg3_netif_start(tp);
11137 tg3_full_unlock(tp);
11142 tg3_flag_clear(tp, RESET_TASK_PENDING);
11145 static int tg3_request_irq(struct tg3 *tp, int irq_num)
11148 unsigned long flags;
11150 struct tg3_napi *tnapi = &tp->napi[irq_num];
11152 if (tp->irq_cnt == 1)
11153 name = tp->dev->name;
11155 name = &tnapi->irq_lbl[0];
11156 if (tnapi->tx_buffers && tnapi->rx_rcb)
11157 snprintf(name, IFNAMSIZ,
11158 "%s-txrx-%d", tp->dev->name, irq_num);
11159 else if (tnapi->tx_buffers)
11160 snprintf(name, IFNAMSIZ,
11161 "%s-tx-%d", tp->dev->name, irq_num);
11162 else if (tnapi->rx_rcb)
11163 snprintf(name, IFNAMSIZ,
11164 "%s-rx-%d", tp->dev->name, irq_num);
11166 snprintf(name, IFNAMSIZ,
11167 "%s-%d", tp->dev->name, irq_num);
11168 name[IFNAMSIZ-1] = 0;
11171 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11173 if (tg3_flag(tp, 1SHOT_MSI))
11174 fn = tg3_msi_1shot;
11177 fn = tg3_interrupt;
11178 if (tg3_flag(tp, TAGGED_STATUS))
11179 fn = tg3_interrupt_tagged;
11180 flags = IRQF_SHARED;
11183 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
11186 static int tg3_test_interrupt(struct tg3 *tp)
11188 struct tg3_napi *tnapi = &tp->napi[0];
11189 struct net_device *dev = tp->dev;
11190 int err, i, intr_ok = 0;
11193 if (!netif_running(dev))
11196 tg3_disable_ints(tp);
11198 free_irq(tnapi->irq_vec, tnapi);
11201 * Turn off MSI one shot mode. Otherwise this test has no
11202 * observable way to know whether the interrupt was delivered.
11204 if (tg3_flag(tp, 57765_PLUS)) {
11205 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
11206 tw32(MSGINT_MODE, val);
11209 err = request_irq(tnapi->irq_vec, tg3_test_isr,
11210 IRQF_SHARED, dev->name, tnapi);
11214 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
11215 tg3_enable_ints(tp);
11217 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
11220 for (i = 0; i < 5; i++) {
11221 u32 int_mbox, misc_host_ctrl;
11223 int_mbox = tr32_mailbox(tnapi->int_mbox);
11224 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
11226 if ((int_mbox != 0) ||
11227 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
11232 if (tg3_flag(tp, 57765_PLUS) &&
11233 tnapi->hw_status->status_tag != tnapi->last_tag)
11234 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
11239 tg3_disable_ints(tp);
11241 free_irq(tnapi->irq_vec, tnapi);
11243 err = tg3_request_irq(tp, 0);
11249 /* Reenable MSI one shot mode. */
11250 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) {
11251 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
11252 tw32(MSGINT_MODE, val);
11260 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
11261 * successfully restored
11263 static int tg3_test_msi(struct tg3 *tp)
11268 if (!tg3_flag(tp, USING_MSI))
11271 /* Turn off SERR reporting in case MSI terminates with Master
11274 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
11275 pci_write_config_word(tp->pdev, PCI_COMMAND,
11276 pci_cmd & ~PCI_COMMAND_SERR);
11278 err = tg3_test_interrupt(tp);
11280 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
11285 /* other failures */
11289 /* MSI test failed, go back to INTx mode */
11290 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching "
11291 "to INTx mode. Please report this failure to the PCI "
11292 "maintainer and include system chipset information\n");
11294 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11296 pci_disable_msi(tp->pdev);
11298 tg3_flag_clear(tp, USING_MSI);
11299 tp->napi[0].irq_vec = tp->pdev->irq;
11301 err = tg3_request_irq(tp, 0);
11305 /* Need to reset the chip because the MSI cycle may have terminated
11306 * with Master Abort.
11308 tg3_full_lock(tp, 1);
11310 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11311 err = tg3_init_hw(tp, true);
11313 tg3_full_unlock(tp);
11316 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
11321 static int tg3_request_firmware(struct tg3 *tp)
11323 const struct tg3_firmware_hdr *fw_hdr;
11325 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
11326 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
11331 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data;
11333 /* Firmware blob starts with version numbers, followed by
11334 * start address and _full_ length including BSS sections
11335 * (which must be longer than the actual data, of course
11338 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */
11339 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) {
11340 netdev_err(tp->dev, "bogus length %d in \"%s\"\n",
11341 tp->fw_len, tp->fw_needed);
11342 release_firmware(tp->fw);
11347 /* We no longer need firmware; we have it. */
11348 tp->fw_needed = NULL;
11352 static u32 tg3_irq_count(struct tg3 *tp)
11354 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt);
11357 /* We want as many rx rings enabled as there are cpus.
11358 * In multiqueue MSI-X mode, the first MSI-X vector
11359 * only deals with link interrupts, etc, so we add
11360 * one to the number of vectors we are requesting.
11362 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max);
11368 static bool tg3_enable_msix(struct tg3 *tp)
11371 struct msix_entry msix_ent[TG3_IRQ_MAX_VECS];
11373 tp->txq_cnt = tp->txq_req;
11374 tp->rxq_cnt = tp->rxq_req;
11376 tp->rxq_cnt = netif_get_num_default_rss_queues();
11377 if (tp->rxq_cnt > tp->rxq_max)
11378 tp->rxq_cnt = tp->rxq_max;
11380 /* Disable multiple TX rings by default. Simple round-robin hardware
11381 * scheduling of the TX rings can cause starvation of rings with
11382 * small packets when other rings have TSO or jumbo packets.
11387 tp->irq_cnt = tg3_irq_count(tp);
11389 for (i = 0; i < tp->irq_max; i++) {
11390 msix_ent[i].entry = i;
11391 msix_ent[i].vector = 0;
11394 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt);
11397 } else if (rc < tp->irq_cnt) {
11398 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n",
11401 tp->rxq_cnt = max(rc - 1, 1);
11403 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max);
11406 for (i = 0; i < tp->irq_max; i++)
11407 tp->napi[i].irq_vec = msix_ent[i].vector;
11409 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) {
11410 pci_disable_msix(tp->pdev);
11414 if (tp->irq_cnt == 1)
11417 tg3_flag_set(tp, ENABLE_RSS);
11419 if (tp->txq_cnt > 1)
11420 tg3_flag_set(tp, ENABLE_TSS);
11422 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt);
11427 static void tg3_ints_init(struct tg3 *tp)
11429 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) &&
11430 !tg3_flag(tp, TAGGED_STATUS)) {
11431 /* All MSI supporting chips should support tagged
11432 * status. Assert that this is the case.
11434 netdev_warn(tp->dev,
11435 "MSI without TAGGED_STATUS? Not using MSI\n");
11439 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp))
11440 tg3_flag_set(tp, USING_MSIX);
11441 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0)
11442 tg3_flag_set(tp, USING_MSI);
11444 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) {
11445 u32 msi_mode = tr32(MSGINT_MODE);
11446 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1)
11447 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
11448 if (!tg3_flag(tp, 1SHOT_MSI))
11449 msi_mode |= MSGINT_MODE_ONE_SHOT_DISABLE;
11450 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
11453 if (!tg3_flag(tp, USING_MSIX)) {
11455 tp->napi[0].irq_vec = tp->pdev->irq;
11458 if (tp->irq_cnt == 1) {
11461 netif_set_real_num_tx_queues(tp->dev, 1);
11462 netif_set_real_num_rx_queues(tp->dev, 1);
11466 static void tg3_ints_fini(struct tg3 *tp)
11468 if (tg3_flag(tp, USING_MSIX))
11469 pci_disable_msix(tp->pdev);
11470 else if (tg3_flag(tp, USING_MSI))
11471 pci_disable_msi(tp->pdev);
11472 tg3_flag_clear(tp, USING_MSI);
11473 tg3_flag_clear(tp, USING_MSIX);
11474 tg3_flag_clear(tp, ENABLE_RSS);
11475 tg3_flag_clear(tp, ENABLE_TSS);
11478 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq,
11481 struct net_device *dev = tp->dev;
11485 * Setup interrupts first so we know how
11486 * many NAPI resources to allocate
11490 tg3_rss_check_indir_tbl(tp);
11492 /* The placement of this call is tied
11493 * to the setup and use of Host TX descriptors.
11495 err = tg3_alloc_consistent(tp);
11497 goto out_ints_fini;
11501 tg3_napi_enable(tp);
11503 for (i = 0; i < tp->irq_cnt; i++) {
11504 struct tg3_napi *tnapi = &tp->napi[i];
11505 err = tg3_request_irq(tp, i);
11507 for (i--; i >= 0; i--) {
11508 tnapi = &tp->napi[i];
11509 free_irq(tnapi->irq_vec, tnapi);
11511 goto out_napi_fini;
11515 tg3_full_lock(tp, 0);
11518 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
11520 err = tg3_init_hw(tp, reset_phy);
11522 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11523 tg3_free_rings(tp);
11526 tg3_full_unlock(tp);
11531 if (test_irq && tg3_flag(tp, USING_MSI)) {
11532 err = tg3_test_msi(tp);
11535 tg3_full_lock(tp, 0);
11536 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11537 tg3_free_rings(tp);
11538 tg3_full_unlock(tp);
11540 goto out_napi_fini;
11543 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) {
11544 u32 val = tr32(PCIE_TRANSACTION_CFG);
11546 tw32(PCIE_TRANSACTION_CFG,
11547 val | PCIE_TRANS_CFG_1SHOT_MSI);
11553 tg3_hwmon_open(tp);
11555 tg3_full_lock(tp, 0);
11557 tg3_timer_start(tp);
11558 tg3_flag_set(tp, INIT_COMPLETE);
11559 tg3_enable_ints(tp);
11564 tg3_ptp_resume(tp);
11567 tg3_full_unlock(tp);
11569 netif_tx_start_all_queues(dev);
11572 * Reset loopback feature if it was turned on while the device was down
11573 * make sure that it's installed properly now.
11575 if (dev->features & NETIF_F_LOOPBACK)
11576 tg3_set_loopback(dev, dev->features);
11581 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11582 struct tg3_napi *tnapi = &tp->napi[i];
11583 free_irq(tnapi->irq_vec, tnapi);
11587 tg3_napi_disable(tp);
11589 tg3_free_consistent(tp);
11597 static void tg3_stop(struct tg3 *tp)
11601 tg3_reset_task_cancel(tp);
11602 tg3_netif_stop(tp);
11604 tg3_timer_stop(tp);
11606 tg3_hwmon_close(tp);
11610 tg3_full_lock(tp, 1);
11612 tg3_disable_ints(tp);
11614 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11615 tg3_free_rings(tp);
11616 tg3_flag_clear(tp, INIT_COMPLETE);
11618 tg3_full_unlock(tp);
11620 for (i = tp->irq_cnt - 1; i >= 0; i--) {
11621 struct tg3_napi *tnapi = &tp->napi[i];
11622 free_irq(tnapi->irq_vec, tnapi);
11629 tg3_free_consistent(tp);
11632 static int tg3_open(struct net_device *dev)
11634 struct tg3 *tp = netdev_priv(dev);
11637 if (tp->pcierr_recovery) {
11638 netdev_err(dev, "Failed to open device. PCI error recovery "
11643 if (tp->fw_needed) {
11644 err = tg3_request_firmware(tp);
11645 if (tg3_asic_rev(tp) == ASIC_REV_57766) {
11647 netdev_warn(tp->dev, "EEE capability disabled\n");
11648 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
11649 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
11650 netdev_warn(tp->dev, "EEE capability restored\n");
11651 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
11653 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) {
11657 netdev_warn(tp->dev, "TSO capability disabled\n");
11658 tg3_flag_clear(tp, TSO_CAPABLE);
11659 } else if (!tg3_flag(tp, TSO_CAPABLE)) {
11660 netdev_notice(tp->dev, "TSO capability restored\n");
11661 tg3_flag_set(tp, TSO_CAPABLE);
11665 tg3_carrier_off(tp);
11667 err = tg3_power_up(tp);
11671 tg3_full_lock(tp, 0);
11673 tg3_disable_ints(tp);
11674 tg3_flag_clear(tp, INIT_COMPLETE);
11676 tg3_full_unlock(tp);
11678 err = tg3_start(tp,
11679 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN),
11682 tg3_frob_aux_power(tp, false);
11683 pci_set_power_state(tp->pdev, PCI_D3hot);
11686 if (tg3_flag(tp, PTP_CAPABLE)) {
11687 tp->ptp_clock = ptp_clock_register(&tp->ptp_info,
11689 if (IS_ERR(tp->ptp_clock))
11690 tp->ptp_clock = NULL;
11696 static int tg3_close(struct net_device *dev)
11698 struct tg3 *tp = netdev_priv(dev);
11700 if (tp->pcierr_recovery) {
11701 netdev_err(dev, "Failed to close device. PCI error recovery "
11710 /* Clear stats across close / open calls */
11711 memset(&tp->net_stats_prev, 0, sizeof(tp->net_stats_prev));
11712 memset(&tp->estats_prev, 0, sizeof(tp->estats_prev));
11714 if (pci_device_is_present(tp->pdev)) {
11715 tg3_power_down_prepare(tp);
11717 tg3_carrier_off(tp);
11722 static inline u64 get_stat64(tg3_stat64_t *val)
11724 return ((u64)val->high << 32) | ((u64)val->low);
11727 static u64 tg3_calc_crc_errors(struct tg3 *tp)
11729 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11731 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
11732 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
11733 tg3_asic_rev(tp) == ASIC_REV_5701)) {
11736 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
11737 tg3_writephy(tp, MII_TG3_TEST1,
11738 val | MII_TG3_TEST1_CRC_EN);
11739 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val);
11743 tp->phy_crc_errors += val;
11745 return tp->phy_crc_errors;
11748 return get_stat64(&hw_stats->rx_fcs_errors);
11751 #define ESTAT_ADD(member) \
11752 estats->member = old_estats->member + \
11753 get_stat64(&hw_stats->member)
11755 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats)
11757 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
11758 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11760 ESTAT_ADD(rx_octets);
11761 ESTAT_ADD(rx_fragments);
11762 ESTAT_ADD(rx_ucast_packets);
11763 ESTAT_ADD(rx_mcast_packets);
11764 ESTAT_ADD(rx_bcast_packets);
11765 ESTAT_ADD(rx_fcs_errors);
11766 ESTAT_ADD(rx_align_errors);
11767 ESTAT_ADD(rx_xon_pause_rcvd);
11768 ESTAT_ADD(rx_xoff_pause_rcvd);
11769 ESTAT_ADD(rx_mac_ctrl_rcvd);
11770 ESTAT_ADD(rx_xoff_entered);
11771 ESTAT_ADD(rx_frame_too_long_errors);
11772 ESTAT_ADD(rx_jabbers);
11773 ESTAT_ADD(rx_undersize_packets);
11774 ESTAT_ADD(rx_in_length_errors);
11775 ESTAT_ADD(rx_out_length_errors);
11776 ESTAT_ADD(rx_64_or_less_octet_packets);
11777 ESTAT_ADD(rx_65_to_127_octet_packets);
11778 ESTAT_ADD(rx_128_to_255_octet_packets);
11779 ESTAT_ADD(rx_256_to_511_octet_packets);
11780 ESTAT_ADD(rx_512_to_1023_octet_packets);
11781 ESTAT_ADD(rx_1024_to_1522_octet_packets);
11782 ESTAT_ADD(rx_1523_to_2047_octet_packets);
11783 ESTAT_ADD(rx_2048_to_4095_octet_packets);
11784 ESTAT_ADD(rx_4096_to_8191_octet_packets);
11785 ESTAT_ADD(rx_8192_to_9022_octet_packets);
11787 ESTAT_ADD(tx_octets);
11788 ESTAT_ADD(tx_collisions);
11789 ESTAT_ADD(tx_xon_sent);
11790 ESTAT_ADD(tx_xoff_sent);
11791 ESTAT_ADD(tx_flow_control);
11792 ESTAT_ADD(tx_mac_errors);
11793 ESTAT_ADD(tx_single_collisions);
11794 ESTAT_ADD(tx_mult_collisions);
11795 ESTAT_ADD(tx_deferred);
11796 ESTAT_ADD(tx_excessive_collisions);
11797 ESTAT_ADD(tx_late_collisions);
11798 ESTAT_ADD(tx_collide_2times);
11799 ESTAT_ADD(tx_collide_3times);
11800 ESTAT_ADD(tx_collide_4times);
11801 ESTAT_ADD(tx_collide_5times);
11802 ESTAT_ADD(tx_collide_6times);
11803 ESTAT_ADD(tx_collide_7times);
11804 ESTAT_ADD(tx_collide_8times);
11805 ESTAT_ADD(tx_collide_9times);
11806 ESTAT_ADD(tx_collide_10times);
11807 ESTAT_ADD(tx_collide_11times);
11808 ESTAT_ADD(tx_collide_12times);
11809 ESTAT_ADD(tx_collide_13times);
11810 ESTAT_ADD(tx_collide_14times);
11811 ESTAT_ADD(tx_collide_15times);
11812 ESTAT_ADD(tx_ucast_packets);
11813 ESTAT_ADD(tx_mcast_packets);
11814 ESTAT_ADD(tx_bcast_packets);
11815 ESTAT_ADD(tx_carrier_sense_errors);
11816 ESTAT_ADD(tx_discards);
11817 ESTAT_ADD(tx_errors);
11819 ESTAT_ADD(dma_writeq_full);
11820 ESTAT_ADD(dma_write_prioq_full);
11821 ESTAT_ADD(rxbds_empty);
11822 ESTAT_ADD(rx_discards);
11823 ESTAT_ADD(rx_errors);
11824 ESTAT_ADD(rx_threshold_hit);
11826 ESTAT_ADD(dma_readq_full);
11827 ESTAT_ADD(dma_read_prioq_full);
11828 ESTAT_ADD(tx_comp_queue_full);
11830 ESTAT_ADD(ring_set_send_prod_index);
11831 ESTAT_ADD(ring_status_update);
11832 ESTAT_ADD(nic_irqs);
11833 ESTAT_ADD(nic_avoided_irqs);
11834 ESTAT_ADD(nic_tx_threshold_hit);
11836 ESTAT_ADD(mbuf_lwm_thresh_hit);
11839 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats)
11841 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev;
11842 struct tg3_hw_stats *hw_stats = tp->hw_stats;
11844 stats->rx_packets = old_stats->rx_packets +
11845 get_stat64(&hw_stats->rx_ucast_packets) +
11846 get_stat64(&hw_stats->rx_mcast_packets) +
11847 get_stat64(&hw_stats->rx_bcast_packets);
11849 stats->tx_packets = old_stats->tx_packets +
11850 get_stat64(&hw_stats->tx_ucast_packets) +
11851 get_stat64(&hw_stats->tx_mcast_packets) +
11852 get_stat64(&hw_stats->tx_bcast_packets);
11854 stats->rx_bytes = old_stats->rx_bytes +
11855 get_stat64(&hw_stats->rx_octets);
11856 stats->tx_bytes = old_stats->tx_bytes +
11857 get_stat64(&hw_stats->tx_octets);
11859 stats->rx_errors = old_stats->rx_errors +
11860 get_stat64(&hw_stats->rx_errors);
11861 stats->tx_errors = old_stats->tx_errors +
11862 get_stat64(&hw_stats->tx_errors) +
11863 get_stat64(&hw_stats->tx_mac_errors) +
11864 get_stat64(&hw_stats->tx_carrier_sense_errors) +
11865 get_stat64(&hw_stats->tx_discards);
11867 stats->multicast = old_stats->multicast +
11868 get_stat64(&hw_stats->rx_mcast_packets);
11869 stats->collisions = old_stats->collisions +
11870 get_stat64(&hw_stats->tx_collisions);
11872 stats->rx_length_errors = old_stats->rx_length_errors +
11873 get_stat64(&hw_stats->rx_frame_too_long_errors) +
11874 get_stat64(&hw_stats->rx_undersize_packets);
11876 stats->rx_frame_errors = old_stats->rx_frame_errors +
11877 get_stat64(&hw_stats->rx_align_errors);
11878 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
11879 get_stat64(&hw_stats->tx_discards);
11880 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
11881 get_stat64(&hw_stats->tx_carrier_sense_errors);
11883 stats->rx_crc_errors = old_stats->rx_crc_errors +
11884 tg3_calc_crc_errors(tp);
11886 stats->rx_missed_errors = old_stats->rx_missed_errors +
11887 get_stat64(&hw_stats->rx_discards);
11889 stats->rx_dropped = tp->rx_dropped;
11890 stats->tx_dropped = tp->tx_dropped;
11893 static int tg3_get_regs_len(struct net_device *dev)
11895 return TG3_REG_BLK_SIZE;
11898 static void tg3_get_regs(struct net_device *dev,
11899 struct ethtool_regs *regs, void *_p)
11901 struct tg3 *tp = netdev_priv(dev);
11905 memset(_p, 0, TG3_REG_BLK_SIZE);
11907 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
11910 tg3_full_lock(tp, 0);
11912 tg3_dump_legacy_regs(tp, (u32 *)_p);
11914 tg3_full_unlock(tp);
11917 static int tg3_get_eeprom_len(struct net_device *dev)
11919 struct tg3 *tp = netdev_priv(dev);
11921 return tp->nvram_size;
11924 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
11926 struct tg3 *tp = netdev_priv(dev);
11927 int ret, cpmu_restore = 0;
11929 u32 i, offset, len, b_offset, b_count, cpmu_val = 0;
11932 if (tg3_flag(tp, NO_NVRAM))
11935 offset = eeprom->offset;
11939 eeprom->magic = TG3_EEPROM_MAGIC;
11941 /* Override clock, link aware and link idle modes */
11942 if (tg3_flag(tp, CPMU_PRESENT)) {
11943 cpmu_val = tr32(TG3_CPMU_CTRL);
11944 if (cpmu_val & (CPMU_CTRL_LINK_AWARE_MODE |
11945 CPMU_CTRL_LINK_IDLE_MODE)) {
11946 tw32(TG3_CPMU_CTRL, cpmu_val &
11947 ~(CPMU_CTRL_LINK_AWARE_MODE |
11948 CPMU_CTRL_LINK_IDLE_MODE));
11952 tg3_override_clk(tp);
11955 /* adjustments to start on required 4 byte boundary */
11956 b_offset = offset & 3;
11957 b_count = 4 - b_offset;
11958 if (b_count > len) {
11959 /* i.e. offset=1 len=2 */
11962 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
11965 memcpy(data, ((char *)&val) + b_offset, b_count);
11968 eeprom->len += b_count;
11971 /* read bytes up to the last 4 byte boundary */
11972 pd = &data[eeprom->len];
11973 for (i = 0; i < (len - (len & 3)); i += 4) {
11974 ret = tg3_nvram_read_be32(tp, offset + i, &val);
11981 memcpy(pd + i, &val, 4);
11982 if (need_resched()) {
11983 if (signal_pending(current)) {
11994 /* read last bytes not ending on 4 byte boundary */
11995 pd = &data[eeprom->len];
11997 b_offset = offset + len - b_count;
11998 ret = tg3_nvram_read_be32(tp, b_offset, &val);
12001 memcpy(pd, &val, b_count);
12002 eeprom->len += b_count;
12007 /* Restore clock, link aware and link idle modes */
12008 tg3_restore_clk(tp);
12010 tw32(TG3_CPMU_CTRL, cpmu_val);
12015 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
12017 struct tg3 *tp = netdev_priv(dev);
12019 u32 offset, len, b_offset, odd_len;
12023 if (tg3_flag(tp, NO_NVRAM) ||
12024 eeprom->magic != TG3_EEPROM_MAGIC)
12027 offset = eeprom->offset;
12030 if ((b_offset = (offset & 3))) {
12031 /* adjustments to start on required 4 byte boundary */
12032 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
12043 /* adjustments to end on required 4 byte boundary */
12045 len = (len + 3) & ~3;
12046 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
12052 if (b_offset || odd_len) {
12053 buf = kmalloc(len, GFP_KERNEL);
12057 memcpy(buf, &start, 4);
12059 memcpy(buf+len-4, &end, 4);
12060 memcpy(buf + b_offset, data, eeprom->len);
12063 ret = tg3_nvram_write_block(tp, offset, len, buf);
12071 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12073 struct tg3 *tp = netdev_priv(dev);
12075 if (tg3_flag(tp, USE_PHYLIB)) {
12076 struct phy_device *phydev;
12077 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12079 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12080 return phy_ethtool_gset(phydev, cmd);
12083 cmd->supported = (SUPPORTED_Autoneg);
12085 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12086 cmd->supported |= (SUPPORTED_1000baseT_Half |
12087 SUPPORTED_1000baseT_Full);
12089 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12090 cmd->supported |= (SUPPORTED_100baseT_Half |
12091 SUPPORTED_100baseT_Full |
12092 SUPPORTED_10baseT_Half |
12093 SUPPORTED_10baseT_Full |
12095 cmd->port = PORT_TP;
12097 cmd->supported |= SUPPORTED_FIBRE;
12098 cmd->port = PORT_FIBRE;
12101 cmd->advertising = tp->link_config.advertising;
12102 if (tg3_flag(tp, PAUSE_AUTONEG)) {
12103 if (tp->link_config.flowctrl & FLOW_CTRL_RX) {
12104 if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12105 cmd->advertising |= ADVERTISED_Pause;
12107 cmd->advertising |= ADVERTISED_Pause |
12108 ADVERTISED_Asym_Pause;
12110 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) {
12111 cmd->advertising |= ADVERTISED_Asym_Pause;
12114 if (netif_running(dev) && tp->link_up) {
12115 ethtool_cmd_speed_set(cmd, tp->link_config.active_speed);
12116 cmd->duplex = tp->link_config.active_duplex;
12117 cmd->lp_advertising = tp->link_config.rmt_adv;
12118 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) {
12119 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE)
12120 cmd->eth_tp_mdix = ETH_TP_MDI_X;
12122 cmd->eth_tp_mdix = ETH_TP_MDI;
12125 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
12126 cmd->duplex = DUPLEX_UNKNOWN;
12127 cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
12129 cmd->phy_address = tp->phy_addr;
12130 cmd->transceiver = XCVR_INTERNAL;
12131 cmd->autoneg = tp->link_config.autoneg;
12137 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
12139 struct tg3 *tp = netdev_priv(dev);
12140 u32 speed = ethtool_cmd_speed(cmd);
12142 if (tg3_flag(tp, USE_PHYLIB)) {
12143 struct phy_device *phydev;
12144 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12146 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12147 return phy_ethtool_sset(phydev, cmd);
12150 if (cmd->autoneg != AUTONEG_ENABLE &&
12151 cmd->autoneg != AUTONEG_DISABLE)
12154 if (cmd->autoneg == AUTONEG_DISABLE &&
12155 cmd->duplex != DUPLEX_FULL &&
12156 cmd->duplex != DUPLEX_HALF)
12159 if (cmd->autoneg == AUTONEG_ENABLE) {
12160 u32 mask = ADVERTISED_Autoneg |
12162 ADVERTISED_Asym_Pause;
12164 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
12165 mask |= ADVERTISED_1000baseT_Half |
12166 ADVERTISED_1000baseT_Full;
12168 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
12169 mask |= ADVERTISED_100baseT_Half |
12170 ADVERTISED_100baseT_Full |
12171 ADVERTISED_10baseT_Half |
12172 ADVERTISED_10baseT_Full |
12175 mask |= ADVERTISED_FIBRE;
12177 if (cmd->advertising & ~mask)
12180 mask &= (ADVERTISED_1000baseT_Half |
12181 ADVERTISED_1000baseT_Full |
12182 ADVERTISED_100baseT_Half |
12183 ADVERTISED_100baseT_Full |
12184 ADVERTISED_10baseT_Half |
12185 ADVERTISED_10baseT_Full);
12187 cmd->advertising &= mask;
12189 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) {
12190 if (speed != SPEED_1000)
12193 if (cmd->duplex != DUPLEX_FULL)
12196 if (speed != SPEED_100 &&
12202 tg3_full_lock(tp, 0);
12204 tp->link_config.autoneg = cmd->autoneg;
12205 if (cmd->autoneg == AUTONEG_ENABLE) {
12206 tp->link_config.advertising = (cmd->advertising |
12207 ADVERTISED_Autoneg);
12208 tp->link_config.speed = SPEED_UNKNOWN;
12209 tp->link_config.duplex = DUPLEX_UNKNOWN;
12211 tp->link_config.advertising = 0;
12212 tp->link_config.speed = speed;
12213 tp->link_config.duplex = cmd->duplex;
12216 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12218 tg3_warn_mgmt_link_flap(tp);
12220 if (netif_running(dev))
12221 tg3_setup_phy(tp, true);
12223 tg3_full_unlock(tp);
12228 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
12230 struct tg3 *tp = netdev_priv(dev);
12232 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
12233 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
12234 strlcpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version));
12235 strlcpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info));
12238 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12240 struct tg3 *tp = netdev_priv(dev);
12242 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev))
12243 wol->supported = WAKE_MAGIC;
12245 wol->supported = 0;
12247 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev))
12248 wol->wolopts = WAKE_MAGIC;
12249 memset(&wol->sopass, 0, sizeof(wol->sopass));
12252 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
12254 struct tg3 *tp = netdev_priv(dev);
12255 struct device *dp = &tp->pdev->dev;
12257 if (wol->wolopts & ~WAKE_MAGIC)
12259 if ((wol->wolopts & WAKE_MAGIC) &&
12260 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp)))
12263 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC);
12265 if (device_may_wakeup(dp))
12266 tg3_flag_set(tp, WOL_ENABLE);
12268 tg3_flag_clear(tp, WOL_ENABLE);
12273 static u32 tg3_get_msglevel(struct net_device *dev)
12275 struct tg3 *tp = netdev_priv(dev);
12276 return tp->msg_enable;
12279 static void tg3_set_msglevel(struct net_device *dev, u32 value)
12281 struct tg3 *tp = netdev_priv(dev);
12282 tp->msg_enable = value;
12285 static int tg3_nway_reset(struct net_device *dev)
12287 struct tg3 *tp = netdev_priv(dev);
12290 if (!netif_running(dev))
12293 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
12296 tg3_warn_mgmt_link_flap(tp);
12298 if (tg3_flag(tp, USE_PHYLIB)) {
12299 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
12301 r = phy_start_aneg(tp->mdio_bus->phy_map[tp->phy_addr]);
12305 spin_lock_bh(&tp->lock);
12307 tg3_readphy(tp, MII_BMCR, &bmcr);
12308 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
12309 ((bmcr & BMCR_ANENABLE) ||
12310 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) {
12311 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
12315 spin_unlock_bh(&tp->lock);
12321 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12323 struct tg3 *tp = netdev_priv(dev);
12325 ering->rx_max_pending = tp->rx_std_ring_mask;
12326 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12327 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask;
12329 ering->rx_jumbo_max_pending = 0;
12331 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
12333 ering->rx_pending = tp->rx_pending;
12334 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12335 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
12337 ering->rx_jumbo_pending = 0;
12339 ering->tx_pending = tp->napi[0].tx_pending;
12342 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
12344 struct tg3 *tp = netdev_priv(dev);
12345 int i, irq_sync = 0, err = 0;
12347 if ((ering->rx_pending > tp->rx_std_ring_mask) ||
12348 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) ||
12349 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
12350 (ering->tx_pending <= MAX_SKB_FRAGS) ||
12351 (tg3_flag(tp, TSO_BUG) &&
12352 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
12355 if (netif_running(dev)) {
12357 tg3_netif_stop(tp);
12361 tg3_full_lock(tp, irq_sync);
12363 tp->rx_pending = ering->rx_pending;
12365 if (tg3_flag(tp, MAX_RXPEND_64) &&
12366 tp->rx_pending > 63)
12367 tp->rx_pending = 63;
12369 if (tg3_flag(tp, JUMBO_RING_ENABLE))
12370 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
12372 for (i = 0; i < tp->irq_max; i++)
12373 tp->napi[i].tx_pending = ering->tx_pending;
12375 if (netif_running(dev)) {
12376 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12377 err = tg3_restart_hw(tp, false);
12379 tg3_netif_start(tp);
12382 tg3_full_unlock(tp);
12384 if (irq_sync && !err)
12390 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12392 struct tg3 *tp = netdev_priv(dev);
12394 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG);
12396 if (tp->link_config.flowctrl & FLOW_CTRL_RX)
12397 epause->rx_pause = 1;
12399 epause->rx_pause = 0;
12401 if (tp->link_config.flowctrl & FLOW_CTRL_TX)
12402 epause->tx_pause = 1;
12404 epause->tx_pause = 0;
12407 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
12409 struct tg3 *tp = netdev_priv(dev);
12412 if (tp->link_config.autoneg == AUTONEG_ENABLE)
12413 tg3_warn_mgmt_link_flap(tp);
12415 if (tg3_flag(tp, USE_PHYLIB)) {
12417 struct phy_device *phydev;
12419 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
12421 if (!(phydev->supported & SUPPORTED_Pause) ||
12422 (!(phydev->supported & SUPPORTED_Asym_Pause) &&
12423 (epause->rx_pause != epause->tx_pause)))
12426 tp->link_config.flowctrl = 0;
12427 if (epause->rx_pause) {
12428 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12430 if (epause->tx_pause) {
12431 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12432 newadv = ADVERTISED_Pause;
12434 newadv = ADVERTISED_Pause |
12435 ADVERTISED_Asym_Pause;
12436 } else if (epause->tx_pause) {
12437 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12438 newadv = ADVERTISED_Asym_Pause;
12442 if (epause->autoneg)
12443 tg3_flag_set(tp, PAUSE_AUTONEG);
12445 tg3_flag_clear(tp, PAUSE_AUTONEG);
12447 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
12448 u32 oldadv = phydev->advertising &
12449 (ADVERTISED_Pause | ADVERTISED_Asym_Pause);
12450 if (oldadv != newadv) {
12451 phydev->advertising &=
12452 ~(ADVERTISED_Pause |
12453 ADVERTISED_Asym_Pause);
12454 phydev->advertising |= newadv;
12455 if (phydev->autoneg) {
12457 * Always renegotiate the link to
12458 * inform our link partner of our
12459 * flow control settings, even if the
12460 * flow control is forced. Let
12461 * tg3_adjust_link() do the final
12462 * flow control setup.
12464 return phy_start_aneg(phydev);
12468 if (!epause->autoneg)
12469 tg3_setup_flow_control(tp, 0, 0);
12471 tp->link_config.advertising &=
12472 ~(ADVERTISED_Pause |
12473 ADVERTISED_Asym_Pause);
12474 tp->link_config.advertising |= newadv;
12479 if (netif_running(dev)) {
12480 tg3_netif_stop(tp);
12484 tg3_full_lock(tp, irq_sync);
12486 if (epause->autoneg)
12487 tg3_flag_set(tp, PAUSE_AUTONEG);
12489 tg3_flag_clear(tp, PAUSE_AUTONEG);
12490 if (epause->rx_pause)
12491 tp->link_config.flowctrl |= FLOW_CTRL_RX;
12493 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
12494 if (epause->tx_pause)
12495 tp->link_config.flowctrl |= FLOW_CTRL_TX;
12497 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
12499 if (netif_running(dev)) {
12500 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12501 err = tg3_restart_hw(tp, false);
12503 tg3_netif_start(tp);
12506 tg3_full_unlock(tp);
12509 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
12514 static int tg3_get_sset_count(struct net_device *dev, int sset)
12518 return TG3_NUM_TEST;
12520 return TG3_NUM_STATS;
12522 return -EOPNOTSUPP;
12526 static int tg3_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
12527 u32 *rules __always_unused)
12529 struct tg3 *tp = netdev_priv(dev);
12531 if (!tg3_flag(tp, SUPPORT_MSIX))
12532 return -EOPNOTSUPP;
12534 switch (info->cmd) {
12535 case ETHTOOL_GRXRINGS:
12536 if (netif_running(tp->dev))
12537 info->data = tp->rxq_cnt;
12539 info->data = num_online_cpus();
12540 if (info->data > TG3_RSS_MAX_NUM_QS)
12541 info->data = TG3_RSS_MAX_NUM_QS;
12544 /* The first interrupt vector only
12545 * handles link interrupts.
12551 return -EOPNOTSUPP;
12555 static u32 tg3_get_rxfh_indir_size(struct net_device *dev)
12558 struct tg3 *tp = netdev_priv(dev);
12560 if (tg3_flag(tp, SUPPORT_MSIX))
12561 size = TG3_RSS_INDIR_TBL_SIZE;
12566 static int tg3_get_rxfh(struct net_device *dev, u32 *indir, u8 *key)
12568 struct tg3 *tp = netdev_priv(dev);
12571 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12572 indir[i] = tp->rss_ind_tbl[i];
12577 static int tg3_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key)
12579 struct tg3 *tp = netdev_priv(dev);
12582 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++)
12583 tp->rss_ind_tbl[i] = indir[i];
12585 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS))
12588 /* It is legal to write the indirection
12589 * table while the device is running.
12591 tg3_full_lock(tp, 0);
12592 tg3_rss_write_indir_tbl(tp);
12593 tg3_full_unlock(tp);
12598 static void tg3_get_channels(struct net_device *dev,
12599 struct ethtool_channels *channel)
12601 struct tg3 *tp = netdev_priv(dev);
12602 u32 deflt_qs = netif_get_num_default_rss_queues();
12604 channel->max_rx = tp->rxq_max;
12605 channel->max_tx = tp->txq_max;
12607 if (netif_running(dev)) {
12608 channel->rx_count = tp->rxq_cnt;
12609 channel->tx_count = tp->txq_cnt;
12612 channel->rx_count = tp->rxq_req;
12614 channel->rx_count = min(deflt_qs, tp->rxq_max);
12617 channel->tx_count = tp->txq_req;
12619 channel->tx_count = min(deflt_qs, tp->txq_max);
12623 static int tg3_set_channels(struct net_device *dev,
12624 struct ethtool_channels *channel)
12626 struct tg3 *tp = netdev_priv(dev);
12628 if (!tg3_flag(tp, SUPPORT_MSIX))
12629 return -EOPNOTSUPP;
12631 if (channel->rx_count > tp->rxq_max ||
12632 channel->tx_count > tp->txq_max)
12635 tp->rxq_req = channel->rx_count;
12636 tp->txq_req = channel->tx_count;
12638 if (!netif_running(dev))
12643 tg3_carrier_off(tp);
12645 tg3_start(tp, true, false, false);
12650 static void tg3_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
12652 switch (stringset) {
12654 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
12657 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
12660 WARN_ON(1); /* we need a WARN() */
12665 static int tg3_set_phys_id(struct net_device *dev,
12666 enum ethtool_phys_id_state state)
12668 struct tg3 *tp = netdev_priv(dev);
12670 if (!netif_running(tp->dev))
12674 case ETHTOOL_ID_ACTIVE:
12675 return 1; /* cycle on/off once per second */
12677 case ETHTOOL_ID_ON:
12678 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12679 LED_CTRL_1000MBPS_ON |
12680 LED_CTRL_100MBPS_ON |
12681 LED_CTRL_10MBPS_ON |
12682 LED_CTRL_TRAFFIC_OVERRIDE |
12683 LED_CTRL_TRAFFIC_BLINK |
12684 LED_CTRL_TRAFFIC_LED);
12687 case ETHTOOL_ID_OFF:
12688 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
12689 LED_CTRL_TRAFFIC_OVERRIDE);
12692 case ETHTOOL_ID_INACTIVE:
12693 tw32(MAC_LED_CTRL, tp->led_ctrl);
12700 static void tg3_get_ethtool_stats(struct net_device *dev,
12701 struct ethtool_stats *estats, u64 *tmp_stats)
12703 struct tg3 *tp = netdev_priv(dev);
12706 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats);
12708 memset(tmp_stats, 0, sizeof(struct tg3_ethtool_stats));
12711 static __be32 *tg3_vpd_readblock(struct tg3 *tp, u32 *vpdlen)
12715 u32 offset = 0, len = 0;
12718 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic))
12721 if (magic == TG3_EEPROM_MAGIC) {
12722 for (offset = TG3_NVM_DIR_START;
12723 offset < TG3_NVM_DIR_END;
12724 offset += TG3_NVM_DIRENT_SIZE) {
12725 if (tg3_nvram_read(tp, offset, &val))
12728 if ((val >> TG3_NVM_DIRTYPE_SHIFT) ==
12729 TG3_NVM_DIRTYPE_EXTVPD)
12733 if (offset != TG3_NVM_DIR_END) {
12734 len = (val & TG3_NVM_DIRTYPE_LENMSK) * 4;
12735 if (tg3_nvram_read(tp, offset + 4, &offset))
12738 offset = tg3_nvram_logical_addr(tp, offset);
12742 if (!offset || !len) {
12743 offset = TG3_NVM_VPD_OFF;
12744 len = TG3_NVM_VPD_LEN;
12747 buf = kmalloc(len, GFP_KERNEL);
12751 if (magic == TG3_EEPROM_MAGIC) {
12752 for (i = 0; i < len; i += 4) {
12753 /* The data is in little-endian format in NVRAM.
12754 * Use the big-endian read routines to preserve
12755 * the byte order as it exists in NVRAM.
12757 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4]))
12763 unsigned int pos = 0;
12765 ptr = (u8 *)&buf[0];
12766 for (i = 0; pos < len && i < 3; i++, pos += cnt, ptr += cnt) {
12767 cnt = pci_read_vpd(tp->pdev, pos,
12769 if (cnt == -ETIMEDOUT || cnt == -EINTR)
12787 #define NVRAM_TEST_SIZE 0x100
12788 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12789 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12790 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12791 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12792 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12793 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12794 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12795 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12797 static int tg3_test_nvram(struct tg3 *tp)
12799 u32 csum, magic, len;
12801 int i, j, k, err = 0, size;
12803 if (tg3_flag(tp, NO_NVRAM))
12806 if (tg3_nvram_read(tp, 0, &magic) != 0)
12809 if (magic == TG3_EEPROM_MAGIC)
12810 size = NVRAM_TEST_SIZE;
12811 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
12812 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
12813 TG3_EEPROM_SB_FORMAT_1) {
12814 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
12815 case TG3_EEPROM_SB_REVISION_0:
12816 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
12818 case TG3_EEPROM_SB_REVISION_2:
12819 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
12821 case TG3_EEPROM_SB_REVISION_3:
12822 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
12824 case TG3_EEPROM_SB_REVISION_4:
12825 size = NVRAM_SELFBOOT_FORMAT1_4_SIZE;
12827 case TG3_EEPROM_SB_REVISION_5:
12828 size = NVRAM_SELFBOOT_FORMAT1_5_SIZE;
12830 case TG3_EEPROM_SB_REVISION_6:
12831 size = NVRAM_SELFBOOT_FORMAT1_6_SIZE;
12838 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12839 size = NVRAM_SELFBOOT_HW_SIZE;
12843 buf = kmalloc(size, GFP_KERNEL);
12848 for (i = 0, j = 0; i < size; i += 4, j++) {
12849 err = tg3_nvram_read_be32(tp, i, &buf[j]);
12856 /* Selfboot format */
12857 magic = be32_to_cpu(buf[0]);
12858 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
12859 TG3_EEPROM_MAGIC_FW) {
12860 u8 *buf8 = (u8 *) buf, csum8 = 0;
12862 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
12863 TG3_EEPROM_SB_REVISION_2) {
12864 /* For rev 2, the csum doesn't include the MBA. */
12865 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
12867 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
12870 for (i = 0; i < size; i++)
12883 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
12884 TG3_EEPROM_MAGIC_HW) {
12885 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
12886 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
12887 u8 *buf8 = (u8 *) buf;
12889 /* Separate the parity bits and the data bytes. */
12890 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
12891 if ((i == 0) || (i == 8)) {
12895 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
12896 parity[k++] = buf8[i] & msk;
12898 } else if (i == 16) {
12902 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
12903 parity[k++] = buf8[i] & msk;
12906 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
12907 parity[k++] = buf8[i] & msk;
12910 data[j++] = buf8[i];
12914 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
12915 u8 hw8 = hweight8(data[i]);
12917 if ((hw8 & 0x1) && parity[i])
12919 else if (!(hw8 & 0x1) && !parity[i])
12928 /* Bootstrap checksum at offset 0x10 */
12929 csum = calc_crc((unsigned char *) buf, 0x10);
12930 if (csum != le32_to_cpu(buf[0x10/4]))
12933 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12934 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
12935 if (csum != le32_to_cpu(buf[0xfc/4]))
12940 buf = tg3_vpd_readblock(tp, &len);
12944 i = pci_vpd_find_tag((u8 *)buf, 0, len, PCI_VPD_LRDT_RO_DATA);
12946 j = pci_vpd_lrdt_size(&((u8 *)buf)[i]);
12950 if (i + PCI_VPD_LRDT_TAG_SIZE + j > len)
12953 i += PCI_VPD_LRDT_TAG_SIZE;
12954 j = pci_vpd_find_info_keyword((u8 *)buf, i, j,
12955 PCI_VPD_RO_KEYWORD_CHKSUM);
12959 j += PCI_VPD_INFO_FLD_HDR_SIZE;
12961 for (i = 0; i <= j; i++)
12962 csum8 += ((u8 *)buf)[i];
12976 #define TG3_SERDES_TIMEOUT_SEC 2
12977 #define TG3_COPPER_TIMEOUT_SEC 6
12979 static int tg3_test_link(struct tg3 *tp)
12983 if (!netif_running(tp->dev))
12986 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
12987 max = TG3_SERDES_TIMEOUT_SEC;
12989 max = TG3_COPPER_TIMEOUT_SEC;
12991 for (i = 0; i < max; i++) {
12995 if (msleep_interruptible(1000))
13002 /* Only test the commonly used registers */
13003 static int tg3_test_registers(struct tg3 *tp)
13005 int i, is_5705, is_5750;
13006 u32 offset, read_mask, write_mask, val, save_val, read_val;
13010 #define TG3_FL_5705 0x1
13011 #define TG3_FL_NOT_5705 0x2
13012 #define TG3_FL_NOT_5788 0x4
13013 #define TG3_FL_NOT_5750 0x8
13017 /* MAC Control Registers */
13018 { MAC_MODE, TG3_FL_NOT_5705,
13019 0x00000000, 0x00ef6f8c },
13020 { MAC_MODE, TG3_FL_5705,
13021 0x00000000, 0x01ef6b8c },
13022 { MAC_STATUS, TG3_FL_NOT_5705,
13023 0x03800107, 0x00000000 },
13024 { MAC_STATUS, TG3_FL_5705,
13025 0x03800100, 0x00000000 },
13026 { MAC_ADDR_0_HIGH, 0x0000,
13027 0x00000000, 0x0000ffff },
13028 { MAC_ADDR_0_LOW, 0x0000,
13029 0x00000000, 0xffffffff },
13030 { MAC_RX_MTU_SIZE, 0x0000,
13031 0x00000000, 0x0000ffff },
13032 { MAC_TX_MODE, 0x0000,
13033 0x00000000, 0x00000070 },
13034 { MAC_TX_LENGTHS, 0x0000,
13035 0x00000000, 0x00003fff },
13036 { MAC_RX_MODE, TG3_FL_NOT_5705,
13037 0x00000000, 0x000007fc },
13038 { MAC_RX_MODE, TG3_FL_5705,
13039 0x00000000, 0x000007dc },
13040 { MAC_HASH_REG_0, 0x0000,
13041 0x00000000, 0xffffffff },
13042 { MAC_HASH_REG_1, 0x0000,
13043 0x00000000, 0xffffffff },
13044 { MAC_HASH_REG_2, 0x0000,
13045 0x00000000, 0xffffffff },
13046 { MAC_HASH_REG_3, 0x0000,
13047 0x00000000, 0xffffffff },
13049 /* Receive Data and Receive BD Initiator Control Registers. */
13050 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
13051 0x00000000, 0xffffffff },
13052 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
13053 0x00000000, 0xffffffff },
13054 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
13055 0x00000000, 0x00000003 },
13056 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
13057 0x00000000, 0xffffffff },
13058 { RCVDBDI_STD_BD+0, 0x0000,
13059 0x00000000, 0xffffffff },
13060 { RCVDBDI_STD_BD+4, 0x0000,
13061 0x00000000, 0xffffffff },
13062 { RCVDBDI_STD_BD+8, 0x0000,
13063 0x00000000, 0xffff0002 },
13064 { RCVDBDI_STD_BD+0xc, 0x0000,
13065 0x00000000, 0xffffffff },
13067 /* Receive BD Initiator Control Registers. */
13068 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
13069 0x00000000, 0xffffffff },
13070 { RCVBDI_STD_THRESH, TG3_FL_5705,
13071 0x00000000, 0x000003ff },
13072 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
13073 0x00000000, 0xffffffff },
13075 /* Host Coalescing Control Registers. */
13076 { HOSTCC_MODE, TG3_FL_NOT_5705,
13077 0x00000000, 0x00000004 },
13078 { HOSTCC_MODE, TG3_FL_5705,
13079 0x00000000, 0x000000f6 },
13080 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
13081 0x00000000, 0xffffffff },
13082 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
13083 0x00000000, 0x000003ff },
13084 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
13085 0x00000000, 0xffffffff },
13086 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
13087 0x00000000, 0x000003ff },
13088 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
13089 0x00000000, 0xffffffff },
13090 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13091 0x00000000, 0x000000ff },
13092 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
13093 0x00000000, 0xffffffff },
13094 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
13095 0x00000000, 0x000000ff },
13096 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
13097 0x00000000, 0xffffffff },
13098 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
13099 0x00000000, 0xffffffff },
13100 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13101 0x00000000, 0xffffffff },
13102 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13103 0x00000000, 0x000000ff },
13104 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
13105 0x00000000, 0xffffffff },
13106 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
13107 0x00000000, 0x000000ff },
13108 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
13109 0x00000000, 0xffffffff },
13110 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
13111 0x00000000, 0xffffffff },
13112 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
13113 0x00000000, 0xffffffff },
13114 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
13115 0x00000000, 0xffffffff },
13116 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
13117 0x00000000, 0xffffffff },
13118 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
13119 0xffffffff, 0x00000000 },
13120 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
13121 0xffffffff, 0x00000000 },
13123 /* Buffer Manager Control Registers. */
13124 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
13125 0x00000000, 0x007fff80 },
13126 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
13127 0x00000000, 0x007fffff },
13128 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
13129 0x00000000, 0x0000003f },
13130 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
13131 0x00000000, 0x000001ff },
13132 { BUFMGR_MB_HIGH_WATER, 0x0000,
13133 0x00000000, 0x000001ff },
13134 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
13135 0xffffffff, 0x00000000 },
13136 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
13137 0xffffffff, 0x00000000 },
13139 /* Mailbox Registers */
13140 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
13141 0x00000000, 0x000001ff },
13142 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
13143 0x00000000, 0x000001ff },
13144 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
13145 0x00000000, 0x000007ff },
13146 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
13147 0x00000000, 0x000001ff },
13149 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
13152 is_5705 = is_5750 = 0;
13153 if (tg3_flag(tp, 5705_PLUS)) {
13155 if (tg3_flag(tp, 5750_PLUS))
13159 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
13160 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
13163 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
13166 if (tg3_flag(tp, IS_5788) &&
13167 (reg_tbl[i].flags & TG3_FL_NOT_5788))
13170 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
13173 offset = (u32) reg_tbl[i].offset;
13174 read_mask = reg_tbl[i].read_mask;
13175 write_mask = reg_tbl[i].write_mask;
13177 /* Save the original register content */
13178 save_val = tr32(offset);
13180 /* Determine the read-only value. */
13181 read_val = save_val & read_mask;
13183 /* Write zero to the register, then make sure the read-only bits
13184 * are not changed and the read/write bits are all zeros.
13188 val = tr32(offset);
13190 /* Test the read-only and read/write bits. */
13191 if (((val & read_mask) != read_val) || (val & write_mask))
13194 /* Write ones to all the bits defined by RdMask and WrMask, then
13195 * make sure the read-only bits are not changed and the
13196 * read/write bits are all ones.
13198 tw32(offset, read_mask | write_mask);
13200 val = tr32(offset);
13202 /* Test the read-only bits. */
13203 if ((val & read_mask) != read_val)
13206 /* Test the read/write bits. */
13207 if ((val & write_mask) != write_mask)
13210 tw32(offset, save_val);
13216 if (netif_msg_hw(tp))
13217 netdev_err(tp->dev,
13218 "Register test failed at offset %x\n", offset);
13219 tw32(offset, save_val);
13223 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
13225 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
13229 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
13230 for (j = 0; j < len; j += 4) {
13233 tg3_write_mem(tp, offset + j, test_pattern[i]);
13234 tg3_read_mem(tp, offset + j, &val);
13235 if (val != test_pattern[i])
13242 static int tg3_test_memory(struct tg3 *tp)
13244 static struct mem_entry {
13247 } mem_tbl_570x[] = {
13248 { 0x00000000, 0x00b50},
13249 { 0x00002000, 0x1c000},
13250 { 0xffffffff, 0x00000}
13251 }, mem_tbl_5705[] = {
13252 { 0x00000100, 0x0000c},
13253 { 0x00000200, 0x00008},
13254 { 0x00004000, 0x00800},
13255 { 0x00006000, 0x01000},
13256 { 0x00008000, 0x02000},
13257 { 0x00010000, 0x0e000},
13258 { 0xffffffff, 0x00000}
13259 }, mem_tbl_5755[] = {
13260 { 0x00000200, 0x00008},
13261 { 0x00004000, 0x00800},
13262 { 0x00006000, 0x00800},
13263 { 0x00008000, 0x02000},
13264 { 0x00010000, 0x0c000},
13265 { 0xffffffff, 0x00000}
13266 }, mem_tbl_5906[] = {
13267 { 0x00000200, 0x00008},
13268 { 0x00004000, 0x00400},
13269 { 0x00006000, 0x00400},
13270 { 0x00008000, 0x01000},
13271 { 0x00010000, 0x01000},
13272 { 0xffffffff, 0x00000}
13273 }, mem_tbl_5717[] = {
13274 { 0x00000200, 0x00008},
13275 { 0x00010000, 0x0a000},
13276 { 0x00020000, 0x13c00},
13277 { 0xffffffff, 0x00000}
13278 }, mem_tbl_57765[] = {
13279 { 0x00000200, 0x00008},
13280 { 0x00004000, 0x00800},
13281 { 0x00006000, 0x09800},
13282 { 0x00010000, 0x0a000},
13283 { 0xffffffff, 0x00000}
13285 struct mem_entry *mem_tbl;
13289 if (tg3_flag(tp, 5717_PLUS))
13290 mem_tbl = mem_tbl_5717;
13291 else if (tg3_flag(tp, 57765_CLASS) ||
13292 tg3_asic_rev(tp) == ASIC_REV_5762)
13293 mem_tbl = mem_tbl_57765;
13294 else if (tg3_flag(tp, 5755_PLUS))
13295 mem_tbl = mem_tbl_5755;
13296 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
13297 mem_tbl = mem_tbl_5906;
13298 else if (tg3_flag(tp, 5705_PLUS))
13299 mem_tbl = mem_tbl_5705;
13301 mem_tbl = mem_tbl_570x;
13303 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
13304 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len);
13312 #define TG3_TSO_MSS 500
13314 #define TG3_TSO_IP_HDR_LEN 20
13315 #define TG3_TSO_TCP_HDR_LEN 20
13316 #define TG3_TSO_TCP_OPT_LEN 12
13318 static const u8 tg3_tso_header[] = {
13320 0x45, 0x00, 0x00, 0x00,
13321 0x00, 0x00, 0x40, 0x00,
13322 0x40, 0x06, 0x00, 0x00,
13323 0x0a, 0x00, 0x00, 0x01,
13324 0x0a, 0x00, 0x00, 0x02,
13325 0x0d, 0x00, 0xe0, 0x00,
13326 0x00, 0x00, 0x01, 0x00,
13327 0x00, 0x00, 0x02, 0x00,
13328 0x80, 0x10, 0x10, 0x00,
13329 0x14, 0x09, 0x00, 0x00,
13330 0x01, 0x01, 0x08, 0x0a,
13331 0x11, 0x11, 0x11, 0x11,
13332 0x11, 0x11, 0x11, 0x11,
13335 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback)
13337 u32 rx_start_idx, rx_idx, tx_idx, opaque_key;
13338 u32 base_flags = 0, mss = 0, desc_idx, coal_now, data_off, val;
13340 struct sk_buff *skb;
13341 u8 *tx_data, *rx_data;
13343 int num_pkts, tx_len, rx_len, i, err;
13344 struct tg3_rx_buffer_desc *desc;
13345 struct tg3_napi *tnapi, *rnapi;
13346 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring;
13348 tnapi = &tp->napi[0];
13349 rnapi = &tp->napi[0];
13350 if (tp->irq_cnt > 1) {
13351 if (tg3_flag(tp, ENABLE_RSS))
13352 rnapi = &tp->napi[1];
13353 if (tg3_flag(tp, ENABLE_TSS))
13354 tnapi = &tp->napi[1];
13356 coal_now = tnapi->coal_now | rnapi->coal_now;
13361 skb = netdev_alloc_skb(tp->dev, tx_len);
13365 tx_data = skb_put(skb, tx_len);
13366 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN);
13367 memset(tx_data + ETH_ALEN, 0x0, 8);
13369 tw32(MAC_RX_MTU_SIZE, tx_len + ETH_FCS_LEN);
13371 if (tso_loopback) {
13372 struct iphdr *iph = (struct iphdr *)&tx_data[ETH_HLEN];
13374 u32 hdr_len = TG3_TSO_IP_HDR_LEN + TG3_TSO_TCP_HDR_LEN +
13375 TG3_TSO_TCP_OPT_LEN;
13377 memcpy(tx_data + ETH_ALEN * 2, tg3_tso_header,
13378 sizeof(tg3_tso_header));
13381 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header);
13382 num_pkts = DIV_ROUND_UP(val, TG3_TSO_MSS);
13384 /* Set the total length field in the IP header */
13385 iph->tot_len = htons((u16)(mss + hdr_len));
13387 base_flags = (TXD_FLAG_CPU_PRE_DMA |
13388 TXD_FLAG_CPU_POST_DMA);
13390 if (tg3_flag(tp, HW_TSO_1) ||
13391 tg3_flag(tp, HW_TSO_2) ||
13392 tg3_flag(tp, HW_TSO_3)) {
13394 val = ETH_HLEN + TG3_TSO_IP_HDR_LEN;
13395 th = (struct tcphdr *)&tx_data[val];
13398 base_flags |= TXD_FLAG_TCPUDP_CSUM;
13400 if (tg3_flag(tp, HW_TSO_3)) {
13401 mss |= (hdr_len & 0xc) << 12;
13402 if (hdr_len & 0x10)
13403 base_flags |= 0x00000010;
13404 base_flags |= (hdr_len & 0x3e0) << 5;
13405 } else if (tg3_flag(tp, HW_TSO_2))
13406 mss |= hdr_len << 9;
13407 else if (tg3_flag(tp, HW_TSO_1) ||
13408 tg3_asic_rev(tp) == ASIC_REV_5705) {
13409 mss |= (TG3_TSO_TCP_OPT_LEN << 9);
13411 base_flags |= (TG3_TSO_TCP_OPT_LEN << 10);
13414 data_off = ETH_ALEN * 2 + sizeof(tg3_tso_header);
13417 data_off = ETH_HLEN;
13419 if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
13420 tx_len > VLAN_ETH_FRAME_LEN)
13421 base_flags |= TXD_FLAG_JMB_PKT;
13424 for (i = data_off; i < tx_len; i++)
13425 tx_data[i] = (u8) (i & 0xff);
13427 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
13428 if (pci_dma_mapping_error(tp->pdev, map)) {
13429 dev_kfree_skb(skb);
13433 val = tnapi->tx_prod;
13434 tnapi->tx_buffers[val].skb = skb;
13435 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map);
13437 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13442 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
13444 budget = tg3_tx_avail(tnapi);
13445 if (tg3_tx_frag_set(tnapi, &val, &budget, map, tx_len,
13446 base_flags | TXD_FLAG_END, mss, 0)) {
13447 tnapi->tx_buffers[val].skb = NULL;
13448 dev_kfree_skb(skb);
13454 /* Sync BD data before updating mailbox */
13457 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
13458 tr32_mailbox(tnapi->prodmbox);
13462 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13463 for (i = 0; i < 35; i++) {
13464 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13469 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
13470 rx_idx = rnapi->hw_status->idx[0].rx_producer;
13471 if ((tx_idx == tnapi->tx_prod) &&
13472 (rx_idx == (rx_start_idx + num_pkts)))
13476 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1);
13477 dev_kfree_skb(skb);
13479 if (tx_idx != tnapi->tx_prod)
13482 if (rx_idx != rx_start_idx + num_pkts)
13486 while (rx_idx != rx_start_idx) {
13487 desc = &rnapi->rx_rcb[rx_start_idx++];
13488 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
13489 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
13491 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
13492 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
13495 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT)
13498 if (!tso_loopback) {
13499 if (rx_len != tx_len)
13502 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) {
13503 if (opaque_key != RXD_OPAQUE_RING_STD)
13506 if (opaque_key != RXD_OPAQUE_RING_JUMBO)
13509 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
13510 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
13511 >> RXD_TCPCSUM_SHIFT != 0xffff) {
13515 if (opaque_key == RXD_OPAQUE_RING_STD) {
13516 rx_data = tpr->rx_std_buffers[desc_idx].data;
13517 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx],
13519 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
13520 rx_data = tpr->rx_jmb_buffers[desc_idx].data;
13521 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx],
13526 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len,
13527 PCI_DMA_FROMDEVICE);
13529 rx_data += TG3_RX_OFFSET(tp);
13530 for (i = data_off; i < rx_len; i++, val++) {
13531 if (*(rx_data + i) != (u8) (val & 0xff))
13538 /* tg3_free_rings will unmap and free the rx_data */
13543 #define TG3_STD_LOOPBACK_FAILED 1
13544 #define TG3_JMB_LOOPBACK_FAILED 2
13545 #define TG3_TSO_LOOPBACK_FAILED 4
13546 #define TG3_LOOPBACK_FAILED \
13547 (TG3_STD_LOOPBACK_FAILED | \
13548 TG3_JMB_LOOPBACK_FAILED | \
13549 TG3_TSO_LOOPBACK_FAILED)
13551 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk)
13555 u32 jmb_pkt_sz = 9000;
13558 jmb_pkt_sz = tp->dma_limit - ETH_HLEN;
13560 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP;
13561 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP;
13563 if (!netif_running(tp->dev)) {
13564 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13565 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13567 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13571 err = tg3_reset_hw(tp, true);
13573 data[TG3_MAC_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13574 data[TG3_PHY_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13576 data[TG3_EXT_LOOPB_TEST] = TG3_LOOPBACK_FAILED;
13580 if (tg3_flag(tp, ENABLE_RSS)) {
13583 /* Reroute all rx packets to the 1st queue */
13584 for (i = MAC_RSS_INDIR_TBL_0;
13585 i < MAC_RSS_INDIR_TBL_0 + TG3_RSS_INDIR_TBL_SIZE; i += 4)
13589 /* HW errata - mac loopback fails in some cases on 5780.
13590 * Normal traffic and PHY loopback are not affected by
13591 * errata. Also, the MAC loopback test is deprecated for
13592 * all newer ASIC revisions.
13594 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
13595 !tg3_flag(tp, CPMU_PRESENT)) {
13596 tg3_mac_loopback(tp, true);
13598 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13599 data[TG3_MAC_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13601 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13602 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13603 data[TG3_MAC_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13605 tg3_mac_loopback(tp, false);
13608 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) &&
13609 !tg3_flag(tp, USE_PHYLIB)) {
13612 tg3_phy_lpbk_set(tp, 0, false);
13614 /* Wait for link */
13615 for (i = 0; i < 100; i++) {
13616 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
13621 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13622 data[TG3_PHY_LOOPB_TEST] |= TG3_STD_LOOPBACK_FAILED;
13623 if (tg3_flag(tp, TSO_CAPABLE) &&
13624 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13625 data[TG3_PHY_LOOPB_TEST] |= TG3_TSO_LOOPBACK_FAILED;
13626 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13627 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13628 data[TG3_PHY_LOOPB_TEST] |= TG3_JMB_LOOPBACK_FAILED;
13631 tg3_phy_lpbk_set(tp, 0, true);
13633 /* All link indications report up, but the hardware
13634 * isn't really ready for about 20 msec. Double it
13639 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false))
13640 data[TG3_EXT_LOOPB_TEST] |=
13641 TG3_STD_LOOPBACK_FAILED;
13642 if (tg3_flag(tp, TSO_CAPABLE) &&
13643 tg3_run_loopback(tp, ETH_FRAME_LEN, true))
13644 data[TG3_EXT_LOOPB_TEST] |=
13645 TG3_TSO_LOOPBACK_FAILED;
13646 if (tg3_flag(tp, JUMBO_RING_ENABLE) &&
13647 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false))
13648 data[TG3_EXT_LOOPB_TEST] |=
13649 TG3_JMB_LOOPBACK_FAILED;
13652 /* Re-enable gphy autopowerdown. */
13653 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD)
13654 tg3_phy_toggle_apd(tp, true);
13657 err = (data[TG3_MAC_LOOPB_TEST] | data[TG3_PHY_LOOPB_TEST] |
13658 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0;
13661 tp->phy_flags |= eee_cap;
13666 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
13669 struct tg3 *tp = netdev_priv(dev);
13670 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB;
13672 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) {
13673 if (tg3_power_up(tp)) {
13674 etest->flags |= ETH_TEST_FL_FAILED;
13675 memset(data, 1, sizeof(u64) * TG3_NUM_TEST);
13678 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
13681 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
13683 if (tg3_test_nvram(tp) != 0) {
13684 etest->flags |= ETH_TEST_FL_FAILED;
13685 data[TG3_NVRAM_TEST] = 1;
13687 if (!doextlpbk && tg3_test_link(tp)) {
13688 etest->flags |= ETH_TEST_FL_FAILED;
13689 data[TG3_LINK_TEST] = 1;
13691 if (etest->flags & ETH_TEST_FL_OFFLINE) {
13692 int err, err2 = 0, irq_sync = 0;
13694 if (netif_running(dev)) {
13696 tg3_netif_stop(tp);
13700 tg3_full_lock(tp, irq_sync);
13701 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
13702 err = tg3_nvram_lock(tp);
13703 tg3_halt_cpu(tp, RX_CPU_BASE);
13704 if (!tg3_flag(tp, 5705_PLUS))
13705 tg3_halt_cpu(tp, TX_CPU_BASE);
13707 tg3_nvram_unlock(tp);
13709 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
13712 if (tg3_test_registers(tp) != 0) {
13713 etest->flags |= ETH_TEST_FL_FAILED;
13714 data[TG3_REGISTER_TEST] = 1;
13717 if (tg3_test_memory(tp) != 0) {
13718 etest->flags |= ETH_TEST_FL_FAILED;
13719 data[TG3_MEMORY_TEST] = 1;
13723 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
13725 if (tg3_test_loopback(tp, data, doextlpbk))
13726 etest->flags |= ETH_TEST_FL_FAILED;
13728 tg3_full_unlock(tp);
13730 if (tg3_test_interrupt(tp) != 0) {
13731 etest->flags |= ETH_TEST_FL_FAILED;
13732 data[TG3_INTERRUPT_TEST] = 1;
13735 tg3_full_lock(tp, 0);
13737 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
13738 if (netif_running(dev)) {
13739 tg3_flag_set(tp, INIT_COMPLETE);
13740 err2 = tg3_restart_hw(tp, true);
13742 tg3_netif_start(tp);
13745 tg3_full_unlock(tp);
13747 if (irq_sync && !err2)
13750 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)
13751 tg3_power_down_prepare(tp);
13755 static int tg3_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
13757 struct tg3 *tp = netdev_priv(dev);
13758 struct hwtstamp_config stmpconf;
13760 if (!tg3_flag(tp, PTP_CAPABLE))
13761 return -EOPNOTSUPP;
13763 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf)))
13766 if (stmpconf.flags)
13769 if (stmpconf.tx_type != HWTSTAMP_TX_ON &&
13770 stmpconf.tx_type != HWTSTAMP_TX_OFF)
13773 switch (stmpconf.rx_filter) {
13774 case HWTSTAMP_FILTER_NONE:
13777 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
13778 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13779 TG3_RX_PTP_CTL_ALL_V1_EVENTS;
13781 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
13782 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13783 TG3_RX_PTP_CTL_SYNC_EVNT;
13785 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
13786 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN |
13787 TG3_RX_PTP_CTL_DELAY_REQ;
13789 case HWTSTAMP_FILTER_PTP_V2_EVENT:
13790 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13791 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13793 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
13794 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13795 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13797 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
13798 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13799 TG3_RX_PTP_CTL_ALL_V2_EVENTS;
13801 case HWTSTAMP_FILTER_PTP_V2_SYNC:
13802 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13803 TG3_RX_PTP_CTL_SYNC_EVNT;
13805 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
13806 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13807 TG3_RX_PTP_CTL_SYNC_EVNT;
13809 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
13810 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13811 TG3_RX_PTP_CTL_SYNC_EVNT;
13813 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
13814 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN |
13815 TG3_RX_PTP_CTL_DELAY_REQ;
13817 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
13818 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN |
13819 TG3_RX_PTP_CTL_DELAY_REQ;
13821 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
13822 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN |
13823 TG3_RX_PTP_CTL_DELAY_REQ;
13829 if (netif_running(dev) && tp->rxptpctl)
13830 tw32(TG3_RX_PTP_CTL,
13831 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK);
13833 if (stmpconf.tx_type == HWTSTAMP_TX_ON)
13834 tg3_flag_set(tp, TX_TSTAMP_EN);
13836 tg3_flag_clear(tp, TX_TSTAMP_EN);
13838 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13842 static int tg3_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
13844 struct tg3 *tp = netdev_priv(dev);
13845 struct hwtstamp_config stmpconf;
13847 if (!tg3_flag(tp, PTP_CAPABLE))
13848 return -EOPNOTSUPP;
13850 stmpconf.flags = 0;
13851 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ?
13852 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF);
13854 switch (tp->rxptpctl) {
13856 stmpconf.rx_filter = HWTSTAMP_FILTER_NONE;
13858 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_ALL_V1_EVENTS:
13859 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
13861 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13862 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC;
13864 case TG3_RX_PTP_CTL_RX_PTP_V1_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13865 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ;
13867 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13868 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
13870 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13871 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
13873 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_ALL_V2_EVENTS:
13874 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
13876 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13877 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC;
13879 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13880 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_SYNC;
13882 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_SYNC_EVNT:
13883 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC;
13885 case TG3_RX_PTP_CTL_RX_PTP_V2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13886 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ;
13888 case TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13889 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ;
13891 case TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | TG3_RX_PTP_CTL_DELAY_REQ:
13892 stmpconf.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ;
13899 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ?
13903 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
13905 struct mii_ioctl_data *data = if_mii(ifr);
13906 struct tg3 *tp = netdev_priv(dev);
13909 if (tg3_flag(tp, USE_PHYLIB)) {
13910 struct phy_device *phydev;
13911 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED))
13913 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
13914 return phy_mii_ioctl(phydev, ifr, cmd);
13919 data->phy_id = tp->phy_addr;
13922 case SIOCGMIIREG: {
13925 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13926 break; /* We have no PHY */
13928 if (!netif_running(dev))
13931 spin_lock_bh(&tp->lock);
13932 err = __tg3_readphy(tp, data->phy_id & 0x1f,
13933 data->reg_num & 0x1f, &mii_regval);
13934 spin_unlock_bh(&tp->lock);
13936 data->val_out = mii_regval;
13942 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
13943 break; /* We have no PHY */
13945 if (!netif_running(dev))
13948 spin_lock_bh(&tp->lock);
13949 err = __tg3_writephy(tp, data->phy_id & 0x1f,
13950 data->reg_num & 0x1f, data->val_in);
13951 spin_unlock_bh(&tp->lock);
13955 case SIOCSHWTSTAMP:
13956 return tg3_hwtstamp_set(dev, ifr);
13958 case SIOCGHWTSTAMP:
13959 return tg3_hwtstamp_get(dev, ifr);
13965 return -EOPNOTSUPP;
13968 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13970 struct tg3 *tp = netdev_priv(dev);
13972 memcpy(ec, &tp->coal, sizeof(*ec));
13976 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
13978 struct tg3 *tp = netdev_priv(dev);
13979 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
13980 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
13982 if (!tg3_flag(tp, 5705_PLUS)) {
13983 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
13984 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
13985 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
13986 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
13989 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
13990 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
13991 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
13992 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
13993 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
13994 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
13995 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
13996 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
13997 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
13998 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
14001 /* No rx interrupts will be generated if both are zero */
14002 if ((ec->rx_coalesce_usecs == 0) &&
14003 (ec->rx_max_coalesced_frames == 0))
14006 /* No tx interrupts will be generated if both are zero */
14007 if ((ec->tx_coalesce_usecs == 0) &&
14008 (ec->tx_max_coalesced_frames == 0))
14011 /* Only copy relevant parameters, ignore all others. */
14012 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
14013 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
14014 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
14015 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
14016 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
14017 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
14018 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
14019 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
14020 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
14022 if (netif_running(dev)) {
14023 tg3_full_lock(tp, 0);
14024 __tg3_set_coalesce(tp, &tp->coal);
14025 tg3_full_unlock(tp);
14030 static int tg3_set_eee(struct net_device *dev, struct ethtool_eee *edata)
14032 struct tg3 *tp = netdev_priv(dev);
14034 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14035 netdev_warn(tp->dev, "Board does not support EEE!\n");
14036 return -EOPNOTSUPP;
14039 if (edata->advertised != tp->eee.advertised) {
14040 netdev_warn(tp->dev,
14041 "Direct manipulation of EEE advertisement is not supported\n");
14045 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) {
14046 netdev_warn(tp->dev,
14047 "Maximal Tx Lpi timer supported is %#x(u)\n",
14048 TG3_CPMU_DBTMR1_LNKIDLE_MAX);
14054 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED;
14055 tg3_warn_mgmt_link_flap(tp);
14057 if (netif_running(tp->dev)) {
14058 tg3_full_lock(tp, 0);
14061 tg3_full_unlock(tp);
14067 static int tg3_get_eee(struct net_device *dev, struct ethtool_eee *edata)
14069 struct tg3 *tp = netdev_priv(dev);
14071 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) {
14072 netdev_warn(tp->dev,
14073 "Board does not support EEE!\n");
14074 return -EOPNOTSUPP;
14081 static const struct ethtool_ops tg3_ethtool_ops = {
14082 .get_settings = tg3_get_settings,
14083 .set_settings = tg3_set_settings,
14084 .get_drvinfo = tg3_get_drvinfo,
14085 .get_regs_len = tg3_get_regs_len,
14086 .get_regs = tg3_get_regs,
14087 .get_wol = tg3_get_wol,
14088 .set_wol = tg3_set_wol,
14089 .get_msglevel = tg3_get_msglevel,
14090 .set_msglevel = tg3_set_msglevel,
14091 .nway_reset = tg3_nway_reset,
14092 .get_link = ethtool_op_get_link,
14093 .get_eeprom_len = tg3_get_eeprom_len,
14094 .get_eeprom = tg3_get_eeprom,
14095 .set_eeprom = tg3_set_eeprom,
14096 .get_ringparam = tg3_get_ringparam,
14097 .set_ringparam = tg3_set_ringparam,
14098 .get_pauseparam = tg3_get_pauseparam,
14099 .set_pauseparam = tg3_set_pauseparam,
14100 .self_test = tg3_self_test,
14101 .get_strings = tg3_get_strings,
14102 .set_phys_id = tg3_set_phys_id,
14103 .get_ethtool_stats = tg3_get_ethtool_stats,
14104 .get_coalesce = tg3_get_coalesce,
14105 .set_coalesce = tg3_set_coalesce,
14106 .get_sset_count = tg3_get_sset_count,
14107 .get_rxnfc = tg3_get_rxnfc,
14108 .get_rxfh_indir_size = tg3_get_rxfh_indir_size,
14109 .get_rxfh = tg3_get_rxfh,
14110 .set_rxfh = tg3_set_rxfh,
14111 .get_channels = tg3_get_channels,
14112 .set_channels = tg3_set_channels,
14113 .get_ts_info = tg3_get_ts_info,
14114 .get_eee = tg3_get_eee,
14115 .set_eee = tg3_set_eee,
14118 static struct rtnl_link_stats64 *tg3_get_stats64(struct net_device *dev,
14119 struct rtnl_link_stats64 *stats)
14121 struct tg3 *tp = netdev_priv(dev);
14123 spin_lock_bh(&tp->lock);
14124 if (!tp->hw_stats) {
14125 *stats = tp->net_stats_prev;
14126 spin_unlock_bh(&tp->lock);
14130 tg3_get_nstats(tp, stats);
14131 spin_unlock_bh(&tp->lock);
14136 static void tg3_set_rx_mode(struct net_device *dev)
14138 struct tg3 *tp = netdev_priv(dev);
14140 if (!netif_running(dev))
14143 tg3_full_lock(tp, 0);
14144 __tg3_set_rx_mode(dev);
14145 tg3_full_unlock(tp);
14148 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
14151 dev->mtu = new_mtu;
14153 if (new_mtu > ETH_DATA_LEN) {
14154 if (tg3_flag(tp, 5780_CLASS)) {
14155 netdev_update_features(dev);
14156 tg3_flag_clear(tp, TSO_CAPABLE);
14158 tg3_flag_set(tp, JUMBO_RING_ENABLE);
14161 if (tg3_flag(tp, 5780_CLASS)) {
14162 tg3_flag_set(tp, TSO_CAPABLE);
14163 netdev_update_features(dev);
14165 tg3_flag_clear(tp, JUMBO_RING_ENABLE);
14169 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
14171 struct tg3 *tp = netdev_priv(dev);
14173 bool reset_phy = false;
14175 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
14178 if (!netif_running(dev)) {
14179 /* We'll just catch it later when the
14182 tg3_set_mtu(dev, tp, new_mtu);
14188 tg3_netif_stop(tp);
14190 tg3_set_mtu(dev, tp, new_mtu);
14192 tg3_full_lock(tp, 1);
14194 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14196 /* Reset PHY, otherwise the read DMA engine will be in a mode that
14197 * breaks all requests to 256 bytes.
14199 if (tg3_asic_rev(tp) == ASIC_REV_57766)
14202 err = tg3_restart_hw(tp, reset_phy);
14205 tg3_netif_start(tp);
14207 tg3_full_unlock(tp);
14215 static const struct net_device_ops tg3_netdev_ops = {
14216 .ndo_open = tg3_open,
14217 .ndo_stop = tg3_close,
14218 .ndo_start_xmit = tg3_start_xmit,
14219 .ndo_get_stats64 = tg3_get_stats64,
14220 .ndo_validate_addr = eth_validate_addr,
14221 .ndo_set_rx_mode = tg3_set_rx_mode,
14222 .ndo_set_mac_address = tg3_set_mac_addr,
14223 .ndo_do_ioctl = tg3_ioctl,
14224 .ndo_tx_timeout = tg3_tx_timeout,
14225 .ndo_change_mtu = tg3_change_mtu,
14226 .ndo_fix_features = tg3_fix_features,
14227 .ndo_set_features = tg3_set_features,
14228 #ifdef CONFIG_NET_POLL_CONTROLLER
14229 .ndo_poll_controller = tg3_poll_controller,
14233 static void tg3_get_eeprom_size(struct tg3 *tp)
14235 u32 cursize, val, magic;
14237 tp->nvram_size = EEPROM_CHIP_SIZE;
14239 if (tg3_nvram_read(tp, 0, &magic) != 0)
14242 if ((magic != TG3_EEPROM_MAGIC) &&
14243 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
14244 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
14248 * Size the chip by reading offsets at increasing powers of two.
14249 * When we encounter our validation signature, we know the addressing
14250 * has wrapped around, and thus have our chip size.
14254 while (cursize < tp->nvram_size) {
14255 if (tg3_nvram_read(tp, cursize, &val) != 0)
14264 tp->nvram_size = cursize;
14267 static void tg3_get_nvram_size(struct tg3 *tp)
14271 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0)
14274 /* Selfboot format */
14275 if (val != TG3_EEPROM_MAGIC) {
14276 tg3_get_eeprom_size(tp);
14280 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
14282 /* This is confusing. We want to operate on the
14283 * 16-bit value at offset 0xf2. The tg3_nvram_read()
14284 * call will read from NVRAM and byteswap the data
14285 * according to the byteswapping settings for all
14286 * other register accesses. This ensures the data we
14287 * want will always reside in the lower 16-bits.
14288 * However, the data in NVRAM is in LE format, which
14289 * means the data from the NVRAM read will always be
14290 * opposite the endianness of the CPU. The 16-bit
14291 * byteswap then brings the data to CPU endianness.
14293 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
14297 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14300 static void tg3_get_nvram_info(struct tg3 *tp)
14304 nvcfg1 = tr32(NVRAM_CFG1);
14305 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
14306 tg3_flag_set(tp, FLASH);
14308 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14309 tw32(NVRAM_CFG1, nvcfg1);
14312 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
14313 tg3_flag(tp, 5780_CLASS)) {
14314 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
14315 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
14316 tp->nvram_jedecnum = JEDEC_ATMEL;
14317 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14318 tg3_flag_set(tp, NVRAM_BUFFERED);
14320 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
14321 tp->nvram_jedecnum = JEDEC_ATMEL;
14322 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
14324 case FLASH_VENDOR_ATMEL_EEPROM:
14325 tp->nvram_jedecnum = JEDEC_ATMEL;
14326 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14327 tg3_flag_set(tp, NVRAM_BUFFERED);
14329 case FLASH_VENDOR_ST:
14330 tp->nvram_jedecnum = JEDEC_ST;
14331 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
14332 tg3_flag_set(tp, NVRAM_BUFFERED);
14334 case FLASH_VENDOR_SAIFUN:
14335 tp->nvram_jedecnum = JEDEC_SAIFUN;
14336 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
14338 case FLASH_VENDOR_SST_SMALL:
14339 case FLASH_VENDOR_SST_LARGE:
14340 tp->nvram_jedecnum = JEDEC_SST;
14341 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
14345 tp->nvram_jedecnum = JEDEC_ATMEL;
14346 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
14347 tg3_flag_set(tp, NVRAM_BUFFERED);
14351 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
14353 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
14354 case FLASH_5752PAGE_SIZE_256:
14355 tp->nvram_pagesize = 256;
14357 case FLASH_5752PAGE_SIZE_512:
14358 tp->nvram_pagesize = 512;
14360 case FLASH_5752PAGE_SIZE_1K:
14361 tp->nvram_pagesize = 1024;
14363 case FLASH_5752PAGE_SIZE_2K:
14364 tp->nvram_pagesize = 2048;
14366 case FLASH_5752PAGE_SIZE_4K:
14367 tp->nvram_pagesize = 4096;
14369 case FLASH_5752PAGE_SIZE_264:
14370 tp->nvram_pagesize = 264;
14372 case FLASH_5752PAGE_SIZE_528:
14373 tp->nvram_pagesize = 528;
14378 static void tg3_get_5752_nvram_info(struct tg3 *tp)
14382 nvcfg1 = tr32(NVRAM_CFG1);
14384 /* NVRAM protection for TPM */
14385 if (nvcfg1 & (1 << 27))
14386 tg3_flag_set(tp, PROTECTED_NVRAM);
14388 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14389 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
14390 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
14391 tp->nvram_jedecnum = JEDEC_ATMEL;
14392 tg3_flag_set(tp, NVRAM_BUFFERED);
14394 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14395 tp->nvram_jedecnum = JEDEC_ATMEL;
14396 tg3_flag_set(tp, NVRAM_BUFFERED);
14397 tg3_flag_set(tp, FLASH);
14399 case FLASH_5752VENDOR_ST_M45PE10:
14400 case FLASH_5752VENDOR_ST_M45PE20:
14401 case FLASH_5752VENDOR_ST_M45PE40:
14402 tp->nvram_jedecnum = JEDEC_ST;
14403 tg3_flag_set(tp, NVRAM_BUFFERED);
14404 tg3_flag_set(tp, FLASH);
14408 if (tg3_flag(tp, FLASH)) {
14409 tg3_nvram_get_pagesize(tp, nvcfg1);
14411 /* For eeprom, set pagesize to maximum eeprom size */
14412 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14414 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14415 tw32(NVRAM_CFG1, nvcfg1);
14419 static void tg3_get_5755_nvram_info(struct tg3 *tp)
14421 u32 nvcfg1, protect = 0;
14423 nvcfg1 = tr32(NVRAM_CFG1);
14425 /* NVRAM protection for TPM */
14426 if (nvcfg1 & (1 << 27)) {
14427 tg3_flag_set(tp, PROTECTED_NVRAM);
14431 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14433 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14434 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14435 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14436 case FLASH_5755VENDOR_ATMEL_FLASH_5:
14437 tp->nvram_jedecnum = JEDEC_ATMEL;
14438 tg3_flag_set(tp, NVRAM_BUFFERED);
14439 tg3_flag_set(tp, FLASH);
14440 tp->nvram_pagesize = 264;
14441 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
14442 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
14443 tp->nvram_size = (protect ? 0x3e200 :
14444 TG3_NVRAM_SIZE_512KB);
14445 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
14446 tp->nvram_size = (protect ? 0x1f200 :
14447 TG3_NVRAM_SIZE_256KB);
14449 tp->nvram_size = (protect ? 0x1f200 :
14450 TG3_NVRAM_SIZE_128KB);
14452 case FLASH_5752VENDOR_ST_M45PE10:
14453 case FLASH_5752VENDOR_ST_M45PE20:
14454 case FLASH_5752VENDOR_ST_M45PE40:
14455 tp->nvram_jedecnum = JEDEC_ST;
14456 tg3_flag_set(tp, NVRAM_BUFFERED);
14457 tg3_flag_set(tp, FLASH);
14458 tp->nvram_pagesize = 256;
14459 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
14460 tp->nvram_size = (protect ?
14461 TG3_NVRAM_SIZE_64KB :
14462 TG3_NVRAM_SIZE_128KB);
14463 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
14464 tp->nvram_size = (protect ?
14465 TG3_NVRAM_SIZE_64KB :
14466 TG3_NVRAM_SIZE_256KB);
14468 tp->nvram_size = (protect ?
14469 TG3_NVRAM_SIZE_128KB :
14470 TG3_NVRAM_SIZE_512KB);
14475 static void tg3_get_5787_nvram_info(struct tg3 *tp)
14479 nvcfg1 = tr32(NVRAM_CFG1);
14481 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14482 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
14483 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14484 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
14485 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14486 tp->nvram_jedecnum = JEDEC_ATMEL;
14487 tg3_flag_set(tp, NVRAM_BUFFERED);
14488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14490 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14491 tw32(NVRAM_CFG1, nvcfg1);
14493 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14494 case FLASH_5755VENDOR_ATMEL_FLASH_1:
14495 case FLASH_5755VENDOR_ATMEL_FLASH_2:
14496 case FLASH_5755VENDOR_ATMEL_FLASH_3:
14497 tp->nvram_jedecnum = JEDEC_ATMEL;
14498 tg3_flag_set(tp, NVRAM_BUFFERED);
14499 tg3_flag_set(tp, FLASH);
14500 tp->nvram_pagesize = 264;
14502 case FLASH_5752VENDOR_ST_M45PE10:
14503 case FLASH_5752VENDOR_ST_M45PE20:
14504 case FLASH_5752VENDOR_ST_M45PE40:
14505 tp->nvram_jedecnum = JEDEC_ST;
14506 tg3_flag_set(tp, NVRAM_BUFFERED);
14507 tg3_flag_set(tp, FLASH);
14508 tp->nvram_pagesize = 256;
14513 static void tg3_get_5761_nvram_info(struct tg3 *tp)
14515 u32 nvcfg1, protect = 0;
14517 nvcfg1 = tr32(NVRAM_CFG1);
14519 /* NVRAM protection for TPM */
14520 if (nvcfg1 & (1 << 27)) {
14521 tg3_flag_set(tp, PROTECTED_NVRAM);
14525 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
14527 case FLASH_5761VENDOR_ATMEL_ADB021D:
14528 case FLASH_5761VENDOR_ATMEL_ADB041D:
14529 case FLASH_5761VENDOR_ATMEL_ADB081D:
14530 case FLASH_5761VENDOR_ATMEL_ADB161D:
14531 case FLASH_5761VENDOR_ATMEL_MDB021D:
14532 case FLASH_5761VENDOR_ATMEL_MDB041D:
14533 case FLASH_5761VENDOR_ATMEL_MDB081D:
14534 case FLASH_5761VENDOR_ATMEL_MDB161D:
14535 tp->nvram_jedecnum = JEDEC_ATMEL;
14536 tg3_flag_set(tp, NVRAM_BUFFERED);
14537 tg3_flag_set(tp, FLASH);
14538 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14539 tp->nvram_pagesize = 256;
14541 case FLASH_5761VENDOR_ST_A_M45PE20:
14542 case FLASH_5761VENDOR_ST_A_M45PE40:
14543 case FLASH_5761VENDOR_ST_A_M45PE80:
14544 case FLASH_5761VENDOR_ST_A_M45PE16:
14545 case FLASH_5761VENDOR_ST_M_M45PE20:
14546 case FLASH_5761VENDOR_ST_M_M45PE40:
14547 case FLASH_5761VENDOR_ST_M_M45PE80:
14548 case FLASH_5761VENDOR_ST_M_M45PE16:
14549 tp->nvram_jedecnum = JEDEC_ST;
14550 tg3_flag_set(tp, NVRAM_BUFFERED);
14551 tg3_flag_set(tp, FLASH);
14552 tp->nvram_pagesize = 256;
14557 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
14560 case FLASH_5761VENDOR_ATMEL_ADB161D:
14561 case FLASH_5761VENDOR_ATMEL_MDB161D:
14562 case FLASH_5761VENDOR_ST_A_M45PE16:
14563 case FLASH_5761VENDOR_ST_M_M45PE16:
14564 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
14566 case FLASH_5761VENDOR_ATMEL_ADB081D:
14567 case FLASH_5761VENDOR_ATMEL_MDB081D:
14568 case FLASH_5761VENDOR_ST_A_M45PE80:
14569 case FLASH_5761VENDOR_ST_M_M45PE80:
14570 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14572 case FLASH_5761VENDOR_ATMEL_ADB041D:
14573 case FLASH_5761VENDOR_ATMEL_MDB041D:
14574 case FLASH_5761VENDOR_ST_A_M45PE40:
14575 case FLASH_5761VENDOR_ST_M_M45PE40:
14576 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14578 case FLASH_5761VENDOR_ATMEL_ADB021D:
14579 case FLASH_5761VENDOR_ATMEL_MDB021D:
14580 case FLASH_5761VENDOR_ST_A_M45PE20:
14581 case FLASH_5761VENDOR_ST_M_M45PE20:
14582 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14588 static void tg3_get_5906_nvram_info(struct tg3 *tp)
14590 tp->nvram_jedecnum = JEDEC_ATMEL;
14591 tg3_flag_set(tp, NVRAM_BUFFERED);
14592 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14595 static void tg3_get_57780_nvram_info(struct tg3 *tp)
14599 nvcfg1 = tr32(NVRAM_CFG1);
14601 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14602 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
14603 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
14604 tp->nvram_jedecnum = JEDEC_ATMEL;
14605 tg3_flag_set(tp, NVRAM_BUFFERED);
14606 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14608 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14609 tw32(NVRAM_CFG1, nvcfg1);
14611 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14612 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14613 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14614 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14615 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14616 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14617 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14618 tp->nvram_jedecnum = JEDEC_ATMEL;
14619 tg3_flag_set(tp, NVRAM_BUFFERED);
14620 tg3_flag_set(tp, FLASH);
14622 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14623 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
14624 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
14625 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
14626 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14628 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
14629 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
14630 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14632 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
14633 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
14634 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14638 case FLASH_5752VENDOR_ST_M45PE10:
14639 case FLASH_5752VENDOR_ST_M45PE20:
14640 case FLASH_5752VENDOR_ST_M45PE40:
14641 tp->nvram_jedecnum = JEDEC_ST;
14642 tg3_flag_set(tp, NVRAM_BUFFERED);
14643 tg3_flag_set(tp, FLASH);
14645 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14646 case FLASH_5752VENDOR_ST_M45PE10:
14647 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14649 case FLASH_5752VENDOR_ST_M45PE20:
14650 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14652 case FLASH_5752VENDOR_ST_M45PE40:
14653 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14658 tg3_flag_set(tp, NO_NVRAM);
14662 tg3_nvram_get_pagesize(tp, nvcfg1);
14663 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14664 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14668 static void tg3_get_5717_nvram_info(struct tg3 *tp)
14672 nvcfg1 = tr32(NVRAM_CFG1);
14674 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14675 case FLASH_5717VENDOR_ATMEL_EEPROM:
14676 case FLASH_5717VENDOR_MICRO_EEPROM:
14677 tp->nvram_jedecnum = JEDEC_ATMEL;
14678 tg3_flag_set(tp, NVRAM_BUFFERED);
14679 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14681 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14682 tw32(NVRAM_CFG1, nvcfg1);
14684 case FLASH_5717VENDOR_ATMEL_MDB011D:
14685 case FLASH_5717VENDOR_ATMEL_ADB011B:
14686 case FLASH_5717VENDOR_ATMEL_ADB011D:
14687 case FLASH_5717VENDOR_ATMEL_MDB021D:
14688 case FLASH_5717VENDOR_ATMEL_ADB021B:
14689 case FLASH_5717VENDOR_ATMEL_ADB021D:
14690 case FLASH_5717VENDOR_ATMEL_45USPT:
14691 tp->nvram_jedecnum = JEDEC_ATMEL;
14692 tg3_flag_set(tp, NVRAM_BUFFERED);
14693 tg3_flag_set(tp, FLASH);
14695 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14696 case FLASH_5717VENDOR_ATMEL_MDB021D:
14697 /* Detect size with tg3_nvram_get_size() */
14699 case FLASH_5717VENDOR_ATMEL_ADB021B:
14700 case FLASH_5717VENDOR_ATMEL_ADB021D:
14701 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14704 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14708 case FLASH_5717VENDOR_ST_M_M25PE10:
14709 case FLASH_5717VENDOR_ST_A_M25PE10:
14710 case FLASH_5717VENDOR_ST_M_M45PE10:
14711 case FLASH_5717VENDOR_ST_A_M45PE10:
14712 case FLASH_5717VENDOR_ST_M_M25PE20:
14713 case FLASH_5717VENDOR_ST_A_M25PE20:
14714 case FLASH_5717VENDOR_ST_M_M45PE20:
14715 case FLASH_5717VENDOR_ST_A_M45PE20:
14716 case FLASH_5717VENDOR_ST_25USPT:
14717 case FLASH_5717VENDOR_ST_45USPT:
14718 tp->nvram_jedecnum = JEDEC_ST;
14719 tg3_flag_set(tp, NVRAM_BUFFERED);
14720 tg3_flag_set(tp, FLASH);
14722 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
14723 case FLASH_5717VENDOR_ST_M_M25PE20:
14724 case FLASH_5717VENDOR_ST_M_M45PE20:
14725 /* Detect size with tg3_nvram_get_size() */
14727 case FLASH_5717VENDOR_ST_A_M25PE20:
14728 case FLASH_5717VENDOR_ST_A_M45PE20:
14729 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14732 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14737 tg3_flag_set(tp, NO_NVRAM);
14741 tg3_nvram_get_pagesize(tp, nvcfg1);
14742 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14743 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14746 static void tg3_get_5720_nvram_info(struct tg3 *tp)
14748 u32 nvcfg1, nvmpinstrp;
14750 nvcfg1 = tr32(NVRAM_CFG1);
14751 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
14753 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14754 if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {
14755 tg3_flag_set(tp, NO_NVRAM);
14759 switch (nvmpinstrp) {
14760 case FLASH_5762_EEPROM_HD:
14761 nvmpinstrp = FLASH_5720_EEPROM_HD;
14763 case FLASH_5762_EEPROM_LD:
14764 nvmpinstrp = FLASH_5720_EEPROM_LD;
14766 case FLASH_5720VENDOR_M_ST_M45PE20:
14767 /* This pinstrap supports multiple sizes, so force it
14768 * to read the actual size from location 0xf0.
14770 nvmpinstrp = FLASH_5720VENDOR_ST_45USPT;
14775 switch (nvmpinstrp) {
14776 case FLASH_5720_EEPROM_HD:
14777 case FLASH_5720_EEPROM_LD:
14778 tp->nvram_jedecnum = JEDEC_ATMEL;
14779 tg3_flag_set(tp, NVRAM_BUFFERED);
14781 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
14782 tw32(NVRAM_CFG1, nvcfg1);
14783 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
14784 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
14786 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
14788 case FLASH_5720VENDOR_M_ATMEL_DB011D:
14789 case FLASH_5720VENDOR_A_ATMEL_DB011B:
14790 case FLASH_5720VENDOR_A_ATMEL_DB011D:
14791 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14792 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14793 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14794 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14795 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14796 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14797 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14798 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14799 case FLASH_5720VENDOR_ATMEL_45USPT:
14800 tp->nvram_jedecnum = JEDEC_ATMEL;
14801 tg3_flag_set(tp, NVRAM_BUFFERED);
14802 tg3_flag_set(tp, FLASH);
14804 switch (nvmpinstrp) {
14805 case FLASH_5720VENDOR_M_ATMEL_DB021D:
14806 case FLASH_5720VENDOR_A_ATMEL_DB021B:
14807 case FLASH_5720VENDOR_A_ATMEL_DB021D:
14808 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14810 case FLASH_5720VENDOR_M_ATMEL_DB041D:
14811 case FLASH_5720VENDOR_A_ATMEL_DB041B:
14812 case FLASH_5720VENDOR_A_ATMEL_DB041D:
14813 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14815 case FLASH_5720VENDOR_M_ATMEL_DB081D:
14816 case FLASH_5720VENDOR_A_ATMEL_DB081D:
14817 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14820 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14821 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14825 case FLASH_5720VENDOR_M_ST_M25PE10:
14826 case FLASH_5720VENDOR_M_ST_M45PE10:
14827 case FLASH_5720VENDOR_A_ST_M25PE10:
14828 case FLASH_5720VENDOR_A_ST_M45PE10:
14829 case FLASH_5720VENDOR_M_ST_M25PE20:
14830 case FLASH_5720VENDOR_M_ST_M45PE20:
14831 case FLASH_5720VENDOR_A_ST_M25PE20:
14832 case FLASH_5720VENDOR_A_ST_M45PE20:
14833 case FLASH_5720VENDOR_M_ST_M25PE40:
14834 case FLASH_5720VENDOR_M_ST_M45PE40:
14835 case FLASH_5720VENDOR_A_ST_M25PE40:
14836 case FLASH_5720VENDOR_A_ST_M45PE40:
14837 case FLASH_5720VENDOR_M_ST_M25PE80:
14838 case FLASH_5720VENDOR_M_ST_M45PE80:
14839 case FLASH_5720VENDOR_A_ST_M25PE80:
14840 case FLASH_5720VENDOR_A_ST_M45PE80:
14841 case FLASH_5720VENDOR_ST_25USPT:
14842 case FLASH_5720VENDOR_ST_45USPT:
14843 tp->nvram_jedecnum = JEDEC_ST;
14844 tg3_flag_set(tp, NVRAM_BUFFERED);
14845 tg3_flag_set(tp, FLASH);
14847 switch (nvmpinstrp) {
14848 case FLASH_5720VENDOR_M_ST_M25PE20:
14849 case FLASH_5720VENDOR_M_ST_M45PE20:
14850 case FLASH_5720VENDOR_A_ST_M25PE20:
14851 case FLASH_5720VENDOR_A_ST_M45PE20:
14852 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
14854 case FLASH_5720VENDOR_M_ST_M25PE40:
14855 case FLASH_5720VENDOR_M_ST_M45PE40:
14856 case FLASH_5720VENDOR_A_ST_M25PE40:
14857 case FLASH_5720VENDOR_A_ST_M45PE40:
14858 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
14860 case FLASH_5720VENDOR_M_ST_M25PE80:
14861 case FLASH_5720VENDOR_M_ST_M45PE80:
14862 case FLASH_5720VENDOR_A_ST_M25PE80:
14863 case FLASH_5720VENDOR_A_ST_M45PE80:
14864 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
14867 if (tg3_asic_rev(tp) != ASIC_REV_5762)
14868 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
14873 tg3_flag_set(tp, NO_NVRAM);
14877 tg3_nvram_get_pagesize(tp, nvcfg1);
14878 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
14879 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS);
14881 if (tg3_asic_rev(tp) == ASIC_REV_5762) {
14884 if (tg3_nvram_read(tp, 0, &val))
14887 if (val != TG3_EEPROM_MAGIC &&
14888 (val & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW)
14889 tg3_flag_set(tp, NO_NVRAM);
14893 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14894 static void tg3_nvram_init(struct tg3 *tp)
14896 if (tg3_flag(tp, IS_SSB_CORE)) {
14897 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14898 tg3_flag_clear(tp, NVRAM);
14899 tg3_flag_clear(tp, NVRAM_BUFFERED);
14900 tg3_flag_set(tp, NO_NVRAM);
14904 tw32_f(GRC_EEPROM_ADDR,
14905 (EEPROM_ADDR_FSM_RESET |
14906 (EEPROM_DEFAULT_CLOCK_PERIOD <<
14907 EEPROM_ADDR_CLKPERD_SHIFT)));
14911 /* Enable seeprom accesses. */
14912 tw32_f(GRC_LOCAL_CTRL,
14913 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
14916 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
14917 tg3_asic_rev(tp) != ASIC_REV_5701) {
14918 tg3_flag_set(tp, NVRAM);
14920 if (tg3_nvram_lock(tp)) {
14921 netdev_warn(tp->dev,
14922 "Cannot get nvram lock, %s failed\n",
14926 tg3_enable_nvram_access(tp);
14928 tp->nvram_size = 0;
14930 if (tg3_asic_rev(tp) == ASIC_REV_5752)
14931 tg3_get_5752_nvram_info(tp);
14932 else if (tg3_asic_rev(tp) == ASIC_REV_5755)
14933 tg3_get_5755_nvram_info(tp);
14934 else if (tg3_asic_rev(tp) == ASIC_REV_5787 ||
14935 tg3_asic_rev(tp) == ASIC_REV_5784 ||
14936 tg3_asic_rev(tp) == ASIC_REV_5785)
14937 tg3_get_5787_nvram_info(tp);
14938 else if (tg3_asic_rev(tp) == ASIC_REV_5761)
14939 tg3_get_5761_nvram_info(tp);
14940 else if (tg3_asic_rev(tp) == ASIC_REV_5906)
14941 tg3_get_5906_nvram_info(tp);
14942 else if (tg3_asic_rev(tp) == ASIC_REV_57780 ||
14943 tg3_flag(tp, 57765_CLASS))
14944 tg3_get_57780_nvram_info(tp);
14945 else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
14946 tg3_asic_rev(tp) == ASIC_REV_5719)
14947 tg3_get_5717_nvram_info(tp);
14948 else if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
14949 tg3_asic_rev(tp) == ASIC_REV_5762)
14950 tg3_get_5720_nvram_info(tp);
14952 tg3_get_nvram_info(tp);
14954 if (tp->nvram_size == 0)
14955 tg3_get_nvram_size(tp);
14957 tg3_disable_nvram_access(tp);
14958 tg3_nvram_unlock(tp);
14961 tg3_flag_clear(tp, NVRAM);
14962 tg3_flag_clear(tp, NVRAM_BUFFERED);
14964 tg3_get_eeprom_size(tp);
14968 struct subsys_tbl_ent {
14969 u16 subsys_vendor, subsys_devid;
14973 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
14974 /* Broadcom boards. */
14975 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14976 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
14977 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14978 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
14979 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14980 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
14981 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14982 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
14983 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14984 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
14985 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14986 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
14987 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14988 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
14989 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14990 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
14991 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14992 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
14993 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14994 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
14995 { TG3PCI_SUBVENDOR_ID_BROADCOM,
14996 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
14999 { TG3PCI_SUBVENDOR_ID_3COM,
15000 TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
15001 { TG3PCI_SUBVENDOR_ID_3COM,
15002 TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
15003 { TG3PCI_SUBVENDOR_ID_3COM,
15004 TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
15005 { TG3PCI_SUBVENDOR_ID_3COM,
15006 TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
15007 { TG3PCI_SUBVENDOR_ID_3COM,
15008 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
15011 { TG3PCI_SUBVENDOR_ID_DELL,
15012 TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
15013 { TG3PCI_SUBVENDOR_ID_DELL,
15014 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
15015 { TG3PCI_SUBVENDOR_ID_DELL,
15016 TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
15017 { TG3PCI_SUBVENDOR_ID_DELL,
15018 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
15020 /* Compaq boards. */
15021 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15022 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
15023 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15024 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
15025 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15026 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
15027 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15028 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
15029 { TG3PCI_SUBVENDOR_ID_COMPAQ,
15030 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
15033 { TG3PCI_SUBVENDOR_ID_IBM,
15034 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
15037 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
15041 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
15042 if ((subsys_id_to_phy_id[i].subsys_vendor ==
15043 tp->pdev->subsystem_vendor) &&
15044 (subsys_id_to_phy_id[i].subsys_devid ==
15045 tp->pdev->subsystem_device))
15046 return &subsys_id_to_phy_id[i];
15051 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
15055 tp->phy_id = TG3_PHY_ID_INVALID;
15056 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15058 /* Assume an onboard device and WOL capable by default. */
15059 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15060 tg3_flag_set(tp, WOL_CAP);
15062 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15063 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
15064 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15065 tg3_flag_set(tp, IS_NIC);
15067 val = tr32(VCPU_CFGSHDW);
15068 if (val & VCPU_CFGSHDW_ASPM_DBNC)
15069 tg3_flag_set(tp, ASPM_WORKAROUND);
15070 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
15071 (val & VCPU_CFGSHDW_WOL_MAGPKT)) {
15072 tg3_flag_set(tp, WOL_ENABLE);
15073 device_set_wakeup_enable(&tp->pdev->dev, true);
15078 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
15079 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
15080 u32 nic_cfg, led_cfg;
15081 u32 cfg2 = 0, cfg4 = 0, cfg5 = 0;
15082 u32 nic_phy_id, ver, eeprom_phy_id;
15083 int eeprom_phy_serdes = 0;
15085 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
15086 tp->nic_sram_data_cfg = nic_cfg;
15088 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
15089 ver >>= NIC_SRAM_DATA_VER_SHIFT;
15090 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
15091 tg3_asic_rev(tp) != ASIC_REV_5701 &&
15092 tg3_asic_rev(tp) != ASIC_REV_5703 &&
15093 (ver > 0) && (ver < 0x100))
15094 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
15096 if (tg3_asic_rev(tp) == ASIC_REV_5785)
15097 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
15099 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
15100 tg3_asic_rev(tp) == ASIC_REV_5719 ||
15101 tg3_asic_rev(tp) == ASIC_REV_5720)
15102 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5);
15104 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
15105 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
15106 eeprom_phy_serdes = 1;
15108 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
15109 if (nic_phy_id != 0) {
15110 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
15111 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
15113 eeprom_phy_id = (id1 >> 16) << 10;
15114 eeprom_phy_id |= (id2 & 0xfc00) << 16;
15115 eeprom_phy_id |= (id2 & 0x03ff) << 0;
15119 tp->phy_id = eeprom_phy_id;
15120 if (eeprom_phy_serdes) {
15121 if (!tg3_flag(tp, 5705_PLUS))
15122 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15124 tp->phy_flags |= TG3_PHYFLG_MII_SERDES;
15127 if (tg3_flag(tp, 5750_PLUS))
15128 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
15129 SHASTA_EXT_LED_MODE_MASK);
15131 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
15135 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
15136 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15139 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
15140 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15143 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
15144 tp->led_ctrl = LED_CTRL_MODE_MAC;
15146 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
15147 * read on some older 5700/5701 bootcode.
15149 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
15150 tg3_asic_rev(tp) == ASIC_REV_5701)
15151 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15155 case SHASTA_EXT_LED_SHARED:
15156 tp->led_ctrl = LED_CTRL_MODE_SHARED;
15157 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 &&
15158 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1)
15159 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15160 LED_CTRL_MODE_PHY_2);
15162 if (tg3_flag(tp, 5717_PLUS) ||
15163 tg3_asic_rev(tp) == ASIC_REV_5762)
15164 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE |
15165 LED_CTRL_BLINK_RATE_MASK;
15169 case SHASTA_EXT_LED_MAC:
15170 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
15173 case SHASTA_EXT_LED_COMBO:
15174 tp->led_ctrl = LED_CTRL_MODE_COMBO;
15175 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0)
15176 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
15177 LED_CTRL_MODE_PHY_2);
15182 if ((tg3_asic_rev(tp) == ASIC_REV_5700 ||
15183 tg3_asic_rev(tp) == ASIC_REV_5701) &&
15184 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
15185 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
15187 if (tg3_chip_rev(tp) == CHIPREV_5784_AX)
15188 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
15190 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
15191 tg3_flag_set(tp, EEPROM_WRITE_PROT);
15192 if ((tp->pdev->subsystem_vendor ==
15193 PCI_VENDOR_ID_ARIMA) &&
15194 (tp->pdev->subsystem_device == 0x205a ||
15195 tp->pdev->subsystem_device == 0x2063))
15196 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15198 tg3_flag_clear(tp, EEPROM_WRITE_PROT);
15199 tg3_flag_set(tp, IS_NIC);
15202 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
15203 tg3_flag_set(tp, ENABLE_ASF);
15204 if (tg3_flag(tp, 5750_PLUS))
15205 tg3_flag_set(tp, ASF_NEW_HANDSHAKE);
15208 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
15209 tg3_flag(tp, 5750_PLUS))
15210 tg3_flag_set(tp, ENABLE_APE);
15212 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES &&
15213 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
15214 tg3_flag_clear(tp, WOL_CAP);
15216 if (tg3_flag(tp, WOL_CAP) &&
15217 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE)) {
15218 tg3_flag_set(tp, WOL_ENABLE);
15219 device_set_wakeup_enable(&tp->pdev->dev, true);
15222 if (cfg2 & (1 << 17))
15223 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING;
15225 /* serdes signal pre-emphasis in register 0x590 set by */
15226 /* bootcode if bit 18 is set */
15227 if (cfg2 & (1 << 18))
15228 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS;
15230 if ((tg3_flag(tp, 57765_PLUS) ||
15231 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
15232 tg3_chip_rev(tp) != CHIPREV_5784_AX)) &&
15233 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
15234 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD;
15236 if (tg3_flag(tp, PCI_EXPRESS)) {
15239 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
15240 if (tg3_asic_rev(tp) != ASIC_REV_5785 &&
15241 !tg3_flag(tp, 57765_PLUS) &&
15242 (cfg3 & NIC_SRAM_ASPM_DEBOUNCE))
15243 tg3_flag_set(tp, ASPM_WORKAROUND);
15244 if (cfg3 & NIC_SRAM_LNK_FLAP_AVOID)
15245 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN;
15246 if (cfg3 & NIC_SRAM_1G_ON_VAUX_OK)
15247 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK;
15250 if (cfg4 & NIC_SRAM_RGMII_INBAND_DISABLE)
15251 tg3_flag_set(tp, RGMII_INBAND_DISABLE);
15252 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
15253 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN);
15254 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
15255 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN);
15257 if (cfg5 & NIC_SRAM_DISABLE_1G_HALF_ADV)
15258 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV;
15261 if (tg3_flag(tp, WOL_CAP))
15262 device_set_wakeup_enable(&tp->pdev->dev,
15263 tg3_flag(tp, WOL_ENABLE));
15265 device_set_wakeup_capable(&tp->pdev->dev, false);
15268 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val)
15271 u32 val2, off = offset * 8;
15273 err = tg3_nvram_lock(tp);
15277 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE);
15278 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN |
15279 APE_OTP_CTRL_CMD_RD | APE_OTP_CTRL_START);
15280 tg3_ape_read32(tp, TG3_APE_OTP_CTRL);
15283 for (i = 0; i < 100; i++) {
15284 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS);
15285 if (val2 & APE_OTP_STATUS_CMD_DONE) {
15286 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA);
15292 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0);
15294 tg3_nvram_unlock(tp);
15295 if (val2 & APE_OTP_STATUS_CMD_DONE)
15301 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
15306 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
15307 tw32(OTP_CTRL, cmd);
15309 /* Wait for up to 1 ms for command to execute. */
15310 for (i = 0; i < 100; i++) {
15311 val = tr32(OTP_STATUS);
15312 if (val & OTP_STATUS_CMD_DONE)
15317 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
15320 /* Read the gphy configuration from the OTP region of the chip. The gphy
15321 * configuration is a 32-bit value that straddles the alignment boundary.
15322 * We do two 32-bit reads and then shift and merge the results.
15324 static u32 tg3_read_otp_phycfg(struct tg3 *tp)
15326 u32 bhalf_otp, thalf_otp;
15328 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
15330 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
15333 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
15335 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15338 thalf_otp = tr32(OTP_READ_DATA);
15340 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
15342 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
15345 bhalf_otp = tr32(OTP_READ_DATA);
15347 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
15350 static void tg3_phy_init_link_config(struct tg3 *tp)
15352 u32 adv = ADVERTISED_Autoneg;
15354 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
15355 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV))
15356 adv |= ADVERTISED_1000baseT_Half;
15357 adv |= ADVERTISED_1000baseT_Full;
15360 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
15361 adv |= ADVERTISED_100baseT_Half |
15362 ADVERTISED_100baseT_Full |
15363 ADVERTISED_10baseT_Half |
15364 ADVERTISED_10baseT_Full |
15367 adv |= ADVERTISED_FIBRE;
15369 tp->link_config.advertising = adv;
15370 tp->link_config.speed = SPEED_UNKNOWN;
15371 tp->link_config.duplex = DUPLEX_UNKNOWN;
15372 tp->link_config.autoneg = AUTONEG_ENABLE;
15373 tp->link_config.active_speed = SPEED_UNKNOWN;
15374 tp->link_config.active_duplex = DUPLEX_UNKNOWN;
15379 static int tg3_phy_probe(struct tg3 *tp)
15381 u32 hw_phy_id_1, hw_phy_id_2;
15382 u32 hw_phy_id, hw_phy_id_masked;
15385 /* flow control autonegotiation is default behavior */
15386 tg3_flag_set(tp, PAUSE_AUTONEG);
15387 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
15389 if (tg3_flag(tp, ENABLE_APE)) {
15390 switch (tp->pci_fn) {
15392 tp->phy_ape_lock = TG3_APE_LOCK_PHY0;
15395 tp->phy_ape_lock = TG3_APE_LOCK_PHY1;
15398 tp->phy_ape_lock = TG3_APE_LOCK_PHY2;
15401 tp->phy_ape_lock = TG3_APE_LOCK_PHY3;
15406 if (!tg3_flag(tp, ENABLE_ASF) &&
15407 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15408 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
15409 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK |
15410 TG3_PHYFLG_KEEP_LINK_ON_PWRDN);
15412 if (tg3_flag(tp, USE_PHYLIB))
15413 return tg3_phy_init(tp);
15415 /* Reading the PHY ID register can conflict with ASF
15416 * firmware access to the PHY hardware.
15419 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
15420 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
15422 /* Now read the physical PHY_ID from the chip and verify
15423 * that it is sane. If it doesn't look good, we fall back
15424 * to either the hard-coded table based PHY_ID and failing
15425 * that the value found in the eeprom area.
15427 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
15428 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
15430 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
15431 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
15432 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
15434 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
15437 if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
15438 tp->phy_id = hw_phy_id;
15439 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
15440 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15442 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
15444 if (tp->phy_id != TG3_PHY_ID_INVALID) {
15445 /* Do nothing, phy ID already set up in
15446 * tg3_get_eeprom_hw_cfg().
15449 struct subsys_tbl_ent *p;
15451 /* No eeprom signature? Try the hardcoded
15452 * subsys device table.
15454 p = tg3_lookup_by_subsys(tp);
15456 tp->phy_id = p->phy_id;
15457 } else if (!tg3_flag(tp, IS_SSB_CORE)) {
15458 /* For now we saw the IDs 0xbc050cd0,
15459 * 0xbc050f80 and 0xbc050c30 on devices
15460 * connected to an BCM4785 and there are
15461 * probably more. Just assume that the phy is
15462 * supported when it is connected to a SSB core
15469 tp->phy_id == TG3_PHY_ID_BCM8002)
15470 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
15474 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15475 (tg3_asic_rev(tp) == ASIC_REV_5719 ||
15476 tg3_asic_rev(tp) == ASIC_REV_5720 ||
15477 tg3_asic_rev(tp) == ASIC_REV_57766 ||
15478 tg3_asic_rev(tp) == ASIC_REV_5762 ||
15479 (tg3_asic_rev(tp) == ASIC_REV_5717 &&
15480 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) ||
15481 (tg3_asic_rev(tp) == ASIC_REV_57765 &&
15482 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) {
15483 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
15485 tp->eee.supported = SUPPORTED_100baseT_Full |
15486 SUPPORTED_1000baseT_Full;
15487 tp->eee.advertised = ADVERTISED_100baseT_Full |
15488 ADVERTISED_1000baseT_Full;
15489 tp->eee.eee_enabled = 1;
15490 tp->eee.tx_lpi_enabled = 1;
15491 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US;
15494 tg3_phy_init_link_config(tp);
15496 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) &&
15497 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
15498 !tg3_flag(tp, ENABLE_APE) &&
15499 !tg3_flag(tp, ENABLE_ASF)) {
15502 tg3_readphy(tp, MII_BMSR, &bmsr);
15503 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
15504 (bmsr & BMSR_LSTATUS))
15505 goto skip_phy_reset;
15507 err = tg3_phy_reset(tp);
15511 tg3_phy_set_wirespeed(tp);
15513 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) {
15514 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
15515 tp->link_config.flowctrl);
15517 tg3_writephy(tp, MII_BMCR,
15518 BMCR_ANENABLE | BMCR_ANRESTART);
15523 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
15524 err = tg3_init_5401phy_dsp(tp);
15528 err = tg3_init_5401phy_dsp(tp);
15534 static void tg3_read_vpd(struct tg3 *tp)
15537 unsigned int block_end, rosize, len;
15541 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen);
15545 i = pci_vpd_find_tag(vpd_data, 0, vpdlen, PCI_VPD_LRDT_RO_DATA);
15547 goto out_not_found;
15549 rosize = pci_vpd_lrdt_size(&vpd_data[i]);
15550 block_end = i + PCI_VPD_LRDT_TAG_SIZE + rosize;
15551 i += PCI_VPD_LRDT_TAG_SIZE;
15553 if (block_end > vpdlen)
15554 goto out_not_found;
15556 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15557 PCI_VPD_RO_KEYWORD_MFR_ID);
15559 len = pci_vpd_info_field_size(&vpd_data[j]);
15561 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15562 if (j + len > block_end || len != 4 ||
15563 memcmp(&vpd_data[j], "1028", 4))
15566 j = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15567 PCI_VPD_RO_KEYWORD_VENDOR0);
15571 len = pci_vpd_info_field_size(&vpd_data[j]);
15573 j += PCI_VPD_INFO_FLD_HDR_SIZE;
15574 if (j + len > block_end)
15577 if (len >= sizeof(tp->fw_ver))
15578 len = sizeof(tp->fw_ver) - 1;
15579 memset(tp->fw_ver, 0, sizeof(tp->fw_ver));
15580 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len,
15585 i = pci_vpd_find_info_keyword(vpd_data, i, rosize,
15586 PCI_VPD_RO_KEYWORD_PARTNO);
15588 goto out_not_found;
15590 len = pci_vpd_info_field_size(&vpd_data[i]);
15592 i += PCI_VPD_INFO_FLD_HDR_SIZE;
15593 if (len > TG3_BPN_SIZE ||
15594 (len + i) > vpdlen)
15595 goto out_not_found;
15597 memcpy(tp->board_part_number, &vpd_data[i], len);
15601 if (tp->board_part_number[0])
15605 if (tg3_asic_rev(tp) == ASIC_REV_5717) {
15606 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
15607 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C)
15608 strcpy(tp->board_part_number, "BCM5717");
15609 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718)
15610 strcpy(tp->board_part_number, "BCM5718");
15613 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) {
15614 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
15615 strcpy(tp->board_part_number, "BCM57780");
15616 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
15617 strcpy(tp->board_part_number, "BCM57760");
15618 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
15619 strcpy(tp->board_part_number, "BCM57790");
15620 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
15621 strcpy(tp->board_part_number, "BCM57788");
15624 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) {
15625 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761)
15626 strcpy(tp->board_part_number, "BCM57761");
15627 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765)
15628 strcpy(tp->board_part_number, "BCM57765");
15629 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781)
15630 strcpy(tp->board_part_number, "BCM57781");
15631 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785)
15632 strcpy(tp->board_part_number, "BCM57785");
15633 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791)
15634 strcpy(tp->board_part_number, "BCM57791");
15635 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
15636 strcpy(tp->board_part_number, "BCM57795");
15639 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) {
15640 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762)
15641 strcpy(tp->board_part_number, "BCM57762");
15642 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766)
15643 strcpy(tp->board_part_number, "BCM57766");
15644 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782)
15645 strcpy(tp->board_part_number, "BCM57782");
15646 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
15647 strcpy(tp->board_part_number, "BCM57786");
15650 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) {
15651 strcpy(tp->board_part_number, "BCM95906");
15654 strcpy(tp->board_part_number, "none");
15658 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
15662 if (tg3_nvram_read(tp, offset, &val) ||
15663 (val & 0xfc000000) != 0x0c000000 ||
15664 tg3_nvram_read(tp, offset + 4, &val) ||
15671 static void tg3_read_bc_ver(struct tg3 *tp)
15673 u32 val, offset, start, ver_offset;
15675 bool newver = false;
15677 if (tg3_nvram_read(tp, 0xc, &offset) ||
15678 tg3_nvram_read(tp, 0x4, &start))
15681 offset = tg3_nvram_logical_addr(tp, offset);
15683 if (tg3_nvram_read(tp, offset, &val))
15686 if ((val & 0xfc000000) == 0x0c000000) {
15687 if (tg3_nvram_read(tp, offset + 4, &val))
15694 dst_off = strlen(tp->fw_ver);
15697 if (TG3_VER_SIZE - dst_off < 16 ||
15698 tg3_nvram_read(tp, offset + 8, &ver_offset))
15701 offset = offset + ver_offset - start;
15702 for (i = 0; i < 16; i += 4) {
15704 if (tg3_nvram_read_be32(tp, offset + i, &v))
15707 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v));
15712 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
15715 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
15716 TG3_NVM_BCVER_MAJSFT;
15717 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
15718 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off,
15719 "v%d.%02d", major, minor);
15723 static void tg3_read_hwsb_ver(struct tg3 *tp)
15725 u32 val, major, minor;
15727 /* Use native endian representation */
15728 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
15731 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
15732 TG3_NVM_HWSB_CFG1_MAJSFT;
15733 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
15734 TG3_NVM_HWSB_CFG1_MINSFT;
15736 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
15739 static void tg3_read_sb_ver(struct tg3 *tp, u32 val)
15741 u32 offset, major, minor, build;
15743 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1);
15745 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
15748 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
15749 case TG3_EEPROM_SB_REVISION_0:
15750 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
15752 case TG3_EEPROM_SB_REVISION_2:
15753 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
15755 case TG3_EEPROM_SB_REVISION_3:
15756 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
15758 case TG3_EEPROM_SB_REVISION_4:
15759 offset = TG3_EEPROM_SB_F1R4_EDH_OFF;
15761 case TG3_EEPROM_SB_REVISION_5:
15762 offset = TG3_EEPROM_SB_F1R5_EDH_OFF;
15764 case TG3_EEPROM_SB_REVISION_6:
15765 offset = TG3_EEPROM_SB_F1R6_EDH_OFF;
15771 if (tg3_nvram_read(tp, offset, &val))
15774 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
15775 TG3_EEPROM_SB_EDH_BLD_SHFT;
15776 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
15777 TG3_EEPROM_SB_EDH_MAJ_SHFT;
15778 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
15780 if (minor > 99 || build > 26)
15783 offset = strlen(tp->fw_ver);
15784 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset,
15785 " v%d.%02d", major, minor);
15788 offset = strlen(tp->fw_ver);
15789 if (offset < TG3_VER_SIZE - 1)
15790 tp->fw_ver[offset] = 'a' + build - 1;
15794 static void tg3_read_mgmtfw_ver(struct tg3 *tp)
15796 u32 val, offset, start;
15799 for (offset = TG3_NVM_DIR_START;
15800 offset < TG3_NVM_DIR_END;
15801 offset += TG3_NVM_DIRENT_SIZE) {
15802 if (tg3_nvram_read(tp, offset, &val))
15805 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
15809 if (offset == TG3_NVM_DIR_END)
15812 if (!tg3_flag(tp, 5705_PLUS))
15813 start = 0x08000000;
15814 else if (tg3_nvram_read(tp, offset - 4, &start))
15817 if (tg3_nvram_read(tp, offset + 4, &offset) ||
15818 !tg3_fw_img_is_valid(tp, offset) ||
15819 tg3_nvram_read(tp, offset + 8, &val))
15822 offset += val - start;
15824 vlen = strlen(tp->fw_ver);
15826 tp->fw_ver[vlen++] = ',';
15827 tp->fw_ver[vlen++] = ' ';
15829 for (i = 0; i < 4; i++) {
15831 if (tg3_nvram_read_be32(tp, offset, &v))
15834 offset += sizeof(v);
15836 if (vlen > TG3_VER_SIZE - sizeof(v)) {
15837 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
15841 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
15846 static void tg3_probe_ncsi(struct tg3 *tp)
15850 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
15851 if (apedata != APE_SEG_SIG_MAGIC)
15854 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
15855 if (!(apedata & APE_FW_STATUS_READY))
15858 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI)
15859 tg3_flag_set(tp, APE_HAS_NCSI);
15862 static void tg3_read_dash_ver(struct tg3 *tp)
15868 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
15870 if (tg3_flag(tp, APE_HAS_NCSI))
15872 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725)
15877 vlen = strlen(tp->fw_ver);
15879 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d",
15881 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
15882 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
15883 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
15884 (apedata & APE_FW_VERSION_BLDMSK));
15887 static void tg3_read_otp_ver(struct tg3 *tp)
15891 if (tg3_asic_rev(tp) != ASIC_REV_5762)
15894 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) &&
15895 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) &&
15896 TG3_OTP_MAGIC0_VALID(val)) {
15897 u64 val64 = (u64) val << 32 | val2;
15901 for (i = 0; i < 7; i++) {
15902 if ((val64 & 0xff) == 0)
15904 ver = val64 & 0xff;
15907 vlen = strlen(tp->fw_ver);
15908 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver);
15912 static void tg3_read_fw_ver(struct tg3 *tp)
15915 bool vpd_vers = false;
15917 if (tp->fw_ver[0] != 0)
15920 if (tg3_flag(tp, NO_NVRAM)) {
15921 strcat(tp->fw_ver, "sb");
15922 tg3_read_otp_ver(tp);
15926 if (tg3_nvram_read(tp, 0, &val))
15929 if (val == TG3_EEPROM_MAGIC)
15930 tg3_read_bc_ver(tp);
15931 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
15932 tg3_read_sb_ver(tp, val);
15933 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
15934 tg3_read_hwsb_ver(tp);
15936 if (tg3_flag(tp, ENABLE_ASF)) {
15937 if (tg3_flag(tp, ENABLE_APE)) {
15938 tg3_probe_ncsi(tp);
15940 tg3_read_dash_ver(tp);
15941 } else if (!vpd_vers) {
15942 tg3_read_mgmtfw_ver(tp);
15946 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
15949 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp)
15951 if (tg3_flag(tp, LRG_PROD_RING_CAP))
15952 return TG3_RX_RET_MAX_SIZE_5717;
15953 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))
15954 return TG3_RX_RET_MAX_SIZE_5700;
15956 return TG3_RX_RET_MAX_SIZE_5705;
15959 static const struct pci_device_id tg3_write_reorder_chipsets[] = {
15960 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C) },
15961 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE) },
15962 { PCI_DEVICE(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8385_0) },
15966 static struct pci_dev *tg3_find_peer(struct tg3 *tp)
15968 struct pci_dev *peer;
15969 unsigned int func, devnr = tp->pdev->devfn & ~7;
15971 for (func = 0; func < 8; func++) {
15972 peer = pci_get_slot(tp->pdev->bus, devnr | func);
15973 if (peer && peer != tp->pdev)
15977 /* 5704 can be configured in single-port mode, set peer to
15978 * tp->pdev in that case.
15986 * We don't need to keep the refcount elevated; there's no way
15987 * to remove one half of this device without removing the other
15994 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg)
15996 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT;
15997 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) {
16000 /* All devices that use the alternate
16001 * ASIC REV location have a CPMU.
16003 tg3_flag_set(tp, CPMU_PRESENT);
16005 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
16006 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
16007 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
16008 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
16009 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
16010 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
16011 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
16012 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
16013 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
16014 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
16015 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787)
16016 reg = TG3PCI_GEN2_PRODID_ASICREV;
16017 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
16018 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
16019 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
16020 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
16021 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
16022 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 ||
16023 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 ||
16024 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 ||
16025 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 ||
16026 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786)
16027 reg = TG3PCI_GEN15_PRODID_ASICREV;
16029 reg = TG3PCI_PRODID_ASICREV;
16031 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id);
16034 /* Wrong chip ID in 5752 A0. This code can be removed later
16035 * as A0 is not in production.
16037 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW)
16038 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
16040 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0)
16041 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0;
16043 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16044 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16045 tg3_asic_rev(tp) == ASIC_REV_5720)
16046 tg3_flag_set(tp, 5717_PLUS);
16048 if (tg3_asic_rev(tp) == ASIC_REV_57765 ||
16049 tg3_asic_rev(tp) == ASIC_REV_57766)
16050 tg3_flag_set(tp, 57765_CLASS);
16052 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) ||
16053 tg3_asic_rev(tp) == ASIC_REV_5762)
16054 tg3_flag_set(tp, 57765_PLUS);
16056 /* Intentionally exclude ASIC_REV_5906 */
16057 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16058 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16059 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16060 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16061 tg3_asic_rev(tp) == ASIC_REV_5785 ||
16062 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16063 tg3_flag(tp, 57765_PLUS))
16064 tg3_flag_set(tp, 5755_PLUS);
16066 if (tg3_asic_rev(tp) == ASIC_REV_5780 ||
16067 tg3_asic_rev(tp) == ASIC_REV_5714)
16068 tg3_flag_set(tp, 5780_CLASS);
16070 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16071 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16072 tg3_asic_rev(tp) == ASIC_REV_5906 ||
16073 tg3_flag(tp, 5755_PLUS) ||
16074 tg3_flag(tp, 5780_CLASS))
16075 tg3_flag_set(tp, 5750_PLUS);
16077 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
16078 tg3_flag(tp, 5750_PLUS))
16079 tg3_flag_set(tp, 5705_PLUS);
16082 static bool tg3_10_100_only_device(struct tg3 *tp,
16083 const struct pci_device_id *ent)
16085 u32 grc_misc_cfg = tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK;
16087 if ((tg3_asic_rev(tp) == ASIC_REV_5703 &&
16088 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
16089 (tp->phy_flags & TG3_PHYFLG_IS_FET))
16092 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) {
16093 if (tg3_asic_rev(tp) == ASIC_REV_5705) {
16094 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100)
16104 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent)
16107 u32 pci_state_reg, grc_misc_cfg;
16112 /* Force memory write invalidate off. If we leave it on,
16113 * then on 5700_BX chips we have to enable a workaround.
16114 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
16115 * to match the cacheline size. The Broadcom driver have this
16116 * workaround but turns MWI off all the times so never uses
16117 * it. This seems to suggest that the workaround is insufficient.
16119 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16120 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
16121 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16123 /* Important! -- Make sure register accesses are byteswapped
16124 * correctly. Also, for those chips that require it, make
16125 * sure that indirect register accesses are enabled before
16126 * the first operation.
16128 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16130 tp->misc_host_ctrl |= (misc_ctrl_reg &
16131 MISC_HOST_CTRL_CHIPREV);
16132 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16133 tp->misc_host_ctrl);
16135 tg3_detect_asic_rev(tp, misc_ctrl_reg);
16137 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
16138 * we need to disable memory and use config. cycles
16139 * only to access all registers. The 5702/03 chips
16140 * can mistakenly decode the special cycles from the
16141 * ICH chipsets as memory write cycles, causing corruption
16142 * of register and memory space. Only certain ICH bridges
16143 * will drive special cycles with non-zero data during the
16144 * address phase which can fall within the 5703's address
16145 * range. This is not an ICH bug as the PCI spec allows
16146 * non-zero address during special cycles. However, only
16147 * these ICH bridges are known to drive non-zero addresses
16148 * during special cycles.
16150 * Since special cycles do not cross PCI bridges, we only
16151 * enable this workaround if the 5703 is on the secondary
16152 * bus of these ICH bridges.
16154 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) ||
16155 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) {
16156 static struct tg3_dev_id {
16160 } ich_chipsets[] = {
16161 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
16163 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
16165 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
16167 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
16171 struct tg3_dev_id *pci_id = &ich_chipsets[0];
16172 struct pci_dev *bridge = NULL;
16174 while (pci_id->vendor != 0) {
16175 bridge = pci_get_device(pci_id->vendor, pci_id->device,
16181 if (pci_id->rev != PCI_ANY_ID) {
16182 if (bridge->revision > pci_id->rev)
16185 if (bridge->subordinate &&
16186 (bridge->subordinate->number ==
16187 tp->pdev->bus->number)) {
16188 tg3_flag_set(tp, ICH_WORKAROUND);
16189 pci_dev_put(bridge);
16195 if (tg3_asic_rev(tp) == ASIC_REV_5701) {
16196 static struct tg3_dev_id {
16199 } bridge_chipsets[] = {
16200 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
16201 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
16204 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
16205 struct pci_dev *bridge = NULL;
16207 while (pci_id->vendor != 0) {
16208 bridge = pci_get_device(pci_id->vendor,
16215 if (bridge->subordinate &&
16216 (bridge->subordinate->number <=
16217 tp->pdev->bus->number) &&
16218 (bridge->subordinate->busn_res.end >=
16219 tp->pdev->bus->number)) {
16220 tg3_flag_set(tp, 5701_DMA_BUG);
16221 pci_dev_put(bridge);
16227 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
16228 * DMA addresses > 40-bit. This bridge may have other additional
16229 * 57xx devices behind it in some 4-port NIC designs for example.
16230 * Any tg3 device found behind the bridge will also need the 40-bit
16233 if (tg3_flag(tp, 5780_CLASS)) {
16234 tg3_flag_set(tp, 40BIT_DMA_BUG);
16235 tp->msi_cap = tp->pdev->msi_cap;
16237 struct pci_dev *bridge = NULL;
16240 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
16241 PCI_DEVICE_ID_SERVERWORKS_EPB,
16243 if (bridge && bridge->subordinate &&
16244 (bridge->subordinate->number <=
16245 tp->pdev->bus->number) &&
16246 (bridge->subordinate->busn_res.end >=
16247 tp->pdev->bus->number)) {
16248 tg3_flag_set(tp, 40BIT_DMA_BUG);
16249 pci_dev_put(bridge);
16255 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16256 tg3_asic_rev(tp) == ASIC_REV_5714)
16257 tp->pdev_peer = tg3_find_peer(tp);
16259 /* Determine TSO capabilities */
16260 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0)
16261 ; /* Do nothing. HW bug. */
16262 else if (tg3_flag(tp, 57765_PLUS))
16263 tg3_flag_set(tp, HW_TSO_3);
16264 else if (tg3_flag(tp, 5755_PLUS) ||
16265 tg3_asic_rev(tp) == ASIC_REV_5906)
16266 tg3_flag_set(tp, HW_TSO_2);
16267 else if (tg3_flag(tp, 5750_PLUS)) {
16268 tg3_flag_set(tp, HW_TSO_1);
16269 tg3_flag_set(tp, TSO_BUG);
16270 if (tg3_asic_rev(tp) == ASIC_REV_5750 &&
16271 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2)
16272 tg3_flag_clear(tp, TSO_BUG);
16273 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
16274 tg3_asic_rev(tp) != ASIC_REV_5701 &&
16275 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) {
16276 tg3_flag_set(tp, FW_TSO);
16277 tg3_flag_set(tp, TSO_BUG);
16278 if (tg3_asic_rev(tp) == ASIC_REV_5705)
16279 tp->fw_needed = FIRMWARE_TG3TSO5;
16281 tp->fw_needed = FIRMWARE_TG3TSO;
16284 /* Selectively allow TSO based on operating conditions */
16285 if (tg3_flag(tp, HW_TSO_1) ||
16286 tg3_flag(tp, HW_TSO_2) ||
16287 tg3_flag(tp, HW_TSO_3) ||
16288 tg3_flag(tp, FW_TSO)) {
16289 /* For firmware TSO, assume ASF is disabled.
16290 * We'll disable TSO later if we discover ASF
16291 * is enabled in tg3_get_eeprom_hw_cfg().
16293 tg3_flag_set(tp, TSO_CAPABLE);
16295 tg3_flag_clear(tp, TSO_CAPABLE);
16296 tg3_flag_clear(tp, TSO_BUG);
16297 tp->fw_needed = NULL;
16300 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0)
16301 tp->fw_needed = FIRMWARE_TG3;
16303 if (tg3_asic_rev(tp) == ASIC_REV_57766)
16304 tp->fw_needed = FIRMWARE_TG357766;
16308 if (tg3_flag(tp, 5750_PLUS)) {
16309 tg3_flag_set(tp, SUPPORT_MSI);
16310 if (tg3_chip_rev(tp) == CHIPREV_5750_AX ||
16311 tg3_chip_rev(tp) == CHIPREV_5750_BX ||
16312 (tg3_asic_rev(tp) == ASIC_REV_5714 &&
16313 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 &&
16314 tp->pdev_peer == tp->pdev))
16315 tg3_flag_clear(tp, SUPPORT_MSI);
16317 if (tg3_flag(tp, 5755_PLUS) ||
16318 tg3_asic_rev(tp) == ASIC_REV_5906) {
16319 tg3_flag_set(tp, 1SHOT_MSI);
16322 if (tg3_flag(tp, 57765_PLUS)) {
16323 tg3_flag_set(tp, SUPPORT_MSIX);
16324 tp->irq_max = TG3_IRQ_MAX_VECS;
16330 if (tp->irq_max > 1) {
16331 tp->rxq_max = TG3_RSS_MAX_NUM_QS;
16332 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS);
16334 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
16335 tg3_asic_rev(tp) == ASIC_REV_5720)
16336 tp->txq_max = tp->irq_max - 1;
16339 if (tg3_flag(tp, 5755_PLUS) ||
16340 tg3_asic_rev(tp) == ASIC_REV_5906)
16341 tg3_flag_set(tp, SHORT_DMA_BUG);
16343 if (tg3_asic_rev(tp) == ASIC_REV_5719)
16344 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K;
16346 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16347 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16348 tg3_asic_rev(tp) == ASIC_REV_5720 ||
16349 tg3_asic_rev(tp) == ASIC_REV_5762)
16350 tg3_flag_set(tp, LRG_PROD_RING_CAP);
16352 if (tg3_flag(tp, 57765_PLUS) &&
16353 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0)
16354 tg3_flag_set(tp, USE_JUMBO_BDFLAG);
16356 if (!tg3_flag(tp, 5705_PLUS) ||
16357 tg3_flag(tp, 5780_CLASS) ||
16358 tg3_flag(tp, USE_JUMBO_BDFLAG))
16359 tg3_flag_set(tp, JUMBO_CAPABLE);
16361 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16364 if (pci_is_pcie(tp->pdev)) {
16367 tg3_flag_set(tp, PCI_EXPRESS);
16369 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl);
16370 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
16371 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16372 tg3_flag_clear(tp, HW_TSO_2);
16373 tg3_flag_clear(tp, TSO_CAPABLE);
16375 if (tg3_asic_rev(tp) == ASIC_REV_5784 ||
16376 tg3_asic_rev(tp) == ASIC_REV_5761 ||
16377 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 ||
16378 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1)
16379 tg3_flag_set(tp, CLKREQ_BUG);
16380 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) {
16381 tg3_flag_set(tp, L1PLLPD_EN);
16383 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) {
16384 /* BCM5785 devices are effectively PCIe devices, and should
16385 * follow PCIe codepaths, but do not have a PCIe capabilities
16388 tg3_flag_set(tp, PCI_EXPRESS);
16389 } else if (!tg3_flag(tp, 5705_PLUS) ||
16390 tg3_flag(tp, 5780_CLASS)) {
16391 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
16392 if (!tp->pcix_cap) {
16393 dev_err(&tp->pdev->dev,
16394 "Cannot find PCI-X capability, aborting\n");
16398 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
16399 tg3_flag_set(tp, PCIX_MODE);
16402 /* If we have an AMD 762 or VIA K8T800 chipset, write
16403 * reordering to the mailbox registers done by the host
16404 * controller can cause major troubles. We read back from
16405 * every mailbox register write to force the writes to be
16406 * posted to the chip in order.
16408 if (pci_dev_present(tg3_write_reorder_chipsets) &&
16409 !tg3_flag(tp, PCI_EXPRESS))
16410 tg3_flag_set(tp, MBOX_WRITE_REORDER);
16412 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
16413 &tp->pci_cacheline_sz);
16414 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16415 &tp->pci_lat_timer);
16416 if (tg3_asic_rev(tp) == ASIC_REV_5703 &&
16417 tp->pci_lat_timer < 64) {
16418 tp->pci_lat_timer = 64;
16419 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
16420 tp->pci_lat_timer);
16423 /* Important! -- It is critical that the PCI-X hw workaround
16424 * situation is decided before the first MMIO register access.
16426 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) {
16427 /* 5700 BX chips need to have their TX producer index
16428 * mailboxes written twice to workaround a bug.
16430 tg3_flag_set(tp, TXD_MBOX_HWBUG);
16432 /* If we are in PCI-X mode, enable register write workaround.
16434 * The workaround is to use indirect register accesses
16435 * for all chip writes not to mailbox registers.
16437 if (tg3_flag(tp, PCIX_MODE)) {
16440 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16442 /* The chip can have it's power management PCI config
16443 * space registers clobbered due to this bug.
16444 * So explicitly force the chip into D0 here.
16446 pci_read_config_dword(tp->pdev,
16447 tp->pdev->pm_cap + PCI_PM_CTRL,
16449 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
16450 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
16451 pci_write_config_dword(tp->pdev,
16452 tp->pdev->pm_cap + PCI_PM_CTRL,
16455 /* Also, force SERR#/PERR# in PCI command. */
16456 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16457 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
16458 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16462 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
16463 tg3_flag_set(tp, PCI_HIGH_SPEED);
16464 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
16465 tg3_flag_set(tp, PCI_32BIT);
16467 /* Chip-specific fixup from Broadcom driver */
16468 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) &&
16469 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
16470 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
16471 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
16474 /* Default fast path register access methods */
16475 tp->read32 = tg3_read32;
16476 tp->write32 = tg3_write32;
16477 tp->read32_mbox = tg3_read32;
16478 tp->write32_mbox = tg3_write32;
16479 tp->write32_tx_mbox = tg3_write32;
16480 tp->write32_rx_mbox = tg3_write32;
16482 /* Various workaround register access methods */
16483 if (tg3_flag(tp, PCIX_TARGET_HWBUG))
16484 tp->write32 = tg3_write_indirect_reg32;
16485 else if (tg3_asic_rev(tp) == ASIC_REV_5701 ||
16486 (tg3_flag(tp, PCI_EXPRESS) &&
16487 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) {
16489 * Back to back register writes can cause problems on these
16490 * chips, the workaround is to read back all reg writes
16491 * except those to mailbox regs.
16493 * See tg3_write_indirect_reg32().
16495 tp->write32 = tg3_write_flush_reg32;
16498 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) {
16499 tp->write32_tx_mbox = tg3_write32_tx_mbox;
16500 if (tg3_flag(tp, MBOX_WRITE_REORDER))
16501 tp->write32_rx_mbox = tg3_write_flush_reg32;
16504 if (tg3_flag(tp, ICH_WORKAROUND)) {
16505 tp->read32 = tg3_read_indirect_reg32;
16506 tp->write32 = tg3_write_indirect_reg32;
16507 tp->read32_mbox = tg3_read_indirect_mbox;
16508 tp->write32_mbox = tg3_write_indirect_mbox;
16509 tp->write32_tx_mbox = tg3_write_indirect_mbox;
16510 tp->write32_rx_mbox = tg3_write_indirect_mbox;
16515 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
16516 pci_cmd &= ~PCI_COMMAND_MEMORY;
16517 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
16519 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
16520 tp->read32_mbox = tg3_read32_mbox_5906;
16521 tp->write32_mbox = tg3_write32_mbox_5906;
16522 tp->write32_tx_mbox = tg3_write32_mbox_5906;
16523 tp->write32_rx_mbox = tg3_write32_mbox_5906;
16526 if (tp->write32 == tg3_write_indirect_reg32 ||
16527 (tg3_flag(tp, PCIX_MODE) &&
16528 (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16529 tg3_asic_rev(tp) == ASIC_REV_5701)))
16530 tg3_flag_set(tp, SRAM_USE_CONFIG);
16532 /* The memory arbiter has to be enabled in order for SRAM accesses
16533 * to succeed. Normally on powerup the tg3 chip firmware will make
16534 * sure it is enabled, but other entities such as system netboot
16535 * code might disable it.
16537 val = tr32(MEMARB_MODE);
16538 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
16540 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3;
16541 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16542 tg3_flag(tp, 5780_CLASS)) {
16543 if (tg3_flag(tp, PCIX_MODE)) {
16544 pci_read_config_dword(tp->pdev,
16545 tp->pcix_cap + PCI_X_STATUS,
16547 tp->pci_fn = val & 0x7;
16549 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16550 tg3_asic_rev(tp) == ASIC_REV_5719 ||
16551 tg3_asic_rev(tp) == ASIC_REV_5720) {
16552 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val);
16553 if ((val & NIC_SRAM_CPMUSTAT_SIG_MSK) != NIC_SRAM_CPMUSTAT_SIG)
16554 val = tr32(TG3_CPMU_STATUS);
16556 if (tg3_asic_rev(tp) == ASIC_REV_5717)
16557 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0;
16559 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >>
16560 TG3_CPMU_STATUS_FSHFT_5719;
16563 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) {
16564 tp->write32_tx_mbox = tg3_write_flush_reg32;
16565 tp->write32_rx_mbox = tg3_write_flush_reg32;
16568 /* Get eeprom hw config before calling tg3_set_power_state().
16569 * In particular, the TG3_FLAG_IS_NIC flag must be
16570 * determined before calling tg3_set_power_state() so that
16571 * we know whether or not to switch out of Vaux power.
16572 * When the flag is set, it means that GPIO1 is used for eeprom
16573 * write protect and also implies that it is a LOM where GPIOs
16574 * are not used to switch power.
16576 tg3_get_eeprom_hw_cfg(tp);
16578 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) {
16579 tg3_flag_clear(tp, TSO_CAPABLE);
16580 tg3_flag_clear(tp, TSO_BUG);
16581 tp->fw_needed = NULL;
16584 if (tg3_flag(tp, ENABLE_APE)) {
16585 /* Allow reads and writes to the
16586 * APE register and memory space.
16588 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
16589 PCISTATE_ALLOW_APE_SHMEM_WR |
16590 PCISTATE_ALLOW_APE_PSPACE_WR;
16591 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
16594 tg3_ape_lock_init(tp);
16597 /* Set up tp->grc_local_ctrl before calling
16598 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16599 * will bring 5700's external PHY out of reset.
16600 * It is also used as eeprom write protect on LOMs.
16602 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
16603 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16604 tg3_flag(tp, EEPROM_WRITE_PROT))
16605 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
16606 GRC_LCLCTRL_GPIO_OUTPUT1);
16607 /* Unused GPIO3 must be driven as output on 5752 because there
16608 * are no pull-up resistors on unused GPIO pins.
16610 else if (tg3_asic_rev(tp) == ASIC_REV_5752)
16611 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
16613 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16614 tg3_asic_rev(tp) == ASIC_REV_57780 ||
16615 tg3_flag(tp, 57765_CLASS))
16616 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16618 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
16619 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
16620 /* Turn off the debug UART. */
16621 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
16622 if (tg3_flag(tp, IS_NIC))
16623 /* Keep VMain power. */
16624 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
16625 GRC_LCLCTRL_GPIO_OUTPUT0;
16628 if (tg3_asic_rev(tp) == ASIC_REV_5762)
16629 tp->grc_local_ctrl |=
16630 tr32(GRC_LOCAL_CTRL) & GRC_LCLCTRL_GPIO_UART_SEL;
16632 /* Switch out of Vaux if it is a NIC */
16633 tg3_pwrsrc_switch_to_vmain(tp);
16635 /* Derive initial jumbo mode from MTU assigned in
16636 * ether_setup() via the alloc_etherdev() call
16638 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS))
16639 tg3_flag_set(tp, JUMBO_RING_ENABLE);
16641 /* Determine WakeOnLan speed to use. */
16642 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16643 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16644 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16645 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) {
16646 tg3_flag_clear(tp, WOL_SPEED_100MB);
16648 tg3_flag_set(tp, WOL_SPEED_100MB);
16651 if (tg3_asic_rev(tp) == ASIC_REV_5906)
16652 tp->phy_flags |= TG3_PHYFLG_IS_FET;
16654 /* A few boards don't want Ethernet@WireSpeed phy feature */
16655 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
16656 (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16657 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) &&
16658 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) ||
16659 (tp->phy_flags & TG3_PHYFLG_IS_FET) ||
16660 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
16661 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED;
16663 if (tg3_chip_rev(tp) == CHIPREV_5703_AX ||
16664 tg3_chip_rev(tp) == CHIPREV_5704_AX)
16665 tp->phy_flags |= TG3_PHYFLG_ADC_BUG;
16666 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0)
16667 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG;
16669 if (tg3_flag(tp, 5705_PLUS) &&
16670 !(tp->phy_flags & TG3_PHYFLG_IS_FET) &&
16671 tg3_asic_rev(tp) != ASIC_REV_5785 &&
16672 tg3_asic_rev(tp) != ASIC_REV_57780 &&
16673 !tg3_flag(tp, 57765_PLUS)) {
16674 if (tg3_asic_rev(tp) == ASIC_REV_5755 ||
16675 tg3_asic_rev(tp) == ASIC_REV_5787 ||
16676 tg3_asic_rev(tp) == ASIC_REV_5784 ||
16677 tg3_asic_rev(tp) == ASIC_REV_5761) {
16678 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
16679 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
16680 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG;
16681 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
16682 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM;
16684 tp->phy_flags |= TG3_PHYFLG_BER_BUG;
16687 if (tg3_asic_rev(tp) == ASIC_REV_5784 &&
16688 tg3_chip_rev(tp) != CHIPREV_5784_AX) {
16689 tp->phy_otp = tg3_read_otp_phycfg(tp);
16690 if (tp->phy_otp == 0)
16691 tp->phy_otp = TG3_OTP_DEFAULT;
16694 if (tg3_flag(tp, CPMU_PRESENT))
16695 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
16697 tp->mi_mode = MAC_MI_MODE_BASE;
16699 tp->coalesce_mode = 0;
16700 if (tg3_chip_rev(tp) != CHIPREV_5700_AX &&
16701 tg3_chip_rev(tp) != CHIPREV_5700_BX)
16702 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
16704 /* Set these bits to enable statistics workaround. */
16705 if (tg3_asic_rev(tp) == ASIC_REV_5717 ||
16706 tg3_asic_rev(tp) == ASIC_REV_5762 ||
16707 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 ||
16708 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) {
16709 tp->coalesce_mode |= HOSTCC_MODE_ATTN;
16710 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN;
16713 if (tg3_asic_rev(tp) == ASIC_REV_5785 ||
16714 tg3_asic_rev(tp) == ASIC_REV_57780)
16715 tg3_flag_set(tp, USE_PHYLIB);
16717 err = tg3_mdio_init(tp);
16721 /* Initialize data/descriptor byte/word swapping. */
16722 val = tr32(GRC_MODE);
16723 if (tg3_asic_rev(tp) == ASIC_REV_5720 ||
16724 tg3_asic_rev(tp) == ASIC_REV_5762)
16725 val &= (GRC_MODE_BYTE_SWAP_B2HRX_DATA |
16726 GRC_MODE_WORD_SWAP_B2HRX_DATA |
16727 GRC_MODE_B2HRX_ENABLE |
16728 GRC_MODE_HTX2B_ENABLE |
16729 GRC_MODE_HOST_STACKUP);
16731 val &= GRC_MODE_HOST_STACKUP;
16733 tw32(GRC_MODE, val | tp->grc_mode);
16735 tg3_switch_clocks(tp);
16737 /* Clear this out for sanity. */
16738 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
16740 /* Clear TG3PCI_REG_BASE_ADDR to prevent hangs. */
16741 tw32(TG3PCI_REG_BASE_ADDR, 0);
16743 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
16745 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
16746 !tg3_flag(tp, PCIX_TARGET_HWBUG)) {
16747 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 ||
16748 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 ||
16749 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 ||
16750 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) {
16751 void __iomem *sram_base;
16753 /* Write some dummy words into the SRAM status block
16754 * area, see if it reads back correctly. If the return
16755 * value is bad, force enable the PCIX workaround.
16757 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
16759 writel(0x00000000, sram_base);
16760 writel(0x00000000, sram_base + 4);
16761 writel(0xffffffff, sram_base + 4);
16762 if (readl(sram_base) != 0x00000000)
16763 tg3_flag_set(tp, PCIX_TARGET_HWBUG);
16768 tg3_nvram_init(tp);
16770 /* If the device has an NVRAM, no need to load patch firmware */
16771 if (tg3_asic_rev(tp) == ASIC_REV_57766 &&
16772 !tg3_flag(tp, NO_NVRAM))
16773 tp->fw_needed = NULL;
16775 grc_misc_cfg = tr32(GRC_MISC_CFG);
16776 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
16778 if (tg3_asic_rev(tp) == ASIC_REV_5705 &&
16779 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
16780 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
16781 tg3_flag_set(tp, IS_5788);
16783 if (!tg3_flag(tp, IS_5788) &&
16784 tg3_asic_rev(tp) != ASIC_REV_5700)
16785 tg3_flag_set(tp, TAGGED_STATUS);
16786 if (tg3_flag(tp, TAGGED_STATUS)) {
16787 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
16788 HOSTCC_MODE_CLRTICK_TXBD);
16790 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
16791 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
16792 tp->misc_host_ctrl);
16795 /* Preserve the APE MAC_MODE bits */
16796 if (tg3_flag(tp, ENABLE_APE))
16797 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
16801 if (tg3_10_100_only_device(tp, ent))
16802 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY;
16804 err = tg3_phy_probe(tp);
16806 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err);
16807 /* ... but do not return immediately ... */
16812 tg3_read_fw_ver(tp);
16814 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) {
16815 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16817 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16818 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16820 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT;
16823 /* 5700 {AX,BX} chips have a broken status block link
16824 * change bit implementation, so we must use the
16825 * status register in those cases.
16827 if (tg3_asic_rev(tp) == ASIC_REV_5700)
16828 tg3_flag_set(tp, USE_LINKCHG_REG);
16830 tg3_flag_clear(tp, USE_LINKCHG_REG);
16832 /* The led_ctrl is set during tg3_phy_probe, here we might
16833 * have to force the link status polling mechanism based
16834 * upon subsystem IDs.
16836 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
16837 tg3_asic_rev(tp) == ASIC_REV_5701 &&
16838 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) {
16839 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT;
16840 tg3_flag_set(tp, USE_LINKCHG_REG);
16843 /* For all SERDES we poll the MAC status register. */
16844 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
16845 tg3_flag_set(tp, POLL_SERDES);
16847 tg3_flag_clear(tp, POLL_SERDES);
16849 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF))
16850 tg3_flag_set(tp, POLL_CPMU_LINK);
16852 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN;
16853 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD;
16854 if (tg3_asic_rev(tp) == ASIC_REV_5701 &&
16855 tg3_flag(tp, PCIX_MODE)) {
16856 tp->rx_offset = NET_SKB_PAD;
16857 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16858 tp->rx_copy_thresh = ~(u16)0;
16862 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1;
16863 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1;
16864 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1;
16866 tp->rx_std_max_post = tp->rx_std_ring_mask + 1;
16868 /* Increment the rx prod index on the rx std ring by at most
16869 * 8 for these chips to workaround hw errata.
16871 if (tg3_asic_rev(tp) == ASIC_REV_5750 ||
16872 tg3_asic_rev(tp) == ASIC_REV_5752 ||
16873 tg3_asic_rev(tp) == ASIC_REV_5755)
16874 tp->rx_std_max_post = 8;
16876 if (tg3_flag(tp, ASPM_WORKAROUND))
16877 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
16878 PCIE_PWR_MGMT_L1_THRESH_MSK;
16883 #ifdef CONFIG_SPARC
16884 static int tg3_get_macaddr_sparc(struct tg3 *tp)
16886 struct net_device *dev = tp->dev;
16887 struct pci_dev *pdev = tp->pdev;
16888 struct device_node *dp = pci_device_to_OF_node(pdev);
16889 const unsigned char *addr;
16892 addr = of_get_property(dp, "local-mac-address", &len);
16893 if (addr && len == ETH_ALEN) {
16894 memcpy(dev->dev_addr, addr, ETH_ALEN);
16900 static int tg3_get_default_macaddr_sparc(struct tg3 *tp)
16902 struct net_device *dev = tp->dev;
16904 memcpy(dev->dev_addr, idprom->id_ethaddr, ETH_ALEN);
16909 static int tg3_get_device_address(struct tg3 *tp)
16911 struct net_device *dev = tp->dev;
16912 u32 hi, lo, mac_offset;
16916 #ifdef CONFIG_SPARC
16917 if (!tg3_get_macaddr_sparc(tp))
16921 if (tg3_flag(tp, IS_SSB_CORE)) {
16922 err = ssb_gige_get_macaddr(tp->pdev, &dev->dev_addr[0]);
16923 if (!err && is_valid_ether_addr(&dev->dev_addr[0]))
16928 if (tg3_asic_rev(tp) == ASIC_REV_5704 ||
16929 tg3_flag(tp, 5780_CLASS)) {
16930 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
16932 if (tg3_nvram_lock(tp))
16933 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
16935 tg3_nvram_unlock(tp);
16936 } else if (tg3_flag(tp, 5717_PLUS)) {
16937 if (tp->pci_fn & 1)
16939 if (tp->pci_fn > 1)
16940 mac_offset += 0x18c;
16941 } else if (tg3_asic_rev(tp) == ASIC_REV_5906)
16944 /* First try to get it from MAC address mailbox. */
16945 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
16946 if ((hi >> 16) == 0x484b) {
16947 dev->dev_addr[0] = (hi >> 8) & 0xff;
16948 dev->dev_addr[1] = (hi >> 0) & 0xff;
16950 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
16951 dev->dev_addr[2] = (lo >> 24) & 0xff;
16952 dev->dev_addr[3] = (lo >> 16) & 0xff;
16953 dev->dev_addr[4] = (lo >> 8) & 0xff;
16954 dev->dev_addr[5] = (lo >> 0) & 0xff;
16956 /* Some old bootcode may report a 0 MAC address in SRAM */
16957 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
16960 /* Next, try NVRAM. */
16961 if (!tg3_flag(tp, NO_NVRAM) &&
16962 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
16963 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
16964 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
16965 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
16967 /* Finally just fetch it out of the MAC control regs. */
16969 hi = tr32(MAC_ADDR_0_HIGH);
16970 lo = tr32(MAC_ADDR_0_LOW);
16972 dev->dev_addr[5] = lo & 0xff;
16973 dev->dev_addr[4] = (lo >> 8) & 0xff;
16974 dev->dev_addr[3] = (lo >> 16) & 0xff;
16975 dev->dev_addr[2] = (lo >> 24) & 0xff;
16976 dev->dev_addr[1] = hi & 0xff;
16977 dev->dev_addr[0] = (hi >> 8) & 0xff;
16981 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
16982 #ifdef CONFIG_SPARC
16983 if (!tg3_get_default_macaddr_sparc(tp))
16991 #define BOUNDARY_SINGLE_CACHELINE 1
16992 #define BOUNDARY_MULTI_CACHELINE 2
16994 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
16996 int cacheline_size;
17000 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
17002 cacheline_size = 1024;
17004 cacheline_size = (int) byte * 4;
17006 /* On 5703 and later chips, the boundary bits have no
17009 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17010 tg3_asic_rev(tp) != ASIC_REV_5701 &&
17011 !tg3_flag(tp, PCI_EXPRESS))
17014 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
17015 goal = BOUNDARY_MULTI_CACHELINE;
17017 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
17018 goal = BOUNDARY_SINGLE_CACHELINE;
17024 if (tg3_flag(tp, 57765_PLUS)) {
17025 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
17032 /* PCI controllers on most RISC systems tend to disconnect
17033 * when a device tries to burst across a cache-line boundary.
17034 * Therefore, letting tg3 do so just wastes PCI bandwidth.
17036 * Unfortunately, for PCI-E there are only limited
17037 * write-side controls for this, and thus for reads
17038 * we will still get the disconnects. We'll also waste
17039 * these PCI cycles for both read and write for chips
17040 * other than 5700 and 5701 which do not implement the
17043 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) {
17044 switch (cacheline_size) {
17049 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17050 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
17051 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
17053 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17054 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17059 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
17060 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
17064 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
17065 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
17068 } else if (tg3_flag(tp, PCI_EXPRESS)) {
17069 switch (cacheline_size) {
17073 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17074 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17075 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
17081 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
17082 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
17086 switch (cacheline_size) {
17088 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17089 val |= (DMA_RWCTRL_READ_BNDRY_16 |
17090 DMA_RWCTRL_WRITE_BNDRY_16);
17095 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17096 val |= (DMA_RWCTRL_READ_BNDRY_32 |
17097 DMA_RWCTRL_WRITE_BNDRY_32);
17102 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17103 val |= (DMA_RWCTRL_READ_BNDRY_64 |
17104 DMA_RWCTRL_WRITE_BNDRY_64);
17109 if (goal == BOUNDARY_SINGLE_CACHELINE) {
17110 val |= (DMA_RWCTRL_READ_BNDRY_128 |
17111 DMA_RWCTRL_WRITE_BNDRY_128);
17116 val |= (DMA_RWCTRL_READ_BNDRY_256 |
17117 DMA_RWCTRL_WRITE_BNDRY_256);
17120 val |= (DMA_RWCTRL_READ_BNDRY_512 |
17121 DMA_RWCTRL_WRITE_BNDRY_512);
17125 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
17126 DMA_RWCTRL_WRITE_BNDRY_1024);
17135 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma,
17136 int size, bool to_device)
17138 struct tg3_internal_buffer_desc test_desc;
17139 u32 sram_dma_descs;
17142 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
17144 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
17145 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
17146 tw32(RDMAC_STATUS, 0);
17147 tw32(WDMAC_STATUS, 0);
17149 tw32(BUFMGR_MODE, 0);
17150 tw32(FTQ_RESET, 0);
17152 test_desc.addr_hi = ((u64) buf_dma) >> 32;
17153 test_desc.addr_lo = buf_dma & 0xffffffff;
17154 test_desc.nic_mbuf = 0x00002100;
17155 test_desc.len = size;
17158 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
17159 * the *second* time the tg3 driver was getting loaded after an
17162 * Broadcom tells me:
17163 * ...the DMA engine is connected to the GRC block and a DMA
17164 * reset may affect the GRC block in some unpredictable way...
17165 * The behavior of resets to individual blocks has not been tested.
17167 * Broadcom noted the GRC reset will also reset all sub-components.
17170 test_desc.cqid_sqid = (13 << 8) | 2;
17172 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17175 test_desc.cqid_sqid = (16 << 8) | 7;
17177 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
17180 test_desc.flags = 0x00000005;
17182 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
17185 val = *(((u32 *)&test_desc) + i);
17186 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
17187 sram_dma_descs + (i * sizeof(u32)));
17188 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
17190 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
17193 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
17195 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
17198 for (i = 0; i < 40; i++) {
17202 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
17204 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
17205 if ((val & 0xffff) == sram_dma_descs) {
17216 #define TEST_BUFFER_SIZE 0x2000
17218 static const struct pci_device_id tg3_dma_wait_state_chipsets[] = {
17219 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
17223 static int tg3_test_dma(struct tg3 *tp)
17225 dma_addr_t buf_dma;
17226 u32 *buf, saved_dma_rwctrl;
17229 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE,
17230 &buf_dma, GFP_KERNEL);
17236 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
17237 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
17239 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
17241 if (tg3_flag(tp, 57765_PLUS))
17244 if (tg3_flag(tp, PCI_EXPRESS)) {
17245 /* DMA read watermark not used on PCIE */
17246 tp->dma_rwctrl |= 0x00180000;
17247 } else if (!tg3_flag(tp, PCIX_MODE)) {
17248 if (tg3_asic_rev(tp) == ASIC_REV_5705 ||
17249 tg3_asic_rev(tp) == ASIC_REV_5750)
17250 tp->dma_rwctrl |= 0x003f0000;
17252 tp->dma_rwctrl |= 0x003f000f;
17254 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17255 tg3_asic_rev(tp) == ASIC_REV_5704) {
17256 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
17257 u32 read_water = 0x7;
17259 /* If the 5704 is behind the EPB bridge, we can
17260 * do the less restrictive ONE_DMA workaround for
17261 * better performance.
17263 if (tg3_flag(tp, 40BIT_DMA_BUG) &&
17264 tg3_asic_rev(tp) == ASIC_REV_5704)
17265 tp->dma_rwctrl |= 0x8000;
17266 else if (ccval == 0x6 || ccval == 0x7)
17267 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17269 if (tg3_asic_rev(tp) == ASIC_REV_5703)
17271 /* Set bit 23 to enable PCIX hw bug fix */
17273 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
17274 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
17276 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) {
17277 /* 5780 always in PCIX mode */
17278 tp->dma_rwctrl |= 0x00144000;
17279 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) {
17280 /* 5714 always in PCIX mode */
17281 tp->dma_rwctrl |= 0x00148000;
17283 tp->dma_rwctrl |= 0x001b000f;
17286 if (tg3_flag(tp, ONE_DMA_AT_ONCE))
17287 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
17289 if (tg3_asic_rev(tp) == ASIC_REV_5703 ||
17290 tg3_asic_rev(tp) == ASIC_REV_5704)
17291 tp->dma_rwctrl &= 0xfffffff0;
17293 if (tg3_asic_rev(tp) == ASIC_REV_5700 ||
17294 tg3_asic_rev(tp) == ASIC_REV_5701) {
17295 /* Remove this if it causes problems for some boards. */
17296 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
17298 /* On 5700/5701 chips, we need to set this bit.
17299 * Otherwise the chip will issue cacheline transactions
17300 * to streamable DMA memory with not all the byte
17301 * enables turned on. This is an error on several
17302 * RISC PCI controllers, in particular sparc64.
17304 * On 5703/5704 chips, this bit has been reassigned
17305 * a different meaning. In particular, it is used
17306 * on those chips to enable a PCI-X workaround.
17308 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
17311 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17314 if (tg3_asic_rev(tp) != ASIC_REV_5700 &&
17315 tg3_asic_rev(tp) != ASIC_REV_5701)
17318 /* It is best to perform DMA test with maximum write burst size
17319 * to expose the 5700/5701 write DMA bug.
17321 saved_dma_rwctrl = tp->dma_rwctrl;
17322 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17323 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17328 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
17331 /* Send the buffer to the chip. */
17332 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true);
17334 dev_err(&tp->pdev->dev,
17335 "%s: Buffer write failed. err = %d\n",
17340 /* Now read it back. */
17341 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false);
17343 dev_err(&tp->pdev->dev, "%s: Buffer read failed. "
17344 "err = %d\n", __func__, ret);
17349 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
17353 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17354 DMA_RWCTRL_WRITE_BNDRY_16) {
17355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17356 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17357 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17360 dev_err(&tp->pdev->dev,
17361 "%s: Buffer corrupted on read back! "
17362 "(%d != %d)\n", __func__, p[i], i);
17368 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
17374 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
17375 DMA_RWCTRL_WRITE_BNDRY_16) {
17376 /* DMA test passed without adjusting DMA boundary,
17377 * now look for chipsets that are known to expose the
17378 * DMA bug without failing the test.
17380 if (pci_dev_present(tg3_dma_wait_state_chipsets)) {
17381 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
17382 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
17384 /* Safe to use the calculated DMA boundary. */
17385 tp->dma_rwctrl = saved_dma_rwctrl;
17388 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
17392 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma);
17397 static void tg3_init_bufmgr_config(struct tg3 *tp)
17399 if (tg3_flag(tp, 57765_PLUS)) {
17400 tp->bufmgr_config.mbuf_read_dma_low_water =
17401 DEFAULT_MB_RDMA_LOW_WATER_5705;
17402 tp->bufmgr_config.mbuf_mac_rx_low_water =
17403 DEFAULT_MB_MACRX_LOW_WATER_57765;
17404 tp->bufmgr_config.mbuf_high_water =
17405 DEFAULT_MB_HIGH_WATER_57765;
17407 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17408 DEFAULT_MB_RDMA_LOW_WATER_5705;
17409 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17410 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
17411 tp->bufmgr_config.mbuf_high_water_jumbo =
17412 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
17413 } else if (tg3_flag(tp, 5705_PLUS)) {
17414 tp->bufmgr_config.mbuf_read_dma_low_water =
17415 DEFAULT_MB_RDMA_LOW_WATER_5705;
17416 tp->bufmgr_config.mbuf_mac_rx_low_water =
17417 DEFAULT_MB_MACRX_LOW_WATER_5705;
17418 tp->bufmgr_config.mbuf_high_water =
17419 DEFAULT_MB_HIGH_WATER_5705;
17420 if (tg3_asic_rev(tp) == ASIC_REV_5906) {
17421 tp->bufmgr_config.mbuf_mac_rx_low_water =
17422 DEFAULT_MB_MACRX_LOW_WATER_5906;
17423 tp->bufmgr_config.mbuf_high_water =
17424 DEFAULT_MB_HIGH_WATER_5906;
17427 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17428 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
17429 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17430 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
17431 tp->bufmgr_config.mbuf_high_water_jumbo =
17432 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
17434 tp->bufmgr_config.mbuf_read_dma_low_water =
17435 DEFAULT_MB_RDMA_LOW_WATER;
17436 tp->bufmgr_config.mbuf_mac_rx_low_water =
17437 DEFAULT_MB_MACRX_LOW_WATER;
17438 tp->bufmgr_config.mbuf_high_water =
17439 DEFAULT_MB_HIGH_WATER;
17441 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
17442 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
17443 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
17444 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
17445 tp->bufmgr_config.mbuf_high_water_jumbo =
17446 DEFAULT_MB_HIGH_WATER_JUMBO;
17449 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
17450 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
17453 static char *tg3_phy_string(struct tg3 *tp)
17455 switch (tp->phy_id & TG3_PHY_ID_MASK) {
17456 case TG3_PHY_ID_BCM5400: return "5400";
17457 case TG3_PHY_ID_BCM5401: return "5401";
17458 case TG3_PHY_ID_BCM5411: return "5411";
17459 case TG3_PHY_ID_BCM5701: return "5701";
17460 case TG3_PHY_ID_BCM5703: return "5703";
17461 case TG3_PHY_ID_BCM5704: return "5704";
17462 case TG3_PHY_ID_BCM5705: return "5705";
17463 case TG3_PHY_ID_BCM5750: return "5750";
17464 case TG3_PHY_ID_BCM5752: return "5752";
17465 case TG3_PHY_ID_BCM5714: return "5714";
17466 case TG3_PHY_ID_BCM5780: return "5780";
17467 case TG3_PHY_ID_BCM5755: return "5755";
17468 case TG3_PHY_ID_BCM5787: return "5787";
17469 case TG3_PHY_ID_BCM5784: return "5784";
17470 case TG3_PHY_ID_BCM5756: return "5722/5756";
17471 case TG3_PHY_ID_BCM5906: return "5906";
17472 case TG3_PHY_ID_BCM5761: return "5761";
17473 case TG3_PHY_ID_BCM5718C: return "5718C";
17474 case TG3_PHY_ID_BCM5718S: return "5718S";
17475 case TG3_PHY_ID_BCM57765: return "57765";
17476 case TG3_PHY_ID_BCM5719C: return "5719C";
17477 case TG3_PHY_ID_BCM5720C: return "5720C";
17478 case TG3_PHY_ID_BCM5762: return "5762C";
17479 case TG3_PHY_ID_BCM8002: return "8002/serdes";
17480 case 0: return "serdes";
17481 default: return "unknown";
17485 static char *tg3_bus_string(struct tg3 *tp, char *str)
17487 if (tg3_flag(tp, PCI_EXPRESS)) {
17488 strcpy(str, "PCI Express");
17490 } else if (tg3_flag(tp, PCIX_MODE)) {
17491 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
17493 strcpy(str, "PCIX:");
17495 if ((clock_ctrl == 7) ||
17496 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
17497 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
17498 strcat(str, "133MHz");
17499 else if (clock_ctrl == 0)
17500 strcat(str, "33MHz");
17501 else if (clock_ctrl == 2)
17502 strcat(str, "50MHz");
17503 else if (clock_ctrl == 4)
17504 strcat(str, "66MHz");
17505 else if (clock_ctrl == 6)
17506 strcat(str, "100MHz");
17508 strcpy(str, "PCI:");
17509 if (tg3_flag(tp, PCI_HIGH_SPEED))
17510 strcat(str, "66MHz");
17512 strcat(str, "33MHz");
17514 if (tg3_flag(tp, PCI_32BIT))
17515 strcat(str, ":32-bit");
17517 strcat(str, ":64-bit");
17521 static void tg3_init_coal(struct tg3 *tp)
17523 struct ethtool_coalesce *ec = &tp->coal;
17525 memset(ec, 0, sizeof(*ec));
17526 ec->cmd = ETHTOOL_GCOALESCE;
17527 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
17528 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
17529 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
17530 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
17531 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
17532 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
17533 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
17534 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
17535 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
17537 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
17538 HOSTCC_MODE_CLRTICK_TXBD)) {
17539 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
17540 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
17541 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
17542 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
17545 if (tg3_flag(tp, 5705_PLUS)) {
17546 ec->rx_coalesce_usecs_irq = 0;
17547 ec->tx_coalesce_usecs_irq = 0;
17548 ec->stats_block_coalesce_usecs = 0;
17552 static int tg3_init_one(struct pci_dev *pdev,
17553 const struct pci_device_id *ent)
17555 struct net_device *dev;
17558 u32 sndmbx, rcvmbx, intmbx;
17560 u64 dma_mask, persist_dma_mask;
17561 netdev_features_t features = 0;
17563 printk_once(KERN_INFO "%s\n", version);
17565 err = pci_enable_device(pdev);
17567 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
17571 err = pci_request_regions(pdev, DRV_MODULE_NAME);
17573 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
17574 goto err_out_disable_pdev;
17577 pci_set_master(pdev);
17579 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
17582 goto err_out_free_res;
17585 SET_NETDEV_DEV(dev, &pdev->dev);
17587 tp = netdev_priv(dev);
17590 tp->rx_mode = TG3_DEF_RX_MODE;
17591 tp->tx_mode = TG3_DEF_TX_MODE;
17593 tp->pcierr_recovery = false;
17596 tp->msg_enable = tg3_debug;
17598 tp->msg_enable = TG3_DEF_MSG_ENABLE;
17600 if (pdev_is_ssb_gige_core(pdev)) {
17601 tg3_flag_set(tp, IS_SSB_CORE);
17602 if (ssb_gige_must_flush_posted_writes(pdev))
17603 tg3_flag_set(tp, FLUSH_POSTED_WRITES);
17604 if (ssb_gige_one_dma_at_once(pdev))
17605 tg3_flag_set(tp, ONE_DMA_AT_ONCE);
17606 if (ssb_gige_have_roboswitch(pdev)) {
17607 tg3_flag_set(tp, USE_PHYLIB);
17608 tg3_flag_set(tp, ROBOSWITCH);
17610 if (ssb_gige_is_rgmii(pdev))
17611 tg3_flag_set(tp, RGMII_MODE);
17614 /* The word/byte swap controls here control register access byte
17615 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17618 tp->misc_host_ctrl =
17619 MISC_HOST_CTRL_MASK_PCI_INT |
17620 MISC_HOST_CTRL_WORD_SWAP |
17621 MISC_HOST_CTRL_INDIR_ACCESS |
17622 MISC_HOST_CTRL_PCISTATE_RW;
17624 /* The NONFRM (non-frame) byte/word swap controls take effect
17625 * on descriptor entries, anything which isn't packet data.
17627 * The StrongARM chips on the board (one for tx, one for rx)
17628 * are running in big-endian mode.
17630 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
17631 GRC_MODE_WSWAP_NONFRM_DATA);
17632 #ifdef __BIG_ENDIAN
17633 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
17635 spin_lock_init(&tp->lock);
17636 spin_lock_init(&tp->indirect_lock);
17637 INIT_WORK(&tp->reset_task, tg3_reset_task);
17639 tp->regs = pci_ioremap_bar(pdev, BAR_0);
17641 dev_err(&pdev->dev, "Cannot map device registers, aborting\n");
17643 goto err_out_free_dev;
17646 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
17647 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E ||
17648 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S ||
17649 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE ||
17650 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
17651 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C ||
17652 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
17653 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 ||
17654 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 ||
17655 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 ||
17656 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 ||
17657 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 ||
17658 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 ||
17659 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 ||
17660 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) {
17661 tg3_flag_set(tp, ENABLE_APE);
17662 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
17663 if (!tp->aperegs) {
17664 dev_err(&pdev->dev,
17665 "Cannot map APE registers, aborting\n");
17667 goto err_out_iounmap;
17671 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
17672 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
17674 dev->ethtool_ops = &tg3_ethtool_ops;
17675 dev->watchdog_timeo = TG3_TX_TIMEOUT;
17676 dev->netdev_ops = &tg3_netdev_ops;
17677 dev->irq = pdev->irq;
17679 err = tg3_get_invariants(tp, ent);
17681 dev_err(&pdev->dev,
17682 "Problem fetching invariants of chip, aborting\n");
17683 goto err_out_apeunmap;
17686 /* The EPB bridge inside 5714, 5715, and 5780 and any
17687 * device behind the EPB cannot support DMA addresses > 40-bit.
17688 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17689 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17690 * do DMA address check in tg3_start_xmit().
17692 if (tg3_flag(tp, IS_5788))
17693 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
17694 else if (tg3_flag(tp, 40BIT_DMA_BUG)) {
17695 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
17696 #ifdef CONFIG_HIGHMEM
17697 dma_mask = DMA_BIT_MASK(64);
17700 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
17702 /* Configure DMA attributes. */
17703 if (dma_mask > DMA_BIT_MASK(32)) {
17704 err = pci_set_dma_mask(pdev, dma_mask);
17706 features |= NETIF_F_HIGHDMA;
17707 err = pci_set_consistent_dma_mask(pdev,
17710 dev_err(&pdev->dev, "Unable to obtain 64 bit "
17711 "DMA for consistent allocations\n");
17712 goto err_out_apeunmap;
17716 if (err || dma_mask == DMA_BIT_MASK(32)) {
17717 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
17719 dev_err(&pdev->dev,
17720 "No usable DMA configuration, aborting\n");
17721 goto err_out_apeunmap;
17725 tg3_init_bufmgr_config(tp);
17727 /* 5700 B0 chips do not support checksumming correctly due
17728 * to hardware bugs.
17730 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) {
17731 features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
17733 if (tg3_flag(tp, 5755_PLUS))
17734 features |= NETIF_F_IPV6_CSUM;
17737 /* TSO is on by default on chips that support hardware TSO.
17738 * Firmware TSO on older chips gives lower performance, so it
17739 * is off by default, but can be enabled using ethtool.
17741 if ((tg3_flag(tp, HW_TSO_1) ||
17742 tg3_flag(tp, HW_TSO_2) ||
17743 tg3_flag(tp, HW_TSO_3)) &&
17744 (features & NETIF_F_IP_CSUM))
17745 features |= NETIF_F_TSO;
17746 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) {
17747 if (features & NETIF_F_IPV6_CSUM)
17748 features |= NETIF_F_TSO6;
17749 if (tg3_flag(tp, HW_TSO_3) ||
17750 tg3_asic_rev(tp) == ASIC_REV_5761 ||
17751 (tg3_asic_rev(tp) == ASIC_REV_5784 &&
17752 tg3_chip_rev(tp) != CHIPREV_5784_AX) ||
17753 tg3_asic_rev(tp) == ASIC_REV_5785 ||
17754 tg3_asic_rev(tp) == ASIC_REV_57780)
17755 features |= NETIF_F_TSO_ECN;
17758 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX |
17759 NETIF_F_HW_VLAN_CTAG_RX;
17760 dev->vlan_features |= features;
17763 * Add loopback capability only for a subset of devices that support
17764 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17765 * loopback for the remaining devices.
17767 if (tg3_asic_rev(tp) != ASIC_REV_5780 &&
17768 !tg3_flag(tp, CPMU_PRESENT))
17769 /* Add the loopback capability */
17770 features |= NETIF_F_LOOPBACK;
17772 dev->hw_features |= features;
17773 dev->priv_flags |= IFF_UNICAST_FLT;
17775 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 &&
17776 !tg3_flag(tp, TSO_CAPABLE) &&
17777 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
17778 tg3_flag_set(tp, MAX_RXPEND_64);
17779 tp->rx_pending = 63;
17782 err = tg3_get_device_address(tp);
17784 dev_err(&pdev->dev,
17785 "Could not obtain valid ethernet address, aborting\n");
17786 goto err_out_apeunmap;
17790 * Reset chip in case UNDI or EFI driver did not shutdown
17791 * DMA self test will enable WDMAC and we'll see (spurious)
17792 * pending DMA on the PCI bus at that point.
17794 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
17795 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
17796 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
17797 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17800 err = tg3_test_dma(tp);
17802 dev_err(&pdev->dev, "DMA engine test failed, aborting\n");
17803 goto err_out_apeunmap;
17806 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
17807 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
17808 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
17809 for (i = 0; i < tp->irq_max; i++) {
17810 struct tg3_napi *tnapi = &tp->napi[i];
17813 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
17815 tnapi->int_mbox = intmbx;
17821 tnapi->consmbox = rcvmbx;
17822 tnapi->prodmbox = sndmbx;
17825 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
17827 tnapi->coal_now = HOSTCC_MODE_NOW;
17829 if (!tg3_flag(tp, SUPPORT_MSIX))
17833 * If we support MSIX, we'll be using RSS. If we're using
17834 * RSS, the first vector only handles link interrupts and the
17835 * remaining vectors handle rx and tx interrupts. Reuse the
17836 * mailbox values for the next iteration. The values we setup
17837 * above are still useful for the single vectored mode.
17852 pci_set_drvdata(pdev, dev);
17854 if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
17855 tg3_asic_rev(tp) == ASIC_REV_5720 ||
17856 tg3_asic_rev(tp) == ASIC_REV_5762)
17857 tg3_flag_set(tp, PTP_CAPABLE);
17859 tg3_timer_init(tp);
17861 tg3_carrier_off(tp);
17863 err = register_netdev(dev);
17865 dev_err(&pdev->dev, "Cannot register net device, aborting\n");
17866 goto err_out_apeunmap;
17869 netdev_info(dev, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17870 tp->board_part_number,
17871 tg3_chip_rev_id(tp),
17872 tg3_bus_string(tp, str),
17875 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) {
17876 struct phy_device *phydev;
17877 phydev = tp->mdio_bus->phy_map[tp->phy_addr];
17879 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17880 phydev->drv->name, dev_name(&phydev->dev));
17884 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
17885 ethtype = "10/100Base-TX";
17886 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
17887 ethtype = "1000Base-SX";
17889 ethtype = "10/100/1000Base-T";
17891 netdev_info(dev, "attached PHY is %s (%s Ethernet) "
17892 "(WireSpeed[%d], EEE[%d])\n",
17893 tg3_phy_string(tp), ethtype,
17894 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0,
17895 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0);
17898 netdev_info(dev, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17899 (dev->features & NETIF_F_RXCSUM) != 0,
17900 tg3_flag(tp, USE_LINKCHG_REG) != 0,
17901 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0,
17902 tg3_flag(tp, ENABLE_ASF) != 0,
17903 tg3_flag(tp, TSO_CAPABLE) != 0);
17904 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17906 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 :
17907 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64);
17909 pci_save_state(pdev);
17915 iounmap(tp->aperegs);
17916 tp->aperegs = NULL;
17929 pci_release_regions(pdev);
17931 err_out_disable_pdev:
17932 if (pci_is_enabled(pdev))
17933 pci_disable_device(pdev);
17937 static void tg3_remove_one(struct pci_dev *pdev)
17939 struct net_device *dev = pci_get_drvdata(pdev);
17942 struct tg3 *tp = netdev_priv(dev);
17944 release_firmware(tp->fw);
17946 tg3_reset_task_cancel(tp);
17948 if (tg3_flag(tp, USE_PHYLIB)) {
17953 unregister_netdev(dev);
17955 iounmap(tp->aperegs);
17956 tp->aperegs = NULL;
17963 pci_release_regions(pdev);
17964 pci_disable_device(pdev);
17968 #ifdef CONFIG_PM_SLEEP
17969 static int tg3_suspend(struct device *device)
17971 struct pci_dev *pdev = to_pci_dev(device);
17972 struct net_device *dev = pci_get_drvdata(pdev);
17973 struct tg3 *tp = netdev_priv(dev);
17978 if (!netif_running(dev))
17981 tg3_reset_task_cancel(tp);
17983 tg3_netif_stop(tp);
17985 tg3_timer_stop(tp);
17987 tg3_full_lock(tp, 1);
17988 tg3_disable_ints(tp);
17989 tg3_full_unlock(tp);
17991 netif_device_detach(dev);
17993 tg3_full_lock(tp, 0);
17994 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
17995 tg3_flag_clear(tp, INIT_COMPLETE);
17996 tg3_full_unlock(tp);
17998 err = tg3_power_down_prepare(tp);
18002 tg3_full_lock(tp, 0);
18004 tg3_flag_set(tp, INIT_COMPLETE);
18005 err2 = tg3_restart_hw(tp, true);
18009 tg3_timer_start(tp);
18011 netif_device_attach(dev);
18012 tg3_netif_start(tp);
18015 tg3_full_unlock(tp);
18026 static int tg3_resume(struct device *device)
18028 struct pci_dev *pdev = to_pci_dev(device);
18029 struct net_device *dev = pci_get_drvdata(pdev);
18030 struct tg3 *tp = netdev_priv(dev);
18035 if (!netif_running(dev))
18038 netif_device_attach(dev);
18040 tg3_full_lock(tp, 0);
18042 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18044 tg3_flag_set(tp, INIT_COMPLETE);
18045 err = tg3_restart_hw(tp,
18046 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN));
18050 tg3_timer_start(tp);
18052 tg3_netif_start(tp);
18055 tg3_full_unlock(tp);
18064 #endif /* CONFIG_PM_SLEEP */
18066 static SIMPLE_DEV_PM_OPS(tg3_pm_ops, tg3_suspend, tg3_resume);
18068 static void tg3_shutdown(struct pci_dev *pdev)
18070 struct net_device *dev = pci_get_drvdata(pdev);
18071 struct tg3 *tp = netdev_priv(dev);
18074 netif_device_detach(dev);
18076 if (netif_running(dev))
18079 if (system_state == SYSTEM_POWER_OFF)
18080 tg3_power_down(tp);
18086 * tg3_io_error_detected - called when PCI error is detected
18087 * @pdev: Pointer to PCI device
18088 * @state: The current pci connection state
18090 * This function is called after a PCI bus error affecting
18091 * this device has been detected.
18093 static pci_ers_result_t tg3_io_error_detected(struct pci_dev *pdev,
18094 pci_channel_state_t state)
18096 struct net_device *netdev = pci_get_drvdata(pdev);
18097 struct tg3 *tp = netdev_priv(netdev);
18098 pci_ers_result_t err = PCI_ERS_RESULT_NEED_RESET;
18100 netdev_info(netdev, "PCI I/O error detected\n");
18104 tp->pcierr_recovery = true;
18106 /* We probably don't have netdev yet */
18107 if (!netdev || !netif_running(netdev))
18112 tg3_netif_stop(tp);
18114 tg3_timer_stop(tp);
18116 /* Want to make sure that the reset task doesn't run */
18117 tg3_reset_task_cancel(tp);
18119 netif_device_detach(netdev);
18121 /* Clean up software state, even if MMIO is blocked */
18122 tg3_full_lock(tp, 0);
18123 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
18124 tg3_full_unlock(tp);
18127 if (state == pci_channel_io_perm_failure) {
18129 tg3_napi_enable(tp);
18132 err = PCI_ERS_RESULT_DISCONNECT;
18134 pci_disable_device(pdev);
18143 * tg3_io_slot_reset - called after the pci bus has been reset.
18144 * @pdev: Pointer to PCI device
18146 * Restart the card from scratch, as if from a cold-boot.
18147 * At this point, the card has exprienced a hard reset,
18148 * followed by fixups by BIOS, and has its config space
18149 * set up identically to what it was at cold boot.
18151 static pci_ers_result_t tg3_io_slot_reset(struct pci_dev *pdev)
18153 struct net_device *netdev = pci_get_drvdata(pdev);
18154 struct tg3 *tp = netdev_priv(netdev);
18155 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
18160 if (pci_enable_device(pdev)) {
18161 dev_err(&pdev->dev,
18162 "Cannot re-enable PCI device after reset.\n");
18166 pci_set_master(pdev);
18167 pci_restore_state(pdev);
18168 pci_save_state(pdev);
18170 if (!netdev || !netif_running(netdev)) {
18171 rc = PCI_ERS_RESULT_RECOVERED;
18175 err = tg3_power_up(tp);
18179 rc = PCI_ERS_RESULT_RECOVERED;
18182 if (rc != PCI_ERS_RESULT_RECOVERED && netdev && netif_running(netdev)) {
18183 tg3_napi_enable(tp);
18192 * tg3_io_resume - called when traffic can start flowing again.
18193 * @pdev: Pointer to PCI device
18195 * This callback is called when the error recovery driver tells
18196 * us that its OK to resume normal operation.
18198 static void tg3_io_resume(struct pci_dev *pdev)
18200 struct net_device *netdev = pci_get_drvdata(pdev);
18201 struct tg3 *tp = netdev_priv(netdev);
18206 if (!netif_running(netdev))
18209 tg3_full_lock(tp, 0);
18210 tg3_ape_driver_state_change(tp, RESET_KIND_INIT);
18211 tg3_flag_set(tp, INIT_COMPLETE);
18212 err = tg3_restart_hw(tp, true);
18214 tg3_full_unlock(tp);
18215 netdev_err(netdev, "Cannot restart hardware after reset.\n");
18219 netif_device_attach(netdev);
18221 tg3_timer_start(tp);
18223 tg3_netif_start(tp);
18225 tg3_full_unlock(tp);
18230 tp->pcierr_recovery = false;
18234 static const struct pci_error_handlers tg3_err_handler = {
18235 .error_detected = tg3_io_error_detected,
18236 .slot_reset = tg3_io_slot_reset,
18237 .resume = tg3_io_resume
18240 static struct pci_driver tg3_driver = {
18241 .name = DRV_MODULE_NAME,
18242 .id_table = tg3_pci_tbl,
18243 .probe = tg3_init_one,
18244 .remove = tg3_remove_one,
18245 .err_handler = &tg3_err_handler,
18246 .driver.pm = &tg3_pm_ops,
18247 .shutdown = tg3_shutdown,
18250 module_pci_driver(tg3_driver);