1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2007-2012 Broadcom Corporation.
13 #define TG3_64BIT_REG_HIGH 0x00UL
14 #define TG3_64BIT_REG_LOW 0x04UL
16 /* Descriptor block info. */
17 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
18 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
19 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
20 #define BDINFO_FLAGS_DISABLED 0x00000002
21 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
22 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
23 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
24 #define TG3_BDINFO_SIZE 0x10UL
26 #define TG3_RX_STD_MAX_SIZE_5700 512
27 #define TG3_RX_STD_MAX_SIZE_5717 2048
28 #define TG3_RX_JMB_MAX_SIZE_5700 256
29 #define TG3_RX_JMB_MAX_SIZE_5717 1024
30 #define TG3_RX_RET_MAX_SIZE_5700 1024
31 #define TG3_RX_RET_MAX_SIZE_5705 512
32 #define TG3_RX_RET_MAX_SIZE_5717 4096
34 #define TG3_RSS_INDIR_TBL_SIZE 128
36 /* First 256 bytes are a mirror of PCI config space. */
37 #define TG3PCI_VENDOR 0x00000000
38 #define TG3PCI_VENDOR_BROADCOM 0x14e4
39 #define TG3PCI_DEVICE 0x00000002
40 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
41 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
42 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
43 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
44 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688
45 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
46 #define TG3PCI_DEVICE_TIGON3_57780 0x1692
47 #define TG3PCI_DEVICE_TIGON3_5787M 0x1693
48 #define TG3PCI_DEVICE_TIGON3_57760 0x1690
49 #define TG3PCI_DEVICE_TIGON3_57790 0x1694
50 #define TG3PCI_DEVICE_TIGON3_57788 0x1691
51 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
52 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
53 #define TG3PCI_DEVICE_TIGON3_5717 0x1655
54 #define TG3PCI_DEVICE_TIGON3_5717_C 0x1665
55 #define TG3PCI_DEVICE_TIGON3_5718 0x1656
56 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
57 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
58 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
59 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4
60 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
61 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
62 #define TG3PCI_DEVICE_TIGON3_5719 0x1657
63 #define TG3PCI_DEVICE_TIGON3_5720 0x165f
64 #define TG3PCI_DEVICE_TIGON3_57762 0x1682
65 #define TG3PCI_DEVICE_TIGON3_57766 0x1686
66 #define TG3PCI_DEVICE_TIGON3_57786 0x16b3
67 #define TG3PCI_DEVICE_TIGON3_57782 0x16b7
68 /* 0x04 --> 0x2c unused */
69 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
70 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
71 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
72 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
73 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
74 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
75 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
76 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
77 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
78 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
79 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
80 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
81 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
82 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
83 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
84 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
85 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
86 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
87 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
88 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
89 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
90 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
91 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
92 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
93 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
94 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
95 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
96 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
97 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
98 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
99 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
100 #define TG3PCI_SUBDEVICE_ID_ACER_57780_A 0x0601
101 #define TG3PCI_SUBDEVICE_ID_ACER_57780_B 0x0612
102 #define TG3PCI_SUBDEVICE_ID_LENOVO_5787M 0x3056
104 /* 0x30 --> 0x64 unused */
105 #define TG3PCI_MSI_DATA 0x00000064
106 /* 0x66 --> 0x68 unused */
107 #define TG3PCI_MISC_HOST_CTRL 0x00000068
108 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
109 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
110 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
111 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
112 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
113 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
114 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
115 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
116 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
117 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
118 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
119 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
120 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
121 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
122 MISC_HOST_CTRL_CHIPREV_SHIFT)
123 #define CHIPREV_ID_5700_A0 0x7000
124 #define CHIPREV_ID_5700_A1 0x7001
125 #define CHIPREV_ID_5700_B0 0x7100
126 #define CHIPREV_ID_5700_B1 0x7101
127 #define CHIPREV_ID_5700_B3 0x7102
128 #define CHIPREV_ID_5700_ALTIMA 0x7104
129 #define CHIPREV_ID_5700_C0 0x7200
130 #define CHIPREV_ID_5701_A0 0x0000
131 #define CHIPREV_ID_5701_B0 0x0100
132 #define CHIPREV_ID_5701_B2 0x0102
133 #define CHIPREV_ID_5701_B5 0x0105
134 #define CHIPREV_ID_5703_A0 0x1000
135 #define CHIPREV_ID_5703_A1 0x1001
136 #define CHIPREV_ID_5703_A2 0x1002
137 #define CHIPREV_ID_5703_A3 0x1003
138 #define CHIPREV_ID_5704_A0 0x2000
139 #define CHIPREV_ID_5704_A1 0x2001
140 #define CHIPREV_ID_5704_A2 0x2002
141 #define CHIPREV_ID_5704_A3 0x2003
142 #define CHIPREV_ID_5705_A0 0x3000
143 #define CHIPREV_ID_5705_A1 0x3001
144 #define CHIPREV_ID_5705_A2 0x3002
145 #define CHIPREV_ID_5705_A3 0x3003
146 #define CHIPREV_ID_5750_A0 0x4000
147 #define CHIPREV_ID_5750_A1 0x4001
148 #define CHIPREV_ID_5750_A3 0x4003
149 #define CHIPREV_ID_5750_C2 0x4202
150 #define CHIPREV_ID_5752_A0_HW 0x5000
151 #define CHIPREV_ID_5752_A0 0x6000
152 #define CHIPREV_ID_5752_A1 0x6001
153 #define CHIPREV_ID_5714_A2 0x9002
154 #define CHIPREV_ID_5906_A1 0xc001
155 #define CHIPREV_ID_57780_A0 0x57780000
156 #define CHIPREV_ID_57780_A1 0x57780001
157 #define CHIPREV_ID_5717_A0 0x05717000
158 #define CHIPREV_ID_5717_C0 0x05717200
159 #define CHIPREV_ID_57765_A0 0x57785000
160 #define CHIPREV_ID_5719_A0 0x05719000
161 #define CHIPREV_ID_5720_A0 0x05720000
162 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
163 #define ASIC_REV_5700 0x07
164 #define ASIC_REV_5701 0x00
165 #define ASIC_REV_5703 0x01
166 #define ASIC_REV_5704 0x02
167 #define ASIC_REV_5705 0x03
168 #define ASIC_REV_5750 0x04
169 #define ASIC_REV_5752 0x06
170 #define ASIC_REV_5780 0x08
171 #define ASIC_REV_5714 0x09
172 #define ASIC_REV_5755 0x0a
173 #define ASIC_REV_5787 0x0b
174 #define ASIC_REV_5906 0x0c
175 #define ASIC_REV_USE_PROD_ID_REG 0x0f
176 #define ASIC_REV_5784 0x5784
177 #define ASIC_REV_5761 0x5761
178 #define ASIC_REV_5785 0x5785
179 #define ASIC_REV_57780 0x57780
180 #define ASIC_REV_5717 0x5717
181 #define ASIC_REV_57765 0x57785
182 #define ASIC_REV_5719 0x5719
183 #define ASIC_REV_5720 0x5720
184 #define ASIC_REV_57766 0x57766
185 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
186 #define CHIPREV_5700_AX 0x70
187 #define CHIPREV_5700_BX 0x71
188 #define CHIPREV_5700_CX 0x72
189 #define CHIPREV_5701_AX 0x00
190 #define CHIPREV_5703_AX 0x10
191 #define CHIPREV_5704_AX 0x20
192 #define CHIPREV_5704_BX 0x21
193 #define CHIPREV_5750_AX 0x40
194 #define CHIPREV_5750_BX 0x41
195 #define CHIPREV_5784_AX 0x57840
196 #define CHIPREV_5761_AX 0x57610
197 #define CHIPREV_57765_AX 0x577650
198 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
199 #define METAL_REV_A0 0x00
200 #define METAL_REV_A1 0x01
201 #define METAL_REV_B0 0x00
202 #define METAL_REV_B1 0x01
203 #define METAL_REV_B2 0x02
204 #define TG3PCI_DMA_RW_CTRL 0x0000006c
205 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
206 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
207 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
208 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
209 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
210 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
211 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
212 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
213 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
214 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
215 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
216 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
217 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
218 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
219 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
220 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
221 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
222 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
223 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
224 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
225 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
226 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
227 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
228 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
229 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
230 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
231 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
232 #define DMA_RWCTRL_ONE_DMA 0x00004000
233 #define DMA_RWCTRL_READ_WATER 0x00070000
234 #define DMA_RWCTRL_READ_WATER_SHIFT 16
235 #define DMA_RWCTRL_WRITE_WATER 0x00380000
236 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
237 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
238 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
239 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
240 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
241 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
242 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
243 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
244 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
245 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
246 #define TG3PCI_PCISTATE 0x00000070
247 #define PCISTATE_FORCE_RESET 0x00000001
248 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
249 #define PCISTATE_CONV_PCI_MODE 0x00000004
250 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
251 #define PCISTATE_BUS_32BIT 0x00000010
252 #define PCISTATE_ROM_ENABLE 0x00000020
253 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
254 #define PCISTATE_FLAT_VIEW 0x00000100
255 #define PCISTATE_RETRY_SAME_DMA 0x00002000
256 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
257 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
258 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
259 #define TG3PCI_CLOCK_CTRL 0x00000074
260 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
261 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
262 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
263 #define CLOCK_CTRL_ALTCLK 0x00001000
264 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
265 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
266 #define CLOCK_CTRL_625_CORE 0x00100000
267 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
268 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
269 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
270 #define TG3PCI_REG_BASE_ADDR 0x00000078
271 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
272 #define TG3PCI_REG_DATA 0x00000080
273 #define TG3PCI_MEM_WIN_DATA 0x00000084
274 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
275 /* 0x94 --> 0x98 unused */
276 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
277 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
278 /* 0xa8 --> 0xb8 unused */
279 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
280 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
281 #define DUAL_MAC_CTRL_ID 0x00000004
282 #define TG3PCI_PRODID_ASICREV 0x000000bc
283 #define PROD_ID_ASIC_REV_MASK 0x0fffffff
284 /* 0xc0 --> 0xf4 unused */
286 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
287 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
288 /* 0xf8 --> 0x200 unused */
290 #define TG3_CORR_ERR_STAT 0x00000110
291 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
292 /* 0x114 --> 0x200 unused */
294 /* Mailbox registers */
295 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
296 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
297 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
298 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
299 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
300 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
301 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
302 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
303 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
304 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
305 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
306 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
307 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
308 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
309 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
311 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
312 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
314 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
315 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
316 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
317 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
318 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
319 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
320 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
321 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
322 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
323 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
324 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
325 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
326 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
327 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
328 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
329 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
330 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
331 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
332 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
333 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
334 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
335 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
336 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
337 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
338 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
339 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
340 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
341 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
342 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
343 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
344 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
345 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
346 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
347 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
348 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
349 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
350 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
351 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
352 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
353 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
354 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
355 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
356 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
357 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
358 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
359 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
360 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
361 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
362 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
364 /* MAC control registers */
365 #define MAC_MODE 0x00000400
366 #define MAC_MODE_RESET 0x00000001
367 #define MAC_MODE_HALF_DUPLEX 0x00000002
368 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
369 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
370 #define MAC_MODE_PORT_MODE_GMII 0x00000008
371 #define MAC_MODE_PORT_MODE_MII 0x00000004
372 #define MAC_MODE_PORT_MODE_NONE 0x00000000
373 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
374 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
375 #define MAC_MODE_TX_BURSTING 0x00000100
376 #define MAC_MODE_MAX_DEFER 0x00000200
377 #define MAC_MODE_LINK_POLARITY 0x00000400
378 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
379 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
380 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
381 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
382 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
383 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
384 #define MAC_MODE_SEND_CONFIGS 0x00020000
385 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
386 #define MAC_MODE_ACPI_ENABLE 0x00080000
387 #define MAC_MODE_MIP_ENABLE 0x00100000
388 #define MAC_MODE_TDE_ENABLE 0x00200000
389 #define MAC_MODE_RDE_ENABLE 0x00400000
390 #define MAC_MODE_FHDE_ENABLE 0x00800000
391 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
392 #define MAC_MODE_APE_RX_EN 0x08000000
393 #define MAC_MODE_APE_TX_EN 0x10000000
394 #define MAC_STATUS 0x00000404
395 #define MAC_STATUS_PCS_SYNCED 0x00000001
396 #define MAC_STATUS_SIGNAL_DET 0x00000002
397 #define MAC_STATUS_RCVD_CFG 0x00000004
398 #define MAC_STATUS_CFG_CHANGED 0x00000008
399 #define MAC_STATUS_SYNC_CHANGED 0x00000010
400 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
401 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
402 #define MAC_STATUS_MI_COMPLETION 0x00400000
403 #define MAC_STATUS_MI_INTERRUPT 0x00800000
404 #define MAC_STATUS_AP_ERROR 0x01000000
405 #define MAC_STATUS_ODI_ERROR 0x02000000
406 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
407 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
408 #define MAC_EVENT 0x00000408
409 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
410 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
411 #define MAC_EVENT_MI_COMPLETION 0x00400000
412 #define MAC_EVENT_MI_INTERRUPT 0x00800000
413 #define MAC_EVENT_AP_ERROR 0x01000000
414 #define MAC_EVENT_ODI_ERROR 0x02000000
415 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
416 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
417 #define MAC_LED_CTRL 0x0000040c
418 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
419 #define LED_CTRL_1000MBPS_ON 0x00000002
420 #define LED_CTRL_100MBPS_ON 0x00000004
421 #define LED_CTRL_10MBPS_ON 0x00000008
422 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
423 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
424 #define LED_CTRL_TRAFFIC_LED 0x00000040
425 #define LED_CTRL_1000MBPS_STATUS 0x00000080
426 #define LED_CTRL_100MBPS_STATUS 0x00000100
427 #define LED_CTRL_10MBPS_STATUS 0x00000200
428 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
429 #define LED_CTRL_MODE_MAC 0x00000000
430 #define LED_CTRL_MODE_PHY_1 0x00000800
431 #define LED_CTRL_MODE_PHY_2 0x00001000
432 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
433 #define LED_CTRL_MODE_SHARED 0x00004000
434 #define LED_CTRL_MODE_COMBO 0x00008000
435 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
436 #define LED_CTRL_BLINK_RATE_SHIFT 19
437 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
438 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
439 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
440 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
441 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
442 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
443 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
444 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
445 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
446 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
447 #define MAC_ACPI_MBUF_PTR 0x00000430
448 #define MAC_ACPI_LEN_OFFSET 0x00000434
449 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
450 #define ACPI_LENOFF_LEN_SHIFT 0
451 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
452 #define ACPI_LENOFF_OFF_SHIFT 16
453 #define MAC_TX_BACKOFF_SEED 0x00000438
454 #define TX_BACKOFF_SEED_MASK 0x000003ff
455 #define MAC_RX_MTU_SIZE 0x0000043c
456 #define RX_MTU_SIZE_MASK 0x0000ffff
457 #define MAC_PCS_TEST 0x00000440
458 #define PCS_TEST_PATTERN_MASK 0x000fffff
459 #define PCS_TEST_PATTERN_SHIFT 0
460 #define PCS_TEST_ENABLE 0x00100000
461 #define MAC_TX_AUTO_NEG 0x00000444
462 #define TX_AUTO_NEG_MASK 0x0000ffff
463 #define TX_AUTO_NEG_SHIFT 0
464 #define MAC_RX_AUTO_NEG 0x00000448
465 #define RX_AUTO_NEG_MASK 0x0000ffff
466 #define RX_AUTO_NEG_SHIFT 0
467 #define MAC_MI_COM 0x0000044c
468 #define MI_COM_CMD_MASK 0x0c000000
469 #define MI_COM_CMD_WRITE 0x04000000
470 #define MI_COM_CMD_READ 0x08000000
471 #define MI_COM_READ_FAILED 0x10000000
472 #define MI_COM_START 0x20000000
473 #define MI_COM_BUSY 0x20000000
474 #define MI_COM_PHY_ADDR_MASK 0x03e00000
475 #define MI_COM_PHY_ADDR_SHIFT 21
476 #define MI_COM_REG_ADDR_MASK 0x001f0000
477 #define MI_COM_REG_ADDR_SHIFT 16
478 #define MI_COM_DATA_MASK 0x0000ffff
479 #define MAC_MI_STAT 0x00000450
480 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
481 #define MAC_MI_STAT_10MBPS_MODE 0x00000002
482 #define MAC_MI_MODE 0x00000454
483 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
484 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
485 #define MAC_MI_MODE_AUTO_POLL 0x00000010
486 #define MAC_MI_MODE_500KHZ_CONST 0x00008000
487 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
488 #define MAC_AUTO_POLL_STATUS 0x00000458
489 #define MAC_AUTO_POLL_ERROR 0x00000001
490 #define MAC_TX_MODE 0x0000045c
491 #define TX_MODE_RESET 0x00000001
492 #define TX_MODE_ENABLE 0x00000002
493 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
494 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
495 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
496 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
497 #define TX_MODE_JMB_FRM_LEN 0x00400000
498 #define TX_MODE_CNT_DN_MODE 0x00800000
499 #define MAC_TX_STATUS 0x00000460
500 #define TX_STATUS_XOFFED 0x00000001
501 #define TX_STATUS_SENT_XOFF 0x00000002
502 #define TX_STATUS_SENT_XON 0x00000004
503 #define TX_STATUS_LINK_UP 0x00000008
504 #define TX_STATUS_ODI_UNDERRUN 0x00000010
505 #define TX_STATUS_ODI_OVERRUN 0x00000020
506 #define MAC_TX_LENGTHS 0x00000464
507 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
508 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
509 #define TX_LENGTHS_IPG_MASK 0x00000f00
510 #define TX_LENGTHS_IPG_SHIFT 8
511 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
512 #define TX_LENGTHS_IPG_CRS_SHIFT 12
513 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
514 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
515 #define MAC_RX_MODE 0x00000468
516 #define RX_MODE_RESET 0x00000001
517 #define RX_MODE_ENABLE 0x00000002
518 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
519 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
520 #define RX_MODE_KEEP_PAUSE 0x00000010
521 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
522 #define RX_MODE_ACCEPT_RUNTS 0x00000040
523 #define RX_MODE_LEN_CHECK 0x00000080
524 #define RX_MODE_PROMISC 0x00000100
525 #define RX_MODE_NO_CRC_CHECK 0x00000200
526 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
527 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
528 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
529 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
530 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
531 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
532 #define RX_MODE_RSS_ENABLE 0x00800000
533 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
534 #define MAC_RX_STATUS 0x0000046c
535 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
536 #define RX_STATUS_XOFF_RCVD 0x00000002
537 #define RX_STATUS_XON_RCVD 0x00000004
538 #define MAC_HASH_REG_0 0x00000470
539 #define MAC_HASH_REG_1 0x00000474
540 #define MAC_HASH_REG_2 0x00000478
541 #define MAC_HASH_REG_3 0x0000047c
542 #define MAC_RCV_RULE_0 0x00000480
543 #define MAC_RCV_VALUE_0 0x00000484
544 #define MAC_RCV_RULE_1 0x00000488
545 #define MAC_RCV_VALUE_1 0x0000048c
546 #define MAC_RCV_RULE_2 0x00000490
547 #define MAC_RCV_VALUE_2 0x00000494
548 #define MAC_RCV_RULE_3 0x00000498
549 #define MAC_RCV_VALUE_3 0x0000049c
550 #define MAC_RCV_RULE_4 0x000004a0
551 #define MAC_RCV_VALUE_4 0x000004a4
552 #define MAC_RCV_RULE_5 0x000004a8
553 #define MAC_RCV_VALUE_5 0x000004ac
554 #define MAC_RCV_RULE_6 0x000004b0
555 #define MAC_RCV_VALUE_6 0x000004b4
556 #define MAC_RCV_RULE_7 0x000004b8
557 #define MAC_RCV_VALUE_7 0x000004bc
558 #define MAC_RCV_RULE_8 0x000004c0
559 #define MAC_RCV_VALUE_8 0x000004c4
560 #define MAC_RCV_RULE_9 0x000004c8
561 #define MAC_RCV_VALUE_9 0x000004cc
562 #define MAC_RCV_RULE_10 0x000004d0
563 #define MAC_RCV_VALUE_10 0x000004d4
564 #define MAC_RCV_RULE_11 0x000004d8
565 #define MAC_RCV_VALUE_11 0x000004dc
566 #define MAC_RCV_RULE_12 0x000004e0
567 #define MAC_RCV_VALUE_12 0x000004e4
568 #define MAC_RCV_RULE_13 0x000004e8
569 #define MAC_RCV_VALUE_13 0x000004ec
570 #define MAC_RCV_RULE_14 0x000004f0
571 #define MAC_RCV_VALUE_14 0x000004f4
572 #define MAC_RCV_RULE_15 0x000004f8
573 #define MAC_RCV_VALUE_15 0x000004fc
574 #define RCV_RULE_DISABLE_MASK 0x7fffffff
575 #define MAC_RCV_RULE_CFG 0x00000500
576 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
577 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
578 /* 0x508 --> 0x520 unused */
579 #define MAC_HASHREGU_0 0x00000520
580 #define MAC_HASHREGU_1 0x00000524
581 #define MAC_HASHREGU_2 0x00000528
582 #define MAC_HASHREGU_3 0x0000052c
583 #define MAC_EXTADDR_0_HIGH 0x00000530
584 #define MAC_EXTADDR_0_LOW 0x00000534
585 #define MAC_EXTADDR_1_HIGH 0x00000538
586 #define MAC_EXTADDR_1_LOW 0x0000053c
587 #define MAC_EXTADDR_2_HIGH 0x00000540
588 #define MAC_EXTADDR_2_LOW 0x00000544
589 #define MAC_EXTADDR_3_HIGH 0x00000548
590 #define MAC_EXTADDR_3_LOW 0x0000054c
591 #define MAC_EXTADDR_4_HIGH 0x00000550
592 #define MAC_EXTADDR_4_LOW 0x00000554
593 #define MAC_EXTADDR_5_HIGH 0x00000558
594 #define MAC_EXTADDR_5_LOW 0x0000055c
595 #define MAC_EXTADDR_6_HIGH 0x00000560
596 #define MAC_EXTADDR_6_LOW 0x00000564
597 #define MAC_EXTADDR_7_HIGH 0x00000568
598 #define MAC_EXTADDR_7_LOW 0x0000056c
599 #define MAC_EXTADDR_8_HIGH 0x00000570
600 #define MAC_EXTADDR_8_LOW 0x00000574
601 #define MAC_EXTADDR_9_HIGH 0x00000578
602 #define MAC_EXTADDR_9_LOW 0x0000057c
603 #define MAC_EXTADDR_10_HIGH 0x00000580
604 #define MAC_EXTADDR_10_LOW 0x00000584
605 #define MAC_EXTADDR_11_HIGH 0x00000588
606 #define MAC_EXTADDR_11_LOW 0x0000058c
607 #define MAC_SERDES_CFG 0x00000590
608 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
609 #define MAC_SERDES_STAT 0x00000594
610 /* 0x598 --> 0x5a0 unused */
611 #define MAC_PHYCFG1 0x000005a0
612 #define MAC_PHYCFG1_RGMII_INT 0x00000001
613 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
614 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
615 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
616 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
617 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
618 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
619 #define MAC_PHYCFG1_TXC_DRV 0x20000000
620 #define MAC_PHYCFG2 0x000005a4
621 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
622 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
623 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
624 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
625 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
626 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
627 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
628 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
629 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
630 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
631 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
632 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
633 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
634 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
635 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
636 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
637 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
638 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
639 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
640 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
641 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
642 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
643 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
644 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
645 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
646 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
647 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
648 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
649 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
650 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
651 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
652 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
653 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
654 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
655 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
656 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
657 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
658 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
659 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
660 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
661 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
662 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
663 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
664 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
665 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
666 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
667 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
668 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
669 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
670 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
671 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
672 #define MAC_PHYCFG2_50610_LED_MODES \
673 (MAC_PHYCFG2_EMODE_MASK_50610 | \
674 MAC_PHYCFG2_EMODE_COMP_50610 | \
675 MAC_PHYCFG2_FMODE_MASK_50610 | \
676 MAC_PHYCFG2_FMODE_COMP_50610 | \
677 MAC_PHYCFG2_GMODE_MASK_50610 | \
678 MAC_PHYCFG2_GMODE_COMP_50610 | \
679 MAC_PHYCFG2_ACT_MASK_50610 | \
680 MAC_PHYCFG2_ACT_COMP_50610 | \
681 MAC_PHYCFG2_QUAL_MASK_50610 | \
682 MAC_PHYCFG2_QUAL_COMP_50610)
683 #define MAC_PHYCFG2_AC131_LED_MODES \
684 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
685 MAC_PHYCFG2_EMODE_COMP_AC131 | \
686 MAC_PHYCFG2_FMODE_MASK_AC131 | \
687 MAC_PHYCFG2_FMODE_COMP_AC131 | \
688 MAC_PHYCFG2_GMODE_MASK_AC131 | \
689 MAC_PHYCFG2_GMODE_COMP_AC131 | \
690 MAC_PHYCFG2_ACT_MASK_AC131 | \
691 MAC_PHYCFG2_ACT_COMP_AC131 | \
692 MAC_PHYCFG2_QUAL_MASK_AC131 | \
693 MAC_PHYCFG2_QUAL_COMP_AC131)
694 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
695 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
696 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
697 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
698 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
699 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
700 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
701 MAC_PHYCFG2_ACT_MASK_RT8211 | \
702 MAC_PHYCFG2_ACT_COMP_RT8211 | \
703 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
704 MAC_PHYCFG2_QUAL_COMP_RT8211)
705 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
706 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
707 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
708 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
709 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
710 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
711 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
712 MAC_PHYCFG2_ACT_MASK_RT8201 | \
713 MAC_PHYCFG2_ACT_COMP_RT8201 | \
714 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
715 MAC_PHYCFG2_QUAL_COMP_RT8201)
716 #define MAC_EXT_RGMII_MODE 0x000005a8
717 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001
718 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
719 #define MAC_RGMII_MODE_TX_RESET 0x00000004
720 #define MAC_RGMII_MODE_RX_INT_B 0x00000100
721 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200
722 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
723 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
724 /* 0x5ac --> 0x5b0 unused */
725 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
726 #define SERDES_RX_SIG_DETECT 0x00000400
727 #define SG_DIG_CTRL 0x000005b0
728 #define SG_DIG_USING_HW_AUTONEG 0x80000000
729 #define SG_DIG_SOFT_RESET 0x40000000
730 #define SG_DIG_DISABLE_LINKRDY 0x20000000
731 #define SG_DIG_CRC16_CLEAR_N 0x01000000
732 #define SG_DIG_EN10B 0x00800000
733 #define SG_DIG_CLEAR_STATUS 0x00400000
734 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
735 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
736 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
737 #define SG_DIG_SPEED_STATUS_SHIFT 18
738 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
739 #define SG_DIG_RESTART_AUTONEG 0x00010000
740 #define SG_DIG_FIBER_MODE 0x00008000
741 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
742 #define SG_DIG_PAUSE_MASK 0x00001800
743 #define SG_DIG_PAUSE_CAP 0x00000800
744 #define SG_DIG_ASYM_PAUSE 0x00001000
745 #define SG_DIG_GBIC_ENABLE 0x00000400
746 #define SG_DIG_CHECK_END_ENABLE 0x00000200
747 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
748 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
749 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
750 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
751 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
752 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
753 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
754 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
755 #define SG_DIG_LOOPBACK 0x00000001
756 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
757 SG_DIG_LOCAL_DUPLEX_STATUS | \
758 SG_DIG_LOCAL_LINK_STATUS | \
759 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
760 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
761 #define SG_DIG_STATUS 0x000005b4
762 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
763 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
764 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
765 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
766 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
767 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
768 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
769 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
770 #define SG_DIG_IS_SERDES 0x00000100
771 #define SG_DIG_COMMA_DETECTOR 0x00000008
772 #define SG_DIG_MAC_ACK_STATUS 0x00000004
773 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
774 #define SG_DIG_AUTONEG_ERROR 0x00000001
775 #define TG3_TX_TSTAMP_LSB 0x000005c0
776 #define TG3_TX_TSTAMP_MSB 0x000005c4
777 #define TG3_TSTAMP_MASK 0x7fffffffffffffff
778 /* 0x5c8 --> 0x600 unused */
779 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
780 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
781 /* 0x624 --> 0x670 unused */
783 #define MAC_RSS_INDIR_TBL_0 0x00000630
785 #define MAC_RSS_HASH_KEY_0 0x00000670
786 #define MAC_RSS_HASH_KEY_1 0x00000674
787 #define MAC_RSS_HASH_KEY_2 0x00000678
788 #define MAC_RSS_HASH_KEY_3 0x0000067c
789 #define MAC_RSS_HASH_KEY_4 0x00000680
790 #define MAC_RSS_HASH_KEY_5 0x00000684
791 #define MAC_RSS_HASH_KEY_6 0x00000688
792 #define MAC_RSS_HASH_KEY_7 0x0000068c
793 #define MAC_RSS_HASH_KEY_8 0x00000690
794 #define MAC_RSS_HASH_KEY_9 0x00000694
795 /* 0x698 --> 0x6b0 unused */
797 #define TG3_RX_TSTAMP_LSB 0x000006b0
798 #define TG3_RX_TSTAMP_MSB 0x000006b4
799 /* 0x6b8 --> 0x6c8 unused */
801 #define TG3_RX_PTP_CTL 0x000006c8
802 #define TG3_RX_PTP_CTL_SYNC_EVNT 0x00000001
803 #define TG3_RX_PTP_CTL_DELAY_REQ 0x00000002
804 #define TG3_RX_PTP_CTL_PDLAY_REQ 0x00000004
805 #define TG3_RX_PTP_CTL_PDLAY_RES 0x00000008
806 #define TG3_RX_PTP_CTL_ALL_V1_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
807 TG3_RX_PTP_CTL_DELAY_REQ)
808 #define TG3_RX_PTP_CTL_ALL_V2_EVENTS (TG3_RX_PTP_CTL_SYNC_EVNT | \
809 TG3_RX_PTP_CTL_DELAY_REQ | \
810 TG3_RX_PTP_CTL_PDLAY_REQ | \
811 TG3_RX_PTP_CTL_PDLAY_RES)
812 #define TG3_RX_PTP_CTL_FOLLOW_UP 0x00000100
813 #define TG3_RX_PTP_CTL_DELAY_RES 0x00000200
814 #define TG3_RX_PTP_CTL_PDRES_FLW_UP 0x00000400
815 #define TG3_RX_PTP_CTL_ANNOUNCE 0x00000800
816 #define TG3_RX_PTP_CTL_SIGNALING 0x00001000
817 #define TG3_RX_PTP_CTL_MANAGEMENT 0x00002000
818 #define TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN 0x00800000
819 #define TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN 0x01000000
820 #define TG3_RX_PTP_CTL_RX_PTP_V2_EN (TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | \
821 TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN)
822 #define TG3_RX_PTP_CTL_RX_PTP_V1_EN 0x02000000
823 #define TG3_RX_PTP_CTL_HWTS_INTERLOCK 0x04000000
824 /* 0x6cc --> 0x800 unused */
826 #define MAC_TX_STATS_OCTETS 0x00000800
827 #define MAC_TX_STATS_RESV1 0x00000804
828 #define MAC_TX_STATS_COLLISIONS 0x00000808
829 #define MAC_TX_STATS_XON_SENT 0x0000080c
830 #define MAC_TX_STATS_XOFF_SENT 0x00000810
831 #define MAC_TX_STATS_RESV2 0x00000814
832 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
833 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
834 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
835 #define MAC_TX_STATS_DEFERRED 0x00000824
836 #define MAC_TX_STATS_RESV3 0x00000828
837 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
838 #define MAC_TX_STATS_LATE_COL 0x00000830
839 #define MAC_TX_STATS_RESV4_1 0x00000834
840 #define MAC_TX_STATS_RESV4_2 0x00000838
841 #define MAC_TX_STATS_RESV4_3 0x0000083c
842 #define MAC_TX_STATS_RESV4_4 0x00000840
843 #define MAC_TX_STATS_RESV4_5 0x00000844
844 #define MAC_TX_STATS_RESV4_6 0x00000848
845 #define MAC_TX_STATS_RESV4_7 0x0000084c
846 #define MAC_TX_STATS_RESV4_8 0x00000850
847 #define MAC_TX_STATS_RESV4_9 0x00000854
848 #define MAC_TX_STATS_RESV4_10 0x00000858
849 #define MAC_TX_STATS_RESV4_11 0x0000085c
850 #define MAC_TX_STATS_RESV4_12 0x00000860
851 #define MAC_TX_STATS_RESV4_13 0x00000864
852 #define MAC_TX_STATS_RESV4_14 0x00000868
853 #define MAC_TX_STATS_UCAST 0x0000086c
854 #define MAC_TX_STATS_MCAST 0x00000870
855 #define MAC_TX_STATS_BCAST 0x00000874
856 #define MAC_TX_STATS_RESV5_1 0x00000878
857 #define MAC_TX_STATS_RESV5_2 0x0000087c
858 #define MAC_RX_STATS_OCTETS 0x00000880
859 #define MAC_RX_STATS_RESV1 0x00000884
860 #define MAC_RX_STATS_FRAGMENTS 0x00000888
861 #define MAC_RX_STATS_UCAST 0x0000088c
862 #define MAC_RX_STATS_MCAST 0x00000890
863 #define MAC_RX_STATS_BCAST 0x00000894
864 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
865 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
866 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
867 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
868 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
869 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
870 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
871 #define MAC_RX_STATS_JABBERS 0x000008b4
872 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
873 /* 0x8bc --> 0xc00 unused */
875 /* Send data initiator control registers */
876 #define SNDDATAI_MODE 0x00000c00
877 #define SNDDATAI_MODE_RESET 0x00000001
878 #define SNDDATAI_MODE_ENABLE 0x00000002
879 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
880 #define SNDDATAI_STATUS 0x00000c04
881 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
882 #define SNDDATAI_STATSCTRL 0x00000c08
883 #define SNDDATAI_SCTRL_ENABLE 0x00000001
884 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
885 #define SNDDATAI_SCTRL_CLEAR 0x00000004
886 #define SNDDATAI_SCTRL_FLUSH 0x00000008
887 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
888 #define SNDDATAI_STATSENAB 0x00000c0c
889 #define SNDDATAI_STATSINCMASK 0x00000c10
890 #define ISO_PKT_TX 0x00000c20
891 /* 0xc24 --> 0xc80 unused */
892 #define SNDDATAI_COS_CNT_0 0x00000c80
893 #define SNDDATAI_COS_CNT_1 0x00000c84
894 #define SNDDATAI_COS_CNT_2 0x00000c88
895 #define SNDDATAI_COS_CNT_3 0x00000c8c
896 #define SNDDATAI_COS_CNT_4 0x00000c90
897 #define SNDDATAI_COS_CNT_5 0x00000c94
898 #define SNDDATAI_COS_CNT_6 0x00000c98
899 #define SNDDATAI_COS_CNT_7 0x00000c9c
900 #define SNDDATAI_COS_CNT_8 0x00000ca0
901 #define SNDDATAI_COS_CNT_9 0x00000ca4
902 #define SNDDATAI_COS_CNT_10 0x00000ca8
903 #define SNDDATAI_COS_CNT_11 0x00000cac
904 #define SNDDATAI_COS_CNT_12 0x00000cb0
905 #define SNDDATAI_COS_CNT_13 0x00000cb4
906 #define SNDDATAI_COS_CNT_14 0x00000cb8
907 #define SNDDATAI_COS_CNT_15 0x00000cbc
908 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
909 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
910 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
911 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
912 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
913 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
914 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
915 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
916 /* 0xce0 --> 0x1000 unused */
918 /* Send data completion control registers */
919 #define SNDDATAC_MODE 0x00001000
920 #define SNDDATAC_MODE_RESET 0x00000001
921 #define SNDDATAC_MODE_ENABLE 0x00000002
922 #define SNDDATAC_MODE_CDELAY 0x00000010
923 /* 0x1004 --> 0x1400 unused */
925 /* Send BD ring selector */
926 #define SNDBDS_MODE 0x00001400
927 #define SNDBDS_MODE_RESET 0x00000001
928 #define SNDBDS_MODE_ENABLE 0x00000002
929 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
930 #define SNDBDS_STATUS 0x00001404
931 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
932 #define SNDBDS_HWDIAG 0x00001408
933 /* 0x140c --> 0x1440 */
934 #define SNDBDS_SEL_CON_IDX_0 0x00001440
935 #define SNDBDS_SEL_CON_IDX_1 0x00001444
936 #define SNDBDS_SEL_CON_IDX_2 0x00001448
937 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
938 #define SNDBDS_SEL_CON_IDX_4 0x00001450
939 #define SNDBDS_SEL_CON_IDX_5 0x00001454
940 #define SNDBDS_SEL_CON_IDX_6 0x00001458
941 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
942 #define SNDBDS_SEL_CON_IDX_8 0x00001460
943 #define SNDBDS_SEL_CON_IDX_9 0x00001464
944 #define SNDBDS_SEL_CON_IDX_10 0x00001468
945 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
946 #define SNDBDS_SEL_CON_IDX_12 0x00001470
947 #define SNDBDS_SEL_CON_IDX_13 0x00001474
948 #define SNDBDS_SEL_CON_IDX_14 0x00001478
949 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
950 /* 0x1480 --> 0x1800 unused */
952 /* Send BD initiator control registers */
953 #define SNDBDI_MODE 0x00001800
954 #define SNDBDI_MODE_RESET 0x00000001
955 #define SNDBDI_MODE_ENABLE 0x00000002
956 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
957 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
958 #define SNDBDI_STATUS 0x00001804
959 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
960 #define SNDBDI_IN_PROD_IDX_0 0x00001808
961 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
962 #define SNDBDI_IN_PROD_IDX_2 0x00001810
963 #define SNDBDI_IN_PROD_IDX_3 0x00001814
964 #define SNDBDI_IN_PROD_IDX_4 0x00001818
965 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
966 #define SNDBDI_IN_PROD_IDX_6 0x00001820
967 #define SNDBDI_IN_PROD_IDX_7 0x00001824
968 #define SNDBDI_IN_PROD_IDX_8 0x00001828
969 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
970 #define SNDBDI_IN_PROD_IDX_10 0x00001830
971 #define SNDBDI_IN_PROD_IDX_11 0x00001834
972 #define SNDBDI_IN_PROD_IDX_12 0x00001838
973 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
974 #define SNDBDI_IN_PROD_IDX_14 0x00001840
975 #define SNDBDI_IN_PROD_IDX_15 0x00001844
976 /* 0x1848 --> 0x1c00 unused */
978 /* Send BD completion control registers */
979 #define SNDBDC_MODE 0x00001c00
980 #define SNDBDC_MODE_RESET 0x00000001
981 #define SNDBDC_MODE_ENABLE 0x00000002
982 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
983 /* 0x1c04 --> 0x2000 unused */
985 /* Receive list placement control registers */
986 #define RCVLPC_MODE 0x00002000
987 #define RCVLPC_MODE_RESET 0x00000001
988 #define RCVLPC_MODE_ENABLE 0x00000002
989 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
990 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
991 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
992 #define RCVLPC_STATUS 0x00002004
993 #define RCVLPC_STATUS_CLASS0 0x00000004
994 #define RCVLPC_STATUS_MAPOOR 0x00000008
995 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
996 #define RCVLPC_LOCK 0x00002008
997 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
998 #define RCVLPC_LOCK_REQ_SHIFT 0
999 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1000 #define RCVLPC_LOCK_GRANT_SHIFT 16
1001 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
1002 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1003 #define RCVLPC_CONFIG 0x00002010
1004 #define RCVLPC_STATSCTRL 0x00002014
1005 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
1006 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1007 #define RCVLPC_STATS_ENABLE 0x00002018
1008 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1009 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1010 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1011 #define RCVLPC_STATS_INCMASK 0x0000201c
1012 /* 0x2020 --> 0x2100 unused */
1013 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1014 #define SELLST_TAIL 0x00000004
1015 #define SELLST_CONT 0x00000008
1016 #define SELLST_UNUSED 0x0000000c
1017 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1018 #define RCVLPC_DROP_FILTER_CNT 0x00002240
1019 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1020 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1021 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1022 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
1023 #define RCVLPC_IN_ERRORS_CNT 0x00002254
1024 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1025 /* 0x225c --> 0x2400 unused */
1027 /* Receive Data and Receive BD Initiator Control */
1028 #define RCVDBDI_MODE 0x00002400
1029 #define RCVDBDI_MODE_RESET 0x00000001
1030 #define RCVDBDI_MODE_ENABLE 0x00000002
1031 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1032 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1033 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1034 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1035 #define RCVDBDI_STATUS 0x00002404
1036 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1037 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1038 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1039 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1040 /* 0x240c --> 0x2440 unused */
1041 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1042 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1043 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1044 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
1045 #define RCVDBDI_STD_CON_IDX 0x00002474
1046 #define RCVDBDI_MINI_CON_IDX 0x00002478
1047 /* 0x247c --> 0x2480 unused */
1048 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
1049 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
1050 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
1051 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1052 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
1053 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
1054 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
1055 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1056 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1057 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1058 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1059 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1060 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1061 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1062 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1063 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1064 #define RCVDBDI_HWDIAG 0x000024c0
1065 /* 0x24c4 --> 0x2800 unused */
1067 /* Receive Data Completion Control */
1068 #define RCVDCC_MODE 0x00002800
1069 #define RCVDCC_MODE_RESET 0x00000001
1070 #define RCVDCC_MODE_ENABLE 0x00000002
1071 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1072 /* 0x2804 --> 0x2c00 unused */
1074 /* Receive BD Initiator Control Registers */
1075 #define RCVBDI_MODE 0x00002c00
1076 #define RCVBDI_MODE_RESET 0x00000001
1077 #define RCVBDI_MODE_ENABLE 0x00000002
1078 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1079 #define RCVBDI_STATUS 0x00002c04
1080 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
1081 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1082 #define RCVBDI_STD_PROD_IDX 0x00002c0c
1083 #define RCVBDI_MINI_PROD_IDX 0x00002c10
1084 #define RCVBDI_MINI_THRESH 0x00002c14
1085 #define RCVBDI_STD_THRESH 0x00002c18
1086 #define RCVBDI_JUMBO_THRESH 0x00002c1c
1087 /* 0x2c20 --> 0x2d00 unused */
1089 #define STD_REPLENISH_LWM 0x00002d00
1090 #define JMB_REPLENISH_LWM 0x00002d04
1091 /* 0x2d08 --> 0x3000 unused */
1093 /* Receive BD Completion Control Registers */
1094 #define RCVCC_MODE 0x00003000
1095 #define RCVCC_MODE_RESET 0x00000001
1096 #define RCVCC_MODE_ENABLE 0x00000002
1097 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
1098 #define RCVCC_STATUS 0x00003004
1099 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
1100 #define RCVCC_JUMP_PROD_IDX 0x00003008
1101 #define RCVCC_STD_PROD_IDX 0x0000300c
1102 #define RCVCC_MINI_PROD_IDX 0x00003010
1103 /* 0x3014 --> 0x3400 unused */
1105 /* Receive list selector control registers */
1106 #define RCVLSC_MODE 0x00003400
1107 #define RCVLSC_MODE_RESET 0x00000001
1108 #define RCVLSC_MODE_ENABLE 0x00000002
1109 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1110 #define RCVLSC_STATUS 0x00003404
1111 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1112 /* 0x3408 --> 0x3600 unused */
1114 #define TG3_CPMU_DRV_STATUS 0x0000344c
1116 /* CPMU registers */
1117 #define TG3_CPMU_CTRL 0x00003600
1118 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1119 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1120 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1121 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1122 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1123 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1124 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1125 /* 0x3608 --> 0x360c unused */
1127 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1128 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1129 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1130 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1131 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1132 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1133 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1134 /* 0x3614 --> 0x361c unused */
1136 #define TG3_CPMU_HST_ACC 0x0000361c
1137 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1138 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1139 /* 0x3620 --> 0x3630 unused */
1141 #define TG3_CPMU_CLCK_ORIDE 0x00003624
1142 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1144 #define TG3_CPMU_STATUS 0x0000362c
1145 #define TG3_CPMU_STATUS_FMSK_5717 0x20000000
1146 #define TG3_CPMU_STATUS_FMSK_5719 0xc0000000
1147 #define TG3_CPMU_STATUS_FSHFT_5719 30
1149 #define TG3_CPMU_CLCK_STAT 0x00003630
1150 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1151 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1152 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1153 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1154 /* 0x3634 --> 0x365c unused */
1156 #define TG3_CPMU_MUTEX_REQ 0x0000365c
1157 #define CPMU_MUTEX_REQ_DRIVER 0x00001000
1158 #define TG3_CPMU_MUTEX_GNT 0x00003660
1159 #define CPMU_MUTEX_GNT_DRIVER 0x00001000
1160 #define TG3_CPMU_PHY_STRAP 0x00003664
1161 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1162 /* 0x3664 --> 0x36b0 unused */
1164 #define TG3_CPMU_EEE_MODE 0x000036b0
1165 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1166 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1167 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1168 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1169 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1170 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1171 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1172 #define TG3_CPMU_EEE_DBTMR1 0x000036b4
1173 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1174 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000007ff
1175 #define TG3_CPMU_EEE_DBTMR2 0x000036b8
1176 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1177 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000007ff
1178 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1179 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1180 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1181 /* 0x36c0 --> 0x36d0 unused */
1183 #define TG3_CPMU_EEE_CTRL 0x000036d0
1184 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1185 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1186 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1187 /* 0x36d4 --> 0x3800 unused */
1189 /* Mbuf cluster free registers */
1190 #define MBFREE_MODE 0x00003800
1191 #define MBFREE_MODE_RESET 0x00000001
1192 #define MBFREE_MODE_ENABLE 0x00000002
1193 #define MBFREE_STATUS 0x00003804
1194 /* 0x3808 --> 0x3c00 unused */
1196 /* Host coalescing control registers */
1197 #define HOSTCC_MODE 0x00003c00
1198 #define HOSTCC_MODE_RESET 0x00000001
1199 #define HOSTCC_MODE_ENABLE 0x00000002
1200 #define HOSTCC_MODE_ATTN 0x00000004
1201 #define HOSTCC_MODE_NOW 0x00000008
1202 #define HOSTCC_MODE_FULL_STATUS 0x00000000
1203 #define HOSTCC_MODE_64BYTE 0x00000080
1204 #define HOSTCC_MODE_32BYTE 0x00000100
1205 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1206 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1207 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1208 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1209 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1210 #define HOSTCC_STATUS 0x00003c04
1211 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1212 #define HOSTCC_RXCOL_TICKS 0x00003c08
1213 #define LOW_RXCOL_TICKS 0x00000032
1214 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1215 #define DEFAULT_RXCOL_TICKS 0x00000048
1216 #define HIGH_RXCOL_TICKS 0x00000096
1217 #define MAX_RXCOL_TICKS 0x000003ff
1218 #define HOSTCC_TXCOL_TICKS 0x00003c0c
1219 #define LOW_TXCOL_TICKS 0x00000096
1220 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1221 #define DEFAULT_TXCOL_TICKS 0x0000012c
1222 #define HIGH_TXCOL_TICKS 0x00000145
1223 #define MAX_TXCOL_TICKS 0x000003ff
1224 #define HOSTCC_RXMAX_FRAMES 0x00003c10
1225 #define LOW_RXMAX_FRAMES 0x00000005
1226 #define DEFAULT_RXMAX_FRAMES 0x00000008
1227 #define HIGH_RXMAX_FRAMES 0x00000012
1228 #define MAX_RXMAX_FRAMES 0x000000ff
1229 #define HOSTCC_TXMAX_FRAMES 0x00003c14
1230 #define LOW_TXMAX_FRAMES 0x00000035
1231 #define DEFAULT_TXMAX_FRAMES 0x0000004b
1232 #define HIGH_TXMAX_FRAMES 0x00000052
1233 #define MAX_TXMAX_FRAMES 0x000000ff
1234 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1235 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
1236 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1237 #define MAX_RXCOAL_TICK_INT 0x000003ff
1238 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1239 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
1240 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1241 #define MAX_TXCOAL_TICK_INT 0x000003ff
1242 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1243 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1244 #define MAX_RXCOAL_MAXF_INT 0x000000ff
1245 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1246 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1247 #define MAX_TXCOAL_MAXF_INT 0x000000ff
1248 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
1249 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
1250 #define MAX_STAT_COAL_TICKS 0xd693d400
1251 #define MIN_STAT_COAL_TICKS 0x00000064
1252 /* 0x3c2c --> 0x3c30 unused */
1253 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1254 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1255 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1256 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1257 #define HOSTCC_FLOW_ATTN 0x00003c48
1258 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1259 /* 0x3c4c --> 0x3c50 unused */
1260 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
1261 #define HOSTCC_STD_CON_IDX 0x00003c54
1262 #define HOSTCC_MINI_CON_IDX 0x00003c58
1263 /* 0x3c5c --> 0x3c80 unused */
1264 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
1265 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
1266 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
1267 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1268 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
1269 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
1270 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
1271 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1272 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1273 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1274 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1275 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
1276 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1277 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1278 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1279 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1280 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
1281 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
1282 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
1283 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
1284 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
1285 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
1286 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
1287 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
1288 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
1289 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
1290 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
1291 #define HOSTCC_SND_CON_IDX_11 0x00003cec
1292 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
1293 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
1294 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
1295 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
1296 #define HOSTCC_STATBLCK_RING1 0x00003d00
1297 /* 0x3d00 --> 0x3d80 unused */
1299 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1300 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1301 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1302 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1303 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1304 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1305 /* 0x3d98 --> 0x4000 unused */
1307 /* Memory arbiter control registers */
1308 #define MEMARB_MODE 0x00004000
1309 #define MEMARB_MODE_RESET 0x00000001
1310 #define MEMARB_MODE_ENABLE 0x00000002
1311 #define MEMARB_STATUS 0x00004004
1312 #define MEMARB_TRAP_ADDR_LOW 0x00004008
1313 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1314 /* 0x4010 --> 0x4400 unused */
1316 /* Buffer manager control registers */
1317 #define BUFMGR_MODE 0x00004400
1318 #define BUFMGR_MODE_RESET 0x00000001
1319 #define BUFMGR_MODE_ENABLE 0x00000002
1320 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1321 #define BUFMGR_MODE_BM_TEST 0x00000008
1322 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1323 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1324 #define BUFMGR_STATUS 0x00004404
1325 #define BUFMGR_STATUS_ERROR 0x00000004
1326 #define BUFMGR_STATUS_MBLOW 0x00000010
1327 #define BUFMGR_MB_POOL_ADDR 0x00004408
1328 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1329 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1330 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1331 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1332 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1333 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1334 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1335 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1336 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1337 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1338 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1339 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1340 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1341 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1342 #define BUFMGR_MB_HIGH_WATER 0x00004418
1343 #define DEFAULT_MB_HIGH_WATER 0x00000060
1344 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1345 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1346 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1347 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1348 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1349 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1350 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1351 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1352 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1353 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1354 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1355 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1356 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1357 #define BUFMGR_DMA_LOW_WATER 0x00004434
1358 #define DEFAULT_DMA_LOW_WATER 0x00000005
1359 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1360 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1361 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1362 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1363 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1364 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1365 #define BUFMGR_HWDIAG_0 0x0000444c
1366 #define BUFMGR_HWDIAG_1 0x00004450
1367 #define BUFMGR_HWDIAG_2 0x00004454
1368 /* 0x4458 --> 0x4800 unused */
1370 /* Read DMA control registers */
1371 #define RDMAC_MODE 0x00004800
1372 #define RDMAC_MODE_RESET 0x00000001
1373 #define RDMAC_MODE_ENABLE 0x00000002
1374 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1375 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1376 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1377 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1378 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1379 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1380 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1381 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1382 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1383 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1384 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1385 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1386 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1387 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1388 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1389 #define RDMAC_MODE_JMB_2K_MMRR 0x00800000
1390 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1391 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1392 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1393 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1394 #define RDMAC_STATUS 0x00004804
1395 #define RDMAC_STATUS_TGTABORT 0x00000004
1396 #define RDMAC_STATUS_MSTABORT 0x00000008
1397 #define RDMAC_STATUS_PARITYERR 0x00000010
1398 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1399 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1400 #define RDMAC_STATUS_FIFOURUN 0x00000080
1401 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1402 #define RDMAC_STATUS_LNGREAD 0x00000200
1403 /* 0x4808 --> 0x4900 unused */
1405 #define TG3_RDMA_RSRVCTRL_REG 0x00004900
1406 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1407 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1408 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1409 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1410 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1411 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1412 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1413 /* 0x4904 --> 0x4910 unused */
1415 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1416 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1417 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1418 #define TG3_LSO_RD_DMA_TX_LENGTH_WA 0x02000000
1419 /* 0x4914 --> 0x4be0 unused */
1421 #define TG3_NUM_RDMA_CHANNELS 4
1422 #define TG3_RDMA_LENGTH 0x00004be0
1424 /* Write DMA control registers */
1425 #define WDMAC_MODE 0x00004c00
1426 #define WDMAC_MODE_RESET 0x00000001
1427 #define WDMAC_MODE_ENABLE 0x00000002
1428 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1429 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1430 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1431 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1432 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1433 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1434 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1435 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1436 #define WDMAC_MODE_RX_ACCEL 0x00000400
1437 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1438 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1439 #define WDMAC_STATUS 0x00004c04
1440 #define WDMAC_STATUS_TGTABORT 0x00000004
1441 #define WDMAC_STATUS_MSTABORT 0x00000008
1442 #define WDMAC_STATUS_PARITYERR 0x00000010
1443 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1444 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1445 #define WDMAC_STATUS_FIFOURUN 0x00000080
1446 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1447 #define WDMAC_STATUS_LNGREAD 0x00000200
1448 /* 0x4c08 --> 0x5000 unused */
1450 /* Per-cpu register offsets (arm9) */
1451 #define CPU_MODE 0x00000000
1452 #define CPU_MODE_RESET 0x00000001
1453 #define CPU_MODE_HALT 0x00000400
1454 #define CPU_STATE 0x00000004
1455 #define CPU_EVTMASK 0x00000008
1456 /* 0xc --> 0x1c reserved */
1457 #define CPU_PC 0x0000001c
1458 #define CPU_INSN 0x00000020
1459 #define CPU_SPAD_UFLOW 0x00000024
1460 #define CPU_WDOG_CLEAR 0x00000028
1461 #define CPU_WDOG_VECTOR 0x0000002c
1462 #define CPU_WDOG_PC 0x00000030
1463 #define CPU_HW_BP 0x00000034
1464 /* 0x38 --> 0x44 unused */
1465 #define CPU_WDOG_SAVED_STATE 0x00000044
1466 #define CPU_LAST_BRANCH_ADDR 0x00000048
1467 #define CPU_SPAD_UFLOW_SET 0x0000004c
1468 /* 0x50 --> 0x200 unused */
1469 #define CPU_R0 0x00000200
1470 #define CPU_R1 0x00000204
1471 #define CPU_R2 0x00000208
1472 #define CPU_R3 0x0000020c
1473 #define CPU_R4 0x00000210
1474 #define CPU_R5 0x00000214
1475 #define CPU_R6 0x00000218
1476 #define CPU_R7 0x0000021c
1477 #define CPU_R8 0x00000220
1478 #define CPU_R9 0x00000224
1479 #define CPU_R10 0x00000228
1480 #define CPU_R11 0x0000022c
1481 #define CPU_R12 0x00000230
1482 #define CPU_R13 0x00000234
1483 #define CPU_R14 0x00000238
1484 #define CPU_R15 0x0000023c
1485 #define CPU_R16 0x00000240
1486 #define CPU_R17 0x00000244
1487 #define CPU_R18 0x00000248
1488 #define CPU_R19 0x0000024c
1489 #define CPU_R20 0x00000250
1490 #define CPU_R21 0x00000254
1491 #define CPU_R22 0x00000258
1492 #define CPU_R23 0x0000025c
1493 #define CPU_R24 0x00000260
1494 #define CPU_R25 0x00000264
1495 #define CPU_R26 0x00000268
1496 #define CPU_R27 0x0000026c
1497 #define CPU_R28 0x00000270
1498 #define CPU_R29 0x00000274
1499 #define CPU_R30 0x00000278
1500 #define CPU_R31 0x0000027c
1501 /* 0x280 --> 0x400 unused */
1503 #define RX_CPU_BASE 0x00005000
1504 #define RX_CPU_MODE 0x00005000
1505 #define RX_CPU_STATE 0x00005004
1506 #define RX_CPU_PGMCTR 0x0000501c
1507 #define RX_CPU_HWBKPT 0x00005034
1508 #define TX_CPU_BASE 0x00005400
1509 #define TX_CPU_MODE 0x00005400
1510 #define TX_CPU_STATE 0x00005404
1511 #define TX_CPU_PGMCTR 0x0000541c
1513 #define VCPU_STATUS 0x00005100
1514 #define VCPU_STATUS_INIT_DONE 0x04000000
1515 #define VCPU_STATUS_DRV_RESET 0x08000000
1517 #define VCPU_CFGSHDW 0x00005104
1518 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1519 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1520 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1523 #define GRCMBOX_BASE 0x00005600
1524 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1525 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1526 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1527 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1528 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1529 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1530 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1531 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1532 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1533 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1534 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1535 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1536 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1537 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1538 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1539 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1540 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1541 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1542 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1543 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1544 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1545 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1546 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1547 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1548 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1549 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1550 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1551 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1552 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1553 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1554 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1555 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1556 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1557 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1558 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1559 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1560 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1561 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1562 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1563 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1564 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1565 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1566 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1567 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1568 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1569 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1570 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1571 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1572 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1573 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1574 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1575 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1576 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1577 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1578 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1579 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1580 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1581 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1582 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1583 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1584 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1585 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1586 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1587 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1588 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1589 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1590 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1591 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1592 /* 0x5a10 --> 0x5c00 */
1594 /* Flow Through queues */
1595 #define FTQ_RESET 0x00005c00
1596 /* 0x5c04 --> 0x5c10 unused */
1597 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1598 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1599 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1600 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1601 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1602 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1603 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1604 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1605 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1606 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1607 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1608 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1609 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1610 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1611 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1612 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1613 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1614 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1615 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1616 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1617 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1618 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1619 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1620 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1621 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1622 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1623 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1624 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1625 #define FTQ_SWTYPE1_CTL 0x00005c80
1626 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1627 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1628 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1629 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1630 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1631 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1632 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1633 #define FTQ_HOST_COAL_CTL 0x00005ca0
1634 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1635 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1636 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1637 #define FTQ_MAC_TX_CTL 0x00005cb0
1638 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1639 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1640 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1641 #define FTQ_MB_FREE_CTL 0x00005cc0
1642 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1643 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1644 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1645 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1646 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1647 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1648 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1649 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1650 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1651 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1652 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1653 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1654 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1655 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1656 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1657 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1658 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1659 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1660 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1661 #define FTQ_SWTYPE2_CTL 0x00005d10
1662 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1663 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1664 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1665 /* 0x5d20 --> 0x6000 unused */
1667 /* Message signaled interrupt registers */
1668 #define MSGINT_MODE 0x00006000
1669 #define MSGINT_MODE_RESET 0x00000001
1670 #define MSGINT_MODE_ENABLE 0x00000002
1671 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1672 #define MSGINT_MODE_MULTIVEC_EN 0x00000080
1673 #define MSGINT_STATUS 0x00006004
1674 #define MSGINT_STATUS_MSI_REQ 0x00000001
1675 #define MSGINT_FIFO 0x00006008
1676 /* 0x600c --> 0x6400 unused */
1678 /* DMA completion registers */
1679 #define DMAC_MODE 0x00006400
1680 #define DMAC_MODE_RESET 0x00000001
1681 #define DMAC_MODE_ENABLE 0x00000002
1682 /* 0x6404 --> 0x6800 unused */
1685 #define GRC_MODE 0x00006800
1686 #define GRC_MODE_UPD_ON_COAL 0x00000001
1687 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1688 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1689 #define GRC_MODE_BSWAP_DATA 0x00000010
1690 #define GRC_MODE_WSWAP_DATA 0x00000020
1691 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1692 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1693 #define GRC_MODE_SPLITHDR 0x00000100
1694 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1695 #define GRC_MODE_INCL_CRC 0x00000400
1696 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1697 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1698 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1699 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1700 #define GRC_MODE_B2HRX_ENABLE 0x00008000
1701 #define GRC_MODE_HOST_STACKUP 0x00010000
1702 #define GRC_MODE_HOST_SENDBDS 0x00020000
1703 #define GRC_MODE_HTX2B_ENABLE 0x00040000
1704 #define GRC_MODE_TIME_SYNC_ENABLE 0x00080000
1705 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1706 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1707 #define GRC_MODE_PCIE_TL_SEL 0x00000000
1708 #define GRC_MODE_PCIE_PL_SEL 0x00400000
1709 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1710 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1711 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1712 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1713 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1714 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1715 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1716 #define GRC_MODE_PCIE_DL_SEL 0x20000000
1717 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1718 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1719 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1720 GRC_MODE_PCIE_PL_SEL | \
1721 GRC_MODE_PCIE_DL_SEL | \
1722 GRC_MODE_PCIE_HI_1K_EN)
1723 #define GRC_MISC_CFG 0x00006804
1724 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1725 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1726 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1727 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1728 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1729 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1730 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1731 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1732 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1733 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1734 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1735 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1736 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1737 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1738 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1739 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1740 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1741 #define GRC_LOCAL_CTRL 0x00006808
1742 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1743 #define GRC_LCLCTRL_CLEARINT 0x00000002
1744 #define GRC_LCLCTRL_SETINT 0x00000004
1745 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1746 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1747 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1748 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1749 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1750 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1751 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1752 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1753 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1754 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1755 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1756 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1757 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1758 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1759 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1760 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1761 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1762 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1763 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1764 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1765 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1766 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1767 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1768 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1769 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1770 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1771 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1772 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1773 #define GRC_TIMER 0x0000680c
1774 #define GRC_RX_CPU_EVENT 0x00006810
1775 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1776 #define GRC_RX_TIMER_REF 0x00006814
1777 #define GRC_RX_CPU_SEM 0x00006818
1778 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1779 #define GRC_TX_CPU_EVENT 0x00006820
1780 #define GRC_TX_TIMER_REF 0x00006824
1781 #define GRC_TX_CPU_SEM 0x00006828
1782 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1783 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1784 #define GRC_EEPROM_ADDR 0x00006838
1785 #define EEPROM_ADDR_WRITE 0x00000000
1786 #define EEPROM_ADDR_READ 0x80000000
1787 #define EEPROM_ADDR_COMPLETE 0x40000000
1788 #define EEPROM_ADDR_FSM_RESET 0x20000000
1789 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1790 #define EEPROM_ADDR_DEVID_SHIFT 26
1791 #define EEPROM_ADDR_START 0x02000000
1792 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1793 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1794 #define EEPROM_ADDR_ADDR_SHIFT 0
1795 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1796 #define EEPROM_CHIP_SIZE (64 * 1024)
1797 #define GRC_EEPROM_DATA 0x0000683c
1798 #define GRC_EEPROM_CTRL 0x00006840
1799 #define GRC_MDI_CTRL 0x00006844
1800 #define GRC_SEEPROM_DELAY 0x00006848
1801 /* 0x684c --> 0x6890 unused */
1802 #define GRC_VCPU_EXT_CTRL 0x00006890
1803 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1804 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1805 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1807 #define TG3_EAV_REF_CLCK_LSB 0x00006900
1808 #define TG3_EAV_REF_CLCK_MSB 0x00006904
1809 #define TG3_EAV_REF_CLCK_CTL 0x00006908
1810 #define TG3_EAV_REF_CLCK_CTL_STOP 0x00000002
1811 #define TG3_EAV_REF_CLCK_CTL_RESUME 0x00000004
1812 #define TG3_EAV_REF_CLK_CORRECT_CTL 0x00006928
1813 #define TG3_EAV_REF_CLK_CORRECT_EN (1 << 31)
1814 #define TG3_EAV_REF_CLK_CORRECT_NEG (1 << 30)
1816 #define TG3_EAV_REF_CLK_CORRECT_MASK 0xffffff
1817 /* 0x690c --> 0x7000 unused */
1819 /* NVRAM Control registers */
1820 #define NVRAM_CMD 0x00007000
1821 #define NVRAM_CMD_RESET 0x00000001
1822 #define NVRAM_CMD_DONE 0x00000008
1823 #define NVRAM_CMD_GO 0x00000010
1824 #define NVRAM_CMD_WR 0x00000020
1825 #define NVRAM_CMD_RD 0x00000000
1826 #define NVRAM_CMD_ERASE 0x00000040
1827 #define NVRAM_CMD_FIRST 0x00000080
1828 #define NVRAM_CMD_LAST 0x00000100
1829 #define NVRAM_CMD_WREN 0x00010000
1830 #define NVRAM_CMD_WRDI 0x00020000
1831 #define NVRAM_STAT 0x00007004
1832 #define NVRAM_WRDATA 0x00007008
1833 #define NVRAM_ADDR 0x0000700c
1834 #define NVRAM_ADDR_MSK 0x00ffffff
1835 #define NVRAM_RDDATA 0x00007010
1836 #define NVRAM_CFG1 0x00007014
1837 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1838 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1839 #define NVRAM_CFG1_PASS_THRU 0x00000004
1840 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1841 #define NVRAM_CFG1_BIT_BANG 0x00000008
1842 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1843 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1844 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1845 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1846 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1847 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1848 #define FLASH_VENDOR_ST 0x03000001
1849 #define FLASH_VENDOR_SAIFUN 0x01000003
1850 #define FLASH_VENDOR_SST_SMALL 0x00000001
1851 #define FLASH_VENDOR_SST_LARGE 0x02000001
1852 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1853 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1854 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1855 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1856 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1857 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1858 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1859 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1860 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1861 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1862 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1863 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1864 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1865 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1866 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1867 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1868 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1869 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1870 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1871 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1872 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1873 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1874 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1875 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1876 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1877 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1878 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1879 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1880 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1881 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1882 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1883 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1884 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1885 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1886 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1887 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1888 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1889 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1890 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1891 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1892 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1893 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1894 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1895 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1896 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1897 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1898 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1899 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1900 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1901 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1902 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1903 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1904 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1905 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1906 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1907 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1908 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1909 #define FLASH_5717VENDOR_ST_25USPT 0x03400002
1910 #define FLASH_5717VENDOR_ST_45USPT 0x03400001
1911 #define FLASH_5720_EEPROM_HD 0x00000001
1912 #define FLASH_5720_EEPROM_LD 0x00000003
1913 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1914 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1915 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1916 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1917 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1918 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1919 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1920 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1921 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1922 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1923 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1924 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1925 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1926 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1927 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1928 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1929 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1930 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
1931 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
1932 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
1933 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
1934 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
1935 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
1936 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
1937 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
1938 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
1939 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
1940 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
1941 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002
1942 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001
1943 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
1944 #define FLASH_5752PAGE_SIZE_256 0x00000000
1945 #define FLASH_5752PAGE_SIZE_512 0x10000000
1946 #define FLASH_5752PAGE_SIZE_1K 0x20000000
1947 #define FLASH_5752PAGE_SIZE_2K 0x30000000
1948 #define FLASH_5752PAGE_SIZE_4K 0x40000000
1949 #define FLASH_5752PAGE_SIZE_264 0x50000000
1950 #define FLASH_5752PAGE_SIZE_528 0x60000000
1951 #define NVRAM_CFG2 0x00007018
1952 #define NVRAM_CFG3 0x0000701c
1953 #define NVRAM_SWARB 0x00007020
1954 #define SWARB_REQ_SET0 0x00000001
1955 #define SWARB_REQ_SET1 0x00000002
1956 #define SWARB_REQ_SET2 0x00000004
1957 #define SWARB_REQ_SET3 0x00000008
1958 #define SWARB_REQ_CLR0 0x00000010
1959 #define SWARB_REQ_CLR1 0x00000020
1960 #define SWARB_REQ_CLR2 0x00000040
1961 #define SWARB_REQ_CLR3 0x00000080
1962 #define SWARB_GNT0 0x00000100
1963 #define SWARB_GNT1 0x00000200
1964 #define SWARB_GNT2 0x00000400
1965 #define SWARB_GNT3 0x00000800
1966 #define SWARB_REQ0 0x00001000
1967 #define SWARB_REQ1 0x00002000
1968 #define SWARB_REQ2 0x00004000
1969 #define SWARB_REQ3 0x00008000
1970 #define NVRAM_ACCESS 0x00007024
1971 #define ACCESS_ENABLE 0x00000001
1972 #define ACCESS_WR_ENABLE 0x00000002
1973 #define NVRAM_WRITE1 0x00007028
1976 #define NVRAM_ADDR_LOCKOUT 0x00007030
1977 /* 0x7034 --> 0x7500 unused */
1979 #define OTP_MODE 0x00007500
1980 #define OTP_MODE_OTP_THRU_GRC 0x00000001
1981 #define OTP_CTRL 0x00007504
1982 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
1983 #define OTP_CTRL_OTP_CMD_READ 0x00000000
1984 #define OTP_CTRL_OTP_CMD_INIT 0x00000008
1985 #define OTP_CTRL_OTP_CMD_START 0x00000001
1986 #define OTP_STATUS 0x00007508
1987 #define OTP_STATUS_CMD_DONE 0x00000001
1988 #define OTP_ADDRESS 0x0000750c
1989 #define OTP_ADDRESS_MAGIC1 0x000000a0
1990 #define OTP_ADDRESS_MAGIC2 0x00000080
1993 #define OTP_READ_DATA 0x00007514
1994 /* 0x7518 --> 0x7c04 unused */
1996 #define PCIE_TRANSACTION_CFG 0x00007c04
1997 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
1998 #define PCIE_TRANS_CFG_LOM 0x00000020
1999 /* 0x7c08 --> 0x7d28 unused */
2001 #define PCIE_PWR_MGMT_THRESH 0x00007d28
2002 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2003 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2004 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2005 /* 0x7d2c --> 0x7d54 unused */
2007 #define TG3_PCIE_LNKCTL 0x00007d54
2008 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2009 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2010 /* 0x7d58 --> 0x7e70 unused */
2012 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2013 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2014 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2016 #define TG3_PCIE_EIDLE_DELAY 0x00007e70
2017 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2018 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2019 /* 0x7e74 --> 0x8000 unused */
2022 /* Alternate PCIE definitions */
2023 #define TG3_PCIE_TLDLPL_PORT 0x00007c00
2024 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2025 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2026 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2027 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2028 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2029 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2030 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2032 #define TG3_REG_BLK_SIZE 0x00008000
2034 /* OTP bit definitions */
2035 #define TG3_OTP_AGCTGT_MASK 0x000000e0
2036 #define TG3_OTP_AGCTGT_SHIFT 1
2037 #define TG3_OTP_HPFFLTR_MASK 0x00000300
2038 #define TG3_OTP_HPFFLTR_SHIFT 1
2039 #define TG3_OTP_HPFOVER_MASK 0x00000400
2040 #define TG3_OTP_HPFOVER_SHIFT 1
2041 #define TG3_OTP_LPFDIS_MASK 0x00000800
2042 #define TG3_OTP_LPFDIS_SHIFT 11
2043 #define TG3_OTP_VDAC_MASK 0xff000000
2044 #define TG3_OTP_VDAC_SHIFT 24
2045 #define TG3_OTP_10BTAMP_MASK 0x0000f000
2046 #define TG3_OTP_10BTAMP_SHIFT 8
2047 #define TG3_OTP_ROFF_MASK 0x00e00000
2048 #define TG3_OTP_ROFF_SHIFT 11
2049 #define TG3_OTP_RCOFF_MASK 0x001c0000
2050 #define TG3_OTP_RCOFF_SHIFT 16
2052 #define TG3_OTP_DEFAULT 0x286c1640
2055 /* Hardware Legacy NVRAM layout */
2056 #define TG3_NVM_VPD_OFF 0x100
2057 #define TG3_NVM_VPD_LEN 256
2059 /* Hardware Selfboot NVRAM layout */
2060 #define TG3_NVM_HWSB_CFG1 0x00000004
2061 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2062 #define TG3_NVM_HWSB_CFG1_MAJSFT 27
2063 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2064 #define TG3_NVM_HWSB_CFG1_MINSFT 22
2066 #define TG3_EEPROM_MAGIC 0x669955aa
2067 #define TG3_EEPROM_MAGIC_FW 0xa5000000
2068 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2069 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2070 #define TG3_EEPROM_SB_FORMAT_1 0x00200000
2071 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2072 #define TG3_EEPROM_SB_REVISION_0 0x00000000
2073 #define TG3_EEPROM_SB_REVISION_2 0x00020000
2074 #define TG3_EEPROM_SB_REVISION_3 0x00030000
2075 #define TG3_EEPROM_SB_REVISION_4 0x00040000
2076 #define TG3_EEPROM_SB_REVISION_5 0x00050000
2077 #define TG3_EEPROM_SB_REVISION_6 0x00060000
2078 #define TG3_EEPROM_MAGIC_HW 0xabcd
2079 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2081 #define TG3_NVM_DIR_START 0x18
2082 #define TG3_NVM_DIR_END 0x78
2083 #define TG3_NVM_DIRENT_SIZE 0xc
2084 #define TG3_NVM_DIRTYPE_SHIFT 24
2085 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2086 #define TG3_NVM_DIRTYPE_ASFINI 1
2087 #define TG3_NVM_DIRTYPE_EXTVPD 20
2088 #define TG3_NVM_PTREV_BCVER 0x94
2089 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2090 #define TG3_NVM_BCVER_MAJSFT 8
2091 #define TG3_NVM_BCVER_MINMSK 0x000000ff
2093 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2094 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2095 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2096 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2097 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2098 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2099 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2100 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2101 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2102 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2103 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2104 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2107 /* 32K Window into NIC internal memory */
2108 #define NIC_SRAM_WIN_BASE 0x00008000
2110 /* Offsets into first 32k of NIC internal memory. */
2111 #define NIC_SRAM_PAGE_ZERO 0x00000000
2112 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
2113 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
2114 #define NIC_SRAM_STATS_BLK 0x00000300
2115 #define NIC_SRAM_STATUS_BLK 0x00000b00
2117 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2118 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2119 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
2121 #define NIC_SRAM_DATA_SIG 0x00000b54
2122 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
2124 #define NIC_SRAM_DATA_CFG 0x00000b58
2125 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2126 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2127 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2128 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2129 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2130 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2131 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2132 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2133 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2134 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2135 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2136 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2137 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2138 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2139 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2141 #define NIC_SRAM_DATA_VER 0x00000b5c
2142 #define NIC_SRAM_DATA_VER_SHIFT 16
2144 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
2145 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2146 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2148 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2149 #define FWCMD_NICDRV_ALIVE 0x00000001
2150 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
2151 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2152 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2153 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
2154 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
2155 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2156 #define FWCMD_NICDRV_ALIVE2 0x0000000d
2157 #define FWCMD_NICDRV_ALIVE3 0x0000000e
2158 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2159 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2160 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2161 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2162 #define DRV_STATE_START 0x00000001
2163 #define DRV_STATE_START_DONE 0x80000001
2164 #define DRV_STATE_UNLOAD 0x00000002
2165 #define DRV_STATE_UNLOAD_DONE 0x80000002
2166 #define DRV_STATE_WOL 0x00000003
2167 #define DRV_STATE_SUSPEND 0x00000004
2169 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2171 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2172 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2174 #define NIC_SRAM_WOL_MBOX 0x00000d30
2175 #define WOL_SIGNATURE 0x474c0000
2176 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
2177 #define WOL_DRV_WOL 0x00000002
2178 #define WOL_SET_MAGIC_PKT 0x00000004
2180 #define NIC_SRAM_DATA_CFG_2 0x00000d38
2182 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
2183 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
2184 #define SHASTA_EXT_LED_LEGACY 0x00000000
2185 #define SHASTA_EXT_LED_SHARED 0x00008000
2186 #define SHASTA_EXT_LED_MAC 0x00010000
2187 #define SHASTA_EXT_LED_COMBO 0x00018000
2189 #define NIC_SRAM_DATA_CFG_3 0x00000d3c
2190 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2192 #define NIC_SRAM_DATA_CFG_4 0x00000d60
2193 #define NIC_SRAM_GMII_MODE 0x00000002
2194 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2195 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2196 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2198 #define NIC_SRAM_CPMU_STATUS 0x00000e00
2199 #define NIC_SRAM_CPMUSTAT_SIG 0x0000362c
2200 #define NIC_SRAM_CPMUSTAT_SIG_MSK 0x0000ffff
2202 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2204 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2205 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2206 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2207 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2208 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2209 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2210 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2211 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2212 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2213 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2215 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2216 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2217 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2219 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2220 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2223 /* Currently this is fixed. */
2224 #define TG3_PHY_MII_ADDR 0x01
2227 /*** Tigon3 specific PHY MII registers. ***/
2228 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2229 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2230 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2232 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2233 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2234 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2235 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2236 #define MII_TG3_EXT_CTRL_TBI 0x8000
2238 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2239 #define MII_TG3_EXT_STAT_MDIX 0x2000
2240 #define MII_TG3_EXT_STAT_LPASS 0x0100
2242 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2243 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2244 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2245 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2247 #define MII_TG3_DSP_TAP1 0x0001
2248 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2249 #define MII_TG3_DSP_TAP26 0x001a
2250 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2251 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2252 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2253 #define MII_TG3_DSP_AADJ1CH0 0x001f
2254 #define MII_TG3_DSP_CH34TP2 0x4022
2255 #define MII_TG3_DSP_CH34TP2_HIBW01 0x01ff
2256 #define MII_TG3_DSP_AADJ1CH3 0x601f
2257 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2258 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2259 #define MII_TG3_DSP_EXP8 0x0f08
2260 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2261 #define MII_TG3_DSP_EXP8_AEDW 0x0200
2262 #define MII_TG3_DSP_EXP75 0x0f75
2263 #define MII_TG3_DSP_EXP96 0x0f96
2264 #define MII_TG3_DSP_EXP97 0x0f97
2266 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
2268 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2269 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2270 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2271 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2272 #define MII_TG3_AUXCTL_ACTL_EXTLOOPBK 0x8000
2274 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2275 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2276 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2277 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2278 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2279 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2281 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2283 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2284 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2285 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2286 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2287 #define MII_TG3_AUXCTL_MISC_WREN 0x8000
2290 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
2291 #define MII_TG3_AUX_STAT_LPASS 0x0004
2292 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
2293 #define MII_TG3_AUX_STAT_10HALF 0x0100
2294 #define MII_TG3_AUX_STAT_10FULL 0x0200
2295 #define MII_TG3_AUX_STAT_100HALF 0x0300
2296 #define MII_TG3_AUX_STAT_100_4 0x0400
2297 #define MII_TG3_AUX_STAT_100FULL 0x0500
2298 #define MII_TG3_AUX_STAT_1000HALF 0x0600
2299 #define MII_TG3_AUX_STAT_1000FULL 0x0700
2300 #define MII_TG3_AUX_STAT_100 0x0008
2301 #define MII_TG3_AUX_STAT_FULL 0x0001
2303 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
2304 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
2306 /* ISTAT/IMASK event bits */
2307 #define MII_TG3_INT_LINKCHG 0x0002
2308 #define MII_TG3_INT_SPEEDCHG 0x0004
2309 #define MII_TG3_INT_DUPLEXCHG 0x0008
2310 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2312 #define MII_TG3_MISC_SHDW 0x1c
2313 #define MII_TG3_MISC_SHDW_WREN 0x8000
2315 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2316 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2317 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2319 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2320 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2321 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2322 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2323 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2324 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2326 #define MII_TG3_TEST1 0x1e
2327 #define MII_TG3_TEST1_TRIM_EN 0x0010
2328 #define MII_TG3_TEST1_CRC_EN 0x8000
2330 /* Clause 45 expansion registers */
2331 #define TG3_CL45_D7_EEERES_STAT 0x803e
2332 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2333 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2336 /* Fast Ethernet Tranceiver definitions */
2337 #define MII_TG3_FET_PTEST 0x17
2338 #define MII_TG3_FET_PTEST_TRIM_SEL 0x0010
2339 #define MII_TG3_FET_PTEST_TRIM_2 0x0002
2340 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2341 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2343 #define MII_TG3_FET_GEN_STAT 0x1c
2344 #define MII_TG3_FET_GEN_STAT_MDIXSTAT 0x2000
2346 #define MII_TG3_FET_TEST 0x1f
2347 #define MII_TG3_FET_SHADOW_EN 0x0080
2349 #define MII_TG3_FET_SHDW_MISCCTRL 0x10
2350 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2352 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2353 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2355 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2356 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2359 /* APE registers. Accessible through BAR1 */
2360 #define TG3_APE_GPIO_MSG 0x0008
2361 #define TG3_APE_GPIO_MSG_SHIFT 4
2362 #define TG3_APE_EVENT 0x000c
2363 #define APE_EVENT_1 0x00000001
2364 #define TG3_APE_LOCK_REQ 0x002c
2365 #define APE_LOCK_REQ_DRIVER 0x00001000
2366 #define TG3_APE_LOCK_GRANT 0x004c
2367 #define APE_LOCK_GRANT_DRIVER 0x00001000
2369 /* APE shared memory. Accessible through BAR1 */
2370 #define TG3_APE_SHMEM_BASE 0x4000
2371 #define TG3_APE_SEG_SIG 0x4000
2372 #define APE_SEG_SIG_MAGIC 0x41504521
2373 #define TG3_APE_FW_STATUS 0x400c
2374 #define APE_FW_STATUS_READY 0x00000100
2375 #define TG3_APE_FW_FEATURES 0x4010
2376 #define TG3_APE_FW_FEATURE_NCSI 0x00000002
2377 #define TG3_APE_FW_VERSION 0x4018
2378 #define APE_FW_VERSION_MAJMSK 0xff000000
2379 #define APE_FW_VERSION_MAJSFT 24
2380 #define APE_FW_VERSION_MINMSK 0x00ff0000
2381 #define APE_FW_VERSION_MINSFT 16
2382 #define APE_FW_VERSION_REVMSK 0x0000ff00
2383 #define APE_FW_VERSION_REVSFT 8
2384 #define APE_FW_VERSION_BLDMSK 0x000000ff
2385 #define TG3_APE_SEG_MSG_BUF_OFF 0x401c
2386 #define TG3_APE_SEG_MSG_BUF_LEN 0x4020
2387 #define TG3_APE_HOST_SEG_SIG 0x4200
2388 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2389 #define TG3_APE_HOST_SEG_LEN 0x4204
2390 #define APE_HOST_SEG_LEN_MAGIC 0x00000020
2391 #define TG3_APE_HOST_INIT_COUNT 0x4208
2392 #define TG3_APE_HOST_DRIVER_ID 0x420c
2393 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2394 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2395 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2396 #define TG3_APE_HOST_BEHAVIOR 0x4210
2397 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2398 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2399 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
2400 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
2401 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2402 #define TG3_APE_HOST_DRVR_STATE 0x421c
2403 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2404 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2405 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2406 #define TG3_APE_HOST_WOL_SPEED 0x4224
2407 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2409 #define TG3_APE_EVENT_STATUS 0x4300
2411 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2412 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2413 #define APE_EVENT_STATUS_SCRTCHPD_READ 0x00001600
2414 #define APE_EVENT_STATUS_SCRTCHPD_WRITE 0x00001700
2415 #define APE_EVENT_STATUS_STATE_START 0x00010000
2416 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2417 #define APE_EVENT_STATUS_STATE_WOL 0x00030000
2418 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2419 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2421 #define TG3_APE_PER_LOCK_REQ 0x8400
2422 #define APE_LOCK_PER_REQ_DRIVER 0x00001000
2423 #define TG3_APE_PER_LOCK_GRANT 0x8420
2424 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2426 /* APE convenience enumerations. */
2427 #define TG3_APE_LOCK_PHY0 0
2428 #define TG3_APE_LOCK_GRC 1
2429 #define TG3_APE_LOCK_PHY1 2
2430 #define TG3_APE_LOCK_PHY2 3
2431 #define TG3_APE_LOCK_MEM 4
2432 #define TG3_APE_LOCK_PHY3 5
2433 #define TG3_APE_LOCK_GPIO 7
2435 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2438 /* There are two ways to manage the TX descriptors on the tigon3.
2439 * Either the descriptors are in host DMA'able memory, or they
2440 * exist only in the cards on-chip SRAM. All 16 send bds are under
2441 * the same mode, they may not be configured individually.
2443 * This driver always uses host memory TX descriptors.
2445 * To use host memory TX descriptors:
2446 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2447 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2448 * 2) Allocate DMA'able memory.
2449 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2450 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2451 * obtained in step 2
2452 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2453 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2454 * of TX descriptors. Leave flags field clear.
2455 * 4) Access TX descriptors via host memory. The chip
2456 * will refetch into local SRAM as needed when producer
2457 * index mailboxes are updated.
2459 * To use on-chip TX descriptors:
2460 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2461 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2462 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2463 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2464 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2465 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2466 * 3) Access TX descriptors directly in on-chip SRAM
2467 * using normal {read,write}l(). (and not using
2468 * pointer dereferencing of ioremap()'d memory like
2469 * the broken Broadcom driver does)
2471 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2472 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2474 struct tg3_tx_buffer_desc {
2479 #define TXD_FLAG_TCPUDP_CSUM 0x0001
2480 #define TXD_FLAG_IP_CSUM 0x0002
2481 #define TXD_FLAG_END 0x0004
2482 #define TXD_FLAG_IP_FRAG 0x0008
2483 #define TXD_FLAG_JMB_PKT 0x0008
2484 #define TXD_FLAG_IP_FRAG_END 0x0010
2485 #define TXD_FLAG_HWTSTAMP 0x0020
2486 #define TXD_FLAG_VLAN 0x0040
2487 #define TXD_FLAG_COAL_NOW 0x0080
2488 #define TXD_FLAG_CPU_PRE_DMA 0x0100
2489 #define TXD_FLAG_CPU_POST_DMA 0x0200
2490 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
2491 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2492 #define TXD_FLAG_NO_CRC 0x8000
2493 #define TXD_LEN_SHIFT 16
2496 #define TXD_VLAN_TAG_SHIFT 0
2497 #define TXD_MSS_SHIFT 16
2500 #define TXD_ADDR 0x00UL /* 64-bit */
2501 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2502 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2503 #define TXD_SIZE 0x10UL
2505 struct tg3_rx_buffer_desc {
2510 #define RXD_IDX_MASK 0xffff0000
2511 #define RXD_IDX_SHIFT 16
2512 #define RXD_LEN_MASK 0x0000ffff
2513 #define RXD_LEN_SHIFT 0
2516 #define RXD_TYPE_SHIFT 16
2517 #define RXD_FLAGS_SHIFT 0
2519 #define RXD_FLAG_END 0x0004
2520 #define RXD_FLAG_MINI 0x0800
2521 #define RXD_FLAG_JUMBO 0x0020
2522 #define RXD_FLAG_VLAN 0x0040
2523 #define RXD_FLAG_ERROR 0x0400
2524 #define RXD_FLAG_IP_CSUM 0x1000
2525 #define RXD_FLAG_TCPUDP_CSUM 0x2000
2526 #define RXD_FLAG_IS_TCP 0x4000
2527 #define RXD_FLAG_PTPSTAT_MASK 0x0210
2528 #define RXD_FLAG_PTPSTAT_PTPV1 0x0010
2529 #define RXD_FLAG_PTPSTAT_PTPV2 0x0200
2532 #define RXD_IPCSUM_MASK 0xffff0000
2533 #define RXD_IPCSUM_SHIFT 16
2534 #define RXD_TCPCSUM_MASK 0x0000ffff
2535 #define RXD_TCPCSUM_SHIFT 0
2539 #define RXD_VLAN_MASK 0x0000ffff
2541 #define RXD_ERR_BAD_CRC 0x00010000
2542 #define RXD_ERR_COLLISION 0x00020000
2543 #define RXD_ERR_LINK_LOST 0x00040000
2544 #define RXD_ERR_PHY_DECODE 0x00080000
2545 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2546 #define RXD_ERR_MAC_ABRT 0x00200000
2547 #define RXD_ERR_TOO_SMALL 0x00400000
2548 #define RXD_ERR_NO_RESOURCES 0x00800000
2549 #define RXD_ERR_HUGE_FRAME 0x01000000
2550 #define RXD_ERR_MASK 0xffff0000
2554 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2555 #define RXD_OPAQUE_INDEX_SHIFT 0
2556 #define RXD_OPAQUE_RING_STD 0x00010000
2557 #define RXD_OPAQUE_RING_JUMBO 0x00020000
2558 #define RXD_OPAQUE_RING_MINI 0x00040000
2559 #define RXD_OPAQUE_RING_MASK 0x00070000
2562 struct tg3_ext_rx_buffer_desc {
2569 struct tg3_rx_buffer_desc std;
2572 /* We only use this when testing out the DMA engine
2573 * at probe time. This is the internal format of buffer
2574 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2576 struct tg3_internal_buffer_desc {
2594 #define TG3_HW_STATUS_SIZE 0x50
2595 struct tg3_hw_status {
2597 #define SD_STATUS_UPDATED 0x00000001
2598 #define SD_STATUS_LINK_CHG 0x00000002
2599 #define SD_STATUS_ERROR 0x00000004
2605 u16 rx_jumbo_consumer;
2607 u16 rx_jumbo_consumer;
2613 u16 rx_mini_consumer;
2615 u16 rx_mini_consumer;
2633 struct tg3_hw_stats {
2634 u8 __reserved0[0x400-0x300];
2636 /* Statistics maintained by Receive MAC. */
2637 tg3_stat64_t rx_octets;
2639 tg3_stat64_t rx_fragments;
2640 tg3_stat64_t rx_ucast_packets;
2641 tg3_stat64_t rx_mcast_packets;
2642 tg3_stat64_t rx_bcast_packets;
2643 tg3_stat64_t rx_fcs_errors;
2644 tg3_stat64_t rx_align_errors;
2645 tg3_stat64_t rx_xon_pause_rcvd;
2646 tg3_stat64_t rx_xoff_pause_rcvd;
2647 tg3_stat64_t rx_mac_ctrl_rcvd;
2648 tg3_stat64_t rx_xoff_entered;
2649 tg3_stat64_t rx_frame_too_long_errors;
2650 tg3_stat64_t rx_jabbers;
2651 tg3_stat64_t rx_undersize_packets;
2652 tg3_stat64_t rx_in_length_errors;
2653 tg3_stat64_t rx_out_length_errors;
2654 tg3_stat64_t rx_64_or_less_octet_packets;
2655 tg3_stat64_t rx_65_to_127_octet_packets;
2656 tg3_stat64_t rx_128_to_255_octet_packets;
2657 tg3_stat64_t rx_256_to_511_octet_packets;
2658 tg3_stat64_t rx_512_to_1023_octet_packets;
2659 tg3_stat64_t rx_1024_to_1522_octet_packets;
2660 tg3_stat64_t rx_1523_to_2047_octet_packets;
2661 tg3_stat64_t rx_2048_to_4095_octet_packets;
2662 tg3_stat64_t rx_4096_to_8191_octet_packets;
2663 tg3_stat64_t rx_8192_to_9022_octet_packets;
2667 /* Statistics maintained by Transmit MAC. */
2668 tg3_stat64_t tx_octets;
2670 tg3_stat64_t tx_collisions;
2671 tg3_stat64_t tx_xon_sent;
2672 tg3_stat64_t tx_xoff_sent;
2673 tg3_stat64_t tx_flow_control;
2674 tg3_stat64_t tx_mac_errors;
2675 tg3_stat64_t tx_single_collisions;
2676 tg3_stat64_t tx_mult_collisions;
2677 tg3_stat64_t tx_deferred;
2679 tg3_stat64_t tx_excessive_collisions;
2680 tg3_stat64_t tx_late_collisions;
2681 tg3_stat64_t tx_collide_2times;
2682 tg3_stat64_t tx_collide_3times;
2683 tg3_stat64_t tx_collide_4times;
2684 tg3_stat64_t tx_collide_5times;
2685 tg3_stat64_t tx_collide_6times;
2686 tg3_stat64_t tx_collide_7times;
2687 tg3_stat64_t tx_collide_8times;
2688 tg3_stat64_t tx_collide_9times;
2689 tg3_stat64_t tx_collide_10times;
2690 tg3_stat64_t tx_collide_11times;
2691 tg3_stat64_t tx_collide_12times;
2692 tg3_stat64_t tx_collide_13times;
2693 tg3_stat64_t tx_collide_14times;
2694 tg3_stat64_t tx_collide_15times;
2695 tg3_stat64_t tx_ucast_packets;
2696 tg3_stat64_t tx_mcast_packets;
2697 tg3_stat64_t tx_bcast_packets;
2698 tg3_stat64_t tx_carrier_sense_errors;
2699 tg3_stat64_t tx_discards;
2700 tg3_stat64_t tx_errors;
2704 /* Statistics maintained by Receive List Placement. */
2705 tg3_stat64_t COS_rx_packets[16];
2706 tg3_stat64_t COS_rx_filter_dropped;
2707 tg3_stat64_t dma_writeq_full;
2708 tg3_stat64_t dma_write_prioq_full;
2709 tg3_stat64_t rxbds_empty;
2710 tg3_stat64_t rx_discards;
2711 tg3_stat64_t rx_errors;
2712 tg3_stat64_t rx_threshold_hit;
2716 /* Statistics maintained by Send Data Initiator. */
2717 tg3_stat64_t COS_out_packets[16];
2718 tg3_stat64_t dma_readq_full;
2719 tg3_stat64_t dma_read_prioq_full;
2720 tg3_stat64_t tx_comp_queue_full;
2722 /* Statistics maintained by Host Coalescing. */
2723 tg3_stat64_t ring_set_send_prod_index;
2724 tg3_stat64_t ring_status_update;
2725 tg3_stat64_t nic_irqs;
2726 tg3_stat64_t nic_avoided_irqs;
2727 tg3_stat64_t nic_tx_threshold_hit;
2729 /* NOT a part of the hardware statistics block format.
2730 * These stats are here as storage for tg3_periodic_fetch_stats().
2732 tg3_stat64_t mbuf_lwm_thresh_hit;
2734 u8 __reserved4[0xb00-0x9c8];
2737 #define TG3_SD_NUM_RECS 3
2738 #define TG3_OCIR_LEN (sizeof(struct tg3_ocir))
2739 #define TG3_OCIR_SIG_MAGIC 0x5253434f
2740 #define TG3_OCIR_FLAG_ACTIVE 0x00000001
2742 #define TG3_TEMP_CAUTION_OFFSET 0xc8
2743 #define TG3_TEMP_MAX_OFFSET 0xcc
2744 #define TG3_TEMP_SENSOR_OFFSET 0xd4
2756 u16 src_data_offset;
2757 u16 src_data_length;
2759 u16 dst_data_offset;
2760 u16 dst_reg_upd_offset;
2771 /* 'mapping' is superfluous as the chip does not write into
2772 * the tx/rx post rings so we could just fetch it from there.
2773 * But the cache behavior is better how we are doing it now.
2775 * This driver uses new build_skb() API :
2776 * RX ring buffer contains pointer to kmalloc() data only,
2777 * skb are built only after Hardware filled the frame.
2781 DEFINE_DMA_UNMAP_ADDR(mapping);
2784 struct tg3_tx_ring_info {
2785 struct sk_buff *skb;
2786 DEFINE_DMA_UNMAP_ADDR(mapping);
2790 struct tg3_link_config {
2791 /* Describes what we're trying to get. */
2798 /* Describes what we actually have. */
2806 struct tg3_bufmgr_config {
2807 u32 mbuf_read_dma_low_water;
2808 u32 mbuf_mac_rx_low_water;
2809 u32 mbuf_high_water;
2811 u32 mbuf_read_dma_low_water_jumbo;
2812 u32 mbuf_mac_rx_low_water_jumbo;
2813 u32 mbuf_high_water_jumbo;
2819 struct tg3_ethtool_stats {
2820 /* Statistics maintained by Receive MAC. */
2823 u64 rx_ucast_packets;
2824 u64 rx_mcast_packets;
2825 u64 rx_bcast_packets;
2827 u64 rx_align_errors;
2828 u64 rx_xon_pause_rcvd;
2829 u64 rx_xoff_pause_rcvd;
2830 u64 rx_mac_ctrl_rcvd;
2831 u64 rx_xoff_entered;
2832 u64 rx_frame_too_long_errors;
2834 u64 rx_undersize_packets;
2835 u64 rx_in_length_errors;
2836 u64 rx_out_length_errors;
2837 u64 rx_64_or_less_octet_packets;
2838 u64 rx_65_to_127_octet_packets;
2839 u64 rx_128_to_255_octet_packets;
2840 u64 rx_256_to_511_octet_packets;
2841 u64 rx_512_to_1023_octet_packets;
2842 u64 rx_1024_to_1522_octet_packets;
2843 u64 rx_1523_to_2047_octet_packets;
2844 u64 rx_2048_to_4095_octet_packets;
2845 u64 rx_4096_to_8191_octet_packets;
2846 u64 rx_8192_to_9022_octet_packets;
2848 /* Statistics maintained by Transmit MAC. */
2853 u64 tx_flow_control;
2855 u64 tx_single_collisions;
2856 u64 tx_mult_collisions;
2858 u64 tx_excessive_collisions;
2859 u64 tx_late_collisions;
2860 u64 tx_collide_2times;
2861 u64 tx_collide_3times;
2862 u64 tx_collide_4times;
2863 u64 tx_collide_5times;
2864 u64 tx_collide_6times;
2865 u64 tx_collide_7times;
2866 u64 tx_collide_8times;
2867 u64 tx_collide_9times;
2868 u64 tx_collide_10times;
2869 u64 tx_collide_11times;
2870 u64 tx_collide_12times;
2871 u64 tx_collide_13times;
2872 u64 tx_collide_14times;
2873 u64 tx_collide_15times;
2874 u64 tx_ucast_packets;
2875 u64 tx_mcast_packets;
2876 u64 tx_bcast_packets;
2877 u64 tx_carrier_sense_errors;
2881 /* Statistics maintained by Receive List Placement. */
2882 u64 dma_writeq_full;
2883 u64 dma_write_prioq_full;
2887 u64 rx_threshold_hit;
2889 /* Statistics maintained by Send Data Initiator. */
2891 u64 dma_read_prioq_full;
2892 u64 tx_comp_queue_full;
2894 /* Statistics maintained by Host Coalescing. */
2895 u64 ring_set_send_prod_index;
2896 u64 ring_status_update;
2898 u64 nic_avoided_irqs;
2899 u64 nic_tx_threshold_hit;
2901 u64 mbuf_lwm_thresh_hit;
2904 struct tg3_rx_prodring_set {
2905 u32 rx_std_prod_idx;
2906 u32 rx_std_cons_idx;
2907 u32 rx_jmb_prod_idx;
2908 u32 rx_jmb_cons_idx;
2909 struct tg3_rx_buffer_desc *rx_std;
2910 struct tg3_ext_rx_buffer_desc *rx_jmb;
2911 struct ring_info *rx_std_buffers;
2912 struct ring_info *rx_jmb_buffers;
2913 dma_addr_t rx_std_mapping;
2914 dma_addr_t rx_jmb_mapping;
2917 #define TG3_RSS_MAX_NUM_QS 4
2918 #define TG3_IRQ_MAX_VECS_RSS (TG3_RSS_MAX_NUM_QS + 1)
2919 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2922 struct napi_struct napi ____cacheline_aligned;
2924 struct tg3_hw_status *hw_status;
2932 u32 consmbox ____cacheline_aligned;
2935 u16 *rx_rcb_prod_idx;
2936 struct tg3_rx_prodring_set prodring;
2937 struct tg3_rx_buffer_desc *rx_rcb;
2939 u32 tx_prod ____cacheline_aligned;
2944 struct tg3_tx_buffer_desc *tx_ring;
2945 struct tg3_tx_ring_info *tx_buffers;
2947 dma_addr_t status_mapping;
2948 dma_addr_t rx_rcb_mapping;
2949 dma_addr_t tx_desc_mapping;
2951 char irq_lbl[IFNAMSIZ];
2952 unsigned int irq_vec;
2956 TG3_FLAG_TAGGED_STATUS = 0,
2957 TG3_FLAG_TXD_MBOX_HWBUG,
2958 TG3_FLAG_USE_LINKCHG_REG,
2959 TG3_FLAG_ERROR_PROCESSED,
2960 TG3_FLAG_ENABLE_ASF,
2961 TG3_FLAG_ASPM_WORKAROUND,
2962 TG3_FLAG_POLL_SERDES,
2963 TG3_FLAG_MBOX_WRITE_REORDER,
2964 TG3_FLAG_PCIX_TARGET_HWBUG,
2965 TG3_FLAG_WOL_SPEED_100MB,
2966 TG3_FLAG_WOL_ENABLE,
2967 TG3_FLAG_EEPROM_WRITE_PROT,
2969 TG3_FLAG_NVRAM_BUFFERED,
2970 TG3_FLAG_SUPPORT_MSI,
2971 TG3_FLAG_SUPPORT_MSIX,
2973 TG3_FLAG_USING_MSIX,
2975 TG3_FLAG_PCI_HIGH_SPEED,
2977 TG3_FLAG_SRAM_USE_CONFIG,
2978 TG3_FLAG_TX_RECOVERY_PENDING,
2980 TG3_FLAG_JUMBO_RING_ENABLE,
2981 TG3_FLAG_PAUSE_AUTONEG,
2982 TG3_FLAG_CPMU_PRESENT,
2983 TG3_FLAG_40BIT_DMA_BUG,
2984 TG3_FLAG_BROKEN_CHECKSUMS,
2985 TG3_FLAG_JUMBO_CAPABLE,
2986 TG3_FLAG_CHIP_RESETTING,
2987 TG3_FLAG_INIT_COMPLETE,
2989 TG3_FLAG_MAX_RXPEND_64,
2990 TG3_FLAG_TSO_CAPABLE,
2991 TG3_FLAG_PCI_EXPRESS, /* BCM5785 + pci_is_pcie() */
2992 TG3_FLAG_ASF_NEW_HANDSHAKE,
2993 TG3_FLAG_HW_AUTONEG,
2999 TG3_FLAG_ICH_WORKAROUND,
3001 TG3_FLAG_NO_FWARE_REPORTED,
3002 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
3003 TG3_FLAG_ENABLE_APE,
3004 TG3_FLAG_PROTECTED_NVRAM,
3005 TG3_FLAG_5701_DMA_BUG,
3006 TG3_FLAG_USE_PHYLIB,
3007 TG3_FLAG_MDIOBUS_INITED,
3008 TG3_FLAG_LRG_PROD_RING_CAP,
3009 TG3_FLAG_RGMII_INBAND_DISABLE,
3010 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
3011 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
3012 TG3_FLAG_CLKREQ_BUG,
3014 TG3_FLAG_ENABLE_RSS,
3015 TG3_FLAG_ENABLE_TSS,
3016 TG3_FLAG_SHORT_DMA_BUG,
3017 TG3_FLAG_USE_JUMBO_BDFLAG,
3018 TG3_FLAG_L1PLLPD_EN,
3019 TG3_FLAG_APE_HAS_NCSI,
3020 TG3_FLAG_TX_TSTAMP_EN,
3021 TG3_FLAG_4K_FIFO_LIMIT,
3022 TG3_FLAG_5719_RDMA_BUG,
3023 TG3_FLAG_RESET_TASK_PENDING,
3024 TG3_FLAG_PTP_CAPABLE,
3028 TG3_FLAG_5780_CLASS,
3030 TG3_FLAG_57765_PLUS,
3031 TG3_FLAG_57765_CLASS,
3034 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3035 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
3039 /* begin "general, frequently-used members" cacheline section */
3041 /* If the IRQ handler (which runs lockless) needs to be
3042 * quiesced, the following bitmask state is used. The
3043 * SYNC flag is set by non-IRQ context code to initiate
3046 * When the IRQ handler notices that SYNC is set, it
3047 * disables interrupts and returns.
3049 * When all outstanding IRQ handlers have returned after
3050 * the SYNC flag has been set, the setter can be assured
3051 * that interrupts will no longer get run.
3053 * In this way all SMP driver locks are never acquired
3054 * in hw IRQ context, only sw IRQ context or lower.
3056 unsigned int irq_sync;
3058 /* SMP locking strategy:
3060 * lock: Held during reset, PHY access, timer, and when
3061 * updating tg3_flags.
3063 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3064 * netif_tx_lock when it needs to call
3067 * Both of these locks are to be held with BH safety.
3069 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3070 * are running lockless, it is necessary to completely
3071 * quiesce the chip with tg3_netif_stop and tg3_full_lock
3072 * before reconfiguring the device.
3074 * indirect_lock: Held when accessing registers indirectly
3075 * with IRQ disabling.
3078 spinlock_t indirect_lock;
3080 u32 (*read32) (struct tg3 *, u32);
3081 void (*write32) (struct tg3 *, u32, u32);
3082 u32 (*read32_mbox) (struct tg3 *, u32);
3083 void (*write32_mbox) (struct tg3 *, u32,
3086 void __iomem *aperegs;
3087 struct net_device *dev;
3088 struct pci_dev *pdev;
3093 struct ptp_clock_info ptp_info;
3094 struct ptp_clock *ptp_clock;
3097 /* begin "tx thread" cacheline section */
3098 void (*write32_tx_mbox) (struct tg3 *, u32,
3105 /* begin "rx thread" cacheline section */
3106 struct tg3_napi napi[TG3_IRQ_MAX_VECS];
3107 void (*write32_rx_mbox) (struct tg3 *, u32,
3110 u32 rx_std_ring_mask;
3111 u32 rx_jmb_ring_mask;
3112 u32 rx_ret_ring_mask;
3114 u32 rx_jumbo_pending;
3115 u32 rx_std_max_post;
3124 /* begin "everything else" cacheline(s) section */
3125 unsigned long rx_dropped;
3126 unsigned long tx_dropped;
3127 struct rtnl_link_stats64 net_stats_prev;
3128 struct tg3_ethtool_stats estats_prev;
3130 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3133 unsigned long phy_crc_errors;
3134 unsigned long last_event_jiffies;
3137 struct timer_list timer;
3139 u16 timer_multiplier;
3144 /* 1 second counter for transient serdes link events */
3146 #define SERDES_AN_TIMEOUT_5704S 2
3147 #define SERDES_PARALLEL_DET_TIMEOUT 1
3148 #define SERDES_AN_TIMEOUT_5714S 1
3150 struct tg3_link_config link_config;
3151 struct tg3_bufmgr_config bufmgr_config;
3153 /* cache h/w values, often passed straight to h/w */
3167 u32 pci_chip_rev_id;
3169 u8 pci_cacheline_sz;
3178 struct mii_bus *mdio_bus;
3179 int mdio_irq[PHY_MAX_ADDR];
3187 #define TG3_PHY_ID_MASK 0xfffffff0
3188 #define TG3_PHY_ID_BCM5400 0x60008040
3189 #define TG3_PHY_ID_BCM5401 0x60008050
3190 #define TG3_PHY_ID_BCM5411 0x60008070
3191 #define TG3_PHY_ID_BCM5701 0x60008110
3192 #define TG3_PHY_ID_BCM5703 0x60008160
3193 #define TG3_PHY_ID_BCM5704 0x60008190
3194 #define TG3_PHY_ID_BCM5705 0x600081a0
3195 #define TG3_PHY_ID_BCM5750 0x60008180
3196 #define TG3_PHY_ID_BCM5752 0x60008100
3197 #define TG3_PHY_ID_BCM5714 0x60008340
3198 #define TG3_PHY_ID_BCM5780 0x60008350
3199 #define TG3_PHY_ID_BCM5755 0xbc050cc0
3200 #define TG3_PHY_ID_BCM5787 0xbc050ce0
3201 #define TG3_PHY_ID_BCM5756 0xbc050ed0
3202 #define TG3_PHY_ID_BCM5784 0xbc050fa0
3203 #define TG3_PHY_ID_BCM5761 0xbc050fd0
3204 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3205 #define TG3_PHY_ID_BCM5718S 0xbc050ff0
3206 #define TG3_PHY_ID_BCM57765 0x5c0d8a40
3207 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3208 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3209 #define TG3_PHY_ID_BCM5906 0xdc00ac40
3210 #define TG3_PHY_ID_BCM8002 0x60010140
3211 #define TG3_PHY_ID_INVALID 0xffffffff
3213 #define PHY_ID_RTL8211C 0x001cc910
3214 #define PHY_ID_RTL8201E 0x00008200
3216 #define TG3_PHY_ID_REV_MASK 0x0000000f
3217 #define TG3_PHY_REV_BCM5401_B0 0x1
3219 /* This macro assumes the passed PHY ID is
3220 * already masked with TG3_PHY_ID_MASK.
3222 #define TG3_KNOWN_PHY_ID(X) \
3223 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3224 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3225 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3226 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3227 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3228 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3229 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3230 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3231 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3232 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3233 (X) == TG3_PHY_ID_BCM8002)
3236 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3237 #define TG3_PHYFLG_IS_CONNECTED 0x00000002
3238 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3239 #define TG3_PHYFLG_PHY_SERDES 0x00000010
3240 #define TG3_PHYFLG_MII_SERDES 0x00000020
3241 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3242 TG3_PHYFLG_MII_SERDES)
3243 #define TG3_PHYFLG_IS_FET 0x00000040
3244 #define TG3_PHYFLG_10_100_ONLY 0x00000080
3245 #define TG3_PHYFLG_ENABLE_APD 0x00000100
3246 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3247 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3248 #define TG3_PHYFLG_JITTER_BUG 0x00000800
3249 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3250 #define TG3_PHYFLG_ADC_BUG 0x00002000
3251 #define TG3_PHYFLG_5704_A0_BUG 0x00004000
3252 #define TG3_PHYFLG_BER_BUG 0x00008000
3253 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3254 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3255 #define TG3_PHYFLG_EEE_CAP 0x00040000
3256 #define TG3_PHYFLG_MDIX_STATE 0x00200000
3261 u8 rss_ind_tbl[TG3_RSS_INDIR_TBL_SIZE];
3263 #define TG3_BPN_SIZE 24
3264 char board_part_number[TG3_BPN_SIZE];
3265 #define TG3_VER_SIZE ETHTOOL_FWVERS_LEN
3266 char fw_ver[TG3_VER_SIZE];
3267 u32 nic_sram_data_cfg;
3269 struct pci_dev *pdev_peer;
3271 struct tg3_hw_stats *hw_stats;
3272 dma_addr_t stats_mapping;
3273 struct work_struct reset_task;
3277 #define TG3_NVRAM_SIZE_2KB 0x00000800
3278 #define TG3_NVRAM_SIZE_64KB 0x00010000
3279 #define TG3_NVRAM_SIZE_128KB 0x00020000
3280 #define TG3_NVRAM_SIZE_256KB 0x00040000
3281 #define TG3_NVRAM_SIZE_512KB 0x00080000
3282 #define TG3_NVRAM_SIZE_1MB 0x00100000
3283 #define TG3_NVRAM_SIZE_2MB 0x00200000
3288 #define JEDEC_ATMEL 0x1f
3289 #define JEDEC_ST 0x20
3290 #define JEDEC_SAIFUN 0x4f
3291 #define JEDEC_SST 0xbf
3293 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3294 #define ATMEL_AT24C02_PAGE_SIZE (8)
3296 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3297 #define ATMEL_AT24C64_PAGE_SIZE (32)
3299 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3300 #define ATMEL_AT24C512_PAGE_SIZE (128)
3302 #define ATMEL_AT45DB0X1B_PAGE_POS 9
3303 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3305 #define ATMEL_AT25F512_PAGE_SIZE 256
3307 #define ST_M45PEX0_PAGE_SIZE 256
3309 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
3311 #define SST_25VF0X0_PAGE_SIZE 4098
3313 unsigned int irq_max;
3314 unsigned int irq_cnt;
3316 struct ethtool_coalesce coal;
3319 const char *fw_needed;
3320 const struct firmware *fw;
3321 u32 fw_len; /* includes BSS */
3323 #if IS_ENABLED(CONFIG_HWMON)
3324 struct device *hwmon_dev;
3329 #endif /* !(_T3_H) */