2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
40 #include <linux/bitops.h>
41 #include <linux/cache.h>
42 #include <linux/interrupt.h>
43 #include <linux/list.h>
44 #include <linux/netdevice.h>
45 #include <linux/pci.h>
46 #include <linux/spinlock.h>
47 #include <linux/timer.h>
48 #include <linux/vmalloc.h>
49 #include <linux/etherdevice.h>
50 #include <linux/net_tstamp.h>
52 #include "t4_chip_type.h"
53 #include "cxgb4_uld.h"
55 #define CH_WARN(adap, fmt, ...) dev_warn(adap->pdev_dev, fmt, ## __VA_ARGS__)
56 extern struct list_head adapter_list;
57 extern struct mutex uld_mutex;
60 MAX_NPORTS = 4, /* max # of ports */
61 SERNUM_LEN = 24, /* Serial # length */
62 EC_LEN = 16, /* E/C length */
63 ID_LEN = 16, /* ID length */
64 PN_LEN = 16, /* Part Number length */
65 MACADDR_LEN = 12, /* MAC Address length */
69 T4_REGMAP_SIZE = (160 * 1024),
70 T5_REGMAP_SIZE = (332 * 1024),
82 MEMWIN0_APERTURE = 2048,
83 MEMWIN0_BASE = 0x1b800,
84 MEMWIN1_APERTURE = 32768,
85 MEMWIN1_BASE = 0x28000,
86 MEMWIN1_BASE_T5 = 0x52000,
87 MEMWIN2_APERTURE = 65536,
88 MEMWIN2_BASE = 0x30000,
89 MEMWIN2_APERTURE_T5 = 131072,
90 MEMWIN2_BASE_T5 = 0x60000,
108 PAUSE_AUTONEG = 1 << 2
112 u64 tx_octets; /* total # of octets in good frames */
113 u64 tx_frames; /* all good frames */
114 u64 tx_bcast_frames; /* all broadcast frames */
115 u64 tx_mcast_frames; /* all multicast frames */
116 u64 tx_ucast_frames; /* all unicast frames */
117 u64 tx_error_frames; /* all error frames */
119 u64 tx_frames_64; /* # of Tx frames in a particular range */
120 u64 tx_frames_65_127;
121 u64 tx_frames_128_255;
122 u64 tx_frames_256_511;
123 u64 tx_frames_512_1023;
124 u64 tx_frames_1024_1518;
125 u64 tx_frames_1519_max;
127 u64 tx_drop; /* # of dropped Tx frames */
128 u64 tx_pause; /* # of transmitted pause frames */
129 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
130 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
131 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
132 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
133 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
134 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
135 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
136 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
138 u64 rx_octets; /* total # of octets in good frames */
139 u64 rx_frames; /* all good frames */
140 u64 rx_bcast_frames; /* all broadcast frames */
141 u64 rx_mcast_frames; /* all multicast frames */
142 u64 rx_ucast_frames; /* all unicast frames */
143 u64 rx_too_long; /* # of frames exceeding MTU */
144 u64 rx_jabber; /* # of jabber frames */
145 u64 rx_fcs_err; /* # of received frames with bad FCS */
146 u64 rx_len_err; /* # of received frames with length error */
147 u64 rx_symbol_err; /* symbol errors */
148 u64 rx_runt; /* # of short frames */
150 u64 rx_frames_64; /* # of Rx frames in a particular range */
151 u64 rx_frames_65_127;
152 u64 rx_frames_128_255;
153 u64 rx_frames_256_511;
154 u64 rx_frames_512_1023;
155 u64 rx_frames_1024_1518;
156 u64 rx_frames_1519_max;
158 u64 rx_pause; /* # of received pause frames */
159 u64 rx_ppp0; /* # of received PPP prio 0 frames */
160 u64 rx_ppp1; /* # of received PPP prio 1 frames */
161 u64 rx_ppp2; /* # of received PPP prio 2 frames */
162 u64 rx_ppp3; /* # of received PPP prio 3 frames */
163 u64 rx_ppp4; /* # of received PPP prio 4 frames */
164 u64 rx_ppp5; /* # of received PPP prio 5 frames */
165 u64 rx_ppp6; /* # of received PPP prio 6 frames */
166 u64 rx_ppp7; /* # of received PPP prio 7 frames */
168 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
169 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
170 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
171 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
172 u64 rx_trunc0; /* buffer-group 0 truncated packets */
173 u64 rx_trunc1; /* buffer-group 1 truncated packets */
174 u64 rx_trunc2; /* buffer-group 2 truncated packets */
175 u64 rx_trunc3; /* buffer-group 3 truncated packets */
178 struct lb_port_stats {
191 u64 frames_1024_1518;
206 struct tp_tcp_stats {
210 u64 tcp_retrans_segs;
213 struct tp_usm_stats {
219 struct tp_fcoe_stats {
225 struct tp_err_stats {
229 u32 tnl_cong_drops[4];
230 u32 ofld_chan_drops[4];
232 u32 ofld_vlan_drops[4];
238 struct tp_cpl_stats {
243 struct tp_rdma_stats {
249 u32 hps; /* host page size for our PF/VF */
250 u32 eq_qpp; /* egress queues/page for our PF/VF */
251 u32 iq_qpp; /* egress queues/page for our PF/VF */
255 unsigned int tre; /* log2 of core clocks per TP tick */
256 unsigned int la_mask; /* what events are recorded by TP LA */
257 unsigned short tx_modq_map; /* TX modulation scheduler queue to */
260 uint32_t dack_re; /* DACK timer resolution */
261 unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
263 u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
264 u32 ingress_config; /* cached TP_INGRESS_CONFIG */
266 /* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
267 * subset of the set of fields which may be present in the Compressed
268 * Filter Tuple portion of filters and TCP TCB connections. The
269 * fields which are present are controlled by the TP_VLAN_PRI_MAP.
270 * Since a variable number of fields may or may not be present, their
271 * shifted field positions within the Compressed Filter Tuple may
272 * vary, or not even be present if the field isn't selected in
273 * TP_VLAN_PRI_MAP. Since some of these fields are needed in various
274 * places we store their offsets here, or a -1 if the field isn't
286 u8 sn[SERNUM_LEN + 1];
289 u8 na[MACADDR_LEN + 1];
297 struct devlog_params {
298 u32 memtype; /* which memory (EDC0, EDC1, MC) */
299 u32 start; /* start of log in firmware memory */
300 u32 size; /* size of log */
303 /* Stores chip specific parameters */
304 struct arch_specific_params {
307 u8 cng_ch_bits_log; /* congestion channel map bits width */
314 struct adapter_params {
315 struct sge_params sge;
317 struct vpd_params vpd;
318 struct pci_params pci;
319 struct devlog_params devlog;
320 enum pcie_memwin drv_memwin;
322 unsigned int cim_la_size;
324 unsigned int sf_size; /* serial flash size in bytes */
325 unsigned int sf_nsec; /* # of flash sectors */
326 unsigned int sf_fw_start; /* start of FW image in flash */
328 unsigned int fw_vers;
329 unsigned int bs_vers; /* bootstrap version */
330 unsigned int tp_vers;
331 unsigned int er_vers; /* expansion ROM version */
334 unsigned short mtus[NMTUS];
335 unsigned short a_wnd[NCCTRL_WIN];
336 unsigned short b_wnd[NCCTRL_WIN];
338 unsigned char nports; /* # of ethernet ports */
339 unsigned char portvec;
340 enum chip_type chip; /* chip code */
341 struct arch_specific_params arch; /* chip specific params */
342 unsigned char offload;
343 unsigned char crypto; /* HW capability for crypto */
345 unsigned char bypass;
347 unsigned int ofldq_wr_cred;
348 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
350 unsigned int nsched_cls; /* number of traffic classes */
351 unsigned int max_ordird_qp; /* Max read depth per RDMA QP */
352 unsigned int max_ird_adapter; /* Max read depth per adapter */
355 /* State needed to monitor the forward progress of SGE Ingress DMA activities
356 * and possible hangs.
358 struct sge_idma_monitor_state {
359 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
360 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
361 unsigned int idma_state[2]; /* IDMA Hang detect state */
362 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
363 unsigned int idma_warn[2]; /* time to warning in HZ */
366 /* Firmware Mailbox Command/Reply log. All values are in Host-Endian format.
367 * The access and execute times are signed in order to accommodate negative
371 u64 cmd[MBOX_LEN / 8]; /* a Firmware Mailbox Command/Reply */
372 u64 timestamp; /* OS-dependent timestamp */
373 u32 seqno; /* sequence number */
374 s16 access; /* time (ms) to access mailbox */
375 s16 execute; /* time (ms) to execute */
378 struct mbox_cmd_log {
379 unsigned int size; /* number of entries in the log */
380 unsigned int cursor; /* next position in the log to write */
381 u32 seqno; /* next sequence number */
382 /* variable length mailbox command log starts here */
385 /* Given a pointer to a Firmware Mailbox Command Log and a log entry index,
386 * return a pointer to the specified entry.
388 static inline struct mbox_cmd *mbox_cmd_log_entry(struct mbox_cmd_log *log,
389 unsigned int entry_idx)
391 return &((struct mbox_cmd *)&(log)[1])[entry_idx];
394 #include "t4fw_api.h"
396 #define FW_VERSION(chip) ( \
397 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
398 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
399 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
400 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
401 #define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
407 struct fw_hdr fw_hdr;
410 struct trace_params {
411 u32 data[TRACE_LEN / 4];
412 u32 mask[TRACE_LEN / 4];
413 unsigned short snap_len;
414 unsigned short min_len;
415 unsigned char skip_ofst;
416 unsigned char skip_len;
417 unsigned char invert;
422 unsigned short supported; /* link capabilities */
423 unsigned short advertising; /* advertised capabilities */
424 unsigned short lp_advertising; /* peer advertised capabilities */
425 unsigned short requested_speed; /* speed user has requested */
426 unsigned short speed; /* actual link speed */
427 unsigned char requested_fc; /* flow control user has requested */
428 unsigned char fc; /* actual link flow control */
429 unsigned char autoneg; /* autonegotiating? */
430 unsigned char link_ok; /* link up? */
431 unsigned char link_down_rc; /* link down reason */
434 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
437 MAX_ETH_QSETS = 32, /* # of Ethernet Tx/Rx queue sets */
438 MAX_OFLD_QSETS = 16, /* # of offload Tx, iscsi Rx queue sets */
439 MAX_CTRL_QUEUES = NCHAN, /* # of control Tx queues */
440 MAX_RDMA_QUEUES = NCHAN, /* # of streaming RDMA Rx queues */
441 MAX_RDMA_CIQS = 32, /* # of RDMA concentrator IQs */
443 /* # of streaming iSCSIT Rx queues */
444 MAX_ISCSIT_QUEUES = MAX_OFLD_QSETS,
448 MAX_TXQ_ENTRIES = 16384,
449 MAX_CTRL_TXQ_ENTRIES = 1024,
450 MAX_RSPQ_ENTRIES = 16384,
451 MAX_RX_BUFFERS = 16384,
452 MIN_TXQ_ENTRIES = 32,
453 MIN_CTRL_TXQ_ENTRIES = 32,
454 MIN_RSPQ_ENTRIES = 128,
459 INGQ_EXTRAS = 2, /* firmware event queue and */
460 /* forwarded interrupts */
461 MAX_INGQ = MAX_ETH_QSETS + MAX_OFLD_QSETS + MAX_RDMA_QUEUES +
462 MAX_RDMA_CIQS + MAX_ISCSIT_QUEUES + INGQ_EXTRAS,
468 #include "cxgb4_dcb.h"
470 #ifdef CONFIG_CHELSIO_T4_FCOE
471 #include "cxgb4_fcoe.h"
472 #endif /* CONFIG_CHELSIO_T4_FCOE */
475 struct adapter *adapter;
477 s16 xact_addr_filt; /* index of exact MAC address filter */
478 u16 rss_size; /* size of VI's RSS table slice */
480 enum fw_port_type port_type;
484 u8 lport; /* associated offload logical port */
485 u8 nqsets; /* # of qsets */
486 u8 first_qset; /* index of first qset */
488 struct link_config link_cfg;
490 struct port_stats stats_base;
491 #ifdef CONFIG_CHELSIO_T4_DCB
492 struct port_dcb_info dcb; /* Data Center Bridging support */
494 #ifdef CONFIG_CHELSIO_T4_FCOE
495 struct cxgb_fcoe fcoe;
496 #endif /* CONFIG_CHELSIO_T4_FCOE */
497 bool rxtstamp; /* Enable TS */
498 struct hwtstamp_config tstamp_config;
499 struct sched_table *sched_tbl;
505 enum { /* adapter flags */
506 FULL_INIT_DONE = (1 << 0),
507 DEV_ENABLED = (1 << 1),
508 USING_MSI = (1 << 2),
509 USING_MSIX = (1 << 3),
511 RSS_TNLALLLOOKUP = (1 << 5),
512 USING_SOFT_PARAMS = (1 << 6),
513 MASTER_PF = (1 << 7),
514 FW_OFLD_CONN = (1 << 9),
518 ULP_CRYPTO_LOOKASIDE = 1 << 0,
523 struct sge_fl { /* SGE free-buffer queue state */
524 unsigned int avail; /* # of available Rx buffers */
525 unsigned int pend_cred; /* new buffers since last FL DB ring */
526 unsigned int cidx; /* consumer index */
527 unsigned int pidx; /* producer index */
528 unsigned long alloc_failed; /* # of times buffer allocation failed */
529 unsigned long large_alloc_failed;
530 unsigned long mapping_err; /* # of RX Buffer DMA Mapping failures */
531 unsigned long low; /* # of times momentarily starving */
532 unsigned long starving;
534 unsigned int cntxt_id; /* SGE context id for the free list */
535 unsigned int size; /* capacity of free list */
536 struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
537 __be64 *desc; /* address of HW Rx descriptor ring */
538 dma_addr_t addr; /* bus address of HW ring start */
539 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
540 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
543 /* A packet gather list */
545 u64 sgetstamp; /* SGE Time Stamp for Ingress Packet */
546 struct page_frag frags[MAX_SKB_FRAGS];
547 void *va; /* virtual address of first byte */
548 unsigned int nfrags; /* # of fragments */
549 unsigned int tot_len; /* total length of fragments */
552 typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
553 const struct pkt_gl *gl);
554 typedef void (*rspq_flush_handler_t)(struct sge_rspq *q);
555 /* LRO related declarations for ULD */
557 #define MAX_LRO_SESSIONS 64
558 u8 lro_session_cnt; /* # of sessions to aggregate */
559 unsigned long lro_pkts; /* # of LRO super packets */
560 unsigned long lro_merged; /* # of wire packets merged by LRO */
561 struct sk_buff_head lroq; /* list of aggregated sessions */
564 struct sge_rspq { /* state for an SGE response queue */
565 struct napi_struct napi;
566 const __be64 *cur_desc; /* current descriptor in queue */
567 unsigned int cidx; /* consumer index */
568 u8 gen; /* current generation bit */
569 u8 intr_params; /* interrupt holdoff parameters */
570 u8 next_intr_params; /* holdoff params for next interrupt */
572 u8 pktcnt_idx; /* interrupt packet threshold */
573 u8 uld; /* ULD handling this queue */
574 u8 idx; /* queue index within its group */
575 int offset; /* offset into current Rx buffer */
576 u16 cntxt_id; /* SGE context id for the response q */
577 u16 abs_id; /* absolute SGE id for the response q */
578 __be64 *desc; /* address of HW response ring */
579 dma_addr_t phys_addr; /* physical address of the ring */
580 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
581 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
582 unsigned int iqe_len; /* entry size */
583 unsigned int size; /* capacity of response queue */
584 struct adapter *adap;
585 struct net_device *netdev; /* associated net device */
586 rspq_handler_t handler;
587 rspq_flush_handler_t flush_handler;
588 struct t4_lro_mgr lro_mgr;
589 #ifdef CONFIG_NET_RX_BUSY_POLL
590 #define CXGB_POLL_STATE_IDLE 0
591 #define CXGB_POLL_STATE_NAPI BIT(0) /* NAPI owns this poll */
592 #define CXGB_POLL_STATE_POLL BIT(1) /* poll owns this poll */
593 #define CXGB_POLL_STATE_NAPI_YIELD BIT(2) /* NAPI yielded this poll */
594 #define CXGB_POLL_STATE_POLL_YIELD BIT(3) /* poll yielded this poll */
595 #define CXGB_POLL_YIELD (CXGB_POLL_STATE_NAPI_YIELD | \
596 CXGB_POLL_STATE_POLL_YIELD)
597 #define CXGB_POLL_LOCKED (CXGB_POLL_STATE_NAPI | \
598 CXGB_POLL_STATE_POLL)
599 #define CXGB_POLL_USER_PEND (CXGB_POLL_STATE_POLL | \
600 CXGB_POLL_STATE_POLL_YIELD)
601 unsigned int bpoll_state;
602 spinlock_t bpoll_lock; /* lock for busy poll */
603 #endif /* CONFIG_NET_RX_BUSY_POLL */
607 struct sge_eth_stats { /* Ethernet queue statistics */
608 unsigned long pkts; /* # of ethernet packets */
609 unsigned long lro_pkts; /* # of LRO super packets */
610 unsigned long lro_merged; /* # of wire packets merged by LRO */
611 unsigned long rx_cso; /* # of Rx checksum offloads */
612 unsigned long vlan_ex; /* # of Rx VLAN extractions */
613 unsigned long rx_drops; /* # of packets dropped due to no mem */
616 struct sge_eth_rxq { /* SW Ethernet Rx queue */
617 struct sge_rspq rspq;
619 struct sge_eth_stats stats;
620 } ____cacheline_aligned_in_smp;
622 struct sge_ofld_stats { /* offload queue statistics */
623 unsigned long pkts; /* # of packets */
624 unsigned long imm; /* # of immediate-data packets */
625 unsigned long an; /* # of asynchronous notifications */
626 unsigned long nomem; /* # of responses deferred due to no mem */
629 struct sge_ofld_rxq { /* SW offload Rx queue */
630 struct sge_rspq rspq;
632 struct sge_ofld_stats stats;
633 } ____cacheline_aligned_in_smp;
642 unsigned int in_use; /* # of in-use Tx descriptors */
643 unsigned int size; /* # of descriptors */
644 unsigned int cidx; /* SW consumer index */
645 unsigned int pidx; /* producer index */
646 unsigned long stops; /* # of times q has been stopped */
647 unsigned long restarts; /* # of queue restarts */
648 unsigned int cntxt_id; /* SGE context id for the Tx q */
649 struct tx_desc *desc; /* address of HW Tx descriptor ring */
650 struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
651 struct sge_qstat *stat; /* queue status entry */
652 dma_addr_t phys_addr; /* physical address of the ring */
655 unsigned short db_pidx;
656 unsigned short db_pidx_inc;
657 void __iomem *bar2_addr; /* address of BAR2 Queue registers */
658 unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
661 struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
663 struct netdev_queue *txq; /* associated netdev TX queue */
664 #ifdef CONFIG_CHELSIO_T4_DCB
665 u8 dcb_prio; /* DCB Priority bound to queue */
667 unsigned long tso; /* # of TSO requests */
668 unsigned long tx_cso; /* # of Tx checksum offloads */
669 unsigned long vlan_ins; /* # of Tx VLAN insertions */
670 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
671 } ____cacheline_aligned_in_smp;
673 struct sge_ofld_txq { /* state for an SGE offload Tx queue */
675 struct adapter *adap;
676 struct sk_buff_head sendq; /* list of backpressured packets */
677 struct tasklet_struct qresume_tsk; /* restarts the queue */
678 bool service_ofldq_running; /* service_ofldq() is processing sendq */
679 u8 full; /* the Tx ring is full */
680 unsigned long mapping_err; /* # of I/O MMU packet mapping errors */
681 } ____cacheline_aligned_in_smp;
683 struct sge_ctrl_txq { /* state for an SGE control Tx queue */
685 struct adapter *adap;
686 struct sk_buff_head sendq; /* list of backpressured packets */
687 struct tasklet_struct qresume_tsk; /* restarts the queue */
688 u8 full; /* the Tx ring is full */
689 } ____cacheline_aligned_in_smp;
691 struct sge_uld_rxq_info {
692 char name[IFNAMSIZ]; /* name of ULD driver */
693 struct sge_ofld_rxq *uldrxq; /* Rxq's for ULD */
694 u16 *msix_tbl; /* msix_tbl for uld */
695 u16 *rspq_id; /* response queue id's of rxq */
696 u16 nrxq; /* # of ingress uld queues */
697 u16 nciq; /* # of completion queues */
698 u8 uld; /* uld type */
702 struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
703 struct sge_ofld_txq ofldtxq[MAX_OFLD_QSETS];
704 struct sge_ctrl_txq ctrlq[MAX_CTRL_QUEUES];
706 struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
707 struct sge_ofld_rxq iscsirxq[MAX_OFLD_QSETS];
708 struct sge_ofld_rxq iscsitrxq[MAX_ISCSIT_QUEUES];
709 struct sge_ofld_rxq rdmarxq[MAX_RDMA_QUEUES];
710 struct sge_ofld_rxq rdmaciq[MAX_RDMA_CIQS];
711 struct sge_rspq fw_evtq ____cacheline_aligned_in_smp;
712 struct sge_uld_rxq_info **uld_rxq_info;
714 struct sge_rspq intrq ____cacheline_aligned_in_smp;
715 spinlock_t intrq_lock;
717 u16 max_ethqsets; /* # of available Ethernet queue sets */
718 u16 ethqsets; /* # of active Ethernet queue sets */
719 u16 ethtxq_rover; /* Tx queue to clean up next */
720 u16 iscsiqsets; /* # of active iSCSI queue sets */
721 u16 niscsitq; /* # of available iSCST Rx queues */
722 u16 rdmaqs; /* # of available RDMA Rx queues */
723 u16 rdmaciqs; /* # of available RDMA concentrator IQs */
724 u16 nqs_per_uld; /* # of Rx queues per ULD */
725 u16 iscsi_rxq[MAX_OFLD_QSETS];
726 u16 iscsit_rxq[MAX_ISCSIT_QUEUES];
727 u16 rdma_rxq[MAX_RDMA_QUEUES];
728 u16 rdma_ciq[MAX_RDMA_CIQS];
729 u16 timer_val[SGE_NTIMERS];
730 u8 counter_val[SGE_NCOUNTERS];
731 u32 fl_pg_order; /* large page allocation size */
732 u32 stat_len; /* length of status page at ring end */
733 u32 pktshift; /* padding between CPL & packet data */
734 u32 fl_align; /* response queue message alignment */
735 u32 fl_starve_thres; /* Free List starvation threshold */
737 struct sge_idma_monitor_state idma_monitor;
738 unsigned int egr_start;
740 unsigned int ingr_start;
741 unsigned int ingr_sz;
742 void **egr_map; /* qid->queue egress queue map */
743 struct sge_rspq **ingr_map; /* qid->queue ingress queue map */
744 unsigned long *starving_fl;
745 unsigned long *txq_maperr;
746 unsigned long *blocked_fl;
747 struct timer_list rx_timer; /* refills starving FLs */
748 struct timer_list tx_timer; /* checks Tx queues */
751 #define for_each_ethrxq(sge, i) for (i = 0; i < (sge)->ethqsets; i++)
752 #define for_each_iscsirxq(sge, i) for (i = 0; i < (sge)->iscsiqsets; i++)
753 #define for_each_iscsitrxq(sge, i) for (i = 0; i < (sge)->niscsitq; i++)
754 #define for_each_rdmarxq(sge, i) for (i = 0; i < (sge)->rdmaqs; i++)
755 #define for_each_rdmaciq(sge, i) for (i = 0; i < (sge)->rdmaciqs; i++)
759 #ifdef CONFIG_PCI_IOV
761 /* T4 supports SRIOV on PF0-3 and T5 on PF0-7. However, the Serial
762 * Configuration initialization for T5 only has SR-IOV functionality enabled
763 * on PF0-3 in order to simplify everything.
765 #define NUM_OF_PF_WITH_SRIOV 4
769 struct doorbell_stats {
775 struct hash_mac_addr {
776 struct list_head list;
780 struct uld_msix_bmap {
781 unsigned long *msix_bmap;
782 unsigned int mapsize;
783 spinlock_t lock; /* lock for acquiring bitmap */
786 struct uld_msix_info {
788 char desc[IFNAMSIZ + 10];
795 struct pci_dev *pdev;
796 struct device *pdev_dev;
805 struct adapter_params params;
806 struct cxgb4_virt_res vres;
811 char desc[IFNAMSIZ + 10];
812 } msix_info[MAX_INGQ + 1];
813 struct uld_msix_info *msix_info_ulds; /* msix info for uld's */
814 struct uld_msix_bmap msix_bmap_ulds; /* msix bitmap for all uld */
815 unsigned int msi_idx;
817 struct doorbell_stats db_stats;
820 struct net_device *port[MAX_NPORTS];
821 u8 chan_map[NCHAN]; /* channel -> port map */
824 unsigned int l2t_start;
825 unsigned int l2t_end;
826 struct l2t_data *l2t;
827 unsigned int clipt_start;
828 unsigned int clipt_end;
829 struct clip_tbl *clipt;
830 struct cxgb4_pci_uld_info *uld;
831 void *uld_handle[CXGB4_ULD_MAX];
832 unsigned int num_uld;
833 struct list_head list_node;
834 struct list_head rcu_node;
835 struct list_head mac_hlist; /* list of MAC addresses in MPS Hash */
839 struct tid_info tids;
840 void **tid_release_head;
841 spinlock_t tid_release_lock;
842 struct workqueue_struct *workq;
843 struct work_struct tid_release_task;
844 struct work_struct db_full_task;
845 struct work_struct db_drop_task;
846 bool tid_release_task_busy;
848 /* support for mailbox command/reply logging */
849 #define T4_OS_LOG_MBOX_CMDS 256
850 struct mbox_cmd_log *mbox_log;
852 struct dentry *debugfs_root;
853 bool use_bd; /* Use SGE Back Door intfc for reading SGE Contexts */
854 bool trace_rss; /* 1 implies that different RSS flit per filter is
855 * used per filter else if 0 default RSS flit is
856 * used for all 4 filters.
859 spinlock_t stats_lock;
860 spinlock_t win0_lock ____cacheline_aligned_in_smp;
863 /* Support for "sched-class" command to allow a TX Scheduling Class to be
864 * programmed with various parameters.
866 struct ch_sched_params {
867 s8 type; /* packet or flow */
870 s8 level; /* scheduler hierarchy level */
871 s8 mode; /* per-class or per-flow */
872 s8 rateunit; /* bit or packet rate */
873 s8 ratemode; /* %port relative or kbps absolute */
874 s8 channel; /* scheduler channel [0..N] */
875 s8 class; /* scheduler class [0..N] */
876 s32 minrate; /* minimum rate */
877 s32 maxrate; /* maximum rate */
878 s16 weight; /* percent weight */
879 s16 pktsize; /* average packet size */
884 /* Defined bit width of user definable filter tuples
886 #define ETHTYPE_BITWIDTH 16
887 #define FRAG_BITWIDTH 1
888 #define MACIDX_BITWIDTH 9
889 #define FCOE_BITWIDTH 1
890 #define IPORT_BITWIDTH 3
891 #define MATCHTYPE_BITWIDTH 3
892 #define PROTO_BITWIDTH 8
893 #define TOS_BITWIDTH 8
894 #define PF_BITWIDTH 8
895 #define VF_BITWIDTH 8
896 #define IVLAN_BITWIDTH 16
897 #define OVLAN_BITWIDTH 16
899 /* Filter matching rules. These consist of a set of ingress packet field
900 * (value, mask) tuples. The associated ingress packet field matches the
901 * tuple when ((field & mask) == value). (Thus a wildcard "don't care" field
902 * rule can be constructed by specifying a tuple of (0, 0).) A filter rule
903 * matches an ingress packet when all of the individual individual field
904 * matching rules are true.
906 * Partial field masks are always valid, however, while it may be easy to
907 * understand their meanings for some fields (e.g. IP address to match a
908 * subnet), for others making sensible partial masks is less intuitive (e.g.
909 * MPS match type) ...
911 * Most of the following data structures are modeled on T4 capabilities.
912 * Drivers for earlier chips use the subsets which make sense for those chips.
913 * We really need to come up with a hardware-independent mechanism to
914 * represent hardware filter capabilities ...
916 struct ch_filter_tuple {
917 /* Compressed header matching field rules. The TP_VLAN_PRI_MAP
918 * register selects which of these fields will participate in the
919 * filter match rules -- up to a maximum of 36 bits. Because
920 * TP_VLAN_PRI_MAP is a global register, all filters must use the same
923 uint32_t ethtype:ETHTYPE_BITWIDTH; /* Ethernet type */
924 uint32_t frag:FRAG_BITWIDTH; /* IP fragmentation header */
925 uint32_t ivlan_vld:1; /* inner VLAN valid */
926 uint32_t ovlan_vld:1; /* outer VLAN valid */
927 uint32_t pfvf_vld:1; /* PF/VF valid */
928 uint32_t macidx:MACIDX_BITWIDTH; /* exact match MAC index */
929 uint32_t fcoe:FCOE_BITWIDTH; /* FCoE packet */
930 uint32_t iport:IPORT_BITWIDTH; /* ingress port */
931 uint32_t matchtype:MATCHTYPE_BITWIDTH; /* MPS match type */
932 uint32_t proto:PROTO_BITWIDTH; /* protocol type */
933 uint32_t tos:TOS_BITWIDTH; /* TOS/Traffic Type */
934 uint32_t pf:PF_BITWIDTH; /* PCI-E PF ID */
935 uint32_t vf:VF_BITWIDTH; /* PCI-E VF ID */
936 uint32_t ivlan:IVLAN_BITWIDTH; /* inner VLAN */
937 uint32_t ovlan:OVLAN_BITWIDTH; /* outer VLAN */
939 /* Uncompressed header matching field rules. These are always
940 * available for field rules.
942 uint8_t lip[16]; /* local IP address (IPv4 in [3:0]) */
943 uint8_t fip[16]; /* foreign IP address (IPv4 in [3:0]) */
944 uint16_t lport; /* local port */
945 uint16_t fport; /* foreign port */
948 /* A filter ioctl command.
950 struct ch_filter_specification {
951 /* Administrative fields for filter.
953 uint32_t hitcnts:1; /* count filter hits in TCB */
954 uint32_t prio:1; /* filter has priority over active/server */
956 /* Fundamental filter typing. This is the one element of filter
957 * matching that doesn't exist as a (value, mask) tuple.
959 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */
961 /* Packet dispatch information. Ingress packets which match the
962 * filter rules will be dropped, passed to the host or switched back
963 * out as egress packets.
965 uint32_t action:2; /* drop, pass, switch */
967 uint32_t rpttid:1; /* report TID in RSS hash field */
969 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */
970 uint32_t iq:10; /* ingress queue */
972 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */
973 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */
974 /* 1 => TCB contains IQ ID */
976 /* Switch proxy/rewrite fields. An ingress packet which matches a
977 * filter with "switch" set will be looped back out as an egress
978 * packet -- potentially with some Ethernet header rewriting.
980 uint32_t eport:2; /* egress port to switch packet out */
981 uint32_t newdmac:1; /* rewrite destination MAC address */
982 uint32_t newsmac:1; /* rewrite source MAC address */
983 uint32_t newvlan:2; /* rewrite VLAN Tag */
984 uint8_t dmac[ETH_ALEN]; /* new destination MAC address */
985 uint8_t smac[ETH_ALEN]; /* new source MAC address */
986 uint16_t vlan; /* VLAN Tag to insert */
988 /* Filter rule value/mask pairs.
990 struct ch_filter_tuple val;
991 struct ch_filter_tuple mask;
995 FILTER_PASS = 0, /* default */
1001 VLAN_NOCHANGE = 0, /* default */
1007 static inline int is_offload(const struct adapter *adap)
1009 return adap->params.offload;
1012 static inline int is_pci_uld(const struct adapter *adap)
1014 return adap->params.crypto;
1017 static inline u32 t4_read_reg(struct adapter *adap, u32 reg_addr)
1019 return readl(adap->regs + reg_addr);
1022 static inline void t4_write_reg(struct adapter *adap, u32 reg_addr, u32 val)
1024 writel(val, adap->regs + reg_addr);
1028 static inline u64 readq(const volatile void __iomem *addr)
1030 return readl(addr) + ((u64)readl(addr + 4) << 32);
1033 static inline void writeq(u64 val, volatile void __iomem *addr)
1036 writel(val >> 32, addr + 4);
1040 static inline u64 t4_read_reg64(struct adapter *adap, u32 reg_addr)
1042 return readq(adap->regs + reg_addr);
1045 static inline void t4_write_reg64(struct adapter *adap, u32 reg_addr, u64 val)
1047 writeq(val, adap->regs + reg_addr);
1051 * t4_set_hw_addr - store a port's MAC address in SW
1052 * @adapter: the adapter
1053 * @port_idx: the port index
1054 * @hw_addr: the Ethernet address
1056 * Store the Ethernet address of the given port in SW. Called by the common
1057 * code when it retrieves a port's Ethernet address from EEPROM.
1059 static inline void t4_set_hw_addr(struct adapter *adapter, int port_idx,
1062 ether_addr_copy(adapter->port[port_idx]->dev_addr, hw_addr);
1063 ether_addr_copy(adapter->port[port_idx]->perm_addr, hw_addr);
1067 * netdev2pinfo - return the port_info structure associated with a net_device
1070 * Return the struct port_info associated with a net_device
1072 static inline struct port_info *netdev2pinfo(const struct net_device *dev)
1074 return netdev_priv(dev);
1078 * adap2pinfo - return the port_info of a port
1079 * @adap: the adapter
1080 * @idx: the port index
1082 * Return the port_info structure for the port of the given index.
1084 static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
1086 return netdev_priv(adap->port[idx]);
1090 * netdev2adap - return the adapter structure associated with a net_device
1093 * Return the struct adapter associated with a net_device
1095 static inline struct adapter *netdev2adap(const struct net_device *dev)
1097 return netdev2pinfo(dev)->adapter;
1100 #ifdef CONFIG_NET_RX_BUSY_POLL
1101 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1103 spin_lock_init(&q->bpoll_lock);
1104 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1107 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1111 spin_lock(&q->bpoll_lock);
1112 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1113 q->bpoll_state |= CXGB_POLL_STATE_NAPI_YIELD;
1116 q->bpoll_state = CXGB_POLL_STATE_NAPI;
1118 spin_unlock(&q->bpoll_lock);
1122 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1126 spin_lock(&q->bpoll_lock);
1127 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1129 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1130 spin_unlock(&q->bpoll_lock);
1134 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1138 spin_lock_bh(&q->bpoll_lock);
1139 if (q->bpoll_state & CXGB_POLL_LOCKED) {
1140 q->bpoll_state |= CXGB_POLL_STATE_POLL_YIELD;
1143 q->bpoll_state |= CXGB_POLL_STATE_POLL;
1145 spin_unlock_bh(&q->bpoll_lock);
1149 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1153 spin_lock_bh(&q->bpoll_lock);
1154 if (q->bpoll_state & CXGB_POLL_STATE_POLL_YIELD)
1156 q->bpoll_state = CXGB_POLL_STATE_IDLE;
1157 spin_unlock_bh(&q->bpoll_lock);
1161 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1163 return q->bpoll_state & CXGB_POLL_USER_PEND;
1166 static inline void cxgb_busy_poll_init_lock(struct sge_rspq *q)
1170 static inline bool cxgb_poll_lock_napi(struct sge_rspq *q)
1175 static inline bool cxgb_poll_unlock_napi(struct sge_rspq *q)
1180 static inline bool cxgb_poll_lock_poll(struct sge_rspq *q)
1185 static inline bool cxgb_poll_unlock_poll(struct sge_rspq *q)
1190 static inline bool cxgb_poll_busy_polling(struct sge_rspq *q)
1194 #endif /* CONFIG_NET_RX_BUSY_POLL */
1196 /* Return a version number to identify the type of adapter. The scheme is:
1197 * - bits 0..9: chip version
1198 * - bits 10..15: chip revision
1199 * - bits 16..23: register dump version
1201 static inline unsigned int mk_adap_vers(struct adapter *ap)
1203 return CHELSIO_CHIP_VERSION(ap->params.chip) |
1204 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1207 /* Return a queue's interrupt hold-off time in us. 0 means no timer. */
1208 static inline unsigned int qtimer_val(const struct adapter *adap,
1209 const struct sge_rspq *q)
1211 unsigned int idx = q->intr_params >> 1;
1213 return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
1216 /* driver version & name used for ethtool_drvinfo */
1217 extern char cxgb4_driver_name[];
1218 extern const char cxgb4_driver_version[];
1220 void t4_os_portmod_changed(const struct adapter *adap, int port_id);
1221 void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
1223 void *t4_alloc_mem(size_t size);
1225 void t4_free_sge_resources(struct adapter *adap);
1226 void t4_free_ofld_rxqs(struct adapter *adap, int n, struct sge_ofld_rxq *q);
1227 irq_handler_t t4_intr_handler(struct adapter *adap);
1228 netdev_tx_t t4_eth_xmit(struct sk_buff *skb, struct net_device *dev);
1229 int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
1230 const struct pkt_gl *gl);
1231 int t4_mgmt_tx(struct adapter *adap, struct sk_buff *skb);
1232 int t4_ofld_send(struct adapter *adap, struct sk_buff *skb);
1233 int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
1234 struct net_device *dev, int intr_idx,
1235 struct sge_fl *fl, rspq_handler_t hnd,
1236 rspq_flush_handler_t flush_handler, int cong);
1237 int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
1238 struct net_device *dev, struct netdev_queue *netdevq,
1240 int t4_sge_alloc_ctrl_txq(struct adapter *adap, struct sge_ctrl_txq *txq,
1241 struct net_device *dev, unsigned int iqid,
1242 unsigned int cmplqid);
1243 int t4_sge_alloc_ofld_txq(struct adapter *adap, struct sge_ofld_txq *txq,
1244 struct net_device *dev, unsigned int iqid);
1245 irqreturn_t t4_sge_intr_msix(int irq, void *cookie);
1246 int t4_sge_init(struct adapter *adap);
1247 void t4_sge_start(struct adapter *adap);
1248 void t4_sge_stop(struct adapter *adap);
1249 int cxgb_busy_poll(struct napi_struct *napi);
1250 void cxgb4_set_ethtool_ops(struct net_device *netdev);
1251 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
1252 extern int dbfifo_int_thresh;
1254 #define for_each_port(adapter, iter) \
1255 for (iter = 0; iter < (adapter)->params.nports; ++iter)
1257 static inline int is_bypass(struct adapter *adap)
1259 return adap->params.bypass;
1262 static inline int is_bypass_device(int device)
1264 /* this should be set based upon device capabilities */
1274 static inline int is_10gbt_device(int device)
1276 /* this should be set based upon device capabilities */
1287 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
1289 return adap->params.vpd.cclk / 1000;
1292 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
1295 return (us * adap->params.vpd.cclk) / 1000;
1298 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
1301 /* add Core Clock / 2 to round ticks to nearest uS */
1302 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
1303 adapter->params.vpd.cclk);
1306 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
1309 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
1310 int size, void *rpl, bool sleep_ok, int timeout);
1311 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
1312 void *rpl, bool sleep_ok);
1314 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
1315 const void *cmd, int size, void *rpl,
1318 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
1322 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
1323 int size, void *rpl)
1325 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
1328 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
1329 int size, void *rpl)
1331 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
1335 * hash_mac_addr - return the hash value of a MAC address
1336 * @addr: the 48-bit Ethernet MAC address
1338 * Hashes a MAC address according to the hash function used by HW inexact
1339 * (hash) address matching.
1341 static inline int hash_mac_addr(const u8 *addr)
1343 u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
1344 u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
1352 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
1354 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
1355 unsigned int us, unsigned int cnt,
1356 unsigned int size, unsigned int iqe_size)
1359 cxgb4_set_rspq_intr_params(q, us, cnt);
1360 q->iqe_len = iqe_size;
1364 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
1365 unsigned int data_reg, const u32 *vals,
1366 unsigned int nregs, unsigned int start_idx);
1367 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
1368 unsigned int data_reg, u32 *vals, unsigned int nregs,
1369 unsigned int start_idx);
1370 void t4_hw_pci_read_cfg4(struct adapter *adapter, int reg, u32 *val);
1372 struct fw_filter_wr;
1374 void t4_intr_enable(struct adapter *adapter);
1375 void t4_intr_disable(struct adapter *adapter);
1376 int t4_slow_intr_handler(struct adapter *adapter);
1378 int t4_wait_dev_ready(void __iomem *regs);
1379 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
1380 struct link_config *lc);
1381 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
1383 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg);
1384 u32 t4_get_util_window(struct adapter *adap);
1385 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window);
1387 #define T4_MEMORY_WRITE 0
1388 #define T4_MEMORY_READ 1
1389 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, u32 len,
1390 void *buf, int dir);
1391 static inline int t4_memory_write(struct adapter *adap, int mtype, u32 addr,
1392 u32 len, __be32 *buf)
1394 return t4_memory_rw(adap, 0, mtype, addr, len, buf, 0);
1397 unsigned int t4_get_regs_len(struct adapter *adapter);
1398 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size);
1400 int t4_seeprom_wp(struct adapter *adapter, bool enable);
1401 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p);
1402 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
1403 int t4_read_flash(struct adapter *adapter, unsigned int addr,
1404 unsigned int nwords, u32 *data, int byte_oriented);
1405 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
1406 int t4_load_phy_fw(struct adapter *adap,
1407 int win, spinlock_t *lock,
1408 int (*phy_fw_version)(const u8 *, size_t),
1409 const u8 *phy_fw_data, size_t phy_fw_size);
1410 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver);
1411 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1412 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
1413 const u8 *fw_data, unsigned int size, int force);
1414 int t4_fl_pkt_align(struct adapter *adap);
1415 unsigned int t4_flash_cfg_addr(struct adapter *adapter);
1416 int t4_check_fw_version(struct adapter *adap);
1417 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
1418 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
1419 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
1420 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
1421 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
1422 const u8 *fw_data, unsigned int fw_size,
1423 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1424 int t4_prep_adapter(struct adapter *adapter);
1426 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1427 int t4_bar2_sge_qregs(struct adapter *adapter,
1429 enum t4_bar2_qtype qtype,
1432 unsigned int *pbar2_qid);
1434 unsigned int qtimer_val(const struct adapter *adap,
1435 const struct sge_rspq *q);
1437 int t4_init_devlog_params(struct adapter *adapter);
1438 int t4_init_sge_params(struct adapter *adapter);
1439 int t4_init_tp_params(struct adapter *adap);
1440 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
1441 int t4_init_rss_mode(struct adapter *adap, int mbox);
1442 int t4_init_portinfo(struct port_info *pi, int mbox,
1443 int port, int pf, int vf, u8 mac[]);
1444 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
1445 void t4_fatal_err(struct adapter *adapter);
1446 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
1447 int start, int n, const u16 *rspq, unsigned int nrspq);
1448 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
1449 unsigned int flags);
1450 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
1451 unsigned int flags, unsigned int defq);
1452 int t4_read_rss(struct adapter *adapter, u16 *entries);
1453 void t4_read_rss_key(struct adapter *adapter, u32 *key);
1454 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx);
1455 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
1457 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
1458 u32 *vfl, u32 *vfh);
1459 u32 t4_read_rss_pf_map(struct adapter *adapter);
1460 u32 t4_read_rss_pf_mask(struct adapter *adapter);
1462 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
1463 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1464 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
1465 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data,
1467 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data,
1469 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
1470 unsigned int *valp);
1471 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
1472 const unsigned int *valp);
1473 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
1474 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
1475 unsigned int *pif_req_wrptr,
1476 unsigned int *pif_rsp_wrptr);
1477 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
1478 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
1479 const char *t4_get_port_type_description(enum fw_port_type port_type);
1480 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
1481 void t4_get_port_stats_offset(struct adapter *adap, int idx,
1482 struct port_stats *stats,
1483 struct port_stats *offset);
1484 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
1485 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
1486 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
1487 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
1488 unsigned int mask, unsigned int val);
1489 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
1490 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st);
1491 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st);
1492 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st);
1493 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st);
1494 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
1495 struct tp_tcp_stats *v6);
1496 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
1497 struct tp_fcoe_stats *st);
1498 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
1499 const unsigned short *alpha, const unsigned short *beta);
1501 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
1503 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
1504 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
1506 void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
1508 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
1509 u64 mask0, u64 mask1, unsigned int crc, bool enable);
1511 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
1512 enum dev_master master, enum dev_state *state);
1513 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
1514 int t4_early_init(struct adapter *adap, unsigned int mbox);
1515 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
1516 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
1517 unsigned int cache_line_size);
1518 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
1519 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1520 unsigned int vf, unsigned int nparams, const u32 *params,
1522 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
1523 unsigned int vf, unsigned int nparams, const u32 *params,
1525 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
1526 unsigned int pf, unsigned int vf,
1527 unsigned int nparams, const u32 *params,
1528 const u32 *val, int timeout);
1529 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
1530 unsigned int vf, unsigned int nparams, const u32 *params,
1532 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
1533 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
1534 unsigned int rxqi, unsigned int rxq, unsigned int tc,
1535 unsigned int vi, unsigned int cmask, unsigned int pmask,
1536 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps);
1537 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
1538 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
1539 unsigned int *rss_size);
1540 int t4_free_vi(struct adapter *adap, unsigned int mbox,
1541 unsigned int pf, unsigned int vf,
1543 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
1544 int mtu, int promisc, int all_multi, int bcast, int vlanex,
1546 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
1547 unsigned int viid, bool free, unsigned int naddr,
1548 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok);
1549 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
1550 unsigned int viid, unsigned int naddr,
1551 const u8 **addr, bool sleep_ok);
1552 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
1553 int idx, const u8 *addr, bool persist, bool add_smt);
1554 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
1555 bool ucast, u64 vec, bool sleep_ok);
1556 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
1557 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
1558 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
1559 bool rx_en, bool tx_en);
1560 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
1561 unsigned int nblinks);
1562 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1563 unsigned int mmd, unsigned int reg, u16 *valp);
1564 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
1565 unsigned int mmd, unsigned int reg, u16 val);
1566 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
1567 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1568 unsigned int fl0id, unsigned int fl1id);
1569 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1570 unsigned int vf, unsigned int iqtype, unsigned int iqid,
1571 unsigned int fl0id, unsigned int fl1id);
1572 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1573 unsigned int vf, unsigned int eqid);
1574 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1575 unsigned int vf, unsigned int eqid);
1576 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
1577 unsigned int vf, unsigned int eqid);
1578 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
1579 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl);
1580 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
1581 void t4_db_full(struct adapter *adapter);
1582 void t4_db_dropped(struct adapter *adapter);
1583 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
1584 int filter_index, int enable);
1585 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
1586 int filter_index, int *enabled);
1587 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
1589 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
1590 int rateunit, int ratemode, int channel, int class,
1591 int minrate, int maxrate, int weight, int pktsize);
1592 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
1593 void t4_free_mem(void *addr);
1594 void t4_idma_monitor_init(struct adapter *adapter,
1595 struct sge_idma_monitor_state *idma);
1596 void t4_idma_monitor(struct adapter *adapter,
1597 struct sge_idma_monitor_state *idma,
1599 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
1600 unsigned int naddr, u8 *addr);
1601 void uld_mem_free(struct adapter *adap);
1602 int uld_mem_alloc(struct adapter *adap);
1603 void free_rspq_fl(struct adapter *adap, struct sge_rspq *rq, struct sge_fl *fl);
1604 #endif /* __CXGB4_H__ */