drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  36
  37 #include <linux/bitmap.h>
  38 #include <linux/crc32.h>
  39 #include <linux/ctype.h>
  40 #include <linux/debugfs.h>
  41 #include <linux/err.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/firmware.h>
  44 #include <linux/if.h>
  45 #include <linux/if_vlan.h>
  46 #include <linux/init.h>
  47 #include <linux/log2.h>
  48 #include <linux/mdio.h>
  49 #include <linux/module.h>
  50 #include <linux/moduleparam.h>
  51 #include <linux/mutex.h>
  52 #include <linux/netdevice.h>
  53 #include <linux/pci.h>
  54 #include <linux/aer.h>
  55 #include <linux/rtnetlink.h>
  56 #include <linux/sched.h>
  57 #include <linux/seq_file.h>
  58 #include <linux/sockios.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/workqueue.h>
  61 #include <net/neighbour.h>
  62 #include <net/netevent.h>
  63 #include <net/addrconf.h>
  64 #include <asm/uaccess.h>
  65
  66 #include "cxgb4.h"
  67 #include "t4_regs.h"
  68 #include "t4_msg.h"
  69 #include "t4fw_api.h"
  70 #include "cxgb4_dcb.h"
  71 #include "l2t.h"
  72
  73 #include <../drivers/net/bonding/bonding.h>
  74
  75 #ifdef DRV_VERSION
  76 #undef DRV_VERSION
  77 #endif
  78 #define DRV_VERSION "2.0.0-ko"
  79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
  80
  81 /*
  82  * Max interrupt hold-off timer value in us.  Queues fall back to this value
  83  * under extreme memory pressure so it's largish to give the system time to
  84  * recover.
  85  */
  86 #define MAX_SGE_TIMERVAL 200U
  87
  88 enum {
  89         /*
  90          * Physical Function provisioning constants.
  91          */
  92         PFRES_NVI = 4,                  /* # of Virtual Interfaces */
  93         PFRES_NETHCTRL = 128,           /* # of EQs used for ETH or CTRL Qs */
  94         PFRES_NIQFLINT = 128,           /* # of ingress Qs/w Free List(s)/intr
  95                                          */
  96         PFRES_NEQ = 256,                /* # of egress queues */
  97         PFRES_NIQ = 0,                  /* # of ingress queues */
  98         PFRES_TC = 0,                   /* PCI-E traffic class */
  99         PFRES_NEXACTF = 128,            /* # of exact MPS filters */
 100
 101         PFRES_R_CAPS = FW_CMD_CAP_PF,
 102         PFRES_WX_CAPS = FW_CMD_CAP_PF,
 103
 104 #ifdef CONFIG_PCI_IOV
 105         /*
 106          * Virtual Function provisioning constants.  We need two extra Ingress
 107          * Queues with Interrupt capability to serve as the VF's Firmware
 108          * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
 109          * neither will have Free Lists associated with them).  For each
 110          * Ethernet/Control Egress Queue and for each Free List, we need an
 111          * Egress Context.
 112          */
 113         VFRES_NPORTS = 1,               /* # of "ports" per VF */
 114         VFRES_NQSETS = 2,               /* # of "Queue Sets" per VF */
 115
 116         VFRES_NVI = VFRES_NPORTS,       /* # of Virtual Interfaces */
 117         VFRES_NETHCTRL = VFRES_NQSETS,  /* # of EQs used for ETH or CTRL Qs */
 118         VFRES_NIQFLINT = VFRES_NQSETS+2,/* # of ingress Qs/w Free List(s)/intr */
 119         VFRES_NEQ = VFRES_NQSETS*2,     /* # of egress queues */
 120         VFRES_NIQ = 0,                  /* # of non-fl/int ingress queues */
 121         VFRES_TC = 0,                   /* PCI-E traffic class */
 122         VFRES_NEXACTF = 16,             /* # of exact MPS filters */
 123
 124         VFRES_R_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF|FW_CMD_CAP_PORT,
 125         VFRES_WX_CAPS = FW_CMD_CAP_DMAQ|FW_CMD_CAP_VF,
 126 #endif
 127 };
 128
 129 /*
 130  * Provide a Port Access Rights Mask for the specified PF/VF.  This is very
 131  * static and likely not to be useful in the long run.  We really need to
 132  * implement some form of persistent configuration which the firmware
 133  * controls.
 134  */
 135 static unsigned int pfvfres_pmask(struct adapter *adapter,
 136                                   unsigned int pf, unsigned int vf)
 137 {
 138         unsigned int portn, portvec;
 139
 140         /*
 141          * Give PF's access to all of the ports.
 142          */
 143         if (vf == 0)
 144                 return FW_PFVF_CMD_PMASK_MASK;
 145
 146         /*
 147          * For VFs, we'll assign them access to the ports based purely on the
 148          * PF.  We assign active ports in order, wrapping around if there are
 149          * fewer active ports than PFs: e.g. active port[pf % nports].
 150          * Unfortunately the adapter's port_info structs haven't been
 151          * initialized yet so we have to compute this.
 152          */
 153         if (adapter->params.nports == 0)
 154                 return 0;
 155
 156         portn = pf % adapter->params.nports;
 157         portvec = adapter->params.portvec;
 158         for (;;) {
 159                 /*
 160                  * Isolate the lowest set bit in the port vector.  If we're at
 161                  * the port number that we want, return that as the pmask.
 162                  * otherwise mask that bit out of the port vector and
 163                  * decrement our port number ...
 164                  */
 165                 unsigned int pmask = portvec ^ (portvec & (portvec-1));
 166                 if (portn == 0)
 167                         return pmask;
 168                 portn--;
 169                 portvec &= ~pmask;
 170         }
 171         /*NOTREACHED*/
 172 }
 173
 174 enum {
 175         MAX_TXQ_ENTRIES      = 16384,
 176         MAX_CTRL_TXQ_ENTRIES = 1024,
 177         MAX_RSPQ_ENTRIES     = 16384,
 178         MAX_RX_BUFFERS       = 16384,
 179         MIN_TXQ_ENTRIES      = 32,
 180         MIN_CTRL_TXQ_ENTRIES = 32,
 181         MIN_RSPQ_ENTRIES     = 128,
 182         MIN_FL_ENTRIES       = 16
 183 };
 184
 185 /* Host shadow copy of ingress filter entry.  This is in host native format
 186  * and doesn't match the ordering or bit order, etc. of the hardware of the
 187  * firmware command.  The use of bit-field structure elements is purely to
 188  * remind ourselves of the field size limitations and save memory in the case
 189  * where the filter table is large.
 190  */
 191 struct filter_entry {
 192         /* Administrative fields for filter.
 193          */
 194         u32 valid:1;            /* filter allocated and valid */
 195         u32 locked:1;           /* filter is administratively locked */
 196
 197         u32 pending:1;          /* filter action is pending firmware reply */
 198         u32 smtidx:8;           /* Source MAC Table index for smac */
 199         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 200
 201         /* The filter itself.  Most of this is a straight copy of information
 202          * provided by the extended ioctl().  Some fields are translated to
 203          * internal forms -- for instance the Ingress Queue ID passed in from
 204          * the ioctl() is translated into the Absolute Ingress Queue ID.
 205          */
 206         struct ch_filter_specification fs;
 207 };
 208
 209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
 210                          NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
 211                          NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
 212
 213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
 214
 215 static DEFINE_PCI_DEVICE_TABLE(cxgb4_pci_tbl) = {
 216         CH_DEVICE(0xa000, 0),  /* PE10K */
 217         CH_DEVICE(0x4001, -1),
 218         CH_DEVICE(0x4002, -1),
 219         CH_DEVICE(0x4003, -1),
 220         CH_DEVICE(0x4004, -1),
 221         CH_DEVICE(0x4005, -1),
 222         CH_DEVICE(0x4006, -1),
 223         CH_DEVICE(0x4007, -1),
 224         CH_DEVICE(0x4008, -1),
 225         CH_DEVICE(0x4009, -1),
 226         CH_DEVICE(0x400a, -1),
 227         CH_DEVICE(0x4401, 4),
 228         CH_DEVICE(0x4402, 4),
 229         CH_DEVICE(0x4403, 4),
 230         CH_DEVICE(0x4404, 4),
 231         CH_DEVICE(0x4405, 4),
 232         CH_DEVICE(0x4406, 4),
 233         CH_DEVICE(0x4407, 4),
 234         CH_DEVICE(0x4408, 4),
 235         CH_DEVICE(0x4409, 4),
 236         CH_DEVICE(0x440a, 4),
 237         CH_DEVICE(0x440d, 4),
 238         CH_DEVICE(0x440e, 4),
 239         CH_DEVICE(0x5001, 4),
 240         CH_DEVICE(0x5002, 4),
 241         CH_DEVICE(0x5003, 4),
 242         CH_DEVICE(0x5004, 4),
 243         CH_DEVICE(0x5005, 4),
 244         CH_DEVICE(0x5006, 4),
 245         CH_DEVICE(0x5007, 4),
 246         CH_DEVICE(0x5008, 4),
 247         CH_DEVICE(0x5009, 4),
 248         CH_DEVICE(0x500A, 4),
 249         CH_DEVICE(0x500B, 4),
 250         CH_DEVICE(0x500C, 4),
 251         CH_DEVICE(0x500D, 4),
 252         CH_DEVICE(0x500E, 4),
 253         CH_DEVICE(0x500F, 4),
 254         CH_DEVICE(0x5010, 4),
 255         CH_DEVICE(0x5011, 4),
 256         CH_DEVICE(0x5012, 4),
 257         CH_DEVICE(0x5013, 4),
 258         CH_DEVICE(0x5014, 4),
 259         CH_DEVICE(0x5015, 4),
 260         CH_DEVICE(0x5080, 4),
 261         CH_DEVICE(0x5081, 4),
 262         CH_DEVICE(0x5082, 4),
 263         CH_DEVICE(0x5083, 4),
 264         CH_DEVICE(0x5084, 4),
 265         CH_DEVICE(0x5085, 4),
 266         CH_DEVICE(0x5401, 4),
 267         CH_DEVICE(0x5402, 4),
 268         CH_DEVICE(0x5403, 4),
 269         CH_DEVICE(0x5404, 4),
 270         CH_DEVICE(0x5405, 4),
 271         CH_DEVICE(0x5406, 4),
 272         CH_DEVICE(0x5407, 4),
 273         CH_DEVICE(0x5408, 4),
 274         CH_DEVICE(0x5409, 4),
 275         CH_DEVICE(0x540A, 4),
 276         CH_DEVICE(0x540B, 4),
 277         CH_DEVICE(0x540C, 4),
 278         CH_DEVICE(0x540D, 4),
 279         CH_DEVICE(0x540E, 4),
 280         CH_DEVICE(0x540F, 4),
 281         CH_DEVICE(0x5410, 4),
 282         CH_DEVICE(0x5411, 4),
 283         CH_DEVICE(0x5412, 4),
 284         CH_DEVICE(0x5413, 4),
 285         CH_DEVICE(0x5414, 4),
 286         CH_DEVICE(0x5415, 4),
 287         CH_DEVICE(0x5480, 4),
 288         CH_DEVICE(0x5481, 4),
 289         CH_DEVICE(0x5482, 4),
 290         CH_DEVICE(0x5483, 4),
 291         CH_DEVICE(0x5484, 4),
 292         CH_DEVICE(0x5485, 4),
 293         { 0, }
 294 };
 295
 296 #define FW4_FNAME "cxgb4/t4fw.bin"
 297 #define FW5_FNAME "cxgb4/t5fw.bin"
 298 #define FW4_CFNAME "cxgb4/t4-config.txt"
 299 #define FW5_CFNAME "cxgb4/t5-config.txt"
 300
 301 MODULE_DESCRIPTION(DRV_DESC);
 302 MODULE_AUTHOR("Chelsio Communications");
 303 MODULE_LICENSE("Dual BSD/GPL");
 304 MODULE_VERSION(DRV_VERSION);
 305 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
 306 MODULE_FIRMWARE(FW4_FNAME);
 307 MODULE_FIRMWARE(FW5_FNAME);
 308
 309 /*
 310  * Normally we're willing to become the firmware's Master PF but will be happy
 311  * if another PF has already become the Master and initialized the adapter.
 312  * Setting "force_init" will cause this driver to forcibly establish itself as
 313  * the Master PF and initialize the adapter.
 314  */
 315 static uint force_init;
 316
 317 module_param(force_init, uint, 0644);
 318 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter");
 319
 320 /*
 321  * Normally if the firmware we connect to has Configuration File support, we
 322  * use that and only fall back to the old Driver-based initialization if the
 323  * Configuration File fails for some reason.  If force_old_init is set, then
 324  * we'll always use the old Driver-based initialization sequence.
 325  */
 326 static uint force_old_init;
 327
 328 module_param(force_old_init, uint, 0644);
 329 MODULE_PARM_DESC(force_old_init, "Force old initialization sequence");
 330
 331 static int dflt_msg_enable = DFLT_MSG_ENABLE;
 332
 333 module_param(dflt_msg_enable, int, 0644);
 334 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
 335
 336 /*
 337  * The driver uses the best interrupt scheme available on a platform in the
 338  * order MSI-X, MSI, legacy INTx interrupts.  This parameter determines which
 339  * of these schemes the driver may consider as follows:
 340  *
 341  * msi = 2: choose from among all three options
 342  * msi = 1: only consider MSI and INTx interrupts
 343  * msi = 0: force INTx interrupts
 344  */
 345 static int msi = 2;
 346
 347 module_param(msi, int, 0644);
 348 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
 349
 350 /*
 351  * Queue interrupt hold-off timer values.  Queues default to the first of these
 352  * upon creation.
 353  */
 354 static unsigned int intr_holdoff[SGE_NTIMERS - 1] = { 5, 10, 20, 50, 100 };
 355
 356 module_param_array(intr_holdoff, uint, NULL, 0644);
 357 MODULE_PARM_DESC(intr_holdoff, "values for queue interrupt hold-off timers "
 358                  "0..4 in microseconds");
 359
 360 static unsigned int intr_cnt[SGE_NCOUNTERS - 1] = { 4, 8, 16 };
 361
 362 module_param_array(intr_cnt, uint, NULL, 0644);
 363 MODULE_PARM_DESC(intr_cnt,
 364                  "thresholds 1..3 for queue interrupt packet counters");
 365
 366 /*
 367  * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
 368  * offset by 2 bytes in order to have the IP headers line up on 4-byte
 369  * boundaries.  This is a requirement for many architectures which will throw
 370  * a machine check fault if an attempt is made to access one of the 4-byte IP
 371  * header fields on a non-4-byte boundary.  And it's a major performance issue
 372  * even on some architectures which allow it like some implementations of the
 373  * x86 ISA.  However, some architectures don't mind this and for some very
 374  * edge-case performance sensitive applications (like forwarding large volumes
 375  * of small packets), setting this DMA offset to 0 will decrease the number of
 376  * PCI-E Bus transfers enough to measurably affect performance.
 377  */
 378 static int rx_dma_offset = 2;
 379
 380 static bool vf_acls;
 381
 382 #ifdef CONFIG_PCI_IOV
 383 module_param(vf_acls, bool, 0644);
 384 MODULE_PARM_DESC(vf_acls, "if set enable virtualization L2 ACL enforcement");
 385
 386 /* Configure the number of PCI-E Virtual Function which are to be instantiated
 387  * on SR-IOV Capable Physical Functions.
 388  */
 389 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
 390
 391 module_param_array(num_vf, uint, NULL, 0644);
 392 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
 393 #endif
 394
 395 /* TX Queue select used to determine what algorithm to use for selecting TX
 396  * queue. Select between the kernel provided function (select_queue=0) or user
 397  * cxgb_select_queue function (select_queue=1)
 398  *
 399  * Default: select_queue=0
 400  */
 401 static int select_queue;
 402 module_param(select_queue, int, 0644);
 403 MODULE_PARM_DESC(select_queue,
 404                  "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
 405
 406 /*
 407  * The filter TCAM has a fixed portion and a variable portion.  The fixed
 408  * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
 409  * ports.  The variable portion is 36 bits which can include things like Exact
 410  * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
 411  * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
 412  * far exceed the 36-bit budget for this "compressed" header portion of the
 413  * filter.  Thus, we have a scarce resource which must be carefully managed.
 414  *
 415  * By default we set this up to mostly match the set of filter matching
 416  * capabilities of T3 but with accommodations for some of T4's more
 417  * interesting features:
 418  *
 419  *   { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
 420  *     [Inner] VLAN (17), Port (3), FCoE (1) }
 421  */
 422 enum {
 423         TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
 424         TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT,
 425         TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT,
 426 };
 427
 428 static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
 429
 430 module_param(tp_vlan_pri_map, uint, 0644);
 431 MODULE_PARM_DESC(tp_vlan_pri_map, "global compressed filter configuration");
 432
 433 static struct dentry *cxgb4_debugfs_root;
 434
 435 static LIST_HEAD(adapter_list);
 436 static DEFINE_MUTEX(uld_mutex);
 437 /* Adapter list to be accessed from atomic context */
 438 static LIST_HEAD(adap_rcu_list);
 439 static DEFINE_SPINLOCK(adap_rcu_lock);
 440 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
 441 static const char *uld_str[] = { "RDMA", "iSCSI" };
 442
 443 static void link_report(struct net_device *dev)
 444 {
 445         if (!netif_carrier_ok(dev))
 446                 netdev_info(dev, "link down\n");
 447         else {
 448                 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
 449
 450                 const char *s = "10Mbps";
 451                 const struct port_info *p = netdev_priv(dev);
 452
 453                 switch (p->link_cfg.speed) {
 454                 case 10000:
 455                         s = "10Gbps";
 456                         break;
 457                 case 1000:
 458                         s = "1000Mbps";
 459                         break;
 460                 case 100:
 461                         s = "100Mbps";
 462                         break;
 463                 case 40000:
 464                         s = "40Gbps";
 465                         break;
 466                 }
 467
 468                 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
 469                             fc[p->link_cfg.fc]);
 470         }
 471 }
 472
 473 #ifdef CONFIG_CHELSIO_T4_DCB
 474 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
 475 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
 476 {
 477         struct port_info *pi = netdev_priv(dev);
 478         struct adapter *adap = pi->adapter;
 479         struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
 480         int i;
 481
 482         /* We use a simple mapping of Port TX Queue Index to DCB
 483          * Priority when we're enabling DCB.
 484          */
 485         for (i = 0; i < pi->nqsets; i++, txq++) {
 486                 u32 name, value;
 487                 int err;
 488
 489                 name = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
 490                         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
 491                         FW_PARAMS_PARAM_YZ(txq->q.cntxt_id));
 492                 value = enable ? i : 0xffffffff;
 493
 494                 /* Since we can be called while atomic (from "interrupt
 495                  * level") we need to issue the Set Parameters Commannd
 496                  * without sleeping (timeout < 0).
 497                  */
 498                 err = t4_set_params_nosleep(adap, adap->mbox, adap->fn, 0, 1,
 499                                             &name, &value);
 500
 501                 if (err)
 502                         dev_err(adap->pdev_dev,
 503                                 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
 504                                 enable ? "set" : "unset", pi->port_id, i, -err);
 505         }
 506 }
 507 #endif /* CONFIG_CHELSIO_T4_DCB */
 508
 509 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
 510 {
 511         struct net_device *dev = adapter->port[port_id];
 512
 513         /* Skip changes from disabled ports. */
 514         if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
 515                 if (link_stat)
 516                         netif_carrier_on(dev);
 517                 else {
 518 #ifdef CONFIG_CHELSIO_T4_DCB
 519                         cxgb4_dcb_state_init(dev);
 520                         dcb_tx_queue_prio_enable(dev, false);
 521 #endif /* CONFIG_CHELSIO_T4_DCB */
 522                         netif_carrier_off(dev);
 523                 }
 524
 525                 link_report(dev);
 526         }
 527 }
 528
 529 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
 530 {
 531         static const char *mod_str[] = {
 532                 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
 533         };
 534
 535         const struct net_device *dev = adap->port[port_id];
 536         const struct port_info *pi = netdev_priv(dev);
 537
 538         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
 539                 netdev_info(dev, "port module unplugged\n");
 540         else if (pi->mod_type < ARRAY_SIZE(mod_str))
 541                 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
 542 }
 543
 544 /*
 545  * Configure the exact and hash address filters to handle a port's multicast
 546  * and secondary unicast MAC addresses.
 547  */
 548 static int set_addr_filters(const struct net_device *dev, bool sleep)
 549 {
 550         u64 mhash = 0;
 551         u64 uhash = 0;
 552         bool free = true;
 553         u16 filt_idx[7];
 554         const u8 *addr[7];
 555         int ret, naddr = 0;
 556         const struct netdev_hw_addr *ha;
 557         int uc_cnt = netdev_uc_count(dev);
 558         int mc_cnt = netdev_mc_count(dev);
 559         const struct port_info *pi = netdev_priv(dev);
 560         unsigned int mb = pi->adapter->fn;
 561
 562         /* first do the secondary unicast addresses */
 563         netdev_for_each_uc_addr(ha, dev) {
 564                 addr[naddr++] = ha->addr;
 565                 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 566                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 567                                         naddr, addr, filt_idx, &uhash, sleep);
 568                         if (ret < 0)
 569                                 return ret;
 570
 571                         free = false;
 572                         naddr = 0;
 573                 }
 574         }
 575
 576         /* next set up the multicast addresses */
 577         netdev_for_each_mc_addr(ha, dev) {
 578                 addr[naddr++] = ha->addr;
 579                 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
 580                         ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
 581                                         naddr, addr, filt_idx, &mhash, sleep);
 582                         if (ret < 0)
 583                                 return ret;
 584
 585                         free = false;
 586                         naddr = 0;
 587                 }
 588         }
 589
 590         return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
 591                                 uhash | mhash, sleep);
 592 }
 593
 594 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
 595 module_param(dbfifo_int_thresh, int, 0644);
 596 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
 597
 598 /*
 599  * usecs to sleep while draining the dbfifo
 600  */
 601 static int dbfifo_drain_delay = 1000;
 602 module_param(dbfifo_drain_delay, int, 0644);
 603 MODULE_PARM_DESC(dbfifo_drain_delay,
 604                  "usecs to sleep while draining the dbfifo");
 605
 606 /*
 607  * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
 608  * If @mtu is -1 it is left unchanged.
 609  */
 610 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
 611 {
 612         int ret;
 613         struct port_info *pi = netdev_priv(dev);
 614
 615         ret = set_addr_filters(dev, sleep_ok);
 616         if (ret == 0)
 617                 ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, mtu,
 618                                     (dev->flags & IFF_PROMISC) ? 1 : 0,
 619                                     (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
 620                                     sleep_ok);
 621         return ret;
 622 }
 623
 624 static struct workqueue_struct *workq;
 625
 626 /**
 627  *      link_start - enable a port
 628  *      @dev: the port to enable
 629  *
 630  *      Performs the MAC and PHY actions needed to enable a port.
 631  */
 632 static int link_start(struct net_device *dev)
 633 {
 634         int ret;
 635         struct port_info *pi = netdev_priv(dev);
 636         unsigned int mb = pi->adapter->fn;
 637
 638         /*
 639          * We do not set address filters and promiscuity here, the stack does
 640          * that step explicitly.
 641          */
 642         ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
 643                             !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
 644         if (ret == 0) {
 645                 ret = t4_change_mac(pi->adapter, mb, pi->viid,
 646                                     pi->xact_addr_filt, dev->dev_addr, true,
 647                                     true);
 648                 if (ret >= 0) {
 649                         pi->xact_addr_filt = ret;
 650                         ret = 0;
 651                 }
 652         }
 653         if (ret == 0)
 654                 ret = t4_link_start(pi->adapter, mb, pi->tx_chan,
 655                                     &pi->link_cfg);
 656         if (ret == 0)
 657                 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
 658                                           true, CXGB4_DCB_ENABLED);
 659
 660         return ret;
 661 }
 662
 663 int cxgb4_dcb_enabled(const struct net_device *dev)
 664 {
 665 #ifdef CONFIG_CHELSIO_T4_DCB
 666         struct port_info *pi = netdev_priv(dev);
 667
 668         return pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED;
 669 #else
 670         return 0;
 671 #endif
 672 }
 673 EXPORT_SYMBOL(cxgb4_dcb_enabled);
 674
 675 #ifdef CONFIG_CHELSIO_T4_DCB
 676 /* Handle a Data Center Bridging update message from the firmware. */
 677 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
 678 {
 679         int port = FW_PORT_CMD_PORTID_GET(ntohl(pcmd->op_to_portid));
 680         struct net_device *dev = adap->port[port];
 681         int old_dcb_enabled = cxgb4_dcb_enabled(dev);
 682         int new_dcb_enabled;
 683
 684         cxgb4_dcb_handle_fw_update(adap, pcmd);
 685         new_dcb_enabled = cxgb4_dcb_enabled(dev);
 686
 687         /* If the DCB has become enabled or disabled on the port then we're
 688          * going to need to set up/tear down DCB Priority parameters for the
 689          * TX Queues associated with the port.
 690          */
 691         if (new_dcb_enabled != old_dcb_enabled)
 692                 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
 693 }
 694 #endif /* CONFIG_CHELSIO_T4_DCB */
 695
 696 /* Clear a filter and release any of its resources that we own.  This also
 697  * clears the filter's "pending" status.
 698  */
 699 static void clear_filter(struct adapter *adap, struct filter_entry *f)
 700 {
 701         /* If the new or old filter have loopback rewriteing rules then we'll
 702          * need to free any existing Layer Two Table (L2T) entries of the old
 703          * filter rule.  The firmware will handle freeing up any Source MAC
 704          * Table (SMT) entries used for rewriting Source MAC Addresses in
 705          * loopback rules.
 706          */
 707         if (f->l2t)
 708                 cxgb4_l2t_release(f->l2t);
 709
 710         /* The zeroing of the filter rule below clears the filter valid,
 711          * pending, locked flags, l2t pointer, etc. so it's all we need for
 712          * this operation.
 713          */
 714         memset(f, 0, sizeof(*f));
 715 }
 716
 717 /* Handle a filter write/deletion reply.
 718  */
 719 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
 720 {
 721         unsigned int idx = GET_TID(rpl);
 722         unsigned int nidx = idx - adap->tids.ftid_base;
 723         unsigned int ret;
 724         struct filter_entry *f;
 725
 726         if (idx >= adap->tids.ftid_base && nidx <
 727            (adap->tids.nftids + adap->tids.nsftids)) {
 728                 idx = nidx;
 729                 ret = GET_TCB_COOKIE(rpl->cookie);
 730                 f = &adap->tids.ftid_tab[idx];
 731
 732                 if (ret == FW_FILTER_WR_FLT_DELETED) {
 733                         /* Clear the filter when we get confirmation from the
 734                          * hardware that the filter has been deleted.
 735                          */
 736                         clear_filter(adap, f);
 737                 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
 738                         dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
 739                                 idx);
 740                         clear_filter(adap, f);
 741                 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
 742                         f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
 743                         f->pending = 0;  /* asynchronous setup completed */
 744                         f->valid = 1;
 745                 } else {
 746                         /* Something went wrong.  Issue a warning about the
 747                          * problem and clear everything out.
 748                          */
 749                         dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
 750                                 idx, ret);
 751                         clear_filter(adap, f);
 752                 }
 753         }
 754 }
 755
 756 /* Response queue handler for the FW event queue.
 757  */
 758 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
 759                           const struct pkt_gl *gl)
 760 {
 761         u8 opcode = ((const struct rss_header *)rsp)->opcode;
 762
 763         rsp++;                                          /* skip RSS header */
 764
 765         /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
 766          */
 767         if (unlikely(opcode == CPL_FW4_MSG &&
 768            ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
 769                 rsp++;
 770                 opcode = ((const struct rss_header *)rsp)->opcode;
 771                 rsp++;
 772                 if (opcode != CPL_SGE_EGR_UPDATE) {
 773                         dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
 774                                 , opcode);
 775                         goto out;
 776                 }
 777         }
 778
 779         if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
 780                 const struct cpl_sge_egr_update *p = (void *)rsp;
 781                 unsigned int qid = EGR_QID(ntohl(p->opcode_qid));
 782                 struct sge_txq *txq;
 783
 784                 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
 785                 txq->restarts++;
 786                 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
 787                         struct sge_eth_txq *eq;
 788
 789                         eq = container_of(txq, struct sge_eth_txq, q);
 790                         netif_tx_wake_queue(eq->txq);
 791                 } else {
 792                         struct sge_ofld_txq *oq;
 793
 794                         oq = container_of(txq, struct sge_ofld_txq, q);
 795                         tasklet_schedule(&oq->qresume_tsk);
 796                 }
 797         } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
 798                 const struct cpl_fw6_msg *p = (void *)rsp;
 799
 800 #ifdef CONFIG_CHELSIO_T4_DCB
 801                 const struct fw_port_cmd *pcmd = (const void *)p->data;
 802                 unsigned int cmd = FW_CMD_OP_GET(ntohl(pcmd->op_to_portid));
 803                 unsigned int action =
 804                         FW_PORT_CMD_ACTION_GET(ntohl(pcmd->action_to_len16));
 805
 806                 if (cmd == FW_PORT_CMD &&
 807                     action == FW_PORT_ACTION_GET_PORT_INFO) {
 808                         int port = FW_PORT_CMD_PORTID_GET(
 809                                         be32_to_cpu(pcmd->op_to_portid));
 810                         struct net_device *dev = q->adap->port[port];
 811                         int state_input = ((pcmd->u.info.dcbxdis_pkd &
 812                                             FW_PORT_CMD_DCBXDIS)
 813                                            ? CXGB4_DCB_INPUT_FW_DISABLED
 814                                            : CXGB4_DCB_INPUT_FW_ENABLED);
 815
 816                         cxgb4_dcb_state_fsm(dev, state_input);
 817                 }
 818
 819                 if (cmd == FW_PORT_CMD &&
 820                     action == FW_PORT_ACTION_L2_DCB_CFG)
 821                         dcb_rpl(q->adap, pcmd);
 822                 else
 823 #endif
 824                         if (p->type == 0)
 825                                 t4_handle_fw_rpl(q->adap, p->data);
 826         } else if (opcode == CPL_L2T_WRITE_RPL) {
 827                 const struct cpl_l2t_write_rpl *p = (void *)rsp;
 828
 829                 do_l2t_write_rpl(q->adap, p);
 830         } else if (opcode == CPL_SET_TCB_RPL) {
 831                 const struct cpl_set_tcb_rpl *p = (void *)rsp;
 832
 833                 filter_rpl(q->adap, p);
 834         } else
 835                 dev_err(q->adap->pdev_dev,
 836                         "unexpected CPL %#x on FW event queue\n", opcode);
 837 out:
 838         return 0;
 839 }
 840
 841 /**
 842  *      uldrx_handler - response queue handler for ULD queues
 843  *      @q: the response queue that received the packet
 844  *      @rsp: the response queue descriptor holding the offload message
 845  *      @gl: the gather list of packet fragments
 846  *
 847  *      Deliver an ingress offload packet to a ULD.  All processing is done by
 848  *      the ULD, we just maintain statistics.
 849  */
 850 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
 851                          const struct pkt_gl *gl)
 852 {
 853         struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
 854
 855         /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
 856          */
 857         if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
 858             ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
 859                 rsp += 2;
 860
 861         if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
 862                 rxq->stats.nomem++;
 863                 return -1;
 864         }
 865         if (gl == NULL)
 866                 rxq->stats.imm++;
 867         else if (gl == CXGB4_MSG_AN)
 868                 rxq->stats.an++;
 869         else
 870                 rxq->stats.pkts++;
 871         return 0;
 872 }
 873
 874 static void disable_msi(struct adapter *adapter)
 875 {
 876         if (adapter->flags & USING_MSIX) {
 877                 pci_disable_msix(adapter->pdev);
 878                 adapter->flags &= ~USING_MSIX;
 879         } else if (adapter->flags & USING_MSI) {
 880                 pci_disable_msi(adapter->pdev);
 881                 adapter->flags &= ~USING_MSI;
 882         }
 883 }
 884
 885 /*
 886  * Interrupt handler for non-data events used with MSI-X.
 887  */
 888 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
 889 {
 890         struct adapter *adap = cookie;
 891
 892         u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE));
 893         if (v & PFSW) {
 894                 adap->swintr = 1;
 895                 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE), v);
 896         }
 897         t4_slow_intr_handler(adap);
 898         return IRQ_HANDLED;
 899 }
 900
 901 /*
 902  * Name the MSI-X interrupts.
 903  */
 904 static void name_msix_vecs(struct adapter *adap)
 905 {
 906         int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
 907
 908         /* non-data interrupts */
 909         snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
 910
 911         /* FW events */
 912         snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
 913                  adap->port[0]->name);
 914
 915         /* Ethernet queues */
 916         for_each_port(adap, j) {
 917                 struct net_device *d = adap->port[j];
 918                 const struct port_info *pi = netdev_priv(d);
 919
 920                 for (i = 0; i < pi->nqsets; i++, msi_idx++)
 921                         snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
 922                                  d->name, i);
 923         }
 924
 925         /* offload queues */
 926         for_each_ofldrxq(&adap->sge, i)
 927                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-ofld%d",
 928                          adap->port[0]->name, i);
 929
 930         for_each_rdmarxq(&adap->sge, i)
 931                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
 932                          adap->port[0]->name, i);
 933
 934         for_each_rdmaciq(&adap->sge, i)
 935                 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
 936                          adap->port[0]->name, i);
 937 }
 938
 939 static int request_msix_queue_irqs(struct adapter *adap)
 940 {
 941         struct sge *s = &adap->sge;
 942         int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
 943         int msi_index = 2;
 944
 945         err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
 946                           adap->msix_info[1].desc, &s->fw_evtq);
 947         if (err)
 948                 return err;
 949
 950         for_each_ethrxq(s, ethqidx) {
 951                 err = request_irq(adap->msix_info[msi_index].vec,
 952                                   t4_sge_intr_msix, 0,
 953                                   adap->msix_info[msi_index].desc,
 954                                   &s->ethrxq[ethqidx].rspq);
 955                 if (err)
 956                         goto unwind;
 957                 msi_index++;
 958         }
 959         for_each_ofldrxq(s, ofldqidx) {
 960                 err = request_irq(adap->msix_info[msi_index].vec,
 961                                   t4_sge_intr_msix, 0,
 962                                   adap->msix_info[msi_index].desc,
 963                                   &s->ofldrxq[ofldqidx].rspq);
 964                 if (err)
 965                         goto unwind;
 966                 msi_index++;
 967         }
 968         for_each_rdmarxq(s, rdmaqidx) {
 969                 err = request_irq(adap->msix_info[msi_index].vec,
 970                                   t4_sge_intr_msix, 0,
 971                                   adap->msix_info[msi_index].desc,
 972                                   &s->rdmarxq[rdmaqidx].rspq);
 973                 if (err)
 974                         goto unwind;
 975                 msi_index++;
 976         }
 977         for_each_rdmaciq(s, rdmaciqqidx) {
 978                 err = request_irq(adap->msix_info[msi_index].vec,
 979                                   t4_sge_intr_msix, 0,
 980                                   adap->msix_info[msi_index].desc,
 981                                   &s->rdmaciq[rdmaciqqidx].rspq);
 982                 if (err)
 983                         goto unwind;
 984                 msi_index++;
 985         }
 986         return 0;
 987
 988 unwind:
 989         while (--rdmaciqqidx >= 0)
 990                 free_irq(adap->msix_info[--msi_index].vec,
 991                          &s->rdmaciq[rdmaciqqidx].rspq);
 992         while (--rdmaqidx >= 0)
 993                 free_irq(adap->msix_info[--msi_index].vec,
 994                          &s->rdmarxq[rdmaqidx].rspq);
 995         while (--ofldqidx >= 0)
 996                 free_irq(adap->msix_info[--msi_index].vec,
 997                          &s->ofldrxq[ofldqidx].rspq);
 998         while (--ethqidx >= 0)
 999                 free_irq(adap->msix_info[--msi_index].vec,
1000                          &s->ethrxq[ethqidx].rspq);
1001         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1002         return err;
1003 }
1004
1005 static void free_msix_queue_irqs(struct adapter *adap)
1006 {
1007         int i, msi_index = 2;
1008         struct sge *s = &adap->sge;
1009
1010         free_irq(adap->msix_info[1].vec, &s->fw_evtq);
1011         for_each_ethrxq(s, i)
1012                 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
1013         for_each_ofldrxq(s, i)
1014                 free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
1015         for_each_rdmarxq(s, i)
1016                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
1017         for_each_rdmaciq(s, i)
1018                 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
1019 }
1020
1021 /**
1022  *      write_rss - write the RSS table for a given port
1023  *      @pi: the port
1024  *      @queues: array of queue indices for RSS
1025  *
1026  *      Sets up the portion of the HW RSS table for the port's VI to distribute
1027  *      packets to the Rx queues in @queues.
1028  */
1029 static int write_rss(const struct port_info *pi, const u16 *queues)
1030 {
1031         u16 *rss;
1032         int i, err;
1033         const struct sge_eth_rxq *q = &pi->adapter->sge.ethrxq[pi->first_qset];
1034
1035         rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
1036         if (!rss)
1037                 return -ENOMEM;
1038
1039         /* map the queue indices to queue ids */
1040         for (i = 0; i < pi->rss_size; i++, queues++)
1041                 rss[i] = q[*queues].rspq.abs_id;
1042
1043         err = t4_config_rss_range(pi->adapter, pi->adapter->fn, pi->viid, 0,
1044                                   pi->rss_size, rss, pi->rss_size);
1045         kfree(rss);
1046         return err;
1047 }
1048
1049 /**
1050  *      setup_rss - configure RSS
1051  *      @adap: the adapter
1052  *
1053  *      Sets up RSS for each port.
1054  */
1055 static int setup_rss(struct adapter *adap)
1056 {
1057         int i, err;
1058
1059         for_each_port(adap, i) {
1060                 const struct port_info *pi = adap2pinfo(adap, i);
1061
1062                 err = write_rss(pi, pi->rss);
1063                 if (err)
1064                         return err;
1065         }
1066         return 0;
1067 }
1068
1069 /*
1070  * Return the channel of the ingress queue with the given qid.
1071  */
1072 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
1073 {
1074         qid -= p->ingr_start;
1075         return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
1076 }
1077
1078 /*
1079  * Wait until all NAPI handlers are descheduled.
1080  */
1081 static void quiesce_rx(struct adapter *adap)
1082 {
1083         int i;
1084
1085         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1086                 struct sge_rspq *q = adap->sge.ingr_map[i];
1087
1088                 if (q && q->handler)
1089                         napi_disable(&q->napi);
1090         }
1091 }
1092
1093 /*
1094  * Enable NAPI scheduling and interrupt generation for all Rx queues.
1095  */
1096 static void enable_rx(struct adapter *adap)
1097 {
1098         int i;
1099
1100         for (i = 0; i < ARRAY_SIZE(adap->sge.ingr_map); i++) {
1101                 struct sge_rspq *q = adap->sge.ingr_map[i];
1102
1103                 if (!q)
1104                         continue;
1105                 if (q->handler)
1106                         napi_enable(&q->napi);
1107                 /* 0-increment GTS to start the timer and enable interrupts */
1108                 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS),
1109                              SEINTARM(q->intr_params) |
1110                              INGRESSQID(q->cntxt_id));
1111         }
1112 }
1113
1114 /**
1115  *      setup_sge_queues - configure SGE Tx/Rx/response queues
1116  *      @adap: the adapter
1117  *
1118  *      Determines how many sets of SGE queues to use and initializes them.
1119  *      We support multiple queue sets per port if we have MSI-X, otherwise
1120  *      just one queue set per port.
1121  */
1122 static int setup_sge_queues(struct adapter *adap)
1123 {
1124         int err, msi_idx, i, j;
1125         struct sge *s = &adap->sge;
1126
1127         bitmap_zero(s->starving_fl, MAX_EGRQ);
1128         bitmap_zero(s->txq_maperr, MAX_EGRQ);
1129
1130         if (adap->flags & USING_MSIX)
1131                 msi_idx = 1;         /* vector 0 is for non-queue interrupts */
1132         else {
1133                 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1134                                        NULL, NULL);
1135                 if (err)
1136                         return err;
1137                 msi_idx = -((int)s->intrq.abs_id + 1);
1138         }
1139
1140         err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1141                                msi_idx, NULL, fwevtq_handler);
1142         if (err) {
1143 freeout:        t4_free_sge_resources(adap);
1144                 return err;
1145         }
1146
1147         for_each_port(adap, i) {
1148                 struct net_device *dev = adap->port[i];
1149                 struct port_info *pi = netdev_priv(dev);
1150                 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1151                 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1152
1153                 for (j = 0; j < pi->nqsets; j++, q++) {
1154                         if (msi_idx > 0)
1155                                 msi_idx++;
1156                         err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1157                                                msi_idx, &q->fl,
1158                                                t4_ethrx_handler);
1159                         if (err)
1160                                 goto freeout;
1161                         q->rspq.idx = j;
1162                         memset(&q->stats, 0, sizeof(q->stats));
1163                 }
1164                 for (j = 0; j < pi->nqsets; j++, t++) {
1165                         err = t4_sge_alloc_eth_txq(adap, t, dev,
1166                                         netdev_get_tx_queue(dev, j),
1167                                         s->fw_evtq.cntxt_id);
1168                         if (err)
1169                                 goto freeout;
1170                 }
1171         }
1172
1173         j = s->ofldqsets / adap->params.nports; /* ofld queues per channel */
1174         for_each_ofldrxq(s, i) {
1175                 struct sge_ofld_rxq *q = &s->ofldrxq[i];
1176                 struct net_device *dev = adap->port[i / j];
1177
1178                 if (msi_idx > 0)
1179                         msi_idx++;
1180                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev, msi_idx,
1181                                        q->fl.size ? &q->fl : NULL,
1182                                        uldrx_handler);
1183                 if (err)
1184                         goto freeout;
1185                 memset(&q->stats, 0, sizeof(q->stats));
1186                 s->ofld_rxq[i] = q->rspq.abs_id;
1187                 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i], dev,
1188                                             s->fw_evtq.cntxt_id);
1189                 if (err)
1190                         goto freeout;
1191         }
1192
1193         for_each_rdmarxq(s, i) {
1194                 struct sge_ofld_rxq *q = &s->rdmarxq[i];
1195
1196                 if (msi_idx > 0)
1197                         msi_idx++;
1198                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1199                                        msi_idx, q->fl.size ? &q->fl : NULL,
1200                                        uldrx_handler);
1201                 if (err)
1202                         goto freeout;
1203                 memset(&q->stats, 0, sizeof(q->stats));
1204                 s->rdma_rxq[i] = q->rspq.abs_id;
1205         }
1206
1207         for_each_rdmaciq(s, i) {
1208                 struct sge_ofld_rxq *q = &s->rdmaciq[i];
1209
1210                 if (msi_idx > 0)
1211                         msi_idx++;
1212                 err = t4_sge_alloc_rxq(adap, &q->rspq, false, adap->port[i],
1213                                        msi_idx, q->fl.size ? &q->fl : NULL,
1214                                        uldrx_handler);
1215                 if (err)
1216                         goto freeout;
1217                 memset(&q->stats, 0, sizeof(q->stats));
1218                 s->rdma_ciq[i] = q->rspq.abs_id;
1219         }
1220
1221         for_each_port(adap, i) {
1222                 /*
1223                  * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1224                  * have RDMA queues, and that's the right value.
1225                  */
1226                 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1227                                             s->fw_evtq.cntxt_id,
1228                                             s->rdmarxq[i].rspq.cntxt_id);
1229                 if (err)
1230                         goto freeout;
1231         }
1232
1233         t4_write_reg(adap, MPS_TRC_RSS_CONTROL,
1234                      RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) |
1235                      QUEUENUMBER(s->ethrxq[0].rspq.abs_id));
1236         return 0;
1237 }
1238
1239 /*
1240  * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1241  * The allocated memory is cleared.
1242  */
1243 void *t4_alloc_mem(size_t size)
1244 {
1245         void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1246
1247         if (!p)
1248                 p = vzalloc(size);
1249         return p;
1250 }
1251
1252 /*
1253  * Free memory allocated through alloc_mem().
1254  */
1255 static void t4_free_mem(void *addr)
1256 {
1257         if (is_vmalloc_addr(addr))
1258                 vfree(addr);
1259         else
1260                 kfree(addr);
1261 }
1262
1263 /* Send a Work Request to write the filter at a specified index.  We construct
1264  * a Firmware Filter Work Request to have the work done and put the indicated
1265  * filter into "pending" mode which will prevent any further actions against
1266  * it till we get a reply from the firmware on the completion status of the
1267  * request.
1268  */
1269 static int set_filter_wr(struct adapter *adapter, int fidx)
1270 {
1271         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1272         struct sk_buff *skb;
1273         struct fw_filter_wr *fwr;
1274         unsigned int ftid;
1275
1276         /* If the new filter requires loopback Destination MAC and/or VLAN
1277          * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1278          * the filter.
1279          */
1280         if (f->fs.newdmac || f->fs.newvlan) {
1281                 /* allocate L2T entry for new filter */
1282                 f->l2t = t4_l2t_alloc_switching(adapter->l2t);
1283                 if (f->l2t == NULL)
1284                         return -EAGAIN;
1285                 if (t4_l2t_set_switching(adapter, f->l2t, f->fs.vlan,
1286                                         f->fs.eport, f->fs.dmac)) {
1287                         cxgb4_l2t_release(f->l2t);
1288                         f->l2t = NULL;
1289                         return -ENOMEM;
1290                 }
1291         }
1292
1293         ftid = adapter->tids.ftid_base + fidx;
1294
1295         skb = alloc_skb(sizeof(*fwr), GFP_KERNEL | __GFP_NOFAIL);
1296         fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1297         memset(fwr, 0, sizeof(*fwr));
1298
1299         /* It would be nice to put most of the following in t4_hw.c but most
1300          * of the work is translating the cxgbtool ch_filter_specification
1301          * into the Work Request and the definition of that structure is
1302          * currently in cxgbtool.h which isn't appropriate to pull into the
1303          * common code.  We may eventually try to come up with a more neutral
1304          * filter specification structure but for now it's easiest to simply
1305          * put this fairly direct code in line ...
1306          */
1307         fwr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
1308         fwr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*fwr)/16));
1309         fwr->tid_to_iq =
1310                 htonl(V_FW_FILTER_WR_TID(ftid) |
1311                       V_FW_FILTER_WR_RQTYPE(f->fs.type) |
1312                       V_FW_FILTER_WR_NOREPLY(0) |
1313                       V_FW_FILTER_WR_IQ(f->fs.iq));
1314         fwr->del_filter_to_l2tix =
1315                 htonl(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
1316                       V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
1317                       V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
1318                       V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
1319                       V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
1320                       V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
1321                       V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
1322                       V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
1323                       V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
1324                                              f->fs.newvlan == VLAN_REWRITE) |
1325                       V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
1326                                             f->fs.newvlan == VLAN_REWRITE) |
1327                       V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
1328                       V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
1329                       V_FW_FILTER_WR_PRIO(f->fs.prio) |
1330                       V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
1331         fwr->ethtype = htons(f->fs.val.ethtype);
1332         fwr->ethtypem = htons(f->fs.mask.ethtype);
1333         fwr->frag_to_ovlan_vldm =
1334                 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
1335                  V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
1336                  V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.ivlan_vld) |
1337                  V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.ovlan_vld) |
1338                  V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.ivlan_vld) |
1339                  V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.ovlan_vld));
1340         fwr->smac_sel = 0;
1341         fwr->rx_chan_rx_rpl_iq =
1342                 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1343                       V_FW_FILTER_WR_RX_RPL_IQ(adapter->sge.fw_evtq.abs_id));
1344         fwr->maci_to_matchtypem =
1345                 htonl(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
1346                       V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
1347                       V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
1348                       V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
1349                       V_FW_FILTER_WR_PORT(f->fs.val.iport) |
1350                       V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
1351                       V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
1352                       V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
1353         fwr->ptcl = f->fs.val.proto;
1354         fwr->ptclm = f->fs.mask.proto;
1355         fwr->ttyp = f->fs.val.tos;
1356         fwr->ttypm = f->fs.mask.tos;
1357         fwr->ivlan = htons(f->fs.val.ivlan);
1358         fwr->ivlanm = htons(f->fs.mask.ivlan);
1359         fwr->ovlan = htons(f->fs.val.ovlan);
1360         fwr->ovlanm = htons(f->fs.mask.ovlan);
1361         memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1362         memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1363         memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1364         memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1365         fwr->lp = htons(f->fs.val.lport);
1366         fwr->lpm = htons(f->fs.mask.lport);
1367         fwr->fp = htons(f->fs.val.fport);
1368         fwr->fpm = htons(f->fs.mask.fport);
1369         if (f->fs.newsmac)
1370                 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1371
1372         /* Mark the filter as "pending" and ship off the Filter Work Request.
1373          * When we get the Work Request Reply we'll clear the pending status.
1374          */
1375         f->pending = 1;
1376         set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1377         t4_ofld_send(adapter, skb);
1378         return 0;
1379 }
1380
1381 /* Delete the filter at a specified index.
1382  */
1383 static int del_filter_wr(struct adapter *adapter, int fidx)
1384 {
1385         struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1386         struct sk_buff *skb;
1387         struct fw_filter_wr *fwr;
1388         unsigned int len, ftid;
1389
1390         len = sizeof(*fwr);
1391         ftid = adapter->tids.ftid_base + fidx;
1392
1393         skb = alloc_skb(len, GFP_KERNEL | __GFP_NOFAIL);
1394         fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1395         t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1396
1397         /* Mark the filter as "pending" and ship off the Filter Work Request.
1398          * When we get the Work Request Reply we'll clear the pending status.
1399          */
1400         f->pending = 1;
1401         t4_mgmt_tx(adapter, skb);
1402         return 0;
1403 }
1404
1405 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1406                              void *accel_priv, select_queue_fallback_t fallback)
1407 {
1408         int txq;
1409
1410 #ifdef CONFIG_CHELSIO_T4_DCB
1411         /* If a Data Center Bridging has been successfully negotiated on this
1412          * link then we'll use the skb's priority to map it to a TX Queue.
1413          * The skb's priority is determined via the VLAN Tag Priority Code
1414          * Point field.
1415          */
1416         if (cxgb4_dcb_enabled(dev)) {
1417                 u16 vlan_tci;
1418                 int err;
1419
1420                 err = vlan_get_tag(skb, &vlan_tci);
1421                 if (unlikely(err)) {
1422                         if (net_ratelimit())
1423                                 netdev_warn(dev,
1424                                             "TX Packet without VLAN Tag on DCB Link\n");
1425                         txq = 0;
1426                 } else {
1427                         txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1428                 }
1429                 return txq;
1430         }
1431 #endif /* CONFIG_CHELSIO_T4_DCB */
1432
1433         if (select_queue) {
1434                 txq = (skb_rx_queue_recorded(skb)
1435                         ? skb_get_rx_queue(skb)
1436                         : smp_processor_id());
1437
1438                 while (unlikely(txq >= dev->real_num_tx_queues))
1439                         txq -= dev->real_num_tx_queues;
1440
1441                 return txq;
1442         }
1443
1444         return fallback(dev, skb) % dev->real_num_tx_queues;
1445 }
1446
1447 static inline int is_offload(const struct adapter *adap)
1448 {
1449         return adap->params.offload;
1450 }
1451
1452 /*
1453  * Implementation of ethtool operations.
1454  */
1455
1456 static u32 get_msglevel(struct net_device *dev)
1457 {
1458         return netdev2adap(dev)->msg_enable;
1459 }
1460
1461 static void set_msglevel(struct net_device *dev, u32 val)
1462 {
1463         netdev2adap(dev)->msg_enable = val;
1464 }
1465
1466 static char stats_strings[][ETH_GSTRING_LEN] = {
1467         "TxOctetsOK         ",
1468         "TxFramesOK         ",
1469         "TxBroadcastFrames  ",
1470         "TxMulticastFrames  ",
1471         "TxUnicastFrames    ",
1472         "TxErrorFrames      ",
1473
1474         "TxFrames64         ",
1475         "TxFrames65To127    ",
1476         "TxFrames128To255   ",
1477         "TxFrames256To511   ",
1478         "TxFrames512To1023  ",
1479         "TxFrames1024To1518 ",
1480         "TxFrames1519ToMax  ",
1481
1482         "TxFramesDropped    ",
1483         "TxPauseFrames      ",
1484         "TxPPP0Frames       ",
1485         "TxPPP1Frames       ",
1486         "TxPPP2Frames       ",
1487         "TxPPP3Frames       ",
1488         "TxPPP4Frames       ",
1489         "TxPPP5Frames       ",
1490         "TxPPP6Frames       ",
1491         "TxPPP7Frames       ",
1492
1493         "RxOctetsOK         ",
1494         "RxFramesOK         ",
1495         "RxBroadcastFrames  ",
1496         "RxMulticastFrames  ",
1497         "RxUnicastFrames    ",
1498
1499         "RxFramesTooLong    ",
1500         "RxJabberErrors     ",
1501         "RxFCSErrors        ",
1502         "RxLengthErrors     ",
1503         "RxSymbolErrors     ",
1504         "RxRuntFrames       ",
1505
1506         "RxFrames64         ",
1507         "RxFrames65To127    ",
1508         "RxFrames128To255   ",
1509         "RxFrames256To511   ",
1510         "RxFrames512To1023  ",
1511         "RxFrames1024To1518 ",
1512         "RxFrames1519ToMax  ",
1513
1514         "RxPauseFrames      ",
1515         "RxPPP0Frames       ",
1516         "RxPPP1Frames       ",
1517         "RxPPP2Frames       ",
1518         "RxPPP3Frames       ",
1519         "RxPPP4Frames       ",
1520         "RxPPP5Frames       ",
1521         "RxPPP6Frames       ",
1522         "RxPPP7Frames       ",
1523
1524         "RxBG0FramesDropped ",
1525         "RxBG1FramesDropped ",
1526         "RxBG2FramesDropped ",
1527         "RxBG3FramesDropped ",
1528         "RxBG0FramesTrunc   ",
1529         "RxBG1FramesTrunc   ",
1530         "RxBG2FramesTrunc   ",
1531         "RxBG3FramesTrunc   ",
1532
1533         "TSO                ",
1534         "TxCsumOffload      ",
1535         "RxCsumGood         ",
1536         "VLANextractions    ",
1537         "VLANinsertions     ",
1538         "GROpackets         ",
1539         "GROmerged          ",
1540         "WriteCoalSuccess   ",
1541         "WriteCoalFail      ",
1542 };
1543
1544 static int get_sset_count(struct net_device *dev, int sset)
1545 {
1546         switch (sset) {
1547         case ETH_SS_STATS:
1548                 return ARRAY_SIZE(stats_strings);
1549         default:
1550                 return -EOPNOTSUPP;
1551         }
1552 }
1553
1554 #define T4_REGMAP_SIZE (160 * 1024)
1555 #define T5_REGMAP_SIZE (332 * 1024)
1556
1557 static int get_regs_len(struct net_device *dev)
1558 {
1559         struct adapter *adap = netdev2adap(dev);
1560         if (is_t4(adap->params.chip))
1561                 return T4_REGMAP_SIZE;
1562         else
1563                 return T5_REGMAP_SIZE;
1564 }
1565
1566 static int get_eeprom_len(struct net_device *dev)
1567 {
1568         return EEPROMSIZE;
1569 }
1570
1571 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1572 {
1573         struct adapter *adapter = netdev2adap(dev);
1574
1575         strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1576         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1577         strlcpy(info->bus_info, pci_name(adapter->pdev),
1578                 sizeof(info->bus_info));
1579
1580         if (adapter->params.fw_vers)
1581                 snprintf(info->fw_version, sizeof(info->fw_version),
1582                         "%u.%u.%u.%u, TP %u.%u.%u.%u",
1583                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers),
1584                         FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers),
1585                         FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers),
1586                         FW_HDR_FW_VER_BUILD_GET(adapter->params.fw_vers),
1587                         FW_HDR_FW_VER_MAJOR_GET(adapter->params.tp_vers),
1588                         FW_HDR_FW_VER_MINOR_GET(adapter->params.tp_vers),
1589                         FW_HDR_FW_VER_MICRO_GET(adapter->params.tp_vers),
1590                         FW_HDR_FW_VER_BUILD_GET(adapter->params.tp_vers));
1591 }
1592
1593 static void get_strings(struct net_device *dev, u32 stringset, u8 *data)
1594 {
1595         if (stringset == ETH_SS_STATS)
1596                 memcpy(data, stats_strings, sizeof(stats_strings));
1597 }
1598
1599 /*
1600  * port stats maintained per queue of the port.  They should be in the same
1601  * order as in stats_strings above.
1602  */
1603 struct queue_port_stats {
1604         u64 tso;
1605         u64 tx_csum;
1606         u64 rx_csum;
1607         u64 vlan_ex;
1608         u64 vlan_ins;
1609         u64 gro_pkts;
1610         u64 gro_merged;
1611 };
1612
1613 static void collect_sge_port_stats(const struct adapter *adap,
1614                 const struct port_info *p, struct queue_port_stats *s)
1615 {
1616         int i;
1617         const struct sge_eth_txq *tx = &adap->sge.ethtxq[p->first_qset];
1618         const struct sge_eth_rxq *rx = &adap->sge.ethrxq[p->first_qset];
1619
1620         memset(s, 0, sizeof(*s));
1621         for (i = 0; i < p->nqsets; i++, rx++, tx++) {
1622                 s->tso += tx->tso;
1623                 s->tx_csum += tx->tx_cso;
1624                 s->rx_csum += rx->stats.rx_cso;
1625                 s->vlan_ex += rx->stats.vlan_ex;
1626                 s->vlan_ins += tx->vlan_ins;
1627                 s->gro_pkts += rx->stats.lro_pkts;
1628                 s->gro_merged += rx->stats.lro_merged;
1629         }
1630 }
1631
1632 static void get_stats(struct net_device *dev, struct ethtool_stats *stats,
1633                       u64 *data)
1634 {
1635         struct port_info *pi = netdev_priv(dev);
1636         struct adapter *adapter = pi->adapter;
1637         u32 val1, val2;
1638
1639         t4_get_port_stats(adapter, pi->tx_chan, (struct port_stats *)data);
1640
1641         data += sizeof(struct port_stats) / sizeof(u64);
1642         collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1643         data += sizeof(struct queue_port_stats) / sizeof(u64);
1644         if (!is_t4(adapter->params.chip)) {
1645                 t4_write_reg(adapter, SGE_STAT_CFG, STATSOURCE_T5(7));
1646                 val1 = t4_read_reg(adapter, SGE_STAT_TOTAL);
1647                 val2 = t4_read_reg(adapter, SGE_STAT_MATCH);
1648                 *data = val1 - val2;
1649                 data++;
1650                 *data = val2;
1651                 data++;
1652         } else {
1653                 memset(data, 0, 2 * sizeof(u64));
1654                 *data += 2;
1655         }
1656 }
1657
1658 /*
1659  * Return a version number to identify the type of adapter.  The scheme is:
1660  * - bits 0..9: chip version
1661  * - bits 10..15: chip revision
1662  * - bits 16..23: register dump version
1663  */
1664 static inline unsigned int mk_adap_vers(const struct adapter *ap)
1665 {
1666         return CHELSIO_CHIP_VERSION(ap->params.chip) |
1667                 (CHELSIO_CHIP_RELEASE(ap->params.chip) << 10) | (1 << 16);
1668 }
1669
1670 static void reg_block_dump(struct adapter *ap, void *buf, unsigned int start,
1671                            unsigned int end)
1672 {
1673         u32 *p = buf + start;
1674
1675         for ( ; start <= end; start += sizeof(u32))
1676                 *p++ = t4_read_reg(ap, start);
1677 }
1678
1679 static void get_regs(struct net_device *dev, struct ethtool_regs *regs,
1680                      void *buf)
1681 {
1682         static const unsigned int t4_reg_ranges[] = {
1683                 0x1008, 0x1108,
1684                 0x1180, 0x11b4,
1685                 0x11fc, 0x123c,
1686                 0x1300, 0x173c,
1687                 0x1800, 0x18fc,
1688                 0x3000, 0x30d8,
1689                 0x30e0, 0x5924,
1690                 0x5960, 0x59d4,
1691                 0x5a00, 0x5af8,
1692                 0x6000, 0x6098,
1693                 0x6100, 0x6150,
1694                 0x6200, 0x6208,
1695                 0x6240, 0x6248,
1696                 0x6280, 0x6338,
1697                 0x6370, 0x638c,
1698                 0x6400, 0x643c,
1699                 0x6500, 0x6524,
1700                 0x6a00, 0x6a38,
1701                 0x6a60, 0x6a78,
1702                 0x6b00, 0x6b84,
1703                 0x6bf0, 0x6c84,
1704                 0x6cf0, 0x6d84,
1705                 0x6df0, 0x6e84,
1706                 0x6ef0, 0x6f84,
1707                 0x6ff0, 0x7084,
1708                 0x70f0, 0x7184,
1709                 0x71f0, 0x7284,
1710                 0x72f0, 0x7384,
1711                 0x73f0, 0x7450,
1712                 0x7500, 0x7530,
1713                 0x7600, 0x761c,
1714                 0x7680, 0x76cc,
1715                 0x7700, 0x7798,
1716                 0x77c0, 0x77fc,
1717                 0x7900, 0x79fc,
1718                 0x7b00, 0x7c38,
1719                 0x7d00, 0x7efc,
1720                 0x8dc0, 0x8e1c,
1721                 0x8e30, 0x8e78,
1722                 0x8ea0, 0x8f6c,
1723                 0x8fc0, 0x9074,
1724                 0x90fc, 0x90fc,
1725                 0x9400, 0x9458,
1726                 0x9600, 0x96bc,
1727                 0x9800, 0x9808,
1728                 0x9820, 0x983c,
1729                 0x9850, 0x9864,
1730                 0x9c00, 0x9c6c,
1731                 0x9c80, 0x9cec,
1732                 0x9d00, 0x9d6c,
1733                 0x9d80, 0x9dec,
1734                 0x9e00, 0x9e6c,
1735                 0x9e80, 0x9eec,
1736                 0x9f00, 0x9f6c,
1737                 0x9f80, 0x9fec,
1738                 0xd004, 0xd03c,
1739                 0xdfc0, 0xdfe0,
1740                 0xe000, 0xea7c,
1741                 0xf000, 0x11190,
1742                 0x19040, 0x1906c,
1743                 0x19078, 0x19080,
1744                 0x1908c, 0x19124,
1745                 0x19150, 0x191b0,
1746                 0x191d0, 0x191e8,
1747                 0x19238, 0x1924c,
1748                 0x193f8, 0x19474,
1749                 0x19490, 0x194f8,
1750                 0x19800, 0x19f30,
1751                 0x1a000, 0x1a06c,
1752                 0x1a0b0, 0x1a120,
1753                 0x1a128, 0x1a138,
1754                 0x1a190, 0x1a1c4,
1755                 0x1a1fc, 0x1a1fc,
1756                 0x1e040, 0x1e04c,
1757                 0x1e284, 0x1e28c,
1758                 0x1e2c0, 0x1e2c0,
1759                 0x1e2e0, 0x1e2e0,
1760                 0x1e300, 0x1e384,
1761                 0x1e3c0, 0x1e3c8,
1762                 0x1e440, 0x1e44c,
1763                 0x1e684, 0x1e68c,
1764                 0x1e6c0, 0x1e6c0,
1765                 0x1e6e0, 0x1e6e0,
1766                 0x1e700, 0x1e784,
1767                 0x1e7c0, 0x1e7c8,
1768                 0x1e840, 0x1e84c,
1769                 0x1ea84, 0x1ea8c,
1770                 0x1eac0, 0x1eac0,
1771                 0x1eae0, 0x1eae0,
1772                 0x1eb00, 0x1eb84,
1773                 0x1ebc0, 0x1ebc8,
1774                 0x1ec40, 0x1ec4c,
1775                 0x1ee84, 0x1ee8c,
1776                 0x1eec0, 0x1eec0,
1777                 0x1eee0, 0x1eee0,
1778                 0x1ef00, 0x1ef84,
1779                 0x1efc0, 0x1efc8,
1780                 0x1f040, 0x1f04c,
1781                 0x1f284, 0x1f28c,
1782                 0x1f2c0, 0x1f2c0,
1783                 0x1f2e0, 0x1f2e0,
1784                 0x1f300, 0x1f384,
1785                 0x1f3c0, 0x1f3c8,
1786                 0x1f440, 0x1f44c,
1787                 0x1f684, 0x1f68c,
1788                 0x1f6c0, 0x1f6c0,
1789                 0x1f6e0, 0x1f6e0,
1790                 0x1f700, 0x1f784,
1791                 0x1f7c0, 0x1f7c8,
1792                 0x1f840, 0x1f84c,
1793                 0x1fa84, 0x1fa8c,
1794                 0x1fac0, 0x1fac0,
1795                 0x1fae0, 0x1fae0,
1796                 0x1fb00, 0x1fb84,
1797                 0x1fbc0, 0x1fbc8,
1798                 0x1fc40, 0x1fc4c,
1799                 0x1fe84, 0x1fe8c,
1800                 0x1fec0, 0x1fec0,
1801                 0x1fee0, 0x1fee0,
1802                 0x1ff00, 0x1ff84,
1803                 0x1ffc0, 0x1ffc8,
1804                 0x20000, 0x2002c,
1805                 0x20100, 0x2013c,
1806                 0x20190, 0x201c8,
1807                 0x20200, 0x20318,
1808                 0x20400, 0x20528,
1809                 0x20540, 0x20614,
1810                 0x21000, 0x21040,
1811                 0x2104c, 0x21060,
1812                 0x210c0, 0x210ec,
1813                 0x21200, 0x21268,
1814                 0x21270, 0x21284,
1815                 0x212fc, 0x21388,
1816                 0x21400, 0x21404,
1817                 0x21500, 0x21518,
1818                 0x2152c, 0x2153c,
1819                 0x21550, 0x21554,
1820                 0x21600, 0x21600,
1821                 0x21608, 0x21628,
1822                 0x21630, 0x2163c,
1823                 0x21700, 0x2171c,
1824                 0x21780, 0x2178c,
1825                 0x21800, 0x21c38,
1826                 0x21c80, 0x21d7c,
1827                 0x21e00, 0x21e04,
1828                 0x22000, 0x2202c,
1829                 0x22100, 0x2213c,
1830                 0x22190, 0x221c8,
1831                 0x22200, 0x22318,
1832                 0x22400, 0x22528,
1833                 0x22540, 0x22614,
1834                 0x23000, 0x23040,
1835                 0x2304c, 0x23060,
1836                 0x230c0, 0x230ec,
1837                 0x23200, 0x23268,
1838                 0x23270, 0x23284,
1839                 0x232fc, 0x23388,
1840                 0x23400, 0x23404,
1841                 0x23500, 0x23518,
1842                 0x2352c, 0x2353c,
1843                 0x23550, 0x23554,
1844                 0x23600, 0x23600,
1845                 0x23608, 0x23628,
1846                 0x23630, 0x2363c,
1847                 0x23700, 0x2371c,
1848                 0x23780, 0x2378c,
1849                 0x23800, 0x23c38,
1850                 0x23c80, 0x23d7c,
1851                 0x23e00, 0x23e04,
1852                 0x24000, 0x2402c,
1853                 0x24100, 0x2413c,
1854                 0x24190, 0x241c8,
1855                 0x24200, 0x24318,
1856                 0x24400, 0x24528,
1857                 0x24540, 0x24614,
1858                 0x25000, 0x25040,
1859                 0x2504c, 0x25060,
1860                 0x250c0, 0x250ec,
1861                 0x25200, 0x25268,
1862                 0x25270, 0x25284,
1863                 0x252fc, 0x25388,
1864                 0x25400, 0x25404,
1865                 0x25500, 0x25518,
1866                 0x2552c, 0x2553c,
1867                 0x25550, 0x25554,
1868                 0x25600, 0x25600,
1869                 0x25608, 0x25628,
1870                 0x25630, 0x2563c,
1871                 0x25700, 0x2571c,
1872                 0x25780, 0x2578c,
1873                 0x25800, 0x25c38,
1874                 0x25c80, 0x25d7c,
1875                 0x25e00, 0x25e04,
1876                 0x26000, 0x2602c,
1877                 0x26100, 0x2613c,
1878                 0x26190, 0x261c8,
1879                 0x26200, 0x26318,
1880                 0x26400, 0x26528,
1881                 0x26540, 0x26614,
1882                 0x27000, 0x27040,
1883                 0x2704c, 0x27060,
1884                 0x270c0, 0x270ec,
1885                 0x27200, 0x27268,
1886                 0x27270, 0x27284,
1887                 0x272fc, 0x27388,
1888                 0x27400, 0x27404,
1889                 0x27500, 0x27518,
1890                 0x2752c, 0x2753c,
1891                 0x27550, 0x27554,
1892                 0x27600, 0x27600,
1893                 0x27608, 0x27628,
1894                 0x27630, 0x2763c,
1895                 0x27700, 0x2771c,
1896                 0x27780, 0x2778c,
1897                 0x27800, 0x27c38,
1898                 0x27c80, 0x27d7c,
1899                 0x27e00, 0x27e04
1900         };
1901
1902         static const unsigned int t5_reg_ranges[] = {
1903                 0x1008, 0x1148,
1904                 0x1180, 0x11b4,
1905                 0x11fc, 0x123c,
1906                 0x1280, 0x173c,
1907                 0x1800, 0x18fc,
1908                 0x3000, 0x3028,
1909                 0x3060, 0x30d8,
1910                 0x30e0, 0x30fc,
1911                 0x3140, 0x357c,
1912                 0x35a8, 0x35cc,
1913                 0x35ec, 0x35ec,
1914                 0x3600, 0x5624,
1915                 0x56cc, 0x575c,
1916                 0x580c, 0x5814,
1917                 0x5890, 0x58bc,
1918                 0x5940, 0x59dc,
1919                 0x59fc, 0x5a18,
1920                 0x5a60, 0x5a9c,
1921                 0x5b9c, 0x5bfc,
1922                 0x6000, 0x6040,
1923                 0x6058, 0x614c,
1924                 0x7700, 0x7798,
1925                 0x77c0, 0x78fc,
1926                 0x7b00, 0x7c54,
1927                 0x7d00, 0x7efc,
1928                 0x8dc0, 0x8de0,
1929                 0x8df8, 0x8e84,
1930                 0x8ea0, 0x8f84,
1931                 0x8fc0, 0x90f8,
1932                 0x9400, 0x9470,
1933                 0x9600, 0x96f4,
1934                 0x9800, 0x9808,
1935                 0x9820, 0x983c,
1936                 0x9850, 0x9864,
1937                 0x9c00, 0x9c6c,
1938                 0x9c80, 0x9cec,
1939                 0x9d00, 0x9d6c,
1940                 0x9d80, 0x9dec,
1941                 0x9e00, 0x9e6c,
1942                 0x9e80, 0x9eec,
1943                 0x9f00, 0x9f6c,
1944                 0x9f80, 0xa020,
1945                 0xd004, 0xd03c,
1946                 0xdfc0, 0xdfe0,
1947                 0xe000, 0x11088,
1948                 0x1109c, 0x1117c,
1949                 0x11190, 0x11204,
1950                 0x19040, 0x1906c,
1951                 0x19078, 0x19080,
1952                 0x1908c, 0x19124,
1953                 0x19150, 0x191b0,
1954                 0x191d0, 0x191e8,
1955                 0x19238, 0x19290,
1956                 0x193f8, 0x19474,
1957                 0x19490, 0x194cc,
1958                 0x194f0, 0x194f8,
1959                 0x19c00, 0x19c60,
1960                 0x19c94, 0x19e10,
1961                 0x19e50, 0x19f34,
1962                 0x19f40, 0x19f50,
1963                 0x19f90, 0x19fe4,
1964                 0x1a000, 0x1a06c,
1965                 0x1a0b0, 0x1a120,
1966                 0x1a128, 0x1a138,
1967                 0x1a190, 0x1a1c4,
1968                 0x1a1fc, 0x1a1fc,
1969                 0x1e008, 0x1e00c,
1970                 0x1e040, 0x1e04c,
1971                 0x1e284, 0x1e290,
1972                 0x1e2c0, 0x1e2c0,
1973                 0x1e2e0, 0x1e2e0,
1974                 0x1e300, 0x1e384,
1975                 0x1e3c0, 0x1e3c8,
1976                 0x1e408, 0x1e40c,
1977                 0x1e440, 0x1e44c,
1978                 0x1e684, 0x1e690,
1979                 0x1e6c0, 0x1e6c0,
1980                 0x1e6e0, 0x1e6e0,
1981                 0x1e700, 0x1e784,
1982                 0x1e7c0, 0x1e7c8,
1983                 0x1e808, 0x1e80c,
1984                 0x1e840, 0x1e84c,
1985                 0x1ea84, 0x1ea90,
1986                 0x1eac0, 0x1eac0,
1987                 0x1eae0, 0x1eae0,
1988                 0x1eb00, 0x1eb84,
1989                 0x1ebc0, 0x1ebc8,
1990                 0x1ec08, 0x1ec0c,
1991                 0x1ec40, 0x1ec4c,
1992                 0x1ee84, 0x1ee90,
1993                 0x1eec0, 0x1eec0,
1994                 0x1eee0, 0x1eee0,
1995                 0x1ef00, 0x1ef84,
1996                 0x1efc0, 0x1efc8,
1997                 0x1f008, 0x1f00c,
1998                 0x1f040, 0x1f04c,
1999                 0x1f284, 0x1f290,
2000                 0x1f2c0, 0x1f2c0,
2001                 0x1f2e0, 0x1f2e0,
2002                 0x1f300, 0x1f384,
2003                 0x1f3c0, 0x1f3c8,
2004                 0x1f408, 0x1f40c,
2005                 0x1f440, 0x1f44c,
2006                 0x1f684, 0x1f690,
2007                 0x1f6c0, 0x1f6c0,
2008                 0x1f6e0, 0x1f6e0,
2009                 0x1f700, 0x1f784,
2010                 0x1f7c0, 0x1f7c8,
2011                 0x1f808, 0x1f80c,
2012                 0x1f840, 0x1f84c,
2013                 0x1fa84, 0x1fa90,
2014                 0x1fac0, 0x1fac0,
2015                 0x1fae0, 0x1fae0,
2016                 0x1fb00, 0x1fb84,
2017                 0x1fbc0, 0x1fbc8,
2018                 0x1fc08, 0x1fc0c,
2019                 0x1fc40, 0x1fc4c,
2020                 0x1fe84, 0x1fe90,
2021                 0x1fec0, 0x1fec0,
2022                 0x1fee0, 0x1fee0,
2023                 0x1ff00, 0x1ff84,
2024                 0x1ffc0, 0x1ffc8,
2025                 0x30000, 0x30030,
2026                 0x30100, 0x30144,
2027                 0x30190, 0x301d0,
2028                 0x30200, 0x30318,
2029                 0x30400, 0x3052c,
2030                 0x30540, 0x3061c,
2031                 0x30800, 0x30834,
2032                 0x308c0, 0x30908,
2033                 0x30910, 0x309ac,
2034                 0x30a00, 0x30a04,
2035                 0x30a0c, 0x30a2c,
2036                 0x30a44, 0x30a50,
2037                 0x30a74, 0x30c24,
2038                 0x30d08, 0x30d14,
2039                 0x30d1c, 0x30d20,
2040                 0x30d3c, 0x30d50,
2041                 0x31200, 0x3120c,
2042                 0x31220, 0x31220,
2043                 0x31240, 0x31240,
2044                 0x31600, 0x31600,
2045                 0x31608, 0x3160c,
2046                 0x31a00, 0x31a1c,
2047                 0x31e04, 0x31e20,
2048                 0x31e38, 0x31e3c,
2049                 0x31e80, 0x31e80,
2050                 0x31e88, 0x31ea8,
2051                 0x31eb0, 0x31eb4,
2052                 0x31ec8, 0x31ed4,
2053                 0x31fb8, 0x32004,
2054                 0x32208, 0x3223c,
2055                 0x32600, 0x32630,
2056                 0x32a00, 0x32abc,
2057                 0x32b00, 0x32b70,
2058                 0x33000, 0x33048,
2059                 0x33060, 0x3309c,
2060                 0x330f0, 0x33148,
2061                 0x33160, 0x3319c,
2062                 0x331f0, 0x332e4,
2063                 0x332f8, 0x333e4,
2064                 0x333f8, 0x33448,
2065                 0x33460, 0x3349c,
2066                 0x334f0, 0x33548,
2067                 0x33560, 0x3359c,
2068                 0x335f0, 0x336e4,
2069                 0x336f8, 0x337e4,
2070                 0x337f8, 0x337fc,
2071                 0x33814, 0x33814,
2072                 0x3382c, 0x3382c,
2073                 0x33880, 0x3388c,
2074                 0x338e8, 0x338ec,
2075                 0x33900, 0x33948,
2076                 0x33960, 0x3399c,
2077                 0x339f0, 0x33ae4,
2078                 0x33af8, 0x33b10,
2079                 0x33b28, 0x33b28,
2080                 0x33b3c, 0x33b50,
2081                 0x33bf0, 0x33c10,
2082                 0x33c28, 0x33c28,
2083                 0x33c3c, 0x33c50,
2084                 0x33cf0, 0x33cfc,
2085                 0x34000, 0x34030,
2086                 0x34100, 0x34144,
2087                 0x34190, 0x341d0,
2088                 0x34200, 0x34318,
2089                 0x34400, 0x3452c,
2090                 0x34540, 0x3461c,
2091                 0x34800, 0x34834,
2092                 0x348c0, 0x34908,
2093                 0x34910, 0x349ac,
2094                 0x34a00, 0x34a04,
2095                 0x34a0c, 0x34a2c,
2096                 0x34a44, 0x34a50,
2097                 0x34a74, 0x34c24,
2098                 0x34d08, 0x34d14,
2099                 0x34d1c, 0x34d20,
2100                 0x34d3c, 0x34d50,
2101                 0x35200, 0x3520c,
2102                 0x35220, 0x35220,
2103                 0x35240, 0x35240,
2104                 0x35600, 0x35600,
2105                 0x35608, 0x3560c,
2106                 0x35a00, 0x35a1c,
2107                 0x35e04, 0x35e20,
2108                 0x35e38, 0x35e3c,
2109                 0x35e80, 0x35e80,
2110                 0x35e88, 0x35ea8,
2111                 0x35eb0, 0x35eb4,
2112                 0x35ec8, 0x35ed4,
2113                 0x35fb8, 0x36004,
2114                 0x36208, 0x3623c,
2115                 0x36600, 0x36630,
2116                 0x36a00, 0x36abc,
2117                 0x36b00, 0x36b70,
2118                 0x37000, 0x37048,
2119                 0x37060, 0x3709c,
2120                 0x370f0, 0x37148,
2121                 0x37160, 0x3719c,
2122                 0x371f0, 0x372e4,
2123                 0x372f8, 0x373e4,
2124                 0x373f8, 0x37448,
2125                 0x37460, 0x3749c,
2126                 0x374f0, 0x37548,
2127                 0x37560, 0x3759c,
2128                 0x375f0, 0x376e4,
2129                 0x376f8, 0x377e4,
2130                 0x377f8, 0x377fc,
2131                 0x37814, 0x37814,
2132                 0x3782c, 0x3782c,
2133                 0x37880, 0x3788c,
2134                 0x378e8, 0x378ec,
2135                 0x37900, 0x37948,
2136                 0x37960, 0x3799c,
2137                 0x379f0, 0x37ae4,
2138                 0x37af8, 0x37b10,
2139                 0x37b28, 0x37b28,
2140                 0x37b3c, 0x37b50,
2141                 0x37bf0, 0x37c10,
2142                 0x37c28, 0x37c28,
2143                 0x37c3c, 0x37c50,
2144                 0x37cf0, 0x37cfc,
2145                 0x38000, 0x38030,
2146                 0x38100, 0x38144,
2147                 0x38190, 0x381d0,
2148                 0x38200, 0x38318,
2149                 0x38400, 0x3852c,
2150                 0x38540, 0x3861c,
2151                 0x38800, 0x38834,
2152                 0x388c0, 0x38908,
2153                 0x38910, 0x389ac,
2154                 0x38a00, 0x38a04,
2155                 0x38a0c, 0x38a2c,
2156                 0x38a44, 0x38a50,
2157                 0x38a74, 0x38c24,
2158                 0x38d08, 0x38d14,
2159                 0x38d1c, 0x38d20,
2160                 0x38d3c, 0x38d50,
2161                 0x39200, 0x3920c,
2162                 0x39220, 0x39220,
2163                 0x39240, 0x39240,
2164                 0x39600, 0x39600,
2165                 0x39608, 0x3960c,
2166                 0x39a00, 0x39a1c,
2167                 0x39e04, 0x39e20,
2168                 0x39e38, 0x39e3c,
2169                 0x39e80, 0x39e80,
2170                 0x39e88, 0x39ea8,
2171                 0x39eb0, 0x39eb4,
2172                 0x39ec8, 0x39ed4,
2173                 0x39fb8, 0x3a004,
2174                 0x3a208, 0x3a23c,
2175                 0x3a600, 0x3a630,
2176                 0x3aa00, 0x3aabc,
2177                 0x3ab00, 0x3ab70,
2178                 0x3b000, 0x3b048,
2179                 0x3b060, 0x3b09c,
2180                 0x3b0f0, 0x3b148,
2181                 0x3b160, 0x3b19c,
2182                 0x3b1f0, 0x3b2e4,
2183                 0x3b2f8, 0x3b3e4,
2184                 0x3b3f8, 0x3b448,
2185                 0x3b460, 0x3b49c,
2186                 0x3b4f0, 0x3b548,
2187                 0x3b560, 0x3b59c,
2188                 0x3b5f0, 0x3b6e4,
2189                 0x3b6f8, 0x3b7e4,
2190                 0x3b7f8, 0x3b7fc,
2191                 0x3b814, 0x3b814,
2192                 0x3b82c, 0x3b82c,
2193                 0x3b880, 0x3b88c,
2194                 0x3b8e8, 0x3b8ec,
2195                 0x3b900, 0x3b948,
2196                 0x3b960, 0x3b99c,
2197                 0x3b9f0, 0x3bae4,
2198                 0x3baf8, 0x3bb10,
2199                 0x3bb28, 0x3bb28,
2200                 0x3bb3c, 0x3bb50,
2201                 0x3bbf0, 0x3bc10,
2202                 0x3bc28, 0x3bc28,
2203                 0x3bc3c, 0x3bc50,
2204                 0x3bcf0, 0x3bcfc,
2205                 0x3c000, 0x3c030,
2206                 0x3c100, 0x3c144,
2207                 0x3c190, 0x3c1d0,
2208                 0x3c200, 0x3c318,
2209                 0x3c400, 0x3c52c,
2210                 0x3c540, 0x3c61c,
2211                 0x3c800, 0x3c834,
2212                 0x3c8c0, 0x3c908,
2213                 0x3c910, 0x3c9ac,
2214                 0x3ca00, 0x3ca04,
2215                 0x3ca0c, 0x3ca2c,
2216                 0x3ca44, 0x3ca50,
2217                 0x3ca74, 0x3cc24,
2218                 0x3cd08, 0x3cd14,
2219                 0x3cd1c, 0x3cd20,
2220                 0x3cd3c, 0x3cd50,
2221                 0x3d200, 0x3d20c,
2222                 0x3d220, 0x3d220,
2223                 0x3d240, 0x3d240,
2224                 0x3d600, 0x3d600,
2225                 0x3d608, 0x3d60c,
2226                 0x3da00, 0x3da1c,
2227                 0x3de04, 0x3de20,
2228                 0x3de38, 0x3de3c,
2229                 0x3de80, 0x3de80,
2230                 0x3de88, 0x3dea8,
2231                 0x3deb0, 0x3deb4,
2232                 0x3dec8, 0x3ded4,
2233                 0x3dfb8, 0x3e004,
2234                 0x3e208, 0x3e23c,
2235                 0x3e600, 0x3e630,
2236                 0x3ea00, 0x3eabc,
2237                 0x3eb00, 0x3eb70,
2238                 0x3f000, 0x3f048,
2239                 0x3f060, 0x3f09c,
2240                 0x3f0f0, 0x3f148,
2241                 0x3f160, 0x3f19c,
2242                 0x3f1f0, 0x3f2e4,
2243                 0x3f2f8, 0x3f3e4,
2244                 0x3f3f8, 0x3f448,
2245                 0x3f460, 0x3f49c,
2246                 0x3f4f0, 0x3f548,
2247                 0x3f560, 0x3f59c,
2248                 0x3f5f0, 0x3f6e4,
2249                 0x3f6f8, 0x3f7e4,
2250                 0x3f7f8, 0x3f7fc,
2251                 0x3f814, 0x3f814,
2252                 0x3f82c, 0x3f82c,
2253                 0x3f880, 0x3f88c,
2254                 0x3f8e8, 0x3f8ec,
2255                 0x3f900, 0x3f948,
2256                 0x3f960, 0x3f99c,
2257                 0x3f9f0, 0x3fae4,
2258                 0x3faf8, 0x3fb10,
2259                 0x3fb28, 0x3fb28,
2260                 0x3fb3c, 0x3fb50,
2261                 0x3fbf0, 0x3fc10,
2262                 0x3fc28, 0x3fc28,
2263                 0x3fc3c, 0x3fc50,
2264                 0x3fcf0, 0x3fcfc,
2265                 0x40000, 0x4000c,
2266                 0x40040, 0x40068,
2267                 0x40080, 0x40144,
2268                 0x40180, 0x4018c,
2269                 0x40200, 0x40298,
2270                 0x402ac, 0x4033c,
2271                 0x403f8, 0x403fc,
2272                 0x41304, 0x413c4,
2273                 0x41400, 0x4141c,
2274                 0x41480, 0x414d0,
2275                 0x44000, 0x44078,
2276                 0x440c0, 0x44278,
2277                 0x442c0, 0x44478,
2278                 0x444c0, 0x44678,
2279                 0x446c0, 0x44878,
2280                 0x448c0, 0x449fc,
2281                 0x45000, 0x45068,
2282                 0x45080, 0x45084,
2283                 0x450a0, 0x450b0,
2284                 0x45200, 0x45268,
2285                 0x45280, 0x45284,
2286                 0x452a0, 0x452b0,
2287                 0x460c0, 0x460e4,
2288                 0x47000, 0x4708c,
2289                 0x47200, 0x47250,
2290                 0x47400, 0x47420,
2291                 0x47600, 0x47618,
2292                 0x47800, 0x47814,
2293                 0x48000, 0x4800c,
2294                 0x48040, 0x48068,
2295                 0x48080, 0x48144,
2296                 0x48180, 0x4818c,
2297                 0x48200, 0x48298,
2298                 0x482ac, 0x4833c,
2299                 0x483f8, 0x483fc,
2300                 0x49304, 0x493c4,
2301                 0x49400, 0x4941c,
2302                 0x49480, 0x494d0,
2303                 0x4c000, 0x4c078,
2304                 0x4c0c0, 0x4c278,
2305                 0x4c2c0, 0x4c478,
2306                 0x4c4c0, 0x4c678,
2307                 0x4c6c0, 0x4c878,
2308                 0x4c8c0, 0x4c9fc,
2309                 0x4d000, 0x4d068,
2310                 0x4d080, 0x4d084,
2311                 0x4d0a0, 0x4d0b0,
2312                 0x4d200, 0x4d268,
2313                 0x4d280, 0x4d284,
2314                 0x4d2a0, 0x4d2b0,
2315                 0x4e0c0, 0x4e0e4,
2316                 0x4f000, 0x4f08c,
2317                 0x4f200, 0x4f250,
2318                 0x4f400, 0x4f420,
2319                 0x4f600, 0x4f618,
2320                 0x4f800, 0x4f814,
2321                 0x50000, 0x500cc,
2322                 0x50400, 0x50400,
2323                 0x50800, 0x508cc,
2324                 0x50c00, 0x50c00,
2325                 0x51000, 0x5101c,
2326                 0x51300, 0x51308,
2327         };
2328
2329         int i;
2330         struct adapter *ap = netdev2adap(dev);
2331         static const unsigned int *reg_ranges;
2332         int arr_size = 0, buf_size = 0;
2333
2334         if (is_t4(ap->params.chip)) {
2335                 reg_ranges = &t4_reg_ranges[0];
2336                 arr_size = ARRAY_SIZE(t4_reg_ranges);
2337                 buf_size = T4_REGMAP_SIZE;
2338         } else {
2339                 reg_ranges = &t5_reg_ranges[0];
2340                 arr_size = ARRAY_SIZE(t5_reg_ranges);
2341                 buf_size = T5_REGMAP_SIZE;
2342         }
2343
2344         regs->version = mk_adap_vers(ap);
2345
2346         memset(buf, 0, buf_size);
2347         for (i = 0; i < arr_size; i += 2)
2348                 reg_block_dump(ap, buf, reg_ranges[i], reg_ranges[i + 1]);
2349 }
2350
2351 static int restart_autoneg(struct net_device *dev)
2352 {
2353         struct port_info *p = netdev_priv(dev);
2354
2355         if (!netif_running(dev))
2356                 return -EAGAIN;
2357         if (p->link_cfg.autoneg != AUTONEG_ENABLE)
2358                 return -EINVAL;
2359         t4_restart_aneg(p->adapter, p->adapter->fn, p->tx_chan);
2360         return 0;
2361 }
2362
2363 static int identify_port(struct net_device *dev,
2364                          enum ethtool_phys_id_state state)
2365 {
2366         unsigned int val;
2367         struct adapter *adap = netdev2adap(dev);
2368
2369         if (state == ETHTOOL_ID_ACTIVE)
2370                 val = 0xffff;
2371         else if (state == ETHTOOL_ID_INACTIVE)
2372                 val = 0;
2373         else
2374                 return -EINVAL;
2375
2376         return t4_identify_port(adap, adap->fn, netdev2pinfo(dev)->viid, val);
2377 }
2378
2379 static unsigned int from_fw_linkcaps(unsigned int type, unsigned int caps)
2380 {
2381         unsigned int v = 0;
2382
2383         if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
2384             type == FW_PORT_TYPE_BT_XAUI) {
2385                 v |= SUPPORTED_TP;
2386                 if (caps & FW_PORT_CAP_SPEED_100M)
2387                         v |= SUPPORTED_100baseT_Full;
2388                 if (caps & FW_PORT_CAP_SPEED_1G)
2389                         v |= SUPPORTED_1000baseT_Full;
2390                 if (caps & FW_PORT_CAP_SPEED_10G)
2391                         v |= SUPPORTED_10000baseT_Full;
2392         } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
2393                 v |= SUPPORTED_Backplane;
2394                 if (caps & FW_PORT_CAP_SPEED_1G)
2395                         v |= SUPPORTED_1000baseKX_Full;
2396                 if (caps & FW_PORT_CAP_SPEED_10G)
2397                         v |= SUPPORTED_10000baseKX4_Full;
2398         } else if (type == FW_PORT_TYPE_KR)
2399                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
2400         else if (type == FW_PORT_TYPE_BP_AP)
2401                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2402                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
2403         else if (type == FW_PORT_TYPE_BP4_AP)
2404                 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
2405                      SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
2406                      SUPPORTED_10000baseKX4_Full;
2407         else if (type == FW_PORT_TYPE_FIBER_XFI ||
2408                  type == FW_PORT_TYPE_FIBER_XAUI || type == FW_PORT_TYPE_SFP)
2409                 v |= SUPPORTED_FIBRE;
2410         else if (type == FW_PORT_TYPE_BP40_BA)
2411                 v |= SUPPORTED_40000baseSR4_Full;
2412
2413         if (caps & FW_PORT_CAP_ANEG)
2414                 v |= SUPPORTED_Autoneg;
2415         return v;
2416 }
2417
2418 static unsigned int to_fw_linkcaps(unsigned int caps)
2419 {
2420         unsigned int v = 0;
2421
2422         if (caps & ADVERTISED_100baseT_Full)
2423                 v |= FW_PORT_CAP_SPEED_100M;
2424         if (caps & ADVERTISED_1000baseT_Full)
2425                 v |= FW_PORT_CAP_SPEED_1G;
2426         if (caps & ADVERTISED_10000baseT_Full)
2427                 v |= FW_PORT_CAP_SPEED_10G;
2428         if (caps & ADVERTISED_40000baseSR4_Full)
2429                 v |= FW_PORT_CAP_SPEED_40G;
2430         return v;
2431 }
2432
2433 static int get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2434 {
2435         const struct port_info *p = netdev_priv(dev);
2436
2437         if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
2438             p->port_type == FW_PORT_TYPE_BT_XFI ||
2439             p->port_type == FW_PORT_TYPE_BT_XAUI)
2440                 cmd->port = PORT_TP;
2441         else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
2442                  p->port_type == FW_PORT_TYPE_FIBER_XAUI)
2443                 cmd->port = PORT_FIBRE;
2444         else if (p->port_type == FW_PORT_TYPE_SFP ||
2445                  p->port_type == FW_PORT_TYPE_QSFP_10G ||
2446                  p->port_type == FW_PORT_TYPE_QSFP) {
2447                 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
2448                     p->mod_type == FW_PORT_MOD_TYPE_SR ||
2449                     p->mod_type == FW_PORT_MOD_TYPE_ER ||
2450                     p->mod_type == FW_PORT_MOD_TYPE_LRM)
2451                         cmd->port = PORT_FIBRE;
2452                 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
2453                          p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
2454                         cmd->port = PORT_DA;
2455                 else
2456                         cmd->port = PORT_OTHER;
2457         } else
2458                 cmd->port = PORT_OTHER;
2459
2460         if (p->mdio_addr >= 0) {
2461                 cmd->phy_address = p->mdio_addr;
2462                 cmd->transceiver = XCVR_EXTERNAL;
2463                 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
2464                         MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
2465         } else {
2466                 cmd->phy_address = 0;  /* not really, but no better option */
2467                 cmd->transceiver = XCVR_INTERNAL;
2468                 cmd->mdio_support = 0;
2469         }
2470
2471         cmd->supported = from_fw_linkcaps(p->port_type, p->link_cfg.supported);
2472         cmd->advertising = from_fw_linkcaps(p->port_type,
2473                                             p->link_cfg.advertising);
2474         ethtool_cmd_speed_set(cmd,
2475                               netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
2476         cmd->duplex = DUPLEX_FULL;
2477         cmd->autoneg = p->link_cfg.autoneg;
2478         cmd->maxtxpkt = 0;
2479         cmd->maxrxpkt = 0;
2480         return 0;
2481 }
2482
2483 static unsigned int speed_to_caps(int speed)
2484 {
2485         if (speed == 100)
2486                 return FW_PORT_CAP_SPEED_100M;
2487         if (speed == 1000)
2488                 return FW_PORT_CAP_SPEED_1G;
2489         if (speed == 10000)
2490                 return FW_PORT_CAP_SPEED_10G;
2491         if (speed == 40000)
2492                 return FW_PORT_CAP_SPEED_40G;
2493         return 0;
2494 }
2495
2496 static int set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2497 {
2498         unsigned int cap;
2499         struct port_info *p = netdev_priv(dev);
2500         struct link_config *lc = &p->link_cfg;
2501         u32 speed = ethtool_cmd_speed(cmd);
2502
2503         if (cmd->duplex != DUPLEX_FULL)     /* only full-duplex supported */
2504                 return -EINVAL;
2505
2506         if (!(lc->supported & FW_PORT_CAP_ANEG)) {
2507                 /*
2508                  * PHY offers a single speed.  See if that's what's
2509                  * being requested.
2510                  */
2511                 if (cmd->autoneg == AUTONEG_DISABLE &&
2512                     (lc->supported & speed_to_caps(speed)))
2513                         return 0;
2514                 return -EINVAL;
2515         }
2516
2517         if (cmd->autoneg == AUTONEG_DISABLE) {
2518                 cap = speed_to_caps(speed);
2519
2520                 if (!(lc->supported & cap) ||
2521                     (speed == 1000) ||
2522                     (speed == 10000) ||
2523                     (speed == 40000))
2524                         return -EINVAL;
2525                 lc->requested_speed = cap;
2526                 lc->advertising = 0;
2527         } else {
2528                 cap = to_fw_linkcaps(cmd->advertising);
2529                 if (!(lc->supported & cap))
2530                         return -EINVAL;
2531                 lc->requested_speed = 0;
2532                 lc->advertising = cap | FW_PORT_CAP_ANEG;
2533         }
2534         lc->autoneg = cmd->autoneg;
2535
2536         if (netif_running(dev))
2537                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2538                                      lc);
2539         return 0;
2540 }
2541
2542 static void get_pauseparam(struct net_device *dev,
2543                            struct ethtool_pauseparam *epause)
2544 {
2545         struct port_info *p = netdev_priv(dev);
2546
2547         epause->autoneg = (p->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
2548         epause->rx_pause = (p->link_cfg.fc & PAUSE_RX) != 0;
2549         epause->tx_pause = (p->link_cfg.fc & PAUSE_TX) != 0;
2550 }
2551
2552 static int set_pauseparam(struct net_device *dev,
2553                           struct ethtool_pauseparam *epause)
2554 {
2555         struct port_info *p = netdev_priv(dev);
2556         struct link_config *lc = &p->link_cfg;
2557
2558         if (epause->autoneg == AUTONEG_DISABLE)
2559                 lc->requested_fc = 0;
2560         else if (lc->supported & FW_PORT_CAP_ANEG)
2561                 lc->requested_fc = PAUSE_AUTONEG;
2562         else
2563                 return -EINVAL;
2564
2565         if (epause->rx_pause)
2566                 lc->requested_fc |= PAUSE_RX;
2567         if (epause->tx_pause)
2568                 lc->requested_fc |= PAUSE_TX;
2569         if (netif_running(dev))
2570                 return t4_link_start(p->adapter, p->adapter->fn, p->tx_chan,
2571                                      lc);
2572         return 0;
2573 }
2574
2575 static void get_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2576 {
2577         const struct port_info *pi = netdev_priv(dev);
2578         const struct sge *s = &pi->adapter->sge;
2579
2580         e->rx_max_pending = MAX_RX_BUFFERS;
2581         e->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
2582         e->rx_jumbo_max_pending = 0;
2583         e->tx_max_pending = MAX_TXQ_ENTRIES;
2584
2585         e->rx_pending = s->ethrxq[pi->first_qset].fl.size - 8;
2586         e->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
2587         e->rx_jumbo_pending = 0;
2588         e->tx_pending = s->ethtxq[pi->first_qset].q.size;
2589 }
2590
2591 static int set_sge_param(struct net_device *dev, struct ethtool_ringparam *e)
2592 {
2593         int i;
2594         const struct port_info *pi = netdev_priv(dev);
2595         struct adapter *adapter = pi->adapter;
2596         struct sge *s = &adapter->sge;
2597
2598         if (e->rx_pending > MAX_RX_BUFFERS || e->rx_jumbo_pending ||
2599             e->tx_pending > MAX_TXQ_ENTRIES ||
2600             e->rx_mini_pending > MAX_RSPQ_ENTRIES ||
2601             e->rx_mini_pending < MIN_RSPQ_ENTRIES ||
2602             e->rx_pending < MIN_FL_ENTRIES || e->tx_pending < MIN_TXQ_ENTRIES)
2603                 return -EINVAL;
2604
2605         if (adapter->flags & FULL_INIT_DONE)
2606                 return -EBUSY;
2607
2608         for (i = 0; i < pi->nqsets; ++i) {
2609                 s->ethtxq[pi->first_qset + i].q.size = e->tx_pending;
2610                 s->ethrxq[pi->first_qset + i].fl.size = e->rx_pending + 8;
2611                 s->ethrxq[pi->first_qset + i].rspq.size = e->rx_mini_pending;
2612         }
2613         return 0;
2614 }
2615
2616 static int closest_timer(const struct sge *s, int time)
2617 {
2618         int i, delta, match = 0, min_delta = INT_MAX;
2619
2620         for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
2621                 delta = time - s->timer_val[i];
2622                 if (delta < 0)
2623                         delta = -delta;
2624                 if (delta < min_delta) {
2625                         min_delta = delta;
2626                         match = i;
2627                 }
2628         }
2629         return match;
2630 }
2631
2632 static int closest_thres(const struct sge *s, int thres)
2633 {
2634         int i, delta, match = 0, min_delta = INT_MAX;
2635
2636         for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
2637                 delta = thres - s->counter_val[i];
2638                 if (delta < 0)
2639                         delta = -delta;
2640                 if (delta < min_delta) {
2641                         min_delta = delta;
2642                         match = i;
2643                 }
2644         }
2645         return match;
2646 }
2647
2648 /*
2649  * Return a queue's interrupt hold-off time in us.  0 means no timer.
2650  */
2651 static unsigned int qtimer_val(const struct adapter *adap,
2652                                const struct sge_rspq *q)
2653 {
2654         unsigned int idx = q->intr_params >> 1;
2655
2656         return idx < SGE_NTIMERS ? adap->sge.timer_val[idx] : 0;
2657 }
2658
2659 /**
2660  *      set_rspq_intr_params - set a queue's interrupt holdoff parameters
2661  *      @q: the Rx queue
2662  *      @us: the hold-off time in us, or 0 to disable timer
2663  *      @cnt: the hold-off packet count, or 0 to disable counter
2664  *
2665  *      Sets an Rx queue's interrupt hold-off time and packet count.  At least
2666  *      one of the two needs to be enabled for the queue to generate interrupts.
2667  */
2668 static int set_rspq_intr_params(struct sge_rspq *q,
2669                                 unsigned int us, unsigned int cnt)
2670 {
2671         struct adapter *adap = q->adap;
2672
2673         if ((us | cnt) == 0)
2674                 cnt = 1;
2675
2676         if (cnt) {
2677                 int err;
2678                 u32 v, new_idx;
2679
2680                 new_idx = closest_thres(&adap->sge, cnt);
2681                 if (q->desc && q->pktcnt_idx != new_idx) {
2682                         /* the queue has already been created, update it */
2683                         v = FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2684                             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
2685                             FW_PARAMS_PARAM_YZ(q->cntxt_id);
2686                         err = t4_set_params(adap, adap->fn, adap->fn, 0, 1, &v,
2687                                             &new_idx);
2688                         if (err)
2689                                 return err;
2690                 }
2691                 q->pktcnt_idx = new_idx;
2692         }
2693
2694         us = us == 0 ? 6 : closest_timer(&adap->sge, us);
2695         q->intr_params = QINTR_TIMER_IDX(us) | (cnt > 0 ? QINTR_CNT_EN : 0);
2696         return 0;
2697 }
2698
2699 /**
2700  * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2701  * @dev: the network device
2702  * @us: the hold-off time in us, or 0 to disable timer
2703  * @cnt: the hold-off packet count, or 0 to disable counter
2704  *
2705  * Set the RX interrupt hold-off parameters for a network device.
2706  */
2707 static int set_rx_intr_params(struct net_device *dev,
2708                               unsigned int us, unsigned int cnt)
2709 {
2710         int i, err;
2711         struct port_info *pi = netdev_priv(dev);
2712         struct adapter *adap = pi->adapter;
2713         struct sge_eth_rxq *q = &adap->sge.ethrxq[pi->first_qset];
2714
2715         for (i = 0; i < pi->nqsets; i++, q++) {
2716                 err = set_rspq_intr_params(&q->rspq, us, cnt);
2717                 if (err)
2718                         return err;
2719         }
2720         return 0;
2721 }
2722
2723 static int set_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2724 {
2725         return set_rx_intr_params(dev, c->rx_coalesce_usecs,
2726                                   c->rx_max_coalesced_frames);
2727 }
2728
2729 static int get_coalesce(struct net_device *dev, struct ethtool_coalesce *c)
2730 {
2731         const struct port_info *pi = netdev_priv(dev);
2732         const struct adapter *adap = pi->adapter;
2733         const struct sge_rspq *rq = &adap->sge.ethrxq[pi->first_qset].rspq;
2734
2735         c->rx_coalesce_usecs = qtimer_val(adap, rq);
2736         c->rx_max_coalesced_frames = (rq->intr_params & QINTR_CNT_EN) ?
2737                 adap->sge.counter_val[rq->pktcnt_idx] : 0;
2738         return 0;
2739 }
2740
2741 /**
2742  *      eeprom_ptov - translate a physical EEPROM address to virtual
2743  *      @phys_addr: the physical EEPROM address
2744  *      @fn: the PCI function number
2745  *      @sz: size of function-specific area
2746  *
2747  *      Translate a physical EEPROM address to virtual.  The first 1K is
2748  *      accessed through virtual addresses starting at 31K, the rest is
2749  *      accessed through virtual addresses starting at 0.
2750  *
2751  *      The mapping is as follows:
2752  *      [0..1K) -> [31K..32K)
2753  *      [1K..1K+A) -> [31K-A..31K)
2754  *      [1K+A..ES) -> [0..ES-A-1K)
2755  *
2756  *      where A = @fn * @sz, and ES = EEPROM size.
2757  */
2758 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2759 {
2760         fn *= sz;
2761         if (phys_addr < 1024)
2762                 return phys_addr + (31 << 10);
2763         if (phys_addr < 1024 + fn)
2764                 return 31744 - fn + phys_addr - 1024;
2765         if (phys_addr < EEPROMSIZE)
2766                 return phys_addr - 1024 - fn;
2767         return -EINVAL;
2768 }
2769
2770 /*
2771  * The next two routines implement eeprom read/write from physical addresses.
2772  */
2773 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v)
2774 {
2775         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2776
2777         if (vaddr >= 0)
2778                 vaddr = pci_read_vpd(adap->pdev, vaddr, sizeof(u32), v);
2779         return vaddr < 0 ? vaddr : 0;
2780 }
2781
2782 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v)
2783 {
2784         int vaddr = eeprom_ptov(phys_addr, adap->fn, EEPROMPFSIZE);
2785
2786         if (vaddr >= 0)
2787                 vaddr = pci_write_vpd(adap->pdev, vaddr, sizeof(u32), &v);
2788         return vaddr < 0 ? vaddr : 0;
2789 }
2790
2791 #define EEPROM_MAGIC 0x38E2F10C
2792
2793 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *e,
2794                       u8 *data)
2795 {
2796         int i, err = 0;
2797         struct adapter *adapter = netdev2adap(dev);
2798
2799         u8 *buf = kmalloc(EEPROMSIZE, GFP_KERNEL);
2800         if (!buf)
2801                 return -ENOMEM;
2802
2803         e->magic = EEPROM_MAGIC;
2804         for (i = e->offset & ~3; !err && i < e->offset + e->len; i += 4)
2805                 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]);
2806
2807         if (!err)
2808                 memcpy(data, buf + e->offset, e->len);
2809         kfree(buf);
2810         return err;
2811 }
2812
2813 static int set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
2814                       u8 *data)
2815 {
2816         u8 *buf;
2817         int err = 0;
2818         u32 aligned_offset, aligned_len, *p;
2819         struct adapter *adapter = netdev2adap(dev);
2820
2821         if (eeprom->magic != EEPROM_MAGIC)
2822                 return -EINVAL;
2823
2824         aligned_offset = eeprom->offset & ~3;
2825         aligned_len = (eeprom->len + (eeprom->offset & 3) + 3) & ~3;
2826
2827         if (adapter->fn > 0) {
2828                 u32 start = 1024 + adapter->fn * EEPROMPFSIZE;
2829
2830                 if (aligned_offset < start ||
2831                     aligned_offset + aligned_len > start + EEPROMPFSIZE)
2832                         return -EPERM;
2833         }
2834
2835         if (aligned_offset != eeprom->offset || aligned_len != eeprom->len) {
2836                 /*
2837                  * RMW possibly needed for first or last words.
2838                  */
2839                 buf = kmalloc(aligned_len, GFP_KERNEL);
2840                 if (!buf)
2841                         return -ENOMEM;
2842                 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf);
2843                 if (!err && aligned_len > 4)
2844                         err = eeprom_rd_phys(adapter,
2845                                              aligned_offset + aligned_len - 4,
2846                                              (u32 *)&buf[aligned_len - 4]);
2847                 if (err)
2848                         goto out;
2849                 memcpy(buf + (eeprom->offset & 3), data, eeprom->len);
2850         } else
2851                 buf = data;
2852
2853         err = t4_seeprom_wp(adapter, false);
2854         if (err)
2855                 goto out;
2856
2857         for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2858                 err = eeprom_wr_phys(adapter, aligned_offset, *p);
2859                 aligned_offset += 4;
2860         }
2861
2862         if (!err)
2863                 err = t4_seeprom_wp(adapter, true);
2864 out:
2865         if (buf != data)
2866                 kfree(buf);
2867         return err;
2868 }
2869
2870 static int set_flash(struct net_device *netdev, struct ethtool_flash *ef)
2871 {
2872         int ret;
2873         const struct firmware *fw;
2874         struct adapter *adap = netdev2adap(netdev);
2875
2876         ef->data[sizeof(ef->data) - 1] = '\0';
2877         ret = request_firmware(&fw, ef->data, adap->pdev_dev);
2878         if (ret < 0)
2879                 return ret;
2880
2881         ret = t4_load_fw(adap, fw->data, fw->size);
2882         release_firmware(fw);
2883         if (!ret)
2884                 dev_info(adap->pdev_dev, "loaded firmware %s\n", ef->data);
2885         return ret;
2886 }
2887
2888 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2889 #define BCAST_CRC 0xa0ccc1a6
2890
2891 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2892 {
2893         wol->supported = WAKE_BCAST | WAKE_MAGIC;
2894         wol->wolopts = netdev2adap(dev)->wol;
2895         memset(&wol->sopass, 0, sizeof(wol->sopass));
2896 }
2897
2898 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2899 {
2900         int err = 0;
2901         struct port_info *pi = netdev_priv(dev);
2902
2903         if (wol->wolopts & ~WOL_SUPPORTED)
2904                 return -EINVAL;
2905         t4_wol_magic_enable(pi->adapter, pi->tx_chan,
2906                             (wol->wolopts & WAKE_MAGIC) ? dev->dev_addr : NULL);
2907         if (wol->wolopts & WAKE_BCAST) {
2908                 err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0xfe, ~0ULL,
2909                                         ~0ULL, 0, false);
2910                 if (!err)
2911                         err = t4_wol_pat_enable(pi->adapter, pi->tx_chan, 1,
2912                                                 ~6ULL, ~0ULL, BCAST_CRC, true);
2913         } else
2914                 t4_wol_pat_enable(pi->adapter, pi->tx_chan, 0, 0, 0, 0, false);
2915         return err;
2916 }
2917
2918 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
2919 {
2920         const struct port_info *pi = netdev_priv(dev);
2921         netdev_features_t changed = dev->features ^ features;
2922         int err;
2923
2924         if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
2925                 return 0;
2926
2927         err = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, -1,
2928                             -1, -1, -1,
2929                             !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
2930         if (unlikely(err))
2931                 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
2932         return err;
2933 }
2934
2935 static u32 get_rss_table_size(struct net_device *dev)
2936 {
2937         const struct port_info *pi = netdev_priv(dev);
2938
2939         return pi->rss_size;
2940 }
2941
2942 static int get_rss_table(struct net_device *dev, u32 *p, u8 *key)
2943 {
2944         const struct port_info *pi = netdev_priv(dev);
2945         unsigned int n = pi->rss_size;
2946
2947         while (n--)
2948                 p[n] = pi->rss[n];
2949         return 0;
2950 }
2951
2952 static int set_rss_table(struct net_device *dev, const u32 *p, const u8 *key)
2953 {
2954         unsigned int i;
2955         struct port_info *pi = netdev_priv(dev);
2956
2957         for (i = 0; i < pi->rss_size; i++)
2958                 pi->rss[i] = p[i];
2959         if (pi->adapter->flags & FULL_INIT_DONE)
2960                 return write_rss(pi, pi->rss);
2961         return 0;
2962 }
2963
2964 static int get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
2965                      u32 *rules)
2966 {
2967         const struct port_info *pi = netdev_priv(dev);
2968
2969         switch (info->cmd) {
2970         case ETHTOOL_GRXFH: {
2971                 unsigned int v = pi->rss_mode;
2972
2973                 info->data = 0;
2974                 switch (info->flow_type) {
2975                 case TCP_V4_FLOW:
2976                         if (v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
2977                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2978                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2979                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2980                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2981                         break;
2982                 case UDP_V4_FLOW:
2983                         if ((v & FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) &&
2984                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
2985                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2986                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
2987                         else if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2988                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2989                         break;
2990                 case SCTP_V4_FLOW:
2991                 case AH_ESP_V4_FLOW:
2992                 case IPV4_FLOW:
2993                         if (v & FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
2994                                 info->data = RXH_IP_SRC | RXH_IP_DST;
2995                         break;
2996                 case TCP_V6_FLOW:
2997                         if (v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
2998                                 info->data = RXH_IP_SRC | RXH_IP_DST |
2999                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3000                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3001                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3002                         break;
3003                 case UDP_V6_FLOW:
3004                         if ((v & FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) &&
3005                             (v & FW_RSS_VI_CONFIG_CMD_UDPEN))
3006                                 info->data = RXH_IP_SRC | RXH_IP_DST |
3007                                              RXH_L4_B_0_1 | RXH_L4_B_2_3;
3008                         else if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3009                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3010                         break;
3011                 case SCTP_V6_FLOW:
3012                 case AH_ESP_V6_FLOW:
3013                 case IPV6_FLOW:
3014                         if (v & FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3015                                 info->data = RXH_IP_SRC | RXH_IP_DST;
3016                         break;
3017                 }
3018                 return 0;
3019         }
3020         case ETHTOOL_GRXRINGS:
3021                 info->data = pi->nqsets;
3022                 return 0;
3023         }
3024         return -EOPNOTSUPP;
3025 }
3026
3027 static const struct ethtool_ops cxgb_ethtool_ops = {
3028         .get_settings      = get_settings,
3029         .set_settings      = set_settings,
3030         .get_drvinfo       = get_drvinfo,
3031         .get_msglevel      = get_msglevel,
3032         .set_msglevel      = set_msglevel,
3033         .get_ringparam     = get_sge_param,
3034         .set_ringparam     = set_sge_param,
3035         .get_coalesce      = get_coalesce,
3036         .set_coalesce      = set_coalesce,
3037         .get_eeprom_len    = get_eeprom_len,
3038         .get_eeprom        = get_eeprom,
3039         .set_eeprom        = set_eeprom,
3040         .get_pauseparam    = get_pauseparam,
3041         .set_pauseparam    = set_pauseparam,
3042         .get_link          = ethtool_op_get_link,
3043         .get_strings       = get_strings,
3044         .set_phys_id       = identify_port,
3045         .nway_reset        = restart_autoneg,
3046         .get_sset_count    = get_sset_count,
3047         .get_ethtool_stats = get_stats,
3048         .get_regs_len      = get_regs_len,
3049         .get_regs          = get_regs,
3050         .get_wol           = get_wol,
3051         .set_wol           = set_wol,
3052         .get_rxnfc         = get_rxnfc,
3053         .get_rxfh_indir_size = get_rss_table_size,
3054         .get_rxfh          = get_rss_table,
3055         .set_rxfh          = set_rss_table,
3056         .flash_device      = set_flash,
3057 };
3058
3059 /*
3060  * debugfs support
3061  */
3062 static ssize_t mem_read(struct file *file, char __user *buf, size_t count,
3063                         loff_t *ppos)
3064 {
3065         loff_t pos = *ppos;
3066         loff_t avail = file_inode(file)->i_size;
3067         unsigned int mem = (uintptr_t)file->private_data & 3;
3068         struct adapter *adap = file->private_data - mem;
3069
3070         if (pos < 0)
3071                 return -EINVAL;
3072         if (pos >= avail)
3073                 return 0;
3074         if (count > avail - pos)
3075                 count = avail - pos;
3076
3077         while (count) {
3078                 size_t len;
3079                 int ret, ofst;
3080                 __be32 data[16];
3081
3082                 if ((mem == MEM_MC) || (mem == MEM_MC1))
3083                         ret = t4_mc_read(adap, mem % MEM_MC, pos, data, NULL);
3084                 else
3085                         ret = t4_edc_read(adap, mem, pos, data, NULL);
3086                 if (ret)
3087                         return ret;
3088
3089                 ofst = pos % sizeof(data);
3090                 len = min(count, sizeof(data) - ofst);
3091                 if (copy_to_user(buf, (u8 *)data + ofst, len))
3092                         return -EFAULT;
3093
3094                 buf += len;
3095                 pos += len;
3096                 count -= len;
3097         }
3098         count = pos - *ppos;
3099         *ppos = pos;
3100         return count;
3101 }
3102
3103 static const struct file_operations mem_debugfs_fops = {
3104         .owner   = THIS_MODULE,
3105         .open    = simple_open,
3106         .read    = mem_read,
3107         .llseek  = default_llseek,
3108 };
3109
3110 static void add_debugfs_mem(struct adapter *adap, const char *name,
3111                             unsigned int idx, unsigned int size_mb)
3112 {
3113         struct dentry *de;
3114
3115         de = debugfs_create_file(name, S_IRUSR, adap->debugfs_root,
3116                                  (void *)adap + idx, &mem_debugfs_fops);
3117         if (de && de->d_inode)
3118                 de->d_inode->i_size = size_mb << 20;
3119 }
3120
3121 static int setup_debugfs(struct adapter *adap)
3122 {
3123         int i;
3124         u32 size;
3125
3126         if (IS_ERR_OR_NULL(adap->debugfs_root))
3127                 return -1;
3128
3129         i = t4_read_reg(adap, MA_TARGET_MEM_ENABLE);
3130         if (i & EDRAM0_ENABLE) {
3131                 size = t4_read_reg(adap, MA_EDRAM0_BAR);
3132                 add_debugfs_mem(adap, "edc0", MEM_EDC0, EDRAM_SIZE_GET(size));
3133         }
3134         if (i & EDRAM1_ENABLE) {
3135                 size = t4_read_reg(adap, MA_EDRAM1_BAR);
3136                 add_debugfs_mem(adap, "edc1", MEM_EDC1, EDRAM_SIZE_GET(size));
3137         }
3138         if (is_t4(adap->params.chip)) {
3139                 size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3140                 if (i & EXT_MEM_ENABLE)
3141                         add_debugfs_mem(adap, "mc", MEM_MC,
3142                                         EXT_MEM_SIZE_GET(size));
3143         } else {
3144                 if (i & EXT_MEM_ENABLE) {
3145                         size = t4_read_reg(adap, MA_EXT_MEMORY_BAR);
3146                         add_debugfs_mem(adap, "mc0", MEM_MC0,
3147                                         EXT_MEM_SIZE_GET(size));
3148                 }
3149                 if (i & EXT_MEM1_ENABLE) {
3150                         size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR);
3151                         add_debugfs_mem(adap, "mc1", MEM_MC1,
3152                                         EXT_MEM_SIZE_GET(size));
3153                 }
3154         }
3155         if (adap->l2t)
3156                 debugfs_create_file("l2t", S_IRUSR, adap->debugfs_root, adap,
3157                                     &t4_l2t_fops);
3158         return 0;
3159 }
3160
3161 /*
3162  * upper-layer driver support
3163  */
3164
3165 /*
3166  * Allocate an active-open TID and set it to the supplied value.
3167  */
3168 int cxgb4_alloc_atid(struct tid_info *t, void *data)
3169 {
3170         int atid = -1;
3171
3172         spin_lock_bh(&t->atid_lock);
3173         if (t->afree) {
3174                 union aopen_entry *p = t->afree;
3175
3176                 atid = (p - t->atid_tab) + t->atid_base;
3177                 t->afree = p->next;
3178                 p->data = data;
3179                 t->atids_in_use++;
3180         }
3181         spin_unlock_bh(&t->atid_lock);
3182         return atid;
3183 }
3184 EXPORT_SYMBOL(cxgb4_alloc_atid);
3185
3186 /*
3187  * Release an active-open TID.
3188  */
3189 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
3190 {
3191         union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
3192
3193         spin_lock_bh(&t->atid_lock);
3194         p->next = t->afree;
3195         t->afree = p;
3196         t->atids_in_use--;
3197         spin_unlock_bh(&t->atid_lock);
3198 }
3199 EXPORT_SYMBOL(cxgb4_free_atid);
3200
3201 /*
3202  * Allocate a server TID and set it to the supplied value.
3203  */
3204 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
3205 {
3206         int stid;
3207
3208         spin_lock_bh(&t->stid_lock);
3209         if (family == PF_INET) {
3210                 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
3211                 if (stid < t->nstids)
3212                         __set_bit(stid, t->stid_bmap);
3213                 else
3214                         stid = -1;
3215         } else {
3216                 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 2);
3217                 if (stid < 0)
3218                         stid = -1;
3219         }
3220         if (stid >= 0) {
3221                 t->stid_tab[stid].data = data;
3222                 stid += t->stid_base;
3223                 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3224                  * This is equivalent to 4 TIDs. With CLIP enabled it
3225                  * needs 2 TIDs.
3226                  */
3227                 if (family == PF_INET)
3228                         t->stids_in_use++;
3229                 else
3230                         t->stids_in_use += 4;
3231         }
3232         spin_unlock_bh(&t->stid_lock);
3233         return stid;
3234 }
3235 EXPORT_SYMBOL(cxgb4_alloc_stid);
3236
3237 /* Allocate a server filter TID and set it to the supplied value.
3238  */
3239 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
3240 {
3241         int stid;
3242
3243         spin_lock_bh(&t->stid_lock);
3244         if (family == PF_INET) {
3245                 stid = find_next_zero_bit(t->stid_bmap,
3246                                 t->nstids + t->nsftids, t->nstids);
3247                 if (stid < (t->nstids + t->nsftids))
3248                         __set_bit(stid, t->stid_bmap);
3249                 else
3250                         stid = -1;
3251         } else {
3252                 stid = -1;
3253         }
3254         if (stid >= 0) {
3255                 t->stid_tab[stid].data = data;
3256                 stid -= t->nstids;
3257                 stid += t->sftid_base;
3258                 t->stids_in_use++;
3259         }
3260         spin_unlock_bh(&t->stid_lock);
3261         return stid;
3262 }
3263 EXPORT_SYMBOL(cxgb4_alloc_sftid);
3264
3265 /* Release a server TID.
3266  */
3267 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
3268 {
3269         /* Is it a server filter TID? */
3270         if (t->nsftids && (stid >= t->sftid_base)) {
3271                 stid -= t->sftid_base;
3272                 stid += t->nstids;
3273         } else {
3274                 stid -= t->stid_base;
3275         }
3276
3277         spin_lock_bh(&t->stid_lock);
3278         if (family == PF_INET)
3279                 __clear_bit(stid, t->stid_bmap);
3280         else
3281                 bitmap_release_region(t->stid_bmap, stid, 2);
3282         t->stid_tab[stid].data = NULL;
3283         if (family == PF_INET)
3284                 t->stids_in_use--;
3285         else
3286                 t->stids_in_use -= 4;
3287         spin_unlock_bh(&t->stid_lock);
3288 }
3289 EXPORT_SYMBOL(cxgb4_free_stid);
3290
3291 /*
3292  * Populate a TID_RELEASE WR.  Caller must properly size the skb.
3293  */
3294 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
3295                            unsigned int tid)
3296 {
3297         struct cpl_tid_release *req;
3298
3299         set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
3300         req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
3301         INIT_TP_WR(req, tid);
3302         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
3303 }
3304
3305 /*
3306  * Queue a TID release request and if necessary schedule a work queue to
3307  * process it.
3308  */
3309 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
3310                                     unsigned int tid)
3311 {
3312         void **p = &t->tid_tab[tid];
3313         struct adapter *adap = container_of(t, struct adapter, tids);
3314
3315         spin_lock_bh(&adap->tid_release_lock);
3316         *p = adap->tid_release_head;
3317         /* Low 2 bits encode the Tx channel number */
3318         adap->tid_release_head = (void **)((uintptr_t)p | chan);
3319         if (!adap->tid_release_task_busy) {
3320                 adap->tid_release_task_busy = true;
3321                 queue_work(workq, &adap->tid_release_task);
3322         }
3323         spin_unlock_bh(&adap->tid_release_lock);
3324 }
3325
3326 /*
3327  * Process the list of pending TID release requests.
3328  */
3329 static void process_tid_release_list(struct work_struct *work)
3330 {
3331         struct sk_buff *skb;
3332         struct adapter *adap;
3333
3334         adap = container_of(work, struct adapter, tid_release_task);
3335
3336         spin_lock_bh(&adap->tid_release_lock);
3337         while (adap->tid_release_head) {
3338                 void **p = adap->tid_release_head;
3339                 unsigned int chan = (uintptr_t)p & 3;
3340                 p = (void *)p - chan;
3341
3342                 adap->tid_release_head = *p;
3343                 *p = NULL;
3344                 spin_unlock_bh(&adap->tid_release_lock);
3345
3346                 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
3347                                          GFP_KERNEL)))
3348                         schedule_timeout_uninterruptible(1);
3349
3350                 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
3351                 t4_ofld_send(adap, skb);
3352                 spin_lock_bh(&adap->tid_release_lock);
3353         }
3354         adap->tid_release_task_busy = false;
3355         spin_unlock_bh(&adap->tid_release_lock);
3356 }
3357
3358 /*
3359  * Release a TID and inform HW.  If we are unable to allocate the release
3360  * message we defer to a work queue.
3361  */
3362 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
3363 {
3364         void *old;
3365         struct sk_buff *skb;
3366         struct adapter *adap = container_of(t, struct adapter, tids);
3367
3368         old = t->tid_tab[tid];
3369         skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
3370         if (likely(skb)) {
3371                 t->tid_tab[tid] = NULL;
3372                 mk_tid_release(skb, chan, tid);
3373                 t4_ofld_send(adap, skb);
3374         } else
3375                 cxgb4_queue_tid_release(t, chan, tid);
3376         if (old)
3377                 atomic_dec(&t->tids_in_use);
3378 }
3379 EXPORT_SYMBOL(cxgb4_remove_tid);
3380
3381 /*
3382  * Allocate and initialize the TID tables.  Returns 0 on success.
3383  */
3384 static int tid_init(struct tid_info *t)
3385 {
3386         size_t size;
3387         unsigned int stid_bmap_size;
3388         unsigned int natids = t->natids;
3389         struct adapter *adap = container_of(t, struct adapter, tids);
3390
3391         stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
3392         size = t->ntids * sizeof(*t->tid_tab) +
3393                natids * sizeof(*t->atid_tab) +
3394                t->nstids * sizeof(*t->stid_tab) +
3395                t->nsftids * sizeof(*t->stid_tab) +
3396                stid_bmap_size * sizeof(long) +
3397                t->nftids * sizeof(*t->ftid_tab) +
3398                t->nsftids * sizeof(*t->ftid_tab);
3399
3400         t->tid_tab = t4_alloc_mem(size);
3401         if (!t->tid_tab)
3402                 return -ENOMEM;
3403
3404         t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
3405         t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
3406         t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
3407         t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
3408         spin_lock_init(&t->stid_lock);
3409         spin_lock_init(&t->atid_lock);
3410
3411         t->stids_in_use = 0;
3412         t->afree = NULL;
3413         t->atids_in_use = 0;
3414         atomic_set(&t->tids_in_use, 0);
3415
3416         /* Setup the free list for atid_tab and clear the stid bitmap. */
3417         if (natids) {
3418                 while (--natids)
3419                         t->atid_tab[natids - 1].next = &t->atid_tab[natids];
3420                 t->afree = t->atid_tab;
3421         }
3422         bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
3423         /* Reserve stid 0 for T4/T5 adapters */
3424         if (!t->stid_base &&
3425             (is_t4(adap->params.chip) || is_t5(adap->params.chip)))
3426                 __set_bit(0, t->stid_bmap);
3427
3428         return 0;
3429 }
3430
3431 static int cxgb4_clip_get(const struct net_device *dev,
3432                           const struct in6_addr *lip)
3433 {
3434         struct adapter *adap;
3435         struct fw_clip_cmd c;
3436
3437         adap = netdev2adap(dev);
3438         memset(&c, 0, sizeof(c));
3439         c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3440                         FW_CMD_REQUEST | FW_CMD_WRITE);
3441         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_ALLOC | FW_LEN16(c));
3442         c.ip_hi = *(__be64 *)(lip->s6_addr);
3443         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3444         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3445 }
3446
3447 static int cxgb4_clip_release(const struct net_device *dev,
3448                               const struct in6_addr *lip)
3449 {
3450         struct adapter *adap;
3451         struct fw_clip_cmd c;
3452
3453         adap = netdev2adap(dev);
3454         memset(&c, 0, sizeof(c));
3455         c.op_to_write = htonl(FW_CMD_OP(FW_CLIP_CMD) |
3456                         FW_CMD_REQUEST | FW_CMD_READ);
3457         c.alloc_to_len16 = htonl(F_FW_CLIP_CMD_FREE | FW_LEN16(c));
3458         c.ip_hi = *(__be64 *)(lip->s6_addr);
3459         c.ip_lo = *(__be64 *)(lip->s6_addr + 8);
3460         return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, false);
3461 }
3462
3463 /**
3464  *      cxgb4_create_server - create an IP server
3465  *      @dev: the device
3466  *      @stid: the server TID
3467  *      @sip: local IP address to bind server to
3468  *      @sport: the server's TCP port
3469  *      @queue: queue to direct messages from this server to
3470  *
3471  *      Create an IP server for the given port and address.
3472  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3473  */
3474 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
3475                         __be32 sip, __be16 sport, __be16 vlan,
3476                         unsigned int queue)
3477 {
3478         unsigned int chan;
3479         struct sk_buff *skb;
3480         struct adapter *adap;
3481         struct cpl_pass_open_req *req;
3482         int ret;
3483
3484         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3485         if (!skb)
3486                 return -ENOMEM;
3487
3488         adap = netdev2adap(dev);
3489         req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
3490         INIT_TP_WR(req, 0);
3491         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
3492         req->local_port = sport;
3493         req->peer_port = htons(0);
3494         req->local_ip = sip;
3495         req->peer_ip = htonl(0);
3496         chan = rxq_to_chan(&adap->sge, queue);
3497         req->opt0 = cpu_to_be64(TX_CHAN(chan));
3498         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3499                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3500         ret = t4_mgmt_tx(adap, skb);
3501         return net_xmit_eval(ret);
3502 }
3503 EXPORT_SYMBOL(cxgb4_create_server);
3504
3505 /*      cxgb4_create_server6 - create an IPv6 server
3506  *      @dev: the device
3507  *      @stid: the server TID
3508  *      @sip: local IPv6 address to bind server to
3509  *      @sport: the server's TCP port
3510  *      @queue: queue to direct messages from this server to
3511  *
3512  *      Create an IPv6 server for the given port and address.
3513  *      Returns <0 on error and one of the %NET_XMIT_* values on success.
3514  */
3515 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
3516                          const struct in6_addr *sip, __be16 sport,
3517                          unsigned int queue)
3518 {
3519         unsigned int chan;
3520         struct sk_buff *skb;
3521         struct adapter *adap;
3522         struct cpl_pass_open_req6 *req;
3523         int ret;
3524
3525         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3526         if (!skb)
3527                 return -ENOMEM;
3528
3529         adap = netdev2adap(dev);
3530         req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
3531         INIT_TP_WR(req, 0);
3532         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
3533         req->local_port = sport;
3534         req->peer_port = htons(0);
3535         req->local_ip_hi = *(__be64 *)(sip->s6_addr);
3536         req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
3537         req->peer_ip_hi = cpu_to_be64(0);
3538         req->peer_ip_lo = cpu_to_be64(0);
3539         chan = rxq_to_chan(&adap->sge, queue);
3540         req->opt0 = cpu_to_be64(TX_CHAN(chan));
3541         req->opt1 = cpu_to_be64(CONN_POLICY_ASK |
3542                                 SYN_RSS_ENABLE | SYN_RSS_QUEUE(queue));
3543         ret = t4_mgmt_tx(adap, skb);
3544         return net_xmit_eval(ret);
3545 }
3546 EXPORT_SYMBOL(cxgb4_create_server6);
3547
3548 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
3549                         unsigned int queue, bool ipv6)
3550 {
3551         struct sk_buff *skb;
3552         struct adapter *adap;
3553         struct cpl_close_listsvr_req *req;
3554         int ret;
3555
3556         adap = netdev2adap(dev);
3557
3558         skb = alloc_skb(sizeof(*req), GFP_KERNEL);
3559         if (!skb)
3560                 return -ENOMEM;
3561
3562         req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
3563         INIT_TP_WR(req, 0);
3564         OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
3565         req->reply_ctrl = htons(NO_REPLY(0) | (ipv6 ? LISTSVR_IPV6(1) :
3566                                 LISTSVR_IPV6(0)) | QUEUENO(queue));
3567         ret = t4_mgmt_tx(adap, skb);
3568         return net_xmit_eval(ret);
3569 }
3570 EXPORT_SYMBOL(cxgb4_remove_server);
3571
3572 /**
3573  *      cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3574  *      @mtus: the HW MTU table
3575  *      @mtu: the target MTU
3576  *      @idx: index of selected entry in the MTU table
3577  *
3578  *      Returns the index and the value in the HW MTU table that is closest to
3579  *      but does not exceed @mtu, unless @mtu is smaller than any value in the
3580  *      table, in which case that smallest available value is selected.
3581  */
3582 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
3583                             unsigned int *idx)
3584 {
3585         unsigned int i = 0;
3586
3587         while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
3588                 ++i;
3589         if (idx)
3590                 *idx = i;
3591         return mtus[i];
3592 }
3593 EXPORT_SYMBOL(cxgb4_best_mtu);
3594
3595 /**
3596  *     cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3597  *     @mtus: the HW MTU table
3598  *     @header_size: Header Size
3599  *     @data_size_max: maximum Data Segment Size
3600  *     @data_size_align: desired Data Segment Size Alignment (2^N)
3601  *     @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3602  *
3603  *     Similar to cxgb4_best_mtu() but instead of searching the Hardware
3604  *     MTU Table based solely on a Maximum MTU parameter, we break that
3605  *     parameter up into a Header Size and Maximum Data Segment Size, and
3606  *     provide a desired Data Segment Size Alignment.  If we find an MTU in
3607  *     the Hardware MTU Table which will result in a Data Segment Size with
3608  *     the requested alignment _and_ that MTU isn't "too far" from the
3609  *     closest MTU, then we'll return that rather than the closest MTU.
3610  */
3611 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
3612                                     unsigned short header_size,
3613                                     unsigned short data_size_max,
3614                                     unsigned short data_size_align,
3615                                     unsigned int *mtu_idxp)
3616 {
3617         unsigned short max_mtu = header_size + data_size_max;
3618         unsigned short data_size_align_mask = data_size_align - 1;
3619         int mtu_idx, aligned_mtu_idx;
3620
3621         /* Scan the MTU Table till we find an MTU which is larger than our
3622          * Maximum MTU or we reach the end of the table.  Along the way,
3623          * record the last MTU found, if any, which will result in a Data
3624          * Segment Length matching the requested alignment.
3625          */
3626         for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
3627                 unsigned short data_size = mtus[mtu_idx] - header_size;
3628
3629                 /* If this MTU minus the Header Size would result in a
3630                  * Data Segment Size of the desired alignment, remember it.
3631                  */
3632                 if ((data_size & data_size_align_mask) == 0)
3633                         aligned_mtu_idx = mtu_idx;
3634
3635                 /* If we're not at the end of the Hardware MTU Table and the
3636                  * next element is larger than our Maximum MTU, drop out of
3637                  * the loop.
3638                  */
3639                 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
3640                         break;
3641         }
3642
3643         /* If we fell out of the loop because we ran to the end of the table,
3644          * then we just have to use the last [largest] entry.
3645          */
3646         if (mtu_idx == NMTUS)
3647                 mtu_idx--;
3648
3649         /* If we found an MTU which resulted in the requested Data Segment
3650          * Length alignment and that's "not far" from the largest MTU which is
3651          * less than or equal to the maximum MTU, then use that.
3652          */
3653         if (aligned_mtu_idx >= 0 &&
3654             mtu_idx - aligned_mtu_idx <= 1)
3655                 mtu_idx = aligned_mtu_idx;
3656
3657         /* If the caller has passed in an MTU Index pointer, pass the
3658          * MTU Index back.  Return the MTU value.
3659          */
3660         if (mtu_idxp)
3661                 *mtu_idxp = mtu_idx;
3662         return mtus[mtu_idx];
3663 }
3664 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
3665
3666 /**
3667  *      cxgb4_port_chan - get the HW channel of a port
3668  *      @dev: the net device for the port
3669  *
3670  *      Return the HW Tx channel of the given port.
3671  */
3672 unsigned int cxgb4_port_chan(const struct net_device *dev)
3673 {
3674         return netdev2pinfo(dev)->tx_chan;
3675 }
3676 EXPORT_SYMBOL(cxgb4_port_chan);
3677
3678 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
3679 {
3680         struct adapter *adap = netdev2adap(dev);
3681         u32 v1, v2, lp_count, hp_count;
3682
3683         v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3684         v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3685         if (is_t4(adap->params.chip)) {
3686                 lp_count = G_LP_COUNT(v1);
3687                 hp_count = G_HP_COUNT(v1);
3688         } else {
3689                 lp_count = G_LP_COUNT_T5(v1);
3690                 hp_count = G_HP_COUNT_T5(v2);
3691         }
3692         return lpfifo ? lp_count : hp_count;
3693 }
3694 EXPORT_SYMBOL(cxgb4_dbfifo_count);
3695
3696 /**
3697  *      cxgb4_port_viid - get the VI id of a port
3698  *      @dev: the net device for the port
3699  *
3700  *      Return the VI id of the given port.
3701  */
3702 unsigned int cxgb4_port_viid(const struct net_device *dev)
3703 {
3704         return netdev2pinfo(dev)->viid;
3705 }
3706 EXPORT_SYMBOL(cxgb4_port_viid);
3707
3708 /**
3709  *      cxgb4_port_idx - get the index of a port
3710  *      @dev: the net device for the port
3711  *
3712  *      Return the index of the given port.
3713  */
3714 unsigned int cxgb4_port_idx(const struct net_device *dev)
3715 {
3716         return netdev2pinfo(dev)->port_id;
3717 }
3718 EXPORT_SYMBOL(cxgb4_port_idx);
3719
3720 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
3721                          struct tp_tcp_stats *v6)
3722 {
3723         struct adapter *adap = pci_get_drvdata(pdev);
3724
3725         spin_lock(&adap->stats_lock);
3726         t4_tp_get_tcp_stats(adap, v4, v6);
3727         spin_unlock(&adap->stats_lock);
3728 }
3729 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
3730
3731 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
3732                       const unsigned int *pgsz_order)
3733 {
3734         struct adapter *adap = netdev2adap(dev);
3735
3736         t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK, tag_mask);
3737         t4_write_reg(adap, ULP_RX_ISCSI_PSZ, HPZ0(pgsz_order[0]) |
3738                      HPZ1(pgsz_order[1]) | HPZ2(pgsz_order[2]) |
3739                      HPZ3(pgsz_order[3]));
3740 }
3741 EXPORT_SYMBOL(cxgb4_iscsi_init);
3742
3743 int cxgb4_flush_eq_cache(struct net_device *dev)
3744 {
3745         struct adapter *adap = netdev2adap(dev);
3746         int ret;
3747
3748         ret = t4_fwaddrspace_write(adap, adap->mbox,
3749                                    0xe1000000 + A_SGE_CTXT_CMD, 0x20000000);
3750         return ret;
3751 }
3752 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
3753
3754 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
3755 {
3756         u32 addr = t4_read_reg(adap, A_SGE_DBQ_CTXT_BADDR) + 24 * qid + 8;
3757         __be64 indices;
3758         int ret;
3759
3760         ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
3761         if (!ret) {
3762                 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
3763                 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
3764         }
3765         return ret;
3766 }
3767
3768 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
3769                         u16 size)
3770 {
3771         struct adapter *adap = netdev2adap(dev);
3772         u16 hw_pidx, hw_cidx;
3773         int ret;
3774
3775         ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
3776         if (ret)
3777                 goto out;
3778
3779         if (pidx != hw_pidx) {
3780                 u16 delta;
3781
3782                 if (pidx >= hw_pidx)
3783                         delta = pidx - hw_pidx;
3784                 else
3785                         delta = size - hw_pidx + pidx;
3786                 wmb();
3787                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3788                              QID(qid) | PIDX(delta));
3789         }
3790 out:
3791         return ret;
3792 }
3793 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
3794
3795 void cxgb4_disable_db_coalescing(struct net_device *dev)
3796 {
3797         struct adapter *adap;
3798
3799         adap = netdev2adap(dev);
3800         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE,
3801                          F_NOCOALESCE);
3802 }
3803 EXPORT_SYMBOL(cxgb4_disable_db_coalescing);
3804
3805 void cxgb4_enable_db_coalescing(struct net_device *dev)
3806 {
3807         struct adapter *adap;
3808
3809         adap = netdev2adap(dev);
3810         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_NOCOALESCE, 0);
3811 }
3812 EXPORT_SYMBOL(cxgb4_enable_db_coalescing);
3813
3814 static struct pci_driver cxgb4_driver;
3815
3816 static void check_neigh_update(struct neighbour *neigh)
3817 {
3818         const struct device *parent;
3819         const struct net_device *netdev = neigh->dev;
3820
3821         if (netdev->priv_flags & IFF_802_1Q_VLAN)
3822                 netdev = vlan_dev_real_dev(netdev);
3823         parent = netdev->dev.parent;
3824         if (parent && parent->driver == &cxgb4_driver.driver)
3825                 t4_l2t_update(dev_get_drvdata(parent), neigh);
3826 }
3827
3828 static int netevent_cb(struct notifier_block *nb, unsigned long event,
3829                        void *data)
3830 {
3831         switch (event) {
3832         case NETEVENT_NEIGH_UPDATE:
3833                 check_neigh_update(data);
3834                 break;
3835         case NETEVENT_REDIRECT:
3836         default:
3837                 break;
3838         }
3839         return 0;
3840 }
3841
3842 static bool netevent_registered;
3843 static struct notifier_block cxgb4_netevent_nb = {
3844         .notifier_call = netevent_cb
3845 };
3846
3847 static void drain_db_fifo(struct adapter *adap, int usecs)
3848 {
3849         u32 v1, v2, lp_count, hp_count;
3850
3851         do {
3852                 v1 = t4_read_reg(adap, A_SGE_DBFIFO_STATUS);
3853                 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2);
3854                 if (is_t4(adap->params.chip)) {
3855                         lp_count = G_LP_COUNT(v1);
3856                         hp_count = G_HP_COUNT(v1);
3857                 } else {
3858                         lp_count = G_LP_COUNT_T5(v1);
3859                         hp_count = G_HP_COUNT_T5(v2);
3860                 }
3861
3862                 if (lp_count == 0 && hp_count == 0)
3863                         break;
3864                 set_current_state(TASK_UNINTERRUPTIBLE);
3865                 schedule_timeout(usecs_to_jiffies(usecs));
3866         } while (1);
3867 }
3868
3869 static void disable_txq_db(struct sge_txq *q)
3870 {
3871         unsigned long flags;
3872
3873         spin_lock_irqsave(&q->db_lock, flags);
3874         q->db_disabled = 1;
3875         spin_unlock_irqrestore(&q->db_lock, flags);
3876 }
3877
3878 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
3879 {
3880         spin_lock_irq(&q->db_lock);
3881         if (q->db_pidx_inc) {
3882                 /* Make sure that all writes to the TX descriptors
3883                  * are committed before we tell HW about them.
3884                  */
3885                 wmb();
3886                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3887                              QID(q->cntxt_id) | PIDX(q->db_pidx_inc));
3888                 q->db_pidx_inc = 0;
3889         }
3890         q->db_disabled = 0;
3891         spin_unlock_irq(&q->db_lock);
3892 }
3893
3894 static void disable_dbs(struct adapter *adap)
3895 {
3896         int i;
3897
3898         for_each_ethrxq(&adap->sge, i)
3899                 disable_txq_db(&adap->sge.ethtxq[i].q);
3900         for_each_ofldrxq(&adap->sge, i)
3901                 disable_txq_db(&adap->sge.ofldtxq[i].q);
3902         for_each_port(adap, i)
3903                 disable_txq_db(&adap->sge.ctrlq[i].q);
3904 }
3905
3906 static void enable_dbs(struct adapter *adap)
3907 {
3908         int i;
3909
3910         for_each_ethrxq(&adap->sge, i)
3911                 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
3912         for_each_ofldrxq(&adap->sge, i)
3913                 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
3914         for_each_port(adap, i)
3915                 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
3916 }
3917
3918 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
3919 {
3920         if (adap->uld_handle[CXGB4_ULD_RDMA])
3921                 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
3922                                 cmd);
3923 }
3924
3925 static void process_db_full(struct work_struct *work)
3926 {
3927         struct adapter *adap;
3928
3929         adap = container_of(work, struct adapter, db_full_task);
3930
3931         drain_db_fifo(adap, dbfifo_drain_delay);
3932         enable_dbs(adap);
3933         notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3934         t4_set_reg_field(adap, SGE_INT_ENABLE3,
3935                          DBFIFO_HP_INT | DBFIFO_LP_INT,
3936                          DBFIFO_HP_INT | DBFIFO_LP_INT);
3937 }
3938
3939 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
3940 {
3941         u16 hw_pidx, hw_cidx;
3942         int ret;
3943
3944         spin_lock_irq(&q->db_lock);
3945         ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
3946         if (ret)
3947                 goto out;
3948         if (q->db_pidx != hw_pidx) {
3949                 u16 delta;
3950
3951                 if (q->db_pidx >= hw_pidx)
3952                         delta = q->db_pidx - hw_pidx;
3953                 else
3954                         delta = q->size - hw_pidx + q->db_pidx;
3955                 wmb();
3956                 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL),
3957                              QID(q->cntxt_id) | PIDX(delta));
3958         }
3959 out:
3960         q->db_disabled = 0;
3961         q->db_pidx_inc = 0;
3962         spin_unlock_irq(&q->db_lock);
3963         if (ret)
3964                 CH_WARN(adap, "DB drop recovery failed.\n");
3965 }
3966 static void recover_all_queues(struct adapter *adap)
3967 {
3968         int i;
3969
3970         for_each_ethrxq(&adap->sge, i)
3971                 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
3972         for_each_ofldrxq(&adap->sge, i)
3973                 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
3974         for_each_port(adap, i)
3975                 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
3976 }
3977
3978 static void process_db_drop(struct work_struct *work)
3979 {
3980         struct adapter *adap;
3981
3982         adap = container_of(work, struct adapter, db_drop_task);
3983
3984         if (is_t4(adap->params.chip)) {
3985                 drain_db_fifo(adap, dbfifo_drain_delay);
3986                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
3987                 drain_db_fifo(adap, dbfifo_drain_delay);
3988                 recover_all_queues(adap);
3989                 drain_db_fifo(adap, dbfifo_drain_delay);
3990                 enable_dbs(adap);
3991                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
3992         } else {
3993                 u32 dropped_db = t4_read_reg(adap, 0x010ac);
3994                 u16 qid = (dropped_db >> 15) & 0x1ffff;
3995                 u16 pidx_inc = dropped_db & 0x1fff;
3996                 unsigned int s_qpp;
3997                 unsigned short udb_density;
3998                 unsigned long qpshift;
3999                 int page;
4000                 u32 udb;
4001
4002                 dev_warn(adap->pdev_dev,
4003                          "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4004                          dropped_db, qid,
4005                          (dropped_db >> 14) & 1,
4006                          (dropped_db >> 13) & 1,
4007                          pidx_inc);
4008
4009                 drain_db_fifo(adap, 1);
4010
4011                 s_qpp = QUEUESPERPAGEPF1 * adap->fn;
4012                 udb_density = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap,
4013                                 SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
4014                 qpshift = PAGE_SHIFT - ilog2(udb_density);
4015                 udb = qid << qpshift;
4016                 udb &= PAGE_MASK;
4017                 page = udb / PAGE_SIZE;
4018                 udb += (qid - (page * udb_density)) * 128;
4019
4020                 writel(PIDX(pidx_inc),  adap->bar2 + udb + 8);
4021
4022                 /* Re-enable BAR2 WC */
4023                 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
4024         }
4025
4026         t4_set_reg_field(adap, A_SGE_DOORBELL_CONTROL, F_DROPPED_DB, 0);
4027 }
4028
4029 void t4_db_full(struct adapter *adap)
4030 {
4031         if (is_t4(adap->params.chip)) {
4032                 disable_dbs(adap);
4033                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4034                 t4_set_reg_field(adap, SGE_INT_ENABLE3,
4035                                  DBFIFO_HP_INT | DBFIFO_LP_INT, 0);
4036                 queue_work(workq, &adap->db_full_task);
4037         }
4038 }
4039
4040 void t4_db_dropped(struct adapter *adap)
4041 {
4042         if (is_t4(adap->params.chip)) {
4043                 disable_dbs(adap);
4044                 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
4045         }
4046         queue_work(workq, &adap->db_drop_task);
4047 }
4048
4049 static void uld_attach(struct adapter *adap, unsigned int uld)
4050 {
4051         void *handle;
4052         struct cxgb4_lld_info lli;
4053         unsigned short i;
4054
4055         lli.pdev = adap->pdev;
4056         lli.pf = adap->fn;
4057         lli.l2t = adap->l2t;
4058         lli.tids = &adap->tids;
4059         lli.ports = adap->port;
4060         lli.vr = &adap->vres;
4061         lli.mtus = adap->params.mtus;
4062         if (uld == CXGB4_ULD_RDMA) {
4063                 lli.rxq_ids = adap->sge.rdma_rxq;
4064                 lli.ciq_ids = adap->sge.rdma_ciq;
4065                 lli.nrxq = adap->sge.rdmaqs;
4066                 lli.nciq = adap->sge.rdmaciqs;
4067         } else if (uld == CXGB4_ULD_ISCSI) {
4068                 lli.rxq_ids = adap->sge.ofld_rxq;
4069                 lli.nrxq = adap->sge.ofldqsets;
4070         }
4071         lli.ntxq = adap->sge.ofldqsets;
4072         lli.nchan = adap->params.nports;
4073         lli.nports = adap->params.nports;
4074         lli.wr_cred = adap->params.ofldq_wr_cred;
4075         lli.adapter_type = adap->params.chip;
4076         lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2));
4077         lli.udb_density = 1 << QUEUESPERPAGEPF0_GET(
4078                         t4_read_reg(adap, SGE_EGRESS_QUEUES_PER_PAGE_PF) >>
4079                         (adap->fn * 4));
4080         lli.ucq_density = 1 << QUEUESPERPAGEPF0_GET(
4081                         t4_read_reg(adap, SGE_INGRESS_QUEUES_PER_PAGE_PF) >>
4082                         (adap->fn * 4));
4083         lli.filt_mode = adap->params.tp.vlan_pri_map;
4084         /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4085         for (i = 0; i < NCHAN; i++)
4086                 lli.tx_modq[i] = i;
4087         lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS);
4088         lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL);
4089         lli.fw_vers = adap->params.fw_vers;
4090         lli.dbfifo_int_thresh = dbfifo_int_thresh;
4091         lli.sge_pktshift = adap->sge.pktshift;
4092         lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
4093         lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
4094
4095         handle = ulds[uld].add(&lli);
4096         if (IS_ERR(handle)) {
4097                 dev_warn(adap->pdev_dev,
4098                          "could not attach to the %s driver, error %ld\n",
4099                          uld_str[uld], PTR_ERR(handle));
4100                 return;
4101         }
4102
4103         adap->uld_handle[uld] = handle;
4104
4105         if (!netevent_registered) {
4106                 register_netevent_notifier(&cxgb4_netevent_nb);
4107                 netevent_registered = true;
4108         }
4109
4110         if (adap->flags & FULL_INIT_DONE)
4111                 ulds[uld].state_change(handle, CXGB4_STATE_UP);
4112 }
4113
4114 static void attach_ulds(struct adapter *adap)
4115 {
4116         unsigned int i;
4117
4118         spin_lock(&adap_rcu_lock);
4119         list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
4120         spin_unlock(&adap_rcu_lock);
4121
4122         mutex_lock(&uld_mutex);
4123         list_add_tail(&adap->list_node, &adapter_list);
4124         for (i = 0; i < CXGB4_ULD_MAX; i++)
4125                 if (ulds[i].add)
4126                         uld_attach(adap, i);
4127         mutex_unlock(&uld_mutex);
4128 }
4129
4130 static void detach_ulds(struct adapter *adap)
4131 {
4132         unsigned int i;
4133
4134         mutex_lock(&uld_mutex);
4135         list_del(&adap->list_node);
4136         for (i = 0; i < CXGB4_ULD_MAX; i++)
4137                 if (adap->uld_handle[i]) {
4138                         ulds[i].state_change(adap->uld_handle[i],
4139                                              CXGB4_STATE_DETACH);
4140                         adap->uld_handle[i] = NULL;
4141                 }
4142         if (netevent_registered && list_empty(&adapter_list)) {
4143                 unregister_netevent_notifier(&cxgb4_netevent_nb);
4144                 netevent_registered = false;
4145         }
4146         mutex_unlock(&uld_mutex);
4147
4148         spin_lock(&adap_rcu_lock);
4149         list_del_rcu(&adap->rcu_node);
4150         spin_unlock(&adap_rcu_lock);
4151 }
4152
4153 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
4154 {
4155         unsigned int i;
4156
4157         mutex_lock(&uld_mutex);
4158         for (i = 0; i < CXGB4_ULD_MAX; i++)
4159                 if (adap->uld_handle[i])
4160                         ulds[i].state_change(adap->uld_handle[i], new_state);
4161         mutex_unlock(&uld_mutex);
4162 }
4163
4164 /**
4165  *      cxgb4_register_uld - register an upper-layer driver
4166  *      @type: the ULD type
4167  *      @p: the ULD methods
4168  *
4169  *      Registers an upper-layer driver with this driver and notifies the ULD
4170  *      about any presently available devices that support its type.  Returns
4171  *      %-EBUSY if a ULD of the same type is already registered.
4172  */
4173 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
4174 {
4175         int ret = 0;
4176         struct adapter *adap;
4177
4178         if (type >= CXGB4_ULD_MAX)
4179                 return -EINVAL;
4180         mutex_lock(&uld_mutex);
4181         if (ulds[type].add) {
4182                 ret = -EBUSY;
4183                 goto out;
4184         }
4185         ulds[type] = *p;
4186         list_for_each_entry(adap, &adapter_list, list_node)
4187                 uld_attach(adap, type);
4188 out:    mutex_unlock(&uld_mutex);
4189         return ret;
4190 }
4191 EXPORT_SYMBOL(cxgb4_register_uld);
4192
4193 /**
4194  *      cxgb4_unregister_uld - unregister an upper-layer driver
4195  *      @type: the ULD type
4196  *
4197  *      Unregisters an existing upper-layer driver.
4198  */
4199 int cxgb4_unregister_uld(enum cxgb4_uld type)
4200 {
4201         struct adapter *adap;
4202
4203         if (type >= CXGB4_ULD_MAX)
4204                 return -EINVAL;
4205         mutex_lock(&uld_mutex);
4206         list_for_each_entry(adap, &adapter_list, list_node)
4207                 adap->uld_handle[type] = NULL;
4208         ulds[type].add = NULL;
4209         mutex_unlock(&uld_mutex);
4210         return 0;
4211 }
4212 EXPORT_SYMBOL(cxgb4_unregister_uld);
4213
4214 /* Check if netdev on which event is occured belongs to us or not. Return
4215  * success (true) if it belongs otherwise failure (false).
4216  * Called with rcu_read_lock() held.
4217  */
4218 static bool cxgb4_netdev(const struct net_device *netdev)
4219 {
4220         struct adapter *adap;
4221         int i;
4222
4223         list_for_each_entry_rcu(adap, &adap_rcu_list, rcu_node)
4224                 for (i = 0; i < MAX_NPORTS; i++)
4225                         if (adap->port[i] == netdev)
4226                                 return true;
4227         return false;
4228 }
4229
4230 static int clip_add(struct net_device *event_dev, struct inet6_ifaddr *ifa,
4231                     unsigned long event)
4232 {
4233         int ret = NOTIFY_DONE;
4234
4235         rcu_read_lock();
4236         if (cxgb4_netdev(event_dev)) {
4237                 switch (event) {
4238                 case NETDEV_UP:
4239                         ret = cxgb4_clip_get(event_dev,
4240                                 (const struct in6_addr *)ifa->addr.s6_addr);
4241                         if (ret < 0) {
4242                                 rcu_read_unlock();
4243                                 return ret;
4244                         }
4245                         ret = NOTIFY_OK;
4246                         break;
4247                 case NETDEV_DOWN:
4248                         cxgb4_clip_release(event_dev,
4249                                 (const struct in6_addr *)ifa->addr.s6_addr);
4250                         ret = NOTIFY_OK;
4251                         break;
4252                 default:
4253                         break;
4254                 }
4255         }
4256         rcu_read_unlock();
4257         return ret;
4258 }
4259
4260 static int cxgb4_inet6addr_handler(struct notifier_block *this,
4261                 unsigned long event, void *data)
4262 {
4263         struct inet6_ifaddr *ifa = data;
4264         struct net_device *event_dev;
4265         int ret = NOTIFY_DONE;
4266         struct bonding *bond = netdev_priv(ifa->idev->dev);
4267         struct list_head *iter;
4268         struct slave *slave;
4269         struct pci_dev *first_pdev = NULL;
4270
4271         if (ifa->idev->dev->priv_flags & IFF_802_1Q_VLAN) {
4272                 event_dev = vlan_dev_real_dev(ifa->idev->dev);
4273                 ret = clip_add(event_dev, ifa, event);
4274         } else if (ifa->idev->dev->flags & IFF_MASTER) {
4275                 /* It is possible that two different adapters are bonded in one
4276                  * bond. We need to find such different adapters and add clip
4277                  * in all of them only once.
4278                  */
4279                 read_lock(&bond->lock);
4280                 bond_for_each_slave(bond, slave, iter) {
4281                         if (!first_pdev) {
4282                                 ret = clip_add(slave->dev, ifa, event);
4283                                 /* If clip_add is success then only initialize
4284                                  * first_pdev since it means it is our device
4285                                  */
4286                                 if (ret == NOTIFY_OK)
4287                                         first_pdev = to_pci_dev(
4288                                                         slave->dev->dev.parent);
4289                         } else if (first_pdev !=
4290                                    to_pci_dev(slave->dev->dev.parent))
4291                                         ret = clip_add(slave->dev, ifa, event);
4292                 }
4293                 read_unlock(&bond->lock);
4294         } else
4295                 ret = clip_add(ifa->idev->dev, ifa, event);
4296
4297         return ret;
4298 }
4299
4300 static struct notifier_block cxgb4_inet6addr_notifier = {
4301         .notifier_call = cxgb4_inet6addr_handler
4302 };
4303
4304 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4305  * a physical device.
4306  * The physical device reference is needed to send the actul CLIP command.
4307  */
4308 static int update_dev_clip(struct net_device *root_dev, struct net_device *dev)
4309 {
4310         struct inet6_dev *idev = NULL;
4311         struct inet6_ifaddr *ifa;
4312         int ret = 0;
4313
4314         idev = __in6_dev_get(root_dev);
4315         if (!idev)
4316                 return ret;
4317
4318         read_lock_bh(&idev->lock);
4319         list_for_each_entry(ifa, &idev->addr_list, if_list) {
4320                 ret = cxgb4_clip_get(dev,
4321                                 (const struct in6_addr *)ifa->addr.s6_addr);
4322                 if (ret < 0)
4323                         break;
4324         }
4325         read_unlock_bh(&idev->lock);
4326
4327         return ret;
4328 }
4329
4330 static int update_root_dev_clip(struct net_device *dev)
4331 {
4332         struct net_device *root_dev = NULL;
4333         int i, ret = 0;
4334
4335         /* First populate the real net device's IPv6 addresses */
4336         ret = update_dev_clip(dev, dev);
4337         if (ret)
4338                 return ret;
4339
4340         /* Parse all bond and vlan devices layered on top of the physical dev */
4341         for (i = 0; i < VLAN_N_VID; i++) {
4342                 root_dev = __vlan_find_dev_deep_rcu(dev, htons(ETH_P_8021Q), i);
4343                 if (!root_dev)
4344                         continue;
4345
4346                 ret = update_dev_clip(root_dev, dev);
4347                 if (ret)
4348                         break;
4349         }
4350         return ret;
4351 }
4352
4353 static void update_clip(const struct adapter *adap)
4354 {
4355         int i;
4356         struct net_device *dev;
4357         int ret;
4358
4359         rcu_read_lock();
4360
4361         for (i = 0; i < MAX_NPORTS; i++) {
4362                 dev = adap->port[i];
4363                 ret = 0;
4364
4365                 if (dev)
4366                         ret = update_root_dev_clip(dev);
4367
4368                 if (ret < 0)
4369                         break;
4370         }
4371         rcu_read_unlock();
4372 }
4373
4374 /**
4375  *      cxgb_up - enable the adapter
4376  *      @adap: adapter being enabled
4377  *
4378  *      Called when the first port is enabled, this function performs the
4379  *      actions necessary to make an adapter operational, such as completing
4380  *      the initialization of HW modules, and enabling interrupts.
4381  *
4382  *      Must be called with the rtnl lock held.
4383  */
4384 static int cxgb_up(struct adapter *adap)
4385 {
4386         int err;
4387
4388         err = setup_sge_queues(adap);
4389         if (err)
4390                 goto out;
4391         err = setup_rss(adap);
4392         if (err)
4393                 goto freeq;
4394
4395         if (adap->flags & USING_MSIX) {
4396                 name_msix_vecs(adap);
4397                 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
4398                                   adap->msix_info[0].desc, adap);
4399                 if (err)
4400                         goto irq_err;
4401
4402                 err = request_msix_queue_irqs(adap);
4403                 if (err) {
4404                         free_irq(adap->msix_info[0].vec, adap);
4405                         goto irq_err;
4406                 }
4407         } else {
4408                 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
4409                                   (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
4410                                   adap->port[0]->name, adap);
4411                 if (err)
4412                         goto irq_err;
4413         }
4414         enable_rx(adap);
4415         t4_sge_start(adap);
4416         t4_intr_enable(adap);
4417         adap->flags |= FULL_INIT_DONE;
4418         notify_ulds(adap, CXGB4_STATE_UP);
4419         update_clip(adap);
4420  out:
4421         return err;
4422  irq_err:
4423         dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
4424  freeq:
4425         t4_free_sge_resources(adap);
4426         goto out;
4427 }
4428
4429 static void cxgb_down(struct adapter *adapter)
4430 {
4431         t4_intr_disable(adapter);
4432         cancel_work_sync(&adapter->tid_release_task);
4433         cancel_work_sync(&adapter->db_full_task);
4434         cancel_work_sync(&adapter->db_drop_task);
4435         adapter->tid_release_task_busy = false;
4436         adapter->tid_release_head = NULL;
4437
4438         if (adapter->flags & USING_MSIX) {
4439                 free_msix_queue_irqs(adapter);
4440                 free_irq(adapter->msix_info[0].vec, adapter);
4441         } else
4442                 free_irq(adapter->pdev->irq, adapter);
4443         quiesce_rx(adapter);
4444         t4_sge_stop(adapter);
4445         t4_free_sge_resources(adapter);
4446         adapter->flags &= ~FULL_INIT_DONE;
4447 }
4448
4449 /*
4450  * net_device operations
4451  */
4452 static int cxgb_open(struct net_device *dev)
4453 {
4454         int err;
4455         struct port_info *pi = netdev_priv(dev);
4456         struct adapter *adapter = pi->adapter;
4457
4458         netif_carrier_off(dev);
4459
4460         if (!(adapter->flags & FULL_INIT_DONE)) {
4461                 err = cxgb_up(adapter);
4462                 if (err < 0)
4463                         return err;
4464         }
4465
4466         err = link_start(dev);
4467         if (!err)
4468                 netif_tx_start_all_queues(dev);
4469         return err;
4470 }
4471
4472 static int cxgb_close(struct net_device *dev)
4473 {
4474         struct port_info *pi = netdev_priv(dev);
4475         struct adapter *adapter = pi->adapter;
4476
4477         netif_tx_stop_all_queues(dev);
4478         netif_carrier_off(dev);
4479         return t4_enable_vi(adapter, adapter->fn, pi->viid, false, false);
4480 }
4481
4482 /* Return an error number if the indicated filter isn't writable ...
4483  */
4484 static int writable_filter(struct filter_entry *f)
4485 {
4486         if (f->locked)
4487                 return -EPERM;
4488         if (f->pending)
4489                 return -EBUSY;
4490
4491         return 0;
4492 }
4493
4494 /* Delete the filter at the specified index (if valid).  The checks for all
4495  * the common problems with doing this like the filter being locked, currently
4496  * pending in another operation, etc.
4497  */
4498 static int delete_filter(struct adapter *adapter, unsigned int fidx)
4499 {
4500         struct filter_entry *f;
4501         int ret;
4502
4503         if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
4504                 return -EINVAL;
4505
4506         f = &adapter->tids.ftid_tab[fidx];
4507         ret = writable_filter(f);
4508         if (ret)
4509                 return ret;
4510         if (f->valid)
4511                 return del_filter_wr(adapter, fidx);
4512
4513         return 0;
4514 }
4515
4516 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
4517                 __be32 sip, __be16 sport, __be16 vlan,
4518                 unsigned int queue, unsigned char port, unsigned char mask)
4519 {
4520         int ret;
4521         struct filter_entry *f;
4522         struct adapter *adap;
4523         int i;
4524         u8 *val;
4525
4526         adap = netdev2adap(dev);
4527
4528         /* Adjust stid to correct filter index */
4529         stid -= adap->tids.sftid_base;
4530         stid += adap->tids.nftids;
4531
4532         /* Check to make sure the filter requested is writable ...
4533          */
4534         f = &adap->tids.ftid_tab[stid];
4535         ret = writable_filter(f);
4536         if (ret)
4537                 return ret;
4538
4539         /* Clear out any old resources being used by the filter before
4540          * we start constructing the new filter.
4541          */
4542         if (f->valid)
4543                 clear_filter(adap, f);
4544
4545         /* Clear out filter specifications */
4546         memset(&f->fs, 0, sizeof(struct ch_filter_specification));
4547         f->fs.val.lport = cpu_to_be16(sport);
4548         f->fs.mask.lport  = ~0;
4549         val = (u8 *)&sip;
4550         if ((val[0] | val[1] | val[2] | val[3]) != 0) {
4551                 for (i = 0; i < 4; i++) {
4552                         f->fs.val.lip[i] = val[i];
4553                         f->fs.mask.lip[i] = ~0;
4554                 }
4555                 if (adap->params.tp.vlan_pri_map & F_PORT) {
4556                         f->fs.val.iport = port;
4557                         f->fs.mask.iport = mask;
4558                 }
4559         }
4560
4561         if (adap->params.tp.vlan_pri_map & F_PROTOCOL) {
4562                 f->fs.val.proto = IPPROTO_TCP;
4563                 f->fs.mask.proto = ~0;
4564         }
4565
4566         f->fs.dirsteer = 1;
4567         f->fs.iq = queue;
4568         /* Mark filter as locked */
4569         f->locked = 1;
4570         f->fs.rpttid = 1;
4571
4572         ret = set_filter_wr(adap, stid);
4573         if (ret) {
4574                 clear_filter(adap, f);
4575                 return ret;
4576         }
4577
4578         return 0;
4579 }
4580 EXPORT_SYMBOL(cxgb4_create_server_filter);
4581
4582 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
4583                 unsigned int queue, bool ipv6)
4584 {
4585         int ret;
4586         struct filter_entry *f;
4587         struct adapter *adap;
4588
4589         adap = netdev2adap(dev);
4590
4591         /* Adjust stid to correct filter index */
4592         stid -= adap->tids.sftid_base;
4593         stid += adap->tids.nftids;
4594
4595         f = &adap->tids.ftid_tab[stid];
4596         /* Unlock the filter */
4597         f->locked = 0;
4598
4599         ret = delete_filter(adap, stid);
4600         if (ret)
4601                 return ret;
4602
4603         return 0;
4604 }
4605 EXPORT_SYMBOL(cxgb4_remove_server_filter);
4606
4607 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
4608                                                 struct rtnl_link_stats64 *ns)
4609 {
4610         struct port_stats stats;
4611         struct port_info *p = netdev_priv(dev);
4612         struct adapter *adapter = p->adapter;
4613
4614         /* Block retrieving statistics during EEH error
4615          * recovery. Otherwise, the recovery might fail
4616          * and the PCI device will be removed permanently
4617          */
4618         spin_lock(&adapter->stats_lock);
4619         if (!netif_device_present(dev)) {
4620                 spin_unlock(&adapter->stats_lock);
4621                 return ns;
4622         }
4623         t4_get_port_stats(adapter, p->tx_chan, &stats);
4624         spin_unlock(&adapter->stats_lock);
4625
4626         ns->tx_bytes   = stats.tx_octets;
4627         ns->tx_packets = stats.tx_frames;
4628         ns->rx_bytes   = stats.rx_octets;
4629         ns->rx_packets = stats.rx_frames;
4630         ns->multicast  = stats.rx_mcast_frames;
4631
4632         /* detailed rx_errors */
4633         ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
4634                                stats.rx_runt;
4635         ns->rx_over_errors   = 0;
4636         ns->rx_crc_errors    = stats.rx_fcs_err;
4637         ns->rx_frame_errors  = stats.rx_symbol_err;
4638         ns->rx_fifo_errors   = stats.rx_ovflow0 + stats.rx_ovflow1 +
4639                                stats.rx_ovflow2 + stats.rx_ovflow3 +
4640                                stats.rx_trunc0 + stats.rx_trunc1 +
4641                                stats.rx_trunc2 + stats.rx_trunc3;
4642         ns->rx_missed_errors = 0;
4643
4644         /* detailed tx_errors */
4645         ns->tx_aborted_errors   = 0;
4646         ns->tx_carrier_errors   = 0;
4647         ns->tx_fifo_errors      = 0;
4648         ns->tx_heartbeat_errors = 0;
4649         ns->tx_window_errors    = 0;
4650
4651         ns->tx_errors = stats.tx_error_frames;
4652         ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
4653                 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
4654         return ns;
4655 }
4656
4657 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
4658 {
4659         unsigned int mbox;
4660         int ret = 0, prtad, devad;
4661         struct port_info *pi = netdev_priv(dev);
4662         struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
4663
4664         switch (cmd) {
4665         case SIOCGMIIPHY:
4666                 if (pi->mdio_addr < 0)
4667                         return -EOPNOTSUPP;
4668                 data->phy_id = pi->mdio_addr;
4669                 break;
4670         case SIOCGMIIREG:
4671         case SIOCSMIIREG:
4672                 if (mdio_phy_id_is_c45(data->phy_id)) {
4673                         prtad = mdio_phy_id_prtad(data->phy_id);
4674                         devad = mdio_phy_id_devad(data->phy_id);
4675                 } else if (data->phy_id < 32) {
4676                         prtad = data->phy_id;
4677                         devad = 0;
4678                         data->reg_num &= 0x1f;
4679                 } else
4680                         return -EINVAL;
4681
4682                 mbox = pi->adapter->fn;
4683                 if (cmd == SIOCGMIIREG)
4684                         ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
4685                                          data->reg_num, &data->val_out);
4686                 else
4687                         ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
4688                                          data->reg_num, data->val_in);
4689                 break;
4690         default:
4691                 return -EOPNOTSUPP;
4692         }
4693         return ret;
4694 }
4695
4696 static void cxgb_set_rxmode(struct net_device *dev)
4697 {
4698         /* unfortunately we can't return errors to the stack */
4699         set_rxmode(dev, -1, false);
4700 }
4701
4702 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
4703 {
4704         int ret;
4705         struct port_info *pi = netdev_priv(dev);
4706
4707         if (new_mtu < 81 || new_mtu > MAX_MTU)         /* accommodate SACK */
4708                 return -EINVAL;
4709         ret = t4_set_rxmode(pi->adapter, pi->adapter->fn, pi->viid, new_mtu, -1,
4710                             -1, -1, -1, true);
4711         if (!ret)
4712                 dev->mtu = new_mtu;
4713         return ret;
4714 }
4715
4716 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
4717 {
4718         int ret;
4719         struct sockaddr *addr = p;
4720         struct port_info *pi = netdev_priv(dev);
4721
4722         if (!is_valid_ether_addr(addr->sa_data))
4723                 return -EADDRNOTAVAIL;
4724
4725         ret = t4_change_mac(pi->adapter, pi->adapter->fn, pi->viid,
4726                             pi->xact_addr_filt, addr->sa_data, true, true);
4727         if (ret < 0)
4728                 return ret;
4729
4730         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4731         pi->xact_addr_filt = ret;
4732         return 0;
4733 }
4734
4735 #ifdef CONFIG_NET_POLL_CONTROLLER
4736 static void cxgb_netpoll(struct net_device *dev)
4737 {
4738         struct port_info *pi = netdev_priv(dev);
4739         struct adapter *adap = pi->adapter;
4740
4741         if (adap->flags & USING_MSIX) {
4742                 int i;
4743                 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
4744
4745                 for (i = pi->nqsets; i; i--, rx++)
4746                         t4_sge_intr_msix(0, &rx->rspq);
4747         } else
4748                 t4_intr_handler(adap)(0, adap);
4749 }
4750 #endif
4751
4752 static const struct net_device_ops cxgb4_netdev_ops = {
4753         .ndo_open             = cxgb_open,
4754         .ndo_stop             = cxgb_close,
4755         .ndo_start_xmit       = t4_eth_xmit,
4756         .ndo_select_queue     = cxgb_select_queue,
4757         .ndo_get_stats64      = cxgb_get_stats,
4758         .ndo_set_rx_mode      = cxgb_set_rxmode,
4759         .ndo_set_mac_address  = cxgb_set_mac_addr,
4760         .ndo_set_features     = cxgb_set_features,
4761         .ndo_validate_addr    = eth_validate_addr,
4762         .ndo_do_ioctl         = cxgb_ioctl,
4763         .ndo_change_mtu       = cxgb_change_mtu,
4764 #ifdef CONFIG_NET_POLL_CONTROLLER
4765         .ndo_poll_controller  = cxgb_netpoll,
4766 #endif
4767 };
4768
4769 void t4_fatal_err(struct adapter *adap)
4770 {
4771         t4_set_reg_field(adap, SGE_CONTROL, GLOBALENABLE, 0);
4772         t4_intr_disable(adap);
4773         dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
4774 }
4775
4776 /* Return the specified PCI-E Configuration Space register from our Physical
4777  * Function.  We try first via a Firmware LDST Command since we prefer to let
4778  * the firmware own all of these registers, but if that fails we go for it
4779  * directly ourselves.
4780  */
4781 static u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
4782 {
4783         struct fw_ldst_cmd ldst_cmd;
4784         u32 val;
4785         int ret;
4786
4787         /* Construct and send the Firmware LDST Command to retrieve the
4788          * specified PCI-E Configuration Space register.
4789          */
4790         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
4791         ldst_cmd.op_to_addrspace =
4792                 htonl(FW_CMD_OP(FW_LDST_CMD) |
4793                       FW_CMD_REQUEST |
4794                       FW_CMD_READ |
4795                       FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE));
4796         ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
4797         ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS(1);
4798         ldst_cmd.u.pcie.ctrl_to_fn =
4799                 (FW_LDST_CMD_LC | FW_LDST_CMD_FN(adap->fn));
4800         ldst_cmd.u.pcie.r = reg;
4801         ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
4802                          &ldst_cmd);
4803
4804         /* If the LDST Command suucceeded, exctract the returned register
4805          * value.  Otherwise read it directly ourself.
4806          */
4807         if (ret == 0)
4808                 val = ntohl(ldst_cmd.u.pcie.data[0]);
4809         else
4810                 t4_hw_pci_read_cfg4(adap, reg, &val);
4811
4812         return val;
4813 }
4814
4815 static void setup_memwin(struct adapter *adap)
4816 {
4817         u32 mem_win0_base, mem_win1_base, mem_win2_base, mem_win2_aperture;
4818
4819         if (is_t4(adap->params.chip)) {
4820                 u32 bar0;
4821
4822                 /* Truncation intentional: we only read the bottom 32-bits of
4823                  * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
4824                  * mechanism to read BAR0 instead of using
4825                  * pci_resource_start() because we could be operating from
4826                  * within a Virtual Machine which is trapping our accesses to
4827                  * our Configuration Space and we need to set up the PCI-E
4828                  * Memory Window decoders with the actual addresses which will
4829                  * be coming across the PCI-E link.
4830                  */
4831                 bar0 = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_0);
4832                 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
4833                 adap->t4_bar0 = bar0;
4834
4835                 mem_win0_base = bar0 + MEMWIN0_BASE;
4836                 mem_win1_base = bar0 + MEMWIN1_BASE;
4837                 mem_win2_base = bar0 + MEMWIN2_BASE;
4838                 mem_win2_aperture = MEMWIN2_APERTURE;
4839         } else {
4840                 /* For T5, only relative offset inside the PCIe BAR is passed */
4841                 mem_win0_base = MEMWIN0_BASE;
4842                 mem_win1_base = MEMWIN1_BASE;
4843                 mem_win2_base = MEMWIN2_BASE_T5;
4844                 mem_win2_aperture = MEMWIN2_APERTURE_T5;
4845         }
4846         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 0),
4847                      mem_win0_base | BIR(0) |
4848                      WINDOW(ilog2(MEMWIN0_APERTURE) - 10));
4849         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 1),
4850                      mem_win1_base | BIR(0) |
4851                      WINDOW(ilog2(MEMWIN1_APERTURE) - 10));
4852         t4_write_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2),
4853                      mem_win2_base | BIR(0) |
4854                      WINDOW(ilog2(mem_win2_aperture) - 10));
4855         t4_read_reg(adap, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 2));
4856 }
4857
4858 static void setup_memwin_rdma(struct adapter *adap)
4859 {
4860         if (adap->vres.ocq.size) {
4861                 u32 start;
4862                 unsigned int sz_kb;
4863
4864                 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
4865                 start &= PCI_BASE_ADDRESS_MEM_MASK;
4866                 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
4867                 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
4868                 t4_write_reg(adap,
4869                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, 3),
4870                              start | BIR(1) | WINDOW(ilog2(sz_kb)));
4871                 t4_write_reg(adap,
4872                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3),
4873                              adap->vres.ocq.start);
4874                 t4_read_reg(adap,
4875                             PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, 3));
4876         }
4877 }
4878
4879 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4880 {
4881         u32 v;
4882         int ret;
4883
4884         /* get device capabilities */
4885         memset(c, 0, sizeof(*c));
4886         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4887                                FW_CMD_REQUEST | FW_CMD_READ);
4888         c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
4889         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), c);
4890         if (ret < 0)
4891                 return ret;
4892
4893         /* select capabilities we'll be using */
4894         if (c->niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
4895                 if (!vf_acls)
4896                         c->niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
4897                 else
4898                         c->niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
4899         } else if (vf_acls) {
4900                 dev_err(adap->pdev_dev, "virtualization ACLs not supported");
4901                 return ret;
4902         }
4903         c->op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
4904                                FW_CMD_REQUEST | FW_CMD_WRITE);
4905         ret = t4_wr_mbox(adap, adap->fn, c, sizeof(*c), NULL);
4906         if (ret < 0)
4907                 return ret;
4908
4909         ret = t4_config_glbl_rss(adap, adap->fn,
4910                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
4911                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
4912                                  FW_RSS_GLB_CONFIG_CMD_TNLALLLKP);
4913         if (ret < 0)
4914                 return ret;
4915
4916         ret = t4_cfg_pfvf(adap, adap->fn, adap->fn, 0, MAX_EGRQ, 64, MAX_INGQ,
4917                           0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF, FW_CMD_CAP_PF);
4918         if (ret < 0)
4919                 return ret;
4920
4921         t4_sge_init(adap);
4922
4923         /* tweak some settings */
4924         t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849);
4925         t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4926         t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG);
4927         v = t4_read_reg(adap, TP_PIO_DATA);
4928         t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR);
4929
4930         /* first 4 Tx modulation queues point to consecutive Tx channels */
4931         adap->params.tp.tx_modq_map = 0xE4;
4932         t4_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
4933                      V_TX_MOD_QUEUE_REQ_MAP(adap->params.tp.tx_modq_map));
4934
4935         /* associate each Tx modulation queue with consecutive Tx channels */
4936         v = 0x84218421;
4937         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4938                           &v, 1, A_TP_TX_SCHED_HDR);
4939         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4940                           &v, 1, A_TP_TX_SCHED_FIFO);
4941         t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA,
4942                           &v, 1, A_TP_TX_SCHED_PCMD);
4943
4944 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
4945         if (is_offload(adap)) {
4946                 t4_write_reg(adap, A_TP_TX_MOD_QUEUE_WEIGHT0,
4947                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4948                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4949                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4950                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4951                 t4_write_reg(adap, A_TP_TX_MOD_CHANNEL_WEIGHT,
4952                              V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4953                              V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4954                              V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
4955                              V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
4956         }
4957
4958         /* get basic stuff going */
4959         return t4_early_init(adap, adap->fn);
4960 }
4961
4962 /*
4963  * Max # of ATIDs.  The absolute HW max is 16K but we keep it lower.
4964  */
4965 #define MAX_ATIDS 8192U
4966
4967 /*
4968  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
4969  *
4970  * If the firmware we're dealing with has Configuration File support, then
4971  * we use that to perform all configuration
4972  */
4973
4974 /*
4975  * Tweak configuration based on module parameters, etc.  Most of these have
4976  * defaults assigned to them by Firmware Configuration Files (if we're using
4977  * them) but need to be explicitly set if we're using hard-coded
4978  * initialization.  But even in the case of using Firmware Configuration
4979  * Files, we'd like to expose the ability to change these via module
4980  * parameters so these are essentially common tweaks/settings for
4981  * Configuration Files and hard-coded initialization ...
4982  */
4983 static int adap_init0_tweaks(struct adapter *adapter)
4984 {
4985         /*
4986          * Fix up various Host-Dependent Parameters like Page Size, Cache
4987          * Line Size, etc.  The firmware default is for a 4KB Page Size and
4988          * 64B Cache Line Size ...
4989          */
4990         t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
4991
4992         /*
4993          * Process module parameters which affect early initialization.
4994          */
4995         if (rx_dma_offset != 2 && rx_dma_offset != 0) {
4996                 dev_err(&adapter->pdev->dev,
4997                         "Ignoring illegal rx_dma_offset=%d, using 2\n",
4998                         rx_dma_offset);
4999                 rx_dma_offset = 2;
5000         }
5001         t4_set_reg_field(adapter, SGE_CONTROL,
5002                          PKTSHIFT_MASK,
5003                          PKTSHIFT(rx_dma_offset));
5004
5005         /*
5006          * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5007          * adds the pseudo header itself.
5008          */
5009         t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG,
5010                                CSUM_HAS_PSEUDO_HDR, 0);
5011
5012         return 0;
5013 }
5014
5015 /*
5016  * Attempt to initialize the adapter via a Firmware Configuration File.
5017  */
5018 static int adap_init0_config(struct adapter *adapter, int reset)
5019 {
5020         struct fw_caps_config_cmd caps_cmd;
5021         const struct firmware *cf;
5022         unsigned long mtype = 0, maddr = 0;
5023         u32 finiver, finicsum, cfcsum;
5024         int ret;
5025         int config_issued = 0;
5026         char *fw_config_file, fw_config_file_path[256];
5027         char *config_name = NULL;
5028
5029         /*
5030          * Reset device if necessary.
5031          */
5032         if (reset) {
5033                 ret = t4_fw_reset(adapter, adapter->mbox,
5034                                   PIORSTMODE | PIORST);
5035                 if (ret < 0)
5036                         goto bye;
5037         }
5038
5039         /*
5040          * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5041          * then use that.  Otherwise, use the configuration file stored
5042          * in the adapter flash ...
5043          */
5044         switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
5045         case CHELSIO_T4:
5046                 fw_config_file = FW4_CFNAME;
5047                 break;
5048         case CHELSIO_T5:
5049                 fw_config_file = FW5_CFNAME;
5050                 break;
5051         default:
5052                 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
5053                        adapter->pdev->device);
5054                 ret = -EINVAL;
5055                 goto bye;
5056         }
5057
5058         ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
5059         if (ret < 0) {
5060                 config_name = "On FLASH";
5061                 mtype = FW_MEMTYPE_CF_FLASH;
5062                 maddr = t4_flash_cfg_addr(adapter);
5063         } else {
5064                 u32 params[7], val[7];
5065
5066                 sprintf(fw_config_file_path,
5067                         "/lib/firmware/%s", fw_config_file);
5068                 config_name = fw_config_file_path;
5069
5070                 if (cf->size >= FLASH_CFG_MAX_SIZE)
5071                         ret = -ENOMEM;
5072                 else {
5073                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5074                              FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5075                         ret = t4_query_params(adapter, adapter->mbox,
5076                                               adapter->fn, 0, 1, params, val);
5077                         if (ret == 0) {
5078                                 /*
5079                                  * For t4_memory_write() below addresses and
5080                                  * sizes have to be in terms of multiples of 4
5081                                  * bytes.  So, if the Configuration File isn't
5082                                  * a multiple of 4 bytes in length we'll have
5083                                  * to write that out separately since we can't
5084                                  * guarantee that the bytes following the
5085                                  * residual byte in the buffer returned by
5086                                  * request_firmware() are zeroed out ...
5087                                  */
5088                                 size_t resid = cf->size & 0x3;
5089                                 size_t size = cf->size & ~0x3;
5090                                 __be32 *data = (__be32 *)cf->data;
5091
5092                                 mtype = FW_PARAMS_PARAM_Y_GET(val[0]);
5093                                 maddr = FW_PARAMS_PARAM_Z_GET(val[0]) << 16;
5094
5095                                 ret = t4_memory_write(adapter, mtype, maddr,
5096                                                       size, data);
5097                                 if (ret == 0 && resid != 0) {
5098                                         union {
5099                                                 __be32 word;
5100                                                 char buf[4];
5101                                         } last;
5102                                         int i;
5103
5104                                         last.word = data[size >> 2];
5105                                         for (i = resid; i < 4; i++)
5106                                                 last.buf[i] = 0;
5107                                         ret = t4_memory_write(adapter, mtype,
5108                                                               maddr + size,
5109                                                               4, &last.word);
5110                                 }
5111                         }
5112                 }
5113
5114                 release_firmware(cf);
5115                 if (ret)
5116                         goto bye;
5117         }
5118
5119         /*
5120          * Issue a Capability Configuration command to the firmware to get it
5121          * to parse the Configuration File.  We don't use t4_fw_config_file()
5122          * because we want the ability to modify various features after we've
5123          * processed the configuration file ...
5124          */
5125         memset(&caps_cmd, 0, sizeof(caps_cmd));
5126         caps_cmd.op_to_write =
5127                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5128                       FW_CMD_REQUEST |
5129                       FW_CMD_READ);
5130         caps_cmd.cfvalid_to_len16 =
5131                 htonl(FW_CAPS_CONFIG_CMD_CFVALID |
5132                       FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
5133                       FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
5134                       FW_LEN16(caps_cmd));
5135         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5136                          &caps_cmd);
5137
5138         /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5139          * Configuration File in FLASH), our last gasp effort is to use the
5140          * Firmware Configuration File which is embedded in the firmware.  A
5141          * very few early versions of the firmware didn't have one embedded
5142          * but we can ignore those.
5143          */
5144         if (ret == -ENOENT) {
5145                 memset(&caps_cmd, 0, sizeof(caps_cmd));
5146                 caps_cmd.op_to_write =
5147                         htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5148                                         FW_CMD_REQUEST |
5149                                         FW_CMD_READ);
5150                 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5151                 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
5152                                 sizeof(caps_cmd), &caps_cmd);
5153                 config_name = "Firmware Default";
5154         }
5155
5156         config_issued = 1;
5157         if (ret < 0)
5158                 goto bye;
5159
5160         finiver = ntohl(caps_cmd.finiver);
5161         finicsum = ntohl(caps_cmd.finicsum);
5162         cfcsum = ntohl(caps_cmd.cfcsum);
5163         if (finicsum != cfcsum)
5164                 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
5165                          "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5166                          finicsum, cfcsum);
5167
5168         /*
5169          * And now tell the firmware to use the configuration we just loaded.
5170          */
5171         caps_cmd.op_to_write =
5172                 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5173                       FW_CMD_REQUEST |
5174                       FW_CMD_WRITE);
5175         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5176         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5177                          NULL);
5178         if (ret < 0)
5179                 goto bye;
5180
5181         /*
5182          * Tweak configuration based on system architecture, module
5183          * parameters, etc.
5184          */
5185         ret = adap_init0_tweaks(adapter);
5186         if (ret < 0)
5187                 goto bye;
5188
5189         /*
5190          * And finally tell the firmware to initialize itself using the
5191          * parameters from the Configuration File.
5192          */
5193         ret = t4_fw_initialize(adapter, adapter->mbox);
5194         if (ret < 0)
5195                 goto bye;
5196
5197         /*
5198          * Return successfully and note that we're operating with parameters
5199          * not supplied by the driver, rather than from hard-wired
5200          * initialization constants burried in the driver.
5201          */
5202         adapter->flags |= USING_SOFT_PARAMS;
5203         dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
5204                  "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5205                  config_name, finiver, cfcsum);
5206         return 0;
5207
5208         /*
5209          * Something bad happened.  Return the error ...  (If the "error"
5210          * is that there's no Configuration File on the adapter we don't
5211          * want to issue a warning since this is fairly common.)
5212          */
5213 bye:
5214         if (config_issued && ret != -ENOENT)
5215                 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
5216                          config_name, -ret);
5217         return ret;
5218 }
5219
5220 /*
5221  * Attempt to initialize the adapter via hard-coded, driver supplied
5222  * parameters ...
5223  */
5224 static int adap_init0_no_config(struct adapter *adapter, int reset)
5225 {
5226         struct sge *s = &adapter->sge;
5227         struct fw_caps_config_cmd caps_cmd;
5228         u32 v;
5229         int i, ret;
5230
5231         /*
5232          * Reset device if necessary
5233          */
5234         if (reset) {
5235                 ret = t4_fw_reset(adapter, adapter->mbox,
5236                                   PIORSTMODE | PIORST);
5237                 if (ret < 0)
5238                         goto bye;
5239         }
5240
5241         /*
5242          * Get device capabilities and select which we'll be using.
5243          */
5244         memset(&caps_cmd, 0, sizeof(caps_cmd));
5245         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5246                                      FW_CMD_REQUEST | FW_CMD_READ);
5247         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5248         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5249                          &caps_cmd);
5250         if (ret < 0)
5251                 goto bye;
5252
5253         if (caps_cmd.niccaps & htons(FW_CAPS_CONFIG_NIC_VM)) {
5254                 if (!vf_acls)
5255                         caps_cmd.niccaps ^= htons(FW_CAPS_CONFIG_NIC_VM);
5256                 else
5257                         caps_cmd.niccaps = htons(FW_CAPS_CONFIG_NIC_VM);
5258         } else if (vf_acls) {
5259                 dev_err(adapter->pdev_dev, "virtualization ACLs not supported");
5260                 goto bye;
5261         }
5262         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5263                               FW_CMD_REQUEST | FW_CMD_WRITE);
5264         ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
5265                          NULL);
5266         if (ret < 0)
5267                 goto bye;
5268
5269         /*
5270          * Tweak configuration based on system architecture, module
5271          * parameters, etc.
5272          */
5273         ret = adap_init0_tweaks(adapter);
5274         if (ret < 0)
5275                 goto bye;
5276
5277         /*
5278          * Select RSS Global Mode we want to use.  We use "Basic Virtual"
5279          * mode which maps each Virtual Interface to its own section of
5280          * the RSS Table and we turn on all map and hash enables ...
5281          */
5282         adapter->flags |= RSS_TNLALLLOOKUP;
5283         ret = t4_config_glbl_rss(adapter, adapter->mbox,
5284                                  FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
5285                                  FW_RSS_GLB_CONFIG_CMD_TNLMAPEN |
5286                                  FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ |
5287                                  ((adapter->flags & RSS_TNLALLLOOKUP) ?
5288                                         FW_RSS_GLB_CONFIG_CMD_TNLALLLKP : 0));
5289         if (ret < 0)
5290                 goto bye;
5291
5292         /*
5293          * Set up our own fundamental resource provisioning ...
5294          */
5295         ret = t4_cfg_pfvf(adapter, adapter->mbox, adapter->fn, 0,
5296                           PFRES_NEQ, PFRES_NETHCTRL,
5297                           PFRES_NIQFLINT, PFRES_NIQ,
5298                           PFRES_TC, PFRES_NVI,
5299                           FW_PFVF_CMD_CMASK_MASK,
5300                           pfvfres_pmask(adapter, adapter->fn, 0),
5301                           PFRES_NEXACTF,
5302                           PFRES_R_CAPS, PFRES_WX_CAPS);
5303         if (ret < 0)
5304                 goto bye;
5305
5306         /*
5307          * Perform low level SGE initialization.  We need to do this before we
5308          * send the firmware the INITIALIZE command because that will cause
5309          * any other PF Drivers which are waiting for the Master
5310          * Initialization to proceed forward.
5311          */
5312         for (i = 0; i < SGE_NTIMERS - 1; i++)
5313                 s->timer_val[i] = min(intr_holdoff[i], MAX_SGE_TIMERVAL);
5314         s->timer_val[SGE_NTIMERS - 1] = MAX_SGE_TIMERVAL;
5315         s->counter_val[0] = 1;
5316         for (i = 1; i < SGE_NCOUNTERS; i++)
5317                 s->counter_val[i] = min(intr_cnt[i - 1],
5318                                         THRESHOLD_0_GET(THRESHOLD_0_MASK));
5319         t4_sge_init(adapter);
5320
5321 #ifdef CONFIG_PCI_IOV
5322         /*
5323          * Provision resource limits for Virtual Functions.  We currently
5324          * grant them all the same static resource limits except for the Port
5325          * Access Rights Mask which we're assigning based on the PF.  All of
5326          * the static provisioning stuff for both the PF and VF really needs
5327          * to be managed in a persistent manner for each device which the
5328          * firmware controls.
5329          */
5330         {
5331                 int pf, vf;
5332
5333                 for (pf = 0; pf < ARRAY_SIZE(num_vf); pf++) {
5334                         if (num_vf[pf] <= 0)
5335                                 continue;
5336
5337                         /* VF numbering starts at 1! */
5338                         for (vf = 1; vf <= num_vf[pf]; vf++) {
5339                                 ret = t4_cfg_pfvf(adapter, adapter->mbox,
5340                                                   pf, vf,
5341                                                   VFRES_NEQ, VFRES_NETHCTRL,
5342                                                   VFRES_NIQFLINT, VFRES_NIQ,
5343                                                   VFRES_TC, VFRES_NVI,
5344                                                   FW_PFVF_CMD_CMASK_MASK,
5345                                                   pfvfres_pmask(
5346                                                   adapter, pf, vf),
5347                                                   VFRES_NEXACTF,
5348                                                   VFRES_R_CAPS, VFRES_WX_CAPS);
5349                                 if (ret < 0)
5350                                         dev_warn(adapter->pdev_dev,
5351                                                  "failed to "\
5352                                                  "provision pf/vf=%d/%d; "
5353                                                  "err=%d\n", pf, vf, ret);
5354                         }
5355                 }
5356         }
5357 #endif
5358
5359         /*
5360          * Set up the default filter mode.  Later we'll want to implement this
5361          * via a firmware command, etc. ...  This needs to be done before the
5362          * firmare initialization command ...  If the selected set of fields
5363          * isn't equal to the default value, we'll need to make sure that the
5364          * field selections will fit in the 36-bit budget.
5365          */
5366         if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
5367                 int j, bits = 0;
5368
5369                 for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
5370                         switch (tp_vlan_pri_map & (1 << j)) {
5371                         case 0:
5372                                 /* compressed filter field not enabled */
5373                                 break;
5374                         case FCOE_MASK:
5375                                 bits +=  1;
5376                                 break;
5377                         case PORT_MASK:
5378                                 bits +=  3;
5379                                 break;
5380                         case VNIC_ID_MASK:
5381                                 bits += 17;
5382                                 break;
5383                         case VLAN_MASK:
5384                                 bits += 17;
5385                                 break;
5386                         case TOS_MASK:
5387                                 bits +=  8;
5388                                 break;
5389                         case PROTOCOL_MASK:
5390                                 bits +=  8;
5391                                 break;
5392                         case ETHERTYPE_MASK:
5393                                 bits += 16;
5394                                 break;
5395                         case MACMATCH_MASK:
5396                                 bits +=  9;
5397                                 break;
5398                         case MPSHITTYPE_MASK:
5399                                 bits +=  3;
5400                                 break;
5401                         case FRAGMENTATION_MASK:
5402                                 bits +=  1;
5403                                 break;
5404                         }
5405
5406                 if (bits > 36) {
5407                         dev_err(adapter->pdev_dev,
5408                                 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5409                                 " using %#x\n", tp_vlan_pri_map, bits,
5410                                 TP_VLAN_PRI_MAP_DEFAULT);
5411                         tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
5412                 }
5413         }
5414         v = tp_vlan_pri_map;
5415         t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA,
5416                           &v, 1, TP_VLAN_PRI_MAP);
5417
5418         /*
5419          * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5420          * to support any of the compressed filter fields above.  Newer
5421          * versions of the firmware do this automatically but it doesn't hurt
5422          * to set it here.  Meanwhile, we do _not_ need to set Lookup Every
5423          * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5424          * since the firmware automatically turns this on and off when we have
5425          * a non-zero number of filters active (since it does have a
5426          * performance impact).
5427          */
5428         if (tp_vlan_pri_map)
5429                 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG,
5430                                  FIVETUPLELOOKUP_MASK,
5431                                  FIVETUPLELOOKUP_MASK);
5432
5433         /*
5434          * Tweak some settings.
5435          */
5436         t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) |
5437                      RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5438                      PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5439                      KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5440
5441         /*
5442          * Get basic stuff going by issuing the Firmware Initialize command.
5443          * Note that this _must_ be after all PFVF commands ...
5444          */
5445         ret = t4_fw_initialize(adapter, adapter->mbox);
5446         if (ret < 0)
5447                 goto bye;
5448
5449         /*
5450          * Return successfully!
5451          */
5452         dev_info(adapter->pdev_dev, "Successfully configured using built-in "\
5453                  "driver parameters\n");
5454         return 0;
5455
5456         /*
5457          * Something bad happened.  Return the error ...
5458          */
5459 bye:
5460         return ret;
5461 }
5462
5463 static struct fw_info fw_info_array[] = {
5464         {
5465                 .chip = CHELSIO_T4,
5466                 .fs_name = FW4_CFNAME,
5467                 .fw_mod_name = FW4_FNAME,
5468                 .fw_hdr = {
5469                         .chip = FW_HDR_CHIP_T4,
5470                         .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
5471                         .intfver_nic = FW_INTFVER(T4, NIC),
5472                         .intfver_vnic = FW_INTFVER(T4, VNIC),
5473                         .intfver_ri = FW_INTFVER(T4, RI),
5474                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
5475                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
5476                 },
5477         }, {
5478                 .chip = CHELSIO_T5,
5479                 .fs_name = FW5_CFNAME,
5480                 .fw_mod_name = FW5_FNAME,
5481                 .fw_hdr = {
5482                         .chip = FW_HDR_CHIP_T5,
5483                         .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
5484                         .intfver_nic = FW_INTFVER(T5, NIC),
5485                         .intfver_vnic = FW_INTFVER(T5, VNIC),
5486                         .intfver_ri = FW_INTFVER(T5, RI),
5487                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
5488                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
5489                 },
5490         }
5491 };
5492
5493 static struct fw_info *find_fw_info(int chip)
5494 {
5495         int i;
5496
5497         for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
5498                 if (fw_info_array[i].chip == chip)
5499                         return &fw_info_array[i];
5500         }
5501         return NULL;
5502 }
5503
5504 /*
5505  * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5506  */
5507 static int adap_init0(struct adapter *adap)
5508 {
5509         int ret;
5510         u32 v, port_vec;
5511         enum dev_state state;
5512         u32 params[7], val[7];
5513         struct fw_caps_config_cmd caps_cmd;
5514         int reset = 1;
5515
5516         /*
5517          * Contact FW, advertising Master capability (and potentially forcing
5518          * ourselves as the Master PF if our module parameter force_init is
5519          * set).
5520          */
5521         ret = t4_fw_hello(adap, adap->mbox, adap->fn,
5522                           force_init ? MASTER_MUST : MASTER_MAY,
5523                           &state);
5524         if (ret < 0) {
5525                 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
5526                         ret);
5527                 return ret;
5528         }
5529         if (ret == adap->mbox)
5530                 adap->flags |= MASTER_PF;
5531         if (force_init && state == DEV_STATE_INIT)
5532                 state = DEV_STATE_UNINIT;
5533
5534         /*
5535          * If we're the Master PF Driver and the device is uninitialized,
5536          * then let's consider upgrading the firmware ...  (We always want
5537          * to check the firmware version number in order to A. get it for
5538          * later reporting and B. to warn if the currently loaded firmware
5539          * is excessively mismatched relative to the driver.)
5540          */
5541         t4_get_fw_version(adap, &adap->params.fw_vers);
5542         t4_get_tp_version(adap, &adap->params.tp_vers);
5543         if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
5544                 struct fw_info *fw_info;
5545                 struct fw_hdr *card_fw;
5546                 const struct firmware *fw;
5547                 const u8 *fw_data = NULL;
5548                 unsigned int fw_size = 0;
5549
5550                 /* This is the firmware whose headers the driver was compiled
5551                  * against
5552                  */
5553                 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
5554                 if (fw_info == NULL) {
5555                         dev_err(adap->pdev_dev,
5556                                 "unable to get firmware info for chip %d.\n",
5557                                 CHELSIO_CHIP_VERSION(adap->params.chip));
5558                         return -EINVAL;
5559                 }
5560
5561                 /* allocate memory to read the header of the firmware on the
5562                  * card
5563                  */
5564                 card_fw = t4_alloc_mem(sizeof(*card_fw));
5565
5566                 /* Get FW from from /lib/firmware/ */
5567                 ret = request_firmware(&fw, fw_info->fw_mod_name,
5568                                        adap->pdev_dev);
5569                 if (ret < 0) {
5570                         dev_err(adap->pdev_dev,
5571                                 "unable to load firmware image %s, error %d\n",
5572                                 fw_info->fw_mod_name, ret);
5573                 } else {
5574                         fw_data = fw->data;
5575                         fw_size = fw->size;
5576                 }
5577
5578                 /* upgrade FW logic */
5579                 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
5580                                  state, &reset);
5581
5582                 /* Cleaning up */
5583                 if (fw != NULL)
5584                         release_firmware(fw);
5585                 t4_free_mem(card_fw);
5586
5587                 if (ret < 0)
5588                         goto bye;
5589         }
5590
5591         /*
5592          * Grab VPD parameters.  This should be done after we establish a
5593          * connection to the firmware since some of the VPD parameters
5594          * (notably the Core Clock frequency) are retrieved via requests to
5595          * the firmware.  On the other hand, we need these fairly early on
5596          * so we do this right after getting ahold of the firmware.
5597          */
5598         ret = get_vpd_params(adap, &adap->params.vpd);
5599         if (ret < 0)
5600                 goto bye;
5601
5602         /*
5603          * Find out what ports are available to us.  Note that we need to do
5604          * this before calling adap_init0_no_config() since it needs nports
5605          * and portvec ...
5606          */
5607         v =
5608             FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5609             FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC);
5610         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1, &v, &port_vec);
5611         if (ret < 0)
5612                 goto bye;
5613
5614         adap->params.nports = hweight32(port_vec);
5615         adap->params.portvec = port_vec;
5616
5617         /*
5618          * If the firmware is initialized already (and we're not forcing a
5619          * master initialization), note that we're living with existing
5620          * adapter parameters.  Otherwise, it's time to try initializing the
5621          * adapter ...
5622          */
5623         if (state == DEV_STATE_INIT) {
5624                 dev_info(adap->pdev_dev, "Coming up as %s: "\
5625                          "Adapter already initialized\n",
5626                          adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
5627                 adap->flags |= USING_SOFT_PARAMS;
5628         } else {
5629                 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
5630                          "Initializing adapter\n");
5631
5632                 /*
5633                  * If the firmware doesn't support Configuration
5634                  * Files warn user and exit,
5635                  */
5636                 if (ret < 0)
5637                         dev_warn(adap->pdev_dev, "Firmware doesn't support "
5638                                  "configuration file.\n");
5639                 if (force_old_init)
5640                         ret = adap_init0_no_config(adap, reset);
5641                 else {
5642                         /*
5643                          * Find out whether we're dealing with a version of
5644                          * the firmware which has configuration file support.
5645                          */
5646                         params[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5647                                      FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF));
5648                         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 1,
5649                                               params, val);
5650
5651                         /*
5652                          * If the firmware doesn't support Configuration
5653                          * Files, use the old Driver-based, hard-wired
5654                          * initialization.  Otherwise, try using the
5655                          * Configuration File support and fall back to the
5656                          * Driver-based initialization if there's no
5657                          * Configuration File found.
5658                          */
5659                         if (ret < 0)
5660                                 ret = adap_init0_no_config(adap, reset);
5661                         else {
5662                                 /*
5663                                  * The firmware provides us with a memory
5664                                  * buffer where we can load a Configuration
5665                                  * File from the host if we want to override
5666                                  * the Configuration File in flash.
5667                                  */
5668
5669                                 ret = adap_init0_config(adap, reset);
5670                                 if (ret == -ENOENT) {
5671                                         dev_info(adap->pdev_dev,
5672                                             "No Configuration File present "
5673                                             "on adapter. Using hard-wired "
5674                                             "configuration parameters.\n");
5675                                         ret = adap_init0_no_config(adap, reset);
5676                                 }
5677                         }
5678                 }
5679                 if (ret < 0) {
5680                         dev_err(adap->pdev_dev,
5681                                 "could not initialize adapter, error %d\n",
5682                                 -ret);
5683                         goto bye;
5684                 }
5685         }
5686
5687         /*
5688          * If we're living with non-hard-coded parameters (either from a
5689          * Firmware Configuration File or values programmed by a different PF
5690          * Driver), give the SGE code a chance to pull in anything that it
5691          * needs ...  Note that this must be called after we retrieve our VPD
5692          * parameters in order to know how to convert core ticks to seconds.
5693          */
5694         if (adap->flags & USING_SOFT_PARAMS) {
5695                 ret = t4_sge_init(adap);
5696                 if (ret < 0)
5697                         goto bye;
5698         }
5699
5700         if (is_bypass_device(adap->pdev->device))
5701                 adap->params.bypass = 1;
5702
5703         /*
5704          * Grab some of our basic fundamental operating parameters.
5705          */
5706 #define FW_PARAM_DEV(param) \
5707         (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5708         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5709
5710 #define FW_PARAM_PFVF(param) \
5711         FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5712         FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)|  \
5713         FW_PARAMS_PARAM_Y(0) | \
5714         FW_PARAMS_PARAM_Z(0)
5715
5716         params[0] = FW_PARAM_PFVF(EQ_START);
5717         params[1] = FW_PARAM_PFVF(L2T_START);
5718         params[2] = FW_PARAM_PFVF(L2T_END);
5719         params[3] = FW_PARAM_PFVF(FILTER_START);
5720         params[4] = FW_PARAM_PFVF(FILTER_END);
5721         params[5] = FW_PARAM_PFVF(IQFLINT_START);
5722         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6, params, val);
5723         if (ret < 0)
5724                 goto bye;
5725         adap->sge.egr_start = val[0];
5726         adap->l2t_start = val[1];
5727         adap->l2t_end = val[2];
5728         adap->tids.ftid_base = val[3];
5729         adap->tids.nftids = val[4] - val[3] + 1;
5730         adap->sge.ingr_start = val[5];
5731
5732         /* query params related to active filter region */
5733         params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
5734         params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
5735         ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2, params, val);
5736         /* If Active filter size is set we enable establishing
5737          * offload connection through firmware work request
5738          */
5739         if ((val[0] != val[1]) && (ret >= 0)) {
5740                 adap->flags |= FW_OFLD_CONN;
5741                 adap->tids.aftid_base = val[0];
5742                 adap->tids.aftid_end = val[1];
5743         }
5744
5745         /* If we're running on newer firmware, let it know that we're
5746          * prepared to deal with encapsulated CPL messages.  Older
5747          * firmware won't understand this and we'll just get
5748          * unencapsulated messages ...
5749          */
5750         params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
5751         val[0] = 1;
5752         (void) t4_set_params(adap, adap->mbox, adap->fn, 0, 1, params, val);
5753
5754         /*
5755          * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5756          * capability.  Earlier versions of the firmware didn't have the
5757          * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5758          * permission to use ULPTX MEMWRITE DSGL.
5759          */
5760         if (is_t4(adap->params.chip)) {
5761                 adap->params.ulptx_memwrite_dsgl = false;
5762         } else {
5763                 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
5764                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0,
5765                                       1, params, val);
5766                 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
5767         }
5768
5769         /*
5770          * Get device capabilities so we can determine what resources we need
5771          * to manage.
5772          */
5773         memset(&caps_cmd, 0, sizeof(caps_cmd));
5774         caps_cmd.op_to_write = htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
5775                                      FW_CMD_REQUEST | FW_CMD_READ);
5776         caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
5777         ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
5778                          &caps_cmd);
5779         if (ret < 0)
5780                 goto bye;
5781
5782         if (caps_cmd.ofldcaps) {
5783                 /* query offload-related parameters */
5784                 params[0] = FW_PARAM_DEV(NTID);
5785                 params[1] = FW_PARAM_PFVF(SERVER_START);
5786                 params[2] = FW_PARAM_PFVF(SERVER_END);
5787                 params[3] = FW_PARAM_PFVF(TDDP_START);
5788                 params[4] = FW_PARAM_PFVF(TDDP_END);
5789                 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
5790                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5791                                       params, val);
5792                 if (ret < 0)
5793                         goto bye;
5794                 adap->tids.ntids = val[0];
5795                 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
5796                 adap->tids.stid_base = val[1];
5797                 adap->tids.nstids = val[2] - val[1] + 1;
5798                 /*
5799                  * Setup server filter region. Divide the availble filter
5800                  * region into two parts. Regular filters get 1/3rd and server
5801                  * filters get 2/3rd part. This is only enabled if workarond
5802                  * path is enabled.
5803                  * 1. For regular filters.
5804                  * 2. Server filter: This are special filters which are used
5805                  * to redirect SYN packets to offload queue.
5806                  */
5807                 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
5808                         adap->tids.sftid_base = adap->tids.ftid_base +
5809                                         DIV_ROUND_UP(adap->tids.nftids, 3);
5810                         adap->tids.nsftids = adap->tids.nftids -
5811                                          DIV_ROUND_UP(adap->tids.nftids, 3);
5812                         adap->tids.nftids = adap->tids.sftid_base -
5813                                                 adap->tids.ftid_base;
5814                 }
5815                 adap->vres.ddp.start = val[3];
5816                 adap->vres.ddp.size = val[4] - val[3] + 1;
5817                 adap->params.ofldq_wr_cred = val[5];
5818
5819                 adap->params.offload = 1;
5820         }
5821         if (caps_cmd.rdmacaps) {
5822                 params[0] = FW_PARAM_PFVF(STAG_START);
5823                 params[1] = FW_PARAM_PFVF(STAG_END);
5824                 params[2] = FW_PARAM_PFVF(RQ_START);
5825                 params[3] = FW_PARAM_PFVF(RQ_END);
5826                 params[4] = FW_PARAM_PFVF(PBL_START);
5827                 params[5] = FW_PARAM_PFVF(PBL_END);
5828                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 6,
5829                                       params, val);
5830                 if (ret < 0)
5831                         goto bye;
5832                 adap->vres.stag.start = val[0];
5833                 adap->vres.stag.size = val[1] - val[0] + 1;
5834                 adap->vres.rq.start = val[2];
5835                 adap->vres.rq.size = val[3] - val[2] + 1;
5836                 adap->vres.pbl.start = val[4];
5837                 adap->vres.pbl.size = val[5] - val[4] + 1;
5838
5839                 params[0] = FW_PARAM_PFVF(SQRQ_START);
5840                 params[1] = FW_PARAM_PFVF(SQRQ_END);
5841                 params[2] = FW_PARAM_PFVF(CQ_START);
5842                 params[3] = FW_PARAM_PFVF(CQ_END);
5843                 params[4] = FW_PARAM_PFVF(OCQ_START);
5844                 params[5] = FW_PARAM_PFVF(OCQ_END);
5845                 ret = t4_query_params(adap, 0, 0, 0, 6, params, val);
5846                 if (ret < 0)
5847                         goto bye;
5848                 adap->vres.qp.start = val[0];
5849                 adap->vres.qp.size = val[1] - val[0] + 1;
5850                 adap->vres.cq.start = val[2];
5851                 adap->vres.cq.size = val[3] - val[2] + 1;
5852                 adap->vres.ocq.start = val[4];
5853                 adap->vres.ocq.size = val[5] - val[4] + 1;
5854         }
5855         if (caps_cmd.iscsicaps) {
5856                 params[0] = FW_PARAM_PFVF(ISCSI_START);
5857                 params[1] = FW_PARAM_PFVF(ISCSI_END);
5858                 ret = t4_query_params(adap, adap->mbox, adap->fn, 0, 2,
5859                                       params, val);
5860                 if (ret < 0)
5861                         goto bye;
5862                 adap->vres.iscsi.start = val[0];
5863                 adap->vres.iscsi.size = val[1] - val[0] + 1;
5864         }
5865 #undef FW_PARAM_PFVF
5866 #undef FW_PARAM_DEV
5867
5868         /* The MTU/MSS Table is initialized by now, so load their values.  If
5869          * we're initializing the adapter, then we'll make any modifications
5870          * we want to the MTU/MSS Table and also initialize the congestion
5871          * parameters.
5872          */
5873         t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
5874         if (state != DEV_STATE_INIT) {
5875                 int i;
5876
5877                 /* The default MTU Table contains values 1492 and 1500.
5878                  * However, for TCP, it's better to have two values which are
5879                  * a multiple of 8 +/- 4 bytes apart near this popular MTU.
5880                  * This allows us to have a TCP Data Payload which is a
5881                  * multiple of 8 regardless of what combination of TCP Options
5882                  * are in use (always a multiple of 4 bytes) which is
5883                  * important for performance reasons.  For instance, if no
5884                  * options are in use, then we have a 20-byte IP header and a
5885                  * 20-byte TCP header.  In this case, a 1500-byte MSS would
5886                  * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
5887                  * which is not a multiple of 8.  So using an MSS of 1488 in
5888                  * this case results in a TCP Data Payload of 1448 bytes which
5889                  * is a multiple of 8.  On the other hand, if 12-byte TCP Time
5890                  * Stamps have been negotiated, then an MTU of 1500 bytes
5891                  * results in a TCP Data Payload of 1448 bytes which, as
5892                  * above, is a multiple of 8 bytes ...
5893                  */
5894                 for (i = 0; i < NMTUS; i++)
5895                         if (adap->params.mtus[i] == 1492) {
5896                                 adap->params.mtus[i] = 1488;
5897                                 break;
5898                         }
5899
5900                 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5901                              adap->params.b_wnd);
5902         }
5903         t4_init_tp_params(adap);
5904         adap->flags |= FW_OK;
5905         return 0;
5906
5907         /*
5908          * Something bad happened.  If a command timed out or failed with EIO
5909          * FW does not operate within its spec or something catastrophic
5910          * happened to HW/FW, stop issuing commands.
5911          */
5912 bye:
5913         if (ret != -ETIMEDOUT && ret != -EIO)
5914                 t4_fw_bye(adap, adap->mbox);
5915         return ret;
5916 }
5917
5918 /* EEH callbacks */
5919
5920 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
5921                                          pci_channel_state_t state)
5922 {
5923         int i;
5924         struct adapter *adap = pci_get_drvdata(pdev);
5925
5926         if (!adap)
5927                 goto out;
5928
5929         rtnl_lock();
5930         adap->flags &= ~FW_OK;
5931         notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
5932         spin_lock(&adap->stats_lock);
5933         for_each_port(adap, i) {
5934                 struct net_device *dev = adap->port[i];
5935
5936                 netif_device_detach(dev);
5937                 netif_carrier_off(dev);
5938         }
5939         spin_unlock(&adap->stats_lock);
5940         if (adap->flags & FULL_INIT_DONE)
5941                 cxgb_down(adap);
5942         rtnl_unlock();
5943         if ((adap->flags & DEV_ENABLED)) {
5944                 pci_disable_device(pdev);
5945                 adap->flags &= ~DEV_ENABLED;
5946         }
5947 out:    return state == pci_channel_io_perm_failure ?
5948                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
5949 }
5950
5951 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
5952 {
5953         int i, ret;
5954         struct fw_caps_config_cmd c;
5955         struct adapter *adap = pci_get_drvdata(pdev);
5956
5957         if (!adap) {
5958                 pci_restore_state(pdev);
5959                 pci_save_state(pdev);
5960                 return PCI_ERS_RESULT_RECOVERED;
5961         }
5962
5963         if (!(adap->flags & DEV_ENABLED)) {
5964                 if (pci_enable_device(pdev)) {
5965                         dev_err(&pdev->dev, "Cannot reenable PCI "
5966                                             "device after reset\n");
5967                         return PCI_ERS_RESULT_DISCONNECT;
5968                 }
5969                 adap->flags |= DEV_ENABLED;
5970         }
5971
5972         pci_set_master(pdev);
5973         pci_restore_state(pdev);
5974         pci_save_state(pdev);
5975         pci_cleanup_aer_uncorrect_error_status(pdev);
5976
5977         if (t4_wait_dev_ready(adap) < 0)
5978                 return PCI_ERS_RESULT_DISCONNECT;
5979         if (t4_fw_hello(adap, adap->fn, adap->fn, MASTER_MUST, NULL) < 0)
5980                 return PCI_ERS_RESULT_DISCONNECT;
5981         adap->flags |= FW_OK;
5982         if (adap_init1(adap, &c))
5983                 return PCI_ERS_RESULT_DISCONNECT;
5984
5985         for_each_port(adap, i) {
5986                 struct port_info *p = adap2pinfo(adap, i);
5987
5988                 ret = t4_alloc_vi(adap, adap->fn, p->tx_chan, adap->fn, 0, 1,
5989                                   NULL, NULL);
5990                 if (ret < 0)
5991                         return PCI_ERS_RESULT_DISCONNECT;
5992                 p->viid = ret;
5993                 p->xact_addr_filt = -1;
5994         }
5995
5996         t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
5997                      adap->params.b_wnd);
5998         setup_memwin(adap);
5999         if (cxgb_up(adap))
6000                 return PCI_ERS_RESULT_DISCONNECT;
6001         return PCI_ERS_RESULT_RECOVERED;
6002 }
6003
6004 static void eeh_resume(struct pci_dev *pdev)
6005 {
6006         int i;
6007         struct adapter *adap = pci_get_drvdata(pdev);
6008
6009         if (!adap)
6010                 return;
6011
6012         rtnl_lock();
6013         for_each_port(adap, i) {
6014                 struct net_device *dev = adap->port[i];
6015
6016                 if (netif_running(dev)) {
6017                         link_start(dev);
6018                         cxgb_set_rxmode(dev);
6019                 }
6020                 netif_device_attach(dev);
6021         }
6022         rtnl_unlock();
6023 }
6024
6025 static const struct pci_error_handlers cxgb4_eeh = {
6026         .error_detected = eeh_err_detected,
6027         .slot_reset     = eeh_slot_reset,
6028         .resume         = eeh_resume,
6029 };
6030
6031 static inline bool is_x_10g_port(const struct link_config *lc)
6032 {
6033         return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
6034                (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
6035 }
6036
6037 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
6038                              unsigned int us, unsigned int cnt,
6039                              unsigned int size, unsigned int iqe_size)
6040 {
6041         q->adap = adap;
6042         set_rspq_intr_params(q, us, cnt);
6043         q->iqe_len = iqe_size;
6044         q->size = size;
6045 }
6046
6047 /*
6048  * Perform default configuration of DMA queues depending on the number and type
6049  * of ports we found and the number of available CPUs.  Most settings can be
6050  * modified by the admin prior to actual use.
6051  */
6052 static void cfg_queues(struct adapter *adap)
6053 {
6054         struct sge *s = &adap->sge;
6055         int i, n10g = 0, qidx = 0;
6056 #ifndef CONFIG_CHELSIO_T4_DCB
6057         int q10g = 0;
6058 #endif
6059         int ciq_size;
6060
6061         for_each_port(adap, i)
6062                 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
6063 #ifdef CONFIG_CHELSIO_T4_DCB
6064         /* For Data Center Bridging support we need to be able to support up
6065          * to 8 Traffic Priorities; each of which will be assigned to its
6066          * own TX Queue in order to prevent Head-Of-Line Blocking.
6067          */
6068         if (adap->params.nports * 8 > MAX_ETH_QSETS) {
6069                 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
6070                         MAX_ETH_QSETS, adap->params.nports * 8);
6071                 BUG_ON(1);
6072         }
6073
6074         for_each_port(adap, i) {
6075                 struct port_info *pi = adap2pinfo(adap, i);
6076
6077                 pi->first_qset = qidx;
6078                 pi->nqsets = 8;
6079                 qidx += pi->nqsets;
6080         }
6081 #else /* !CONFIG_CHELSIO_T4_DCB */
6082         /*
6083          * We default to 1 queue per non-10G port and up to # of cores queues
6084          * per 10G port.
6085          */
6086         if (n10g)
6087                 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
6088         if (q10g > netif_get_num_default_rss_queues())
6089                 q10g = netif_get_num_default_rss_queues();
6090
6091         for_each_port(adap, i) {
6092                 struct port_info *pi = adap2pinfo(adap, i);
6093
6094                 pi->first_qset = qidx;
6095                 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
6096                 qidx += pi->nqsets;
6097         }
6098 #endif /* !CONFIG_CHELSIO_T4_DCB */
6099
6100         s->ethqsets = qidx;
6101         s->max_ethqsets = qidx;   /* MSI-X may lower it later */
6102
6103         if (is_offload(adap)) {
6104                 /*
6105                  * For offload we use 1 queue/channel if all ports are up to 1G,
6106                  * otherwise we divide all available queues amongst the channels
6107                  * capped by the number of available cores.
6108                  */
6109                 if (n10g) {
6110                         i = min_t(int, ARRAY_SIZE(s->ofldrxq),
6111                                   num_online_cpus());
6112                         s->ofldqsets = roundup(i, adap->params.nports);
6113                 } else
6114                         s->ofldqsets = adap->params.nports;
6115                 /* For RDMA one Rx queue per channel suffices */
6116                 s->rdmaqs = adap->params.nports;
6117                 s->rdmaciqs = adap->params.nports;
6118         }
6119
6120         for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
6121                 struct sge_eth_rxq *r = &s->ethrxq[i];
6122
6123                 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
6124                 r->fl.size = 72;
6125         }
6126
6127         for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
6128                 s->ethtxq[i].q.size = 1024;
6129
6130         for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
6131                 s->ctrlq[i].q.size = 512;
6132
6133         for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
6134                 s->ofldtxq[i].q.size = 1024;
6135
6136         for (i = 0; i < ARRAY_SIZE(s->ofldrxq); i++) {
6137                 struct sge_ofld_rxq *r = &s->ofldrxq[i];
6138
6139                 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
6140                 r->rspq.uld = CXGB4_ULD_ISCSI;
6141                 r->fl.size = 72;
6142         }
6143
6144         for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
6145                 struct sge_ofld_rxq *r = &s->rdmarxq[i];
6146
6147                 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
6148                 r->rspq.uld = CXGB4_ULD_RDMA;
6149                 r->fl.size = 72;
6150         }
6151
6152         ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
6153         if (ciq_size > SGE_MAX_IQ_SIZE) {
6154                 CH_WARN(adap, "CIQ size too small for available IQs\n");
6155                 ciq_size = SGE_MAX_IQ_SIZE;
6156         }
6157
6158         for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
6159                 struct sge_ofld_rxq *r = &s->rdmaciq[i];
6160
6161                 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
6162                 r->rspq.uld = CXGB4_ULD_RDMA;
6163         }
6164
6165         init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
6166         init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
6167 }
6168
6169 /*
6170  * Reduce the number of Ethernet queues across all ports to at most n.
6171  * n provides at least one queue per port.
6172  */
6173 static void reduce_ethqs(struct adapter *adap, int n)
6174 {
6175         int i;
6176         struct port_info *pi;
6177
6178         while (n < adap->sge.ethqsets)
6179                 for_each_port(adap, i) {
6180                         pi = adap2pinfo(adap, i);
6181                         if (pi->nqsets > 1) {
6182                                 pi->nqsets--;
6183                                 adap->sge.ethqsets--;
6184                                 if (adap->sge.ethqsets <= n)
6185                                         break;
6186                         }
6187                 }
6188
6189         n = 0;
6190         for_each_port(adap, i) {
6191                 pi = adap2pinfo(adap, i);
6192                 pi->first_qset = n;
6193                 n += pi->nqsets;
6194         }
6195 }
6196
6197 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6198 #define EXTRA_VECS 2
6199
6200 static int enable_msix(struct adapter *adap)
6201 {
6202         int ofld_need = 0;
6203         int i, want, need;
6204         struct sge *s = &adap->sge;
6205         unsigned int nchan = adap->params.nports;
6206         struct msix_entry entries[MAX_INGQ + 1];
6207
6208         for (i = 0; i < ARRAY_SIZE(entries); ++i)
6209                 entries[i].entry = i;
6210
6211         want = s->max_ethqsets + EXTRA_VECS;
6212         if (is_offload(adap)) {
6213                 want += s->rdmaqs + s->rdmaciqs + s->ofldqsets;
6214                 /* need nchan for each possible ULD */
6215                 ofld_need = 3 * nchan;
6216         }
6217 #ifdef CONFIG_CHELSIO_T4_DCB
6218         /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6219          * each port.
6220          */
6221         need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
6222 #else
6223         need = adap->params.nports + EXTRA_VECS + ofld_need;
6224 #endif
6225         want = pci_enable_msix_range(adap->pdev, entries, need, want);
6226         if (want < 0)
6227                 return want;
6228
6229         /*
6230          * Distribute available vectors to the various queue groups.
6231          * Every group gets its minimum requirement and NIC gets top
6232          * priority for leftovers.
6233          */
6234         i = want - EXTRA_VECS - ofld_need;
6235         if (i < s->max_ethqsets) {
6236                 s->max_ethqsets = i;
6237                 if (i < s->ethqsets)
6238                         reduce_ethqs(adap, i);
6239         }
6240         if (is_offload(adap)) {
6241                 i = want - EXTRA_VECS - s->max_ethqsets;
6242                 i -= ofld_need - nchan;
6243                 s->ofldqsets = (i / nchan) * nchan;  /* round down */
6244         }
6245         for (i = 0; i < want; ++i)
6246                 adap->msix_info[i].vec = entries[i].vector;
6247
6248         return 0;
6249 }
6250
6251 #undef EXTRA_VECS
6252
6253 static int init_rss(struct adapter *adap)
6254 {
6255         unsigned int i, j;
6256
6257         for_each_port(adap, i) {
6258                 struct port_info *pi = adap2pinfo(adap, i);
6259
6260                 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
6261                 if (!pi->rss)
6262                         return -ENOMEM;
6263                 for (j = 0; j < pi->rss_size; j++)
6264                         pi->rss[j] = ethtool_rxfh_indir_default(j, pi->nqsets);
6265         }
6266         return 0;
6267 }
6268
6269 static void print_port_info(const struct net_device *dev)
6270 {
6271         char buf[80];
6272         char *bufp = buf;
6273         const char *spd = "";
6274         const struct port_info *pi = netdev_priv(dev);
6275         const struct adapter *adap = pi->adapter;
6276
6277         if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
6278                 spd = " 2.5 GT/s";
6279         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
6280                 spd = " 5 GT/s";
6281         else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
6282                 spd = " 8 GT/s";
6283
6284         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
6285                 bufp += sprintf(bufp, "100/");
6286         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
6287                 bufp += sprintf(bufp, "1000/");
6288         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
6289                 bufp += sprintf(bufp, "10G/");
6290         if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
6291                 bufp += sprintf(bufp, "40G/");
6292         if (bufp != buf)
6293                 --bufp;
6294         sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
6295
6296         netdev_info(dev, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6297                     adap->params.vpd.id,
6298                     CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
6299                     is_offload(adap) ? "R" : "", adap->params.pci.width, spd,
6300                     (adap->flags & USING_MSIX) ? " MSI-X" :
6301                     (adap->flags & USING_MSI) ? " MSI" : "");
6302         netdev_info(dev, "S/N: %s, P/N: %s\n",
6303                     adap->params.vpd.sn, adap->params.vpd.pn);
6304 }
6305
6306 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
6307 {
6308         pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
6309 }
6310
6311 /*
6312  * Free the following resources:
6313  * - memory used for tables
6314  * - MSI/MSI-X
6315  * - net devices
6316  * - resources FW is holding for us
6317  */
6318 static void free_some_resources(struct adapter *adapter)
6319 {
6320         unsigned int i;
6321
6322         t4_free_mem(adapter->l2t);
6323         t4_free_mem(adapter->tids.tid_tab);
6324         disable_msi(adapter);
6325
6326         for_each_port(adapter, i)
6327                 if (adapter->port[i]) {
6328                         kfree(adap2pinfo(adapter, i)->rss);
6329                         free_netdev(adapter->port[i]);
6330                 }
6331         if (adapter->flags & FW_OK)
6332                 t4_fw_bye(adapter, adapter->fn);
6333 }
6334
6335 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6336 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6337                    NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6338 #define SEGMENT_SIZE 128
6339
6340 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6341 {
6342         int func, i, err, s_qpp, qpp, num_seg;
6343         struct port_info *pi;
6344         bool highdma = false;
6345         struct adapter *adapter = NULL;
6346
6347         printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
6348
6349         err = pci_request_regions(pdev, KBUILD_MODNAME);
6350         if (err) {
6351                 /* Just info, some other driver may have claimed the device. */
6352                 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
6353                 return err;
6354         }
6355
6356         err = pci_enable_device(pdev);
6357         if (err) {
6358                 dev_err(&pdev->dev, "cannot enable PCI device\n");
6359                 goto out_release_regions;
6360         }
6361
6362         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
6363                 highdma = true;
6364                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
6365                 if (err) {
6366                         dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
6367                                 "coherent allocations\n");
6368                         goto out_disable_device;
6369                 }
6370         } else {
6371                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6372                 if (err) {
6373                         dev_err(&pdev->dev, "no usable DMA configuration\n");
6374                         goto out_disable_device;
6375                 }
6376         }
6377
6378         pci_enable_pcie_error_reporting(pdev);
6379         enable_pcie_relaxed_ordering(pdev);
6380         pci_set_master(pdev);
6381         pci_save_state(pdev);
6382
6383         adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
6384         if (!adapter) {
6385                 err = -ENOMEM;
6386                 goto out_disable_device;
6387         }
6388
6389         /* PCI device has been enabled */
6390         adapter->flags |= DEV_ENABLED;
6391
6392         adapter->regs = pci_ioremap_bar(pdev, 0);
6393         if (!adapter->regs) {
6394                 dev_err(&pdev->dev, "cannot map device registers\n");
6395                 err = -ENOMEM;
6396                 goto out_free_adapter;
6397         }
6398
6399         /* We control everything through one PF */
6400         func = SOURCEPF_GET(readl(adapter->regs + PL_WHOAMI));
6401         if ((pdev->device == 0xa000 && func != 0) ||
6402             func != ent->driver_data) {
6403                 pci_save_state(pdev);        /* to restore SR-IOV later */
6404                 err = 0;
6405                 goto out_unmap_bar0;
6406         }
6407
6408         adapter->pdev = pdev;
6409         adapter->pdev_dev = &pdev->dev;
6410         adapter->mbox = func;
6411         adapter->fn = func;
6412         adapter->msg_enable = dflt_msg_enable;
6413         memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
6414
6415         spin_lock_init(&adapter->stats_lock);
6416         spin_lock_init(&adapter->tid_release_lock);
6417
6418         INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
6419         INIT_WORK(&adapter->db_full_task, process_db_full);
6420         INIT_WORK(&adapter->db_drop_task, process_db_drop);
6421
6422         err = t4_prep_adapter(adapter);
6423         if (err)
6424                 goto out_unmap_bar0;
6425
6426         if (!is_t4(adapter->params.chip)) {
6427                 s_qpp = QUEUESPERPAGEPF1 * adapter->fn;
6428                 qpp = 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter,
6429                       SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp);
6430                 num_seg = PAGE_SIZE / SEGMENT_SIZE;
6431
6432                 /* Each segment size is 128B. Write coalescing is enabled only
6433                  * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6434                  * queue is less no of segments that can be accommodated in
6435                  * a page size.
6436                  */
6437                 if (qpp > num_seg) {
6438                         dev_err(&pdev->dev,
6439                                 "Incorrect number of egress queues per page\n");
6440                         err = -EINVAL;
6441                         goto out_unmap_bar0;
6442                 }
6443                 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
6444                 pci_resource_len(pdev, 2));
6445                 if (!adapter->bar2) {
6446                         dev_err(&pdev->dev, "cannot map device bar2 region\n");
6447                         err = -ENOMEM;
6448                         goto out_unmap_bar0;
6449                 }
6450         }
6451
6452         setup_memwin(adapter);
6453         err = adap_init0(adapter);
6454         setup_memwin_rdma(adapter);
6455         if (err)
6456                 goto out_unmap_bar;
6457
6458         for_each_port(adapter, i) {
6459                 struct net_device *netdev;
6460
6461                 netdev = alloc_etherdev_mq(sizeof(struct port_info),
6462                                            MAX_ETH_QSETS);
6463                 if (!netdev) {
6464                         err = -ENOMEM;
6465                         goto out_free_dev;
6466                 }
6467
6468                 SET_NETDEV_DEV(netdev, &pdev->dev);
6469
6470                 adapter->port[i] = netdev;
6471                 pi = netdev_priv(netdev);
6472                 pi->adapter = adapter;
6473                 pi->xact_addr_filt = -1;
6474                 pi->port_id = i;
6475                 netdev->irq = pdev->irq;
6476
6477                 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
6478                         NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
6479                         NETIF_F_RXCSUM | NETIF_F_RXHASH |
6480                         NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
6481                 if (highdma)
6482                         netdev->hw_features |= NETIF_F_HIGHDMA;
6483                 netdev->features |= netdev->hw_features;
6484                 netdev->vlan_features = netdev->features & VLAN_FEAT;
6485
6486                 netdev->priv_flags |= IFF_UNICAST_FLT;
6487
6488                 netdev->netdev_ops = &cxgb4_netdev_ops;
6489 #ifdef CONFIG_CHELSIO_T4_DCB
6490                 netdev->dcbnl_ops = &cxgb4_dcb_ops;
6491                 cxgb4_dcb_state_init(netdev);
6492 #endif
6493                 netdev->ethtool_ops = &cxgb_ethtool_ops;
6494         }
6495
6496         pci_set_drvdata(pdev, adapter);
6497
6498         if (adapter->flags & FW_OK) {
6499                 err = t4_port_init(adapter, func, func, 0);
6500                 if (err)
6501                         goto out_free_dev;
6502         }
6503
6504         /*
6505          * Configure queues and allocate tables now, they can be needed as
6506          * soon as the first register_netdev completes.
6507          */
6508         cfg_queues(adapter);
6509
6510         adapter->l2t = t4_init_l2t();
6511         if (!adapter->l2t) {
6512                 /* We tolerate a lack of L2T, giving up some functionality */
6513                 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
6514                 adapter->params.offload = 0;
6515         }
6516
6517         if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
6518                 dev_warn(&pdev->dev, "could not allocate TID table, "
6519                          "continuing\n");
6520                 adapter->params.offload = 0;
6521         }
6522
6523         /* See what interrupts we'll be using */
6524         if (msi > 1 && enable_msix(adapter) == 0)
6525                 adapter->flags |= USING_MSIX;
6526         else if (msi > 0 && pci_enable_msi(pdev) == 0)
6527                 adapter->flags |= USING_MSI;
6528
6529         err = init_rss(adapter);
6530         if (err)
6531                 goto out_free_dev;
6532
6533         /*
6534          * The card is now ready to go.  If any errors occur during device
6535          * registration we do not fail the whole card but rather proceed only
6536          * with the ports we manage to register successfully.  However we must
6537          * register at least one net device.
6538          */
6539         for_each_port(adapter, i) {
6540                 pi = adap2pinfo(adapter, i);
6541                 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
6542                 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
6543
6544                 err = register_netdev(adapter->port[i]);
6545                 if (err)
6546                         break;
6547                 adapter->chan_map[pi->tx_chan] = i;
6548                 print_port_info(adapter->port[i]);
6549         }
6550         if (i == 0) {
6551                 dev_err(&pdev->dev, "could not register any net devices\n");
6552                 goto out_free_dev;
6553         }
6554         if (err) {
6555                 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
6556                 err = 0;
6557         }
6558
6559         if (cxgb4_debugfs_root) {
6560                 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
6561                                                            cxgb4_debugfs_root);
6562                 setup_debugfs(adapter);
6563         }
6564
6565         /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6566         pdev->needs_freset = 1;
6567
6568         if (is_offload(adapter))
6569                 attach_ulds(adapter);
6570
6571 #ifdef CONFIG_PCI_IOV
6572         if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
6573                 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
6574                         dev_info(&pdev->dev,
6575                                  "instantiated %u virtual functions\n",
6576                                  num_vf[func]);
6577 #endif
6578         return 0;
6579
6580  out_free_dev:
6581         free_some_resources(adapter);
6582  out_unmap_bar:
6583         if (!is_t4(adapter->params.chip))
6584                 iounmap(adapter->bar2);
6585  out_unmap_bar0:
6586         iounmap(adapter->regs);
6587  out_free_adapter:
6588         kfree(adapter);
6589  out_disable_device:
6590         pci_disable_pcie_error_reporting(pdev);
6591         pci_disable_device(pdev);
6592  out_release_regions:
6593         pci_release_regions(pdev);
6594         return err;
6595 }
6596
6597 static void remove_one(struct pci_dev *pdev)
6598 {
6599         struct adapter *adapter = pci_get_drvdata(pdev);
6600
6601 #ifdef CONFIG_PCI_IOV
6602         pci_disable_sriov(pdev);
6603
6604 #endif
6605
6606         if (adapter) {
6607                 int i;
6608
6609                 if (is_offload(adapter))
6610                         detach_ulds(adapter);
6611
6612                 for_each_port(adapter, i)
6613                         if (adapter->port[i]->reg_state == NETREG_REGISTERED)
6614                                 unregister_netdev(adapter->port[i]);
6615
6616                 if (adapter->debugfs_root)
6617                         debugfs_remove_recursive(adapter->debugfs_root);
6618
6619                 /* If we allocated filters, free up state associated with any
6620                  * valid filters ...
6621                  */
6622                 if (adapter->tids.ftid_tab) {
6623                         struct filter_entry *f = &adapter->tids.ftid_tab[0];
6624                         for (i = 0; i < (adapter->tids.nftids +
6625                                         adapter->tids.nsftids); i++, f++)
6626                                 if (f->valid)
6627                                         clear_filter(adapter, f);
6628                 }
6629
6630                 if (adapter->flags & FULL_INIT_DONE)
6631                         cxgb_down(adapter);
6632
6633                 free_some_resources(adapter);
6634                 iounmap(adapter->regs);
6635                 if (!is_t4(adapter->params.chip))
6636                         iounmap(adapter->bar2);
6637                 pci_disable_pcie_error_reporting(pdev);
6638                 if ((adapter->flags & DEV_ENABLED)) {
6639                         pci_disable_device(pdev);
6640                         adapter->flags &= ~DEV_ENABLED;
6641                 }
6642                 pci_release_regions(pdev);
6643                 synchronize_rcu();
6644                 kfree(adapter);
6645         } else
6646                 pci_release_regions(pdev);
6647 }
6648
6649 static struct pci_driver cxgb4_driver = {
6650         .name     = KBUILD_MODNAME,
6651         .id_table = cxgb4_pci_tbl,
6652         .probe    = init_one,
6653         .remove   = remove_one,
6654         .shutdown = remove_one,
6655         .err_handler = &cxgb4_eeh,
6656 };
6657
6658 static int __init cxgb4_init_module(void)
6659 {
6660         int ret;
6661
6662         workq = create_singlethread_workqueue("cxgb4");
6663         if (!workq)
6664                 return -ENOMEM;
6665
6666         /* Debugfs support is optional, just warn if this fails */
6667         cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
6668         if (!cxgb4_debugfs_root)
6669                 pr_warn("could not create debugfs entry, continuing\n");
6670
6671         ret = pci_register_driver(&cxgb4_driver);
6672         if (ret < 0) {
6673                 debugfs_remove(cxgb4_debugfs_root);
6674                 destroy_workqueue(workq);
6675         }
6676
6677         register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6678
6679         return ret;
6680 }
6681
6682 static void __exit cxgb4_cleanup_module(void)
6683 {
6684         unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
6685         pci_unregister_driver(&cxgb4_driver);
6686         debugfs_remove(cxgb4_debugfs_root);  /* NULL ok */
6687         flush_workqueue(workq);
6688         destroy_workqueue(workq);
6689 }
6690
6691 module_init(cxgb4_init_module);
6692 module_exit(cxgb4_cleanup_module);