2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <net/bonding.h>
65 #include <net/addrconf.h>
66 #include <asm/uaccess.h>
70 #include "t4_values.h"
73 #include "t4fw_version.h"
74 #include "cxgb4_dcb.h"
75 #include "cxgb4_debugfs.h"
79 char cxgb4_driver_name[] = KBUILD_MODNAME;
84 #define DRV_VERSION "2.0.0-ko"
85 const char cxgb4_driver_version[] = DRV_VERSION;
86 #define DRV_DESC "Chelsio T4/T5/T6 Network Driver"
88 /* Host shadow copy of ingress filter entry. This is in host native format
89 * and doesn't match the ordering or bit order, etc. of the hardware of the
90 * firmware command. The use of bit-field structure elements is purely to
91 * remind ourselves of the field size limitations and save memory in the case
92 * where the filter table is large.
95 /* Administrative fields for filter.
97 u32 valid:1; /* filter allocated and valid */
98 u32 locked:1; /* filter is administratively locked */
100 u32 pending:1; /* filter action is pending firmware reply */
101 u32 smtidx:8; /* Source MAC Table index for smac */
102 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
104 /* The filter itself. Most of this is a straight copy of information
105 * provided by the extended ioctl(). Some fields are translated to
106 * internal forms -- for instance the Ingress Queue ID passed in from
107 * the ioctl() is translated into the Absolute Ingress Queue ID.
109 struct ch_filter_specification fs;
112 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
113 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
114 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
116 /* Macros needed to support the PCI Device ID Table ...
118 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
119 static const struct pci_device_id cxgb4_pci_tbl[] = {
120 #define CH_PCI_DEVICE_ID_FUNCTION 0x4
122 /* Include PCI Device IDs for both PF4 and PF0-3 so our PCI probe() routine is
125 #define CH_PCI_DEVICE_ID_FUNCTION2 0x0
127 #define CH_PCI_ID_TABLE_ENTRY(devid) \
128 {PCI_VDEVICE(CHELSIO, (devid)), 4}
130 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
134 #include "t4_pci_id_tbl.h"
136 #define FW4_FNAME "cxgb4/t4fw.bin"
137 #define FW5_FNAME "cxgb4/t5fw.bin"
138 #define FW6_FNAME "cxgb4/t6fw.bin"
139 #define FW4_CFNAME "cxgb4/t4-config.txt"
140 #define FW5_CFNAME "cxgb4/t5-config.txt"
141 #define FW6_CFNAME "cxgb4/t6-config.txt"
142 #define PHY_AQ1202_FIRMWARE "cxgb4/aq1202_fw.cld"
143 #define PHY_BCM84834_FIRMWARE "cxgb4/bcm8483.bin"
144 #define PHY_AQ1202_DEVICEID 0x4409
145 #define PHY_BCM84834_DEVICEID 0x4486
147 MODULE_DESCRIPTION(DRV_DESC);
148 MODULE_AUTHOR("Chelsio Communications");
149 MODULE_LICENSE("Dual BSD/GPL");
150 MODULE_VERSION(DRV_VERSION);
151 MODULE_DEVICE_TABLE(pci, cxgb4_pci_tbl);
152 MODULE_FIRMWARE(FW4_FNAME);
153 MODULE_FIRMWARE(FW5_FNAME);
154 MODULE_FIRMWARE(FW6_FNAME);
157 * Normally we're willing to become the firmware's Master PF but will be happy
158 * if another PF has already become the Master and initialized the adapter.
159 * Setting "force_init" will cause this driver to forcibly establish itself as
160 * the Master PF and initialize the adapter.
162 static uint force_init;
164 module_param(force_init, uint, 0644);
165 MODULE_PARM_DESC(force_init, "Forcibly become Master PF and initialize adapter,"
166 "deprecated parameter");
168 static int dflt_msg_enable = DFLT_MSG_ENABLE;
170 module_param(dflt_msg_enable, int, 0644);
171 MODULE_PARM_DESC(dflt_msg_enable, "Chelsio T4 default message enable bitmap");
174 * The driver uses the best interrupt scheme available on a platform in the
175 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
176 * of these schemes the driver may consider as follows:
178 * msi = 2: choose from among all three options
179 * msi = 1: only consider MSI and INTx interrupts
180 * msi = 0: force INTx interrupts
184 module_param(msi, int, 0644);
185 MODULE_PARM_DESC(msi, "whether to use INTx (0), MSI (1) or MSI-X (2)");
188 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
189 * offset by 2 bytes in order to have the IP headers line up on 4-byte
190 * boundaries. This is a requirement for many architectures which will throw
191 * a machine check fault if an attempt is made to access one of the 4-byte IP
192 * header fields on a non-4-byte boundary. And it's a major performance issue
193 * even on some architectures which allow it like some implementations of the
194 * x86 ISA. However, some architectures don't mind this and for some very
195 * edge-case performance sensitive applications (like forwarding large volumes
196 * of small packets), setting this DMA offset to 0 will decrease the number of
197 * PCI-E Bus transfers enough to measurably affect performance.
199 static int rx_dma_offset = 2;
201 #ifdef CONFIG_PCI_IOV
202 /* Configure the number of PCI-E Virtual Function which are to be instantiated
203 * on SR-IOV Capable Physical Functions.
205 static unsigned int num_vf[NUM_OF_PF_WITH_SRIOV];
207 module_param_array(num_vf, uint, NULL, 0644);
208 MODULE_PARM_DESC(num_vf, "number of VFs for each of PFs 0-3");
211 /* TX Queue select used to determine what algorithm to use for selecting TX
212 * queue. Select between the kernel provided function (select_queue=0) or user
213 * cxgb_select_queue function (select_queue=1)
215 * Default: select_queue=0
217 static int select_queue;
218 module_param(select_queue, int, 0644);
219 MODULE_PARM_DESC(select_queue,
220 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
222 static struct dentry *cxgb4_debugfs_root;
224 static LIST_HEAD(adapter_list);
225 static DEFINE_MUTEX(uld_mutex);
226 /* Adapter list to be accessed from atomic context */
227 static LIST_HEAD(adap_rcu_list);
228 static DEFINE_SPINLOCK(adap_rcu_lock);
229 static struct cxgb4_uld_info ulds[CXGB4_ULD_MAX];
230 static const char *uld_str[] = { "RDMA", "iSCSI" };
232 static void link_report(struct net_device *dev)
234 if (!netif_carrier_ok(dev))
235 netdev_info(dev, "link down\n");
237 static const char *fc[] = { "no", "Rx", "Tx", "Tx/Rx" };
240 const struct port_info *p = netdev_priv(dev);
242 switch (p->link_cfg.speed) {
256 pr_info("%s: unsupported speed: %d\n",
257 dev->name, p->link_cfg.speed);
261 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s,
266 #ifdef CONFIG_CHELSIO_T4_DCB
267 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
268 static void dcb_tx_queue_prio_enable(struct net_device *dev, int enable)
270 struct port_info *pi = netdev_priv(dev);
271 struct adapter *adap = pi->adapter;
272 struct sge_eth_txq *txq = &adap->sge.ethtxq[pi->first_qset];
275 /* We use a simple mapping of Port TX Queue Index to DCB
276 * Priority when we're enabling DCB.
278 for (i = 0; i < pi->nqsets; i++, txq++) {
282 name = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
284 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH) |
285 FW_PARAMS_PARAM_YZ_V(txq->q.cntxt_id));
286 value = enable ? i : 0xffffffff;
288 /* Since we can be called while atomic (from "interrupt
289 * level") we need to issue the Set Parameters Commannd
290 * without sleeping (timeout < 0).
292 err = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
294 -FW_CMD_MAX_TIMEOUT);
297 dev_err(adap->pdev_dev,
298 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
299 enable ? "set" : "unset", pi->port_id, i, -err);
301 txq->dcb_prio = value;
304 #endif /* CONFIG_CHELSIO_T4_DCB */
306 void t4_os_link_changed(struct adapter *adapter, int port_id, int link_stat)
308 struct net_device *dev = adapter->port[port_id];
310 /* Skip changes from disabled ports. */
311 if (netif_running(dev) && link_stat != netif_carrier_ok(dev)) {
313 netif_carrier_on(dev);
315 #ifdef CONFIG_CHELSIO_T4_DCB
316 cxgb4_dcb_state_init(dev);
317 dcb_tx_queue_prio_enable(dev, false);
318 #endif /* CONFIG_CHELSIO_T4_DCB */
319 netif_carrier_off(dev);
326 void t4_os_portmod_changed(const struct adapter *adap, int port_id)
328 static const char *mod_str[] = {
329 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
332 const struct net_device *dev = adap->port[port_id];
333 const struct port_info *pi = netdev_priv(dev);
335 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
336 netdev_info(dev, "port module unplugged\n");
337 else if (pi->mod_type < ARRAY_SIZE(mod_str))
338 netdev_info(dev, "%s module inserted\n", mod_str[pi->mod_type]);
342 * Configure the exact and hash address filters to handle a port's multicast
343 * and secondary unicast MAC addresses.
345 static int set_addr_filters(const struct net_device *dev, bool sleep)
353 const struct netdev_hw_addr *ha;
354 int uc_cnt = netdev_uc_count(dev);
355 int mc_cnt = netdev_mc_count(dev);
356 const struct port_info *pi = netdev_priv(dev);
357 unsigned int mb = pi->adapter->pf;
359 /* first do the secondary unicast addresses */
360 netdev_for_each_uc_addr(ha, dev) {
361 addr[naddr++] = ha->addr;
362 if (--uc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
363 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
364 naddr, addr, filt_idx, &uhash, sleep);
373 /* next set up the multicast addresses */
374 netdev_for_each_mc_addr(ha, dev) {
375 addr[naddr++] = ha->addr;
376 if (--mc_cnt == 0 || naddr >= ARRAY_SIZE(addr)) {
377 ret = t4_alloc_mac_filt(pi->adapter, mb, pi->viid, free,
378 naddr, addr, filt_idx, &mhash, sleep);
387 return t4_set_addr_hash(pi->adapter, mb, pi->viid, uhash != 0,
388 uhash | mhash, sleep);
391 int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
392 module_param(dbfifo_int_thresh, int, 0644);
393 MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
396 * usecs to sleep while draining the dbfifo
398 static int dbfifo_drain_delay = 1000;
399 module_param(dbfifo_drain_delay, int, 0644);
400 MODULE_PARM_DESC(dbfifo_drain_delay,
401 "usecs to sleep while draining the dbfifo");
404 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
405 * If @mtu is -1 it is left unchanged.
407 static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
410 struct port_info *pi = netdev_priv(dev);
412 ret = set_addr_filters(dev, sleep_ok);
414 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, mtu,
415 (dev->flags & IFF_PROMISC) ? 1 : 0,
416 (dev->flags & IFF_ALLMULTI) ? 1 : 0, 1, -1,
422 * link_start - enable a port
423 * @dev: the port to enable
425 * Performs the MAC and PHY actions needed to enable a port.
427 static int link_start(struct net_device *dev)
430 struct port_info *pi = netdev_priv(dev);
431 unsigned int mb = pi->adapter->pf;
434 * We do not set address filters and promiscuity here, the stack does
435 * that step explicitly.
437 ret = t4_set_rxmode(pi->adapter, mb, pi->viid, dev->mtu, -1, -1, -1,
438 !!(dev->features & NETIF_F_HW_VLAN_CTAG_RX), true);
440 ret = t4_change_mac(pi->adapter, mb, pi->viid,
441 pi->xact_addr_filt, dev->dev_addr, true,
444 pi->xact_addr_filt = ret;
449 ret = t4_link_l1cfg(pi->adapter, mb, pi->tx_chan,
453 ret = t4_enable_vi_params(pi->adapter, mb, pi->viid, true,
454 true, CXGB4_DCB_ENABLED);
461 int cxgb4_dcb_enabled(const struct net_device *dev)
463 #ifdef CONFIG_CHELSIO_T4_DCB
464 struct port_info *pi = netdev_priv(dev);
466 if (!pi->dcb.enabled)
469 return ((pi->dcb.state == CXGB4_DCB_STATE_FW_ALLSYNCED) ||
470 (pi->dcb.state == CXGB4_DCB_STATE_HOST));
475 EXPORT_SYMBOL(cxgb4_dcb_enabled);
477 #ifdef CONFIG_CHELSIO_T4_DCB
478 /* Handle a Data Center Bridging update message from the firmware. */
479 static void dcb_rpl(struct adapter *adap, const struct fw_port_cmd *pcmd)
481 int port = FW_PORT_CMD_PORTID_G(ntohl(pcmd->op_to_portid));
482 struct net_device *dev = adap->port[port];
483 int old_dcb_enabled = cxgb4_dcb_enabled(dev);
486 cxgb4_dcb_handle_fw_update(adap, pcmd);
487 new_dcb_enabled = cxgb4_dcb_enabled(dev);
489 /* If the DCB has become enabled or disabled on the port then we're
490 * going to need to set up/tear down DCB Priority parameters for the
491 * TX Queues associated with the port.
493 if (new_dcb_enabled != old_dcb_enabled)
494 dcb_tx_queue_prio_enable(dev, new_dcb_enabled);
496 #endif /* CONFIG_CHELSIO_T4_DCB */
498 /* Clear a filter and release any of its resources that we own. This also
499 * clears the filter's "pending" status.
501 static void clear_filter(struct adapter *adap, struct filter_entry *f)
503 /* If the new or old filter have loopback rewriteing rules then we'll
504 * need to free any existing Layer Two Table (L2T) entries of the old
505 * filter rule. The firmware will handle freeing up any Source MAC
506 * Table (SMT) entries used for rewriting Source MAC Addresses in
510 cxgb4_l2t_release(f->l2t);
512 /* The zeroing of the filter rule below clears the filter valid,
513 * pending, locked flags, l2t pointer, etc. so it's all we need for
516 memset(f, 0, sizeof(*f));
519 /* Handle a filter write/deletion reply.
521 static void filter_rpl(struct adapter *adap, const struct cpl_set_tcb_rpl *rpl)
523 unsigned int idx = GET_TID(rpl);
524 unsigned int nidx = idx - adap->tids.ftid_base;
526 struct filter_entry *f;
528 if (idx >= adap->tids.ftid_base && nidx <
529 (adap->tids.nftids + adap->tids.nsftids)) {
531 ret = TCB_COOKIE_G(rpl->cookie);
532 f = &adap->tids.ftid_tab[idx];
534 if (ret == FW_FILTER_WR_FLT_DELETED) {
535 /* Clear the filter when we get confirmation from the
536 * hardware that the filter has been deleted.
538 clear_filter(adap, f);
539 } else if (ret == FW_FILTER_WR_SMT_TBL_FULL) {
540 dev_err(adap->pdev_dev, "filter %u setup failed due to full SMT\n",
542 clear_filter(adap, f);
543 } else if (ret == FW_FILTER_WR_FLT_ADDED) {
544 f->smtidx = (be64_to_cpu(rpl->oldval) >> 24) & 0xff;
545 f->pending = 0; /* asynchronous setup completed */
548 /* Something went wrong. Issue a warning about the
549 * problem and clear everything out.
551 dev_err(adap->pdev_dev, "filter %u setup failed with error %u\n",
553 clear_filter(adap, f);
558 /* Response queue handler for the FW event queue.
560 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp,
561 const struct pkt_gl *gl)
563 u8 opcode = ((const struct rss_header *)rsp)->opcode;
565 rsp++; /* skip RSS header */
567 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
569 if (unlikely(opcode == CPL_FW4_MSG &&
570 ((const struct cpl_fw4_msg *)rsp)->type == FW_TYPE_RSSCPL)) {
572 opcode = ((const struct rss_header *)rsp)->opcode;
574 if (opcode != CPL_SGE_EGR_UPDATE) {
575 dev_err(q->adap->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
581 if (likely(opcode == CPL_SGE_EGR_UPDATE)) {
582 const struct cpl_sge_egr_update *p = (void *)rsp;
583 unsigned int qid = EGR_QID_G(ntohl(p->opcode_qid));
586 txq = q->adap->sge.egr_map[qid - q->adap->sge.egr_start];
588 if ((u8 *)txq < (u8 *)q->adap->sge.ofldtxq) {
589 struct sge_eth_txq *eq;
591 eq = container_of(txq, struct sge_eth_txq, q);
592 netif_tx_wake_queue(eq->txq);
594 struct sge_ofld_txq *oq;
596 oq = container_of(txq, struct sge_ofld_txq, q);
597 tasklet_schedule(&oq->qresume_tsk);
599 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) {
600 const struct cpl_fw6_msg *p = (void *)rsp;
602 #ifdef CONFIG_CHELSIO_T4_DCB
603 const struct fw_port_cmd *pcmd = (const void *)p->data;
604 unsigned int cmd = FW_CMD_OP_G(ntohl(pcmd->op_to_portid));
605 unsigned int action =
606 FW_PORT_CMD_ACTION_G(ntohl(pcmd->action_to_len16));
608 if (cmd == FW_PORT_CMD &&
609 action == FW_PORT_ACTION_GET_PORT_INFO) {
610 int port = FW_PORT_CMD_PORTID_G(
611 be32_to_cpu(pcmd->op_to_portid));
612 struct net_device *dev = q->adap->port[port];
613 int state_input = ((pcmd->u.info.dcbxdis_pkd &
614 FW_PORT_CMD_DCBXDIS_F)
615 ? CXGB4_DCB_INPUT_FW_DISABLED
616 : CXGB4_DCB_INPUT_FW_ENABLED);
618 cxgb4_dcb_state_fsm(dev, state_input);
621 if (cmd == FW_PORT_CMD &&
622 action == FW_PORT_ACTION_L2_DCB_CFG)
623 dcb_rpl(q->adap, pcmd);
627 t4_handle_fw_rpl(q->adap, p->data);
628 } else if (opcode == CPL_L2T_WRITE_RPL) {
629 const struct cpl_l2t_write_rpl *p = (void *)rsp;
631 do_l2t_write_rpl(q->adap, p);
632 } else if (opcode == CPL_SET_TCB_RPL) {
633 const struct cpl_set_tcb_rpl *p = (void *)rsp;
635 filter_rpl(q->adap, p);
637 dev_err(q->adap->pdev_dev,
638 "unexpected CPL %#x on FW event queue\n", opcode);
644 * uldrx_handler - response queue handler for ULD queues
645 * @q: the response queue that received the packet
646 * @rsp: the response queue descriptor holding the offload message
647 * @gl: the gather list of packet fragments
649 * Deliver an ingress offload packet to a ULD. All processing is done by
650 * the ULD, we just maintain statistics.
652 static int uldrx_handler(struct sge_rspq *q, const __be64 *rsp,
653 const struct pkt_gl *gl)
655 struct sge_ofld_rxq *rxq = container_of(q, struct sge_ofld_rxq, rspq);
657 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
659 if (((const struct rss_header *)rsp)->opcode == CPL_FW4_MSG &&
660 ((const struct cpl_fw4_msg *)(rsp + 1))->type == FW_TYPE_RSSCPL)
663 if (ulds[q->uld].rx_handler(q->adap->uld_handle[q->uld], rsp, gl)) {
669 else if (gl == CXGB4_MSG_AN)
676 static void disable_msi(struct adapter *adapter)
678 if (adapter->flags & USING_MSIX) {
679 pci_disable_msix(adapter->pdev);
680 adapter->flags &= ~USING_MSIX;
681 } else if (adapter->flags & USING_MSI) {
682 pci_disable_msi(adapter->pdev);
683 adapter->flags &= ~USING_MSI;
688 * Interrupt handler for non-data events used with MSI-X.
690 static irqreturn_t t4_nondata_intr(int irq, void *cookie)
692 struct adapter *adap = cookie;
693 u32 v = t4_read_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A));
697 t4_write_reg(adap, MYPF_REG(PL_PF_INT_CAUSE_A), v);
699 if (adap->flags & MASTER_PF)
700 t4_slow_intr_handler(adap);
705 * Name the MSI-X interrupts.
707 static void name_msix_vecs(struct adapter *adap)
709 int i, j, msi_idx = 2, n = sizeof(adap->msix_info[0].desc);
711 /* non-data interrupts */
712 snprintf(adap->msix_info[0].desc, n, "%s", adap->port[0]->name);
715 snprintf(adap->msix_info[1].desc, n, "%s-FWeventq",
716 adap->port[0]->name);
718 /* Ethernet queues */
719 for_each_port(adap, j) {
720 struct net_device *d = adap->port[j];
721 const struct port_info *pi = netdev_priv(d);
723 for (i = 0; i < pi->nqsets; i++, msi_idx++)
724 snprintf(adap->msix_info[msi_idx].desc, n, "%s-Rx%d",
729 for_each_iscsirxq(&adap->sge, i)
730 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-iscsi%d",
731 adap->port[0]->name, i);
733 for_each_rdmarxq(&adap->sge, i)
734 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma%d",
735 adap->port[0]->name, i);
737 for_each_rdmaciq(&adap->sge, i)
738 snprintf(adap->msix_info[msi_idx++].desc, n, "%s-rdma-ciq%d",
739 adap->port[0]->name, i);
742 static int request_msix_queue_irqs(struct adapter *adap)
744 struct sge *s = &adap->sge;
745 int err, ethqidx, iscsiqidx = 0, rdmaqidx = 0, rdmaciqqidx = 0;
748 err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
749 adap->msix_info[1].desc, &s->fw_evtq);
753 for_each_ethrxq(s, ethqidx) {
754 err = request_irq(adap->msix_info[msi_index].vec,
756 adap->msix_info[msi_index].desc,
757 &s->ethrxq[ethqidx].rspq);
762 for_each_iscsirxq(s, iscsiqidx) {
763 err = request_irq(adap->msix_info[msi_index].vec,
765 adap->msix_info[msi_index].desc,
766 &s->iscsirxq[iscsiqidx].rspq);
771 for_each_rdmarxq(s, rdmaqidx) {
772 err = request_irq(adap->msix_info[msi_index].vec,
774 adap->msix_info[msi_index].desc,
775 &s->rdmarxq[rdmaqidx].rspq);
780 for_each_rdmaciq(s, rdmaciqqidx) {
781 err = request_irq(adap->msix_info[msi_index].vec,
783 adap->msix_info[msi_index].desc,
784 &s->rdmaciq[rdmaciqqidx].rspq);
792 while (--rdmaciqqidx >= 0)
793 free_irq(adap->msix_info[--msi_index].vec,
794 &s->rdmaciq[rdmaciqqidx].rspq);
795 while (--rdmaqidx >= 0)
796 free_irq(adap->msix_info[--msi_index].vec,
797 &s->rdmarxq[rdmaqidx].rspq);
798 while (--iscsiqidx >= 0)
799 free_irq(adap->msix_info[--msi_index].vec,
800 &s->iscsirxq[iscsiqidx].rspq);
801 while (--ethqidx >= 0)
802 free_irq(adap->msix_info[--msi_index].vec,
803 &s->ethrxq[ethqidx].rspq);
804 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
808 static void free_msix_queue_irqs(struct adapter *adap)
810 int i, msi_index = 2;
811 struct sge *s = &adap->sge;
813 free_irq(adap->msix_info[1].vec, &s->fw_evtq);
814 for_each_ethrxq(s, i)
815 free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
816 for_each_iscsirxq(s, i)
817 free_irq(adap->msix_info[msi_index++].vec,
818 &s->iscsirxq[i].rspq);
819 for_each_rdmarxq(s, i)
820 free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
821 for_each_rdmaciq(s, i)
822 free_irq(adap->msix_info[msi_index++].vec, &s->rdmaciq[i].rspq);
826 * cxgb4_write_rss - write the RSS table for a given port
828 * @queues: array of queue indices for RSS
830 * Sets up the portion of the HW RSS table for the port's VI to distribute
831 * packets to the Rx queues in @queues.
832 * Should never be called before setting up sge eth rx queues
834 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues)
838 struct adapter *adapter = pi->adapter;
839 const struct sge_eth_rxq *rxq;
841 rxq = &adapter->sge.ethrxq[pi->first_qset];
842 rss = kmalloc(pi->rss_size * sizeof(u16), GFP_KERNEL);
846 /* map the queue indices to queue ids */
847 for (i = 0; i < pi->rss_size; i++, queues++)
848 rss[i] = rxq[*queues].rspq.abs_id;
850 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0,
851 pi->rss_size, rss, pi->rss_size);
852 /* If Tunnel All Lookup isn't specified in the global RSS
853 * Configuration, then we need to specify a default Ingress
854 * Queue for any ingress packets which aren't hashed. We'll
855 * use our first ingress queue ...
858 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid,
859 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F |
860 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F |
861 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F |
862 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F |
863 FW_RSS_VI_CONFIG_CMD_UDPEN_F,
870 * setup_rss - configure RSS
873 * Sets up RSS for each port.
875 static int setup_rss(struct adapter *adap)
879 for_each_port(adap, i) {
880 const struct port_info *pi = adap2pinfo(adap, i);
882 /* Fill default values with equal distribution */
883 for (j = 0; j < pi->rss_size; j++)
884 pi->rss[j] = j % pi->nqsets;
886 err = cxgb4_write_rss(pi, pi->rss);
894 * Return the channel of the ingress queue with the given qid.
896 static unsigned int rxq_to_chan(const struct sge *p, unsigned int qid)
898 qid -= p->ingr_start;
899 return netdev2pinfo(p->ingr_map[qid]->netdev)->tx_chan;
903 * Wait until all NAPI handlers are descheduled.
905 static void quiesce_rx(struct adapter *adap)
909 for (i = 0; i < adap->sge.ingr_sz; i++) {
910 struct sge_rspq *q = adap->sge.ingr_map[i];
912 if (q && q->handler) {
913 napi_disable(&q->napi);
915 while (!cxgb_poll_lock_napi(q))
923 /* Disable interrupt and napi handler */
924 static void disable_interrupts(struct adapter *adap)
926 if (adap->flags & FULL_INIT_DONE) {
927 t4_intr_disable(adap);
928 if (adap->flags & USING_MSIX) {
929 free_msix_queue_irqs(adap);
930 free_irq(adap->msix_info[0].vec, adap);
932 free_irq(adap->pdev->irq, adap);
939 * Enable NAPI scheduling and interrupt generation for all Rx queues.
941 static void enable_rx(struct adapter *adap)
945 for (i = 0; i < adap->sge.ingr_sz; i++) {
946 struct sge_rspq *q = adap->sge.ingr_map[i];
951 cxgb_busy_poll_init_lock(q);
952 napi_enable(&q->napi);
954 /* 0-increment GTS to start the timer and enable interrupts */
955 t4_write_reg(adap, MYPF_REG(SGE_PF_GTS_A),
956 SEINTARM_V(q->intr_params) |
957 INGRESSQID_V(q->cntxt_id));
961 static int alloc_ofld_rxqs(struct adapter *adap, struct sge_ofld_rxq *q,
962 unsigned int nq, unsigned int per_chan, int msi_idx,
967 for (i = 0; i < nq; i++, q++) {
970 err = t4_sge_alloc_rxq(adap, &q->rspq, false,
971 adap->port[i / per_chan],
972 msi_idx, q->fl.size ? &q->fl : NULL,
976 memset(&q->stats, 0, sizeof(q->stats));
978 ids[i] = q->rspq.abs_id;
984 * setup_sge_queues - configure SGE Tx/Rx/response queues
987 * Determines how many sets of SGE queues to use and initializes them.
988 * We support multiple queue sets per port if we have MSI-X, otherwise
989 * just one queue set per port.
991 static int setup_sge_queues(struct adapter *adap)
993 int err, msi_idx, i, j;
994 struct sge *s = &adap->sge;
996 bitmap_zero(s->starving_fl, s->egr_sz);
997 bitmap_zero(s->txq_maperr, s->egr_sz);
999 if (adap->flags & USING_MSIX)
1000 msi_idx = 1; /* vector 0 is for non-queue interrupts */
1002 err = t4_sge_alloc_rxq(adap, &s->intrq, false, adap->port[0], 0,
1006 msi_idx = -((int)s->intrq.abs_id + 1);
1009 /* NOTE: If you add/delete any Ingress/Egress Queue allocations in here,
1010 * don't forget to update the following which need to be
1011 * synchronized to and changes here.
1013 * 1. The calculations of MAX_INGQ in cxgb4.h.
1015 * 2. Update enable_msix/name_msix_vecs/request_msix_queue_irqs
1016 * to accommodate any new/deleted Ingress Queues
1017 * which need MSI-X Vectors.
1019 * 3. Update sge_qinfo_show() to include information on the
1020 * new/deleted queues.
1022 err = t4_sge_alloc_rxq(adap, &s->fw_evtq, true, adap->port[0],
1023 msi_idx, NULL, fwevtq_handler, -1);
1025 freeout: t4_free_sge_resources(adap);
1029 for_each_port(adap, i) {
1030 struct net_device *dev = adap->port[i];
1031 struct port_info *pi = netdev_priv(dev);
1032 struct sge_eth_rxq *q = &s->ethrxq[pi->first_qset];
1033 struct sge_eth_txq *t = &s->ethtxq[pi->first_qset];
1035 for (j = 0; j < pi->nqsets; j++, q++) {
1038 err = t4_sge_alloc_rxq(adap, &q->rspq, false, dev,
1041 t4_get_mps_bg_map(adap,
1046 memset(&q->stats, 0, sizeof(q->stats));
1048 for (j = 0; j < pi->nqsets; j++, t++) {
1049 err = t4_sge_alloc_eth_txq(adap, t, dev,
1050 netdev_get_tx_queue(dev, j),
1051 s->fw_evtq.cntxt_id);
1057 j = s->iscsiqsets / adap->params.nports; /* iscsi queues per channel */
1058 for_each_iscsirxq(s, i) {
1059 err = t4_sge_alloc_ofld_txq(adap, &s->ofldtxq[i],
1061 s->fw_evtq.cntxt_id);
1066 #define ALLOC_OFLD_RXQS(firstq, nq, per_chan, ids) do { \
1067 err = alloc_ofld_rxqs(adap, firstq, nq, per_chan, msi_idx, ids); \
1074 ALLOC_OFLD_RXQS(s->iscsirxq, s->iscsiqsets, j, s->iscsi_rxq);
1075 ALLOC_OFLD_RXQS(s->rdmarxq, s->rdmaqs, 1, s->rdma_rxq);
1076 j = s->rdmaciqs / adap->params.nports; /* rdmaq queues per channel */
1077 ALLOC_OFLD_RXQS(s->rdmaciq, s->rdmaciqs, j, s->rdma_ciq);
1079 #undef ALLOC_OFLD_RXQS
1081 for_each_port(adap, i) {
1083 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1084 * have RDMA queues, and that's the right value.
1086 err = t4_sge_alloc_ctrl_txq(adap, &s->ctrlq[i], adap->port[i],
1087 s->fw_evtq.cntxt_id,
1088 s->rdmarxq[i].rspq.cntxt_id);
1093 t4_write_reg(adap, is_t4(adap->params.chip) ?
1094 MPS_TRC_RSS_CONTROL_A :
1095 MPS_T5_TRC_RSS_CONTROL_A,
1096 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1097 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1102 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1103 * The allocated memory is cleared.
1105 void *t4_alloc_mem(size_t size)
1107 void *p = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
1115 * Free memory allocated through alloc_mem().
1117 void t4_free_mem(void *addr)
1122 /* Send a Work Request to write the filter at a specified index. We construct
1123 * a Firmware Filter Work Request to have the work done and put the indicated
1124 * filter into "pending" mode which will prevent any further actions against
1125 * it till we get a reply from the firmware on the completion status of the
1128 static int set_filter_wr(struct adapter *adapter, int fidx)
1130 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1131 struct sk_buff *skb;
1132 struct fw_filter_wr *fwr;
1135 skb = alloc_skb(sizeof(*fwr), GFP_KERNEL);
1139 /* If the new filter requires loopback Destination MAC and/or VLAN
1140 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1143 if (f->fs.newdmac || f->fs.newvlan) {
1144 /* allocate L2T entry for new filter */
1145 f->l2t = t4_l2t_alloc_switching(adapter, f->fs.vlan,
1146 f->fs.eport, f->fs.dmac);
1147 if (f->l2t == NULL) {
1153 ftid = adapter->tids.ftid_base + fidx;
1155 fwr = (struct fw_filter_wr *)__skb_put(skb, sizeof(*fwr));
1156 memset(fwr, 0, sizeof(*fwr));
1158 /* It would be nice to put most of the following in t4_hw.c but most
1159 * of the work is translating the cxgbtool ch_filter_specification
1160 * into the Work Request and the definition of that structure is
1161 * currently in cxgbtool.h which isn't appropriate to pull into the
1162 * common code. We may eventually try to come up with a more neutral
1163 * filter specification structure but for now it's easiest to simply
1164 * put this fairly direct code in line ...
1166 fwr->op_pkd = htonl(FW_WR_OP_V(FW_FILTER_WR));
1167 fwr->len16_pkd = htonl(FW_WR_LEN16_V(sizeof(*fwr)/16));
1169 htonl(FW_FILTER_WR_TID_V(ftid) |
1170 FW_FILTER_WR_RQTYPE_V(f->fs.type) |
1171 FW_FILTER_WR_NOREPLY_V(0) |
1172 FW_FILTER_WR_IQ_V(f->fs.iq));
1173 fwr->del_filter_to_l2tix =
1174 htonl(FW_FILTER_WR_RPTTID_V(f->fs.rpttid) |
1175 FW_FILTER_WR_DROP_V(f->fs.action == FILTER_DROP) |
1176 FW_FILTER_WR_DIRSTEER_V(f->fs.dirsteer) |
1177 FW_FILTER_WR_MASKHASH_V(f->fs.maskhash) |
1178 FW_FILTER_WR_DIRSTEERHASH_V(f->fs.dirsteerhash) |
1179 FW_FILTER_WR_LPBK_V(f->fs.action == FILTER_SWITCH) |
1180 FW_FILTER_WR_DMAC_V(f->fs.newdmac) |
1181 FW_FILTER_WR_SMAC_V(f->fs.newsmac) |
1182 FW_FILTER_WR_INSVLAN_V(f->fs.newvlan == VLAN_INSERT ||
1183 f->fs.newvlan == VLAN_REWRITE) |
1184 FW_FILTER_WR_RMVLAN_V(f->fs.newvlan == VLAN_REMOVE ||
1185 f->fs.newvlan == VLAN_REWRITE) |
1186 FW_FILTER_WR_HITCNTS_V(f->fs.hitcnts) |
1187 FW_FILTER_WR_TXCHAN_V(f->fs.eport) |
1188 FW_FILTER_WR_PRIO_V(f->fs.prio) |
1189 FW_FILTER_WR_L2TIX_V(f->l2t ? f->l2t->idx : 0));
1190 fwr->ethtype = htons(f->fs.val.ethtype);
1191 fwr->ethtypem = htons(f->fs.mask.ethtype);
1192 fwr->frag_to_ovlan_vldm =
1193 (FW_FILTER_WR_FRAG_V(f->fs.val.frag) |
1194 FW_FILTER_WR_FRAGM_V(f->fs.mask.frag) |
1195 FW_FILTER_WR_IVLAN_VLD_V(f->fs.val.ivlan_vld) |
1196 FW_FILTER_WR_OVLAN_VLD_V(f->fs.val.ovlan_vld) |
1197 FW_FILTER_WR_IVLAN_VLDM_V(f->fs.mask.ivlan_vld) |
1198 FW_FILTER_WR_OVLAN_VLDM_V(f->fs.mask.ovlan_vld));
1200 fwr->rx_chan_rx_rpl_iq =
1201 htons(FW_FILTER_WR_RX_CHAN_V(0) |
1202 FW_FILTER_WR_RX_RPL_IQ_V(adapter->sge.fw_evtq.abs_id));
1203 fwr->maci_to_matchtypem =
1204 htonl(FW_FILTER_WR_MACI_V(f->fs.val.macidx) |
1205 FW_FILTER_WR_MACIM_V(f->fs.mask.macidx) |
1206 FW_FILTER_WR_FCOE_V(f->fs.val.fcoe) |
1207 FW_FILTER_WR_FCOEM_V(f->fs.mask.fcoe) |
1208 FW_FILTER_WR_PORT_V(f->fs.val.iport) |
1209 FW_FILTER_WR_PORTM_V(f->fs.mask.iport) |
1210 FW_FILTER_WR_MATCHTYPE_V(f->fs.val.matchtype) |
1211 FW_FILTER_WR_MATCHTYPEM_V(f->fs.mask.matchtype));
1212 fwr->ptcl = f->fs.val.proto;
1213 fwr->ptclm = f->fs.mask.proto;
1214 fwr->ttyp = f->fs.val.tos;
1215 fwr->ttypm = f->fs.mask.tos;
1216 fwr->ivlan = htons(f->fs.val.ivlan);
1217 fwr->ivlanm = htons(f->fs.mask.ivlan);
1218 fwr->ovlan = htons(f->fs.val.ovlan);
1219 fwr->ovlanm = htons(f->fs.mask.ovlan);
1220 memcpy(fwr->lip, f->fs.val.lip, sizeof(fwr->lip));
1221 memcpy(fwr->lipm, f->fs.mask.lip, sizeof(fwr->lipm));
1222 memcpy(fwr->fip, f->fs.val.fip, sizeof(fwr->fip));
1223 memcpy(fwr->fipm, f->fs.mask.fip, sizeof(fwr->fipm));
1224 fwr->lp = htons(f->fs.val.lport);
1225 fwr->lpm = htons(f->fs.mask.lport);
1226 fwr->fp = htons(f->fs.val.fport);
1227 fwr->fpm = htons(f->fs.mask.fport);
1229 memcpy(fwr->sma, f->fs.smac, sizeof(fwr->sma));
1231 /* Mark the filter as "pending" and ship off the Filter Work Request.
1232 * When we get the Work Request Reply we'll clear the pending status.
1235 set_wr_txq(skb, CPL_PRIORITY_CONTROL, f->fs.val.iport & 0x3);
1236 t4_ofld_send(adapter, skb);
1240 /* Delete the filter at a specified index.
1242 static int del_filter_wr(struct adapter *adapter, int fidx)
1244 struct filter_entry *f = &adapter->tids.ftid_tab[fidx];
1245 struct sk_buff *skb;
1246 struct fw_filter_wr *fwr;
1247 unsigned int len, ftid;
1250 ftid = adapter->tids.ftid_base + fidx;
1252 skb = alloc_skb(len, GFP_KERNEL);
1256 fwr = (struct fw_filter_wr *)__skb_put(skb, len);
1257 t4_mk_filtdelwr(ftid, fwr, adapter->sge.fw_evtq.abs_id);
1259 /* Mark the filter as "pending" and ship off the Filter Work Request.
1260 * When we get the Work Request Reply we'll clear the pending status.
1263 t4_mgmt_tx(adapter, skb);
1267 static u16 cxgb_select_queue(struct net_device *dev, struct sk_buff *skb,
1268 void *accel_priv, select_queue_fallback_t fallback)
1272 #ifdef CONFIG_CHELSIO_T4_DCB
1273 /* If a Data Center Bridging has been successfully negotiated on this
1274 * link then we'll use the skb's priority to map it to a TX Queue.
1275 * The skb's priority is determined via the VLAN Tag Priority Code
1278 if (cxgb4_dcb_enabled(dev)) {
1282 err = vlan_get_tag(skb, &vlan_tci);
1283 if (unlikely(err)) {
1284 if (net_ratelimit())
1286 "TX Packet without VLAN Tag on DCB Link\n");
1289 txq = (vlan_tci & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
1290 #ifdef CONFIG_CHELSIO_T4_FCOE
1291 if (skb->protocol == htons(ETH_P_FCOE))
1292 txq = skb->priority & 0x7;
1293 #endif /* CONFIG_CHELSIO_T4_FCOE */
1297 #endif /* CONFIG_CHELSIO_T4_DCB */
1300 txq = (skb_rx_queue_recorded(skb)
1301 ? skb_get_rx_queue(skb)
1302 : smp_processor_id());
1304 while (unlikely(txq >= dev->real_num_tx_queues))
1305 txq -= dev->real_num_tx_queues;
1310 return fallback(dev, skb) % dev->real_num_tx_queues;
1313 static int closest_timer(const struct sge *s, int time)
1315 int i, delta, match = 0, min_delta = INT_MAX;
1317 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
1318 delta = time - s->timer_val[i];
1321 if (delta < min_delta) {
1329 static int closest_thres(const struct sge *s, int thres)
1331 int i, delta, match = 0, min_delta = INT_MAX;
1333 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
1334 delta = thres - s->counter_val[i];
1337 if (delta < min_delta) {
1346 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters
1348 * @us: the hold-off time in us, or 0 to disable timer
1349 * @cnt: the hold-off packet count, or 0 to disable counter
1351 * Sets an Rx queue's interrupt hold-off time and packet count. At least
1352 * one of the two needs to be enabled for the queue to generate interrupts.
1354 int cxgb4_set_rspq_intr_params(struct sge_rspq *q,
1355 unsigned int us, unsigned int cnt)
1357 struct adapter *adap = q->adap;
1359 if ((us | cnt) == 0)
1366 new_idx = closest_thres(&adap->sge, cnt);
1367 if (q->desc && q->pktcnt_idx != new_idx) {
1368 /* the queue has already been created, update it */
1369 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1370 FW_PARAMS_PARAM_X_V(
1371 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1372 FW_PARAMS_PARAM_YZ_V(q->cntxt_id);
1373 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1,
1378 q->pktcnt_idx = new_idx;
1381 us = us == 0 ? 6 : closest_timer(&adap->sge, us);
1382 q->intr_params = QINTR_TIMER_IDX_V(us) | QINTR_CNT_EN_V(cnt > 0);
1386 static int cxgb_set_features(struct net_device *dev, netdev_features_t features)
1388 const struct port_info *pi = netdev_priv(dev);
1389 netdev_features_t changed = dev->features ^ features;
1392 if (!(changed & NETIF_F_HW_VLAN_CTAG_RX))
1395 err = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, -1,
1397 !!(features & NETIF_F_HW_VLAN_CTAG_RX), true);
1399 dev->features = features ^ NETIF_F_HW_VLAN_CTAG_RX;
1403 static int setup_debugfs(struct adapter *adap)
1405 if (IS_ERR_OR_NULL(adap->debugfs_root))
1408 #ifdef CONFIG_DEBUG_FS
1409 t4_setup_debugfs(adap);
1415 * upper-layer driver support
1419 * Allocate an active-open TID and set it to the supplied value.
1421 int cxgb4_alloc_atid(struct tid_info *t, void *data)
1425 spin_lock_bh(&t->atid_lock);
1427 union aopen_entry *p = t->afree;
1429 atid = (p - t->atid_tab) + t->atid_base;
1434 spin_unlock_bh(&t->atid_lock);
1437 EXPORT_SYMBOL(cxgb4_alloc_atid);
1440 * Release an active-open TID.
1442 void cxgb4_free_atid(struct tid_info *t, unsigned int atid)
1444 union aopen_entry *p = &t->atid_tab[atid - t->atid_base];
1446 spin_lock_bh(&t->atid_lock);
1450 spin_unlock_bh(&t->atid_lock);
1452 EXPORT_SYMBOL(cxgb4_free_atid);
1455 * Allocate a server TID and set it to the supplied value.
1457 int cxgb4_alloc_stid(struct tid_info *t, int family, void *data)
1461 spin_lock_bh(&t->stid_lock);
1462 if (family == PF_INET) {
1463 stid = find_first_zero_bit(t->stid_bmap, t->nstids);
1464 if (stid < t->nstids)
1465 __set_bit(stid, t->stid_bmap);
1469 stid = bitmap_find_free_region(t->stid_bmap, t->nstids, 1);
1474 t->stid_tab[stid].data = data;
1475 stid += t->stid_base;
1476 /* IPv6 requires max of 520 bits or 16 cells in TCAM
1477 * This is equivalent to 4 TIDs. With CLIP enabled it
1480 if (family == PF_INET)
1483 t->stids_in_use += 2;
1485 spin_unlock_bh(&t->stid_lock);
1488 EXPORT_SYMBOL(cxgb4_alloc_stid);
1490 /* Allocate a server filter TID and set it to the supplied value.
1492 int cxgb4_alloc_sftid(struct tid_info *t, int family, void *data)
1496 spin_lock_bh(&t->stid_lock);
1497 if (family == PF_INET) {
1498 stid = find_next_zero_bit(t->stid_bmap,
1499 t->nstids + t->nsftids, t->nstids);
1500 if (stid < (t->nstids + t->nsftids))
1501 __set_bit(stid, t->stid_bmap);
1508 t->stid_tab[stid].data = data;
1510 stid += t->sftid_base;
1513 spin_unlock_bh(&t->stid_lock);
1516 EXPORT_SYMBOL(cxgb4_alloc_sftid);
1518 /* Release a server TID.
1520 void cxgb4_free_stid(struct tid_info *t, unsigned int stid, int family)
1522 /* Is it a server filter TID? */
1523 if (t->nsftids && (stid >= t->sftid_base)) {
1524 stid -= t->sftid_base;
1527 stid -= t->stid_base;
1530 spin_lock_bh(&t->stid_lock);
1531 if (family == PF_INET)
1532 __clear_bit(stid, t->stid_bmap);
1534 bitmap_release_region(t->stid_bmap, stid, 1);
1535 t->stid_tab[stid].data = NULL;
1536 if (stid < t->nstids) {
1537 if (family == PF_INET)
1540 t->stids_in_use -= 2;
1544 spin_unlock_bh(&t->stid_lock);
1546 EXPORT_SYMBOL(cxgb4_free_stid);
1549 * Populate a TID_RELEASE WR. Caller must properly size the skb.
1551 static void mk_tid_release(struct sk_buff *skb, unsigned int chan,
1554 struct cpl_tid_release *req;
1556 set_wr_txq(skb, CPL_PRIORITY_SETUP, chan);
1557 req = (struct cpl_tid_release *)__skb_put(skb, sizeof(*req));
1558 INIT_TP_WR(req, tid);
1559 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE, tid));
1563 * Queue a TID release request and if necessary schedule a work queue to
1566 static void cxgb4_queue_tid_release(struct tid_info *t, unsigned int chan,
1569 void **p = &t->tid_tab[tid];
1570 struct adapter *adap = container_of(t, struct adapter, tids);
1572 spin_lock_bh(&adap->tid_release_lock);
1573 *p = adap->tid_release_head;
1574 /* Low 2 bits encode the Tx channel number */
1575 adap->tid_release_head = (void **)((uintptr_t)p | chan);
1576 if (!adap->tid_release_task_busy) {
1577 adap->tid_release_task_busy = true;
1578 queue_work(adap->workq, &adap->tid_release_task);
1580 spin_unlock_bh(&adap->tid_release_lock);
1584 * Process the list of pending TID release requests.
1586 static void process_tid_release_list(struct work_struct *work)
1588 struct sk_buff *skb;
1589 struct adapter *adap;
1591 adap = container_of(work, struct adapter, tid_release_task);
1593 spin_lock_bh(&adap->tid_release_lock);
1594 while (adap->tid_release_head) {
1595 void **p = adap->tid_release_head;
1596 unsigned int chan = (uintptr_t)p & 3;
1597 p = (void *)p - chan;
1599 adap->tid_release_head = *p;
1601 spin_unlock_bh(&adap->tid_release_lock);
1603 while (!(skb = alloc_skb(sizeof(struct cpl_tid_release),
1605 schedule_timeout_uninterruptible(1);
1607 mk_tid_release(skb, chan, p - adap->tids.tid_tab);
1608 t4_ofld_send(adap, skb);
1609 spin_lock_bh(&adap->tid_release_lock);
1611 adap->tid_release_task_busy = false;
1612 spin_unlock_bh(&adap->tid_release_lock);
1616 * Release a TID and inform HW. If we are unable to allocate the release
1617 * message we defer to a work queue.
1619 void cxgb4_remove_tid(struct tid_info *t, unsigned int chan, unsigned int tid)
1621 struct sk_buff *skb;
1622 struct adapter *adap = container_of(t, struct adapter, tids);
1624 WARN_ON(tid >= t->ntids);
1626 if (t->tid_tab[tid]) {
1627 t->tid_tab[tid] = NULL;
1628 if (t->hash_base && (tid >= t->hash_base))
1629 atomic_dec(&t->hash_tids_in_use);
1631 atomic_dec(&t->tids_in_use);
1634 skb = alloc_skb(sizeof(struct cpl_tid_release), GFP_ATOMIC);
1636 mk_tid_release(skb, chan, tid);
1637 t4_ofld_send(adap, skb);
1639 cxgb4_queue_tid_release(t, chan, tid);
1641 EXPORT_SYMBOL(cxgb4_remove_tid);
1644 * Allocate and initialize the TID tables. Returns 0 on success.
1646 static int tid_init(struct tid_info *t)
1649 unsigned int stid_bmap_size;
1650 unsigned int natids = t->natids;
1651 struct adapter *adap = container_of(t, struct adapter, tids);
1653 stid_bmap_size = BITS_TO_LONGS(t->nstids + t->nsftids);
1654 size = t->ntids * sizeof(*t->tid_tab) +
1655 natids * sizeof(*t->atid_tab) +
1656 t->nstids * sizeof(*t->stid_tab) +
1657 t->nsftids * sizeof(*t->stid_tab) +
1658 stid_bmap_size * sizeof(long) +
1659 t->nftids * sizeof(*t->ftid_tab) +
1660 t->nsftids * sizeof(*t->ftid_tab);
1662 t->tid_tab = t4_alloc_mem(size);
1666 t->atid_tab = (union aopen_entry *)&t->tid_tab[t->ntids];
1667 t->stid_tab = (struct serv_entry *)&t->atid_tab[natids];
1668 t->stid_bmap = (unsigned long *)&t->stid_tab[t->nstids + t->nsftids];
1669 t->ftid_tab = (struct filter_entry *)&t->stid_bmap[stid_bmap_size];
1670 spin_lock_init(&t->stid_lock);
1671 spin_lock_init(&t->atid_lock);
1673 t->stids_in_use = 0;
1674 t->sftids_in_use = 0;
1676 t->atids_in_use = 0;
1677 atomic_set(&t->tids_in_use, 0);
1678 atomic_set(&t->hash_tids_in_use, 0);
1680 /* Setup the free list for atid_tab and clear the stid bitmap. */
1683 t->atid_tab[natids - 1].next = &t->atid_tab[natids];
1684 t->afree = t->atid_tab;
1686 bitmap_zero(t->stid_bmap, t->nstids + t->nsftids);
1687 /* Reserve stid 0 for T4/T5 adapters */
1688 if (!t->stid_base &&
1689 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
1690 __set_bit(0, t->stid_bmap);
1696 * cxgb4_create_server - create an IP server
1698 * @stid: the server TID
1699 * @sip: local IP address to bind server to
1700 * @sport: the server's TCP port
1701 * @queue: queue to direct messages from this server to
1703 * Create an IP server for the given port and address.
1704 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1706 int cxgb4_create_server(const struct net_device *dev, unsigned int stid,
1707 __be32 sip, __be16 sport, __be16 vlan,
1711 struct sk_buff *skb;
1712 struct adapter *adap;
1713 struct cpl_pass_open_req *req;
1716 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1720 adap = netdev2adap(dev);
1721 req = (struct cpl_pass_open_req *)__skb_put(skb, sizeof(*req));
1723 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, stid));
1724 req->local_port = sport;
1725 req->peer_port = htons(0);
1726 req->local_ip = sip;
1727 req->peer_ip = htonl(0);
1728 chan = rxq_to_chan(&adap->sge, queue);
1729 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1730 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1731 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1732 ret = t4_mgmt_tx(adap, skb);
1733 return net_xmit_eval(ret);
1735 EXPORT_SYMBOL(cxgb4_create_server);
1737 /* cxgb4_create_server6 - create an IPv6 server
1739 * @stid: the server TID
1740 * @sip: local IPv6 address to bind server to
1741 * @sport: the server's TCP port
1742 * @queue: queue to direct messages from this server to
1744 * Create an IPv6 server for the given port and address.
1745 * Returns <0 on error and one of the %NET_XMIT_* values on success.
1747 int cxgb4_create_server6(const struct net_device *dev, unsigned int stid,
1748 const struct in6_addr *sip, __be16 sport,
1752 struct sk_buff *skb;
1753 struct adapter *adap;
1754 struct cpl_pass_open_req6 *req;
1757 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1761 adap = netdev2adap(dev);
1762 req = (struct cpl_pass_open_req6 *)__skb_put(skb, sizeof(*req));
1764 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6, stid));
1765 req->local_port = sport;
1766 req->peer_port = htons(0);
1767 req->local_ip_hi = *(__be64 *)(sip->s6_addr);
1768 req->local_ip_lo = *(__be64 *)(sip->s6_addr + 8);
1769 req->peer_ip_hi = cpu_to_be64(0);
1770 req->peer_ip_lo = cpu_to_be64(0);
1771 chan = rxq_to_chan(&adap->sge, queue);
1772 req->opt0 = cpu_to_be64(TX_CHAN_V(chan));
1773 req->opt1 = cpu_to_be64(CONN_POLICY_V(CPL_CONN_POLICY_ASK) |
1774 SYN_RSS_ENABLE_F | SYN_RSS_QUEUE_V(queue));
1775 ret = t4_mgmt_tx(adap, skb);
1776 return net_xmit_eval(ret);
1778 EXPORT_SYMBOL(cxgb4_create_server6);
1780 int cxgb4_remove_server(const struct net_device *dev, unsigned int stid,
1781 unsigned int queue, bool ipv6)
1783 struct sk_buff *skb;
1784 struct adapter *adap;
1785 struct cpl_close_listsvr_req *req;
1788 adap = netdev2adap(dev);
1790 skb = alloc_skb(sizeof(*req), GFP_KERNEL);
1794 req = (struct cpl_close_listsvr_req *)__skb_put(skb, sizeof(*req));
1796 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ, stid));
1797 req->reply_ctrl = htons(NO_REPLY_V(0) | (ipv6 ? LISTSVR_IPV6_V(1) :
1798 LISTSVR_IPV6_V(0)) | QUEUENO_V(queue));
1799 ret = t4_mgmt_tx(adap, skb);
1800 return net_xmit_eval(ret);
1802 EXPORT_SYMBOL(cxgb4_remove_server);
1805 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
1806 * @mtus: the HW MTU table
1807 * @mtu: the target MTU
1808 * @idx: index of selected entry in the MTU table
1810 * Returns the index and the value in the HW MTU table that is closest to
1811 * but does not exceed @mtu, unless @mtu is smaller than any value in the
1812 * table, in which case that smallest available value is selected.
1814 unsigned int cxgb4_best_mtu(const unsigned short *mtus, unsigned short mtu,
1819 while (i < NMTUS - 1 && mtus[i + 1] <= mtu)
1825 EXPORT_SYMBOL(cxgb4_best_mtu);
1828 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
1829 * @mtus: the HW MTU table
1830 * @header_size: Header Size
1831 * @data_size_max: maximum Data Segment Size
1832 * @data_size_align: desired Data Segment Size Alignment (2^N)
1833 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
1835 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
1836 * MTU Table based solely on a Maximum MTU parameter, we break that
1837 * parameter up into a Header Size and Maximum Data Segment Size, and
1838 * provide a desired Data Segment Size Alignment. If we find an MTU in
1839 * the Hardware MTU Table which will result in a Data Segment Size with
1840 * the requested alignment _and_ that MTU isn't "too far" from the
1841 * closest MTU, then we'll return that rather than the closest MTU.
1843 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus,
1844 unsigned short header_size,
1845 unsigned short data_size_max,
1846 unsigned short data_size_align,
1847 unsigned int *mtu_idxp)
1849 unsigned short max_mtu = header_size + data_size_max;
1850 unsigned short data_size_align_mask = data_size_align - 1;
1851 int mtu_idx, aligned_mtu_idx;
1853 /* Scan the MTU Table till we find an MTU which is larger than our
1854 * Maximum MTU or we reach the end of the table. Along the way,
1855 * record the last MTU found, if any, which will result in a Data
1856 * Segment Length matching the requested alignment.
1858 for (mtu_idx = 0, aligned_mtu_idx = -1; mtu_idx < NMTUS; mtu_idx++) {
1859 unsigned short data_size = mtus[mtu_idx] - header_size;
1861 /* If this MTU minus the Header Size would result in a
1862 * Data Segment Size of the desired alignment, remember it.
1864 if ((data_size & data_size_align_mask) == 0)
1865 aligned_mtu_idx = mtu_idx;
1867 /* If we're not at the end of the Hardware MTU Table and the
1868 * next element is larger than our Maximum MTU, drop out of
1871 if (mtu_idx+1 < NMTUS && mtus[mtu_idx+1] > max_mtu)
1875 /* If we fell out of the loop because we ran to the end of the table,
1876 * then we just have to use the last [largest] entry.
1878 if (mtu_idx == NMTUS)
1881 /* If we found an MTU which resulted in the requested Data Segment
1882 * Length alignment and that's "not far" from the largest MTU which is
1883 * less than or equal to the maximum MTU, then use that.
1885 if (aligned_mtu_idx >= 0 &&
1886 mtu_idx - aligned_mtu_idx <= 1)
1887 mtu_idx = aligned_mtu_idx;
1889 /* If the caller has passed in an MTU Index pointer, pass the
1890 * MTU Index back. Return the MTU value.
1893 *mtu_idxp = mtu_idx;
1894 return mtus[mtu_idx];
1896 EXPORT_SYMBOL(cxgb4_best_aligned_mtu);
1899 * cxgb4_tp_smt_idx - Get the Source Mac Table index for this VI
1901 * @viid: VI id of the given port
1903 * Return the SMT index for this VI.
1905 unsigned int cxgb4_tp_smt_idx(enum chip_type chip, unsigned int viid)
1907 /* In T4/T5, SMT contains 256 SMAC entries organized in
1908 * 128 rows of 2 entries each.
1909 * In T6, SMT contains 256 SMAC entries in 256 rows.
1910 * TODO: The below code needs to be updated when we add support
1913 if (CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5)
1914 return ((viid & 0x7f) << 1);
1916 return (viid & 0x7f);
1918 EXPORT_SYMBOL(cxgb4_tp_smt_idx);
1921 * cxgb4_port_chan - get the HW channel of a port
1922 * @dev: the net device for the port
1924 * Return the HW Tx channel of the given port.
1926 unsigned int cxgb4_port_chan(const struct net_device *dev)
1928 return netdev2pinfo(dev)->tx_chan;
1930 EXPORT_SYMBOL(cxgb4_port_chan);
1932 unsigned int cxgb4_dbfifo_count(const struct net_device *dev, int lpfifo)
1934 struct adapter *adap = netdev2adap(dev);
1935 u32 v1, v2, lp_count, hp_count;
1937 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
1938 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
1939 if (is_t4(adap->params.chip)) {
1940 lp_count = LP_COUNT_G(v1);
1941 hp_count = HP_COUNT_G(v1);
1943 lp_count = LP_COUNT_T5_G(v1);
1944 hp_count = HP_COUNT_T5_G(v2);
1946 return lpfifo ? lp_count : hp_count;
1948 EXPORT_SYMBOL(cxgb4_dbfifo_count);
1951 * cxgb4_port_viid - get the VI id of a port
1952 * @dev: the net device for the port
1954 * Return the VI id of the given port.
1956 unsigned int cxgb4_port_viid(const struct net_device *dev)
1958 return netdev2pinfo(dev)->viid;
1960 EXPORT_SYMBOL(cxgb4_port_viid);
1963 * cxgb4_port_idx - get the index of a port
1964 * @dev: the net device for the port
1966 * Return the index of the given port.
1968 unsigned int cxgb4_port_idx(const struct net_device *dev)
1970 return netdev2pinfo(dev)->port_id;
1972 EXPORT_SYMBOL(cxgb4_port_idx);
1974 void cxgb4_get_tcp_stats(struct pci_dev *pdev, struct tp_tcp_stats *v4,
1975 struct tp_tcp_stats *v6)
1977 struct adapter *adap = pci_get_drvdata(pdev);
1979 spin_lock(&adap->stats_lock);
1980 t4_tp_get_tcp_stats(adap, v4, v6);
1981 spin_unlock(&adap->stats_lock);
1983 EXPORT_SYMBOL(cxgb4_get_tcp_stats);
1985 void cxgb4_iscsi_init(struct net_device *dev, unsigned int tag_mask,
1986 const unsigned int *pgsz_order)
1988 struct adapter *adap = netdev2adap(dev);
1990 t4_write_reg(adap, ULP_RX_ISCSI_TAGMASK_A, tag_mask);
1991 t4_write_reg(adap, ULP_RX_ISCSI_PSZ_A, HPZ0_V(pgsz_order[0]) |
1992 HPZ1_V(pgsz_order[1]) | HPZ2_V(pgsz_order[2]) |
1993 HPZ3_V(pgsz_order[3]));
1995 EXPORT_SYMBOL(cxgb4_iscsi_init);
1997 int cxgb4_flush_eq_cache(struct net_device *dev)
1999 struct adapter *adap = netdev2adap(dev);
2001 return t4_sge_ctxt_flush(adap, adap->mbox);
2003 EXPORT_SYMBOL(cxgb4_flush_eq_cache);
2005 static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
2007 u32 addr = t4_read_reg(adap, SGE_DBQ_CTXT_BADDR_A) + 24 * qid + 8;
2011 spin_lock(&adap->win0_lock);
2012 ret = t4_memory_rw(adap, 0, MEM_EDC0, addr,
2013 sizeof(indices), (__be32 *)&indices,
2015 spin_unlock(&adap->win0_lock);
2017 *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
2018 *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
2023 int cxgb4_sync_txq_pidx(struct net_device *dev, u16 qid, u16 pidx,
2026 struct adapter *adap = netdev2adap(dev);
2027 u16 hw_pidx, hw_cidx;
2030 ret = read_eq_indices(adap, qid, &hw_pidx, &hw_cidx);
2034 if (pidx != hw_pidx) {
2038 if (pidx >= hw_pidx)
2039 delta = pidx - hw_pidx;
2041 delta = size - hw_pidx + pidx;
2043 if (is_t4(adap->params.chip))
2044 val = PIDX_V(delta);
2046 val = PIDX_T5_V(delta);
2048 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2054 EXPORT_SYMBOL(cxgb4_sync_txq_pidx);
2056 int cxgb4_read_tpte(struct net_device *dev, u32 stag, __be32 *tpte)
2058 struct adapter *adap;
2059 u32 offset, memtype, memaddr;
2060 u32 edc0_size, edc1_size, mc0_size, mc1_size, size;
2061 u32 edc0_end, edc1_end, mc0_end, mc1_end;
2064 adap = netdev2adap(dev);
2066 offset = ((stag >> 8) * 32) + adap->vres.stag.start;
2068 /* Figure out where the offset lands in the Memory Type/Address scheme.
2069 * This code assumes that the memory is laid out starting at offset 0
2070 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
2071 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
2072 * MC0, and some have both MC0 and MC1.
2074 size = t4_read_reg(adap, MA_EDRAM0_BAR_A);
2075 edc0_size = EDRAM0_SIZE_G(size) << 20;
2076 size = t4_read_reg(adap, MA_EDRAM1_BAR_A);
2077 edc1_size = EDRAM1_SIZE_G(size) << 20;
2078 size = t4_read_reg(adap, MA_EXT_MEMORY0_BAR_A);
2079 mc0_size = EXT_MEM0_SIZE_G(size) << 20;
2081 edc0_end = edc0_size;
2082 edc1_end = edc0_end + edc1_size;
2083 mc0_end = edc1_end + mc0_size;
2085 if (offset < edc0_end) {
2088 } else if (offset < edc1_end) {
2090 memaddr = offset - edc0_end;
2092 if (offset < mc0_end) {
2094 memaddr = offset - edc1_end;
2095 } else if (is_t5(adap->params.chip)) {
2096 size = t4_read_reg(adap, MA_EXT_MEMORY1_BAR_A);
2097 mc1_size = EXT_MEM1_SIZE_G(size) << 20;
2098 mc1_end = mc0_end + mc1_size;
2099 if (offset < mc1_end) {
2101 memaddr = offset - mc0_end;
2103 /* offset beyond the end of any memory */
2107 /* T4/T6 only has a single memory channel */
2112 spin_lock(&adap->win0_lock);
2113 ret = t4_memory_rw(adap, 0, memtype, memaddr, 32, tpte, T4_MEMORY_READ);
2114 spin_unlock(&adap->win0_lock);
2118 dev_err(adap->pdev_dev, "stag %#x, offset %#x out of range\n",
2122 EXPORT_SYMBOL(cxgb4_read_tpte);
2124 u64 cxgb4_read_sge_timestamp(struct net_device *dev)
2127 struct adapter *adap;
2129 adap = netdev2adap(dev);
2130 lo = t4_read_reg(adap, SGE_TIMESTAMP_LO_A);
2131 hi = TSVAL_G(t4_read_reg(adap, SGE_TIMESTAMP_HI_A));
2133 return ((u64)hi << 32) | (u64)lo;
2135 EXPORT_SYMBOL(cxgb4_read_sge_timestamp);
2137 int cxgb4_bar2_sge_qregs(struct net_device *dev,
2139 enum cxgb4_bar2_qtype qtype,
2142 unsigned int *pbar2_qid)
2144 return t4_bar2_sge_qregs(netdev2adap(dev),
2146 (qtype == CXGB4_BAR2_QTYPE_EGRESS
2147 ? T4_BAR2_QTYPE_EGRESS
2148 : T4_BAR2_QTYPE_INGRESS),
2153 EXPORT_SYMBOL(cxgb4_bar2_sge_qregs);
2155 static struct pci_driver cxgb4_driver;
2157 static void check_neigh_update(struct neighbour *neigh)
2159 const struct device *parent;
2160 const struct net_device *netdev = neigh->dev;
2162 if (netdev->priv_flags & IFF_802_1Q_VLAN)
2163 netdev = vlan_dev_real_dev(netdev);
2164 parent = netdev->dev.parent;
2165 if (parent && parent->driver == &cxgb4_driver.driver)
2166 t4_l2t_update(dev_get_drvdata(parent), neigh);
2169 static int netevent_cb(struct notifier_block *nb, unsigned long event,
2173 case NETEVENT_NEIGH_UPDATE:
2174 check_neigh_update(data);
2176 case NETEVENT_REDIRECT:
2183 static bool netevent_registered;
2184 static struct notifier_block cxgb4_netevent_nb = {
2185 .notifier_call = netevent_cb
2188 static void drain_db_fifo(struct adapter *adap, int usecs)
2190 u32 v1, v2, lp_count, hp_count;
2193 v1 = t4_read_reg(adap, SGE_DBFIFO_STATUS_A);
2194 v2 = t4_read_reg(adap, SGE_DBFIFO_STATUS2_A);
2195 if (is_t4(adap->params.chip)) {
2196 lp_count = LP_COUNT_G(v1);
2197 hp_count = HP_COUNT_G(v1);
2199 lp_count = LP_COUNT_T5_G(v1);
2200 hp_count = HP_COUNT_T5_G(v2);
2203 if (lp_count == 0 && hp_count == 0)
2205 set_current_state(TASK_UNINTERRUPTIBLE);
2206 schedule_timeout(usecs_to_jiffies(usecs));
2210 static void disable_txq_db(struct sge_txq *q)
2212 unsigned long flags;
2214 spin_lock_irqsave(&q->db_lock, flags);
2216 spin_unlock_irqrestore(&q->db_lock, flags);
2219 static void enable_txq_db(struct adapter *adap, struct sge_txq *q)
2221 spin_lock_irq(&q->db_lock);
2222 if (q->db_pidx_inc) {
2223 /* Make sure that all writes to the TX descriptors
2224 * are committed before we tell HW about them.
2227 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2228 QID_V(q->cntxt_id) | PIDX_V(q->db_pidx_inc));
2232 spin_unlock_irq(&q->db_lock);
2235 static void disable_dbs(struct adapter *adap)
2239 for_each_ethrxq(&adap->sge, i)
2240 disable_txq_db(&adap->sge.ethtxq[i].q);
2241 for_each_iscsirxq(&adap->sge, i)
2242 disable_txq_db(&adap->sge.ofldtxq[i].q);
2243 for_each_port(adap, i)
2244 disable_txq_db(&adap->sge.ctrlq[i].q);
2247 static void enable_dbs(struct adapter *adap)
2251 for_each_ethrxq(&adap->sge, i)
2252 enable_txq_db(adap, &adap->sge.ethtxq[i].q);
2253 for_each_iscsirxq(&adap->sge, i)
2254 enable_txq_db(adap, &adap->sge.ofldtxq[i].q);
2255 for_each_port(adap, i)
2256 enable_txq_db(adap, &adap->sge.ctrlq[i].q);
2259 static void notify_rdma_uld(struct adapter *adap, enum cxgb4_control cmd)
2261 if (adap->uld_handle[CXGB4_ULD_RDMA])
2262 ulds[CXGB4_ULD_RDMA].control(adap->uld_handle[CXGB4_ULD_RDMA],
2266 static void process_db_full(struct work_struct *work)
2268 struct adapter *adap;
2270 adap = container_of(work, struct adapter, db_full_task);
2272 drain_db_fifo(adap, dbfifo_drain_delay);
2274 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2275 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2276 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2277 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F,
2278 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F);
2280 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2281 DBFIFO_LP_INT_F, DBFIFO_LP_INT_F);
2284 static void sync_txq_pidx(struct adapter *adap, struct sge_txq *q)
2286 u16 hw_pidx, hw_cidx;
2289 spin_lock_irq(&q->db_lock);
2290 ret = read_eq_indices(adap, (u16)q->cntxt_id, &hw_pidx, &hw_cidx);
2293 if (q->db_pidx != hw_pidx) {
2297 if (q->db_pidx >= hw_pidx)
2298 delta = q->db_pidx - hw_pidx;
2300 delta = q->size - hw_pidx + q->db_pidx;
2302 if (is_t4(adap->params.chip))
2303 val = PIDX_V(delta);
2305 val = PIDX_T5_V(delta);
2307 t4_write_reg(adap, MYPF_REG(SGE_PF_KDOORBELL_A),
2308 QID_V(q->cntxt_id) | val);
2313 spin_unlock_irq(&q->db_lock);
2315 CH_WARN(adap, "DB drop recovery failed.\n");
2317 static void recover_all_queues(struct adapter *adap)
2321 for_each_ethrxq(&adap->sge, i)
2322 sync_txq_pidx(adap, &adap->sge.ethtxq[i].q);
2323 for_each_iscsirxq(&adap->sge, i)
2324 sync_txq_pidx(adap, &adap->sge.ofldtxq[i].q);
2325 for_each_port(adap, i)
2326 sync_txq_pidx(adap, &adap->sge.ctrlq[i].q);
2329 static void process_db_drop(struct work_struct *work)
2331 struct adapter *adap;
2333 adap = container_of(work, struct adapter, db_drop_task);
2335 if (is_t4(adap->params.chip)) {
2336 drain_db_fifo(adap, dbfifo_drain_delay);
2337 notify_rdma_uld(adap, CXGB4_CONTROL_DB_DROP);
2338 drain_db_fifo(adap, dbfifo_drain_delay);
2339 recover_all_queues(adap);
2340 drain_db_fifo(adap, dbfifo_drain_delay);
2342 notify_rdma_uld(adap, CXGB4_CONTROL_DB_EMPTY);
2343 } else if (is_t5(adap->params.chip)) {
2344 u32 dropped_db = t4_read_reg(adap, 0x010ac);
2345 u16 qid = (dropped_db >> 15) & 0x1ffff;
2346 u16 pidx_inc = dropped_db & 0x1fff;
2348 unsigned int bar2_qid;
2351 ret = t4_bar2_sge_qregs(adap, qid, T4_BAR2_QTYPE_EGRESS,
2352 0, &bar2_qoffset, &bar2_qid);
2354 dev_err(adap->pdev_dev, "doorbell drop recovery: "
2355 "qid=%d, pidx_inc=%d\n", qid, pidx_inc);
2357 writel(PIDX_T5_V(pidx_inc) | QID_V(bar2_qid),
2358 adap->bar2 + bar2_qoffset + SGE_UDB_KDOORBELL);
2360 /* Re-enable BAR2 WC */
2361 t4_set_reg_field(adap, 0x10b0, 1<<15, 1<<15);
2364 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
2365 t4_set_reg_field(adap, SGE_DOORBELL_CONTROL_A, DROPPED_DB_F, 0);
2368 void t4_db_full(struct adapter *adap)
2370 if (is_t4(adap->params.chip)) {
2372 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2373 t4_set_reg_field(adap, SGE_INT_ENABLE3_A,
2374 DBFIFO_HP_INT_F | DBFIFO_LP_INT_F, 0);
2375 queue_work(adap->workq, &adap->db_full_task);
2379 void t4_db_dropped(struct adapter *adap)
2381 if (is_t4(adap->params.chip)) {
2383 notify_rdma_uld(adap, CXGB4_CONTROL_DB_FULL);
2385 queue_work(adap->workq, &adap->db_drop_task);
2388 static void uld_attach(struct adapter *adap, unsigned int uld)
2391 struct cxgb4_lld_info lli;
2394 lli.pdev = adap->pdev;
2396 lli.l2t = adap->l2t;
2397 lli.tids = &adap->tids;
2398 lli.ports = adap->port;
2399 lli.vr = &adap->vres;
2400 lli.mtus = adap->params.mtus;
2401 if (uld == CXGB4_ULD_RDMA) {
2402 lli.rxq_ids = adap->sge.rdma_rxq;
2403 lli.ciq_ids = adap->sge.rdma_ciq;
2404 lli.nrxq = adap->sge.rdmaqs;
2405 lli.nciq = adap->sge.rdmaciqs;
2406 } else if (uld == CXGB4_ULD_ISCSI) {
2407 lli.rxq_ids = adap->sge.iscsi_rxq;
2408 lli.nrxq = adap->sge.iscsiqsets;
2410 lli.ntxq = adap->sge.iscsiqsets;
2411 lli.nchan = adap->params.nports;
2412 lli.nports = adap->params.nports;
2413 lli.wr_cred = adap->params.ofldq_wr_cred;
2414 lli.adapter_type = adap->params.chip;
2415 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
2416 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
2417 lli.udb_density = 1 << adap->params.sge.eq_qpp;
2418 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
2419 lli.filt_mode = adap->params.tp.vlan_pri_map;
2420 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
2421 for (i = 0; i < NCHAN; i++)
2423 lli.gts_reg = adap->regs + MYPF_REG(SGE_PF_GTS_A);
2424 lli.db_reg = adap->regs + MYPF_REG(SGE_PF_KDOORBELL_A);
2425 lli.fw_vers = adap->params.fw_vers;
2426 lli.dbfifo_int_thresh = dbfifo_int_thresh;
2427 lli.sge_ingpadboundary = adap->sge.fl_align;
2428 lli.sge_egrstatuspagesize = adap->sge.stat_len;
2429 lli.sge_pktshift = adap->sge.pktshift;
2430 lli.enable_fw_ofld_conn = adap->flags & FW_OFLD_CONN;
2431 lli.max_ordird_qp = adap->params.max_ordird_qp;
2432 lli.max_ird_adapter = adap->params.max_ird_adapter;
2433 lli.ulptx_memwrite_dsgl = adap->params.ulptx_memwrite_dsgl;
2434 lli.nodeid = dev_to_node(adap->pdev_dev);
2436 handle = ulds[uld].add(&lli);
2437 if (IS_ERR(handle)) {
2438 dev_warn(adap->pdev_dev,
2439 "could not attach to the %s driver, error %ld\n",
2440 uld_str[uld], PTR_ERR(handle));
2444 adap->uld_handle[uld] = handle;
2446 if (!netevent_registered) {
2447 register_netevent_notifier(&cxgb4_netevent_nb);
2448 netevent_registered = true;
2451 if (adap->flags & FULL_INIT_DONE)
2452 ulds[uld].state_change(handle, CXGB4_STATE_UP);
2455 static void attach_ulds(struct adapter *adap)
2459 spin_lock(&adap_rcu_lock);
2460 list_add_tail_rcu(&adap->rcu_node, &adap_rcu_list);
2461 spin_unlock(&adap_rcu_lock);
2463 mutex_lock(&uld_mutex);
2464 list_add_tail(&adap->list_node, &adapter_list);
2465 for (i = 0; i < CXGB4_ULD_MAX; i++)
2467 uld_attach(adap, i);
2468 mutex_unlock(&uld_mutex);
2471 static void detach_ulds(struct adapter *adap)
2475 mutex_lock(&uld_mutex);
2476 list_del(&adap->list_node);
2477 for (i = 0; i < CXGB4_ULD_MAX; i++)
2478 if (adap->uld_handle[i]) {
2479 ulds[i].state_change(adap->uld_handle[i],
2480 CXGB4_STATE_DETACH);
2481 adap->uld_handle[i] = NULL;
2483 if (netevent_registered && list_empty(&adapter_list)) {
2484 unregister_netevent_notifier(&cxgb4_netevent_nb);
2485 netevent_registered = false;
2487 mutex_unlock(&uld_mutex);
2489 spin_lock(&adap_rcu_lock);
2490 list_del_rcu(&adap->rcu_node);
2491 spin_unlock(&adap_rcu_lock);
2494 static void notify_ulds(struct adapter *adap, enum cxgb4_state new_state)
2498 mutex_lock(&uld_mutex);
2499 for (i = 0; i < CXGB4_ULD_MAX; i++)
2500 if (adap->uld_handle[i])
2501 ulds[i].state_change(adap->uld_handle[i], new_state);
2502 mutex_unlock(&uld_mutex);
2506 * cxgb4_register_uld - register an upper-layer driver
2507 * @type: the ULD type
2508 * @p: the ULD methods
2510 * Registers an upper-layer driver with this driver and notifies the ULD
2511 * about any presently available devices that support its type. Returns
2512 * %-EBUSY if a ULD of the same type is already registered.
2514 int cxgb4_register_uld(enum cxgb4_uld type, const struct cxgb4_uld_info *p)
2517 struct adapter *adap;
2519 if (type >= CXGB4_ULD_MAX)
2521 mutex_lock(&uld_mutex);
2522 if (ulds[type].add) {
2527 list_for_each_entry(adap, &adapter_list, list_node)
2528 uld_attach(adap, type);
2529 out: mutex_unlock(&uld_mutex);
2532 EXPORT_SYMBOL(cxgb4_register_uld);
2535 * cxgb4_unregister_uld - unregister an upper-layer driver
2536 * @type: the ULD type
2538 * Unregisters an existing upper-layer driver.
2540 int cxgb4_unregister_uld(enum cxgb4_uld type)
2542 struct adapter *adap;
2544 if (type >= CXGB4_ULD_MAX)
2546 mutex_lock(&uld_mutex);
2547 list_for_each_entry(adap, &adapter_list, list_node)
2548 adap->uld_handle[type] = NULL;
2549 ulds[type].add = NULL;
2550 mutex_unlock(&uld_mutex);
2553 EXPORT_SYMBOL(cxgb4_unregister_uld);
2555 #if IS_ENABLED(CONFIG_IPV6)
2556 static int cxgb4_inet6addr_handler(struct notifier_block *this,
2557 unsigned long event, void *data)
2559 struct inet6_ifaddr *ifa = data;
2560 struct net_device *event_dev = ifa->idev->dev;
2561 const struct device *parent = NULL;
2562 #if IS_ENABLED(CONFIG_BONDING)
2563 struct adapter *adap;
2565 if (event_dev->priv_flags & IFF_802_1Q_VLAN)
2566 event_dev = vlan_dev_real_dev(event_dev);
2567 #if IS_ENABLED(CONFIG_BONDING)
2568 if (event_dev->flags & IFF_MASTER) {
2569 list_for_each_entry(adap, &adapter_list, list_node) {
2572 cxgb4_clip_get(adap->port[0],
2573 (const u32 *)ifa, 1);
2576 cxgb4_clip_release(adap->port[0],
2577 (const u32 *)ifa, 1);
2588 parent = event_dev->dev.parent;
2590 if (parent && parent->driver == &cxgb4_driver.driver) {
2593 cxgb4_clip_get(event_dev, (const u32 *)ifa, 1);
2596 cxgb4_clip_release(event_dev, (const u32 *)ifa, 1);
2605 static bool inet6addr_registered;
2606 static struct notifier_block cxgb4_inet6addr_notifier = {
2607 .notifier_call = cxgb4_inet6addr_handler
2610 static void update_clip(const struct adapter *adap)
2613 struct net_device *dev;
2618 for (i = 0; i < MAX_NPORTS; i++) {
2619 dev = adap->port[i];
2623 ret = cxgb4_update_root_dev_clip(dev);
2630 #endif /* IS_ENABLED(CONFIG_IPV6) */
2633 * cxgb_up - enable the adapter
2634 * @adap: adapter being enabled
2636 * Called when the first port is enabled, this function performs the
2637 * actions necessary to make an adapter operational, such as completing
2638 * the initialization of HW modules, and enabling interrupts.
2640 * Must be called with the rtnl lock held.
2642 static int cxgb_up(struct adapter *adap)
2646 err = setup_sge_queues(adap);
2649 err = setup_rss(adap);
2653 if (adap->flags & USING_MSIX) {
2654 name_msix_vecs(adap);
2655 err = request_irq(adap->msix_info[0].vec, t4_nondata_intr, 0,
2656 adap->msix_info[0].desc, adap);
2660 err = request_msix_queue_irqs(adap);
2662 free_irq(adap->msix_info[0].vec, adap);
2666 err = request_irq(adap->pdev->irq, t4_intr_handler(adap),
2667 (adap->flags & USING_MSI) ? 0 : IRQF_SHARED,
2668 adap->port[0]->name, adap);
2674 t4_intr_enable(adap);
2675 adap->flags |= FULL_INIT_DONE;
2676 notify_ulds(adap, CXGB4_STATE_UP);
2677 #if IS_ENABLED(CONFIG_IPV6)
2683 dev_err(adap->pdev_dev, "request_irq failed, err %d\n", err);
2685 t4_free_sge_resources(adap);
2689 static void cxgb_down(struct adapter *adapter)
2691 cancel_work_sync(&adapter->tid_release_task);
2692 cancel_work_sync(&adapter->db_full_task);
2693 cancel_work_sync(&adapter->db_drop_task);
2694 adapter->tid_release_task_busy = false;
2695 adapter->tid_release_head = NULL;
2697 t4_sge_stop(adapter);
2698 t4_free_sge_resources(adapter);
2699 adapter->flags &= ~FULL_INIT_DONE;
2703 * net_device operations
2705 static int cxgb_open(struct net_device *dev)
2708 struct port_info *pi = netdev_priv(dev);
2709 struct adapter *adapter = pi->adapter;
2711 netif_carrier_off(dev);
2713 if (!(adapter->flags & FULL_INIT_DONE)) {
2714 err = cxgb_up(adapter);
2719 err = link_start(dev);
2721 netif_tx_start_all_queues(dev);
2725 static int cxgb_close(struct net_device *dev)
2727 struct port_info *pi = netdev_priv(dev);
2728 struct adapter *adapter = pi->adapter;
2730 netif_tx_stop_all_queues(dev);
2731 netif_carrier_off(dev);
2732 return t4_enable_vi(adapter, adapter->pf, pi->viid, false, false);
2735 /* Return an error number if the indicated filter isn't writable ...
2737 static int writable_filter(struct filter_entry *f)
2747 /* Delete the filter at the specified index (if valid). The checks for all
2748 * the common problems with doing this like the filter being locked, currently
2749 * pending in another operation, etc.
2751 static int delete_filter(struct adapter *adapter, unsigned int fidx)
2753 struct filter_entry *f;
2756 if (fidx >= adapter->tids.nftids + adapter->tids.nsftids)
2759 f = &adapter->tids.ftid_tab[fidx];
2760 ret = writable_filter(f);
2764 return del_filter_wr(adapter, fidx);
2769 int cxgb4_create_server_filter(const struct net_device *dev, unsigned int stid,
2770 __be32 sip, __be16 sport, __be16 vlan,
2771 unsigned int queue, unsigned char port, unsigned char mask)
2774 struct filter_entry *f;
2775 struct adapter *adap;
2779 adap = netdev2adap(dev);
2781 /* Adjust stid to correct filter index */
2782 stid -= adap->tids.sftid_base;
2783 stid += adap->tids.nftids;
2785 /* Check to make sure the filter requested is writable ...
2787 f = &adap->tids.ftid_tab[stid];
2788 ret = writable_filter(f);
2792 /* Clear out any old resources being used by the filter before
2793 * we start constructing the new filter.
2796 clear_filter(adap, f);
2798 /* Clear out filter specifications */
2799 memset(&f->fs, 0, sizeof(struct ch_filter_specification));
2800 f->fs.val.lport = cpu_to_be16(sport);
2801 f->fs.mask.lport = ~0;
2803 if ((val[0] | val[1] | val[2] | val[3]) != 0) {
2804 for (i = 0; i < 4; i++) {
2805 f->fs.val.lip[i] = val[i];
2806 f->fs.mask.lip[i] = ~0;
2808 if (adap->params.tp.vlan_pri_map & PORT_F) {
2809 f->fs.val.iport = port;
2810 f->fs.mask.iport = mask;
2814 if (adap->params.tp.vlan_pri_map & PROTOCOL_F) {
2815 f->fs.val.proto = IPPROTO_TCP;
2816 f->fs.mask.proto = ~0;
2821 /* Mark filter as locked */
2825 ret = set_filter_wr(adap, stid);
2827 clear_filter(adap, f);
2833 EXPORT_SYMBOL(cxgb4_create_server_filter);
2835 int cxgb4_remove_server_filter(const struct net_device *dev, unsigned int stid,
2836 unsigned int queue, bool ipv6)
2839 struct filter_entry *f;
2840 struct adapter *adap;
2842 adap = netdev2adap(dev);
2844 /* Adjust stid to correct filter index */
2845 stid -= adap->tids.sftid_base;
2846 stid += adap->tids.nftids;
2848 f = &adap->tids.ftid_tab[stid];
2849 /* Unlock the filter */
2852 ret = delete_filter(adap, stid);
2858 EXPORT_SYMBOL(cxgb4_remove_server_filter);
2860 static struct rtnl_link_stats64 *cxgb_get_stats(struct net_device *dev,
2861 struct rtnl_link_stats64 *ns)
2863 struct port_stats stats;
2864 struct port_info *p = netdev_priv(dev);
2865 struct adapter *adapter = p->adapter;
2867 /* Block retrieving statistics during EEH error
2868 * recovery. Otherwise, the recovery might fail
2869 * and the PCI device will be removed permanently
2871 spin_lock(&adapter->stats_lock);
2872 if (!netif_device_present(dev)) {
2873 spin_unlock(&adapter->stats_lock);
2876 t4_get_port_stats_offset(adapter, p->tx_chan, &stats,
2878 spin_unlock(&adapter->stats_lock);
2880 ns->tx_bytes = stats.tx_octets;
2881 ns->tx_packets = stats.tx_frames;
2882 ns->rx_bytes = stats.rx_octets;
2883 ns->rx_packets = stats.rx_frames;
2884 ns->multicast = stats.rx_mcast_frames;
2886 /* detailed rx_errors */
2887 ns->rx_length_errors = stats.rx_jabber + stats.rx_too_long +
2889 ns->rx_over_errors = 0;
2890 ns->rx_crc_errors = stats.rx_fcs_err;
2891 ns->rx_frame_errors = stats.rx_symbol_err;
2892 ns->rx_fifo_errors = stats.rx_ovflow0 + stats.rx_ovflow1 +
2893 stats.rx_ovflow2 + stats.rx_ovflow3 +
2894 stats.rx_trunc0 + stats.rx_trunc1 +
2895 stats.rx_trunc2 + stats.rx_trunc3;
2896 ns->rx_missed_errors = 0;
2898 /* detailed tx_errors */
2899 ns->tx_aborted_errors = 0;
2900 ns->tx_carrier_errors = 0;
2901 ns->tx_fifo_errors = 0;
2902 ns->tx_heartbeat_errors = 0;
2903 ns->tx_window_errors = 0;
2905 ns->tx_errors = stats.tx_error_frames;
2906 ns->rx_errors = stats.rx_symbol_err + stats.rx_fcs_err +
2907 ns->rx_length_errors + stats.rx_len_err + ns->rx_fifo_errors;
2911 static int cxgb_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
2914 int ret = 0, prtad, devad;
2915 struct port_info *pi = netdev_priv(dev);
2916 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&req->ifr_data;
2920 if (pi->mdio_addr < 0)
2922 data->phy_id = pi->mdio_addr;
2926 if (mdio_phy_id_is_c45(data->phy_id)) {
2927 prtad = mdio_phy_id_prtad(data->phy_id);
2928 devad = mdio_phy_id_devad(data->phy_id);
2929 } else if (data->phy_id < 32) {
2930 prtad = data->phy_id;
2932 data->reg_num &= 0x1f;
2936 mbox = pi->adapter->pf;
2937 if (cmd == SIOCGMIIREG)
2938 ret = t4_mdio_rd(pi->adapter, mbox, prtad, devad,
2939 data->reg_num, &data->val_out);
2941 ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
2942 data->reg_num, data->val_in);
2945 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2946 sizeof(pi->tstamp_config)) ?
2949 if (copy_from_user(&pi->tstamp_config, req->ifr_data,
2950 sizeof(pi->tstamp_config)))
2953 switch (pi->tstamp_config.rx_filter) {
2954 case HWTSTAMP_FILTER_NONE:
2955 pi->rxtstamp = false;
2957 case HWTSTAMP_FILTER_ALL:
2958 pi->rxtstamp = true;
2961 pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2965 return copy_to_user(req->ifr_data, &pi->tstamp_config,
2966 sizeof(pi->tstamp_config)) ?
2974 static void cxgb_set_rxmode(struct net_device *dev)
2976 /* unfortunately we can't return errors to the stack */
2977 set_rxmode(dev, -1, false);
2980 static int cxgb_change_mtu(struct net_device *dev, int new_mtu)
2983 struct port_info *pi = netdev_priv(dev);
2985 if (new_mtu < 81 || new_mtu > MAX_MTU) /* accommodate SACK */
2987 ret = t4_set_rxmode(pi->adapter, pi->adapter->pf, pi->viid, new_mtu, -1,
2994 static int cxgb_set_mac_addr(struct net_device *dev, void *p)
2997 struct sockaddr *addr = p;
2998 struct port_info *pi = netdev_priv(dev);
3000 if (!is_valid_ether_addr(addr->sa_data))
3001 return -EADDRNOTAVAIL;
3003 ret = t4_change_mac(pi->adapter, pi->adapter->pf, pi->viid,
3004 pi->xact_addr_filt, addr->sa_data, true, true);
3008 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3009 pi->xact_addr_filt = ret;
3013 #ifdef CONFIG_NET_POLL_CONTROLLER
3014 static void cxgb_netpoll(struct net_device *dev)
3016 struct port_info *pi = netdev_priv(dev);
3017 struct adapter *adap = pi->adapter;
3019 if (adap->flags & USING_MSIX) {
3021 struct sge_eth_rxq *rx = &adap->sge.ethrxq[pi->first_qset];
3023 for (i = pi->nqsets; i; i--, rx++)
3024 t4_sge_intr_msix(0, &rx->rspq);
3026 t4_intr_handler(adap)(0, adap);
3030 static const struct net_device_ops cxgb4_netdev_ops = {
3031 .ndo_open = cxgb_open,
3032 .ndo_stop = cxgb_close,
3033 .ndo_start_xmit = t4_eth_xmit,
3034 .ndo_select_queue = cxgb_select_queue,
3035 .ndo_get_stats64 = cxgb_get_stats,
3036 .ndo_set_rx_mode = cxgb_set_rxmode,
3037 .ndo_set_mac_address = cxgb_set_mac_addr,
3038 .ndo_set_features = cxgb_set_features,
3039 .ndo_validate_addr = eth_validate_addr,
3040 .ndo_do_ioctl = cxgb_ioctl,
3041 .ndo_change_mtu = cxgb_change_mtu,
3042 #ifdef CONFIG_NET_POLL_CONTROLLER
3043 .ndo_poll_controller = cxgb_netpoll,
3045 #ifdef CONFIG_CHELSIO_T4_FCOE
3046 .ndo_fcoe_enable = cxgb_fcoe_enable,
3047 .ndo_fcoe_disable = cxgb_fcoe_disable,
3048 #endif /* CONFIG_CHELSIO_T4_FCOE */
3049 #ifdef CONFIG_NET_RX_BUSY_POLL
3050 .ndo_busy_poll = cxgb_busy_poll,
3055 void t4_fatal_err(struct adapter *adap)
3057 t4_set_reg_field(adap, SGE_CONTROL_A, GLOBALENABLE_F, 0);
3058 t4_intr_disable(adap);
3059 dev_alert(adap->pdev_dev, "encountered fatal error, adapter stopped\n");
3062 static void setup_memwin(struct adapter *adap)
3064 u32 nic_win_base = t4_get_util_window(adap);
3066 t4_setup_memwin(adap, nic_win_base, MEMWIN_NIC);
3069 static void setup_memwin_rdma(struct adapter *adap)
3071 if (adap->vres.ocq.size) {
3075 start = t4_read_pcie_cfg4(adap, PCI_BASE_ADDRESS_2);
3076 start &= PCI_BASE_ADDRESS_MEM_MASK;
3077 start += OCQ_WIN_OFFSET(adap->pdev, &adap->vres);
3078 sz_kb = roundup_pow_of_two(adap->vres.ocq.size) >> 10;
3080 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, 3),
3081 start | BIR_V(1) | WINDOW_V(ilog2(sz_kb)));
3083 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3),
3084 adap->vres.ocq.start);
3086 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, 3));
3090 static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
3095 /* get device capabilities */
3096 memset(c, 0, sizeof(*c));
3097 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3098 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3099 c->cfvalid_to_len16 = htonl(FW_LEN16(*c));
3100 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), c);
3104 c->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3105 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
3106 ret = t4_wr_mbox(adap, adap->mbox, c, sizeof(*c), NULL);
3110 ret = t4_config_glbl_rss(adap, adap->pf,
3111 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL,
3112 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F |
3113 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F);
3117 ret = t4_cfg_pfvf(adap, adap->mbox, adap->pf, 0, adap->sge.egr_sz, 64,
3118 MAX_INGQ, 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF,
3125 /* tweak some settings */
3126 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
3127 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(PAGE_SHIFT - 12));
3128 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
3129 v = t4_read_reg(adap, TP_PIO_DATA_A);
3130 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
3132 /* first 4 Tx modulation queues point to consecutive Tx channels */
3133 adap->params.tp.tx_modq_map = 0xE4;
3134 t4_write_reg(adap, TP_TX_MOD_QUEUE_REQ_MAP_A,
3135 TX_MOD_QUEUE_REQ_MAP_V(adap->params.tp.tx_modq_map));
3137 /* associate each Tx modulation queue with consecutive Tx channels */
3139 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3140 &v, 1, TP_TX_SCHED_HDR_A);
3141 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3142 &v, 1, TP_TX_SCHED_FIFO_A);
3143 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
3144 &v, 1, TP_TX_SCHED_PCMD_A);
3146 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
3147 if (is_offload(adap)) {
3148 t4_write_reg(adap, TP_TX_MOD_QUEUE_WEIGHT0_A,
3149 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3150 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3151 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3152 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3153 t4_write_reg(adap, TP_TX_MOD_CHANNEL_WEIGHT_A,
3154 TX_MODQ_WEIGHT0_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3155 TX_MODQ_WEIGHT1_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3156 TX_MODQ_WEIGHT2_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT) |
3157 TX_MODQ_WEIGHT3_V(T4_TX_MODQ_10G_WEIGHT_DEFAULT));
3160 /* get basic stuff going */
3161 return t4_early_init(adap, adap->pf);
3165 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
3167 #define MAX_ATIDS 8192U
3170 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3172 * If the firmware we're dealing with has Configuration File support, then
3173 * we use that to perform all configuration
3177 * Tweak configuration based on module parameters, etc. Most of these have
3178 * defaults assigned to them by Firmware Configuration Files (if we're using
3179 * them) but need to be explicitly set if we're using hard-coded
3180 * initialization. But even in the case of using Firmware Configuration
3181 * Files, we'd like to expose the ability to change these via module
3182 * parameters so these are essentially common tweaks/settings for
3183 * Configuration Files and hard-coded initialization ...
3185 static int adap_init0_tweaks(struct adapter *adapter)
3188 * Fix up various Host-Dependent Parameters like Page Size, Cache
3189 * Line Size, etc. The firmware default is for a 4KB Page Size and
3190 * 64B Cache Line Size ...
3192 t4_fixup_host_params(adapter, PAGE_SIZE, L1_CACHE_BYTES);
3195 * Process module parameters which affect early initialization.
3197 if (rx_dma_offset != 2 && rx_dma_offset != 0) {
3198 dev_err(&adapter->pdev->dev,
3199 "Ignoring illegal rx_dma_offset=%d, using 2\n",
3203 t4_set_reg_field(adapter, SGE_CONTROL_A,
3204 PKTSHIFT_V(PKTSHIFT_M),
3205 PKTSHIFT_V(rx_dma_offset));
3208 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
3209 * adds the pseudo header itself.
3211 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
3212 CSUM_HAS_PSEUDO_HDR_F, 0);
3217 /* 10Gb/s-BT PHY Support. chip-external 10Gb/s-BT PHYs are complex chips
3218 * unto themselves and they contain their own firmware to perform their
3221 static int phy_aq1202_version(const u8 *phy_fw_data,
3226 /* At offset 0x8 you're looking for the primary image's
3227 * starting offset which is 3 Bytes wide
3229 * At offset 0xa of the primary image, you look for the offset
3230 * of the DRAM segment which is 3 Bytes wide.
3232 * The FW version is at offset 0x27e of the DRAM and is 2 Bytes
3235 #define be16(__p) (((__p)[0] << 8) | (__p)[1])
3236 #define le16(__p) ((__p)[0] | ((__p)[1] << 8))
3237 #define le24(__p) (le16(__p) | ((__p)[2] << 16))
3239 offset = le24(phy_fw_data + 0x8) << 12;
3240 offset = le24(phy_fw_data + offset + 0xa);
3241 return be16(phy_fw_data + offset + 0x27e);
3248 static struct info_10gbt_phy_fw {
3249 unsigned int phy_fw_id; /* PCI Device ID */
3250 char *phy_fw_file; /* /lib/firmware/ PHY Firmware file */
3251 int (*phy_fw_version)(const u8 *phy_fw_data, size_t phy_fw_size);
3252 int phy_flash; /* Has FLASH for PHY Firmware */
3253 } phy_info_array[] = {
3255 PHY_AQ1202_DEVICEID,
3256 PHY_AQ1202_FIRMWARE,
3261 PHY_BCM84834_DEVICEID,
3262 PHY_BCM84834_FIRMWARE,
3269 static struct info_10gbt_phy_fw *find_phy_info(int devid)
3273 for (i = 0; i < ARRAY_SIZE(phy_info_array); i++) {
3274 if (phy_info_array[i].phy_fw_id == devid)
3275 return &phy_info_array[i];
3280 /* Handle updating of chip-external 10Gb/s-BT PHY firmware. This needs to
3281 * happen after the FW_RESET_CMD but before the FW_INITIALIZE_CMD. On error
3282 * we return a negative error number. If we transfer new firmware we return 1
3283 * (from t4_load_phy_fw()). If we don't do anything we return 0.
3285 static int adap_init0_phy(struct adapter *adap)
3287 const struct firmware *phyf;
3289 struct info_10gbt_phy_fw *phy_info;
3291 /* Use the device ID to determine which PHY file to flash.
3293 phy_info = find_phy_info(adap->pdev->device);
3295 dev_warn(adap->pdev_dev,
3296 "No PHY Firmware file found for this PHY\n");
3300 /* If we have a T4 PHY firmware file under /lib/firmware/cxgb4/, then
3301 * use that. The adapter firmware provides us with a memory buffer
3302 * where we can load a PHY firmware file from the host if we want to
3303 * override the PHY firmware File in flash.
3305 ret = request_firmware_direct(&phyf, phy_info->phy_fw_file,
3308 /* For adapters without FLASH attached to PHY for their
3309 * firmware, it's obviously a fatal error if we can't get the
3310 * firmware to the adapter. For adapters with PHY firmware
3311 * FLASH storage, it's worth a warning if we can't find the
3312 * PHY Firmware but we'll neuter the error ...
3314 dev_err(adap->pdev_dev, "unable to find PHY Firmware image "
3315 "/lib/firmware/%s, error %d\n",
3316 phy_info->phy_fw_file, -ret);
3317 if (phy_info->phy_flash) {
3318 int cur_phy_fw_ver = 0;
3320 t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3321 dev_warn(adap->pdev_dev, "continuing with, on-adapter "
3322 "FLASH copy, version %#x\n", cur_phy_fw_ver);
3329 /* Load PHY Firmware onto adapter.
3331 ret = t4_load_phy_fw(adap, MEMWIN_NIC, &adap->win0_lock,
3332 phy_info->phy_fw_version,
3333 (u8 *)phyf->data, phyf->size);
3335 dev_err(adap->pdev_dev, "PHY Firmware transfer error %d\n",
3338 int new_phy_fw_ver = 0;
3340 if (phy_info->phy_fw_version)
3341 new_phy_fw_ver = phy_info->phy_fw_version(phyf->data,
3343 dev_info(adap->pdev_dev, "Successfully transferred PHY "
3344 "Firmware /lib/firmware/%s, version %#x\n",
3345 phy_info->phy_fw_file, new_phy_fw_ver);
3348 release_firmware(phyf);
3354 * Attempt to initialize the adapter via a Firmware Configuration File.
3356 static int adap_init0_config(struct adapter *adapter, int reset)
3358 struct fw_caps_config_cmd caps_cmd;
3359 const struct firmware *cf;
3360 unsigned long mtype = 0, maddr = 0;
3361 u32 finiver, finicsum, cfcsum;
3363 int config_issued = 0;
3364 char *fw_config_file, fw_config_file_path[256];
3365 char *config_name = NULL;
3368 * Reset device if necessary.
3371 ret = t4_fw_reset(adapter, adapter->mbox,
3372 PIORSTMODE_F | PIORST_F);
3377 /* If this is a 10Gb/s-BT adapter make sure the chip-external
3378 * 10Gb/s-BT PHYs have up-to-date firmware. Note that this step needs
3379 * to be performed after any global adapter RESET above since some
3380 * PHYs only have local RAM copies of the PHY firmware.
3382 if (is_10gbt_device(adapter->pdev->device)) {
3383 ret = adap_init0_phy(adapter);
3388 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
3389 * then use that. Otherwise, use the configuration file stored
3390 * in the adapter flash ...
3392 switch (CHELSIO_CHIP_VERSION(adapter->params.chip)) {
3394 fw_config_file = FW4_CFNAME;
3397 fw_config_file = FW5_CFNAME;
3400 fw_config_file = FW6_CFNAME;
3403 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
3404 adapter->pdev->device);
3409 ret = request_firmware(&cf, fw_config_file, adapter->pdev_dev);
3411 config_name = "On FLASH";
3412 mtype = FW_MEMTYPE_CF_FLASH;
3413 maddr = t4_flash_cfg_addr(adapter);
3415 u32 params[7], val[7];
3417 sprintf(fw_config_file_path,
3418 "/lib/firmware/%s", fw_config_file);
3419 config_name = fw_config_file_path;
3421 if (cf->size >= FLASH_CFG_MAX_SIZE)
3424 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3425 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3426 ret = t4_query_params(adapter, adapter->mbox,
3427 adapter->pf, 0, 1, params, val);
3430 * For t4_memory_rw() below addresses and
3431 * sizes have to be in terms of multiples of 4
3432 * bytes. So, if the Configuration File isn't
3433 * a multiple of 4 bytes in length we'll have
3434 * to write that out separately since we can't
3435 * guarantee that the bytes following the
3436 * residual byte in the buffer returned by
3437 * request_firmware() are zeroed out ...
3439 size_t resid = cf->size & 0x3;
3440 size_t size = cf->size & ~0x3;
3441 __be32 *data = (__be32 *)cf->data;
3443 mtype = FW_PARAMS_PARAM_Y_G(val[0]);
3444 maddr = FW_PARAMS_PARAM_Z_G(val[0]) << 16;
3446 spin_lock(&adapter->win0_lock);
3447 ret = t4_memory_rw(adapter, 0, mtype, maddr,
3448 size, data, T4_MEMORY_WRITE);
3449 if (ret == 0 && resid != 0) {
3456 last.word = data[size >> 2];
3457 for (i = resid; i < 4; i++)
3459 ret = t4_memory_rw(adapter, 0, mtype,
3464 spin_unlock(&adapter->win0_lock);
3468 release_firmware(cf);
3474 * Issue a Capability Configuration command to the firmware to get it
3475 * to parse the Configuration File. We don't use t4_fw_config_file()
3476 * because we want the ability to modify various features after we've
3477 * processed the configuration file ...
3479 memset(&caps_cmd, 0, sizeof(caps_cmd));
3480 caps_cmd.op_to_write =
3481 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3484 caps_cmd.cfvalid_to_len16 =
3485 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
3486 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
3487 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
3488 FW_LEN16(caps_cmd));
3489 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3492 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
3493 * Configuration File in FLASH), our last gasp effort is to use the
3494 * Firmware Configuration File which is embedded in the firmware. A
3495 * very few early versions of the firmware didn't have one embedded
3496 * but we can ignore those.
3498 if (ret == -ENOENT) {
3499 memset(&caps_cmd, 0, sizeof(caps_cmd));
3500 caps_cmd.op_to_write =
3501 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3504 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3505 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd,
3506 sizeof(caps_cmd), &caps_cmd);
3507 config_name = "Firmware Default";
3514 finiver = ntohl(caps_cmd.finiver);
3515 finicsum = ntohl(caps_cmd.finicsum);
3516 cfcsum = ntohl(caps_cmd.cfcsum);
3517 if (finicsum != cfcsum)
3518 dev_warn(adapter->pdev_dev, "Configuration File checksum "\
3519 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
3523 * And now tell the firmware to use the configuration we just loaded.
3525 caps_cmd.op_to_write =
3526 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3529 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3530 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd),
3536 * Tweak configuration based on system architecture, module
3539 ret = adap_init0_tweaks(adapter);
3544 * And finally tell the firmware to initialize itself using the
3545 * parameters from the Configuration File.
3547 ret = t4_fw_initialize(adapter, adapter->mbox);
3551 /* Emit Firmware Configuration File information and return
3554 dev_info(adapter->pdev_dev, "Successfully configured using Firmware "\
3555 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
3556 config_name, finiver, cfcsum);
3560 * Something bad happened. Return the error ... (If the "error"
3561 * is that there's no Configuration File on the adapter we don't
3562 * want to issue a warning since this is fairly common.)
3565 if (config_issued && ret != -ENOENT)
3566 dev_warn(adapter->pdev_dev, "\"%s\" configuration file error %d\n",
3571 static struct fw_info fw_info_array[] = {
3574 .fs_name = FW4_CFNAME,
3575 .fw_mod_name = FW4_FNAME,
3577 .chip = FW_HDR_CHIP_T4,
3578 .fw_ver = __cpu_to_be32(FW_VERSION(T4)),
3579 .intfver_nic = FW_INTFVER(T4, NIC),
3580 .intfver_vnic = FW_INTFVER(T4, VNIC),
3581 .intfver_ri = FW_INTFVER(T4, RI),
3582 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
3583 .intfver_fcoe = FW_INTFVER(T4, FCOE),
3587 .fs_name = FW5_CFNAME,
3588 .fw_mod_name = FW5_FNAME,
3590 .chip = FW_HDR_CHIP_T5,
3591 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
3592 .intfver_nic = FW_INTFVER(T5, NIC),
3593 .intfver_vnic = FW_INTFVER(T5, VNIC),
3594 .intfver_ri = FW_INTFVER(T5, RI),
3595 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
3596 .intfver_fcoe = FW_INTFVER(T5, FCOE),
3600 .fs_name = FW6_CFNAME,
3601 .fw_mod_name = FW6_FNAME,
3603 .chip = FW_HDR_CHIP_T6,
3604 .fw_ver = __cpu_to_be32(FW_VERSION(T6)),
3605 .intfver_nic = FW_INTFVER(T6, NIC),
3606 .intfver_vnic = FW_INTFVER(T6, VNIC),
3607 .intfver_ofld = FW_INTFVER(T6, OFLD),
3608 .intfver_ri = FW_INTFVER(T6, RI),
3609 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
3610 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
3611 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
3612 .intfver_fcoe = FW_INTFVER(T6, FCOE),
3618 static struct fw_info *find_fw_info(int chip)
3622 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
3623 if (fw_info_array[i].chip == chip)
3624 return &fw_info_array[i];
3630 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
3632 static int adap_init0(struct adapter *adap)
3636 enum dev_state state;
3637 u32 params[7], val[7];
3638 struct fw_caps_config_cmd caps_cmd;
3641 /* Grab Firmware Device Log parameters as early as possible so we have
3642 * access to it for debugging, etc.
3644 ret = t4_init_devlog_params(adap);
3648 /* Contact FW, advertising Master capability */
3649 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state);
3651 dev_err(adap->pdev_dev, "could not connect to FW, error %d\n",
3655 if (ret == adap->mbox)
3656 adap->flags |= MASTER_PF;
3659 * If we're the Master PF Driver and the device is uninitialized,
3660 * then let's consider upgrading the firmware ... (We always want
3661 * to check the firmware version number in order to A. get it for
3662 * later reporting and B. to warn if the currently loaded firmware
3663 * is excessively mismatched relative to the driver.)
3665 t4_get_fw_version(adap, &adap->params.fw_vers);
3666 t4_get_tp_version(adap, &adap->params.tp_vers);
3667 ret = t4_check_fw_version(adap);
3668 /* If firmware is too old (not supported by driver) force an update. */
3670 state = DEV_STATE_UNINIT;
3671 if ((adap->flags & MASTER_PF) && state != DEV_STATE_INIT) {
3672 struct fw_info *fw_info;
3673 struct fw_hdr *card_fw;
3674 const struct firmware *fw;
3675 const u8 *fw_data = NULL;
3676 unsigned int fw_size = 0;
3678 /* This is the firmware whose headers the driver was compiled
3681 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(adap->params.chip));
3682 if (fw_info == NULL) {
3683 dev_err(adap->pdev_dev,
3684 "unable to get firmware info for chip %d.\n",
3685 CHELSIO_CHIP_VERSION(adap->params.chip));
3689 /* allocate memory to read the header of the firmware on the
3692 card_fw = t4_alloc_mem(sizeof(*card_fw));
3694 /* Get FW from from /lib/firmware/ */
3695 ret = request_firmware(&fw, fw_info->fw_mod_name,
3698 dev_err(adap->pdev_dev,
3699 "unable to load firmware image %s, error %d\n",
3700 fw_info->fw_mod_name, ret);
3706 /* upgrade FW logic */
3707 ret = t4_prep_fw(adap, fw_info, fw_data, fw_size, card_fw,
3711 release_firmware(fw);
3712 t4_free_mem(card_fw);
3719 * Grab VPD parameters. This should be done after we establish a
3720 * connection to the firmware since some of the VPD parameters
3721 * (notably the Core Clock frequency) are retrieved via requests to
3722 * the firmware. On the other hand, we need these fairly early on
3723 * so we do this right after getting ahold of the firmware.
3725 ret = t4_get_vpd_params(adap, &adap->params.vpd);
3730 * Find out what ports are available to us. Note that we need to do
3731 * this before calling adap_init0_no_config() since it needs nports
3735 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3736 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PORTVEC);
3737 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec);
3741 adap->params.nports = hweight32(port_vec);
3742 adap->params.portvec = port_vec;
3744 /* If the firmware is initialized already, emit a simply note to that
3745 * effect. Otherwise, it's time to try initializing the adapter.
3747 if (state == DEV_STATE_INIT) {
3748 dev_info(adap->pdev_dev, "Coming up as %s: "\
3749 "Adapter already initialized\n",
3750 adap->flags & MASTER_PF ? "MASTER" : "SLAVE");
3752 dev_info(adap->pdev_dev, "Coming up as MASTER: "\
3753 "Initializing adapter\n");
3755 /* Find out whether we're dealing with a version of the
3756 * firmware which has configuration file support.
3758 params[0] = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3759 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CF));
3760 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3763 /* If the firmware doesn't support Configuration Files,
3767 dev_err(adap->pdev_dev, "firmware doesn't support "
3768 "Firmware Configuration Files\n");
3772 /* The firmware provides us with a memory buffer where we can
3773 * load a Configuration File from the host if we want to
3774 * override the Configuration File in flash.
3776 ret = adap_init0_config(adap, reset);
3777 if (ret == -ENOENT) {
3778 dev_err(adap->pdev_dev, "no Configuration File "
3779 "present on adapter.\n");
3783 dev_err(adap->pdev_dev, "could not initialize "
3784 "adapter, error %d\n", -ret);
3789 /* Give the SGE code a chance to pull in anything that it needs ...
3790 * Note that this must be called after we retrieve our VPD parameters
3791 * in order to know how to convert core ticks to seconds, etc.
3793 ret = t4_sge_init(adap);
3797 if (is_bypass_device(adap->pdev->device))
3798 adap->params.bypass = 1;
3801 * Grab some of our basic fundamental operating parameters.
3803 #define FW_PARAM_DEV(param) \
3804 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) | \
3805 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_##param))
3807 #define FW_PARAM_PFVF(param) \
3808 FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
3809 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param)| \
3810 FW_PARAMS_PARAM_Y_V(0) | \
3811 FW_PARAMS_PARAM_Z_V(0)
3813 params[0] = FW_PARAM_PFVF(EQ_START);
3814 params[1] = FW_PARAM_PFVF(L2T_START);
3815 params[2] = FW_PARAM_PFVF(L2T_END);
3816 params[3] = FW_PARAM_PFVF(FILTER_START);
3817 params[4] = FW_PARAM_PFVF(FILTER_END);
3818 params[5] = FW_PARAM_PFVF(IQFLINT_START);
3819 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params, val);
3822 adap->sge.egr_start = val[0];
3823 adap->l2t_start = val[1];
3824 adap->l2t_end = val[2];
3825 adap->tids.ftid_base = val[3];
3826 adap->tids.nftids = val[4] - val[3] + 1;
3827 adap->sge.ingr_start = val[5];
3829 /* qids (ingress/egress) returned from firmware can be anywhere
3830 * in the range from EQ(IQFLINT)_START to EQ(IQFLINT)_END.
3831 * Hence driver needs to allocate memory for this range to
3832 * store the queue info. Get the highest IQFLINT/EQ index returned
3833 * in FW_EQ_*_CMD.alloc command.
3835 params[0] = FW_PARAM_PFVF(EQ_END);
3836 params[1] = FW_PARAM_PFVF(IQFLINT_END);
3837 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3840 adap->sge.egr_sz = val[0] - adap->sge.egr_start + 1;
3841 adap->sge.ingr_sz = val[1] - adap->sge.ingr_start + 1;
3843 adap->sge.egr_map = kcalloc(adap->sge.egr_sz,
3844 sizeof(*adap->sge.egr_map), GFP_KERNEL);
3845 if (!adap->sge.egr_map) {
3850 adap->sge.ingr_map = kcalloc(adap->sge.ingr_sz,
3851 sizeof(*adap->sge.ingr_map), GFP_KERNEL);
3852 if (!adap->sge.ingr_map) {
3857 /* Allocate the memory for the vaious egress queue bitmaps
3858 * ie starving_fl, txq_maperr and blocked_fl.
3860 adap->sge.starving_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3861 sizeof(long), GFP_KERNEL);
3862 if (!adap->sge.starving_fl) {
3867 adap->sge.txq_maperr = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3868 sizeof(long), GFP_KERNEL);
3869 if (!adap->sge.txq_maperr) {
3874 #ifdef CONFIG_DEBUG_FS
3875 adap->sge.blocked_fl = kcalloc(BITS_TO_LONGS(adap->sge.egr_sz),
3876 sizeof(long), GFP_KERNEL);
3877 if (!adap->sge.blocked_fl) {
3883 params[0] = FW_PARAM_PFVF(CLIP_START);
3884 params[1] = FW_PARAM_PFVF(CLIP_END);
3885 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3888 adap->clipt_start = val[0];
3889 adap->clipt_end = val[1];
3891 /* query params related to active filter region */
3892 params[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START);
3893 params[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END);
3894 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params, val);
3895 /* If Active filter size is set we enable establishing
3896 * offload connection through firmware work request
3898 if ((val[0] != val[1]) && (ret >= 0)) {
3899 adap->flags |= FW_OFLD_CONN;
3900 adap->tids.aftid_base = val[0];
3901 adap->tids.aftid_end = val[1];
3904 /* If we're running on newer firmware, let it know that we're
3905 * prepared to deal with encapsulated CPL messages. Older
3906 * firmware won't understand this and we'll just get
3907 * unencapsulated messages ...
3909 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3911 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val);
3914 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
3915 * capability. Earlier versions of the firmware didn't have the
3916 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
3917 * permission to use ULPTX MEMWRITE DSGL.
3919 if (is_t4(adap->params.chip)) {
3920 adap->params.ulptx_memwrite_dsgl = false;
3922 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL);
3923 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
3925 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0);
3929 * Get device capabilities so we can determine what resources we need
3932 memset(&caps_cmd, 0, sizeof(caps_cmd));
3933 caps_cmd.op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
3934 FW_CMD_REQUEST_F | FW_CMD_READ_F);
3935 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
3936 ret = t4_wr_mbox(adap, adap->mbox, &caps_cmd, sizeof(caps_cmd),
3941 if (caps_cmd.ofldcaps) {
3942 /* query offload-related parameters */
3943 params[0] = FW_PARAM_DEV(NTID);
3944 params[1] = FW_PARAM_PFVF(SERVER_START);
3945 params[2] = FW_PARAM_PFVF(SERVER_END);
3946 params[3] = FW_PARAM_PFVF(TDDP_START);
3947 params[4] = FW_PARAM_PFVF(TDDP_END);
3948 params[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3949 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3953 adap->tids.ntids = val[0];
3954 adap->tids.natids = min(adap->tids.ntids / 2, MAX_ATIDS);
3955 adap->tids.stid_base = val[1];
3956 adap->tids.nstids = val[2] - val[1] + 1;
3958 * Setup server filter region. Divide the available filter
3959 * region into two parts. Regular filters get 1/3rd and server
3960 * filters get 2/3rd part. This is only enabled if workarond
3962 * 1. For regular filters.
3963 * 2. Server filter: This are special filters which are used
3964 * to redirect SYN packets to offload queue.
3966 if (adap->flags & FW_OFLD_CONN && !is_bypass(adap)) {
3967 adap->tids.sftid_base = adap->tids.ftid_base +
3968 DIV_ROUND_UP(adap->tids.nftids, 3);
3969 adap->tids.nsftids = adap->tids.nftids -
3970 DIV_ROUND_UP(adap->tids.nftids, 3);
3971 adap->tids.nftids = adap->tids.sftid_base -
3972 adap->tids.ftid_base;
3974 adap->vres.ddp.start = val[3];
3975 adap->vres.ddp.size = val[4] - val[3] + 1;
3976 adap->params.ofldq_wr_cred = val[5];
3978 adap->params.offload = 1;
3980 if (caps_cmd.rdmacaps) {
3981 params[0] = FW_PARAM_PFVF(STAG_START);
3982 params[1] = FW_PARAM_PFVF(STAG_END);
3983 params[2] = FW_PARAM_PFVF(RQ_START);
3984 params[3] = FW_PARAM_PFVF(RQ_END);
3985 params[4] = FW_PARAM_PFVF(PBL_START);
3986 params[5] = FW_PARAM_PFVF(PBL_END);
3987 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6,
3991 adap->vres.stag.start = val[0];
3992 adap->vres.stag.size = val[1] - val[0] + 1;
3993 adap->vres.rq.start = val[2];
3994 adap->vres.rq.size = val[3] - val[2] + 1;
3995 adap->vres.pbl.start = val[4];
3996 adap->vres.pbl.size = val[5] - val[4] + 1;
3998 params[0] = FW_PARAM_PFVF(SQRQ_START);
3999 params[1] = FW_PARAM_PFVF(SQRQ_END);
4000 params[2] = FW_PARAM_PFVF(CQ_START);
4001 params[3] = FW_PARAM_PFVF(CQ_END);
4002 params[4] = FW_PARAM_PFVF(OCQ_START);
4003 params[5] = FW_PARAM_PFVF(OCQ_END);
4004 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 6, params,
4008 adap->vres.qp.start = val[0];
4009 adap->vres.qp.size = val[1] - val[0] + 1;
4010 adap->vres.cq.start = val[2];
4011 adap->vres.cq.size = val[3] - val[2] + 1;
4012 adap->vres.ocq.start = val[4];
4013 adap->vres.ocq.size = val[5] - val[4] + 1;
4015 params[0] = FW_PARAM_DEV(MAXORDIRD_QP);
4016 params[1] = FW_PARAM_DEV(MAXIRD_ADAPTER);
4017 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2, params,
4020 adap->params.max_ordird_qp = 8;
4021 adap->params.max_ird_adapter = 32 * adap->tids.ntids;
4024 adap->params.max_ordird_qp = val[0];
4025 adap->params.max_ird_adapter = val[1];
4027 dev_info(adap->pdev_dev,
4028 "max_ordird_qp %d max_ird_adapter %d\n",
4029 adap->params.max_ordird_qp,
4030 adap->params.max_ird_adapter);
4032 if (caps_cmd.iscsicaps) {
4033 params[0] = FW_PARAM_PFVF(ISCSI_START);
4034 params[1] = FW_PARAM_PFVF(ISCSI_END);
4035 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 2,
4039 adap->vres.iscsi.start = val[0];
4040 adap->vres.iscsi.size = val[1] - val[0] + 1;
4042 #undef FW_PARAM_PFVF
4045 /* The MTU/MSS Table is initialized by now, so load their values. If
4046 * we're initializing the adapter, then we'll make any modifications
4047 * we want to the MTU/MSS Table and also initialize the congestion
4050 t4_read_mtu_tbl(adap, adap->params.mtus, NULL);
4051 if (state != DEV_STATE_INIT) {
4054 /* The default MTU Table contains values 1492 and 1500.
4055 * However, for TCP, it's better to have two values which are
4056 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
4057 * This allows us to have a TCP Data Payload which is a
4058 * multiple of 8 regardless of what combination of TCP Options
4059 * are in use (always a multiple of 4 bytes) which is
4060 * important for performance reasons. For instance, if no
4061 * options are in use, then we have a 20-byte IP header and a
4062 * 20-byte TCP header. In this case, a 1500-byte MSS would
4063 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
4064 * which is not a multiple of 8. So using an MSS of 1488 in
4065 * this case results in a TCP Data Payload of 1448 bytes which
4066 * is a multiple of 8. On the other hand, if 12-byte TCP Time
4067 * Stamps have been negotiated, then an MTU of 1500 bytes
4068 * results in a TCP Data Payload of 1448 bytes which, as
4069 * above, is a multiple of 8 bytes ...
4071 for (i = 0; i < NMTUS; i++)
4072 if (adap->params.mtus[i] == 1492) {
4073 adap->params.mtus[i] = 1488;
4077 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4078 adap->params.b_wnd);
4080 t4_init_sge_params(adap);
4081 adap->flags |= FW_OK;
4082 t4_init_tp_params(adap);
4086 * Something bad happened. If a command timed out or failed with EIO
4087 * FW does not operate within its spec or something catastrophic
4088 * happened to HW/FW, stop issuing commands.
4091 kfree(adap->sge.egr_map);
4092 kfree(adap->sge.ingr_map);
4093 kfree(adap->sge.starving_fl);
4094 kfree(adap->sge.txq_maperr);
4095 #ifdef CONFIG_DEBUG_FS
4096 kfree(adap->sge.blocked_fl);
4098 if (ret != -ETIMEDOUT && ret != -EIO)
4099 t4_fw_bye(adap, adap->mbox);
4105 static pci_ers_result_t eeh_err_detected(struct pci_dev *pdev,
4106 pci_channel_state_t state)
4109 struct adapter *adap = pci_get_drvdata(pdev);
4115 adap->flags &= ~FW_OK;
4116 notify_ulds(adap, CXGB4_STATE_START_RECOVERY);
4117 spin_lock(&adap->stats_lock);
4118 for_each_port(adap, i) {
4119 struct net_device *dev = adap->port[i];
4121 netif_device_detach(dev);
4122 netif_carrier_off(dev);
4124 spin_unlock(&adap->stats_lock);
4125 disable_interrupts(adap);
4126 if (adap->flags & FULL_INIT_DONE)
4129 if ((adap->flags & DEV_ENABLED)) {
4130 pci_disable_device(pdev);
4131 adap->flags &= ~DEV_ENABLED;
4133 out: return state == pci_channel_io_perm_failure ?
4134 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
4137 static pci_ers_result_t eeh_slot_reset(struct pci_dev *pdev)
4140 struct fw_caps_config_cmd c;
4141 struct adapter *adap = pci_get_drvdata(pdev);
4144 pci_restore_state(pdev);
4145 pci_save_state(pdev);
4146 return PCI_ERS_RESULT_RECOVERED;
4149 if (!(adap->flags & DEV_ENABLED)) {
4150 if (pci_enable_device(pdev)) {
4151 dev_err(&pdev->dev, "Cannot reenable PCI "
4152 "device after reset\n");
4153 return PCI_ERS_RESULT_DISCONNECT;
4155 adap->flags |= DEV_ENABLED;
4158 pci_set_master(pdev);
4159 pci_restore_state(pdev);
4160 pci_save_state(pdev);
4161 pci_cleanup_aer_uncorrect_error_status(pdev);
4163 if (t4_wait_dev_ready(adap->regs) < 0)
4164 return PCI_ERS_RESULT_DISCONNECT;
4165 if (t4_fw_hello(adap, adap->mbox, adap->pf, MASTER_MUST, NULL) < 0)
4166 return PCI_ERS_RESULT_DISCONNECT;
4167 adap->flags |= FW_OK;
4168 if (adap_init1(adap, &c))
4169 return PCI_ERS_RESULT_DISCONNECT;
4171 for_each_port(adap, i) {
4172 struct port_info *p = adap2pinfo(adap, i);
4174 ret = t4_alloc_vi(adap, adap->mbox, p->tx_chan, adap->pf, 0, 1,
4177 return PCI_ERS_RESULT_DISCONNECT;
4179 p->xact_addr_filt = -1;
4182 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd,
4183 adap->params.b_wnd);
4186 return PCI_ERS_RESULT_DISCONNECT;
4187 return PCI_ERS_RESULT_RECOVERED;
4190 static void eeh_resume(struct pci_dev *pdev)
4193 struct adapter *adap = pci_get_drvdata(pdev);
4199 for_each_port(adap, i) {
4200 struct net_device *dev = adap->port[i];
4202 if (netif_running(dev)) {
4204 cxgb_set_rxmode(dev);
4206 netif_device_attach(dev);
4211 static const struct pci_error_handlers cxgb4_eeh = {
4212 .error_detected = eeh_err_detected,
4213 .slot_reset = eeh_slot_reset,
4214 .resume = eeh_resume,
4217 static inline bool is_x_10g_port(const struct link_config *lc)
4219 return (lc->supported & FW_PORT_CAP_SPEED_10G) != 0 ||
4220 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0;
4223 static inline void init_rspq(struct adapter *adap, struct sge_rspq *q,
4224 unsigned int us, unsigned int cnt,
4225 unsigned int size, unsigned int iqe_size)
4228 cxgb4_set_rspq_intr_params(q, us, cnt);
4229 q->iqe_len = iqe_size;
4234 * Perform default configuration of DMA queues depending on the number and type
4235 * of ports we found and the number of available CPUs. Most settings can be
4236 * modified by the admin prior to actual use.
4238 static void cfg_queues(struct adapter *adap)
4240 struct sge *s = &adap->sge;
4241 int i, n10g = 0, qidx = 0;
4242 #ifndef CONFIG_CHELSIO_T4_DCB
4247 for_each_port(adap, i)
4248 n10g += is_x_10g_port(&adap2pinfo(adap, i)->link_cfg);
4249 #ifdef CONFIG_CHELSIO_T4_DCB
4250 /* For Data Center Bridging support we need to be able to support up
4251 * to 8 Traffic Priorities; each of which will be assigned to its
4252 * own TX Queue in order to prevent Head-Of-Line Blocking.
4254 if (adap->params.nports * 8 > MAX_ETH_QSETS) {
4255 dev_err(adap->pdev_dev, "MAX_ETH_QSETS=%d < %d!\n",
4256 MAX_ETH_QSETS, adap->params.nports * 8);
4260 for_each_port(adap, i) {
4261 struct port_info *pi = adap2pinfo(adap, i);
4263 pi->first_qset = qidx;
4267 #else /* !CONFIG_CHELSIO_T4_DCB */
4269 * We default to 1 queue per non-10G port and up to # of cores queues
4273 q10g = (MAX_ETH_QSETS - (adap->params.nports - n10g)) / n10g;
4274 if (q10g > netif_get_num_default_rss_queues())
4275 q10g = netif_get_num_default_rss_queues();
4277 for_each_port(adap, i) {
4278 struct port_info *pi = adap2pinfo(adap, i);
4280 pi->first_qset = qidx;
4281 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
4284 #endif /* !CONFIG_CHELSIO_T4_DCB */
4287 s->max_ethqsets = qidx; /* MSI-X may lower it later */
4289 if (is_offload(adap)) {
4291 * For offload we use 1 queue/channel if all ports are up to 1G,
4292 * otherwise we divide all available queues amongst the channels
4293 * capped by the number of available cores.
4296 i = min_t(int, ARRAY_SIZE(s->iscsirxq),
4298 s->iscsiqsets = roundup(i, adap->params.nports);
4300 s->iscsiqsets = adap->params.nports;
4301 /* For RDMA one Rx queue per channel suffices */
4302 s->rdmaqs = adap->params.nports;
4303 /* Try and allow at least 1 CIQ per cpu rounding down
4304 * to the number of ports, with a minimum of 1 per port.
4305 * A 2 port card in a 6 cpu system: 6 CIQs, 3 / port.
4306 * A 4 port card in a 6 cpu system: 4 CIQs, 1 / port.
4307 * A 4 port card in a 2 cpu system: 4 CIQs, 1 / port.
4309 s->rdmaciqs = min_t(int, MAX_RDMA_CIQS, num_online_cpus());
4310 s->rdmaciqs = (s->rdmaciqs / adap->params.nports) *
4311 adap->params.nports;
4312 s->rdmaciqs = max_t(int, s->rdmaciqs, adap->params.nports);
4315 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) {
4316 struct sge_eth_rxq *r = &s->ethrxq[i];
4318 init_rspq(adap, &r->rspq, 5, 10, 1024, 64);
4322 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++)
4323 s->ethtxq[i].q.size = 1024;
4325 for (i = 0; i < ARRAY_SIZE(s->ctrlq); i++)
4326 s->ctrlq[i].q.size = 512;
4328 for (i = 0; i < ARRAY_SIZE(s->ofldtxq); i++)
4329 s->ofldtxq[i].q.size = 1024;
4331 for (i = 0; i < ARRAY_SIZE(s->iscsirxq); i++) {
4332 struct sge_ofld_rxq *r = &s->iscsirxq[i];
4334 init_rspq(adap, &r->rspq, 5, 1, 1024, 64);
4335 r->rspq.uld = CXGB4_ULD_ISCSI;
4339 for (i = 0; i < ARRAY_SIZE(s->rdmarxq); i++) {
4340 struct sge_ofld_rxq *r = &s->rdmarxq[i];
4342 init_rspq(adap, &r->rspq, 5, 1, 511, 64);
4343 r->rspq.uld = CXGB4_ULD_RDMA;
4347 ciq_size = 64 + adap->vres.cq.size + adap->tids.nftids;
4348 if (ciq_size > SGE_MAX_IQ_SIZE) {
4349 CH_WARN(adap, "CIQ size too small for available IQs\n");
4350 ciq_size = SGE_MAX_IQ_SIZE;
4353 for (i = 0; i < ARRAY_SIZE(s->rdmaciq); i++) {
4354 struct sge_ofld_rxq *r = &s->rdmaciq[i];
4356 init_rspq(adap, &r->rspq, 5, 1, ciq_size, 64);
4357 r->rspq.uld = CXGB4_ULD_RDMA;
4360 init_rspq(adap, &s->fw_evtq, 0, 1, 1024, 64);
4361 init_rspq(adap, &s->intrq, 0, 1, 2 * MAX_INGQ, 64);
4365 * Reduce the number of Ethernet queues across all ports to at most n.
4366 * n provides at least one queue per port.
4368 static void reduce_ethqs(struct adapter *adap, int n)
4371 struct port_info *pi;
4373 while (n < adap->sge.ethqsets)
4374 for_each_port(adap, i) {
4375 pi = adap2pinfo(adap, i);
4376 if (pi->nqsets > 1) {
4378 adap->sge.ethqsets--;
4379 if (adap->sge.ethqsets <= n)
4385 for_each_port(adap, i) {
4386 pi = adap2pinfo(adap, i);
4392 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
4393 #define EXTRA_VECS 2
4395 static int enable_msix(struct adapter *adap)
4398 int i, want, need, allocated;
4399 struct sge *s = &adap->sge;
4400 unsigned int nchan = adap->params.nports;
4401 struct msix_entry *entries;
4403 entries = kmalloc(sizeof(*entries) * (MAX_INGQ + 1),
4408 for (i = 0; i < MAX_INGQ + 1; ++i)
4409 entries[i].entry = i;
4411 want = s->max_ethqsets + EXTRA_VECS;
4412 if (is_offload(adap)) {
4413 want += s->rdmaqs + s->rdmaciqs + s->iscsiqsets;
4414 /* need nchan for each possible ULD */
4415 ofld_need = 3 * nchan;
4417 #ifdef CONFIG_CHELSIO_T4_DCB
4418 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
4421 need = 8 * adap->params.nports + EXTRA_VECS + ofld_need;
4423 need = adap->params.nports + EXTRA_VECS + ofld_need;
4425 allocated = pci_enable_msix_range(adap->pdev, entries, need, want);
4426 if (allocated < 0) {
4427 dev_info(adap->pdev_dev, "not enough MSI-X vectors left,"
4428 " not using MSI-X\n");
4433 /* Distribute available vectors to the various queue groups.
4434 * Every group gets its minimum requirement and NIC gets top
4435 * priority for leftovers.
4437 i = allocated - EXTRA_VECS - ofld_need;
4438 if (i < s->max_ethqsets) {
4439 s->max_ethqsets = i;
4440 if (i < s->ethqsets)
4441 reduce_ethqs(adap, i);
4443 if (is_offload(adap)) {
4444 if (allocated < want) {
4446 s->rdmaciqs = nchan;
4449 /* leftovers go to OFLD */
4450 i = allocated - EXTRA_VECS - s->max_ethqsets -
4451 s->rdmaqs - s->rdmaciqs;
4452 s->iscsiqsets = (i / nchan) * nchan; /* round down */
4454 for (i = 0; i < allocated; ++i)
4455 adap->msix_info[i].vec = entries[i].vector;
4456 dev_info(adap->pdev_dev, "%d MSI-X vectors allocated, "
4457 "nic %d iscsi %d rdma cpl %d rdma ciq %d\n",
4458 allocated, s->max_ethqsets, s->iscsiqsets, s->rdmaqs,
4467 static int init_rss(struct adapter *adap)
4472 err = t4_init_rss_mode(adap, adap->mbox);
4476 for_each_port(adap, i) {
4477 struct port_info *pi = adap2pinfo(adap, i);
4479 pi->rss = kcalloc(pi->rss_size, sizeof(u16), GFP_KERNEL);
4486 static int cxgb4_get_pcie_dev_link_caps(struct adapter *adap,
4487 enum pci_bus_speed *speed,
4488 enum pcie_link_width *width)
4490 u32 lnkcap1, lnkcap2;
4493 #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */
4495 *speed = PCI_SPEED_UNKNOWN;
4496 *width = PCIE_LNK_WIDTH_UNKNOWN;
4498 err1 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP,
4500 err2 = pcie_capability_read_dword(adap->pdev, PCI_EXP_LNKCAP2,
4502 if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */
4503 if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB)
4504 *speed = PCIE_SPEED_8_0GT;
4505 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB)
4506 *speed = PCIE_SPEED_5_0GT;
4507 else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB)
4508 *speed = PCIE_SPEED_2_5GT;
4511 *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT;
4512 if (!lnkcap2) { /* pre-r3.0 */
4513 if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB)
4514 *speed = PCIE_SPEED_5_0GT;
4515 else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB)
4516 *speed = PCIE_SPEED_2_5GT;
4520 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
4521 return err1 ? err1 : err2 ? err2 : -EINVAL;
4525 static void cxgb4_check_pcie_caps(struct adapter *adap)
4527 enum pcie_link_width width, width_cap;
4528 enum pci_bus_speed speed, speed_cap;
4530 #define PCIE_SPEED_STR(speed) \
4531 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \
4532 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \
4533 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \
4536 if (cxgb4_get_pcie_dev_link_caps(adap, &speed_cap, &width_cap)) {
4537 dev_warn(adap->pdev_dev,
4538 "Unable to determine PCIe device BW capabilities\n");
4542 if (pcie_get_minimum_link(adap->pdev, &speed, &width) ||
4543 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
4544 dev_warn(adap->pdev_dev,
4545 "Unable to determine PCI Express bandwidth.\n");
4549 dev_info(adap->pdev_dev, "PCIe link speed is %s, device supports %s\n",
4550 PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap));
4551 dev_info(adap->pdev_dev, "PCIe link width is x%d, device supports x%d\n",
4553 if (speed < speed_cap || width < width_cap)
4554 dev_info(adap->pdev_dev,
4555 "A slot with more lanes and/or higher speed is "
4556 "suggested for optimal performance.\n");
4559 static void print_port_info(const struct net_device *dev)
4563 const char *spd = "";
4564 const struct port_info *pi = netdev_priv(dev);
4565 const struct adapter *adap = pi->adapter;
4567 if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_2_5GB)
4569 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_5_0GB)
4571 else if (adap->params.pci.speed == PCI_EXP_LNKSTA_CLS_8_0GB)
4574 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M)
4575 bufp += sprintf(bufp, "100/");
4576 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
4577 bufp += sprintf(bufp, "1000/");
4578 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
4579 bufp += sprintf(bufp, "10G/");
4580 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
4581 bufp += sprintf(bufp, "40G/");
4584 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type));
4586 netdev_info(dev, "Chelsio %s rev %d %s %sNIC %s\n",
4587 adap->params.vpd.id,
4588 CHELSIO_CHIP_RELEASE(adap->params.chip), buf,
4589 is_offload(adap) ? "R" : "",
4590 (adap->flags & USING_MSIX) ? " MSI-X" :
4591 (adap->flags & USING_MSI) ? " MSI" : "");
4592 netdev_info(dev, "S/N: %s, P/N: %s\n",
4593 adap->params.vpd.sn, adap->params.vpd.pn);
4596 static void enable_pcie_relaxed_ordering(struct pci_dev *dev)
4598 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
4602 * Free the following resources:
4603 * - memory used for tables
4606 * - resources FW is holding for us
4608 static void free_some_resources(struct adapter *adapter)
4612 t4_free_mem(adapter->l2t);
4613 t4_free_mem(adapter->tids.tid_tab);
4614 kfree(adapter->sge.egr_map);
4615 kfree(adapter->sge.ingr_map);
4616 kfree(adapter->sge.starving_fl);
4617 kfree(adapter->sge.txq_maperr);
4618 #ifdef CONFIG_DEBUG_FS
4619 kfree(adapter->sge.blocked_fl);
4621 disable_msi(adapter);
4623 for_each_port(adapter, i)
4624 if (adapter->port[i]) {
4625 struct port_info *pi = adap2pinfo(adapter, i);
4628 t4_free_vi(adapter, adapter->mbox, adapter->pf,
4630 kfree(adap2pinfo(adapter, i)->rss);
4631 free_netdev(adapter->port[i]);
4633 if (adapter->flags & FW_OK)
4634 t4_fw_bye(adapter, adapter->pf);
4637 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
4638 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
4639 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
4640 #define SEGMENT_SIZE 128
4642 static int get_chip_type(struct pci_dev *pdev, u32 pl_rev)
4646 /* Retrieve adapter's device ID */
4647 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
4649 switch (device_id >> 12) {
4651 return CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
4653 return CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
4655 return CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
4657 dev_err(&pdev->dev, "Device %d is not supported\n",
4663 static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
4665 int func, i, err, s_qpp, qpp, num_seg;
4666 struct port_info *pi;
4667 bool highdma = false;
4668 struct adapter *adapter = NULL;
4671 enum chip_type chip;
4673 printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
4675 err = pci_request_regions(pdev, KBUILD_MODNAME);
4677 /* Just info, some other driver may have claimed the device. */
4678 dev_info(&pdev->dev, "cannot obtain PCI resources\n");
4682 err = pci_enable_device(pdev);
4684 dev_err(&pdev->dev, "cannot enable PCI device\n");
4685 goto out_release_regions;
4688 regs = pci_ioremap_bar(pdev, 0);
4690 dev_err(&pdev->dev, "cannot map device registers\n");
4692 goto out_disable_device;
4695 err = t4_wait_dev_ready(regs);
4697 goto out_unmap_bar0;
4699 /* We control everything through one PF */
4700 whoami = readl(regs + PL_WHOAMI_A);
4701 pl_rev = REV_G(readl(regs + PL_REV_A));
4702 chip = get_chip_type(pdev, pl_rev);
4703 func = CHELSIO_CHIP_VERSION(chip) <= CHELSIO_T5 ?
4704 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4705 if (func != ent->driver_data) {
4707 pci_disable_device(pdev);
4708 pci_save_state(pdev); /* to restore SR-IOV later */
4712 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4714 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4716 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for "
4717 "coherent allocations\n");
4718 goto out_unmap_bar0;
4721 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4723 dev_err(&pdev->dev, "no usable DMA configuration\n");
4724 goto out_unmap_bar0;
4728 pci_enable_pcie_error_reporting(pdev);
4729 enable_pcie_relaxed_ordering(pdev);
4730 pci_set_master(pdev);
4731 pci_save_state(pdev);
4733 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
4736 goto out_unmap_bar0;
4739 adapter->workq = create_singlethread_workqueue("cxgb4");
4740 if (!adapter->workq) {
4742 goto out_free_adapter;
4745 /* PCI device has been enabled */
4746 adapter->flags |= DEV_ENABLED;
4748 adapter->regs = regs;
4749 adapter->pdev = pdev;
4750 adapter->pdev_dev = &pdev->dev;
4751 adapter->mbox = func;
4753 adapter->msg_enable = dflt_msg_enable;
4754 memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
4756 spin_lock_init(&adapter->stats_lock);
4757 spin_lock_init(&adapter->tid_release_lock);
4758 spin_lock_init(&adapter->win0_lock);
4760 INIT_WORK(&adapter->tid_release_task, process_tid_release_list);
4761 INIT_WORK(&adapter->db_full_task, process_db_full);
4762 INIT_WORK(&adapter->db_drop_task, process_db_drop);
4764 err = t4_prep_adapter(adapter);
4766 goto out_free_adapter;
4769 if (!is_t4(adapter->params.chip)) {
4770 s_qpp = (QUEUESPERPAGEPF0_S +
4771 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) *
4773 qpp = 1 << QUEUESPERPAGEPF0_G(t4_read_reg(adapter,
4774 SGE_EGRESS_QUEUES_PER_PAGE_PF_A) >> s_qpp);
4775 num_seg = PAGE_SIZE / SEGMENT_SIZE;
4777 /* Each segment size is 128B. Write coalescing is enabled only
4778 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
4779 * queue is less no of segments that can be accommodated in
4782 if (qpp > num_seg) {
4784 "Incorrect number of egress queues per page\n");
4786 goto out_free_adapter;
4788 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
4789 pci_resource_len(pdev, 2));
4790 if (!adapter->bar2) {
4791 dev_err(&pdev->dev, "cannot map device bar2 region\n");
4793 goto out_free_adapter;
4797 setup_memwin(adapter);
4798 err = adap_init0(adapter);
4799 #ifdef CONFIG_DEBUG_FS
4800 bitmap_zero(adapter->sge.blocked_fl, adapter->sge.egr_sz);
4802 setup_memwin_rdma(adapter);
4806 /* configure SGE_STAT_CFG_A to read WC stats */
4807 if (!is_t4(adapter->params.chip))
4808 t4_write_reg(adapter, SGE_STAT_CFG_A, STATSOURCE_T5_V(7) |
4809 (is_t5(adapter->params.chip) ? STATMODE_V(0) :
4812 for_each_port(adapter, i) {
4813 struct net_device *netdev;
4815 netdev = alloc_etherdev_mq(sizeof(struct port_info),
4822 SET_NETDEV_DEV(netdev, &pdev->dev);
4824 adapter->port[i] = netdev;
4825 pi = netdev_priv(netdev);
4826 pi->adapter = adapter;
4827 pi->xact_addr_filt = -1;
4829 netdev->irq = pdev->irq;
4831 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
4832 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
4833 NETIF_F_RXCSUM | NETIF_F_RXHASH |
4834 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
4836 netdev->hw_features |= NETIF_F_HIGHDMA;
4837 netdev->features |= netdev->hw_features;
4838 netdev->vlan_features = netdev->features & VLAN_FEAT;
4840 netdev->priv_flags |= IFF_UNICAST_FLT;
4842 netdev->netdev_ops = &cxgb4_netdev_ops;
4843 #ifdef CONFIG_CHELSIO_T4_DCB
4844 netdev->dcbnl_ops = &cxgb4_dcb_ops;
4845 cxgb4_dcb_state_init(netdev);
4847 cxgb4_set_ethtool_ops(netdev);
4850 pci_set_drvdata(pdev, adapter);
4852 if (adapter->flags & FW_OK) {
4853 err = t4_port_init(adapter, func, func, 0);
4856 } else if (adapter->params.nports == 1) {
4857 /* If we don't have a connection to the firmware -- possibly
4858 * because of an error -- grab the raw VPD parameters so we
4859 * can set the proper MAC Address on the debug network
4860 * interface that we've created.
4862 u8 hw_addr[ETH_ALEN];
4863 u8 *na = adapter->params.vpd.na;
4865 err = t4_get_raw_vpd_params(adapter, &adapter->params.vpd);
4867 for (i = 0; i < ETH_ALEN; i++)
4868 hw_addr[i] = (hex2val(na[2 * i + 0]) * 16 +
4869 hex2val(na[2 * i + 1]));
4870 t4_set_hw_addr(adapter, 0, hw_addr);
4874 /* Configure queues and allocate tables now, they can be needed as
4875 * soon as the first register_netdev completes.
4877 cfg_queues(adapter);
4879 adapter->l2t = t4_init_l2t(adapter->l2t_start, adapter->l2t_end);
4880 if (!adapter->l2t) {
4881 /* We tolerate a lack of L2T, giving up some functionality */
4882 dev_warn(&pdev->dev, "could not allocate L2T, continuing\n");
4883 adapter->params.offload = 0;
4886 #if IS_ENABLED(CONFIG_IPV6)
4887 if ((CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) &&
4888 (!(t4_read_reg(adapter, LE_DB_CONFIG_A) & ASLIPCOMPEN_F))) {
4889 /* CLIP functionality is not present in hardware,
4890 * hence disable all offload features
4892 dev_warn(&pdev->dev,
4893 "CLIP not enabled in hardware, continuing\n");
4894 adapter->params.offload = 0;
4896 adapter->clipt = t4_init_clip_tbl(adapter->clipt_start,
4897 adapter->clipt_end);
4898 if (!adapter->clipt) {
4899 /* We tolerate a lack of clip_table, giving up
4900 * some functionality
4902 dev_warn(&pdev->dev,
4903 "could not allocate Clip table, continuing\n");
4904 adapter->params.offload = 0;
4908 if (is_offload(adapter) && tid_init(&adapter->tids) < 0) {
4909 dev_warn(&pdev->dev, "could not allocate TID table, "
4911 adapter->params.offload = 0;
4914 if (is_offload(adapter)) {
4915 if (t4_read_reg(adapter, LE_DB_CONFIG_A) & HASHEN_F) {
4916 u32 hash_base, hash_reg;
4918 if (chip <= CHELSIO_T5) {
4919 hash_reg = LE_DB_TID_HASHBASE_A;
4920 hash_base = t4_read_reg(adapter, hash_reg);
4921 adapter->tids.hash_base = hash_base / 4;
4923 hash_reg = T6_LE_DB_HASH_TID_BASE_A;
4924 hash_base = t4_read_reg(adapter, hash_reg);
4925 adapter->tids.hash_base = hash_base;
4930 /* See what interrupts we'll be using */
4931 if (msi > 1 && enable_msix(adapter) == 0)
4932 adapter->flags |= USING_MSIX;
4933 else if (msi > 0 && pci_enable_msi(pdev) == 0)
4934 adapter->flags |= USING_MSI;
4936 /* check for PCI Express bandwidth capabiltites */
4937 cxgb4_check_pcie_caps(adapter);
4939 err = init_rss(adapter);
4944 * The card is now ready to go. If any errors occur during device
4945 * registration we do not fail the whole card but rather proceed only
4946 * with the ports we manage to register successfully. However we must
4947 * register at least one net device.
4949 for_each_port(adapter, i) {
4950 pi = adap2pinfo(adapter, i);
4951 netif_set_real_num_tx_queues(adapter->port[i], pi->nqsets);
4952 netif_set_real_num_rx_queues(adapter->port[i], pi->nqsets);
4954 err = register_netdev(adapter->port[i]);
4957 adapter->chan_map[pi->tx_chan] = i;
4958 print_port_info(adapter->port[i]);
4961 dev_err(&pdev->dev, "could not register any net devices\n");
4965 dev_warn(&pdev->dev, "only %d net devices registered\n", i);
4969 if (cxgb4_debugfs_root) {
4970 adapter->debugfs_root = debugfs_create_dir(pci_name(pdev),
4971 cxgb4_debugfs_root);
4972 setup_debugfs(adapter);
4975 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
4976 pdev->needs_freset = 1;
4978 if (is_offload(adapter))
4979 attach_ulds(adapter);
4982 #ifdef CONFIG_PCI_IOV
4983 if (func < ARRAY_SIZE(num_vf) && num_vf[func] > 0)
4984 if (pci_enable_sriov(pdev, num_vf[func]) == 0)
4985 dev_info(&pdev->dev,
4986 "instantiated %u virtual functions\n",
4992 free_some_resources(adapter);
4994 if (!is_t4(adapter->params.chip))
4995 iounmap(adapter->bar2);
4998 destroy_workqueue(adapter->workq);
5004 pci_disable_pcie_error_reporting(pdev);
5005 pci_disable_device(pdev);
5006 out_release_regions:
5007 pci_release_regions(pdev);
5011 static void remove_one(struct pci_dev *pdev)
5013 struct adapter *adapter = pci_get_drvdata(pdev);
5015 #ifdef CONFIG_PCI_IOV
5016 pci_disable_sriov(pdev);
5023 /* Tear down per-adapter Work Queue first since it can contain
5024 * references to our adapter data structure.
5026 destroy_workqueue(adapter->workq);
5028 if (is_offload(adapter))
5029 detach_ulds(adapter);
5031 disable_interrupts(adapter);
5033 for_each_port(adapter, i)
5034 if (adapter->port[i]->reg_state == NETREG_REGISTERED)
5035 unregister_netdev(adapter->port[i]);
5037 debugfs_remove_recursive(adapter->debugfs_root);
5039 /* If we allocated filters, free up state associated with any
5042 if (adapter->tids.ftid_tab) {
5043 struct filter_entry *f = &adapter->tids.ftid_tab[0];
5044 for (i = 0; i < (adapter->tids.nftids +
5045 adapter->tids.nsftids); i++, f++)
5047 clear_filter(adapter, f);
5050 if (adapter->flags & FULL_INIT_DONE)
5053 free_some_resources(adapter);
5054 #if IS_ENABLED(CONFIG_IPV6)
5055 t4_cleanup_clip_tbl(adapter);
5057 iounmap(adapter->regs);
5058 if (!is_t4(adapter->params.chip))
5059 iounmap(adapter->bar2);
5060 pci_disable_pcie_error_reporting(pdev);
5061 if ((adapter->flags & DEV_ENABLED)) {
5062 pci_disable_device(pdev);
5063 adapter->flags &= ~DEV_ENABLED;
5065 pci_release_regions(pdev);
5069 pci_release_regions(pdev);
5072 static struct pci_driver cxgb4_driver = {
5073 .name = KBUILD_MODNAME,
5074 .id_table = cxgb4_pci_tbl,
5076 .remove = remove_one,
5077 .shutdown = remove_one,
5078 .err_handler = &cxgb4_eeh,
5081 static int __init cxgb4_init_module(void)
5085 /* Debugfs support is optional, just warn if this fails */
5086 cxgb4_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
5087 if (!cxgb4_debugfs_root)
5088 pr_warn("could not create debugfs entry, continuing\n");
5090 ret = pci_register_driver(&cxgb4_driver);
5092 debugfs_remove(cxgb4_debugfs_root);
5094 #if IS_ENABLED(CONFIG_IPV6)
5095 if (!inet6addr_registered) {
5096 register_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5097 inet6addr_registered = true;
5104 static void __exit cxgb4_cleanup_module(void)
5106 #if IS_ENABLED(CONFIG_IPV6)
5107 if (inet6addr_registered) {
5108 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier);
5109 inet6addr_registered = false;
5112 pci_unregister_driver(&cxgb4_driver);
5113 debugfs_remove(cxgb4_debugfs_root); /* NULL ok */
5116 module_init(cxgb4_init_module);
5117 module_exit(cxgb4_cleanup_module);