2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
40 #include "t4fw_version.h"
43 * t4_wait_op_done_val - wait until an operation is completed
44 * @adapter: the adapter performing the operation
45 * @reg: the register to check for completion
46 * @mask: a single-bit field within @reg that indicates completion
47 * @polarity: the value of the field when the operation is completed
48 * @attempts: number of check iterations
49 * @delay: delay in usecs between iterations
50 * @valp: where to store the value of the register at completion time
52 * Wait until an operation is completed by checking a bit in a register
53 * up to @attempts times. If @valp is not NULL the value of the register
54 * at the time it indicated completion is stored there. Returns 0 if the
55 * operation completes and -EAGAIN otherwise.
57 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
58 int polarity, int attempts, int delay, u32 *valp)
61 u32 val = t4_read_reg(adapter, reg);
63 if (!!(val & mask) == polarity) {
75 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
76 int polarity, int attempts, int delay)
78 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
83 * t4_set_reg_field - set a register field to a value
84 * @adapter: the adapter to program
85 * @addr: the register address
86 * @mask: specifies the portion of the register to modify
87 * @val: the new value for the register field
89 * Sets a register field specified by the supplied mask to the
92 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
95 u32 v = t4_read_reg(adapter, addr) & ~mask;
97 t4_write_reg(adapter, addr, v | val);
98 (void) t4_read_reg(adapter, addr); /* flush */
102 * t4_read_indirect - read indirectly addressed registers
104 * @addr_reg: register holding the indirect address
105 * @data_reg: register holding the value of the indirect register
106 * @vals: where the read register values are stored
107 * @nregs: how many indirect registers to read
108 * @start_idx: index of first indirect register to read
110 * Reads registers that are accessed indirectly through an address/data
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
114 unsigned int data_reg, u32 *vals,
115 unsigned int nregs, unsigned int start_idx)
118 t4_write_reg(adap, addr_reg, start_idx);
119 *vals++ = t4_read_reg(adap, data_reg);
125 * t4_write_indirect - write indirectly addressed registers
127 * @addr_reg: register holding the indirect addresses
128 * @data_reg: register holding the value for the indirect registers
129 * @vals: values to write
130 * @nregs: how many indirect registers to write
131 * @start_idx: address of first indirect register to write
133 * Writes a sequential block of registers that are accessed indirectly
134 * through an address/data register pair.
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
137 unsigned int data_reg, const u32 *vals,
138 unsigned int nregs, unsigned int start_idx)
141 t4_write_reg(adap, addr_reg, start_idx++);
142 t4_write_reg(adap, data_reg, *vals++);
147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
148 * mechanism. This guarantees that we get the real value even if we're
149 * operating within a Virtual Machine and the Hypervisor is trapping our
150 * Configuration Space accesses.
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
161 if (is_t4(adap->params.chip))
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
168 * Configuration Space read. (None of the other fields matter when
169 * ENABLE is 0 so a simple register write is easier than a
170 * read-modify-write via t4_set_reg_field().)
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
176 * t4_report_fw_error - report firmware error
179 * The adapter firmware can indicate error conditions to the host.
180 * If the firmware has indicated an error, print out the reason for
181 * the firmware error.
183 static void t4_report_fw_error(struct adapter *adap)
185 static const char *const reason[] = {
186 "Crash", /* PCIE_FW_EVAL_CRASH */
187 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
188 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
189 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
190 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
191 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
192 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
193 "Reserved", /* reserved */
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
198 if (pcie_fw & PCIE_FW_ERR_F)
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
200 reason[PCIE_FW_EVAL_G(pcie_fw)]);
204 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
209 for ( ; nflit; nflit--, mbox_addr += 8)
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 * Handle a FW assertion reported in a mailbox.
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
218 struct fw_debug_cmd asrt;
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
221 dev_alert(adap->pdev_dev,
222 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
223 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
224 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
227 static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
229 dev_err(adap->pdev_dev,
230 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
231 (unsigned long long)t4_read_reg64(adap, data_reg),
232 (unsigned long long)t4_read_reg64(adap, data_reg + 8),
233 (unsigned long long)t4_read_reg64(adap, data_reg + 16),
234 (unsigned long long)t4_read_reg64(adap, data_reg + 24),
235 (unsigned long long)t4_read_reg64(adap, data_reg + 32),
236 (unsigned long long)t4_read_reg64(adap, data_reg + 40),
237 (unsigned long long)t4_read_reg64(adap, data_reg + 48),
238 (unsigned long long)t4_read_reg64(adap, data_reg + 56));
242 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
244 * @mbox: index of the mailbox to use
245 * @cmd: the command to write
246 * @size: command length in bytes
247 * @rpl: where to optionally store the reply
248 * @sleep_ok: if true we may sleep while awaiting command completion
249 * @timeout: time to wait for command to finish before timing out
251 * Sends the given command to FW through the selected mailbox and waits
252 * for the FW to execute the command. If @rpl is not %NULL it is used to
253 * store the FW's reply to the command. The command and its optional
254 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
255 * to respond. @sleep_ok determines whether we may sleep while awaiting
256 * the response. If sleeping is allowed we use progressive backoff
259 * The return value is 0 on success or a negative errno on failure. A
260 * failure can happen either because we are not able to execute the
261 * command or FW executes it but signals an error. In the latter case
262 * the return value is the error code indicated by FW (negated).
264 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
265 int size, void *rpl, bool sleep_ok, int timeout)
267 static const int delay[] = {
268 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
273 int i, ms, delay_idx;
274 const __be64 *p = cmd;
275 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
276 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
278 if ((size & 15) || size > MBOX_LEN)
282 * If the device is off-line, as in EEH, commands will time out.
283 * Fail them early so we don't waste time waiting.
285 if (adap->pdev->error_state != pci_channel_io_normal)
288 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
289 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
290 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
292 if (v != MBOX_OWNER_DRV)
293 return v ? -EBUSY : -ETIMEDOUT;
295 for (i = 0; i < size; i += 8)
296 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
298 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
299 t4_read_reg(adap, ctl_reg); /* flush write */
304 for (i = 0; i < timeout; i += ms) {
306 ms = delay[delay_idx]; /* last element may repeat */
307 if (delay_idx < ARRAY_SIZE(delay) - 1)
313 v = t4_read_reg(adap, ctl_reg);
314 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
315 if (!(v & MBMSGVALID_F)) {
316 t4_write_reg(adap, ctl_reg, 0);
320 res = t4_read_reg64(adap, data_reg);
321 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
322 fw_asrt(adap, data_reg);
323 res = FW_CMD_RETVAL_V(EIO);
325 get_mbox_rpl(adap, rpl, size / 8, data_reg);
328 if (FW_CMD_RETVAL_G((int)res))
329 dump_mbox(adap, mbox, data_reg);
330 t4_write_reg(adap, ctl_reg, 0);
331 return -FW_CMD_RETVAL_G((int)res);
335 dump_mbox(adap, mbox, data_reg);
336 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
337 *(const u8 *)cmd, mbox);
338 t4_report_fw_error(adap);
342 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
343 void *rpl, bool sleep_ok)
345 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
349 static int t4_edc_err_read(struct adapter *adap, int idx)
351 u32 edc_ecc_err_addr_reg;
354 if (is_t4(adap->params.chip)) {
355 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
358 if (idx != 0 && idx != 1) {
359 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
363 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
364 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
367 "edc%d err addr 0x%x: 0x%x.\n",
368 idx, edc_ecc_err_addr_reg,
369 t4_read_reg(adap, edc_ecc_err_addr_reg));
371 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
373 (unsigned long long)t4_read_reg64(adap, rdata_reg),
374 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
375 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
376 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
377 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
378 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
379 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
380 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
381 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
387 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
389 * @win: PCI-E Memory Window to use
390 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
391 * @addr: address within indicated memory type
392 * @len: amount of memory to transfer
393 * @hbuf: host memory buffer
394 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
396 * Reads/writes an [almost] arbitrary memory region in the firmware: the
397 * firmware memory address and host buffer must be aligned on 32-bit
398 * boudaries; the length may be arbitrary. The memory is transferred as
399 * a raw byte sequence from/to the firmware's memory. If this memory
400 * contains data structures which contain multi-byte integers, it's the
401 * caller's responsibility to perform appropriate byte order conversions.
403 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
404 u32 len, void *hbuf, int dir)
406 u32 pos, offset, resid, memoffset;
407 u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
410 /* Argument sanity checks ...
412 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
416 /* It's convenient to be able to handle lengths which aren't a
417 * multiple of 32-bits because we often end up transferring files to
418 * the firmware. So we'll handle that by normalizing the length here
419 * and then handling any residual transfer at the end.
424 /* Offset into the region of memory which is being accessed
427 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
428 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
430 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
431 if (mtype != MEM_MC1)
432 memoffset = (mtype * (edc_size * 1024 * 1024));
434 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
435 MA_EXT_MEMORY0_BAR_A));
436 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
439 /* Determine the PCIE_MEM_ACCESS_OFFSET */
440 addr = addr + memoffset;
442 /* Each PCI-E Memory Window is programmed with a window size -- or
443 * "aperture" -- which controls the granularity of its mapping onto
444 * adapter memory. We need to grab that aperture in order to know
445 * how to use the specified window. The window is also programmed
446 * with the base address of the Memory Window in BAR0's address
447 * space. For T4 this is an absolute PCI-E Bus Address. For T5
448 * the address is relative to BAR0.
450 mem_reg = t4_read_reg(adap,
451 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
453 mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
454 mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
455 if (is_t4(adap->params.chip))
456 mem_base -= adap->t4_bar0;
457 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
459 /* Calculate our initial PCI-E Memory Window Position and Offset into
462 pos = addr & ~(mem_aperture-1);
465 /* Set up initial PCI-E Memory Window to cover the start of our
466 * transfer. (Read it back to ensure that changes propagate before we
467 * attempt to use the new value.)
470 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
473 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
475 /* Transfer data to/from the adapter as long as there's an integral
476 * number of 32-bit transfers to complete.
478 * A note on Endianness issues:
480 * The "register" reads and writes below from/to the PCI-E Memory
481 * Window invoke the standard adapter Big-Endian to PCI-E Link
482 * Little-Endian "swizzel." As a result, if we have the following
483 * data in adapter memory:
485 * Memory: ... | b0 | b1 | b2 | b3 | ...
486 * Address: i+0 i+1 i+2 i+3
488 * Then a read of the adapter memory via the PCI-E Memory Window
493 * [ b3 | b2 | b1 | b0 ]
495 * If this value is stored into local memory on a Little-Endian system
496 * it will show up correctly in local memory as:
498 * ( ..., b0, b1, b2, b3, ... )
500 * But on a Big-Endian system, the store will show up in memory
501 * incorrectly swizzled as:
503 * ( ..., b3, b2, b1, b0, ... )
505 * So we need to account for this in the reads and writes to the
506 * PCI-E Memory Window below by undoing the register read/write
510 if (dir == T4_MEMORY_READ)
511 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
514 t4_write_reg(adap, mem_base + offset,
515 (__force u32)cpu_to_le32(*buf++));
516 offset += sizeof(__be32);
517 len -= sizeof(__be32);
519 /* If we've reached the end of our current window aperture,
520 * move the PCI-E Memory Window on to the next. Note that
521 * doing this here after "len" may be 0 allows us to set up
522 * the PCI-E Memory Window for a possible final residual
525 if (offset == mem_aperture) {
529 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
532 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A,
537 /* If the original transfer had a length which wasn't a multiple of
538 * 32-bits, now's where we need to finish off the transfer of the
539 * residual amount. The PCI-E Memory Window has already been moved
540 * above (if necessary) to cover this final transfer.
550 if (dir == T4_MEMORY_READ) {
551 last.word = le32_to_cpu(
552 (__force __le32)t4_read_reg(adap,
554 for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
555 bp[i] = last.byte[i];
558 for (i = resid; i < 4; i++)
560 t4_write_reg(adap, mem_base + offset,
561 (__force u32)cpu_to_le32(last.word));
568 /* Return the specified PCI-E Configuration Space register from our Physical
569 * Function. We try first via a Firmware LDST Command since we prefer to let
570 * the firmware own all of these registers, but if that fails we go for it
571 * directly ourselves.
573 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
575 u32 val, ldst_addrspace;
577 /* If fw_attach != 0, construct and send the Firmware LDST Command to
578 * retrieve the specified PCI-E Configuration Space register.
580 struct fw_ldst_cmd ldst_cmd;
583 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
584 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
585 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
589 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
590 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
591 ldst_cmd.u.pcie.ctrl_to_fn =
592 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
593 ldst_cmd.u.pcie.r = reg;
595 /* If the LDST Command succeeds, return the result, otherwise
596 * fall through to reading it directly ourselves ...
598 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
601 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
603 /* Read the desired Configuration Space register via the PCI-E
604 * Backdoor mechanism.
606 t4_hw_pci_read_cfg4(adap, reg, &val);
610 /* Get the window based on base passed to it.
611 * Window aperture is currently unhandled, but there is no use case for it
614 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
619 if (is_t4(adap->params.chip)) {
622 /* Truncation intentional: we only read the bottom 32-bits of
623 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
624 * mechanism to read BAR0 instead of using
625 * pci_resource_start() because we could be operating from
626 * within a Virtual Machine which is trapping our accesses to
627 * our Configuration Space and we need to set up the PCI-E
628 * Memory Window decoders with the actual addresses which will
629 * be coming across the PCI-E link.
631 bar0 = t4_read_pcie_cfg4(adap, pci_base);
633 adap->t4_bar0 = bar0;
635 ret = bar0 + memwin_base;
637 /* For T5, only relative offset inside the PCIe BAR is passed */
643 /* Get the default utility window (win0) used by everyone */
644 u32 t4_get_util_window(struct adapter *adap)
646 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
647 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
650 /* Set up memory window for accessing adapter memory ranges. (Read
651 * back MA register to ensure that changes propagate before we attempt
652 * to use the new values.)
654 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
657 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
658 memwin_base | BIR_V(0) |
659 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
661 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
665 * t4_get_regs_len - return the size of the chips register set
666 * @adapter: the adapter
668 * Returns the size of the chip's BAR0 register space.
670 unsigned int t4_get_regs_len(struct adapter *adapter)
672 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
674 switch (chip_version) {
676 return T4_REGMAP_SIZE;
680 return T5_REGMAP_SIZE;
683 dev_err(adapter->pdev_dev,
684 "Unsupported chip version %d\n", chip_version);
689 * t4_get_regs - read chip registers into provided buffer
691 * @buf: register buffer
692 * @buf_size: size (in bytes) of register buffer
694 * If the provided register buffer isn't large enough for the chip's
695 * full register range, the register dump will be truncated to the
696 * register buffer's size.
698 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
700 static const unsigned int t4_reg_ranges[] = {
1158 static const unsigned int t5_reg_ranges[] = {
1933 static const unsigned int t6_reg_ranges[] = {
2510 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2511 const unsigned int *reg_ranges;
2512 int reg_ranges_size, range;
2513 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2515 /* Select the right set of register ranges to dump depending on the
2516 * adapter chip type.
2518 switch (chip_version) {
2520 reg_ranges = t4_reg_ranges;
2521 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2525 reg_ranges = t5_reg_ranges;
2526 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2530 reg_ranges = t6_reg_ranges;
2531 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2535 dev_err(adap->pdev_dev,
2536 "Unsupported chip version %d\n", chip_version);
2540 /* Clear the register buffer and insert the appropriate register
2541 * values selected by the above register ranges.
2543 memset(buf, 0, buf_size);
2544 for (range = 0; range < reg_ranges_size; range += 2) {
2545 unsigned int reg = reg_ranges[range];
2546 unsigned int last_reg = reg_ranges[range + 1];
2547 u32 *bufp = (u32 *)((char *)buf + reg);
2549 /* Iterate across the register range filling in the register
2550 * buffer but don't write past the end of the register buffer.
2552 while (reg <= last_reg && bufp < buf_end) {
2553 *bufp++ = t4_read_reg(adap, reg);
2559 #define EEPROM_STAT_ADDR 0x7bfc
2560 #define VPD_SIZE 0x800
2561 #define VPD_BASE 0x400
2562 #define VPD_BASE_OLD 0
2563 #define VPD_LEN 1024
2564 #define CHELSIO_VPD_UNIQUE_ID 0x82
2567 * t4_seeprom_wp - enable/disable EEPROM write protection
2568 * @adapter: the adapter
2569 * @enable: whether to enable or disable write protection
2571 * Enables or disables write protection on the serial EEPROM.
2573 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2575 unsigned int v = enable ? 0xc : 0;
2576 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2577 return ret < 0 ? ret : 0;
2581 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2582 * @adapter: adapter to read
2583 * @p: where to store the parameters
2585 * Reads card parameters stored in VPD EEPROM.
2587 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2589 int i, ret = 0, addr;
2592 unsigned int vpdr_len, kw_offset, id_len;
2594 vpd = vmalloc(VPD_LEN);
2598 /* We have two VPD data structures stored in the adapter VPD area.
2599 * By default, Linux calculates the size of the VPD area by traversing
2600 * the first VPD area at offset 0x0, so we need to tell the OS what
2601 * our real VPD size is.
2603 ret = pci_set_vpd_size(adapter->pdev, VPD_SIZE);
2607 /* Card information normally starts at VPD_BASE but early cards had
2610 ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
2614 /* The VPD shall have a unique identifier specified by the PCI SIG.
2615 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
2616 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
2617 * is expected to automatically put this entry at the
2618 * beginning of the VPD.
2620 addr = *vpd == CHELSIO_VPD_UNIQUE_ID ? VPD_BASE : VPD_BASE_OLD;
2622 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2626 if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2627 dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2632 id_len = pci_vpd_lrdt_size(vpd);
2633 if (id_len > ID_LEN)
2636 i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2638 dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2643 vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2644 kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2645 if (vpdr_len + kw_offset > VPD_LEN) {
2646 dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2651 #define FIND_VPD_KW(var, name) do { \
2652 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2654 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2658 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2661 FIND_VPD_KW(i, "RV");
2662 for (csum = 0; i >= 0; i--)
2666 dev_err(adapter->pdev_dev,
2667 "corrupted VPD EEPROM, actual csum %u\n", csum);
2672 FIND_VPD_KW(ec, "EC");
2673 FIND_VPD_KW(sn, "SN");
2674 FIND_VPD_KW(pn, "PN");
2675 FIND_VPD_KW(na, "NA");
2678 memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2680 memcpy(p->ec, vpd + ec, EC_LEN);
2682 i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2683 memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2685 i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2686 memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2688 memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2689 strim((char *)p->na);
2697 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2698 * @adapter: adapter to read
2699 * @p: where to store the parameters
2701 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2702 * Clock. This can only be called after a connection to the firmware
2705 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2707 u32 cclk_param, cclk_val;
2710 /* Grab the raw VPD parameters.
2712 ret = t4_get_raw_vpd_params(adapter, p);
2716 /* Ask firmware for the Core Clock since it knows how to translate the
2717 * Reference Clock ('V2') VPD field into a Core Clock value ...
2719 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2721 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2722 1, &cclk_param, &cclk_val);
2731 /* serial flash and firmware constants */
2733 SF_ATTEMPTS = 10, /* max retries for SF operations */
2735 /* flash command opcodes */
2736 SF_PROG_PAGE = 2, /* program page */
2737 SF_WR_DISABLE = 4, /* disable writes */
2738 SF_RD_STATUS = 5, /* read status register */
2739 SF_WR_ENABLE = 6, /* enable writes */
2740 SF_RD_DATA_FAST = 0xb, /* read flash */
2741 SF_RD_ID = 0x9f, /* read ID */
2742 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2744 FW_MAX_SIZE = 16 * SF_SEC_SIZE,
2748 * sf1_read - read data from the serial flash
2749 * @adapter: the adapter
2750 * @byte_cnt: number of bytes to read
2751 * @cont: whether another operation will be chained
2752 * @lock: whether to lock SF for PL access only
2753 * @valp: where to store the read data
2755 * Reads up to 4 bytes of data from the serial flash. The location of
2756 * the read needs to be specified prior to calling this by issuing the
2757 * appropriate commands to the serial flash.
2759 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2760 int lock, u32 *valp)
2764 if (!byte_cnt || byte_cnt > 4)
2766 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2768 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2769 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2770 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2772 *valp = t4_read_reg(adapter, SF_DATA_A);
2777 * sf1_write - write data to the serial flash
2778 * @adapter: the adapter
2779 * @byte_cnt: number of bytes to write
2780 * @cont: whether another operation will be chained
2781 * @lock: whether to lock SF for PL access only
2782 * @val: value to write
2784 * Writes up to 4 bytes of data to the serial flash. The location of
2785 * the write needs to be specified prior to calling this by issuing the
2786 * appropriate commands to the serial flash.
2788 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2791 if (!byte_cnt || byte_cnt > 4)
2793 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2795 t4_write_reg(adapter, SF_DATA_A, val);
2796 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2797 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2798 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2802 * flash_wait_op - wait for a flash operation to complete
2803 * @adapter: the adapter
2804 * @attempts: max number of polls of the status register
2805 * @delay: delay between polls in ms
2807 * Wait for a flash operation to complete by polling the status register.
2809 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2815 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2816 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2820 if (--attempts == 0)
2828 * t4_read_flash - read words from serial flash
2829 * @adapter: the adapter
2830 * @addr: the start address for the read
2831 * @nwords: how many 32-bit words to read
2832 * @data: where to store the read data
2833 * @byte_oriented: whether to store data as bytes or as words
2835 * Read the specified number of 32-bit words from the serial flash.
2836 * If @byte_oriented is set the read data is stored as a byte array
2837 * (i.e., big-endian), otherwise as 32-bit words in the platform's
2838 * natural endianness.
2840 int t4_read_flash(struct adapter *adapter, unsigned int addr,
2841 unsigned int nwords, u32 *data, int byte_oriented)
2845 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
2848 addr = swab32(addr) | SF_RD_DATA_FAST;
2850 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
2851 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
2854 for ( ; nwords; nwords--, data++) {
2855 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
2857 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2861 *data = (__force __u32)(cpu_to_be32(*data));
2867 * t4_write_flash - write up to a page of data to the serial flash
2868 * @adapter: the adapter
2869 * @addr: the start address to write
2870 * @n: length of data to write in bytes
2871 * @data: the data to write
2873 * Writes up to a page of data (256 bytes) to the serial flash starting
2874 * at the given address. All the data must be written to the same page.
2876 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
2877 unsigned int n, const u8 *data)
2881 unsigned int i, c, left, val, offset = addr & 0xff;
2883 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
2886 val = swab32(addr) | SF_PROG_PAGE;
2888 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
2889 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
2892 for (left = n; left; left -= c) {
2894 for (val = 0, i = 0; i < c; ++i)
2895 val = (val << 8) + *data++;
2897 ret = sf1_write(adapter, c, c != left, 1, val);
2901 ret = flash_wait_op(adapter, 8, 1);
2905 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2907 /* Read the page to verify the write succeeded */
2908 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
2912 if (memcmp(data - n, (u8 *)buf + offset, n)) {
2913 dev_err(adapter->pdev_dev,
2914 "failed to correctly write the flash page at %#x\n",
2921 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
2926 * t4_get_fw_version - read the firmware version
2927 * @adapter: the adapter
2928 * @vers: where to place the version
2930 * Reads the FW version from flash.
2932 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
2934 return t4_read_flash(adapter, FLASH_FW_START +
2935 offsetof(struct fw_hdr, fw_ver), 1,
2940 * t4_get_bs_version - read the firmware bootstrap version
2941 * @adapter: the adapter
2942 * @vers: where to place the version
2944 * Reads the FW Bootstrap version from flash.
2946 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
2948 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
2949 offsetof(struct fw_hdr, fw_ver), 1,
2954 * t4_get_tp_version - read the TP microcode version
2955 * @adapter: the adapter
2956 * @vers: where to place the version
2958 * Reads the TP microcode version from flash.
2960 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
2962 return t4_read_flash(adapter, FLASH_FW_START +
2963 offsetof(struct fw_hdr, tp_microcode_ver),
2968 * t4_get_exprom_version - return the Expansion ROM version (if any)
2969 * @adapter: the adapter
2970 * @vers: where to place the version
2972 * Reads the Expansion ROM header from FLASH and returns the version
2973 * number (if present) through the @vers return value pointer. We return
2974 * this in the Firmware Version Format since it's convenient. Return
2975 * 0 on success, -ENOENT if no Expansion ROM is present.
2977 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
2979 struct exprom_header {
2980 unsigned char hdr_arr[16]; /* must start with 0x55aa */
2981 unsigned char hdr_ver[4]; /* Expansion ROM version */
2983 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
2987 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
2988 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
2993 hdr = (struct exprom_header *)exprom_header_buf;
2994 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
2997 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
2998 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
2999 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3000 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3005 * t4_check_fw_version - check if the FW is supported with this driver
3006 * @adap: the adapter
3008 * Checks if an adapter's FW is compatible with the driver. Returns 0
3009 * if there's exact match, a negative error if the version could not be
3010 * read or there's a major version mismatch
3012 int t4_check_fw_version(struct adapter *adap)
3014 int i, ret, major, minor, micro;
3015 int exp_major, exp_minor, exp_micro;
3016 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3018 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3019 /* Try multiple times before returning error */
3020 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3021 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3026 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3027 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3028 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3030 switch (chip_version) {
3032 exp_major = T4FW_MIN_VERSION_MAJOR;
3033 exp_minor = T4FW_MIN_VERSION_MINOR;
3034 exp_micro = T4FW_MIN_VERSION_MICRO;
3037 exp_major = T5FW_MIN_VERSION_MAJOR;
3038 exp_minor = T5FW_MIN_VERSION_MINOR;
3039 exp_micro = T5FW_MIN_VERSION_MICRO;
3042 exp_major = T6FW_MIN_VERSION_MAJOR;
3043 exp_minor = T6FW_MIN_VERSION_MINOR;
3044 exp_micro = T6FW_MIN_VERSION_MICRO;
3047 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3052 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3053 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3054 dev_err(adap->pdev_dev,
3055 "Card has firmware version %u.%u.%u, minimum "
3056 "supported firmware is %u.%u.%u.\n", major, minor,
3057 micro, exp_major, exp_minor, exp_micro);
3063 /* Is the given firmware API compatible with the one the driver was compiled
3066 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3069 /* short circuit if it's the exact same firmware version */
3070 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3073 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3074 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3075 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3082 /* The firmware in the filesystem is usable, but should it be installed?
3083 * This routine explains itself in detail if it indicates the filesystem
3084 * firmware should be installed.
3086 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3091 if (!card_fw_usable) {
3092 reason = "incompatible or unusable";
3097 reason = "older than the version supported with this driver";
3104 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3105 "installing firmware %u.%u.%u.%u on card.\n",
3106 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3107 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3108 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3109 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3114 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3115 const u8 *fw_data, unsigned int fw_size,
3116 struct fw_hdr *card_fw, enum dev_state state,
3119 int ret, card_fw_usable, fs_fw_usable;
3120 const struct fw_hdr *fs_fw;
3121 const struct fw_hdr *drv_fw;
3123 drv_fw = &fw_info->fw_hdr;
3125 /* Read the header of the firmware on the card */
3126 ret = -t4_read_flash(adap, FLASH_FW_START,
3127 sizeof(*card_fw) / sizeof(uint32_t),
3128 (uint32_t *)card_fw, 1);
3130 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3132 dev_err(adap->pdev_dev,
3133 "Unable to read card's firmware header: %d\n", ret);
3137 if (fw_data != NULL) {
3138 fs_fw = (const void *)fw_data;
3139 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3145 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3146 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3147 /* Common case: the firmware on the card is an exact match and
3148 * the filesystem one is an exact match too, or the filesystem
3149 * one is absent/incompatible.
3151 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3152 should_install_fs_fw(adap, card_fw_usable,
3153 be32_to_cpu(fs_fw->fw_ver),
3154 be32_to_cpu(card_fw->fw_ver))) {
3155 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data,
3158 dev_err(adap->pdev_dev,
3159 "failed to install firmware: %d\n", ret);
3163 /* Installed successfully, update the cached header too. */
3166 *reset = 0; /* already reset as part of load_fw */
3169 if (!card_fw_usable) {
3172 d = be32_to_cpu(drv_fw->fw_ver);
3173 c = be32_to_cpu(card_fw->fw_ver);
3174 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3176 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3178 "driver compiled with %d.%d.%d.%d, "
3179 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3181 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3182 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3183 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3184 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3185 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3186 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3191 /* We're using whatever's on the card and it's known to be good. */
3192 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3193 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3200 * t4_flash_erase_sectors - erase a range of flash sectors
3201 * @adapter: the adapter
3202 * @start: the first sector to erase
3203 * @end: the last sector to erase
3205 * Erases the sectors in the given inclusive range.
3207 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3211 if (end >= adapter->params.sf_nsec)
3214 while (start <= end) {
3215 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3216 (ret = sf1_write(adapter, 4, 0, 1,
3217 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3218 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3219 dev_err(adapter->pdev_dev,
3220 "erase of flash sector %d failed, error %d\n",
3226 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3231 * t4_flash_cfg_addr - return the address of the flash configuration file
3232 * @adapter: the adapter
3234 * Return the address within the flash where the Firmware Configuration
3237 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3239 if (adapter->params.sf_size == 0x100000)
3240 return FLASH_FPGA_CFG_START;
3242 return FLASH_CFG_START;
3245 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3246 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3247 * and emit an error message for mismatched firmware to save our caller the
3250 static bool t4_fw_matches_chip(const struct adapter *adap,
3251 const struct fw_hdr *hdr)
3253 /* The expression below will return FALSE for any unsupported adapter
3254 * which will keep us "honest" in the future ...
3256 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3257 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3258 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3261 dev_err(adap->pdev_dev,
3262 "FW image (%d) is not suitable for this adapter (%d)\n",
3263 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3268 * t4_load_fw - download firmware
3269 * @adap: the adapter
3270 * @fw_data: the firmware image to write
3273 * Write the supplied firmware image to the card's serial flash.
3275 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3280 u8 first_page[SF_PAGE_SIZE];
3281 const __be32 *p = (const __be32 *)fw_data;
3282 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3283 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3284 unsigned int fw_img_start = adap->params.sf_fw_start;
3285 unsigned int fw_start_sec = fw_img_start / sf_sec_size;
3288 dev_err(adap->pdev_dev, "FW image has no data\n");
3292 dev_err(adap->pdev_dev,
3293 "FW image size not multiple of 512 bytes\n");
3296 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3297 dev_err(adap->pdev_dev,
3298 "FW image size differs from size in FW header\n");
3301 if (size > FW_MAX_SIZE) {
3302 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3306 if (!t4_fw_matches_chip(adap, hdr))
3309 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3310 csum += be32_to_cpu(p[i]);
3312 if (csum != 0xffffffff) {
3313 dev_err(adap->pdev_dev,
3314 "corrupted firmware image, checksum %#x\n", csum);
3318 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3319 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3324 * We write the correct version at the end so the driver can see a bad
3325 * version if the FW write fails. Start by writing a copy of the
3326 * first page with a bad version.
3328 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3329 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3330 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
3334 addr = fw_img_start;
3335 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3336 addr += SF_PAGE_SIZE;
3337 fw_data += SF_PAGE_SIZE;
3338 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
3343 ret = t4_write_flash(adap,
3344 fw_img_start + offsetof(struct fw_hdr, fw_ver),
3345 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
3348 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3351 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3356 * t4_phy_fw_ver - return current PHY firmware version
3357 * @adap: the adapter
3358 * @phy_fw_ver: return value buffer for PHY firmware version
3360 * Returns the current version of external PHY firmware on the
3363 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3368 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3369 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3370 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3371 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3372 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3381 * t4_load_phy_fw - download port PHY firmware
3382 * @adap: the adapter
3383 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3384 * @win_lock: the lock to use to guard the memory copy
3385 * @phy_fw_version: function to check PHY firmware versions
3386 * @phy_fw_data: the PHY firmware image to write
3387 * @phy_fw_size: image size
3389 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3390 * @phy_fw_version is supplied, then it will be used to determine if
3391 * it's necessary to perform the transfer by comparing the version
3392 * of any existing adapter PHY firmware with that of the passed in
3393 * PHY firmware image. If @win_lock is non-NULL then it will be used
3394 * around the call to t4_memory_rw() which transfers the PHY firmware
3397 * A negative error number will be returned if an error occurs. If
3398 * version number support is available and there's no need to upgrade
3399 * the firmware, 0 will be returned. If firmware is successfully
3400 * transferred to the adapter, 1 will be retured.
3402 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3403 * a result, a RESET of the adapter would cause that RAM to lose its
3404 * contents. Thus, loading PHY firmware on such adapters must happen
3405 * after any FW_RESET_CMDs ...
3407 int t4_load_phy_fw(struct adapter *adap,
3408 int win, spinlock_t *win_lock,
3409 int (*phy_fw_version)(const u8 *, size_t),
3410 const u8 *phy_fw_data, size_t phy_fw_size)
3412 unsigned long mtype = 0, maddr = 0;
3414 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3417 /* If we have version number support, then check to see if the adapter
3418 * already has up-to-date PHY firmware loaded.
3420 if (phy_fw_version) {
3421 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3422 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3426 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3427 CH_WARN(adap, "PHY Firmware already up-to-date, "
3428 "version %#x\n", cur_phy_fw_ver);
3433 /* Ask the firmware where it wants us to copy the PHY firmware image.
3434 * The size of the file requires a special version of the READ coommand
3435 * which will pass the file size via the values field in PARAMS_CMD and
3436 * retrieve the return value from firmware and place it in the same
3439 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3440 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3441 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3442 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3444 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3449 maddr = (val & 0xff) << 16;
3451 /* Copy the supplied PHY Firmware image to the adapter memory location
3452 * allocated by the adapter firmware.
3455 spin_lock_bh(win_lock);
3456 ret = t4_memory_rw(adap, win, mtype, maddr,
3457 phy_fw_size, (__be32 *)phy_fw_data,
3460 spin_unlock_bh(win_lock);
3464 /* Tell the firmware that the PHY firmware image has been written to
3465 * RAM and it can now start copying it over to the PHYs. The chip
3466 * firmware will RESET the affected PHYs as part of this operation
3467 * leaving them running the new PHY firmware image.
3469 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3470 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3471 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3472 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3473 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3474 ¶m, &val, 30000);
3476 /* If we have version number support, then check to see that the new
3477 * firmware got loaded properly.
3479 if (phy_fw_version) {
3480 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3484 if (cur_phy_fw_ver != new_phy_fw_vers) {
3485 CH_WARN(adap, "PHY Firmware did not update: "
3486 "version on adapter %#x, "
3487 "version flashed %#x\n",
3488 cur_phy_fw_ver, new_phy_fw_vers);
3497 * t4_fwcache - firmware cache operation
3498 * @adap: the adapter
3499 * @op : the operation (flush or flush and invalidate)
3501 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3503 struct fw_params_cmd c;
3505 memset(&c, 0, sizeof(c));
3507 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3508 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3509 FW_PARAMS_CMD_PFN_V(adap->pf) |
3510 FW_PARAMS_CMD_VFN_V(0));
3511 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3513 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3514 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3515 c.param[0].val = (__force __be32)op;
3517 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3520 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3521 unsigned int *pif_req_wrptr,
3522 unsigned int *pif_rsp_wrptr)
3525 u32 cfg, val, req, rsp;
3527 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3528 if (cfg & LADBGEN_F)
3529 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3531 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3532 req = POLADBGWRPTR_G(val);
3533 rsp = PILADBGWRPTR_G(val);
3535 *pif_req_wrptr = req;
3537 *pif_rsp_wrptr = rsp;
3539 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3540 for (j = 0; j < 6; j++) {
3541 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3542 PILADBGRDPTR_V(rsp));
3543 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3544 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3548 req = (req + 2) & POLADBGRDPTR_M;
3549 rsp = (rsp + 2) & PILADBGRDPTR_M;
3551 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3554 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3559 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3560 if (cfg & LADBGEN_F)
3561 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3563 for (i = 0; i < CIM_MALA_SIZE; i++) {
3564 for (j = 0; j < 5; j++) {
3566 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3567 PILADBGRDPTR_V(idx));
3568 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3569 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3572 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3575 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3579 for (i = 0; i < 8; i++) {
3580 u32 *p = la_buf + i;
3582 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3583 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3584 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3585 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3586 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3590 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
3591 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
3595 * t4_link_l1cfg - apply link configuration to MAC/PHY
3596 * @phy: the PHY to setup
3597 * @mac: the MAC to setup
3598 * @lc: the requested link configuration
3600 * Set up a port's MAC and PHY according to a desired link configuration.
3601 * - If the PHY can auto-negotiate first decide what to advertise, then
3602 * enable/disable auto-negotiation as desired, and reset.
3603 * - If the PHY does not auto-negotiate just reset it.
3604 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
3605 * otherwise do it later based on the outcome of auto-negotiation.
3607 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
3608 struct link_config *lc)
3610 struct fw_port_cmd c;
3611 unsigned int fc = 0, mdi = FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO);
3614 if (lc->requested_fc & PAUSE_RX)
3615 fc |= FW_PORT_CAP_FC_RX;
3616 if (lc->requested_fc & PAUSE_TX)
3617 fc |= FW_PORT_CAP_FC_TX;
3619 memset(&c, 0, sizeof(c));
3620 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3621 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3622 FW_PORT_CMD_PORTID_V(port));
3624 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3627 if (!(lc->supported & FW_PORT_CAP_ANEG)) {
3628 c.u.l1cfg.rcap = cpu_to_be32((lc->supported & ADVERT_MASK) |
3630 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3631 } else if (lc->autoneg == AUTONEG_DISABLE) {
3632 c.u.l1cfg.rcap = cpu_to_be32(lc->requested_speed | fc | mdi);
3633 lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
3635 c.u.l1cfg.rcap = cpu_to_be32(lc->advertising | fc | mdi);
3637 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3641 * t4_restart_aneg - restart autonegotiation
3642 * @adap: the adapter
3643 * @mbox: mbox to use for the FW command
3644 * @port: the port id
3646 * Restarts autonegotiation for the selected port.
3648 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
3650 struct fw_port_cmd c;
3652 memset(&c, 0, sizeof(c));
3653 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
3654 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
3655 FW_PORT_CMD_PORTID_V(port));
3657 cpu_to_be32(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG) |
3659 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
3660 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
3663 typedef void (*int_handler_t)(struct adapter *adap);
3666 unsigned int mask; /* bits to check in interrupt status */
3667 const char *msg; /* message to print or NULL */
3668 short stat_idx; /* stat counter to increment or -1 */
3669 unsigned short fatal; /* whether the condition reported is fatal */
3670 int_handler_t int_handler; /* platform-specific int handler */
3674 * t4_handle_intr_status - table driven interrupt handler
3675 * @adapter: the adapter that generated the interrupt
3676 * @reg: the interrupt status register to process
3677 * @acts: table of interrupt actions
3679 * A table driven interrupt handler that applies a set of masks to an
3680 * interrupt status word and performs the corresponding actions if the
3681 * interrupts described by the mask have occurred. The actions include
3682 * optionally emitting a warning or alert message. The table is terminated
3683 * by an entry specifying mask 0. Returns the number of fatal interrupt
3686 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
3687 const struct intr_info *acts)
3690 unsigned int mask = 0;
3691 unsigned int status = t4_read_reg(adapter, reg);
3693 for ( ; acts->mask; ++acts) {
3694 if (!(status & acts->mask))
3698 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3699 status & acts->mask);
3700 } else if (acts->msg && printk_ratelimit())
3701 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
3702 status & acts->mask);
3703 if (acts->int_handler)
3704 acts->int_handler(adapter);
3708 if (status) /* clear processed interrupts */
3709 t4_write_reg(adapter, reg, status);
3714 * Interrupt handler for the PCIE module.
3716 static void pcie_intr_handler(struct adapter *adapter)
3718 static const struct intr_info sysbus_intr_info[] = {
3719 { RNPP_F, "RXNP array parity error", -1, 1 },
3720 { RPCP_F, "RXPC array parity error", -1, 1 },
3721 { RCIP_F, "RXCIF array parity error", -1, 1 },
3722 { RCCP_F, "Rx completions control array parity error", -1, 1 },
3723 { RFTP_F, "RXFT array parity error", -1, 1 },
3726 static const struct intr_info pcie_port_intr_info[] = {
3727 { TPCP_F, "TXPC array parity error", -1, 1 },
3728 { TNPP_F, "TXNP array parity error", -1, 1 },
3729 { TFTP_F, "TXFT array parity error", -1, 1 },
3730 { TCAP_F, "TXCA array parity error", -1, 1 },
3731 { TCIP_F, "TXCIF array parity error", -1, 1 },
3732 { RCAP_F, "RXCA array parity error", -1, 1 },
3733 { OTDD_F, "outbound request TLP discarded", -1, 1 },
3734 { RDPE_F, "Rx data parity error", -1, 1 },
3735 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
3738 static const struct intr_info pcie_intr_info[] = {
3739 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
3740 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
3741 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
3742 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3743 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3744 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3745 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3746 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
3747 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
3748 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3749 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
3750 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3751 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3752 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
3753 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3754 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3755 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
3756 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3757 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3758 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3759 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3760 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
3761 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
3762 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3763 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
3764 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
3765 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
3766 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
3767 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
3768 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
3773 static struct intr_info t5_pcie_intr_info[] = {
3774 { MSTGRPPERR_F, "Master Response Read Queue parity error",
3776 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
3777 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
3778 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
3779 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
3780 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
3781 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
3782 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
3784 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
3786 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
3787 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
3788 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
3789 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
3790 { DREQWRPERR_F, "PCI DMA channel write request parity error",
3792 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
3793 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
3794 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
3795 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
3796 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
3797 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
3798 { FIDPERR_F, "PCI FID parity error", -1, 1 },
3799 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
3800 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
3801 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
3802 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
3804 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
3806 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
3807 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
3808 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
3809 { READRSPERR_F, "Outbound read error", -1, 0 },
3815 if (is_t4(adapter->params.chip))
3816 fat = t4_handle_intr_status(adapter,
3817 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
3819 t4_handle_intr_status(adapter,
3820 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
3821 pcie_port_intr_info) +
3822 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3825 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
3829 t4_fatal_err(adapter);
3833 * TP interrupt handler.
3835 static void tp_intr_handler(struct adapter *adapter)
3837 static const struct intr_info tp_intr_info[] = {
3838 { 0x3fffffff, "TP parity error", -1, 1 },
3839 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
3843 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
3844 t4_fatal_err(adapter);
3848 * SGE interrupt handler.
3850 static void sge_intr_handler(struct adapter *adapter)
3855 static const struct intr_info sge_intr_info[] = {
3856 { ERR_CPL_EXCEED_IQE_SIZE_F,
3857 "SGE received CPL exceeding IQE size", -1, 1 },
3858 { ERR_INVALID_CIDX_INC_F,
3859 "SGE GTS CIDX increment too large", -1, 0 },
3860 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
3861 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
3862 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
3863 "SGE IQID > 1023 received CPL for FL", -1, 0 },
3864 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
3866 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
3868 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
3870 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
3872 { ERR_ING_CTXT_PRIO_F,
3873 "SGE too many priority ingress contexts", -1, 0 },
3874 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
3875 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
3879 static struct intr_info t4t5_sge_intr_info[] = {
3880 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
3881 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
3882 { ERR_EGR_CTXT_PRIO_F,
3883 "SGE too many priority egress contexts", -1, 0 },
3887 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) |
3888 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32);
3890 dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
3891 (unsigned long long)v);
3892 t4_write_reg(adapter, SGE_INT_CAUSE1_A, v);
3893 t4_write_reg(adapter, SGE_INT_CAUSE2_A, v >> 32);
3896 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
3897 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
3898 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
3899 t4t5_sge_intr_info);
3901 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
3902 if (err & ERROR_QID_VALID_F) {
3903 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
3905 if (err & UNCAPTURED_ERROR_F)
3906 dev_err(adapter->pdev_dev,
3907 "SGE UNCAPTURED_ERROR set (clearing)\n");
3908 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
3909 UNCAPTURED_ERROR_F);
3913 t4_fatal_err(adapter);
3916 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
3917 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
3918 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
3919 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
3922 * CIM interrupt handler.
3924 static void cim_intr_handler(struct adapter *adapter)
3926 static const struct intr_info cim_intr_info[] = {
3927 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
3928 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
3929 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
3930 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
3931 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
3932 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
3933 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
3936 static const struct intr_info cim_upintr_info[] = {
3937 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
3938 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
3939 { ILLWRINT_F, "CIM illegal write", -1, 1 },
3940 { ILLRDINT_F, "CIM illegal read", -1, 1 },
3941 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
3942 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
3943 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
3944 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
3945 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
3946 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
3947 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
3948 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
3949 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
3950 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
3951 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
3952 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
3953 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
3954 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
3955 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
3956 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
3957 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
3958 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
3959 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
3960 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
3961 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
3962 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
3963 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
3964 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
3970 if (t4_read_reg(adapter, PCIE_FW_A) & PCIE_FW_ERR_F)
3971 t4_report_fw_error(adapter);
3973 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
3975 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
3978 t4_fatal_err(adapter);
3982 * ULP RX interrupt handler.
3984 static void ulprx_intr_handler(struct adapter *adapter)
3986 static const struct intr_info ulprx_intr_info[] = {
3987 { 0x1800000, "ULPRX context error", -1, 1 },
3988 { 0x7fffff, "ULPRX parity error", -1, 1 },
3992 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
3993 t4_fatal_err(adapter);
3997 * ULP TX interrupt handler.
3999 static void ulptx_intr_handler(struct adapter *adapter)
4001 static const struct intr_info ulptx_intr_info[] = {
4002 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4004 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4006 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4008 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4010 { 0xfffffff, "ULPTX parity error", -1, 1 },
4014 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4015 t4_fatal_err(adapter);
4019 * PM TX interrupt handler.
4021 static void pmtx_intr_handler(struct adapter *adapter)
4023 static const struct intr_info pmtx_intr_info[] = {
4024 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4025 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4026 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4027 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4028 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4029 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4030 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4032 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4033 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4037 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4038 t4_fatal_err(adapter);
4042 * PM RX interrupt handler.
4044 static void pmrx_intr_handler(struct adapter *adapter)
4046 static const struct intr_info pmrx_intr_info[] = {
4047 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4048 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4049 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4050 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4052 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4053 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4057 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4058 t4_fatal_err(adapter);
4062 * CPL switch interrupt handler.
4064 static void cplsw_intr_handler(struct adapter *adapter)
4066 static const struct intr_info cplsw_intr_info[] = {
4067 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4068 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4069 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4070 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4071 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4072 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4076 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4077 t4_fatal_err(adapter);
4081 * LE interrupt handler.
4083 static void le_intr_handler(struct adapter *adap)
4085 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4086 static const struct intr_info le_intr_info[] = {
4087 { LIPMISS_F, "LE LIP miss", -1, 0 },
4088 { LIP0_F, "LE 0 LIP error", -1, 0 },
4089 { PARITYERR_F, "LE parity error", -1, 1 },
4090 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4091 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4095 static struct intr_info t6_le_intr_info[] = {
4096 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4097 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4098 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4099 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4100 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4104 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4105 (chip <= CHELSIO_T5) ?
4106 le_intr_info : t6_le_intr_info))
4111 * MPS interrupt handler.
4113 static void mps_intr_handler(struct adapter *adapter)
4115 static const struct intr_info mps_rx_intr_info[] = {
4116 { 0xffffff, "MPS Rx parity error", -1, 1 },
4119 static const struct intr_info mps_tx_intr_info[] = {
4120 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4121 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4122 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4124 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4126 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4127 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4128 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4131 static const struct intr_info mps_trc_intr_info[] = {
4132 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4133 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4135 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4138 static const struct intr_info mps_stat_sram_intr_info[] = {
4139 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4142 static const struct intr_info mps_stat_tx_intr_info[] = {
4143 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4146 static const struct intr_info mps_stat_rx_intr_info[] = {
4147 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4150 static const struct intr_info mps_cls_intr_info[] = {
4151 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4152 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4153 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4159 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4161 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4163 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4164 mps_trc_intr_info) +
4165 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4166 mps_stat_sram_intr_info) +
4167 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4168 mps_stat_tx_intr_info) +
4169 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4170 mps_stat_rx_intr_info) +
4171 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4174 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4175 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4177 t4_fatal_err(adapter);
4180 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4184 * EDC/MC interrupt handler.
4186 static void mem_intr_handler(struct adapter *adapter, int idx)
4188 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4190 unsigned int addr, cnt_addr, v;
4192 if (idx <= MEM_EDC1) {
4193 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4194 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4195 } else if (idx == MEM_MC) {
4196 if (is_t4(adapter->params.chip)) {
4197 addr = MC_INT_CAUSE_A;
4198 cnt_addr = MC_ECC_STATUS_A;
4200 addr = MC_P_INT_CAUSE_A;
4201 cnt_addr = MC_P_ECC_STATUS_A;
4204 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4205 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4208 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4209 if (v & PERR_INT_CAUSE_F)
4210 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4212 if (v & ECC_CE_INT_CAUSE_F) {
4213 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4215 t4_edc_err_read(adapter, idx);
4217 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4218 if (printk_ratelimit())
4219 dev_warn(adapter->pdev_dev,
4220 "%u %s correctable ECC data error%s\n",
4221 cnt, name[idx], cnt > 1 ? "s" : "");
4223 if (v & ECC_UE_INT_CAUSE_F)
4224 dev_alert(adapter->pdev_dev,
4225 "%s uncorrectable ECC data error\n", name[idx]);
4227 t4_write_reg(adapter, addr, v);
4228 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4229 t4_fatal_err(adapter);
4233 * MA interrupt handler.
4235 static void ma_intr_handler(struct adapter *adap)
4237 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4239 if (status & MEM_PERR_INT_CAUSE_F) {
4240 dev_alert(adap->pdev_dev,
4241 "MA parity error, parity status %#x\n",
4242 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4243 if (is_t5(adap->params.chip))
4244 dev_alert(adap->pdev_dev,
4245 "MA parity error, parity status %#x\n",
4247 MA_PARITY_ERROR_STATUS2_A));
4249 if (status & MEM_WRAP_INT_CAUSE_F) {
4250 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4251 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4252 "client %u to address %#x\n",
4253 MEM_WRAP_CLIENT_NUM_G(v),
4254 MEM_WRAP_ADDRESS_G(v) << 4);
4256 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4261 * SMB interrupt handler.
4263 static void smb_intr_handler(struct adapter *adap)
4265 static const struct intr_info smb_intr_info[] = {
4266 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4267 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4268 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4272 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4277 * NC-SI interrupt handler.
4279 static void ncsi_intr_handler(struct adapter *adap)
4281 static const struct intr_info ncsi_intr_info[] = {
4282 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4283 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4284 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4285 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4289 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4294 * XGMAC interrupt handler.
4296 static void xgmac_intr_handler(struct adapter *adap, int port)
4298 u32 v, int_cause_reg;
4300 if (is_t4(adap->params.chip))
4301 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4303 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4305 v = t4_read_reg(adap, int_cause_reg);
4307 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4311 if (v & TXFIFO_PRTY_ERR_F)
4312 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4314 if (v & RXFIFO_PRTY_ERR_F)
4315 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4317 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4322 * PL interrupt handler.
4324 static void pl_intr_handler(struct adapter *adap)
4326 static const struct intr_info pl_intr_info[] = {
4327 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4328 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4332 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4336 #define PF_INTR_MASK (PFSW_F)
4337 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4338 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4339 CPL_SWITCH_F | SGE_F | ULP_TX_F)
4342 * t4_slow_intr_handler - control path interrupt handler
4343 * @adapter: the adapter
4345 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4346 * The designation 'slow' is because it involves register reads, while
4347 * data interrupts typically don't involve any MMIOs.
4349 int t4_slow_intr_handler(struct adapter *adapter)
4351 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
4353 if (!(cause & GLBL_INTR_MASK))
4356 cim_intr_handler(adapter);
4358 mps_intr_handler(adapter);
4360 ncsi_intr_handler(adapter);
4362 pl_intr_handler(adapter);
4364 smb_intr_handler(adapter);
4365 if (cause & XGMAC0_F)
4366 xgmac_intr_handler(adapter, 0);
4367 if (cause & XGMAC1_F)
4368 xgmac_intr_handler(adapter, 1);
4369 if (cause & XGMAC_KR0_F)
4370 xgmac_intr_handler(adapter, 2);
4371 if (cause & XGMAC_KR1_F)
4372 xgmac_intr_handler(adapter, 3);
4374 pcie_intr_handler(adapter);
4376 mem_intr_handler(adapter, MEM_MC);
4377 if (is_t5(adapter->params.chip) && (cause & MC1_F))
4378 mem_intr_handler(adapter, MEM_MC1);
4380 mem_intr_handler(adapter, MEM_EDC0);
4382 mem_intr_handler(adapter, MEM_EDC1);
4384 le_intr_handler(adapter);
4386 tp_intr_handler(adapter);
4388 ma_intr_handler(adapter);
4389 if (cause & PM_TX_F)
4390 pmtx_intr_handler(adapter);
4391 if (cause & PM_RX_F)
4392 pmrx_intr_handler(adapter);
4393 if (cause & ULP_RX_F)
4394 ulprx_intr_handler(adapter);
4395 if (cause & CPL_SWITCH_F)
4396 cplsw_intr_handler(adapter);
4398 sge_intr_handler(adapter);
4399 if (cause & ULP_TX_F)
4400 ulptx_intr_handler(adapter);
4402 /* Clear the interrupts just processed for which we are the master. */
4403 t4_write_reg(adapter, PL_INT_CAUSE_A, cause & GLBL_INTR_MASK);
4404 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
4409 * t4_intr_enable - enable interrupts
4410 * @adapter: the adapter whose interrupts should be enabled
4412 * Enable PF-specific interrupts for the calling function and the top-level
4413 * interrupt concentrator for global interrupts. Interrupts are already
4414 * enabled at each module, here we just enable the roots of the interrupt
4417 * Note: this function should be called only when the driver manages
4418 * non PF-specific interrupts from the various HW modules. Only one PCI
4419 * function at a time should be doing this.
4421 void t4_intr_enable(struct adapter *adapter)
4424 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4425 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4426 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4428 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4429 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
4430 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
4431 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
4432 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
4433 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
4434 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
4435 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
4436 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
4437 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
4438 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
4442 * t4_intr_disable - disable interrupts
4443 * @adapter: the adapter whose interrupts should be disabled
4445 * Disable interrupts. We only disable the top-level interrupt
4446 * concentrators. The caller must be a PCI function managing global
4449 void t4_intr_disable(struct adapter *adapter)
4451 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
4452 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
4453 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
4455 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
4456 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
4460 * t4_config_rss_range - configure a portion of the RSS mapping table
4461 * @adapter: the adapter
4462 * @mbox: mbox to use for the FW command
4463 * @viid: virtual interface whose RSS subtable is to be written
4464 * @start: start entry in the table to write
4465 * @n: how many table entries to write
4466 * @rspq: values for the response queue lookup table
4467 * @nrspq: number of values in @rspq
4469 * Programs the selected part of the VI's RSS mapping table with the
4470 * provided values. If @nrspq < @n the supplied values are used repeatedly
4471 * until the full table range is populated.
4473 * The caller must ensure the values in @rspq are in the range allowed for
4476 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
4477 int start, int n, const u16 *rspq, unsigned int nrspq)
4480 const u16 *rsp = rspq;
4481 const u16 *rsp_end = rspq + nrspq;
4482 struct fw_rss_ind_tbl_cmd cmd;
4484 memset(&cmd, 0, sizeof(cmd));
4485 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
4486 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4487 FW_RSS_IND_TBL_CMD_VIID_V(viid));
4488 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
4490 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
4492 int nq = min(n, 32);
4493 __be32 *qp = &cmd.iq0_to_iq2;
4495 cmd.niqid = cpu_to_be16(nq);
4496 cmd.startidx = cpu_to_be16(start);
4504 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
4505 if (++rsp >= rsp_end)
4507 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
4508 if (++rsp >= rsp_end)
4510 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
4511 if (++rsp >= rsp_end)
4514 *qp++ = cpu_to_be32(v);
4518 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
4526 * t4_config_glbl_rss - configure the global RSS mode
4527 * @adapter: the adapter
4528 * @mbox: mbox to use for the FW command
4529 * @mode: global RSS mode
4530 * @flags: mode-specific flags
4532 * Sets the global RSS mode.
4534 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
4537 struct fw_rss_glb_config_cmd c;
4539 memset(&c, 0, sizeof(c));
4540 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
4541 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
4542 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4543 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
4544 c.u.manual.mode_pkd =
4545 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4546 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
4547 c.u.basicvirtual.mode_pkd =
4548 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
4549 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
4552 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4556 * t4_config_vi_rss - configure per VI RSS settings
4557 * @adapter: the adapter
4558 * @mbox: mbox to use for the FW command
4561 * @defq: id of the default RSS queue for the VI.
4563 * Configures VI-specific RSS properties.
4565 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
4566 unsigned int flags, unsigned int defq)
4568 struct fw_rss_vi_config_cmd c;
4570 memset(&c, 0, sizeof(c));
4571 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
4572 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
4573 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
4574 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
4575 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
4576 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
4577 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
4580 /* Read an RSS table row */
4581 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
4583 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
4584 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
4589 * t4_read_rss - read the contents of the RSS mapping table
4590 * @adapter: the adapter
4591 * @map: holds the contents of the RSS mapping table
4593 * Reads the contents of the RSS hash->queue mapping table.
4595 int t4_read_rss(struct adapter *adapter, u16 *map)
4600 for (i = 0; i < RSS_NENTRIES / 2; ++i) {
4601 ret = rd_rss_row(adapter, i, &val);
4604 *map++ = LKPTBLQUEUE0_G(val);
4605 *map++ = LKPTBLQUEUE1_G(val);
4610 static unsigned int t4_use_ldst(struct adapter *adap)
4612 return (adap->flags & FW_OK) || !adap->use_bd;
4616 * t4_fw_tp_pio_rw - Access TP PIO through LDST
4617 * @adap: the adapter
4618 * @vals: where the indirect register values are stored/written
4619 * @nregs: how many indirect registers to read/write
4620 * @start_idx: index of first indirect register to read/write
4621 * @rw: Read (1) or Write (0)
4623 * Access TP PIO registers through LDST
4625 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs,
4626 unsigned int start_index, unsigned int rw)
4629 int cmd = FW_LDST_ADDRSPC_TP_PIO;
4630 struct fw_ldst_cmd c;
4632 for (i = 0 ; i < nregs; i++) {
4633 memset(&c, 0, sizeof(c));
4634 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
4636 (rw ? FW_CMD_READ_F :
4638 FW_LDST_CMD_ADDRSPACE_V(cmd));
4639 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
4641 c.u.addrval.addr = cpu_to_be32(start_index + i);
4642 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
4643 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c);
4645 vals[i] = be32_to_cpu(c.u.addrval.val);
4650 * t4_read_rss_key - read the global RSS key
4651 * @adap: the adapter
4652 * @key: 10-entry array holding the 320-bit RSS key
4654 * Reads the global 320-bit RSS key.
4656 void t4_read_rss_key(struct adapter *adap, u32 *key)
4658 if (t4_use_ldst(adap))
4659 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1);
4661 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4662 TP_RSS_SECRET_KEY0_A);
4666 * t4_write_rss_key - program one of the RSS keys
4667 * @adap: the adapter
4668 * @key: 10-entry array holding the 320-bit RSS key
4669 * @idx: which RSS key to write
4671 * Writes one of the RSS keys with the given 320-bit value. If @idx is
4672 * 0..15 the corresponding entry in the RSS key table is written,
4673 * otherwise the global RSS key is written.
4675 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx)
4677 u8 rss_key_addr_cnt = 16;
4678 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
4680 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
4681 * allows access to key addresses 16-63 by using KeyWrAddrX
4682 * as index[5:4](upper 2) into key table
4684 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
4685 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
4686 rss_key_addr_cnt = 32;
4688 if (t4_use_ldst(adap))
4689 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0);
4691 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10,
4692 TP_RSS_SECRET_KEY0_A);
4694 if (idx >= 0 && idx < rss_key_addr_cnt) {
4695 if (rss_key_addr_cnt > 16)
4696 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4697 KEYWRADDRX_V(idx >> 4) |
4698 T6_VFWRADDR_V(idx) | KEYWREN_F);
4700 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
4701 KEYWRADDR_V(idx) | KEYWREN_F);
4706 * t4_read_rss_pf_config - read PF RSS Configuration Table
4707 * @adapter: the adapter
4708 * @index: the entry in the PF RSS table to read
4709 * @valp: where to store the returned value
4711 * Reads the PF RSS Configuration Table at the specified index and returns
4712 * the value found there.
4714 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
4717 if (t4_use_ldst(adapter))
4718 t4_fw_tp_pio_rw(adapter, valp, 1,
4719 TP_RSS_PF0_CONFIG_A + index, 1);
4721 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4722 valp, 1, TP_RSS_PF0_CONFIG_A + index);
4726 * t4_read_rss_vf_config - read VF RSS Configuration Table
4727 * @adapter: the adapter
4728 * @index: the entry in the VF RSS table to read
4729 * @vfl: where to store the returned VFL
4730 * @vfh: where to store the returned VFH
4732 * Reads the VF RSS Configuration Table at the specified index and returns
4733 * the (VFL, VFH) values found there.
4735 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
4738 u32 vrt, mask, data;
4740 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
4741 mask = VFWRADDR_V(VFWRADDR_M);
4742 data = VFWRADDR_V(index);
4744 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
4745 data = T6_VFWRADDR_V(index);
4748 /* Request that the index'th VF Table values be read into VFL/VFH.
4750 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
4751 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
4752 vrt |= data | VFRDEN_F;
4753 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
4755 /* Grab the VFL/VFH values ...
4757 if (t4_use_ldst(adapter)) {
4758 t4_fw_tp_pio_rw(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, 1);
4759 t4_fw_tp_pio_rw(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, 1);
4761 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4762 vfl, 1, TP_RSS_VFL_CONFIG_A);
4763 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4764 vfh, 1, TP_RSS_VFH_CONFIG_A);
4769 * t4_read_rss_pf_map - read PF RSS Map
4770 * @adapter: the adapter
4772 * Reads the PF RSS Map register and returns its value.
4774 u32 t4_read_rss_pf_map(struct adapter *adapter)
4778 if (t4_use_ldst(adapter))
4779 t4_fw_tp_pio_rw(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, 1);
4781 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4782 &pfmap, 1, TP_RSS_PF_MAP_A);
4787 * t4_read_rss_pf_mask - read PF RSS Mask
4788 * @adapter: the adapter
4790 * Reads the PF RSS Mask register and returns its value.
4792 u32 t4_read_rss_pf_mask(struct adapter *adapter)
4796 if (t4_use_ldst(adapter))
4797 t4_fw_tp_pio_rw(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, 1);
4799 t4_read_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4800 &pfmask, 1, TP_RSS_PF_MSK_A);
4805 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
4806 * @adap: the adapter
4807 * @v4: holds the TCP/IP counter values
4808 * @v6: holds the TCP/IPv6 counter values
4810 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
4811 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
4813 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
4814 struct tp_tcp_stats *v6)
4816 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
4818 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
4819 #define STAT(x) val[STAT_IDX(x)]
4820 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
4823 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4824 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
4825 v4->tcp_out_rsts = STAT(OUT_RST);
4826 v4->tcp_in_segs = STAT64(IN_SEG);
4827 v4->tcp_out_segs = STAT64(OUT_SEG);
4828 v4->tcp_retrans_segs = STAT64(RXT_SEG);
4831 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4832 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
4833 v6->tcp_out_rsts = STAT(OUT_RST);
4834 v6->tcp_in_segs = STAT64(IN_SEG);
4835 v6->tcp_out_segs = STAT64(OUT_SEG);
4836 v6->tcp_retrans_segs = STAT64(RXT_SEG);
4844 * t4_tp_get_err_stats - read TP's error MIB counters
4845 * @adap: the adapter
4846 * @st: holds the counter values
4848 * Returns the values of TP's error counters.
4850 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st)
4852 int nchan = adap->params.arch.nchan;
4854 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4855 st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A);
4856 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4857 st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A);
4858 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4859 st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A);
4860 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4861 st->tnl_cong_drops, nchan, TP_MIB_TNL_CNG_DROP_0_A);
4862 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4863 st->ofld_chan_drops, nchan, TP_MIB_OFD_CHN_DROP_0_A);
4864 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4865 st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A);
4866 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4867 st->ofld_vlan_drops, nchan, TP_MIB_OFD_VLN_DROP_0_A);
4868 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4869 st->tcp6_in_errs, nchan, TP_MIB_TCP_V6IN_ERR_0_A);
4871 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A,
4872 &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A);
4876 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
4877 * @adap: the adapter
4878 * @st: holds the counter values
4880 * Returns the values of TP's CPL counters.
4882 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st)
4884 int nchan = adap->params.arch.nchan;
4886 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req,
4887 nchan, TP_MIB_CPL_IN_REQ_0_A);
4888 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp,
4889 nchan, TP_MIB_CPL_OUT_RSP_0_A);
4894 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
4895 * @adap: the adapter
4896 * @st: holds the counter values
4898 * Returns the values of TP's RDMA counters.
4900 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st)
4902 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt,
4903 2, TP_MIB_RQE_DFR_PKT_A);
4907 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
4908 * @adap: the adapter
4909 * @idx: the port index
4910 * @st: holds the counter values
4912 * Returns the values of TP's FCoE counters for the selected port.
4914 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
4915 struct tp_fcoe_stats *st)
4919 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp,
4920 1, TP_MIB_FCOE_DDP_0_A + idx);
4921 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop,
4922 1, TP_MIB_FCOE_DROP_0_A + idx);
4923 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
4924 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx);
4925 st->octets_ddp = ((u64)val[0] << 32) | val[1];
4929 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
4930 * @adap: the adapter
4931 * @st: holds the counter values
4933 * Returns the values of TP's counters for non-TCP directly-placed packets.
4935 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st)
4939 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4,
4941 st->frames = val[0];
4943 st->octets = ((u64)val[2] << 32) | val[3];
4947 * t4_read_mtu_tbl - returns the values in the HW path MTU table
4948 * @adap: the adapter
4949 * @mtus: where to store the MTU values
4950 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
4952 * Reads the HW path MTU table.
4954 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
4959 for (i = 0; i < NMTUS; ++i) {
4960 t4_write_reg(adap, TP_MTU_TABLE_A,
4961 MTUINDEX_V(0xff) | MTUVALUE_V(i));
4962 v = t4_read_reg(adap, TP_MTU_TABLE_A);
4963 mtus[i] = MTUVALUE_G(v);
4965 mtu_log[i] = MTUWIDTH_G(v);
4970 * t4_read_cong_tbl - reads the congestion control table
4971 * @adap: the adapter
4972 * @incr: where to store the alpha values
4974 * Reads the additive increments programmed into the HW congestion
4977 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
4979 unsigned int mtu, w;
4981 for (mtu = 0; mtu < NMTUS; ++mtu)
4982 for (w = 0; w < NCCTRL_WIN; ++w) {
4983 t4_write_reg(adap, TP_CCTRL_TABLE_A,
4984 ROWINDEX_V(0xffff) | (mtu << 5) | w);
4985 incr[mtu][w] = (u16)t4_read_reg(adap,
4986 TP_CCTRL_TABLE_A) & 0x1fff;
4991 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
4992 * @adap: the adapter
4993 * @addr: the indirect TP register address
4994 * @mask: specifies the field within the register to modify
4995 * @val: new value for the field
4997 * Sets a field of an indirect TP register to the given value.
4999 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5000 unsigned int mask, unsigned int val)
5002 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5003 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5004 t4_write_reg(adap, TP_PIO_DATA_A, val);
5008 * init_cong_ctrl - initialize congestion control parameters
5009 * @a: the alpha values for congestion control
5010 * @b: the beta values for congestion control
5012 * Initialize the congestion control parameters.
5014 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5016 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5041 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5044 b[13] = b[14] = b[15] = b[16] = 3;
5045 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5046 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5051 /* The minimum additive increment value for the congestion control table */
5052 #define CC_MIN_INCR 2U
5055 * t4_load_mtus - write the MTU and congestion control HW tables
5056 * @adap: the adapter
5057 * @mtus: the values for the MTU table
5058 * @alpha: the values for the congestion control alpha parameter
5059 * @beta: the values for the congestion control beta parameter
5061 * Write the HW MTU table with the supplied MTUs and the high-speed
5062 * congestion control table with the supplied alpha, beta, and MTUs.
5063 * We write the two tables together because the additive increments
5064 * depend on the MTUs.
5066 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5067 const unsigned short *alpha, const unsigned short *beta)
5069 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5070 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5071 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5072 28672, 40960, 57344, 81920, 114688, 163840, 229376
5077 for (i = 0; i < NMTUS; ++i) {
5078 unsigned int mtu = mtus[i];
5079 unsigned int log2 = fls(mtu);
5081 if (!(mtu & ((1 << log2) >> 2))) /* round */
5083 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5084 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5086 for (w = 0; w < NCCTRL_WIN; ++w) {
5089 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5092 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5093 (w << 16) | (beta[w] << 13) | inc);
5098 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5099 * clocks. The formula is
5101 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5103 * which is equivalent to
5105 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5107 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5109 u64 v = bytes256 * adap->params.vpd.cclk;
5111 return v * 62 + v / 2;
5115 * t4_get_chan_txrate - get the current per channel Tx rates
5116 * @adap: the adapter
5117 * @nic_rate: rates for NIC traffic
5118 * @ofld_rate: rates for offloaded traffic
5120 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5123 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5127 v = t4_read_reg(adap, TP_TX_TRATE_A);
5128 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5129 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5130 if (adap->params.arch.nchan == NCHAN) {
5131 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5132 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5135 v = t4_read_reg(adap, TP_TX_ORATE_A);
5136 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5137 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5138 if (adap->params.arch.nchan == NCHAN) {
5139 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5140 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5145 * t4_set_trace_filter - configure one of the tracing filters
5146 * @adap: the adapter
5147 * @tp: the desired trace filter parameters
5148 * @idx: which filter to configure
5149 * @enable: whether to enable or disable the filter
5151 * Configures one of the tracing filters available in HW. If @enable is
5152 * %0 @tp is not examined and may be %NULL. The user is responsible to
5153 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5155 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5156 int idx, int enable)
5158 int i, ofst = idx * 4;
5159 u32 data_reg, mask_reg, cfg;
5160 u32 multitrc = TRCMULTIFILTER_F;
5163 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5167 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5168 if (cfg & TRCMULTIFILTER_F) {
5169 /* If multiple tracers are enabled, then maximum
5170 * capture size is 2.5KB (FIFO size of a single channel)
5171 * minus 2 flits for CPL_TRACE_PKT header.
5173 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5176 /* If multiple tracers are disabled, to avoid deadlocks
5177 * maximum packet capture size of 9600 bytes is recommended.
5178 * Also in this mode, only trace0 can be enabled and running.
5181 if (tp->snap_len > 9600 || idx)
5185 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5186 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5187 tp->min_len > TFMINPKTSIZE_M)
5190 /* stop the tracer we'll be changing */
5191 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5193 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5194 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5195 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5197 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5198 t4_write_reg(adap, data_reg, tp->data[i]);
5199 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5201 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5202 TFCAPTUREMAX_V(tp->snap_len) |
5203 TFMINPKTSIZE_V(tp->min_len));
5204 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5205 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5206 (is_t4(adap->params.chip) ?
5207 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5208 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5209 T5_TFINVERTMATCH_V(tp->invert)));
5215 * t4_get_trace_filter - query one of the tracing filters
5216 * @adap: the adapter
5217 * @tp: the current trace filter parameters
5218 * @idx: which trace filter to query
5219 * @enabled: non-zero if the filter is enabled
5221 * Returns the current settings of one of the HW tracing filters.
5223 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
5227 int i, ofst = idx * 4;
5228 u32 data_reg, mask_reg;
5230 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
5231 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
5233 if (is_t4(adap->params.chip)) {
5234 *enabled = !!(ctla & TFEN_F);
5235 tp->port = TFPORT_G(ctla);
5236 tp->invert = !!(ctla & TFINVERTMATCH_F);
5238 *enabled = !!(ctla & T5_TFEN_F);
5239 tp->port = T5_TFPORT_G(ctla);
5240 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
5242 tp->snap_len = TFCAPTUREMAX_G(ctlb);
5243 tp->min_len = TFMINPKTSIZE_G(ctlb);
5244 tp->skip_ofst = TFOFFSET_G(ctla);
5245 tp->skip_len = TFLENGTH_G(ctla);
5247 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
5248 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
5249 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
5251 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5252 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
5253 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
5258 * t4_pmtx_get_stats - returns the HW stats from PMTX
5259 * @adap: the adapter
5260 * @cnt: where to store the count statistics
5261 * @cycles: where to store the cycle statistics
5263 * Returns performance statistics from PMTX.
5265 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5270 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5271 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
5272 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
5273 if (is_t4(adap->params.chip)) {
5274 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
5276 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
5277 PM_TX_DBG_DATA_A, data, 2,
5278 PM_TX_DBG_STAT_MSB_A);
5279 cycles[i] = (((u64)data[0] << 32) | data[1]);
5285 * t4_pmrx_get_stats - returns the HW stats from PMRX
5286 * @adap: the adapter
5287 * @cnt: where to store the count statistics
5288 * @cycles: where to store the cycle statistics
5290 * Returns performance statistics from PMRX.
5292 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
5297 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
5298 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
5299 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
5300 if (is_t4(adap->params.chip)) {
5301 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
5303 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
5304 PM_RX_DBG_DATA_A, data, 2,
5305 PM_RX_DBG_STAT_MSB_A);
5306 cycles[i] = (((u64)data[0] << 32) | data[1]);
5312 * t4_get_mps_bg_map - return the buffer groups associated with a port
5313 * @adap: the adapter
5314 * @idx: the port index
5316 * Returns a bitmap indicating which MPS buffer groups are associated
5317 * with the given port. Bit i is set if buffer group i is used by the
5320 unsigned int t4_get_mps_bg_map(struct adapter *adap, int idx)
5322 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
5325 return idx == 0 ? 0xf : 0;
5326 /* In T6 (which is a 2 port card),
5327 * port 0 is mapped to channel 0 and port 1 is mapped to channel 1.
5328 * For 2 port T4/T5 adapter,
5329 * port 0 is mapped to channel 0 and 1,
5330 * port 1 is mapped to channel 2 and 3.
5333 (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5))
5334 return idx < 2 ? (3 << (2 * idx)) : 0;
5339 * t4_get_port_type_description - return Port Type string description
5340 * @port_type: firmware Port Type enumeration
5342 const char *t4_get_port_type_description(enum fw_port_type port_type)
5344 static const char *const port_type_description[] = {
5363 if (port_type < ARRAY_SIZE(port_type_description))
5364 return port_type_description[port_type];
5369 * t4_get_port_stats_offset - collect port stats relative to a previous
5371 * @adap: The adapter
5373 * @stats: Current stats to fill
5374 * @offset: Previous stats snapshot
5376 void t4_get_port_stats_offset(struct adapter *adap, int idx,
5377 struct port_stats *stats,
5378 struct port_stats *offset)
5383 t4_get_port_stats(adap, idx, stats);
5384 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
5385 i < (sizeof(struct port_stats) / sizeof(u64));
5391 * t4_get_port_stats - collect port statistics
5392 * @adap: the adapter
5393 * @idx: the port index
5394 * @p: the stats structure to fill
5396 * Collect statistics related to the given port from HW.
5398 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
5400 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5402 #define GET_STAT(name) \
5403 t4_read_reg64(adap, \
5404 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
5405 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
5406 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5408 p->tx_octets = GET_STAT(TX_PORT_BYTES);
5409 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
5410 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
5411 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
5412 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
5413 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
5414 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
5415 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
5416 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
5417 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
5418 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
5419 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
5420 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
5421 p->tx_drop = GET_STAT(TX_PORT_DROP);
5422 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
5423 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
5424 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
5425 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
5426 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
5427 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
5428 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
5429 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
5430 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
5432 p->rx_octets = GET_STAT(RX_PORT_BYTES);
5433 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
5434 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
5435 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
5436 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
5437 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
5438 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
5439 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
5440 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
5441 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
5442 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
5443 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
5444 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
5445 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
5446 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
5447 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
5448 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
5449 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
5450 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
5451 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
5452 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
5453 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
5454 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
5455 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
5456 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
5457 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
5458 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
5460 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
5461 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
5462 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
5463 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
5464 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
5465 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
5466 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
5467 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
5474 * t4_get_lb_stats - collect loopback port statistics
5475 * @adap: the adapter
5476 * @idx: the loopback port index
5477 * @p: the stats structure to fill
5479 * Return HW statistics for the given loopback port.
5481 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
5483 u32 bgmap = t4_get_mps_bg_map(adap, idx);
5485 #define GET_STAT(name) \
5486 t4_read_reg64(adap, \
5487 (is_t4(adap->params.chip) ? \
5488 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
5489 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
5490 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
5492 p->octets = GET_STAT(BYTES);
5493 p->frames = GET_STAT(FRAMES);
5494 p->bcast_frames = GET_STAT(BCAST);
5495 p->mcast_frames = GET_STAT(MCAST);
5496 p->ucast_frames = GET_STAT(UCAST);
5497 p->error_frames = GET_STAT(ERROR);
5499 p->frames_64 = GET_STAT(64B);
5500 p->frames_65_127 = GET_STAT(65B_127B);
5501 p->frames_128_255 = GET_STAT(128B_255B);
5502 p->frames_256_511 = GET_STAT(256B_511B);
5503 p->frames_512_1023 = GET_STAT(512B_1023B);
5504 p->frames_1024_1518 = GET_STAT(1024B_1518B);
5505 p->frames_1519_max = GET_STAT(1519B_MAX);
5506 p->drop = GET_STAT(DROP_FRAMES);
5508 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
5509 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
5510 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
5511 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
5512 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
5513 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
5514 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
5515 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
5521 /* t4_mk_filtdelwr - create a delete filter WR
5522 * @ftid: the filter ID
5523 * @wr: the filter work request to populate
5524 * @qid: ingress queue to receive the delete notification
5526 * Creates a filter work request to delete the supplied filter. If @qid is
5527 * negative the delete notification is suppressed.
5529 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
5531 memset(wr, 0, sizeof(*wr));
5532 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
5533 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
5534 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
5535 FW_FILTER_WR_NOREPLY_V(qid < 0));
5536 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
5538 wr->rx_chan_rx_rpl_iq =
5539 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
5542 #define INIT_CMD(var, cmd, rd_wr) do { \
5543 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
5544 FW_CMD_REQUEST_F | \
5545 FW_CMD_##rd_wr##_F); \
5546 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
5549 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
5553 struct fw_ldst_cmd c;
5555 memset(&c, 0, sizeof(c));
5556 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
5557 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5561 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5562 c.u.addrval.addr = cpu_to_be32(addr);
5563 c.u.addrval.val = cpu_to_be32(val);
5565 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5569 * t4_mdio_rd - read a PHY register through MDIO
5570 * @adap: the adapter
5571 * @mbox: mailbox to use for the FW command
5572 * @phy_addr: the PHY address
5573 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5574 * @reg: the register to read
5575 * @valp: where to store the value
5577 * Issues a FW command through the given mailbox to read a PHY register.
5579 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5580 unsigned int mmd, unsigned int reg, u16 *valp)
5584 struct fw_ldst_cmd c;
5586 memset(&c, 0, sizeof(c));
5587 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5588 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5589 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5591 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5592 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5593 FW_LDST_CMD_MMD_V(mmd));
5594 c.u.mdio.raddr = cpu_to_be16(reg);
5596 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5598 *valp = be16_to_cpu(c.u.mdio.rval);
5603 * t4_mdio_wr - write a PHY register through MDIO
5604 * @adap: the adapter
5605 * @mbox: mailbox to use for the FW command
5606 * @phy_addr: the PHY address
5607 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
5608 * @reg: the register to write
5609 * @valp: value to write
5611 * Issues a FW command through the given mailbox to write a PHY register.
5613 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
5614 unsigned int mmd, unsigned int reg, u16 val)
5617 struct fw_ldst_cmd c;
5619 memset(&c, 0, sizeof(c));
5620 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
5621 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5622 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5624 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5625 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
5626 FW_LDST_CMD_MMD_V(mmd));
5627 c.u.mdio.raddr = cpu_to_be16(reg);
5628 c.u.mdio.rval = cpu_to_be16(val);
5630 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5634 * t4_sge_decode_idma_state - decode the idma state
5635 * @adap: the adapter
5636 * @state: the state idma is stuck in
5638 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
5640 static const char * const t4_decode[] = {
5642 "IDMA_PUSH_MORE_CPL_FIFO",
5643 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5645 "IDMA_PHYSADDR_SEND_PCIEHDR",
5646 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5647 "IDMA_PHYSADDR_SEND_PAYLOAD",
5648 "IDMA_SEND_FIFO_TO_IMSG",
5649 "IDMA_FL_REQ_DATA_FL_PREP",
5650 "IDMA_FL_REQ_DATA_FL",
5652 "IDMA_FL_H_REQ_HEADER_FL",
5653 "IDMA_FL_H_SEND_PCIEHDR",
5654 "IDMA_FL_H_PUSH_CPL_FIFO",
5655 "IDMA_FL_H_SEND_CPL",
5656 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5657 "IDMA_FL_H_SEND_IP_HDR",
5658 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5659 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5660 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5661 "IDMA_FL_D_SEND_PCIEHDR",
5662 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5663 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5664 "IDMA_FL_SEND_PCIEHDR",
5665 "IDMA_FL_PUSH_CPL_FIFO",
5667 "IDMA_FL_SEND_PAYLOAD_FIRST",
5668 "IDMA_FL_SEND_PAYLOAD",
5669 "IDMA_FL_REQ_NEXT_DATA_FL",
5670 "IDMA_FL_SEND_NEXT_PCIEHDR",
5671 "IDMA_FL_SEND_PADDING",
5672 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5673 "IDMA_FL_SEND_FIFO_TO_IMSG",
5674 "IDMA_FL_REQ_DATAFL_DONE",
5675 "IDMA_FL_REQ_HEADERFL_DONE",
5677 static const char * const t5_decode[] = {
5680 "IDMA_PUSH_MORE_CPL_FIFO",
5681 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5682 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5683 "IDMA_PHYSADDR_SEND_PCIEHDR",
5684 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5685 "IDMA_PHYSADDR_SEND_PAYLOAD",
5686 "IDMA_SEND_FIFO_TO_IMSG",
5687 "IDMA_FL_REQ_DATA_FL",
5689 "IDMA_FL_DROP_SEND_INC",
5690 "IDMA_FL_H_REQ_HEADER_FL",
5691 "IDMA_FL_H_SEND_PCIEHDR",
5692 "IDMA_FL_H_PUSH_CPL_FIFO",
5693 "IDMA_FL_H_SEND_CPL",
5694 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5695 "IDMA_FL_H_SEND_IP_HDR",
5696 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5697 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5698 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5699 "IDMA_FL_D_SEND_PCIEHDR",
5700 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5701 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5702 "IDMA_FL_SEND_PCIEHDR",
5703 "IDMA_FL_PUSH_CPL_FIFO",
5705 "IDMA_FL_SEND_PAYLOAD_FIRST",
5706 "IDMA_FL_SEND_PAYLOAD",
5707 "IDMA_FL_REQ_NEXT_DATA_FL",
5708 "IDMA_FL_SEND_NEXT_PCIEHDR",
5709 "IDMA_FL_SEND_PADDING",
5710 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5712 static const char * const t6_decode[] = {
5714 "IDMA_PUSH_MORE_CPL_FIFO",
5715 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
5716 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
5717 "IDMA_PHYSADDR_SEND_PCIEHDR",
5718 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
5719 "IDMA_PHYSADDR_SEND_PAYLOAD",
5720 "IDMA_FL_REQ_DATA_FL",
5722 "IDMA_FL_DROP_SEND_INC",
5723 "IDMA_FL_H_REQ_HEADER_FL",
5724 "IDMA_FL_H_SEND_PCIEHDR",
5725 "IDMA_FL_H_PUSH_CPL_FIFO",
5726 "IDMA_FL_H_SEND_CPL",
5727 "IDMA_FL_H_SEND_IP_HDR_FIRST",
5728 "IDMA_FL_H_SEND_IP_HDR",
5729 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
5730 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
5731 "IDMA_FL_H_SEND_IP_HDR_PADDING",
5732 "IDMA_FL_D_SEND_PCIEHDR",
5733 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
5734 "IDMA_FL_D_REQ_NEXT_DATA_FL",
5735 "IDMA_FL_SEND_PCIEHDR",
5736 "IDMA_FL_PUSH_CPL_FIFO",
5738 "IDMA_FL_SEND_PAYLOAD_FIRST",
5739 "IDMA_FL_SEND_PAYLOAD",
5740 "IDMA_FL_REQ_NEXT_DATA_FL",
5741 "IDMA_FL_SEND_NEXT_PCIEHDR",
5742 "IDMA_FL_SEND_PADDING",
5743 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
5745 static const u32 sge_regs[] = {
5746 SGE_DEBUG_DATA_LOW_INDEX_2_A,
5747 SGE_DEBUG_DATA_LOW_INDEX_3_A,
5748 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
5750 const char **sge_idma_decode;
5751 int sge_idma_decode_nstates;
5753 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
5755 /* Select the right set of decode strings to dump depending on the
5756 * adapter chip type.
5758 switch (chip_version) {
5760 sge_idma_decode = (const char **)t4_decode;
5761 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5765 sge_idma_decode = (const char **)t5_decode;
5766 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5770 sge_idma_decode = (const char **)t6_decode;
5771 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
5775 dev_err(adapter->pdev_dev,
5776 "Unsupported chip version %d\n", chip_version);
5780 if (is_t4(adapter->params.chip)) {
5781 sge_idma_decode = (const char **)t4_decode;
5782 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
5784 sge_idma_decode = (const char **)t5_decode;
5785 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
5788 if (state < sge_idma_decode_nstates)
5789 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
5791 CH_WARN(adapter, "idma state %d unknown\n", state);
5793 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
5794 CH_WARN(adapter, "SGE register %#x value %#x\n",
5795 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
5799 * t4_sge_ctxt_flush - flush the SGE context cache
5800 * @adap: the adapter
5801 * @mbox: mailbox to use for the FW command
5803 * Issues a FW command through the given mailbox to flush the
5804 * SGE context cache.
5806 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox)
5810 struct fw_ldst_cmd c;
5812 memset(&c, 0, sizeof(c));
5813 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_SGE_EGRC);
5814 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5815 FW_CMD_REQUEST_F | FW_CMD_READ_F |
5817 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5818 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
5820 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5825 * t4_fw_hello - establish communication with FW
5826 * @adap: the adapter
5827 * @mbox: mailbox to use for the FW command
5828 * @evt_mbox: mailbox to receive async FW events
5829 * @master: specifies the caller's willingness to be the device master
5830 * @state: returns the current device state (if non-NULL)
5832 * Issues a command to establish communication with FW. Returns either
5833 * an error (negative integer) or the mailbox of the Master PF.
5835 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
5836 enum dev_master master, enum dev_state *state)
5839 struct fw_hello_cmd c;
5841 unsigned int master_mbox;
5842 int retries = FW_CMD_HELLO_RETRIES;
5845 memset(&c, 0, sizeof(c));
5846 INIT_CMD(c, HELLO, WRITE);
5847 c.err_to_clearinit = cpu_to_be32(
5848 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
5849 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
5850 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
5851 mbox : FW_HELLO_CMD_MBMASTER_M) |
5852 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
5853 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
5854 FW_HELLO_CMD_CLEARINIT_F);
5857 * Issue the HELLO command to the firmware. If it's not successful
5858 * but indicates that we got a "busy" or "timeout" condition, retry
5859 * the HELLO until we exhaust our retry limit. If we do exceed our
5860 * retry limit, check to see if the firmware left us any error
5861 * information and report that if so.
5863 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
5865 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
5867 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
5868 t4_report_fw_error(adap);
5872 v = be32_to_cpu(c.err_to_clearinit);
5873 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
5875 if (v & FW_HELLO_CMD_ERR_F)
5876 *state = DEV_STATE_ERR;
5877 else if (v & FW_HELLO_CMD_INIT_F)
5878 *state = DEV_STATE_INIT;
5880 *state = DEV_STATE_UNINIT;
5884 * If we're not the Master PF then we need to wait around for the
5885 * Master PF Driver to finish setting up the adapter.
5887 * Note that we also do this wait if we're a non-Master-capable PF and
5888 * there is no current Master PF; a Master PF may show up momentarily
5889 * and we wouldn't want to fail pointlessly. (This can happen when an
5890 * OS loads lots of different drivers rapidly at the same time). In
5891 * this case, the Master PF returned by the firmware will be
5892 * PCIE_FW_MASTER_M so the test below will work ...
5894 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
5895 master_mbox != mbox) {
5896 int waiting = FW_CMD_HELLO_TIMEOUT;
5899 * Wait for the firmware to either indicate an error or
5900 * initialized state. If we see either of these we bail out
5901 * and report the issue to the caller. If we exhaust the
5902 * "hello timeout" and we haven't exhausted our retries, try
5903 * again. Otherwise bail with a timeout error.
5912 * If neither Error nor Initialialized are indicated
5913 * by the firmware keep waiting till we exaust our
5914 * timeout ... and then retry if we haven't exhausted
5917 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
5918 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
5929 * We either have an Error or Initialized condition
5930 * report errors preferentially.
5933 if (pcie_fw & PCIE_FW_ERR_F)
5934 *state = DEV_STATE_ERR;
5935 else if (pcie_fw & PCIE_FW_INIT_F)
5936 *state = DEV_STATE_INIT;
5940 * If we arrived before a Master PF was selected and
5941 * there's not a valid Master PF, grab its identity
5944 if (master_mbox == PCIE_FW_MASTER_M &&
5945 (pcie_fw & PCIE_FW_MASTER_VLD_F))
5946 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
5955 * t4_fw_bye - end communication with FW
5956 * @adap: the adapter
5957 * @mbox: mailbox to use for the FW command
5959 * Issues a command to terminate communication with FW.
5961 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
5963 struct fw_bye_cmd c;
5965 memset(&c, 0, sizeof(c));
5966 INIT_CMD(c, BYE, WRITE);
5967 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5971 * t4_init_cmd - ask FW to initialize the device
5972 * @adap: the adapter
5973 * @mbox: mailbox to use for the FW command
5975 * Issues a command to FW to partially initialize the device. This
5976 * performs initialization that generally doesn't depend on user input.
5978 int t4_early_init(struct adapter *adap, unsigned int mbox)
5980 struct fw_initialize_cmd c;
5982 memset(&c, 0, sizeof(c));
5983 INIT_CMD(c, INITIALIZE, WRITE);
5984 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
5988 * t4_fw_reset - issue a reset to FW
5989 * @adap: the adapter
5990 * @mbox: mailbox to use for the FW command
5991 * @reset: specifies the type of reset to perform
5993 * Issues a reset command of the specified type to FW.
5995 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
5997 struct fw_reset_cmd c;
5999 memset(&c, 0, sizeof(c));
6000 INIT_CMD(c, RESET, WRITE);
6001 c.val = cpu_to_be32(reset);
6002 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6006 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
6007 * @adap: the adapter
6008 * @mbox: mailbox to use for the FW RESET command (if desired)
6009 * @force: force uP into RESET even if FW RESET command fails
6011 * Issues a RESET command to firmware (if desired) with a HALT indication
6012 * and then puts the microprocessor into RESET state. The RESET command
6013 * will only be issued if a legitimate mailbox is provided (mbox <=
6014 * PCIE_FW_MASTER_M).
6016 * This is generally used in order for the host to safely manipulate the
6017 * adapter without fear of conflicting with whatever the firmware might
6018 * be doing. The only way out of this state is to RESTART the firmware
6021 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
6026 * If a legitimate mailbox is provided, issue a RESET command
6027 * with a HALT indication.
6029 if (mbox <= PCIE_FW_MASTER_M) {
6030 struct fw_reset_cmd c;
6032 memset(&c, 0, sizeof(c));
6033 INIT_CMD(c, RESET, WRITE);
6034 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
6035 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
6036 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6040 * Normally we won't complete the operation if the firmware RESET
6041 * command fails but if our caller insists we'll go ahead and put the
6042 * uP into RESET. This can be useful if the firmware is hung or even
6043 * missing ... We'll have to take the risk of putting the uP into
6044 * RESET without the cooperation of firmware in that case.
6046 * We also force the firmware's HALT flag to be on in case we bypassed
6047 * the firmware RESET command above or we're dealing with old firmware
6048 * which doesn't have the HALT capability. This will serve as a flag
6049 * for the incoming firmware to know that it's coming out of a HALT
6050 * rather than a RESET ... if it's new enough to understand that ...
6052 if (ret == 0 || force) {
6053 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
6054 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
6059 * And we always return the result of the firmware RESET command
6060 * even when we force the uP into RESET ...
6066 * t4_fw_restart - restart the firmware by taking the uP out of RESET
6067 * @adap: the adapter
6068 * @reset: if we want to do a RESET to restart things
6070 * Restart firmware previously halted by t4_fw_halt(). On successful
6071 * return the previous PF Master remains as the new PF Master and there
6072 * is no need to issue a new HELLO command, etc.
6074 * We do this in two ways:
6076 * 1. If we're dealing with newer firmware we'll simply want to take
6077 * the chip's microprocessor out of RESET. This will cause the
6078 * firmware to start up from its start vector. And then we'll loop
6079 * until the firmware indicates it's started again (PCIE_FW.HALT
6080 * reset to 0) or we timeout.
6082 * 2. If we're dealing with older firmware then we'll need to RESET
6083 * the chip since older firmware won't recognize the PCIE_FW.HALT
6084 * flag and automatically RESET itself on startup.
6086 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
6090 * Since we're directing the RESET instead of the firmware
6091 * doing it automatically, we need to clear the PCIE_FW.HALT
6094 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
6097 * If we've been given a valid mailbox, first try to get the
6098 * firmware to do the RESET. If that works, great and we can
6099 * return success. Otherwise, if we haven't been given a
6100 * valid mailbox or the RESET command failed, fall back to
6101 * hitting the chip with a hammer.
6103 if (mbox <= PCIE_FW_MASTER_M) {
6104 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6106 if (t4_fw_reset(adap, mbox,
6107 PIORST_F | PIORSTMODE_F) == 0)
6111 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
6116 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
6117 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
6118 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
6129 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
6130 * @adap: the adapter
6131 * @mbox: mailbox to use for the FW RESET command (if desired)
6132 * @fw_data: the firmware image to write
6134 * @force: force upgrade even if firmware doesn't cooperate
6136 * Perform all of the steps necessary for upgrading an adapter's
6137 * firmware image. Normally this requires the cooperation of the
6138 * existing firmware in order to halt all existing activities
6139 * but if an invalid mailbox token is passed in we skip that step
6140 * (though we'll still put the adapter microprocessor into RESET in
6143 * On successful return the new firmware will have been loaded and
6144 * the adapter will have been fully RESET losing all previous setup
6145 * state. On unsuccessful return the adapter may be completely hosed ...
6146 * positive errno indicates that the adapter is ~probably~ intact, a
6147 * negative errno indicates that things are looking bad ...
6149 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
6150 const u8 *fw_data, unsigned int size, int force)
6152 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
6155 if (!t4_fw_matches_chip(adap, fw_hdr))
6158 ret = t4_fw_halt(adap, mbox, force);
6159 if (ret < 0 && !force)
6162 ret = t4_load_fw(adap, fw_data, size);
6167 * Older versions of the firmware don't understand the new
6168 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
6169 * restart. So for newly loaded older firmware we'll have to do the
6170 * RESET for it so it starts up on a clean slate. We can tell if
6171 * the newly loaded firmware will handle this right by checking
6172 * its header flags to see if it advertises the capability.
6174 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
6175 return t4_fw_restart(adap, mbox, reset);
6179 * t4_fl_pkt_align - return the fl packet alignment
6180 * @adap: the adapter
6182 * T4 has a single field to specify the packing and padding boundary.
6183 * T5 onwards has separate fields for this and hence the alignment for
6184 * next packet offset is maximum of these two.
6187 int t4_fl_pkt_align(struct adapter *adap)
6189 u32 sge_control, sge_control2;
6190 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
6192 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
6194 /* T4 uses a single control field to specify both the PCIe Padding and
6195 * Packing Boundary. T5 introduced the ability to specify these
6196 * separately. The actual Ingress Packet Data alignment boundary
6197 * within Packed Buffer Mode is the maximum of these two
6198 * specifications. (Note that it makes no real practical sense to
6199 * have the Pading Boudary be larger than the Packing Boundary but you
6200 * could set the chip up that way and, in fact, legacy T4 code would
6201 * end doing this because it would initialize the Padding Boundary and
6202 * leave the Packing Boundary initialized to 0 (16 bytes).)
6203 * Padding Boundary values in T6 starts from 8B,
6204 * where as it is 32B for T4 and T5.
6206 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
6207 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
6209 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
6211 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
6213 fl_align = ingpadboundary;
6214 if (!is_t4(adap->params.chip)) {
6215 /* T5 has a weird interpretation of one of the PCIe Packing
6216 * Boundary values. No idea why ...
6218 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
6219 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
6220 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
6221 ingpackboundary = 16;
6223 ingpackboundary = 1 << (ingpackboundary +
6224 INGPACKBOUNDARY_SHIFT_X);
6226 fl_align = max(ingpadboundary, ingpackboundary);
6232 * t4_fixup_host_params - fix up host-dependent parameters
6233 * @adap: the adapter
6234 * @page_size: the host's Base Page Size
6235 * @cache_line_size: the host's Cache Line Size
6237 * Various registers in T4 contain values which are dependent on the
6238 * host's Base Page and Cache Line Sizes. This function will fix all of
6239 * those registers with the appropriate values as passed in ...
6241 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
6242 unsigned int cache_line_size)
6244 unsigned int page_shift = fls(page_size) - 1;
6245 unsigned int sge_hps = page_shift - 10;
6246 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
6247 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
6248 unsigned int fl_align_log = fls(fl_align) - 1;
6249 unsigned int ingpad;
6251 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
6252 HOSTPAGESIZEPF0_V(sge_hps) |
6253 HOSTPAGESIZEPF1_V(sge_hps) |
6254 HOSTPAGESIZEPF2_V(sge_hps) |
6255 HOSTPAGESIZEPF3_V(sge_hps) |
6256 HOSTPAGESIZEPF4_V(sge_hps) |
6257 HOSTPAGESIZEPF5_V(sge_hps) |
6258 HOSTPAGESIZEPF6_V(sge_hps) |
6259 HOSTPAGESIZEPF7_V(sge_hps));
6261 if (is_t4(adap->params.chip)) {
6262 t4_set_reg_field(adap, SGE_CONTROL_A,
6263 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6264 EGRSTATUSPAGESIZE_F,
6265 INGPADBOUNDARY_V(fl_align_log -
6266 INGPADBOUNDARY_SHIFT_X) |
6267 EGRSTATUSPAGESIZE_V(stat_len != 64));
6269 /* T5 introduced the separation of the Free List Padding and
6270 * Packing Boundaries. Thus, we can select a smaller Padding
6271 * Boundary to avoid uselessly chewing up PCIe Link and Memory
6272 * Bandwidth, and use a Packing Boundary which is large enough
6273 * to avoid false sharing between CPUs, etc.
6275 * For the PCI Link, the smaller the Padding Boundary the
6276 * better. For the Memory Controller, a smaller Padding
6277 * Boundary is better until we cross under the Memory Line
6278 * Size (the minimum unit of transfer to/from Memory). If we
6279 * have a Padding Boundary which is smaller than the Memory
6280 * Line Size, that'll involve a Read-Modify-Write cycle on the
6281 * Memory Controller which is never good. For T5 the smallest
6282 * Padding Boundary which we can select is 32 bytes which is
6283 * larger than any known Memory Controller Line Size so we'll
6286 * T5 has a different interpretation of the "0" value for the
6287 * Packing Boundary. This corresponds to 16 bytes instead of
6288 * the expected 32 bytes. We never have a Packing Boundary
6289 * less than 32 bytes so we can't use that special value but
6290 * on the other hand, if we wanted 32 bytes, the best we can
6291 * really do is 64 bytes.
6293 if (fl_align <= 32) {
6298 if (is_t5(adap->params.chip))
6299 ingpad = INGPCIEBOUNDARY_32B_X;
6301 ingpad = T6_INGPADBOUNDARY_32B_X;
6303 t4_set_reg_field(adap, SGE_CONTROL_A,
6304 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
6305 EGRSTATUSPAGESIZE_F,
6306 INGPADBOUNDARY_V(ingpad) |
6307 EGRSTATUSPAGESIZE_V(stat_len != 64));
6308 t4_set_reg_field(adap, SGE_CONTROL2_A,
6309 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
6310 INGPACKBOUNDARY_V(fl_align_log -
6311 INGPACKBOUNDARY_SHIFT_X));
6314 * Adjust various SGE Free List Host Buffer Sizes.
6316 * This is something of a crock since we're using fixed indices into
6317 * the array which are also known by the sge.c code and the T4
6318 * Firmware Configuration File. We need to come up with a much better
6319 * approach to managing this array. For now, the first four entries
6324 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
6325 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
6327 * For the single-MTU buffers in unpacked mode we need to include
6328 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
6329 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
6330 * Padding boundary. All of these are accommodated in the Factory
6331 * Default Firmware Configuration File but we need to adjust it for
6332 * this host's cache line size.
6334 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
6335 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
6336 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
6338 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
6339 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
6342 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
6348 * t4_fw_initialize - ask FW to initialize the device
6349 * @adap: the adapter
6350 * @mbox: mailbox to use for the FW command
6352 * Issues a command to FW to partially initialize the device. This
6353 * performs initialization that generally doesn't depend on user input.
6355 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
6357 struct fw_initialize_cmd c;
6359 memset(&c, 0, sizeof(c));
6360 INIT_CMD(c, INITIALIZE, WRITE);
6361 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6365 * t4_query_params_rw - query FW or device parameters
6366 * @adap: the adapter
6367 * @mbox: mailbox to use for the FW command
6370 * @nparams: the number of parameters
6371 * @params: the parameter names
6372 * @val: the parameter values
6373 * @rw: Write and read flag
6375 * Reads the value of FW or device parameters. Up to 7 parameters can be
6378 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
6379 unsigned int vf, unsigned int nparams, const u32 *params,
6383 struct fw_params_cmd c;
6384 __be32 *p = &c.param[0].mnem;
6389 memset(&c, 0, sizeof(c));
6390 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6391 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6392 FW_PARAMS_CMD_PFN_V(pf) |
6393 FW_PARAMS_CMD_VFN_V(vf));
6394 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6396 for (i = 0; i < nparams; i++) {
6397 *p++ = cpu_to_be32(*params++);
6399 *p = cpu_to_be32(*(val + i));
6403 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6405 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
6406 *val++ = be32_to_cpu(*p);
6410 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6411 unsigned int vf, unsigned int nparams, const u32 *params,
6414 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0);
6418 * t4_set_params_timeout - sets FW or device parameters
6419 * @adap: the adapter
6420 * @mbox: mailbox to use for the FW command
6423 * @nparams: the number of parameters
6424 * @params: the parameter names
6425 * @val: the parameter values
6426 * @timeout: the timeout time
6428 * Sets the value of FW or device parameters. Up to 7 parameters can be
6429 * specified at once.
6431 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
6432 unsigned int pf, unsigned int vf,
6433 unsigned int nparams, const u32 *params,
6434 const u32 *val, int timeout)
6436 struct fw_params_cmd c;
6437 __be32 *p = &c.param[0].mnem;
6442 memset(&c, 0, sizeof(c));
6443 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
6444 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6445 FW_PARAMS_CMD_PFN_V(pf) |
6446 FW_PARAMS_CMD_VFN_V(vf));
6447 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6450 *p++ = cpu_to_be32(*params++);
6451 *p++ = cpu_to_be32(*val++);
6454 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
6458 * t4_set_params - sets FW or device parameters
6459 * @adap: the adapter
6460 * @mbox: mailbox to use for the FW command
6463 * @nparams: the number of parameters
6464 * @params: the parameter names
6465 * @val: the parameter values
6467 * Sets the value of FW or device parameters. Up to 7 parameters can be
6468 * specified at once.
6470 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
6471 unsigned int vf, unsigned int nparams, const u32 *params,
6474 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
6475 FW_CMD_MAX_TIMEOUT);
6479 * t4_cfg_pfvf - configure PF/VF resource limits
6480 * @adap: the adapter
6481 * @mbox: mailbox to use for the FW command
6482 * @pf: the PF being configured
6483 * @vf: the VF being configured
6484 * @txq: the max number of egress queues
6485 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
6486 * @rxqi: the max number of interrupt-capable ingress queues
6487 * @rxq: the max number of interruptless ingress queues
6488 * @tc: the PCI traffic class
6489 * @vi: the max number of virtual interfaces
6490 * @cmask: the channel access rights mask for the PF/VF
6491 * @pmask: the port access rights mask for the PF/VF
6492 * @nexact: the maximum number of exact MPS filters
6493 * @rcaps: read capabilities
6494 * @wxcaps: write/execute capabilities
6496 * Configures resource limits and capabilities for a physical or virtual
6499 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
6500 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
6501 unsigned int rxqi, unsigned int rxq, unsigned int tc,
6502 unsigned int vi, unsigned int cmask, unsigned int pmask,
6503 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
6505 struct fw_pfvf_cmd c;
6507 memset(&c, 0, sizeof(c));
6508 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
6509 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
6510 FW_PFVF_CMD_VFN_V(vf));
6511 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6512 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
6513 FW_PFVF_CMD_NIQ_V(rxq));
6514 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
6515 FW_PFVF_CMD_PMASK_V(pmask) |
6516 FW_PFVF_CMD_NEQ_V(txq));
6517 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
6518 FW_PFVF_CMD_NVI_V(vi) |
6519 FW_PFVF_CMD_NEXACTF_V(nexact));
6520 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
6521 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
6522 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
6523 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6527 * t4_alloc_vi - allocate a virtual interface
6528 * @adap: the adapter
6529 * @mbox: mailbox to use for the FW command
6530 * @port: physical port associated with the VI
6531 * @pf: the PF owning the VI
6532 * @vf: the VF owning the VI
6533 * @nmac: number of MAC addresses needed (1 to 5)
6534 * @mac: the MAC addresses of the VI
6535 * @rss_size: size of RSS table slice associated with this VI
6537 * Allocates a virtual interface for the given physical port. If @mac is
6538 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
6539 * @mac should be large enough to hold @nmac Ethernet addresses, they are
6540 * stored consecutively so the space needed is @nmac * 6 bytes.
6541 * Returns a negative error number or the non-negative VI id.
6543 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
6544 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
6545 unsigned int *rss_size)
6550 memset(&c, 0, sizeof(c));
6551 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
6552 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
6553 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
6554 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
6555 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
6558 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6563 memcpy(mac, c.mac, sizeof(c.mac));
6566 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
6568 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
6570 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
6572 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
6576 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
6577 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
6581 * t4_free_vi - free a virtual interface
6582 * @adap: the adapter
6583 * @mbox: mailbox to use for the FW command
6584 * @pf: the PF owning the VI
6585 * @vf: the VF owning the VI
6586 * @viid: virtual interface identifiler
6588 * Free a previously allocated virtual interface.
6590 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
6591 unsigned int vf, unsigned int viid)
6595 memset(&c, 0, sizeof(c));
6596 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
6599 FW_VI_CMD_PFN_V(pf) |
6600 FW_VI_CMD_VFN_V(vf));
6601 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
6602 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
6604 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6608 * t4_set_rxmode - set Rx properties of a virtual interface
6609 * @adap: the adapter
6610 * @mbox: mailbox to use for the FW command
6612 * @mtu: the new MTU or -1
6613 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
6614 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
6615 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
6616 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
6617 * @sleep_ok: if true we may sleep while awaiting command completion
6619 * Sets Rx properties of a virtual interface.
6621 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
6622 int mtu, int promisc, int all_multi, int bcast, int vlanex,
6625 struct fw_vi_rxmode_cmd c;
6627 /* convert to FW values */
6629 mtu = FW_RXMODE_MTU_NO_CHG;
6631 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
6633 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
6635 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
6637 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
6639 memset(&c, 0, sizeof(c));
6640 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
6641 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6642 FW_VI_RXMODE_CMD_VIID_V(viid));
6643 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
6645 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
6646 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
6647 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
6648 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
6649 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
6650 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6654 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
6655 * @adap: the adapter
6656 * @mbox: mailbox to use for the FW command
6658 * @free: if true any existing filters for this VI id are first removed
6659 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6660 * @addr: the MAC address(es)
6661 * @idx: where to store the index of each allocated filter
6662 * @hash: pointer to hash address filter bitmap
6663 * @sleep_ok: call is allowed to sleep
6665 * Allocates an exact-match filter for each of the supplied addresses and
6666 * sets it to the corresponding address. If @idx is not %NULL it should
6667 * have at least @naddr entries, each of which will be set to the index of
6668 * the filter allocated for the corresponding MAC address. If a filter
6669 * could not be allocated for an address its index is set to 0xffff.
6670 * If @hash is not %NULL addresses that fail to allocate an exact filter
6671 * are hashed and update the hash filter bitmap pointed at by @hash.
6673 * Returns a negative error number or the number of filters allocated.
6675 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
6676 unsigned int viid, bool free, unsigned int naddr,
6677 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
6679 int offset, ret = 0;
6680 struct fw_vi_mac_cmd c;
6681 unsigned int nfilters = 0;
6682 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
6683 unsigned int rem = naddr;
6685 if (naddr > max_naddr)
6688 for (offset = 0; offset < naddr ; /**/) {
6689 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
6690 rem : ARRAY_SIZE(c.u.exact));
6691 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6692 u.exact[fw_naddr]), 16);
6693 struct fw_vi_mac_exact *p;
6696 memset(&c, 0, sizeof(c));
6697 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6700 FW_CMD_EXEC_V(free) |
6701 FW_VI_MAC_CMD_VIID_V(viid));
6702 c.freemacs_to_len16 =
6703 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
6704 FW_CMD_LEN16_V(len16));
6706 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6708 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6709 FW_VI_MAC_CMD_IDX_V(
6710 FW_VI_MAC_ADD_MAC));
6711 memcpy(p->macaddr, addr[offset + i],
6712 sizeof(p->macaddr));
6715 /* It's okay if we run out of space in our MAC address arena.
6716 * Some of the addresses we submit may get stored so we need
6717 * to run through the reply to see what the results were ...
6719 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6720 if (ret && ret != -FW_ENOMEM)
6723 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6724 u16 index = FW_VI_MAC_CMD_IDX_G(
6725 be16_to_cpu(p->valid_to_idx));
6728 idx[offset + i] = (index >= max_naddr ?
6730 if (index < max_naddr)
6734 hash_mac_addr(addr[offset + i]));
6742 if (ret == 0 || ret == -FW_ENOMEM)
6748 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
6749 * @adap: the adapter
6750 * @mbox: mailbox to use for the FW command
6752 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
6753 * @addr: the MAC address(es)
6754 * @sleep_ok: call is allowed to sleep
6756 * Frees the exact-match filter for each of the supplied addresses
6758 * Returns a negative error number or the number of filters freed.
6760 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
6761 unsigned int viid, unsigned int naddr,
6762 const u8 **addr, bool sleep_ok)
6764 int offset, ret = 0;
6765 struct fw_vi_mac_cmd c;
6766 unsigned int nfilters = 0;
6767 unsigned int max_naddr = is_t4(adap->params.chip) ?
6768 NUM_MPS_CLS_SRAM_L_INSTANCES :
6769 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6770 unsigned int rem = naddr;
6772 if (naddr > max_naddr)
6775 for (offset = 0; offset < (int)naddr ; /**/) {
6776 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
6778 : ARRAY_SIZE(c.u.exact));
6779 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
6780 u.exact[fw_naddr]), 16);
6781 struct fw_vi_mac_exact *p;
6784 memset(&c, 0, sizeof(c));
6785 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6789 FW_VI_MAC_CMD_VIID_V(viid));
6790 c.freemacs_to_len16 =
6791 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
6792 FW_CMD_LEN16_V(len16));
6794 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
6795 p->valid_to_idx = cpu_to_be16(
6796 FW_VI_MAC_CMD_VALID_F |
6797 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
6798 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
6801 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
6805 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
6806 u16 index = FW_VI_MAC_CMD_IDX_G(
6807 be16_to_cpu(p->valid_to_idx));
6809 if (index < max_naddr)
6823 * t4_change_mac - modifies the exact-match filter for a MAC address
6824 * @adap: the adapter
6825 * @mbox: mailbox to use for the FW command
6827 * @idx: index of existing filter for old value of MAC address, or -1
6828 * @addr: the new MAC address value
6829 * @persist: whether a new MAC allocation should be persistent
6830 * @add_smt: if true also add the address to the HW SMT
6832 * Modifies an exact-match filter and sets it to the new MAC address.
6833 * Note that in general it is not possible to modify the value of a given
6834 * filter so the generic way to modify an address filter is to free the one
6835 * being used by the old address value and allocate a new filter for the
6836 * new address value. @idx can be -1 if the address is a new addition.
6838 * Returns a negative error number or the index of the filter with the new
6841 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
6842 int idx, const u8 *addr, bool persist, bool add_smt)
6845 struct fw_vi_mac_cmd c;
6846 struct fw_vi_mac_exact *p = c.u.exact;
6847 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
6849 if (idx < 0) /* new allocation */
6850 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
6851 mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
6853 memset(&c, 0, sizeof(c));
6854 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6855 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6856 FW_VI_MAC_CMD_VIID_V(viid));
6857 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
6858 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
6859 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
6860 FW_VI_MAC_CMD_IDX_V(idx));
6861 memcpy(p->macaddr, addr, sizeof(p->macaddr));
6863 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6865 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
6866 if (ret >= max_mac_addr)
6873 * t4_set_addr_hash - program the MAC inexact-match hash filter
6874 * @adap: the adapter
6875 * @mbox: mailbox to use for the FW command
6877 * @ucast: whether the hash filter should also match unicast addresses
6878 * @vec: the value to be written to the hash filter
6879 * @sleep_ok: call is allowed to sleep
6881 * Sets the 64-bit inexact-match hash filter for a virtual interface.
6883 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
6884 bool ucast, u64 vec, bool sleep_ok)
6886 struct fw_vi_mac_cmd c;
6888 memset(&c, 0, sizeof(c));
6889 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
6890 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6891 FW_VI_ENABLE_CMD_VIID_V(viid));
6892 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
6893 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
6895 c.u.hash.hashvec = cpu_to_be64(vec);
6896 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
6900 * t4_enable_vi_params - enable/disable a virtual interface
6901 * @adap: the adapter
6902 * @mbox: mailbox to use for the FW command
6904 * @rx_en: 1=enable Rx, 0=disable Rx
6905 * @tx_en: 1=enable Tx, 0=disable Tx
6906 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
6908 * Enables/disables a virtual interface. Note that setting DCB Enable
6909 * only makes sense when enabling a Virtual Interface ...
6911 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
6912 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
6914 struct fw_vi_enable_cmd c;
6916 memset(&c, 0, sizeof(c));
6917 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6918 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6919 FW_VI_ENABLE_CMD_VIID_V(viid));
6920 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
6921 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
6922 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
6924 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
6928 * t4_enable_vi - enable/disable a virtual interface
6929 * @adap: the adapter
6930 * @mbox: mailbox to use for the FW command
6932 * @rx_en: 1=enable Rx, 0=disable Rx
6933 * @tx_en: 1=enable Tx, 0=disable Tx
6935 * Enables/disables a virtual interface.
6937 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
6938 bool rx_en, bool tx_en)
6940 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
6944 * t4_identify_port - identify a VI's port by blinking its LED
6945 * @adap: the adapter
6946 * @mbox: mailbox to use for the FW command
6948 * @nblinks: how many times to blink LED at 2.5 Hz
6950 * Identifies a VI's port by blinking its LED.
6952 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
6953 unsigned int nblinks)
6955 struct fw_vi_enable_cmd c;
6957 memset(&c, 0, sizeof(c));
6958 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
6959 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
6960 FW_VI_ENABLE_CMD_VIID_V(viid));
6961 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
6962 c.blinkdur = cpu_to_be16(nblinks);
6963 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6967 * t4_iq_stop - stop an ingress queue and its FLs
6968 * @adap: the adapter
6969 * @mbox: mailbox to use for the FW command
6970 * @pf: the PF owning the queues
6971 * @vf: the VF owning the queues
6972 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
6973 * @iqid: ingress queue id
6974 * @fl0id: FL0 queue id or 0xffff if no attached FL0
6975 * @fl1id: FL1 queue id or 0xffff if no attached FL1
6977 * Stops an ingress queue and its associated FLs, if any. This causes
6978 * any current or future data/messages destined for these queues to be
6981 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
6982 unsigned int vf, unsigned int iqtype, unsigned int iqid,
6983 unsigned int fl0id, unsigned int fl1id)
6987 memset(&c, 0, sizeof(c));
6988 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
6989 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
6990 FW_IQ_CMD_VFN_V(vf));
6991 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
6992 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
6993 c.iqid = cpu_to_be16(iqid);
6994 c.fl0id = cpu_to_be16(fl0id);
6995 c.fl1id = cpu_to_be16(fl1id);
6996 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7000 * t4_iq_free - free an ingress queue and its FLs
7001 * @adap: the adapter
7002 * @mbox: mailbox to use for the FW command
7003 * @pf: the PF owning the queues
7004 * @vf: the VF owning the queues
7005 * @iqtype: the ingress queue type
7006 * @iqid: ingress queue id
7007 * @fl0id: FL0 queue id or 0xffff if no attached FL0
7008 * @fl1id: FL1 queue id or 0xffff if no attached FL1
7010 * Frees an ingress queue and its associated FLs, if any.
7012 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7013 unsigned int vf, unsigned int iqtype, unsigned int iqid,
7014 unsigned int fl0id, unsigned int fl1id)
7018 memset(&c, 0, sizeof(c));
7019 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
7020 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
7021 FW_IQ_CMD_VFN_V(vf));
7022 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
7023 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
7024 c.iqid = cpu_to_be16(iqid);
7025 c.fl0id = cpu_to_be16(fl0id);
7026 c.fl1id = cpu_to_be16(fl1id);
7027 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7031 * t4_eth_eq_free - free an Ethernet egress queue
7032 * @adap: the adapter
7033 * @mbox: mailbox to use for the FW command
7034 * @pf: the PF owning the queue
7035 * @vf: the VF owning the queue
7036 * @eqid: egress queue id
7038 * Frees an Ethernet egress queue.
7040 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7041 unsigned int vf, unsigned int eqid)
7043 struct fw_eq_eth_cmd c;
7045 memset(&c, 0, sizeof(c));
7046 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
7047 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7048 FW_EQ_ETH_CMD_PFN_V(pf) |
7049 FW_EQ_ETH_CMD_VFN_V(vf));
7050 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
7051 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
7052 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7056 * t4_ctrl_eq_free - free a control egress queue
7057 * @adap: the adapter
7058 * @mbox: mailbox to use for the FW command
7059 * @pf: the PF owning the queue
7060 * @vf: the VF owning the queue
7061 * @eqid: egress queue id
7063 * Frees a control egress queue.
7065 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7066 unsigned int vf, unsigned int eqid)
7068 struct fw_eq_ctrl_cmd c;
7070 memset(&c, 0, sizeof(c));
7071 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
7072 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7073 FW_EQ_CTRL_CMD_PFN_V(pf) |
7074 FW_EQ_CTRL_CMD_VFN_V(vf));
7075 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
7076 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
7077 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7081 * t4_ofld_eq_free - free an offload egress queue
7082 * @adap: the adapter
7083 * @mbox: mailbox to use for the FW command
7084 * @pf: the PF owning the queue
7085 * @vf: the VF owning the queue
7086 * @eqid: egress queue id
7088 * Frees a control egress queue.
7090 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
7091 unsigned int vf, unsigned int eqid)
7093 struct fw_eq_ofld_cmd c;
7095 memset(&c, 0, sizeof(c));
7096 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
7097 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
7098 FW_EQ_OFLD_CMD_PFN_V(pf) |
7099 FW_EQ_OFLD_CMD_VFN_V(vf));
7100 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
7101 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
7102 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7106 * t4_handle_fw_rpl - process a FW reply message
7107 * @adap: the adapter
7108 * @rpl: start of the FW message
7110 * Processes a FW message, such as link state change messages.
7112 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
7114 u8 opcode = *(const u8 *)rpl;
7116 if (opcode == FW_PORT_CMD) { /* link/module state change message */
7117 int speed = 0, fc = 0;
7118 const struct fw_port_cmd *p = (void *)rpl;
7119 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
7120 int port = adap->chan_map[chan];
7121 struct port_info *pi = adap2pinfo(adap, port);
7122 struct link_config *lc = &pi->link_cfg;
7123 u32 stat = be32_to_cpu(p->u.info.lstatus_to_modtype);
7124 int link_ok = (stat & FW_PORT_CMD_LSTATUS_F) != 0;
7125 u32 mod = FW_PORT_CMD_MODTYPE_G(stat);
7127 if (stat & FW_PORT_CMD_RXPAUSE_F)
7129 if (stat & FW_PORT_CMD_TXPAUSE_F)
7131 if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
7133 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
7135 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
7137 else if (stat & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
7140 if (link_ok != lc->link_ok || speed != lc->speed ||
7141 fc != lc->fc) { /* something changed */
7142 lc->link_ok = link_ok;
7145 lc->supported = be16_to_cpu(p->u.info.pcap);
7146 t4_os_link_changed(adap, port, link_ok);
7148 if (mod != pi->mod_type) {
7150 t4_os_portmod_changed(adap, port);
7156 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
7160 if (pci_is_pcie(adapter->pdev)) {
7161 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
7162 p->speed = val & PCI_EXP_LNKSTA_CLS;
7163 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
7168 * init_link_config - initialize a link's SW state
7169 * @lc: structure holding the link state
7170 * @caps: link capabilities
7172 * Initializes the SW state maintained for each link, including the link's
7173 * capabilities and default speed/flow-control/autonegotiation settings.
7175 static void init_link_config(struct link_config *lc, unsigned int caps)
7177 lc->supported = caps;
7178 lc->requested_speed = 0;
7180 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
7181 if (lc->supported & FW_PORT_CAP_ANEG) {
7182 lc->advertising = lc->supported & ADVERT_MASK;
7183 lc->autoneg = AUTONEG_ENABLE;
7184 lc->requested_fc |= PAUSE_AUTONEG;
7186 lc->advertising = 0;
7187 lc->autoneg = AUTONEG_DISABLE;
7191 #define CIM_PF_NOACCESS 0xeeeeeeee
7193 int t4_wait_dev_ready(void __iomem *regs)
7197 whoami = readl(regs + PL_WHOAMI_A);
7198 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
7202 whoami = readl(regs + PL_WHOAMI_A);
7203 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
7207 u32 vendor_and_model_id;
7211 static int get_flash_params(struct adapter *adap)
7213 /* Table for non-Numonix supported flash parts. Numonix parts are left
7214 * to the preexisting code. All flash parts have 64KB sectors.
7216 static struct flash_desc supported_flash[] = {
7217 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
7223 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
7225 ret = sf1_read(adap, 3, 0, 1, &info);
7226 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
7230 for (ret = 0; ret < ARRAY_SIZE(supported_flash); ++ret)
7231 if (supported_flash[ret].vendor_and_model_id == info) {
7232 adap->params.sf_size = supported_flash[ret].size_mb;
7233 adap->params.sf_nsec =
7234 adap->params.sf_size / SF_SEC_SIZE;
7238 if ((info & 0xff) != 0x20) /* not a Numonix flash */
7240 info >>= 16; /* log2 of size */
7241 if (info >= 0x14 && info < 0x18)
7242 adap->params.sf_nsec = 1 << (info - 16);
7243 else if (info == 0x18)
7244 adap->params.sf_nsec = 64;
7247 adap->params.sf_size = 1 << info;
7248 adap->params.sf_fw_start =
7249 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M;
7251 if (adap->params.sf_size < FLASH_MIN_SIZE)
7252 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n",
7253 adap->params.sf_size, FLASH_MIN_SIZE);
7257 static void set_pcie_completion_timeout(struct adapter *adapter, u8 range)
7262 pcie_cap = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
7264 pci_read_config_word(adapter->pdev,
7265 pcie_cap + PCI_EXP_DEVCTL2, &val);
7266 val &= ~PCI_EXP_DEVCTL2_COMP_TIMEOUT;
7268 pci_write_config_word(adapter->pdev,
7269 pcie_cap + PCI_EXP_DEVCTL2, val);
7274 * t4_prep_adapter - prepare SW and HW for operation
7275 * @adapter: the adapter
7276 * @reset: if true perform a HW reset
7278 * Initialize adapter SW state for the various HW modules, set initial
7279 * values for some adapter tunables, take PHYs out of reset, and
7280 * initialize the MDIO interface.
7282 int t4_prep_adapter(struct adapter *adapter)
7288 get_pci_mode(adapter, &adapter->params.pci);
7289 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
7291 ret = get_flash_params(adapter);
7293 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
7297 /* Retrieve adapter's device ID
7299 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
7300 ver = device_id >> 12;
7301 adapter->params.chip = 0;
7304 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
7305 adapter->params.arch.sge_fl_db = DBPRIO_F;
7306 adapter->params.arch.mps_tcam_size =
7307 NUM_MPS_CLS_SRAM_L_INSTANCES;
7308 adapter->params.arch.mps_rplc_size = 128;
7309 adapter->params.arch.nchan = NCHAN;
7310 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7311 adapter->params.arch.vfcount = 128;
7312 /* Congestion map is for 4 channels so that
7313 * MPS can have 4 priority per port.
7315 adapter->params.arch.cng_ch_bits_log = 2;
7318 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
7319 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
7320 adapter->params.arch.mps_tcam_size =
7321 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7322 adapter->params.arch.mps_rplc_size = 128;
7323 adapter->params.arch.nchan = NCHAN;
7324 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
7325 adapter->params.arch.vfcount = 128;
7326 adapter->params.arch.cng_ch_bits_log = 2;
7329 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
7330 adapter->params.arch.sge_fl_db = 0;
7331 adapter->params.arch.mps_tcam_size =
7332 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
7333 adapter->params.arch.mps_rplc_size = 256;
7334 adapter->params.arch.nchan = 2;
7335 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
7336 adapter->params.arch.vfcount = 256;
7337 /* Congestion map will be for 2 channels so that
7338 * MPS can have 8 priority per port.
7340 adapter->params.arch.cng_ch_bits_log = 3;
7343 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
7348 adapter->params.cim_la_size = CIMLA_SIZE;
7349 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
7352 * Default port for debugging in case we can't reach FW.
7354 adapter->params.nports = 1;
7355 adapter->params.portvec = 1;
7356 adapter->params.vpd.cclk = 50000;
7358 /* Set pci completion timeout value to 4 seconds. */
7359 set_pcie_completion_timeout(adapter, 0xd);
7364 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
7365 * @adapter: the adapter
7366 * @qid: the Queue ID
7367 * @qtype: the Ingress or Egress type for @qid
7368 * @user: true if this request is for a user mode queue
7369 * @pbar2_qoffset: BAR2 Queue Offset
7370 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
7372 * Returns the BAR2 SGE Queue Registers information associated with the
7373 * indicated Absolute Queue ID. These are passed back in return value
7374 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
7375 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
7377 * This may return an error which indicates that BAR2 SGE Queue
7378 * registers aren't available. If an error is not returned, then the
7379 * following values are returned:
7381 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
7382 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
7384 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
7385 * require the "Inferred Queue ID" ability may be used. E.g. the
7386 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
7387 * then these "Inferred Queue ID" register may not be used.
7389 int t4_bar2_sge_qregs(struct adapter *adapter,
7391 enum t4_bar2_qtype qtype,
7394 unsigned int *pbar2_qid)
7396 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
7397 u64 bar2_page_offset, bar2_qoffset;
7398 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
7400 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
7401 if (!user && is_t4(adapter->params.chip))
7404 /* Get our SGE Page Size parameters.
7406 page_shift = adapter->params.sge.hps + 10;
7407 page_size = 1 << page_shift;
7409 /* Get the right Queues per Page parameters for our Queue.
7411 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
7412 ? adapter->params.sge.eq_qpp
7413 : adapter->params.sge.iq_qpp);
7414 qpp_mask = (1 << qpp_shift) - 1;
7416 /* Calculate the basics of the BAR2 SGE Queue register area:
7417 * o The BAR2 page the Queue registers will be in.
7418 * o The BAR2 Queue ID.
7419 * o The BAR2 Queue ID Offset into the BAR2 page.
7421 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
7422 bar2_qid = qid & qpp_mask;
7423 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
7425 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
7426 * hardware will infer the Absolute Queue ID simply from the writes to
7427 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
7428 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
7429 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
7430 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
7431 * from the BAR2 Page and BAR2 Queue ID.
7433 * One important censequence of this is that some BAR2 SGE registers
7434 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
7435 * there. But other registers synthesize the SGE Queue ID purely
7436 * from the writes to the registers -- the Write Combined Doorbell
7437 * Buffer is a good example. These BAR2 SGE Registers are only
7438 * available for those BAR2 SGE Register areas where the SGE Absolute
7439 * Queue ID can be inferred from simple writes.
7441 bar2_qoffset = bar2_page_offset;
7442 bar2_qinferred = (bar2_qid_offset < page_size);
7443 if (bar2_qinferred) {
7444 bar2_qoffset += bar2_qid_offset;
7448 *pbar2_qoffset = bar2_qoffset;
7449 *pbar2_qid = bar2_qid;
7454 * t4_init_devlog_params - initialize adapter->params.devlog
7455 * @adap: the adapter
7457 * Initialize various fields of the adapter's Firmware Device Log
7458 * Parameters structure.
7460 int t4_init_devlog_params(struct adapter *adap)
7462 struct devlog_params *dparams = &adap->params.devlog;
7464 unsigned int devlog_meminfo;
7465 struct fw_devlog_cmd devlog_cmd;
7468 /* If we're dealing with newer firmware, the Device Log Paramerters
7469 * are stored in a designated register which allows us to access the
7470 * Device Log even if we can't talk to the firmware.
7473 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
7475 unsigned int nentries, nentries128;
7477 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
7478 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
7480 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
7481 nentries = (nentries128 + 1) * 128;
7482 dparams->size = nentries * sizeof(struct fw_devlog_e);
7487 /* Otherwise, ask the firmware for it's Device Log Parameters.
7489 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
7490 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
7491 FW_CMD_REQUEST_F | FW_CMD_READ_F);
7492 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
7493 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
7499 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
7500 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
7501 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
7502 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
7508 * t4_init_sge_params - initialize adap->params.sge
7509 * @adapter: the adapter
7511 * Initialize various fields of the adapter's SGE Parameters structure.
7513 int t4_init_sge_params(struct adapter *adapter)
7515 struct sge_params *sge_params = &adapter->params.sge;
7517 unsigned int s_hps, s_qpp;
7519 /* Extract the SGE Page Size for our PF.
7521 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
7522 s_hps = (HOSTPAGESIZEPF0_S +
7523 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
7524 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
7526 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
7528 s_qpp = (QUEUESPERPAGEPF0_S +
7529 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
7530 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
7531 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7532 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
7533 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
7539 * t4_init_tp_params - initialize adap->params.tp
7540 * @adap: the adapter
7542 * Initialize various fields of the adapter's TP Parameters structure.
7544 int t4_init_tp_params(struct adapter *adap)
7549 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
7550 adap->params.tp.tre = TIMERRESOLUTION_G(v);
7551 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
7553 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
7554 for (chan = 0; chan < NCHAN; chan++)
7555 adap->params.tp.tx_modq[chan] = chan;
7557 /* Cache the adapter's Compressed Filter Mode and global Incress
7560 if (t4_use_ldst(adap)) {
7561 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1,
7562 TP_VLAN_PRI_MAP_A, 1);
7563 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1,
7564 TP_INGRESS_CONFIG_A, 1);
7566 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7567 &adap->params.tp.vlan_pri_map, 1,
7569 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
7570 &adap->params.tp.ingress_config, 1,
7571 TP_INGRESS_CONFIG_A);
7574 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
7575 * shift positions of several elements of the Compressed Filter Tuple
7576 * for this adapter which we need frequently ...
7578 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
7579 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
7580 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
7581 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
7584 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
7585 * represents the presence of an Outer VLAN instead of a VNIC ID.
7587 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
7588 adap->params.tp.vnic_shift = -1;
7594 * t4_filter_field_shift - calculate filter field shift
7595 * @adap: the adapter
7596 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
7598 * Return the shift position of a filter field within the Compressed
7599 * Filter Tuple. The filter field is specified via its selection bit
7600 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
7602 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
7604 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
7608 if ((filter_mode & filter_sel) == 0)
7611 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
7612 switch (filter_mode & sel) {
7614 field_shift += FT_FCOE_W;
7617 field_shift += FT_PORT_W;
7620 field_shift += FT_VNIC_ID_W;
7623 field_shift += FT_VLAN_W;
7626 field_shift += FT_TOS_W;
7629 field_shift += FT_PROTOCOL_W;
7632 field_shift += FT_ETHERTYPE_W;
7635 field_shift += FT_MACMATCH_W;
7638 field_shift += FT_MPSHITTYPE_W;
7640 case FRAGMENTATION_F:
7641 field_shift += FT_FRAGMENTATION_W;
7648 int t4_init_rss_mode(struct adapter *adap, int mbox)
7651 struct fw_rss_vi_config_cmd rvc;
7653 memset(&rvc, 0, sizeof(rvc));
7655 for_each_port(adap, i) {
7656 struct port_info *p = adap2pinfo(adap, i);
7659 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
7660 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7661 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
7662 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
7663 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
7666 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
7672 * t4_init_portinfo - allocate a virtual interface amd initialize port_info
7673 * @pi: the port_info
7674 * @mbox: mailbox to use for the FW command
7675 * @port: physical port associated with the VI
7676 * @pf: the PF owning the VI
7677 * @vf: the VF owning the VI
7678 * @mac: the MAC address of the VI
7680 * Allocates a virtual interface for the given physical port. If @mac is
7681 * not %NULL it contains the MAC address of the VI as assigned by FW.
7682 * @mac should be large enough to hold an Ethernet address.
7683 * Returns < 0 on error.
7685 int t4_init_portinfo(struct port_info *pi, int mbox,
7686 int port, int pf, int vf, u8 mac[])
7689 struct fw_port_cmd c;
7690 unsigned int rss_size;
7692 memset(&c, 0, sizeof(c));
7693 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
7694 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7695 FW_PORT_CMD_PORTID_V(port));
7696 c.action_to_len16 = cpu_to_be32(
7697 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO) |
7699 ret = t4_wr_mbox(pi->adapter, mbox, &c, sizeof(c), &c);
7703 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size);
7710 pi->rss_size = rss_size;
7712 ret = be32_to_cpu(c.u.info.lstatus_to_modtype);
7713 pi->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP_F) ?
7714 FW_PORT_CMD_MDIOADDR_G(ret) : -1;
7715 pi->port_type = FW_PORT_CMD_PTYPE_G(ret);
7716 pi->mod_type = FW_PORT_MOD_TYPE_NA;
7718 init_link_config(&pi->link_cfg, be16_to_cpu(c.u.info.pcap));
7722 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
7727 for_each_port(adap, i) {
7728 struct port_info *pi = adap2pinfo(adap, i);
7730 while ((adap->params.portvec & (1 << j)) == 0)
7733 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
7737 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
7738 adap->port[i]->dev_port = j;
7745 * t4_read_cimq_cfg - read CIM queue configuration
7746 * @adap: the adapter
7747 * @base: holds the queue base addresses in bytes
7748 * @size: holds the queue sizes in bytes
7749 * @thres: holds the queue full thresholds in bytes
7751 * Returns the current configuration of the CIM queues, starting with
7752 * the IBQs, then the OBQs.
7754 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
7757 int cim_num_obq = is_t4(adap->params.chip) ?
7758 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7760 for (i = 0; i < CIM_NUM_IBQ; i++) {
7761 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
7763 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7764 /* value is in 256-byte units */
7765 *base++ = CIMQBASE_G(v) * 256;
7766 *size++ = CIMQSIZE_G(v) * 256;
7767 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
7769 for (i = 0; i < cim_num_obq; i++) {
7770 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7772 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7773 /* value is in 256-byte units */
7774 *base++ = CIMQBASE_G(v) * 256;
7775 *size++ = CIMQSIZE_G(v) * 256;
7780 * t4_read_cim_ibq - read the contents of a CIM inbound queue
7781 * @adap: the adapter
7782 * @qid: the queue index
7783 * @data: where to store the queue contents
7784 * @n: capacity of @data in 32-bit words
7786 * Reads the contents of the selected CIM queue starting at address 0 up
7787 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7788 * error and the number of 32-bit words actually read on success.
7790 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7792 int i, err, attempts;
7794 const unsigned int nwords = CIM_IBQ_SIZE * 4;
7796 if (qid > 5 || (n & 3))
7799 addr = qid * nwords;
7803 /* It might take 3-10ms before the IBQ debug read access is allowed.
7804 * Wait for 1 Sec with a delay of 1 usec.
7808 for (i = 0; i < n; i++, addr++) {
7809 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
7811 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
7815 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
7817 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
7822 * t4_read_cim_obq - read the contents of a CIM outbound queue
7823 * @adap: the adapter
7824 * @qid: the queue index
7825 * @data: where to store the queue contents
7826 * @n: capacity of @data in 32-bit words
7828 * Reads the contents of the selected CIM queue starting at address 0 up
7829 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
7830 * error and the number of 32-bit words actually read on success.
7832 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
7835 unsigned int addr, v, nwords;
7836 int cim_num_obq = is_t4(adap->params.chip) ?
7837 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
7839 if ((qid > (cim_num_obq - 1)) || (n & 3))
7842 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
7843 QUENUMSELECT_V(qid));
7844 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
7846 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
7847 nwords = CIMQSIZE_G(v) * 64; /* same */
7851 for (i = 0; i < n; i++, addr++) {
7852 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
7854 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
7858 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
7860 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
7865 * t4_cim_read - read a block from CIM internal address space
7866 * @adap: the adapter
7867 * @addr: the start address within the CIM address space
7868 * @n: number of words to read
7869 * @valp: where to store the result
7871 * Reads a block of 4-byte words from the CIM intenal address space.
7873 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
7878 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7881 for ( ; !ret && n--; addr += 4) {
7882 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
7883 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7886 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
7892 * t4_cim_write - write a block into CIM internal address space
7893 * @adap: the adapter
7894 * @addr: the start address within the CIM address space
7895 * @n: number of words to write
7896 * @valp: set of values to write
7898 * Writes a block of 4-byte words into the CIM intenal address space.
7900 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
7901 const unsigned int *valp)
7905 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
7908 for ( ; !ret && n--; addr += 4) {
7909 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
7910 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
7911 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
7917 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
7920 return t4_cim_write(adap, addr, 1, &val);
7924 * t4_cim_read_la - read CIM LA capture buffer
7925 * @adap: the adapter
7926 * @la_buf: where to store the LA data
7927 * @wrptr: the HW write pointer within the capture buffer
7929 * Reads the contents of the CIM LA buffer with the most recent entry at
7930 * the end of the returned data and with the entry at @wrptr first.
7931 * We try to leave the LA in the running state we find it in.
7933 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
7936 unsigned int cfg, val, idx;
7938 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
7942 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
7943 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
7948 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7952 idx = UPDBGLAWRPTR_G(val);
7956 for (i = 0; i < adap->params.cim_la_size; i++) {
7957 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7958 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
7961 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
7964 if (val & UPDBGLARDEN_F) {
7968 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
7971 idx = (idx + 1) & UPDBGLARDPTR_M;
7974 if (cfg & UPDBGLAEN_F) {
7975 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
7976 cfg & ~UPDBGLARDEN_F);
7984 * t4_tp_read_la - read TP LA capture buffer
7985 * @adap: the adapter
7986 * @la_buf: where to store the LA data
7987 * @wrptr: the HW write pointer within the capture buffer
7989 * Reads the contents of the TP LA buffer with the most recent entry at
7990 * the end of the returned data and with the entry at @wrptr first.
7991 * We leave the LA in the running state we find it in.
7993 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
7995 bool last_incomplete;
7996 unsigned int i, cfg, val, idx;
7998 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
7999 if (cfg & DBGLAENABLE_F) /* freeze LA */
8000 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8001 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
8003 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
8004 idx = DBGLAWPTR_G(val);
8005 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
8006 if (last_incomplete)
8007 idx = (idx + 1) & DBGLARPTR_M;
8012 val &= ~DBGLARPTR_V(DBGLARPTR_M);
8013 val |= adap->params.tp.la_mask;
8015 for (i = 0; i < TPLA_SIZE; i++) {
8016 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
8017 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
8018 idx = (idx + 1) & DBGLARPTR_M;
8021 /* Wipe out last entry if it isn't valid */
8022 if (last_incomplete)
8023 la_buf[TPLA_SIZE - 1] = ~0ULL;
8025 if (cfg & DBGLAENABLE_F) /* restore running state */
8026 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
8027 cfg | adap->params.tp.la_mask);
8030 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
8031 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
8032 * state for more than the Warning Threshold then we'll issue a warning about
8033 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
8034 * appears to be hung every Warning Repeat second till the situation clears.
8035 * If the situation clears, we'll note that as well.
8037 #define SGE_IDMA_WARN_THRESH 1
8038 #define SGE_IDMA_WARN_REPEAT 300
8041 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
8042 * @adapter: the adapter
8043 * @idma: the adapter IDMA Monitor state
8045 * Initialize the state of an SGE Ingress DMA Monitor.
8047 void t4_idma_monitor_init(struct adapter *adapter,
8048 struct sge_idma_monitor_state *idma)
8050 /* Initialize the state variables for detecting an SGE Ingress DMA
8051 * hang. The SGE has internal counters which count up on each clock
8052 * tick whenever the SGE finds its Ingress DMA State Engines in the
8053 * same state they were on the previous clock tick. The clock used is
8054 * the Core Clock so we have a limit on the maximum "time" they can
8055 * record; typically a very small number of seconds. For instance,
8056 * with a 600MHz Core Clock, we can only count up to a bit more than
8057 * 7s. So we'll synthesize a larger counter in order to not run the
8058 * risk of having the "timers" overflow and give us the flexibility to
8059 * maintain a Hung SGE State Machine of our own which operates across
8060 * a longer time frame.
8062 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
8063 idma->idma_stalled[0] = 0;
8064 idma->idma_stalled[1] = 0;
8068 * t4_idma_monitor - monitor SGE Ingress DMA state
8069 * @adapter: the adapter
8070 * @idma: the adapter IDMA Monitor state
8071 * @hz: number of ticks/second
8072 * @ticks: number of ticks since the last IDMA Monitor call
8074 void t4_idma_monitor(struct adapter *adapter,
8075 struct sge_idma_monitor_state *idma,
8078 int i, idma_same_state_cnt[2];
8080 /* Read the SGE Debug Ingress DMA Same State Count registers. These
8081 * are counters inside the SGE which count up on each clock when the
8082 * SGE finds its Ingress DMA State Engines in the same states they
8083 * were in the previous clock. The counters will peg out at
8084 * 0xffffffff without wrapping around so once they pass the 1s
8085 * threshold they'll stay above that till the IDMA state changes.
8087 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
8088 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
8089 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8091 for (i = 0; i < 2; i++) {
8092 u32 debug0, debug11;
8094 /* If the Ingress DMA Same State Counter ("timer") is less
8095 * than 1s, then we can reset our synthesized Stall Timer and
8096 * continue. If we have previously emitted warnings about a
8097 * potential stalled Ingress Queue, issue a note indicating
8098 * that the Ingress Queue has resumed forward progress.
8100 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
8101 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
8102 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
8103 "resumed after %d seconds\n",
8104 i, idma->idma_qid[i],
8105 idma->idma_stalled[i] / hz);
8106 idma->idma_stalled[i] = 0;
8110 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
8111 * domain. The first time we get here it'll be because we
8112 * passed the 1s Threshold; each additional time it'll be
8113 * because the RX Timer Callback is being fired on its regular
8116 * If the stall is below our Potential Hung Ingress Queue
8117 * Warning Threshold, continue.
8119 if (idma->idma_stalled[i] == 0) {
8120 idma->idma_stalled[i] = hz;
8121 idma->idma_warn[i] = 0;
8123 idma->idma_stalled[i] += ticks;
8124 idma->idma_warn[i] -= ticks;
8127 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
8130 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
8132 if (idma->idma_warn[i] > 0)
8134 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
8136 /* Read and save the SGE IDMA State and Queue ID information.
8137 * We do this every time in case it changes across time ...
8138 * can't be too careful ...
8140 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
8141 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8142 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
8144 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
8145 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
8146 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
8148 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
8149 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
8150 i, idma->idma_qid[i], idma->idma_state[i],
8151 idma->idma_stalled[i] / hz,
8153 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);